Line data Source code
1 : /* Optimize by combining instructions for GNU compiler.
2 : Copyright (C) 1987-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it under
7 : the terms of the GNU General Public License as published by the Free
8 : Software Foundation; either version 3, or (at your option) any later
9 : version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : /* This module is essentially the "combiner" phase of the U. of Arizona
21 : Portable Optimizer, but redone to work on our list-structured
22 : representation for RTL instead of their string representation.
23 :
24 : The LOG_LINKS of each insn identify the most recent assignment
25 : to each REG used in the insn. It is a list of previous insns,
26 : each of which contains a SET for a REG that is used in this insn
27 : and not used or set in between. LOG_LINKs never cross basic blocks.
28 : They were set up by the preceding pass (lifetime analysis).
29 :
30 : We try to combine each pair of insns joined by a logical link.
31 : We also try to combine triplets of insns A, B and C when C has
32 : a link back to B and B has a link back to A. Likewise for a
33 : small number of quadruplets of insns A, B, C and D for which
34 : there's high likelihood of success.
35 :
36 : We check (with modified_between_p) to avoid combining in such a way
37 : as to move a computation to a place where its value would be different.
38 :
39 : Combination is done by mathematically substituting the previous
40 : insn(s) values for the regs they set into the expressions in
41 : the later insns that refer to these regs. If the result is a valid insn
42 : for our target machine, according to the machine description,
43 : we install it, delete the earlier insns, and update the data flow
44 : information (LOG_LINKS and REG_NOTES) for what we did.
45 :
46 : There are a few exceptions where the dataflow information isn't
47 : completely updated (however this is only a local issue since it is
48 : regenerated before the next pass that uses it):
49 :
50 : - reg_live_length is not updated
51 : - reg_n_refs is not adjusted in the rare case when a register is
52 : no longer required in a computation
53 : - there are extremely rare cases (see distribute_notes) when a
54 : REG_DEAD note is lost
55 : - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 : removed because there is no way to know which register it was
57 : linking
58 :
59 : To simplify substitution, we combine only when the earlier insn(s)
60 : consist of only a single assignment. To simplify updating afterward,
61 : we never combine when a subroutine call appears in the middle. */
62 :
63 : #include "config.h"
64 : #include "system.h"
65 : #include "coretypes.h"
66 : #include "backend.h"
67 : #include "target.h"
68 : #include "rtl.h"
69 : #include "tree.h"
70 : #include "cfghooks.h"
71 : #include "predict.h"
72 : #include "df.h"
73 : #include "memmodel.h"
74 : #include "tm_p.h"
75 : #include "optabs.h"
76 : #include "regs.h"
77 : #include "emit-rtl.h"
78 : #include "recog.h"
79 : #include "cgraph.h"
80 : #include "stor-layout.h"
81 : #include "cfgrtl.h"
82 : #include "cfgcleanup.h"
83 : /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84 : #include "explow.h"
85 : #include "insn-attr.h"
86 : #include "rtlhooks-def.h"
87 : #include "expr.h"
88 : #include "tree-pass.h"
89 : #include "valtrack.h"
90 : #include "rtl-iter.h"
91 : #include "print-rtl.h"
92 : #include "function-abi.h"
93 : #include "rtlanal.h"
94 :
95 : /* Number of attempts to combine instructions in this function. */
96 :
97 : static int combine_attempts;
98 :
99 : /* Number of attempts that got as far as substitution in this function. */
100 :
101 : static int combine_merges;
102 :
103 : /* Number of instructions combined with added SETs in this function. */
104 :
105 : static int combine_extras;
106 :
107 : /* Number of instructions combined in this function. */
108 :
109 : static int combine_successes;
110 :
111 : /* combine_instructions may try to replace the right hand side of the
112 : second instruction with the value of an associated REG_EQUAL note
113 : before throwing it at try_combine. That is problematic when there
114 : is a REG_DEAD note for a register used in the old right hand side
115 : and can cause distribute_notes to do wrong things. This is the
116 : second instruction if it has been so modified, null otherwise. */
117 :
118 : static rtx_insn *i2mod;
119 :
120 : /* When I2MOD is nonnull, this is a copy of the old right hand side. */
121 :
122 : static rtx i2mod_old_rhs;
123 :
124 : /* When I2MOD is nonnull, this is a copy of the new right hand side. */
125 :
126 : static rtx i2mod_new_rhs;
127 :
128 : struct reg_stat_type {
129 : /* Record last point of death of (hard or pseudo) register n. */
130 : rtx_insn *last_death;
131 :
132 : /* Record last point of modification of (hard or pseudo) register n. */
133 : rtx_insn *last_set;
134 :
135 : /* The next group of fields allows the recording of the last value assigned
136 : to (hard or pseudo) register n. We use this information to see if an
137 : operation being processed is redundant given a prior operation performed
138 : on the register. For example, an `and' with a constant is redundant if
139 : all the zero bits are already known to be turned off.
140 :
141 : We use an approach similar to that used by cse, but change it in the
142 : following ways:
143 :
144 : (1) We do not want to reinitialize at each label.
145 : (2) It is useful, but not critical, to know the actual value assigned
146 : to a register. Often just its form is helpful.
147 :
148 : Therefore, we maintain the following fields:
149 :
150 : last_set_value the last value assigned
151 : last_set_label records the value of label_tick when the
152 : register was assigned
153 : last_set_table_tick records the value of label_tick when a
154 : value using the register is assigned
155 : last_set_invalid set to true when it is not valid
156 : to use the value of this register in some
157 : register's value
158 :
159 : To understand the usage of these tables, it is important to understand
160 : the distinction between the value in last_set_value being valid and
161 : the register being validly contained in some other expression in the
162 : table.
163 :
164 : (The next two parameters are out of date).
165 :
166 : reg_stat[i].last_set_value is valid if it is nonzero, and either
167 : reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168 :
169 : Register I may validly appear in any expression returned for the value
170 : of another register if reg_n_sets[i] is 1. It may also appear in the
171 : value for register J if reg_stat[j].last_set_invalid is zero, or
172 : reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173 :
174 : If an expression is found in the table containing a register which may
175 : not validly appear in an expression, the register is replaced by
176 : something that won't match, (clobber (const_int 0)). */
177 :
178 : /* Record last value assigned to (hard or pseudo) register n. */
179 :
180 : rtx last_set_value;
181 :
182 : /* Record the value of label_tick when an expression involving register n
183 : is placed in last_set_value. */
184 :
185 : int last_set_table_tick;
186 :
187 : /* Record the value of label_tick when the value for register n is placed in
188 : last_set_value. */
189 :
190 : int last_set_label;
191 :
192 : /* These fields are maintained in parallel with last_set_value and are
193 : used to store the mode in which the register was last set, the bits
194 : that were known to be zero when it was last set, and the number of
195 : sign bits copies it was known to have when it was last set. */
196 :
197 : unsigned HOST_WIDE_INT last_set_nonzero_bits;
198 : unsigned short last_set_sign_bit_copies;
199 : machine_mode last_set_mode : MACHINE_MODE_BITSIZE;
200 :
201 : /* Set to true if references to register n in expressions should not be
202 : used. last_set_invalid is set nonzero when this register is being
203 : assigned to and last_set_table_tick == label_tick. */
204 :
205 : bool last_set_invalid;
206 :
207 : /* Some registers that are set more than once and used in more than one
208 : basic block are nevertheless always set in similar ways. For example,
209 : a QImode register may be loaded from memory in two places on a machine
210 : where byte loads zero extend.
211 :
212 : We record in the following fields if a register has some leading bits
213 : that are always equal to the sign bit, and what we know about the
214 : nonzero bits of a register, specifically which bits are known to be
215 : zero.
216 :
217 : If an entry is zero, it means that we don't know anything special. */
218 :
219 : unsigned short sign_bit_copies;
220 :
221 : unsigned HOST_WIDE_INT nonzero_bits;
222 :
223 : /* Record the value of the label_tick when the last truncation
224 : happened. The field truncated_to_mode is only valid if
225 : truncation_label == label_tick. */
226 :
227 : int truncation_label;
228 :
229 : /* Record the last truncation seen for this register. If truncation
230 : is not a nop to this mode we might be able to save an explicit
231 : truncation if we know that value already contains a truncated
232 : value. */
233 :
234 : machine_mode truncated_to_mode : MACHINE_MODE_BITSIZE;
235 : };
236 :
237 :
238 : static vec<reg_stat_type> reg_stat;
239 :
240 : /* One plus the highest pseudo for which we track REG_N_SETS.
241 : regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 : but during combine_split_insns new pseudos can be created. As we don't have
243 : updated DF information in that case, it is hard to initialize the array
244 : after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 : so instead of growing the arrays, just assume all newly created pseudos
246 : during combine might be set multiple times. */
247 :
248 : static unsigned int reg_n_sets_max;
249 :
250 : /* Record the luid of the last insn that invalidated memory
251 : (anything that writes memory, and subroutine calls, but not pushes). */
252 :
253 : static int mem_last_set;
254 :
255 : /* Record the luid of the last CALL_INSN
256 : so we can tell whether a potential combination crosses any calls. */
257 :
258 : static int last_call_luid;
259 :
260 : /* When `subst' is called, this is the insn that is being modified
261 : (by combining in a previous insn). The PATTERN of this insn
262 : is still the old pattern partially modified and it should not be
263 : looked at, but this may be used to examine the successors of the insn
264 : to judge whether a simplification is valid. */
265 :
266 : static rtx_insn *subst_insn;
267 :
268 : /* This is the lowest LUID that `subst' is currently dealing with.
269 : get_last_value will not return a value if the register was set at or
270 : after this LUID. If not for this mechanism, we could get confused if
271 : I2 or I1 in try_combine were an insn that used the old value of a register
272 : to obtain a new value. In that case, we might erroneously get the
273 : new value of the register when we wanted the old one. */
274 :
275 : static int subst_low_luid;
276 :
277 : /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 : must consider all these registers to be always live. */
279 :
280 : static HARD_REG_SET newpat_used_regs;
281 :
282 : /* This is an insn to which a LOG_LINKS entry has been added. If this
283 : insn is the earlier than I2 or I3, combine should rescan starting at
284 : that location. */
285 :
286 : static rtx_insn *added_links_insn;
287 :
288 : /* And similarly, for notes. */
289 :
290 : static rtx_insn *added_notes_insn;
291 :
292 : /* Basic block in which we are performing combines. */
293 : static basic_block this_basic_block;
294 : static bool optimize_this_for_speed_p;
295 :
296 :
297 : /* Length of the currently allocated uid_insn_cost array. */
298 :
299 : static int max_uid_known;
300 :
301 : /* The following array records the insn_cost for every insn
302 : in the instruction stream. */
303 :
304 : static int *uid_insn_cost;
305 :
306 : /* The following array records the LOG_LINKS for every insn in the
307 : instruction stream as struct insn_link pointers. */
308 :
309 : struct insn_link {
310 : rtx_insn *insn;
311 : unsigned int regno;
312 : int insn_count;
313 : struct insn_link *next;
314 : };
315 :
316 : static struct insn_link **uid_log_links;
317 :
318 : static inline int
319 775306247 : insn_uid_check (const_rtx insn)
320 : {
321 775306247 : int uid = INSN_UID (insn);
322 775306247 : gcc_checking_assert (uid <= max_uid_known);
323 775306247 : return uid;
324 : }
325 :
326 : #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
327 : #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 :
329 : #define FOR_EACH_LOG_LINK(L, INSN) \
330 : for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 :
332 : /* Links for LOG_LINKS are allocated from this obstack. */
333 :
334 : static struct obstack insn_link_obstack;
335 :
336 : /* Allocate a link. */
337 :
338 : static inline struct insn_link *
339 38883564 : alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
340 : {
341 38883564 : struct insn_link *l
342 38883564 : = (struct insn_link *) obstack_alloc (&insn_link_obstack,
343 : sizeof (struct insn_link));
344 38883564 : l->insn = insn;
345 38883564 : l->regno = regno;
346 38883564 : l->insn_count = 0;
347 38883564 : l->next = next;
348 38883564 : return l;
349 : }
350 :
351 : /* Incremented for each basic block. */
352 :
353 : static int label_tick;
354 :
355 : /* Reset to label_tick for each extended basic block in scanning order. */
356 :
357 : static int label_tick_ebb_start;
358 :
359 : /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
360 : largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
361 :
362 : static scalar_int_mode nonzero_bits_mode;
363 :
364 : /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
365 : be safely used. It is zero while computing them and after combine has
366 : completed. This former test prevents propagating values based on
367 : previously set values, which can be incorrect if a variable is modified
368 : in a loop. */
369 :
370 : static int nonzero_sign_valid;
371 :
372 :
373 : /* Record one modification to rtl structure
374 : to be undone by storing old_contents into *where. */
375 :
376 : enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
377 :
378 : struct undo
379 : {
380 : struct undo *next;
381 : enum undo_kind kind;
382 : union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
383 : union { rtx *r; int *i; int regno; struct insn_link **l; } where;
384 : };
385 :
386 : /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
387 : num_undo says how many are currently recorded.
388 :
389 : other_insn is nonzero if we have modified some other insn in the process
390 : of working on subst_insn. It must be verified too. */
391 :
392 : struct undobuf
393 : {
394 : struct undo *undos;
395 : struct undo *frees;
396 : rtx_insn *other_insn;
397 : };
398 :
399 : static struct undobuf undobuf;
400 :
401 : /* Number of times the pseudo being substituted for
402 : was found and replaced. */
403 :
404 : static int n_occurrences;
405 :
406 : static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
407 : scalar_int_mode,
408 : unsigned HOST_WIDE_INT *);
409 : static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
410 : scalar_int_mode,
411 : unsigned int *);
412 : static void do_SUBST (rtx *, rtx);
413 : static void do_SUBST_INT (int *, int);
414 : static void init_reg_last (void);
415 : static void setup_incoming_promotions (rtx_insn *);
416 : static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
417 : static bool cant_combine_insn_p (rtx_insn *);
418 : static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
419 : rtx_insn *, rtx_insn *, rtx *, rtx *);
420 : static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
421 : bool, bool, rtx *);
422 : static bool contains_muldiv (rtx);
423 : static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
424 : bool *, rtx_insn *);
425 : static void undo_all (void);
426 : static void undo_commit (void);
427 : static rtx *find_split_point (rtx *, rtx_insn *, bool);
428 : static rtx subst (rtx, rtx, rtx, bool, bool, bool);
429 : static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
430 : static rtx simplify_if_then_else (rtx);
431 : static rtx simplify_set (rtx);
432 : static rtx simplify_logical (rtx);
433 : static rtx expand_compound_operation (rtx);
434 : static const_rtx expand_field_assignment (const_rtx);
435 : static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
436 : unsigned HOST_WIDE_INT, bool, bool, bool);
437 : static int get_pos_from_mask (unsigned HOST_WIDE_INT,
438 : unsigned HOST_WIDE_INT *);
439 : static rtx canon_reg_for_combine (rtx, rtx);
440 : static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
441 : scalar_int_mode, unsigned HOST_WIDE_INT, bool);
442 : static rtx force_to_mode (rtx, machine_mode,
443 : unsigned HOST_WIDE_INT, bool);
444 : static rtx if_then_else_cond (rtx, rtx *, rtx *);
445 : static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
446 : static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
447 : static rtx make_field_assignment (rtx);
448 : static rtx apply_distributive_law (rtx);
449 : static rtx distribute_and_simplify_rtx (rtx, int);
450 : static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
451 : unsigned HOST_WIDE_INT);
452 : static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
453 : unsigned HOST_WIDE_INT);
454 : static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
455 : HOST_WIDE_INT, machine_mode, bool *);
456 : static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
457 : static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
458 : int);
459 : static int recog_for_combine (rtx *, rtx_insn *, rtx *, unsigned = 0, unsigned = 0);
460 : static rtx gen_lowpart_for_combine (machine_mode, rtx);
461 : static rtx gen_lowpart_for_combine_no_emit (machine_mode, rtx);
462 : static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
463 : rtx *, rtx *);
464 : static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
465 : static void update_table_tick (rtx);
466 : static void record_value_for_reg (rtx, rtx_insn *, rtx);
467 : static void check_promoted_subreg (rtx_insn *, rtx);
468 : static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
469 : static void record_dead_and_set_regs (rtx_insn *);
470 : static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
471 : static rtx get_last_value (const_rtx);
472 : static void reg_dead_at_p_1 (rtx, const_rtx, void *);
473 : static bool reg_dead_at_p (rtx, rtx_insn *);
474 : static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
475 : static bool reg_bitfield_target_p (rtx, rtx);
476 : static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
477 : rtx, rtx, rtx);
478 : static void distribute_links (struct insn_link *, rtx_insn * = nullptr,
479 : int limit = INT_MAX);
480 : static void mark_used_regs_combine (rtx);
481 : static void record_promoted_value (rtx_insn *, rtx);
482 : static bool unmentioned_reg_p (rtx, rtx);
483 : static void record_truncated_values (rtx *, void *);
484 : static bool reg_truncated_to_mode (machine_mode, const_rtx);
485 : static rtx gen_lowpart_or_truncate (machine_mode, rtx);
486 :
487 :
488 : /* It is not safe to use ordinary gen_lowpart in combine.
489 : See comments in gen_lowpart_for_combine. */
490 : #undef RTL_HOOKS_GEN_LOWPART
491 : #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 :
493 : /* Our implementation of gen_lowpart never emits a new pseudo. */
494 : #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 : #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine_no_emit
496 :
497 : #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 : #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 :
500 : #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 : #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 :
503 : #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 : #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
505 :
506 : static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
507 :
508 :
509 : /* Convenience wrapper for the canonicalize_comparison target hook.
510 : Target hooks cannot use enum rtx_code. */
511 : static inline void
512 25164306 : target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
513 : bool op0_preserve_value)
514 : {
515 25164306 : int code_int = (int)*code;
516 25164306 : targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
517 25164306 : *code = (enum rtx_code)code_int;
518 : }
519 :
520 : /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 : PATTERN cannot be split. Otherwise, it returns an insn sequence.
522 : Updates OLD_NREGS with the max number of regs before the split
523 : and NEW_NREGS after the split.
524 : This is a wrapper around split_insns which ensures that the
525 : reg_stat vector is made larger if the splitter creates a new
526 : register. */
527 :
528 : static rtx_insn *
529 12095036 : combine_split_insns (rtx pattern, rtx_insn *insn,
530 : unsigned int *old_nregs,
531 : unsigned int *new_regs)
532 : {
533 12095036 : rtx_insn *ret;
534 12095036 : unsigned int nregs;
535 12095036 : *old_nregs = max_reg_num ();
536 12095036 : ret = split_insns (pattern, insn);
537 12095036 : *new_regs = nregs = max_reg_num ();
538 24190072 : if (nregs > reg_stat.length ())
539 2251 : reg_stat.safe_grow_cleared (nregs, true);
540 12095036 : return ret;
541 : }
542 :
543 : /* This is used by find_single_use to locate an rtx in LOC that
544 : contains exactly one use of DEST, which is typically a REG.
545 : It returns a pointer to the innermost rtx expression
546 : containing DEST. Appearances of DEST that are being used to
547 : totally replace it are not counted. */
548 :
549 : static rtx *
550 33255206 : find_single_use_1 (rtx dest, rtx *loc)
551 : {
552 40255237 : rtx x = *loc;
553 40255237 : enum rtx_code code = GET_CODE (x);
554 40255237 : rtx *result = NULL;
555 40255237 : rtx *this_result;
556 40255237 : int i;
557 40255237 : const char *fmt;
558 :
559 40255237 : switch (code)
560 : {
561 : case CONST:
562 : case LABEL_REF:
563 : case SYMBOL_REF:
564 : CASE_CONST_ANY:
565 : case CLOBBER:
566 : return 0;
567 :
568 6955318 : case SET:
569 : /* If the destination is anything other than PC, a REG or a SUBREG
570 : of a REG that occupies all of the REG, the insn uses DEST if
571 : it is mentioned in the destination or the source. Otherwise, we
572 : need just check the source. */
573 6955318 : if (GET_CODE (SET_DEST (x)) != PC
574 6955318 : && !REG_P (SET_DEST (x))
575 6957462 : && ! (GET_CODE (SET_DEST (x)) == SUBREG
576 2144 : && REG_P (SUBREG_REG (SET_DEST (x)))
577 2144 : && !read_modify_subreg_p (SET_DEST (x))))
578 : break;
579 :
580 6953909 : return find_single_use_1 (dest, &SET_SRC (x));
581 :
582 46122 : case MEM:
583 46122 : case SUBREG:
584 46122 : return find_single_use_1 (dest, &XEXP (x, 0));
585 :
586 : default:
587 : break;
588 : }
589 :
590 : /* If it wasn't one of the common cases above, check each expression and
591 : vector of this code. Look for a unique usage of DEST. */
592 :
593 20031936 : fmt = GET_RTX_FORMAT (code);
594 53560202 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
595 : {
596 33535730 : if (fmt[i] == 'e')
597 : {
598 33156311 : if (dest == XEXP (x, i)
599 33156311 : || (REG_P (dest) && REG_P (XEXP (x, i))
600 864707 : && REGNO (dest) == REGNO (XEXP (x, i))))
601 : this_result = loc;
602 : else
603 26198203 : this_result = find_single_use_1 (dest, &XEXP (x, i));
604 :
605 33156311 : if (result == NULL)
606 : result = this_result;
607 40691 : else if (this_result)
608 : /* Duplicate usage. */
609 : return NULL;
610 : }
611 379419 : else if (fmt[i] == 'E')
612 : {
613 51305 : int j;
614 :
615 156225 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
616 : {
617 109017 : if (XVECEXP (x, i, j) == dest
618 109017 : || (REG_P (dest)
619 109017 : && REG_P (XVECEXP (x, i, j))
620 4627 : && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
621 : this_result = loc;
622 : else
623 109017 : this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
624 :
625 109017 : if (result == NULL)
626 : result = this_result;
627 17156 : else if (this_result)
628 : return NULL;
629 : }
630 : }
631 : }
632 :
633 : return result;
634 : }
635 :
636 :
637 : /* See if DEST, produced in INSN, is used only a single time in the
638 : sequel. If so, return a pointer to the innermost rtx expression in which
639 : it is used.
640 :
641 : If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 :
643 : Otherwise, we find the single use by finding an insn that has a
644 : LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
645 : only referenced once in that insn, we know that it must be the first
646 : and last insn referencing DEST. */
647 :
648 : static rtx *
649 7564409 : find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
650 : {
651 7564409 : basic_block bb;
652 7564409 : rtx_insn *next;
653 7564409 : rtx *result;
654 7564409 : struct insn_link *link;
655 :
656 7564409 : if (!REG_P (dest))
657 : return 0;
658 :
659 7564409 : bb = BLOCK_FOR_INSN (insn);
660 10419215 : for (next = NEXT_INSN (insn);
661 10419215 : next && BLOCK_FOR_INSN (next) == bb;
662 2854806 : next = NEXT_INSN (next))
663 9802792 : if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
664 : {
665 9251996 : FOR_EACH_LOG_LINK (link, next)
666 8230171 : if (link->insn == insn && link->regno == REGNO (dest))
667 : break;
668 :
669 7969811 : if (link)
670 : {
671 6947986 : result = find_single_use_1 (dest, &PATTERN (next));
672 6947986 : if (ploc)
673 6947985 : *ploc = next;
674 : return result;
675 : }
676 : }
677 :
678 : return 0;
679 : }
680 :
681 : /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 : insn. The substitution can be undone by undo_all. If INTO is already
683 : set to NEWVAL, do not record this change. Because computing NEWVAL might
684 : also call SUBST, we have to compute it before we put anything into
685 : the undo table. */
686 :
687 : static void
688 763433743 : do_SUBST (rtx *into, rtx newval)
689 : {
690 763433743 : struct undo *buf;
691 763433743 : rtx oldval = *into;
692 :
693 763433743 : if (oldval == newval)
694 : return;
695 :
696 : /* We'd like to catch as many invalid transformations here as
697 : possible. Unfortunately, there are way too many mode changes
698 : that are perfectly valid, so we'd waste too much effort for
699 : little gain doing the checks here. Focus on catching invalid
700 : transformations involving integer constants. */
701 96560021 : if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 58528837 : && CONST_INT_P (newval))
703 : {
704 : /* Sanity check that we're replacing oldval with a CONST_INT
705 : that is a valid sign-extension for the original mode. */
706 1797833 : gcc_assert (INTVAL (newval)
707 : == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 :
709 : /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 : CONST_INT is not valid, because after the replacement, the
711 : original mode would be gone. Unfortunately, we can't tell
712 : when do_SUBST is called to replace the operand thereof, so we
713 : perform this test on oldval instead, checking whether an
714 : invalid replacement took place before we got here. */
715 1797833 : gcc_assert (!(GET_CODE (oldval) == SUBREG
716 : && CONST_INT_P (SUBREG_REG (oldval))));
717 1797833 : gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 : && CONST_INT_P (XEXP (oldval, 0))));
719 : }
720 :
721 96560021 : if (undobuf.frees)
722 92400359 : buf = undobuf.frees, undobuf.frees = buf->next;
723 : else
724 4159662 : buf = XNEW (struct undo);
725 :
726 96560021 : buf->kind = UNDO_RTX;
727 96560021 : buf->where.r = into;
728 96560021 : buf->old_contents.r = oldval;
729 96560021 : *into = newval;
730 :
731 96560021 : buf->next = undobuf.undos, undobuf.undos = buf;
732 : }
733 :
734 : #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
735 :
736 : /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 : for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 : not safe. */
739 :
740 : static void
741 16189080 : do_SUBST_INT (int *into, int newval)
742 : {
743 16189080 : struct undo *buf;
744 16189080 : int oldval = *into;
745 :
746 16189080 : if (oldval == newval)
747 : return;
748 :
749 6998326 : if (undobuf.frees)
750 6470771 : buf = undobuf.frees, undobuf.frees = buf->next;
751 : else
752 527555 : buf = XNEW (struct undo);
753 :
754 6998326 : buf->kind = UNDO_INT;
755 6998326 : buf->where.i = into;
756 6998326 : buf->old_contents.i = oldval;
757 6998326 : *into = newval;
758 :
759 6998326 : buf->next = undobuf.undos, undobuf.undos = buf;
760 : }
761 :
762 : #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
763 :
764 : /* Similar to SUBST, but just substitute the mode. This is used when
765 : changing the mode of a pseudo-register, so that any other
766 : references to the entry in the regno_reg_rtx array will change as
767 : well. */
768 :
769 : static void
770 1454475 : subst_mode (int regno, machine_mode newval)
771 : {
772 1454475 : struct undo *buf;
773 1454475 : rtx reg = regno_reg_rtx[regno];
774 1454475 : machine_mode oldval = GET_MODE (reg);
775 :
776 1454475 : if (oldval == newval)
777 : return;
778 :
779 1454475 : if (undobuf.frees)
780 1375568 : buf = undobuf.frees, undobuf.frees = buf->next;
781 : else
782 78907 : buf = XNEW (struct undo);
783 :
784 1454475 : buf->kind = UNDO_MODE;
785 1454475 : buf->where.regno = regno;
786 1454475 : buf->old_contents.m = oldval;
787 1454475 : adjust_reg_mode (reg, newval);
788 :
789 1454475 : buf->next = undobuf.undos, undobuf.undos = buf;
790 : }
791 :
792 : /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
793 :
794 : static void
795 71783 : do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
796 : {
797 71783 : struct undo *buf;
798 71783 : struct insn_link * oldval = *into;
799 :
800 71783 : if (oldval == newval)
801 : return;
802 :
803 71783 : if (undobuf.frees)
804 68748 : buf = undobuf.frees, undobuf.frees = buf->next;
805 : else
806 3035 : buf = XNEW (struct undo);
807 :
808 71783 : buf->kind = UNDO_LINKS;
809 71783 : buf->where.l = into;
810 71783 : buf->old_contents.l = oldval;
811 71783 : *into = newval;
812 :
813 71783 : buf->next = undobuf.undos, undobuf.undos = buf;
814 : }
815 :
816 : #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
817 :
818 : /* Subroutine of try_combine. Determine whether the replacement patterns
819 : NEWPAT, NEWI2PAT and NEWOTHERPAT are more expensive according to insn_cost
820 : than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
821 : that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
822 : undobuf.other_insn may also both be NULL_RTX. Return false if the cost
823 : of all the instructions can be estimated and the replacements are more
824 : expensive than the original sequence. */
825 :
826 : static bool
827 4280081 : combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
828 : rtx newpat, rtx newi2pat, rtx newotherpat,
829 : int insn_code, int i2_code, int other_code)
830 : {
831 4280081 : int i0_cost, i1_cost, i2_cost, i3_cost;
832 4280081 : int new_i2_cost, new_i3_cost;
833 4280081 : int old_cost, new_cost;
834 :
835 : /* Lookup the original insn_costs. */
836 4280081 : i2_cost = INSN_COST (i2);
837 4280081 : i3_cost = INSN_COST (i3);
838 :
839 4280081 : if (i1)
840 : {
841 121643 : i1_cost = INSN_COST (i1);
842 121643 : if (i0)
843 : {
844 4947 : i0_cost = INSN_COST (i0);
845 4814 : old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
846 9749 : ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
847 : }
848 : else
849 : {
850 112138 : old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
851 228832 : ? i1_cost + i2_cost + i3_cost : 0);
852 : i0_cost = 0;
853 : }
854 : }
855 : else
856 : {
857 4158438 : old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
858 : i1_cost = i0_cost = 0;
859 : }
860 :
861 : /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
862 : correct that. */
863 4280081 : if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
864 2228 : old_cost -= i1_cost;
865 :
866 :
867 : /* Calculate the replacement insn_costs. */
868 4280081 : rtx tmp = PATTERN (i3);
869 4280081 : PATTERN (i3) = newpat;
870 4280081 : int tmpi = INSN_CODE (i3);
871 4280081 : INSN_CODE (i3) = insn_code;
872 4280081 : new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
873 4280081 : PATTERN (i3) = tmp;
874 4280081 : INSN_CODE (i3) = tmpi;
875 4280081 : if (newi2pat)
876 : {
877 215111 : tmp = PATTERN (i2);
878 215111 : PATTERN (i2) = newi2pat;
879 215111 : tmpi = INSN_CODE (i2);
880 215111 : INSN_CODE (i2) = i2_code;
881 215111 : new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
882 215111 : PATTERN (i2) = tmp;
883 215111 : INSN_CODE (i2) = tmpi;
884 215111 : new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
885 215111 : ? new_i2_cost + new_i3_cost : 0;
886 : }
887 : else
888 : {
889 : new_cost = new_i3_cost;
890 : new_i2_cost = 0;
891 : }
892 :
893 4280081 : if (undobuf.other_insn)
894 : {
895 223838 : int old_other_cost, new_other_cost;
896 :
897 223838 : old_other_cost = INSN_COST (undobuf.other_insn);
898 223838 : tmp = PATTERN (undobuf.other_insn);
899 223838 : PATTERN (undobuf.other_insn) = newotherpat;
900 223838 : tmpi = INSN_CODE (undobuf.other_insn);
901 223838 : INSN_CODE (undobuf.other_insn) = other_code;
902 223838 : new_other_cost = insn_cost (undobuf.other_insn,
903 : optimize_this_for_speed_p);
904 223838 : PATTERN (undobuf.other_insn) = tmp;
905 223838 : INSN_CODE (undobuf.other_insn) = tmpi;
906 223838 : if (old_other_cost > 0 && new_other_cost > 0)
907 : {
908 223838 : old_cost += old_other_cost;
909 223838 : new_cost += new_other_cost;
910 : }
911 : else
912 : old_cost = 0;
913 : }
914 :
915 : /* Disallow this combination if both new_cost and old_cost are greater than
916 : zero, and new_cost is greater than old cost. */
917 4280081 : bool reject = old_cost > 0 && new_cost > old_cost;
918 :
919 4280081 : if (dump_file)
920 : {
921 484 : fprintf (dump_file, "%s combination of insns ",
922 : reject ? "rejecting" : "allowing");
923 244 : if (i0)
924 0 : fprintf (dump_file, "%d, ", INSN_UID (i0));
925 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
926 1 : fprintf (dump_file, "%d, ", INSN_UID (i1));
927 244 : fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
928 :
929 244 : fprintf (dump_file, "original costs ");
930 244 : if (i0)
931 0 : fprintf (dump_file, "%d + ", i0_cost);
932 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
933 1 : fprintf (dump_file, "%d + ", i1_cost);
934 244 : fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
935 :
936 244 : if (newi2pat)
937 19 : fprintf (dump_file, "replacement costs %d + %d = %d\n",
938 : new_i2_cost, new_i3_cost, new_cost);
939 : else
940 225 : fprintf (dump_file, "replacement cost %d\n", new_cost);
941 : }
942 :
943 4280081 : if (reject)
944 : return false;
945 :
946 : /* Update the uid_insn_cost array with the replacement costs. */
947 4067065 : INSN_COST (i2) = new_i2_cost;
948 4067065 : INSN_COST (i3) = new_i3_cost;
949 4067065 : if (i1)
950 : {
951 103010 : INSN_COST (i1) = 0;
952 103010 : if (i0)
953 4592 : INSN_COST (i0) = 0;
954 : }
955 :
956 : return true;
957 : }
958 :
959 :
960 : /* Delete any insns that copy a register to itself.
961 : Return true if the CFG was changed. */
962 :
963 : static bool
964 1017764 : delete_noop_moves (void)
965 : {
966 1017764 : rtx_insn *insn, *next;
967 1017764 : basic_block bb;
968 :
969 1017764 : bool edges_deleted = false;
970 :
971 11576436 : FOR_EACH_BB_FN (bb, cfun)
972 : {
973 143529134 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
974 : {
975 132970462 : next = NEXT_INSN (insn);
976 132970462 : if (INSN_P (insn) && noop_move_p (insn))
977 : {
978 6853 : if (dump_file)
979 0 : fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
980 :
981 6853 : edges_deleted |= delete_insn_and_edges (insn);
982 : }
983 : }
984 : }
985 :
986 1017764 : return edges_deleted;
987 : }
988 :
989 :
990 : /* Return false if we do not want to (or cannot) combine DEF. */
991 : static bool
992 42743452 : can_combine_def_p (df_ref def)
993 : {
994 : /* Do not consider if it is pre/post modification in MEM. */
995 42743452 : if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
996 : return false;
997 :
998 41067516 : unsigned int regno = DF_REF_REGNO (def);
999 :
1000 : /* Do not combine frame pointer adjustments. */
1001 41067516 : if ((regno == FRAME_POINTER_REGNUM
1002 0 : && (!reload_completed || frame_pointer_needed))
1003 2062 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 41067516 : && regno == HARD_FRAME_POINTER_REGNUM
1005 : && (!reload_completed || frame_pointer_needed))
1006 41065454 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1007 0 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1008 2062 : return false;
1009 :
1010 : return true;
1011 : }
1012 :
1013 : /* Return false if we do not want to (or cannot) combine USE. */
1014 : static bool
1015 79228710 : can_combine_use_p (df_ref use)
1016 : {
1017 : /* Do not consider the usage of the stack pointer by function call. */
1018 0 : if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1019 0 : return false;
1020 :
1021 : return true;
1022 : }
1023 :
1024 : /* Fill in log links field for all insns. */
1025 :
1026 : static void
1027 1017764 : create_log_links (void)
1028 : {
1029 1017764 : basic_block bb;
1030 1017764 : rtx_insn **next_use;
1031 1017764 : rtx_insn *insn;
1032 1017764 : df_ref def, use;
1033 :
1034 1017764 : next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1035 :
1036 : /* Pass through each block from the end, recording the uses of each
1037 : register and establishing log links when def is encountered.
1038 : Note that we do not clear next_use array in order to save time,
1039 : so we have to test whether the use is in the same basic block as def.
1040 :
1041 : There are a few cases below when we do not consider the definition or
1042 : usage -- these are taken from original flow.c did. Don't ask me why it is
1043 : done this way; I don't know and if it works, I don't want to know. */
1044 :
1045 11576436 : FOR_EACH_BB_FN (bb, cfun)
1046 : {
1047 143512249 : FOR_BB_INSNS_REVERSE (bb, insn)
1048 : {
1049 132953577 : if (!NONDEBUG_INSN_P (insn))
1050 69992382 : continue;
1051 :
1052 : /* Log links are created only once. */
1053 62961195 : gcc_assert (!LOG_LINKS (insn));
1054 :
1055 507483548 : FOR_EACH_INSN_DEF (def, insn)
1056 : {
1057 444522353 : unsigned int regno = DF_REF_REGNO (def);
1058 444522353 : rtx_insn *use_insn;
1059 :
1060 444522353 : if (!next_use[regno])
1061 401778901 : continue;
1062 :
1063 42743452 : if (!can_combine_def_p (def))
1064 1677998 : continue;
1065 :
1066 41065454 : use_insn = next_use[regno];
1067 41065454 : next_use[regno] = NULL;
1068 :
1069 41065454 : if (BLOCK_FOR_INSN (use_insn) != bb)
1070 2270036 : continue;
1071 :
1072 : /* flow.c claimed:
1073 :
1074 : We don't build a LOG_LINK for hard registers contained
1075 : in ASM_OPERANDs. If these registers get replaced,
1076 : we might wind up changing the semantics of the insn,
1077 : even if reload can make what appear to be valid
1078 : assignments later. */
1079 38796270 : if (regno < FIRST_PSEUDO_REGISTER
1080 38795418 : && asm_noperands (PATTERN (use_insn)) >= 0)
1081 852 : continue;
1082 :
1083 : /* Don't add duplicate links between instructions. */
1084 38794566 : struct insn_link *links;
1085 52009068 : FOR_EACH_LOG_LINK (links, use_insn)
1086 13214502 : if (insn == links->insn && regno == links->regno)
1087 : break;
1088 :
1089 38794566 : if (!links)
1090 38794566 : LOG_LINKS (use_insn)
1091 77589132 : = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1092 : }
1093 :
1094 142189905 : FOR_EACH_INSN_USE (use, insn)
1095 153681640 : if (can_combine_use_p (use))
1096 74452930 : next_use[DF_REF_REGNO (use)] = insn;
1097 : }
1098 : }
1099 :
1100 1017764 : free (next_use);
1101 1017764 : }
1102 :
1103 : /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 : true if we found a LOG_LINK that proves that A feeds B. This only works
1105 : if there are no instructions between A and B which could have a link
1106 : depending on A, since in that case we would not record a link for B. */
1107 :
1108 : static bool
1109 13213412 : insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1110 : {
1111 13213412 : struct insn_link *links;
1112 16642393 : FOR_EACH_LOG_LINK (links, b)
1113 14038687 : if (links->insn == a)
1114 : return true;
1115 : return false;
1116 : }
1117 :
1118 : /* Main entry point for combiner. F is the first insn of the function.
1119 : NREGS is the first unused pseudo-reg number.
1120 :
1121 : Return nonzero if the CFG was changed (e.g. if the combiner has
1122 : turned an indirect jump instruction into a direct jump). */
1123 : static bool
1124 1062343 : combine_instructions (rtx_insn *f, unsigned int nregs)
1125 : {
1126 1062343 : rtx_insn *insn, *next;
1127 1062343 : struct insn_link *links, *nextlinks;
1128 1062343 : rtx_insn *first;
1129 1062343 : basic_block last_bb;
1130 :
1131 1062343 : bool new_direct_jump_p = false;
1132 :
1133 3182283 : for (first = f; first && !NONDEBUG_INSN_P (first); )
1134 2119940 : first = NEXT_INSN (first);
1135 1062343 : if (!first)
1136 : return false;
1137 :
1138 1017764 : combine_attempts = 0;
1139 1017764 : combine_merges = 0;
1140 1017764 : combine_extras = 0;
1141 1017764 : combine_successes = 0;
1142 :
1143 1017764 : rtl_hooks = combine_rtl_hooks;
1144 :
1145 1017764 : reg_stat.safe_grow_cleared (nregs, true);
1146 :
1147 1017764 : init_recog_no_volatile ();
1148 :
1149 : /* Allocate array for insn info. */
1150 1017764 : max_uid_known = get_max_uid ();
1151 1017764 : uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1152 1017764 : uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1153 1017764 : gcc_obstack_init (&insn_link_obstack);
1154 :
1155 1017764 : nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1156 :
1157 : /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1158 : problems when, for example, we have j <<= 1 in a loop. */
1159 :
1160 1017764 : nonzero_sign_valid = 0;
1161 1017764 : label_tick = label_tick_ebb_start = 1;
1162 :
1163 : /* Scan all SETs and see if we can deduce anything about what
1164 : bits are known to be zero for some registers and how many copies
1165 : of the sign bit are known to exist for those registers.
1166 :
1167 : Also set any known values so that we can use it while searching
1168 : for what bits are known to be set. */
1169 :
1170 1017764 : setup_incoming_promotions (first);
1171 : /* Allow the entry block and the first block to fall into the same EBB.
1172 : Conceptually the incoming promotions are assigned to the entry block. */
1173 1017764 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1174 :
1175 1017764 : create_log_links ();
1176 11576436 : FOR_EACH_BB_FN (this_basic_block, cfun)
1177 : {
1178 10558672 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1179 10558672 : last_call_luid = 0;
1180 10558672 : mem_last_set = -1;
1181 :
1182 10558672 : label_tick++;
1183 10558672 : if (!single_pred_p (this_basic_block)
1184 10558672 : || single_pred (this_basic_block) != last_bb)
1185 5068475 : label_tick_ebb_start = label_tick;
1186 10558672 : last_bb = this_basic_block;
1187 :
1188 143512249 : FOR_BB_INSNS (this_basic_block, insn)
1189 132953577 : if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1190 : {
1191 116210479 : rtx links;
1192 :
1193 116210479 : subst_low_luid = DF_INSN_LUID (insn);
1194 116210479 : subst_insn = insn;
1195 :
1196 116210479 : note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1197 116210479 : record_dead_and_set_regs (insn);
1198 :
1199 116210479 : if (AUTO_INC_DEC)
1200 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1201 : if (REG_NOTE_KIND (links) == REG_INC)
1202 : set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1203 : insn);
1204 :
1205 : /* Record the current insn_cost of this instruction. */
1206 116210479 : INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1207 116210479 : if (dump_file)
1208 : {
1209 1695 : fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1210 1695 : dump_insn_slim (dump_file, insn);
1211 : }
1212 : }
1213 : }
1214 :
1215 1017764 : nonzero_sign_valid = 1;
1216 :
1217 : /* Now scan all the insns in forward order. */
1218 1017764 : label_tick = label_tick_ebb_start = 1;
1219 1017764 : init_reg_last ();
1220 1017764 : setup_incoming_promotions (first);
1221 1017764 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1222 1017764 : int max_combine = param_max_combine_insns;
1223 :
1224 11576436 : FOR_EACH_BB_FN (this_basic_block, cfun)
1225 : {
1226 10558672 : rtx_insn *last_combined_insn = NULL;
1227 :
1228 : /* Ignore instruction combination in basic blocks that are going to
1229 : be removed as unreachable anyway. See PR82386. */
1230 10558672 : if (EDGE_COUNT (this_basic_block->preds) == 0)
1231 1643 : continue;
1232 :
1233 10557029 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1234 10557029 : last_call_luid = 0;
1235 10557029 : mem_last_set = -1;
1236 :
1237 10557029 : label_tick++;
1238 10557029 : if (!single_pred_p (this_basic_block)
1239 10557029 : || single_pred (this_basic_block) != last_bb)
1240 5068127 : label_tick_ebb_start = label_tick;
1241 10557029 : last_bb = this_basic_block;
1242 :
1243 10557029 : rtl_profile_for_bb (this_basic_block);
1244 10557029 : for (insn = BB_HEAD (this_basic_block);
1245 148072373 : insn != NEXT_INSN (BB_END (this_basic_block));
1246 133448279 : insn = next ? next : NEXT_INSN (insn))
1247 : {
1248 137515344 : next = 0;
1249 137515344 : if (!NONDEBUG_INSN_P (insn))
1250 70199885 : continue;
1251 :
1252 : while (last_combined_insn
1253 67317453 : && (!NONDEBUG_INSN_P (last_combined_insn)
1254 56948081 : || last_combined_insn->deleted ()))
1255 1994 : last_combined_insn = PREV_INSN (last_combined_insn);
1256 67315459 : if (last_combined_insn == NULL_RTX
1257 56947462 : || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1258 124262695 : || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1259 : last_combined_insn = insn;
1260 :
1261 : /* See if we know about function return values before this
1262 : insn based upon SUBREG flags. */
1263 67315459 : check_promoted_subreg (insn, PATTERN (insn));
1264 :
1265 : /* See if we can find hardregs and subreg of pseudos in
1266 : narrower modes. This could help turning TRUNCATEs
1267 : into SUBREGs. */
1268 67315459 : note_uses (&PATTERN (insn), record_truncated_values, NULL);
1269 :
1270 : /* Try this insn with each insn it links back to. */
1271 :
1272 105178188 : FOR_EACH_LOG_LINK (links, insn)
1273 41802143 : if ((next = try_combine (insn, links->insn, NULL,
1274 : NULL, &new_direct_jump_p,
1275 : last_combined_insn)) != 0)
1276 : {
1277 3939414 : statistics_counter_event (cfun, "two-insn combine", 1);
1278 3939414 : goto retry;
1279 : }
1280 :
1281 : /* Try each sequence of three linked insns ending with this one. */
1282 :
1283 63376045 : if (max_combine >= 3)
1284 100637532 : FOR_EACH_LOG_LINK (links, insn)
1285 : {
1286 37444371 : rtx_insn *link = links->insn;
1287 :
1288 : /* If the linked insn has been replaced by a note, then there
1289 : is no point in pursuing this chain any further. */
1290 37444371 : if (NOTE_P (link))
1291 227 : continue;
1292 :
1293 55759165 : FOR_EACH_LOG_LINK (nextlinks, link)
1294 18396286 : if ((next = try_combine (insn, link, nextlinks->insn,
1295 : NULL, &new_direct_jump_p,
1296 : last_combined_insn)) != 0)
1297 : {
1298 81265 : statistics_counter_event (cfun, "three-insn combine", 1);
1299 81265 : goto retry;
1300 : }
1301 : }
1302 :
1303 : /* Try combining an insn with two different insns whose results it
1304 : uses. */
1305 63193161 : if (max_combine >= 3)
1306 100520316 : FOR_EACH_LOG_LINK (links, insn)
1307 50236223 : for (nextlinks = links->next; nextlinks;
1308 12894354 : nextlinks = nextlinks->next)
1309 12909068 : if ((next = try_combine (insn, links->insn,
1310 : nextlinks->insn, NULL,
1311 : &new_direct_jump_p,
1312 : last_combined_insn)) != 0)
1313 :
1314 : {
1315 14714 : statistics_counter_event (cfun, "three-insn combine", 1);
1316 14714 : goto retry;
1317 : }
1318 :
1319 : /* Try four-instruction combinations. */
1320 63178447 : if (max_combine >= 4)
1321 100497796 : FOR_EACH_LOG_LINK (links, insn)
1322 : {
1323 37323884 : struct insn_link *next1;
1324 37323884 : rtx_insn *link = links->insn;
1325 :
1326 : /* If the linked insn has been replaced by a note, then there
1327 : is no point in pursuing this chain any further. */
1328 37323884 : if (NOTE_P (link))
1329 226 : continue;
1330 :
1331 55616135 : FOR_EACH_LOG_LINK (next1, link)
1332 : {
1333 18293839 : rtx_insn *link1 = next1->insn;
1334 18293839 : if (NOTE_P (link1))
1335 76 : continue;
1336 : /* I0 -> I1 -> I2 -> I3. */
1337 29909152 : FOR_EACH_LOG_LINK (nextlinks, link1)
1338 11616639 : if ((next = try_combine (insn, link, link1,
1339 : nextlinks->insn,
1340 : &new_direct_jump_p,
1341 : last_combined_insn)) != 0)
1342 : {
1343 1250 : statistics_counter_event (cfun, "four-insn combine", 1);
1344 1250 : goto retry;
1345 : }
1346 : /* I0, I1 -> I2, I2 -> I3. */
1347 22259761 : for (nextlinks = next1->next; nextlinks;
1348 3967248 : nextlinks = nextlinks->next)
1349 3967360 : if ((next = try_combine (insn, link, link1,
1350 : nextlinks->insn,
1351 : &new_direct_jump_p,
1352 : last_combined_insn)) != 0)
1353 : {
1354 112 : statistics_counter_event (cfun, "four-insn combine", 1);
1355 112 : goto retry;
1356 : }
1357 : }
1358 :
1359 50213226 : for (next1 = links->next; next1; next1 = next1->next)
1360 : {
1361 12894024 : rtx_insn *link1 = next1->insn;
1362 12894024 : if (NOTE_P (link1))
1363 8 : continue;
1364 : /* I0 -> I2; I1, I2 -> I3. */
1365 16343909 : FOR_EACH_LOG_LINK (nextlinks, link)
1366 3452803 : if ((next = try_combine (insn, link, link1,
1367 : nextlinks->insn,
1368 : &new_direct_jump_p,
1369 : last_combined_insn)) != 0)
1370 : {
1371 2910 : statistics_counter_event (cfun, "four-insn combine", 1);
1372 2910 : goto retry;
1373 : }
1374 : /* I0 -> I1; I1, I2 -> I3. */
1375 16595549 : FOR_EACH_LOG_LINK (nextlinks, link1)
1376 3704627 : if ((next = try_combine (insn, link, link1,
1377 : nextlinks->insn,
1378 : &new_direct_jump_p,
1379 : last_combined_insn)) != 0)
1380 : {
1381 184 : statistics_counter_event (cfun, "four-insn combine", 1);
1382 184 : goto retry;
1383 : }
1384 : }
1385 : }
1386 :
1387 : /* Try this insn with each REG_EQUAL note it links back to. */
1388 100619484 : FOR_EACH_LOG_LINK (links, insn)
1389 : {
1390 37371090 : rtx set, note;
1391 37371090 : rtx_insn *temp = links->insn;
1392 37371090 : if ((set = single_set (temp)) != 0
1393 36978472 : && (note = find_reg_equal_equiv_note (temp)) != 0
1394 2759267 : && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1395 2759267 : && ! side_effects_p (SET_SRC (set))
1396 : /* Avoid using a register that may already been marked
1397 : dead by an earlier instruction. */
1398 2759267 : && ! unmentioned_reg_p (note, SET_SRC (set))
1399 38737009 : && (GET_MODE (note) == VOIDmode
1400 26819 : ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1401 1339100 : : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1402 1339067 : && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1403 0 : || (GET_MODE (XEXP (SET_DEST (set), 0))
1404 : == GET_MODE (note))))))
1405 : {
1406 : /* Temporarily replace the set's source with the
1407 : contents of the REG_EQUAL note. The insn will
1408 : be deleted or recognized by try_combine. */
1409 1365869 : rtx orig_src = SET_SRC (set);
1410 1365869 : rtx orig_dest = SET_DEST (set);
1411 1365869 : if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1412 0 : SET_DEST (set) = XEXP (SET_DEST (set), 0);
1413 1365869 : SET_SRC (set) = note;
1414 1365869 : i2mod = temp;
1415 1365869 : i2mod_old_rhs = copy_rtx (orig_src);
1416 1365869 : i2mod_new_rhs = copy_rtx (note);
1417 1365869 : next = try_combine (insn, i2mod, NULL, NULL,
1418 : &new_direct_jump_p,
1419 : last_combined_insn);
1420 1365869 : i2mod = NULL;
1421 1365869 : if (next)
1422 : {
1423 27216 : statistics_counter_event (cfun, "insn-with-note combine", 1);
1424 27216 : goto retry;
1425 : }
1426 1338653 : INSN_CODE (temp) = -1;
1427 1338653 : SET_SRC (set) = orig_src;
1428 1338653 : SET_DEST (set) = orig_dest;
1429 : }
1430 : }
1431 :
1432 63248394 : if (!NOTE_P (insn))
1433 63248394 : record_dead_and_set_regs (insn);
1434 :
1435 137515344 : retry:
1436 137515344 : ;
1437 : }
1438 : }
1439 :
1440 1017764 : default_rtl_profile ();
1441 1017764 : clear_bb_flags ();
1442 :
1443 1017764 : if (purge_all_dead_edges ())
1444 1438 : new_direct_jump_p = true;
1445 1017764 : if (delete_noop_moves ())
1446 0 : new_direct_jump_p = true;
1447 :
1448 : /* Clean up. */
1449 1017764 : obstack_free (&insn_link_obstack, NULL);
1450 1017764 : free (uid_log_links);
1451 1017764 : free (uid_insn_cost);
1452 1017764 : reg_stat.release ();
1453 :
1454 1017764 : {
1455 1017764 : struct undo *undo, *next;
1456 5786923 : for (undo = undobuf.frees; undo; undo = next)
1457 : {
1458 4769159 : next = undo->next;
1459 4769159 : free (undo);
1460 : }
1461 1017764 : undobuf.frees = 0;
1462 : }
1463 :
1464 1017764 : statistics_counter_event (cfun, "attempts", combine_attempts);
1465 1017764 : statistics_counter_event (cfun, "merges", combine_merges);
1466 1017764 : statistics_counter_event (cfun, "extras", combine_extras);
1467 1017764 : statistics_counter_event (cfun, "successes", combine_successes);
1468 :
1469 1017764 : nonzero_sign_valid = 0;
1470 1017764 : rtl_hooks = general_rtl_hooks;
1471 :
1472 : /* Make recognizer allow volatile MEMs again. */
1473 1017764 : init_recog ();
1474 :
1475 1017764 : return new_direct_jump_p;
1476 : }
1477 :
1478 : /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1479 :
1480 : static void
1481 1017764 : init_reg_last (void)
1482 : {
1483 1017764 : unsigned int i;
1484 1017764 : reg_stat_type *p;
1485 :
1486 145160907 : FOR_EACH_VEC_ELT (reg_stat, i, p)
1487 144143143 : memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1488 1017764 : }
1489 :
1490 : /* Set up any promoted values for incoming argument registers. */
1491 :
1492 : static void
1493 2035528 : setup_incoming_promotions (rtx_insn *first)
1494 : {
1495 2035528 : tree arg;
1496 2035528 : bool strictly_local = false;
1497 :
1498 5511140 : for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 3475612 : arg = DECL_CHAIN (arg))
1500 : {
1501 3475612 : rtx x, reg = DECL_INCOMING_RTL (arg);
1502 3475612 : int uns1, uns3;
1503 3475612 : machine_mode mode1, mode2, mode3, mode4;
1504 :
1505 : /* Only continue if the incoming argument is in a register. */
1506 3475612 : if (!REG_P (reg))
1507 3475512 : continue;
1508 :
1509 : /* Determine, if possible, whether all call sites of the current
1510 : function lie within the current compilation unit. (This does
1511 : take into account the exporting of a function via taking its
1512 : address, and so forth.) */
1513 2733190 : strictly_local
1514 2733190 : = cgraph_node::local_info_node (current_function_decl)->local;
1515 :
1516 : /* The mode and signedness of the argument before any promotions happen
1517 : (equal to the mode of the pseudo holding it at that stage). */
1518 2733190 : mode1 = TYPE_MODE (TREE_TYPE (arg));
1519 2733190 : uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1520 :
1521 : /* The mode and signedness of the argument after any source language and
1522 : TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1523 2733190 : mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1524 2733190 : uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1525 :
1526 : /* The mode and signedness of the argument as it is actually passed,
1527 : see assign_parm_setup_reg in function.cc. */
1528 2733190 : mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1529 2733190 : TREE_TYPE (cfun->decl), 0);
1530 :
1531 : /* The mode of the register in which the argument is being passed. */
1532 2733190 : mode4 = GET_MODE (reg);
1533 :
1534 : /* Eliminate sign extensions in the callee when:
1535 : (a) A mode promotion has occurred; */
1536 2733190 : if (mode1 == mode3)
1537 2733090 : continue;
1538 : /* (b) The mode of the register is the same as the mode of
1539 : the argument as it is passed; */
1540 100 : if (mode3 != mode4)
1541 0 : continue;
1542 : /* (c) There's no language level extension; */
1543 100 : if (mode1 == mode2)
1544 : ;
1545 : /* (c.1) All callers are from the current compilation unit. If that's
1546 : the case we don't have to rely on an ABI, we only have to know
1547 : what we're generating right now, and we know that we will do the
1548 : mode1 to mode2 promotion with the given sign. */
1549 0 : else if (!strictly_local)
1550 0 : continue;
1551 : /* (c.2) The combination of the two promotions is useful. This is
1552 : true when the signs match, or if the first promotion is unsigned.
1553 : In the later case, (sign_extend (zero_extend x)) is the same as
1554 : (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1555 0 : else if (uns1)
1556 0 : uns3 = true;
1557 0 : else if (uns3)
1558 0 : continue;
1559 :
1560 : /* Record that the value was promoted from mode1 to mode3,
1561 : so that any sign extension at the head of the current
1562 : function may be eliminated. */
1563 100 : x = gen_rtx_CLOBBER (mode1, const0_rtx);
1564 100 : x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1565 100 : record_value_for_reg (reg, first, x);
1566 : }
1567 2035528 : }
1568 :
1569 : /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1570 : that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1571 : because some machines (maybe most) will actually do the sign-extension and
1572 : this is the conservative approach.
1573 :
1574 : ??? For 2.5, try to tighten up the MD files in this regard instead of this
1575 : kludge. */
1576 :
1577 : static rtx
1578 0 : sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1579 : {
1580 0 : scalar_int_mode int_mode;
1581 0 : if (CONST_INT_P (src)
1582 0 : && is_a <scalar_int_mode> (mode, &int_mode)
1583 0 : && GET_MODE_PRECISION (int_mode) < prec
1584 0 : && INTVAL (src) > 0
1585 0 : && val_signbit_known_set_p (int_mode, INTVAL (src)))
1586 0 : src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1587 :
1588 0 : return src;
1589 : }
1590 :
1591 : /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1592 : and SET. */
1593 :
1594 : static void
1595 23797216 : update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1596 : rtx x)
1597 : {
1598 23797216 : rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1599 23797216 : unsigned HOST_WIDE_INT bits = 0;
1600 23797216 : rtx reg_equal = NULL, src = SET_SRC (set);
1601 23797216 : unsigned int num = 0;
1602 :
1603 23797216 : if (reg_equal_note)
1604 1001440 : reg_equal = XEXP (reg_equal_note, 0);
1605 :
1606 23797216 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
1607 : {
1608 : src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1609 : if (reg_equal)
1610 : reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1611 : }
1612 :
1613 : /* Don't call nonzero_bits if it cannot change anything. */
1614 23797216 : if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1615 : {
1616 20590935 : machine_mode mode = GET_MODE (x);
1617 20590935 : if (GET_MODE_CLASS (mode) == MODE_INT
1618 20590935 : && HWI_COMPUTABLE_MODE_P (mode))
1619 20590803 : mode = nonzero_bits_mode;
1620 20590935 : bits = nonzero_bits (src, mode);
1621 20590935 : if (reg_equal && bits)
1622 948483 : bits &= nonzero_bits (reg_equal, mode);
1623 20590935 : rsp->nonzero_bits |= bits;
1624 : }
1625 :
1626 : /* Don't call num_sign_bit_copies if it cannot change anything. */
1627 23797216 : if (rsp->sign_bit_copies != 1)
1628 : {
1629 20444618 : num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1630 20444618 : if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1631 : {
1632 945735 : unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1633 945735 : if (num == 0 || numeq > num)
1634 20444618 : num = numeq;
1635 : }
1636 20444618 : if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1637 19743767 : rsp->sign_bit_copies = num;
1638 : }
1639 23797216 : }
1640 :
1641 : /* Called via note_stores. If X is a pseudo that is narrower than
1642 : HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1643 :
1644 : If we are setting only a portion of X and we can't figure out what
1645 : portion, assume all bits will be used since we don't know what will
1646 : be happening.
1647 :
1648 : Similarly, set how many bits of X are known to be copies of the sign bit
1649 : at all locations in the function. This is the smallest number implied
1650 : by any set of X. */
1651 :
1652 : static void
1653 73338093 : set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1654 : {
1655 73338093 : rtx_insn *insn = (rtx_insn *) data;
1656 73338093 : scalar_int_mode mode;
1657 :
1658 73338093 : if (REG_P (x)
1659 59063952 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1660 : /* If this register is undefined at the start of the file, we can't
1661 : say what its contents were. */
1662 59032348 : && ! REGNO_REG_SET_P
1663 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1664 29415419 : && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1665 98060789 : && HWI_COMPUTABLE_MODE_P (mode))
1666 : {
1667 24004363 : reg_stat_type *rsp = ®_stat[REGNO (x)];
1668 :
1669 24004363 : if (set == 0 || GET_CODE (set) == CLOBBER)
1670 : {
1671 22629 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1672 22629 : rsp->sign_bit_copies = 1;
1673 22629 : return;
1674 : }
1675 :
1676 : /* If this register is being initialized using itself, and the
1677 : register is uninitialized in this basic block, and there are
1678 : no LOG_LINKS which set the register, then part of the
1679 : register is uninitialized. In that case we can't assume
1680 : anything about the number of nonzero bits.
1681 :
1682 : ??? We could do better if we checked this in
1683 : reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1684 : could avoid making assumptions about the insn which initially
1685 : sets the register, while still using the information in other
1686 : insns. We would have to be careful to check every insn
1687 : involved in the combination. */
1688 :
1689 23981734 : if (insn
1690 22571128 : && reg_referenced_p (x, PATTERN (insn))
1691 26546634 : && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1692 : REGNO (x)))
1693 : {
1694 255463 : struct insn_link *link;
1695 :
1696 384789 : FOR_EACH_LOG_LINK (link, insn)
1697 298395 : if (dead_or_set_p (link->insn, x))
1698 : break;
1699 255463 : if (!link)
1700 : {
1701 86394 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1702 86394 : rsp->sign_bit_copies = 1;
1703 86394 : return;
1704 : }
1705 : }
1706 :
1707 : /* If this is a complex assignment, see if we can convert it into a
1708 : simple assignment. */
1709 23895340 : set = expand_field_assignment (set);
1710 :
1711 : /* If this is a simple assignment, or we have a paradoxical SUBREG,
1712 : set what we know about X. */
1713 :
1714 23895340 : if (SET_DEST (set) == x
1715 23895340 : || (paradoxical_subreg_p (SET_DEST (set))
1716 4508 : && SUBREG_REG (SET_DEST (set)) == x))
1717 23797216 : update_rsp_from_reg_equal (rsp, insn, set, x);
1718 : else
1719 : {
1720 98124 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1721 98124 : rsp->sign_bit_copies = 1;
1722 : }
1723 : }
1724 : }
1725 :
1726 : /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1727 : optionally insns that were previously combined into I3 or that will be
1728 : combined into the merger of INSN and I3. The order is PRED, PRED2,
1729 : INSN, SUCC, SUCC2, I3.
1730 :
1731 : Return false if the combination is not allowed for any reason.
1732 :
1733 : If the combination is allowed, *PDEST will be set to the single
1734 : destination of INSN and *PSRC to the single source, and this function
1735 : will return true. */
1736 :
1737 : static bool
1738 62024699 : can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1739 : rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1740 : rtx *pdest, rtx *psrc)
1741 : {
1742 62024699 : int i;
1743 62024699 : const_rtx set = 0;
1744 62024699 : rtx src, dest;
1745 62024699 : rtx_insn *p;
1746 62024699 : rtx link;
1747 62024699 : bool all_adjacent = true;
1748 62024699 : bool (*is_volatile_p) (const_rtx);
1749 :
1750 62024699 : if (succ)
1751 : {
1752 14607860 : if (succ2)
1753 : {
1754 2173105 : if (next_active_insn (succ2) != i3)
1755 194051 : all_adjacent = false;
1756 2173105 : if (next_active_insn (succ) != succ2)
1757 2046059 : all_adjacent = false;
1758 : }
1759 12434755 : else if (next_active_insn (succ) != i3)
1760 2046059 : all_adjacent = false;
1761 14607860 : if (next_active_insn (insn) != succ)
1762 17260776 : all_adjacent = false;
1763 : }
1764 47416839 : else if (next_active_insn (insn) != i3)
1765 17260776 : all_adjacent = false;
1766 :
1767 : /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1768 : or a PARALLEL consisting of such a SET and CLOBBERs.
1769 :
1770 : If INSN has CLOBBER parallel parts, ignore them for our processing.
1771 : By definition, these happen during the execution of the insn. When it
1772 : is merged with another insn, all bets are off. If they are, in fact,
1773 : needed and aren't also supplied in I3, they may be added by
1774 : recog_for_combine. Otherwise, it won't match.
1775 :
1776 : We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1777 : note.
1778 :
1779 : Get the source and destination of INSN. If more than one, can't
1780 : combine. */
1781 :
1782 62024699 : if (GET_CODE (PATTERN (insn)) == SET)
1783 : set = PATTERN (insn);
1784 16303634 : else if (GET_CODE (PATTERN (insn)) == PARALLEL
1785 16303634 : && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1786 : {
1787 48860888 : for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1788 : {
1789 33075464 : rtx elt = XVECEXP (PATTERN (insn), 0, i);
1790 :
1791 33075464 : switch (GET_CODE (elt))
1792 : {
1793 : /* This is important to combine floating point insns
1794 : for the SH4 port. */
1795 135505 : case USE:
1796 : /* Combining an isolated USE doesn't make sense.
1797 : We depend here on combinable_i3pat to reject them. */
1798 : /* The code below this loop only verifies that the inputs of
1799 : the SET in INSN do not change. We call reg_set_between_p
1800 : to verify that the REG in the USE does not change between
1801 : I3 and INSN.
1802 : If the USE in INSN was for a pseudo register, the matching
1803 : insn pattern will likely match any register; combining this
1804 : with any other USE would only be safe if we knew that the
1805 : used registers have identical values, or if there was
1806 : something to tell them apart, e.g. different modes. For
1807 : now, we forgo such complicated tests and simply disallow
1808 : combining of USES of pseudo registers with any other USE. */
1809 135505 : if (REG_P (XEXP (elt, 0))
1810 135505 : && GET_CODE (PATTERN (i3)) == PARALLEL)
1811 : {
1812 249 : rtx i3pat = PATTERN (i3);
1813 249 : int i = XVECLEN (i3pat, 0) - 1;
1814 249 : unsigned int regno = REGNO (XEXP (elt, 0));
1815 :
1816 509 : do
1817 : {
1818 509 : rtx i3elt = XVECEXP (i3pat, 0, i);
1819 :
1820 509 : if (GET_CODE (i3elt) == USE
1821 225 : && REG_P (XEXP (i3elt, 0))
1822 761 : && (REGNO (XEXP (i3elt, 0)) == regno
1823 198 : ? reg_set_between_p (XEXP (elt, 0),
1824 27 : PREV_INSN (insn), i3)
1825 : : regno >= FIRST_PSEUDO_REGISTER))
1826 : return false;
1827 : }
1828 311 : while (--i >= 0);
1829 : }
1830 : break;
1831 :
1832 : /* We can ignore CLOBBERs. */
1833 : case CLOBBER:
1834 : break;
1835 :
1836 16892691 : case SET:
1837 : /* Ignore SETs whose result isn't used but not those that
1838 : have side-effects. */
1839 16892691 : if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1840 192963 : && insn_nothrow_p (insn)
1841 17072547 : && !side_effects_p (elt))
1842 : break;
1843 :
1844 : /* If we have already found a SET, this is a second one and
1845 : so we cannot combine with this insn. */
1846 16796274 : if (set)
1847 : return false;
1848 :
1849 : set = elt;
1850 : break;
1851 :
1852 : default:
1853 : /* Anything else means we can't combine. */
1854 : return false;
1855 : }
1856 : }
1857 :
1858 15785424 : if (set == 0
1859 : /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1860 : so don't do anything with it. */
1861 15785424 : || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1862 : return false;
1863 : }
1864 : else
1865 : return false;
1866 :
1867 : if (set == 0)
1868 : return false;
1869 :
1870 : /* The simplification in expand_field_assignment may call back to
1871 : get_last_value, so set safe guard here. */
1872 61486927 : subst_low_luid = DF_INSN_LUID (insn);
1873 :
1874 61486927 : set = expand_field_assignment (set);
1875 61486927 : src = SET_SRC (set), dest = SET_DEST (set);
1876 :
1877 : /* Do not eliminate user-specified register if it is in an
1878 : asm input because we may break the register asm usage defined
1879 : in GCC manual if allow to do so.
1880 : Be aware that this may cover more cases than we expect but this
1881 : should be harmless. */
1882 60926871 : if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1883 61486930 : && extract_asm_operands (PATTERN (i3)))
1884 : return false;
1885 :
1886 : /* Don't eliminate a store in the stack pointer. */
1887 61486927 : if (dest == stack_pointer_rtx
1888 : /* Don't combine with an insn that sets a register to itself if it has
1889 : a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1890 59585967 : || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1891 : /* Can't merge an ASM_OPERANDS. */
1892 59585967 : || GET_CODE (src) == ASM_OPERANDS
1893 : /* Can't merge a function call. */
1894 59582351 : || GET_CODE (src) == CALL
1895 : /* Don't eliminate a function call argument. */
1896 59582351 : || (CALL_P (i3)
1897 8897408 : && (find_reg_fusage (i3, USE, dest)
1898 168126 : || (REG_P (dest)
1899 168126 : && REGNO (dest) < FIRST_PSEUDO_REGISTER
1900 283 : && global_regs[REGNO (dest)])))
1901 : /* Don't substitute into an incremented register. */
1902 : || FIND_REG_INC_NOTE (i3, dest)
1903 : || (succ && FIND_REG_INC_NOTE (succ, dest))
1904 59582351 : || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1905 : /* Don't substitute into a non-local goto, this confuses CFG. */
1906 50853066 : || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1907 : /* Make sure that DEST is not used after INSN but before SUCC, or
1908 : after SUCC and before SUCC2, or after SUCC2 but before I3. */
1909 50852345 : || (!all_adjacent
1910 12460598 : && ((succ2
1911 954516 : && (reg_used_between_p (dest, succ2, i3)
1912 934076 : || reg_used_between_p (dest, succ, succ2)))
1913 12395331 : || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1914 12119874 : || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1915 12119874 : || (succ
1916 : /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1917 : that case SUCC is not in the insn stream, so use SUCC2
1918 : instead for this test. */
1919 9986148 : && reg_used_between_p (dest, insn,
1920 : succ2
1921 889249 : && INSN_UID (succ) == INSN_UID (succ2)
1922 : ? succ2 : succ))))
1923 : /* Make sure that the value that is to be substituted for the register
1924 : does not use any registers whose values alter in between. However,
1925 : If the insns are adjacent, a use can't cross a set even though we
1926 : think it might (this can happen for a sequence of insns each setting
1927 : the same destination; last_set of that register might point to
1928 : a NOTE). If INSN has a REG_EQUIV note, the register is always
1929 : equivalent to the memory so the substitution is valid even if there
1930 : are intervening stores. Also, don't move a volatile asm or
1931 : UNSPEC_VOLATILE across any other insns. */
1932 : || (! all_adjacent
1933 12119874 : && (((!MEM_P (src)
1934 3443377 : || ! find_reg_note (insn, REG_EQUIV, src))
1935 12004805 : && modified_between_p (src, insn, i3))
1936 10974273 : || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1937 10974273 : || GET_CODE (src) == UNSPEC_VOLATILE))
1938 : /* Don't combine across a CALL_INSN, because that would possibly
1939 : change whether the life span of some REGs crosses calls or not,
1940 : and it is a pain to update that information.
1941 : Exception: if source is a constant, moving it later can't hurt.
1942 : Accept that as a special case. */
1943 110842487 : || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1944 : return false;
1945 :
1946 : /* DEST must be a REG. */
1947 49055110 : if (REG_P (dest))
1948 : {
1949 : /* If register alignment is being enforced for multi-word items in all
1950 : cases except for parameters, it is possible to have a register copy
1951 : insn referencing a hard register that is not allowed to contain the
1952 : mode being copied and which would not be valid as an operand of most
1953 : insns. Eliminate this problem by not combining with such an insn.
1954 :
1955 : Also, on some machines we don't want to extend the life of a hard
1956 : register. */
1957 :
1958 48499923 : if (REG_P (src)
1959 48499923 : && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1960 29556 : && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1961 : /* Don't extend the life of a hard register unless it is
1962 : user variable (if we have few registers) or it can't
1963 : fit into the desired register (meaning something special
1964 : is going on).
1965 : Also avoid substituting a return register into I3, because
1966 : reload can't handle a conflict with constraints of other
1967 : inputs. */
1968 2568852 : || (REGNO (src) < FIRST_PSEUDO_REGISTER
1969 37487 : && !targetm.hard_regno_mode_ok (REGNO (src),
1970 37487 : GET_MODE (src)))))
1971 : return false;
1972 : }
1973 : else
1974 : return false;
1975 :
1976 :
1977 48499923 : if (GET_CODE (PATTERN (i3)) == PARALLEL)
1978 36626167 : for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1979 24693309 : if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1980 : {
1981 11601245 : rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1982 :
1983 : /* If the clobber represents an earlyclobber operand, we must not
1984 : substitute an expression containing the clobbered register.
1985 : As we do not analyze the constraint strings here, we have to
1986 : make the conservative assumption. However, if the register is
1987 : a fixed hard reg, the clobber cannot represent any operand;
1988 : we leave it up to the machine description to either accept or
1989 : reject use-and-clobber patterns. */
1990 11601245 : if (!REG_P (reg)
1991 11235097 : || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1992 22787560 : || !fixed_regs[REGNO (reg)])
1993 452654 : if (reg_overlap_mentioned_p (reg, src))
1994 : return false;
1995 : }
1996 :
1997 : /* If INSN contains anything volatile, or is an `asm' (whether volatile
1998 : or not), reject, unless nothing volatile comes between it and I3 */
1999 :
2000 48499268 : if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2001 : {
2002 : /* Make sure neither succ nor succ2 contains a volatile reference. */
2003 698691 : if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2004 : return false;
2005 698598 : if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2006 : return false;
2007 : /* We'll check insns between INSN and I3 below. */
2008 : }
2009 :
2010 : /* If INSN is an asm, and DEST is a hard register, reject, since it has
2011 : to be an explicit register variable, and was chosen for a reason. */
2012 :
2013 48463119 : if (GET_CODE (src) == ASM_OPERANDS
2014 48463119 : && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2015 : return false;
2016 :
2017 : /* If INSN contains volatile references (specifically volatile MEMs),
2018 : we cannot combine across any other volatile references.
2019 : Even if INSN doesn't contain volatile references, any intervening
2020 : volatile insn might affect machine state. */
2021 :
2022 96262828 : is_volatile_p = volatile_refs_p (PATTERN (insn))
2023 48463119 : ? volatile_refs_p
2024 : : volatile_insn_p;
2025 :
2026 221553886 : for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2027 124833471 : if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2028 : return false;
2029 :
2030 : /* If INSN contains an autoincrement or autodecrement, make sure that
2031 : register is not used between there and I3, and not already used in
2032 : I3 either. Neither must it be used in PRED or SUCC, if they exist.
2033 : Also insist that I3 not be a jump if using LRA; if it were one
2034 : and the incremented register were spilled, we would lose.
2035 : Reload handles this correctly. */
2036 :
2037 48257296 : if (AUTO_INC_DEC)
2038 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2039 : if (REG_NOTE_KIND (link) == REG_INC
2040 : && ((JUMP_P (i3) && targetm.lra_p ())
2041 : || reg_used_between_p (XEXP (link, 0), insn, i3)
2042 : || (pred != NULL_RTX
2043 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2044 : || (pred2 != NULL_RTX
2045 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2046 : || (succ != NULL_RTX
2047 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2048 : || (succ2 != NULL_RTX
2049 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2050 : || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2051 : return false;
2052 :
2053 : /* If we get here, we have passed all the tests and the combination is
2054 : to be allowed. */
2055 :
2056 48257296 : *pdest = dest;
2057 48257296 : *psrc = src;
2058 :
2059 48257296 : return true;
2060 : }
2061 :
2062 : /* LOC is the location within I3 that contains its pattern or the component
2063 : of a PARALLEL of the pattern. We validate that it is valid for combining.
2064 :
2065 : One problem is if I3 modifies its output, as opposed to replacing it
2066 : entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2067 : doing so would produce an insn that is not equivalent to the original insns.
2068 :
2069 : Consider:
2070 :
2071 : (set (reg:DI 101) (reg:DI 100))
2072 : (set (subreg:SI (reg:DI 101) 0) <foo>)
2073 :
2074 : This is NOT equivalent to:
2075 :
2076 : (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2077 : (set (reg:DI 101) (reg:DI 100))])
2078 :
2079 : Not only does this modify 100 (in which case it might still be valid
2080 : if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2081 :
2082 : We can also run into a problem if I2 sets a register that I1
2083 : uses and I1 gets directly substituted into I3 (not via I2). In that
2084 : case, we would be getting the wrong value of I2DEST into I3, so we
2085 : must reject the combination. This case occurs when I2 and I1 both
2086 : feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2087 : If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2088 : of a SET must prevent combination from occurring. The same situation
2089 : can occur for I0, in which case I0_NOT_IN_SRC is set.
2090 :
2091 : Before doing the above check, we first try to expand a field assignment
2092 : into a set of logical operations.
2093 :
2094 : If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2095 : we place a register that is both set and used within I3. If more than one
2096 : such register is detected, we fail.
2097 :
2098 : Return true if the combination is valid, false otherwise. */
2099 :
2100 : static bool
2101 69394463 : combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2102 : bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2103 : {
2104 69394463 : rtx x = *loc;
2105 :
2106 69394463 : if (GET_CODE (x) == SET)
2107 : {
2108 46767609 : rtx set = x ;
2109 46767609 : rtx dest = SET_DEST (set);
2110 46767609 : rtx src = SET_SRC (set);
2111 46767609 : rtx inner_dest = dest;
2112 46767609 : rtx subdest;
2113 :
2114 46767609 : while (GET_CODE (inner_dest) == STRICT_LOW_PART
2115 47278805 : || GET_CODE (inner_dest) == SUBREG
2116 47278805 : || GET_CODE (inner_dest) == ZERO_EXTRACT)
2117 511196 : inner_dest = XEXP (inner_dest, 0);
2118 :
2119 : /* Check for the case where I3 modifies its output, as discussed
2120 : above. We don't want to prevent pseudos from being combined
2121 : into the address of a MEM, so only prevent the combination if
2122 : i1 or i2 set the same MEM. */
2123 490602 : if ((inner_dest != dest &&
2124 : (!MEM_P (inner_dest)
2125 792 : || rtx_equal_p (i2dest, inner_dest)
2126 792 : || (i1dest && rtx_equal_p (i1dest, inner_dest))
2127 792 : || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2128 489810 : && (reg_overlap_mentioned_p (i2dest, inner_dest)
2129 360646 : || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2130 359350 : || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2131 :
2132 : /* This is the same test done in can_combine_p except we can't test
2133 : all_adjacent; we don't have to, since this instruction will stay
2134 : in place, thus we are not considering increasing the lifetime of
2135 : INNER_DEST.
2136 :
2137 : Also, if this insn sets a function argument, combining it with
2138 : something that might need a spill could clobber a previous
2139 : function argument; the all_adjacent test in can_combine_p also
2140 : checks this; here, we do a more specific test for this case. */
2141 :
2142 46637057 : || (REG_P (inner_dest)
2143 29994691 : && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2144 7426479 : && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2145 7426479 : GET_MODE (inner_dest)))
2146 46637057 : || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2147 93397833 : || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2148 : return false;
2149 :
2150 : /* If DEST is used in I3, it is being killed in this insn, so
2151 : record that for later. We have to consider paradoxical
2152 : subregs here, since they kill the whole register, but we
2153 : ignore partial subregs, STRICT_LOW_PART, etc.
2154 : Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2155 : STACK_POINTER_REGNUM, since these are always considered to be
2156 : live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2157 46599597 : subdest = dest;
2158 46599597 : if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2159 249779 : subdest = SUBREG_REG (subdest);
2160 46599597 : if (pi3dest_killed
2161 33861256 : && REG_P (subdest)
2162 21494816 : && reg_referenced_p (subdest, PATTERN (i3))
2163 1211721 : && REGNO (subdest) != FRAME_POINTER_REGNUM
2164 1211721 : && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2165 1211721 : || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2166 1211721 : && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2167 1211721 : || (REGNO (subdest) != ARG_POINTER_REGNUM
2168 0 : || ! fixed_regs [REGNO (subdest)]))
2169 47811318 : && REGNO (subdest) != STACK_POINTER_REGNUM)
2170 : {
2171 1174264 : if (*pi3dest_killed)
2172 : return false;
2173 :
2174 1151230 : *pi3dest_killed = subdest;
2175 : }
2176 : }
2177 :
2178 22626854 : else if (GET_CODE (x) == PARALLEL)
2179 : {
2180 : int i;
2181 :
2182 34442359 : for (i = 0; i < XVECLEN (x, 0); i++)
2183 23223404 : if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2184 : i1_not_in_src, i0_not_in_src, pi3dest_killed))
2185 : return false;
2186 : }
2187 :
2188 : return true;
2189 : }
2190 :
2191 : /* Return true if X is an arithmetic expression that contains a multiplication
2192 : and division. We don't count multiplications by powers of two here. */
2193 :
2194 : static bool
2195 17347030 : contains_muldiv (rtx x)
2196 : {
2197 18013367 : switch (GET_CODE (x))
2198 : {
2199 : case MOD: case DIV: case UMOD: case UDIV:
2200 : return true;
2201 :
2202 520931 : case MULT:
2203 520931 : return ! (CONST_INT_P (XEXP (x, 1))
2204 122759 : && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2205 17334198 : default:
2206 17334198 : if (BINARY_P (x))
2207 5938239 : return contains_muldiv (XEXP (x, 0))
2208 5938239 : || contains_muldiv (XEXP (x, 1));
2209 :
2210 11395959 : if (UNARY_P (x))
2211 666337 : return contains_muldiv (XEXP (x, 0));
2212 :
2213 : return false;
2214 : }
2215 : }
2216 :
2217 : /* Determine whether INSN can be used in a combination. Return true if
2218 : not. This is used in try_combine to detect early some cases where we
2219 : can't perform combinations. */
2220 :
2221 : static bool
2222 168725412 : cant_combine_insn_p (rtx_insn *insn)
2223 : {
2224 168725412 : rtx set;
2225 168725412 : rtx src, dest;
2226 :
2227 : /* If this isn't really an insn, we can't do anything.
2228 : This can occur when flow deletes an insn that it has merged into an
2229 : auto-increment address. */
2230 168725412 : if (!NONDEBUG_INSN_P (insn))
2231 : return true;
2232 :
2233 : /* Never combine loads and stores involving hard regs that are likely
2234 : to be spilled. The register allocator can usually handle such
2235 : reg-reg moves by tying. If we allow the combiner to make
2236 : substitutions of likely-spilled regs, reload might die.
2237 : As an exception, we allow combinations involving fixed regs; these are
2238 : not available to the register allocator so there's no risk involved. */
2239 :
2240 168725017 : set = single_set (insn);
2241 168725017 : if (! set)
2242 : return false;
2243 155241250 : src = SET_SRC (set);
2244 155241250 : dest = SET_DEST (set);
2245 155241250 : if (GET_CODE (src) == SUBREG)
2246 1148450 : src = SUBREG_REG (src);
2247 155241250 : if (GET_CODE (dest) == SUBREG)
2248 1724108 : dest = SUBREG_REG (dest);
2249 42157871 : if (REG_P (src) && REG_P (dest)
2250 190587968 : && ((HARD_REGISTER_P (src)
2251 6816611 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2252 : #ifdef LEAF_REGISTERS
2253 : && ! LEAF_REGISTERS [REGNO (src)])
2254 : #else
2255 : )
2256 : #endif
2257 28867638 : || (HARD_REGISTER_P (dest)
2258 20601377 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2259 20300276 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2260 25199333 : return true;
2261 :
2262 : return false;
2263 : }
2264 :
2265 : struct likely_spilled_retval_info
2266 : {
2267 : unsigned regno, nregs;
2268 : unsigned mask;
2269 : };
2270 :
2271 : /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2272 : hard registers that are known to be written to / clobbered in full. */
2273 : static void
2274 167005 : likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2275 : {
2276 167005 : struct likely_spilled_retval_info *const info =
2277 : (struct likely_spilled_retval_info *) data;
2278 167005 : unsigned regno, nregs;
2279 167005 : unsigned new_mask;
2280 :
2281 167005 : if (!REG_P (XEXP (set, 0)))
2282 : return;
2283 167005 : regno = REGNO (x);
2284 167005 : if (regno >= info->regno + info->nregs)
2285 : return;
2286 167005 : nregs = REG_NREGS (x);
2287 167005 : if (regno + nregs <= info->regno)
2288 : return;
2289 167005 : new_mask = (2U << (nregs - 1)) - 1;
2290 167005 : if (regno < info->regno)
2291 0 : new_mask >>= info->regno - regno;
2292 : else
2293 167005 : new_mask <<= regno - info->regno;
2294 167005 : info->mask &= ~new_mask;
2295 : }
2296 :
2297 : /* Return true iff part of the return value is live during INSN, and
2298 : it is likely spilled. This can happen when more than one insn is needed
2299 : to copy the return value, e.g. when we consider to combine into the
2300 : second copy insn for a complex value. */
2301 :
2302 : static bool
2303 47770117 : likely_spilled_retval_p (rtx_insn *insn)
2304 : {
2305 47770117 : rtx_insn *use = BB_END (this_basic_block);
2306 47770117 : rtx reg;
2307 47770117 : rtx_insn *p;
2308 47770117 : unsigned regno, nregs;
2309 : /* We assume here that no machine mode needs more than
2310 : 32 hard registers when the value overlaps with a register
2311 : for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2312 47770117 : unsigned mask;
2313 47770117 : struct likely_spilled_retval_info info;
2314 :
2315 47770117 : if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2316 : return false;
2317 3203457 : reg = XEXP (PATTERN (use), 0);
2318 3203457 : if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2319 : return false;
2320 3203457 : regno = REGNO (reg);
2321 3203457 : nregs = REG_NREGS (reg);
2322 3203457 : if (nregs == 1)
2323 : return false;
2324 164297 : mask = (2U << (nregs - 1)) - 1;
2325 :
2326 : /* Disregard parts of the return value that are set later. */
2327 164297 : info.regno = regno;
2328 164297 : info.nregs = nregs;
2329 164297 : info.mask = mask;
2330 558655 : for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2331 230061 : if (INSN_P (p))
2332 230061 : note_stores (p, likely_spilled_retval_1, &info);
2333 328582 : mask = info.mask;
2334 :
2335 : /* Check if any of the (probably) live return value registers is
2336 : likely spilled. */
2337 : nregs --;
2338 328582 : do
2339 : {
2340 328582 : if ((mask & 1 << nregs)
2341 328582 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2342 : return true;
2343 328560 : } while (nregs--);
2344 : return false;
2345 : }
2346 :
2347 : /* Adjust INSN after we made a change to its destination.
2348 :
2349 : Changing the destination can invalidate notes that say something about
2350 : the results of the insn and a LOG_LINK pointing to the insn. */
2351 :
2352 : static void
2353 17215 : adjust_for_new_dest (rtx_insn *insn)
2354 : {
2355 : /* For notes, be conservative and simply remove them. */
2356 17215 : remove_reg_equal_equiv_notes (insn, true);
2357 :
2358 : /* The new insn will have a destination that was previously the destination
2359 : of an insn just above it. Call distribute_links to make a LOG_LINK from
2360 : the next use of that destination. */
2361 :
2362 17215 : rtx set = single_set (insn);
2363 17215 : gcc_assert (set);
2364 :
2365 17215 : rtx reg = SET_DEST (set);
2366 :
2367 17215 : while (GET_CODE (reg) == ZERO_EXTRACT
2368 17215 : || GET_CODE (reg) == STRICT_LOW_PART
2369 34430 : || GET_CODE (reg) == SUBREG)
2370 0 : reg = XEXP (reg, 0);
2371 17215 : gcc_assert (REG_P (reg));
2372 :
2373 17215 : distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2374 :
2375 17215 : df_insn_rescan (insn);
2376 17215 : }
2377 :
2378 : /* Return TRUE if combine can reuse reg X in mode MODE.
2379 : ADDED_SETS is trueif the original set is still required. */
2380 : static bool
2381 2730303 : can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2382 : {
2383 2730303 : unsigned int regno;
2384 :
2385 2730303 : if (!REG_P (x))
2386 : return false;
2387 :
2388 : /* Don't change between modes with different underlying register sizes,
2389 : since this could lead to invalid subregs. */
2390 2730303 : if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2391 2730303 : REGMODE_NATURAL_SIZE (GET_MODE (x))))
2392 : return false;
2393 :
2394 2730303 : regno = REGNO (x);
2395 : /* Allow hard registers if the new mode is legal, and occupies no more
2396 : registers than the old mode. */
2397 2730303 : if (regno < FIRST_PSEUDO_REGISTER)
2398 1215742 : return (targetm.hard_regno_mode_ok (regno, mode)
2399 1215742 : && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2400 :
2401 : /* Or a pseudo that is only used once. */
2402 1514561 : return (regno < reg_n_sets_max
2403 1514529 : && REG_N_SETS (regno) == 1
2404 1465885 : && !added_sets
2405 2980446 : && !REG_USERVAR_P (x));
2406 : }
2407 :
2408 :
2409 : /* Check whether X, the destination of a set, refers to part of
2410 : the register specified by REG. */
2411 :
2412 : static bool
2413 17494 : reg_subword_p (rtx x, rtx reg)
2414 : {
2415 : /* Check that reg is an integer mode register. */
2416 17494 : if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2417 : return false;
2418 :
2419 16924 : if (GET_CODE (x) == STRICT_LOW_PART
2420 16495 : || GET_CODE (x) == ZERO_EXTRACT)
2421 453 : x = XEXP (x, 0);
2422 :
2423 16924 : return GET_CODE (x) == SUBREG
2424 16727 : && !paradoxical_subreg_p (x)
2425 16727 : && SUBREG_REG (x) == reg
2426 33651 : && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2427 : }
2428 :
2429 : /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2430 : by an arbitrary number of CLOBBERs. */
2431 : static bool
2432 102207872 : is_parallel_of_n_reg_sets (rtx pat, int n)
2433 : {
2434 102207872 : if (GET_CODE (pat) != PARALLEL)
2435 : return false;
2436 :
2437 27318208 : int len = XVECLEN (pat, 0);
2438 27318208 : if (len < n)
2439 : return false;
2440 :
2441 : int i;
2442 54342774 : for (i = 0; i < n; i++)
2443 51534521 : if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2444 30430786 : || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2445 : return false;
2446 3193597 : for ( ; i < len; i++)
2447 1002398 : switch (GET_CODE (XVECEXP (pat, 0, i)))
2448 : {
2449 385345 : case CLOBBER:
2450 385345 : if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2451 : return false;
2452 385344 : break;
2453 : default:
2454 : return false;
2455 : }
2456 : return true;
2457 : }
2458 :
2459 : /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2460 : CLOBBERs), can be split into individual SETs in that order, without
2461 : changing semantics. */
2462 : static bool
2463 362456 : can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2464 : {
2465 362456 : if (!insn_nothrow_p (insn))
2466 : return false;
2467 :
2468 360960 : rtx pat = PATTERN (insn);
2469 :
2470 360960 : int i, j;
2471 977656 : for (i = 0; i < n; i++)
2472 : {
2473 669308 : if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2474 : return false;
2475 :
2476 666196 : rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2477 :
2478 974544 : for (j = i + 1; j < n; j++)
2479 357848 : if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2480 : return false;
2481 : }
2482 :
2483 : return true;
2484 : }
2485 :
2486 : /* Return whether X is just a single_set, with the source
2487 : a general_operand. */
2488 : static bool
2489 67298528 : is_just_move (rtx_insn *x)
2490 : {
2491 67298528 : rtx set = single_set (x);
2492 67298528 : if (!set)
2493 : return false;
2494 :
2495 66886433 : return general_operand (SET_SRC (set), VOIDmode);
2496 : }
2497 :
2498 : /* Callback function to count autoincs. */
2499 :
2500 : static int
2501 1039220 : count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2502 : {
2503 1039220 : (*((int *) arg))++;
2504 :
2505 1039220 : return 0;
2506 : }
2507 :
2508 : /* Try to combine the insns I0, I1 and I2 into I3.
2509 : Here I0, I1 and I2 appear earlier than I3.
2510 : I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2511 : I3.
2512 :
2513 : If we are combining more than two insns and the resulting insn is not
2514 : recognized, try splitting it into two insns. If that happens, I2 and I3
2515 : are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2516 : Otherwise, I0, I1 and I2 are pseudo-deleted.
2517 :
2518 : Return 0 if the combination does not work. Then nothing is changed.
2519 : If we did the combination, return the insn at which combine should
2520 : resume scanning.
2521 :
2522 : Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2523 : new direct jump instruction.
2524 :
2525 : LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2526 : been I3 passed to an earlier try_combine within the same basic
2527 : block. */
2528 :
2529 : static rtx_insn *
2530 97214795 : try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2531 : bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2532 : {
2533 : /* New patterns for I3 and I2, respectively. */
2534 97214795 : rtx newpat, newi2pat = 0;
2535 97214795 : rtvec newpat_vec_with_clobbers = 0;
2536 97214795 : bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2537 : /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2538 : dead. */
2539 97214795 : bool added_sets_0, added_sets_1, added_sets_2;
2540 : /* Total number of SETs to put into I3. */
2541 97214795 : int total_sets;
2542 : /* Nonzero if I2's or I1's body now appears in I3. */
2543 97214795 : int i2_is_used = 0, i1_is_used = 0;
2544 : /* INSN_CODEs for new I3, new I2, and user of condition code. */
2545 97214795 : int insn_code_number, i2_code_number = 0, other_code_number = 0;
2546 : /* Contains I3 if the destination of I3 is used in its source, which means
2547 : that the old life of I3 is being killed. If that usage is placed into
2548 : I2 and not in I3, a REG_DEAD note must be made. */
2549 97214795 : rtx i3dest_killed = 0;
2550 : /* SET_DEST and SET_SRC of I2, I1 and I0. */
2551 97214795 : rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2552 : /* Copy of SET_SRC of I1 and I0, if needed. */
2553 97214795 : rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2554 : /* Set if I2DEST was reused as a scratch register. */
2555 97214795 : bool i2scratch = false;
2556 : /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2557 97214795 : rtx i0pat = 0, i1pat = 0, i2pat = 0;
2558 : /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2559 97214795 : bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2560 97214795 : bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2561 97214795 : bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2562 97214795 : bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2563 97214795 : bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2564 : /* Notes that must be added to REG_NOTES in I3 and I2. */
2565 97214795 : rtx new_i3_notes, new_i2_notes;
2566 : /* Notes that we substituted I3 into I2 instead of the normal case. */
2567 97214795 : bool i3_subst_into_i2 = false;
2568 : /* Notes that I1, I2 or I3 is a MULT operation. */
2569 97214795 : bool have_mult = false;
2570 97214795 : bool swap_i2i3 = false;
2571 97214795 : bool split_i2i3 = false;
2572 97214795 : bool changed_i3_dest = false;
2573 97214795 : bool i2_was_move = false, i3_was_move = false;
2574 97214795 : int n_auto_inc = 0;
2575 :
2576 97214795 : int maxreg;
2577 97214795 : rtx_insn *temp_insn;
2578 97214795 : rtx temp_expr;
2579 97214795 : struct insn_link *link;
2580 97214795 : rtx other_pat = 0;
2581 97214795 : rtx new_other_notes;
2582 97214795 : int i;
2583 97214795 : scalar_int_mode dest_mode, temp_mode;
2584 97214795 : bool has_non_call_exception = false;
2585 :
2586 : /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2587 : never be). */
2588 97214795 : if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2589 : return 0;
2590 :
2591 : /* Only try four-insn combinations when there's high likelihood of
2592 : success. Look for simple insns, such as loads of constants or
2593 : binary operations involving a constant. */
2594 22342417 : if (i0)
2595 : {
2596 22342417 : int i;
2597 22342417 : int ngood = 0;
2598 22342417 : int nshift = 0;
2599 22342417 : rtx set0, set3;
2600 :
2601 22342417 : if (!flag_expensive_optimizations)
2602 : return 0;
2603 :
2604 88163364 : for (i = 0; i < 4; i++)
2605 : {
2606 72123156 : rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2607 72123156 : rtx set = single_set (insn);
2608 72123156 : rtx src;
2609 72123156 : if (!set)
2610 2293475 : continue;
2611 69829681 : src = SET_SRC (set);
2612 69829681 : if (CONSTANT_P (src))
2613 : {
2614 4827623 : ngood += 2;
2615 4827623 : break;
2616 : }
2617 65002058 : else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2618 8368118 : ngood++;
2619 56633940 : else if (GET_CODE (src) == IF_THEN_ELSE)
2620 2133411 : ngood++;
2621 54500529 : else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2622 54404384 : || GET_CODE (src) == LSHIFTRT)
2623 126737 : nshift++;
2624 : }
2625 :
2626 : /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2627 : are likely manipulating its value. Ideally we'll be able to combine
2628 : all four insns into a bitfield insertion of some kind.
2629 :
2630 : Note the source in I0 might be inside a sign/zero extension and the
2631 : memory modes in I0 and I3 might be different. So extract the address
2632 : from the destination of I3 and search for it in the source of I0.
2633 :
2634 : In the event that there's a match but the source/dest do not actually
2635 : refer to the same memory, the worst that happens is we try some
2636 : combinations that we wouldn't have otherwise. */
2637 20867831 : if ((set0 = single_set (i0))
2638 : /* Ensure the source of SET0 is a MEM, possibly buried inside
2639 : an extension. */
2640 20740285 : && (GET_CODE (SET_SRC (set0)) == MEM
2641 17478301 : || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2642 17478301 : || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2643 548593 : && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2644 3375066 : && (set3 = single_set (i3))
2645 : /* Ensure the destination of SET3 is a MEM. */
2646 2927458 : && GET_CODE (SET_DEST (set3)) == MEM
2647 : /* Would it be better to extract the base address for the MEM
2648 : in SET3 and look for that? I don't have cases where it matters
2649 : but I could envision such cases. */
2650 21166948 : && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2651 21707 : ngood += 2;
2652 :
2653 20867831 : if (ngood < 2 && nshift < 2)
2654 : return 0;
2655 : }
2656 :
2657 : /* Exit early if one of the insns involved can't be used for
2658 : combinations. */
2659 81976921 : if (CALL_P (i2)
2660 76886183 : || (i1 && CALL_P (i1))
2661 73439968 : || (i0 && CALL_P (i0))
2662 72969845 : || cant_combine_insn_p (i3)
2663 69534165 : || cant_combine_insn_p (i2)
2664 53150272 : || (i1 && cant_combine_insn_p (i1))
2665 48005507 : || (i0 && cant_combine_insn_p (i0))
2666 129747038 : || likely_spilled_retval_p (i3))
2667 : return 0;
2668 :
2669 47770095 : combine_attempts++;
2670 47770095 : undobuf.other_insn = 0;
2671 :
2672 : /* Reset the hard register usage information. */
2673 47770095 : CLEAR_HARD_REG_SET (newpat_used_regs);
2674 :
2675 47770095 : if (dump_file && (dump_flags & TDF_DETAILS))
2676 : {
2677 174 : if (i0)
2678 20 : fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2679 20 : INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2680 154 : else if (i1)
2681 26 : fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2682 26 : INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2683 : else
2684 128 : fprintf (dump_file, "\nTrying %d -> %d:\n",
2685 128 : INSN_UID (i2), INSN_UID (i3));
2686 :
2687 174 : if (i0)
2688 20 : dump_insn_slim (dump_file, i0);
2689 174 : if (i1)
2690 46 : dump_insn_slim (dump_file, i1);
2691 174 : dump_insn_slim (dump_file, i2);
2692 174 : dump_insn_slim (dump_file, i3);
2693 : }
2694 :
2695 : /* If multiple insns feed into one of I2 or I3, they can be in any
2696 : order. To simplify the code below, reorder them in sequence. */
2697 47770095 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2698 : std::swap (i0, i2);
2699 47770095 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2700 : std::swap (i0, i1);
2701 47770095 : if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2702 : std::swap (i1, i2);
2703 :
2704 47770095 : added_links_insn = 0;
2705 47770095 : added_notes_insn = 0;
2706 :
2707 : /* First check for one important special case that the code below will
2708 : not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2709 : and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2710 : we may be able to replace that destination with the destination of I3.
2711 : This occurs in the common code where we compute both a quotient and
2712 : remainder into a structure, in which case we want to do the computation
2713 : directly into the structure to avoid register-register copies.
2714 :
2715 : Note that this case handles both multiple sets in I2 and also cases
2716 : where I2 has a number of CLOBBERs inside the PARALLEL.
2717 :
2718 : We make very conservative checks below and only try to handle the
2719 : most common cases of this. For example, we only handle the case
2720 : where I2 and I3 are adjacent to avoid making difficult register
2721 : usage tests. */
2722 :
2723 29865525 : if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2724 15532304 : && REG_P (SET_SRC (PATTERN (i3)))
2725 5252478 : && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2726 5011122 : && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2727 4100419 : && GET_CODE (PATTERN (i2)) == PARALLEL
2728 1102117 : && ! side_effects_p (SET_DEST (PATTERN (i3)))
2729 : /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2730 : below would need to check what is inside (and reg_overlap_mentioned_p
2731 : doesn't support those codes anyway). Don't allow those destinations;
2732 : the resulting insn isn't likely to be recognized anyway. */
2733 610101 : && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2734 610081 : && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2735 608889 : && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2736 608889 : SET_DEST (PATTERN (i3)))
2737 48378841 : && next_active_insn (i2) == i3)
2738 : {
2739 398383 : rtx p2 = PATTERN (i2);
2740 :
2741 : /* Make sure that the destination of I3,
2742 : which we are going to substitute into one output of I2,
2743 : is not used within another output of I2. We must avoid making this:
2744 : (parallel [(set (mem (reg 69)) ...)
2745 : (set (reg 69) ...)])
2746 : which is not well-defined as to order of actions.
2747 : (Besides, reload can't handle output reloads for this.)
2748 :
2749 : The problem can also happen if the dest of I3 is a memory ref,
2750 : if another dest in I2 is an indirect memory ref.
2751 :
2752 : Neither can this PARALLEL be an asm. We do not allow combining
2753 : that usually (see can_combine_p), so do not here either. */
2754 398383 : bool ok = true;
2755 1207674 : for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2756 : {
2757 809291 : if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2758 398038 : || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2759 1617172 : && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2760 807881 : SET_DEST (XVECEXP (p2, 0, i))))
2761 : ok = false;
2762 808506 : else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2763 410470 : && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2764 809291 : ok = false;
2765 : }
2766 :
2767 398383 : if (ok)
2768 519700 : for (i = 0; i < XVECLEN (p2, 0); i++)
2769 459770 : if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2770 459770 : && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2771 : {
2772 336532 : combine_merges++;
2773 :
2774 336532 : subst_insn = i3;
2775 336532 : subst_low_luid = DF_INSN_LUID (i2);
2776 :
2777 336532 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2778 336532 : i2src = SET_SRC (XVECEXP (p2, 0, i));
2779 336532 : i2dest = SET_DEST (XVECEXP (p2, 0, i));
2780 336532 : i2dest_killed = dead_or_set_p (i2, i2dest);
2781 :
2782 : /* Replace the dest in I2 with our dest and make the resulting
2783 : insn the new pattern for I3. Then skip to where we validate
2784 : the pattern. Everything was set up above. */
2785 336532 : SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2786 336532 : newpat = p2;
2787 336532 : i3_subst_into_i2 = true;
2788 336532 : goto validate_replacement;
2789 : }
2790 : }
2791 :
2792 : /* If I2 is setting a pseudo to a constant and I3 is setting some
2793 : sub-part of it to another constant, merge them by making a new
2794 : constant. */
2795 47433563 : if (i1 == 0
2796 29528993 : && (temp_expr = single_set (i2)) != 0
2797 29252521 : && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2798 19263914 : && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2799 2862591 : && GET_CODE (PATTERN (i3)) == SET
2800 1415119 : && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2801 47451057 : && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2802 : {
2803 16727 : rtx dest = SET_DEST (PATTERN (i3));
2804 16727 : rtx temp_dest = SET_DEST (temp_expr);
2805 16727 : int offset = -1;
2806 16727 : int width = 0;
2807 :
2808 16727 : if (GET_CODE (dest) == ZERO_EXTRACT)
2809 : {
2810 1 : if (CONST_INT_P (XEXP (dest, 1))
2811 1 : && CONST_INT_P (XEXP (dest, 2))
2812 2 : && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2813 : &dest_mode))
2814 : {
2815 1 : width = INTVAL (XEXP (dest, 1));
2816 1 : offset = INTVAL (XEXP (dest, 2));
2817 1 : dest = XEXP (dest, 0);
2818 1 : if (BITS_BIG_ENDIAN)
2819 : offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2820 : }
2821 : }
2822 : else
2823 : {
2824 16726 : if (GET_CODE (dest) == STRICT_LOW_PART)
2825 429 : dest = XEXP (dest, 0);
2826 16726 : if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2827 : {
2828 16726 : width = GET_MODE_PRECISION (dest_mode);
2829 16726 : offset = 0;
2830 : }
2831 : }
2832 :
2833 16727 : if (offset >= 0)
2834 : {
2835 : /* If this is the low part, we're done. */
2836 16727 : if (subreg_lowpart_p (dest))
2837 : ;
2838 : /* Handle the case where inner is twice the size of outer. */
2839 5008 : else if (GET_MODE_PRECISION (temp_mode)
2840 5008 : == 2 * GET_MODE_PRECISION (dest_mode))
2841 5005 : offset += GET_MODE_PRECISION (dest_mode);
2842 : /* Otherwise give up for now. */
2843 : else
2844 : offset = -1;
2845 : }
2846 :
2847 16724 : if (offset >= 0)
2848 : {
2849 16724 : rtx inner = SET_SRC (PATTERN (i3));
2850 16724 : rtx outer = SET_SRC (temp_expr);
2851 :
2852 33448 : wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2853 16724 : rtx_mode_t (inner, dest_mode),
2854 33448 : offset, width);
2855 :
2856 16724 : combine_merges++;
2857 16724 : subst_insn = i3;
2858 16724 : subst_low_luid = DF_INSN_LUID (i2);
2859 16724 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2860 16724 : i2dest = temp_dest;
2861 16724 : i2dest_killed = dead_or_set_p (i2, i2dest);
2862 :
2863 : /* Replace the source in I2 with the new constant and make the
2864 : resulting insn the new pattern for I3. Then skip to where we
2865 : validate the pattern. Everything was set up above. */
2866 16724 : SUBST (SET_SRC (temp_expr),
2867 : immed_wide_int_const (o, temp_mode));
2868 :
2869 16724 : newpat = PATTERN (i2);
2870 :
2871 : /* The dest of I3 has been replaced with the dest of I2. */
2872 16724 : changed_i3_dest = true;
2873 16724 : goto validate_replacement;
2874 16724 : }
2875 : }
2876 :
2877 : /* If we have no I1 and I2 looks like:
2878 : (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2879 : (set Y OP)])
2880 : make up a dummy I1 that is
2881 : (set Y OP)
2882 : and change I2 to be
2883 : (set (reg:CC X) (compare:CC Y (const_int 0)))
2884 :
2885 : (We can ignore any trailing CLOBBERs.)
2886 :
2887 : This undoes a previous combination and allows us to match a branch-and-
2888 : decrement insn. */
2889 :
2890 47416839 : if (i1 == 0
2891 29512269 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2892 233143 : && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2893 : == MODE_CC)
2894 141148 : && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2895 114598 : && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2896 77241 : && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2897 77241 : SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2898 72001 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2899 47488840 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2900 : {
2901 : /* We make I1 with the same INSN_UID as I2. This gives it
2902 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2903 : never appear in the insn stream so giving it the same INSN_UID
2904 : as I2 will not cause a problem. */
2905 :
2906 143566 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2907 71783 : XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2908 : -1, NULL_RTX);
2909 71783 : INSN_UID (i1) = INSN_UID (i2);
2910 :
2911 71783 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2912 71783 : SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2913 : SET_DEST (PATTERN (i1)));
2914 71783 : unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2915 71783 : SUBST_LINK (LOG_LINKS (i2),
2916 : alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2917 : }
2918 :
2919 : /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2920 : make those two SETs separate I1 and I2 insns, and make an I0 that is
2921 : the original I1. */
2922 47416839 : if (i0 == 0
2923 44715562 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2924 362456 : && can_split_parallel_of_n_reg_sets (i2, 2)
2925 308348 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2926 278046 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2927 261606 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2928 47678436 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2929 : {
2930 : /* If there is no I1, there is no I0 either. */
2931 261597 : i0 = i1;
2932 :
2933 : /* We make I1 with the same INSN_UID as I2. This gives it
2934 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2935 : never appear in the insn stream so giving it the same INSN_UID
2936 : as I2 will not cause a problem. */
2937 :
2938 523194 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2939 261597 : XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2940 : -1, NULL_RTX);
2941 261597 : INSN_UID (i1) = INSN_UID (i2);
2942 :
2943 261597 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2944 : }
2945 :
2946 : /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2947 47416839 : if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2948 : {
2949 12126036 : if (dump_file && (dump_flags & TDF_DETAILS))
2950 8 : fprintf (dump_file, "Can't combine i2 into i3\n");
2951 12126036 : undo_all ();
2952 12126036 : return 0;
2953 : }
2954 35290803 : if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2955 : {
2956 1399041 : if (dump_file && (dump_flags & TDF_DETAILS))
2957 0 : fprintf (dump_file, "Can't combine i1 into i3\n");
2958 1399041 : undo_all ();
2959 1399041 : return 0;
2960 : }
2961 33891762 : if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2962 : {
2963 242326 : if (dump_file && (dump_flags & TDF_DETAILS))
2964 0 : fprintf (dump_file, "Can't combine i0 into i3\n");
2965 242326 : undo_all ();
2966 242326 : return 0;
2967 : }
2968 :
2969 : /* With non-call exceptions we can end up trying to combine multiple
2970 : insns with possible EH side effects. Make sure we can combine
2971 : that to a single insn which means there must be at most one insn
2972 : in the combination with an EH side effect. */
2973 33649436 : if (cfun->can_throw_non_call_exceptions)
2974 : {
2975 6088437 : if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2976 6064796 : || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2977 6064714 : || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2978 12153150 : || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2979 : {
2980 23724 : has_non_call_exception = true;
2981 23724 : if (insn_could_throw_p (i3)
2982 23724 : + insn_could_throw_p (i2)
2983 23724 : + (i1 ? insn_could_throw_p (i1) : 0)
2984 23724 : + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2985 : {
2986 172 : if (dump_file && (dump_flags & TDF_DETAILS))
2987 0 : fprintf (dump_file, "Can't combine multiple insns with EH "
2988 : "side-effects\n");
2989 172 : undo_all ();
2990 172 : return 0;
2991 : }
2992 : }
2993 : }
2994 :
2995 : /* Record whether i2 and i3 are trivial moves. */
2996 33649264 : i2_was_move = is_just_move (i2);
2997 33649264 : i3_was_move = is_just_move (i3);
2998 :
2999 : /* Record whether I2DEST is used in I2SRC and similarly for the other
3000 : cases. Knowing this will help in register status updating below. */
3001 33649264 : i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
3002 33649264 : i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3003 10793339 : i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3004 33649264 : i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3005 1930779 : i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3006 1930779 : i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3007 33649264 : i2dest_killed = dead_or_set_p (i2, i2dest);
3008 33649264 : i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3009 33649264 : i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3010 :
3011 : /* For the earlier insns, determine which of the subsequent ones they
3012 : feed. */
3013 33649264 : i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3014 33649264 : i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3015 3372264 : i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3016 1441485 : : (!reg_overlap_mentioned_p (i1dest, i0dest)
3017 1416170 : && reg_overlap_mentioned_p (i0dest, i2src))));
3018 :
3019 : /* Ensure that I3's pattern can be the destination of combines. */
3020 44442603 : if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3021 10793339 : i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3022 1930779 : i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3023 1902062 : || (i1dest_in_i0src && !i0_feeds_i1_n)),
3024 : &i3dest_killed))
3025 : {
3026 191022 : undo_all ();
3027 191022 : return 0;
3028 : }
3029 :
3030 : /* See if any of the insns is a MULT operation. Unless one is, we will
3031 : reject a combination that is, since it must be slower. Be conservative
3032 : here. */
3033 33458242 : if (GET_CODE (i2src) == MULT
3034 32604905 : || (i1 != 0 && GET_CODE (i1src) == MULT)
3035 32266179 : || (i0 != 0 && GET_CODE (i0src) == MULT)
3036 65678512 : || (GET_CODE (PATTERN (i3)) == SET
3037 25224305 : && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3038 : have_mult = true;
3039 :
3040 : /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3041 : We used to do this EXCEPT in one case: I3 has a post-inc in an
3042 : output operand. However, that exception can give rise to insns like
3043 : mov r3,(r3)+
3044 : which is a famous insn on the PDP-11 where the value of r3 used as the
3045 : source was model-dependent. Avoid this sort of thing. */
3046 :
3047 : #if 0
3048 : if (!(GET_CODE (PATTERN (i3)) == SET
3049 : && REG_P (SET_SRC (PATTERN (i3)))
3050 : && MEM_P (SET_DEST (PATTERN (i3)))
3051 : && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3052 : || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3053 : /* It's not the exception. */
3054 : #endif
3055 33458242 : if (AUTO_INC_DEC)
3056 : {
3057 : rtx link;
3058 : for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3059 : if (REG_NOTE_KIND (link) == REG_INC
3060 : && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3061 : || (i1 != 0
3062 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3063 : {
3064 : undo_all ();
3065 : return 0;
3066 : }
3067 : }
3068 :
3069 : /* See if the SETs in I1 or I2 need to be kept around in the merged
3070 : instruction: whenever the value set there is still needed past I3.
3071 : For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3072 :
3073 : For the SET in I1, we have two cases: if I1 and I2 independently feed
3074 : into I3, the set in I1 needs to be kept around unless I1DEST dies
3075 : or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3076 : in I1 needs to be kept around unless I1DEST dies or is set in either
3077 : I2 or I3. The same considerations apply to I0. */
3078 :
3079 33458242 : added_sets_2 = !dead_or_set_p (i3, i2dest);
3080 :
3081 33458242 : if (i1)
3082 10726897 : added_sets_1 = !(dead_or_set_p (i3, i1dest)
3083 8235874 : || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3084 : else
3085 : added_sets_1 = false;
3086 :
3087 33458242 : if (i0)
3088 2794873 : added_sets_0 = !(dead_or_set_p (i3, i0dest)
3089 1725611 : || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3090 353284 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3091 836640 : && dead_or_set_p (i2, i0dest)));
3092 : else
3093 : added_sets_0 = false;
3094 :
3095 : /* We are about to copy insns for the case where they need to be kept
3096 : around. Check that they can be copied in the merged instruction. */
3097 :
3098 33458242 : if (targetm.cannot_copy_insn_p
3099 33458242 : && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3100 0 : || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3101 0 : || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3102 : {
3103 0 : undo_all ();
3104 0 : return 0;
3105 : }
3106 :
3107 : /* We cannot safely duplicate volatile references in any case. */
3108 :
3109 7498604 : if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3110 33421961 : || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3111 66851901 : || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3112 : {
3113 66815 : undo_all ();
3114 66815 : return 0;
3115 : }
3116 :
3117 : /* Count how many auto_inc expressions there were in the original insns;
3118 : we need to have the same number in the resulting patterns. */
3119 :
3120 33391427 : if (i0)
3121 1889874 : for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3122 33391427 : if (i1)
3123 10694877 : for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3124 33391427 : for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3125 33391427 : for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3126 :
3127 : /* If the set in I2 needs to be kept around, we must make a copy of
3128 : PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3129 : PATTERN (I2), we are only substituting for the original I1DEST, not into
3130 : an already-substituted copy. This also prevents making self-referential
3131 : rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3132 : I2DEST. */
3133 :
3134 33391427 : if (added_sets_2)
3135 : {
3136 7459431 : if (GET_CODE (PATTERN (i2)) == PARALLEL)
3137 2324167 : i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3138 : else
3139 5135264 : i2pat = copy_rtx (PATTERN (i2));
3140 : }
3141 :
3142 33391427 : if (added_sets_1)
3143 : {
3144 4033573 : if (GET_CODE (PATTERN (i1)) == PARALLEL)
3145 1282232 : i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3146 : else
3147 2751341 : i1pat = copy_rtx (PATTERN (i1));
3148 : }
3149 :
3150 33391427 : if (added_sets_0)
3151 : {
3152 523757 : if (GET_CODE (PATTERN (i0)) == PARALLEL)
3153 197240 : i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3154 : else
3155 326517 : i0pat = copy_rtx (PATTERN (i0));
3156 : }
3157 :
3158 33391427 : combine_merges++;
3159 :
3160 : /* Substitute in the latest insn for the regs set by the earlier ones. */
3161 :
3162 33391427 : maxreg = max_reg_num ();
3163 :
3164 33391427 : subst_insn = i3;
3165 :
3166 : /* Many machines have insns that can both perform an
3167 : arithmetic operation and set the condition code. These operations will
3168 : be represented as a PARALLEL with the first element of the vector
3169 : being a COMPARE of an arithmetic operation with the constant zero.
3170 : The second element of the vector will set some pseudo to the result
3171 : of the same arithmetic operation. If we simplify the COMPARE, we won't
3172 : match such a pattern and so will generate an extra insn. Here we test
3173 : for this case, where both the comparison and the operation result are
3174 : needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3175 : I2SRC. Later we will make the PARALLEL that contains I2. */
3176 :
3177 22696550 : if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3178 4304200 : && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3179 1826588 : && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3180 34282706 : && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3181 : {
3182 821174 : rtx newpat_dest;
3183 821174 : rtx *cc_use_loc = NULL;
3184 821174 : rtx_insn *cc_use_insn = NULL;
3185 821174 : rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3186 821174 : machine_mode compare_mode, orig_compare_mode;
3187 821174 : enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3188 821174 : scalar_int_mode mode;
3189 :
3190 821174 : newpat = PATTERN (i3);
3191 821174 : newpat_dest = SET_DEST (newpat);
3192 821174 : compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3193 :
3194 821174 : if (undobuf.other_insn == 0
3195 821174 : && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3196 : &cc_use_insn)))
3197 : {
3198 814789 : compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3199 814789 : if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3200 814789 : compare_code = simplify_compare_const (compare_code, mode,
3201 : &op0, &op1);
3202 814789 : target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3203 : }
3204 :
3205 : /* Do the rest only if op1 is const0_rtx, which may be the
3206 : result of simplification. */
3207 821174 : if (op1 == const0_rtx)
3208 : {
3209 : /* If a single use of the CC is found, prepare to modify it
3210 : when SELECT_CC_MODE returns a new CC-class mode, or when
3211 : the above simplify_compare_const() returned a new comparison
3212 : operator. undobuf.other_insn is assigned the CC use insn
3213 : when modifying it. */
3214 515442 : if (cc_use_loc)
3215 : {
3216 : #ifdef SELECT_CC_MODE
3217 512765 : machine_mode new_mode
3218 512765 : = SELECT_CC_MODE (compare_code, op0, op1);
3219 512765 : if (new_mode != orig_compare_mode
3220 512765 : && can_change_dest_mode (SET_DEST (newpat),
3221 : added_sets_2, new_mode))
3222 : {
3223 477 : unsigned int regno = REGNO (newpat_dest);
3224 477 : compare_mode = new_mode;
3225 477 : if (regno < FIRST_PSEUDO_REGISTER)
3226 477 : newpat_dest = gen_rtx_REG (compare_mode, regno);
3227 : else
3228 : {
3229 0 : subst_mode (regno, compare_mode);
3230 0 : newpat_dest = regno_reg_rtx[regno];
3231 : }
3232 : }
3233 : #endif
3234 : /* Cases for modifying the CC-using comparison. */
3235 512765 : if (compare_code != orig_compare_code
3236 501 : && COMPARISON_P (*cc_use_loc))
3237 : {
3238 : /* Replace cc_use_loc with entire new RTX. */
3239 501 : SUBST (*cc_use_loc,
3240 : gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3241 : newpat_dest, const0_rtx));
3242 501 : undobuf.other_insn = cc_use_insn;
3243 : }
3244 512264 : else if (compare_mode != orig_compare_mode)
3245 : {
3246 1 : subrtx_ptr_iterator::array_type array;
3247 :
3248 : /* Just replace the CC reg with a new mode. */
3249 4 : FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3250 : {
3251 3 : rtx *loc = *iter;
3252 3 : if (REG_P (*loc)
3253 3 : && REGNO (*loc) == REGNO (newpat_dest))
3254 : {
3255 1 : SUBST (*loc, newpat_dest);
3256 1 : iter.skip_subrtxes ();
3257 : }
3258 : }
3259 1 : undobuf.other_insn = cc_use_insn;
3260 1 : }
3261 : }
3262 :
3263 : /* Now we modify the current newpat:
3264 : First, SET_DEST(newpat) is updated if the CC mode has been
3265 : altered. For targets without SELECT_CC_MODE, this should be
3266 : optimized away. */
3267 515442 : if (compare_mode != orig_compare_mode)
3268 477 : SUBST (SET_DEST (newpat), newpat_dest);
3269 : /* This is always done to propagate i2src into newpat. */
3270 515442 : SUBST (SET_SRC (newpat),
3271 : gen_rtx_COMPARE (compare_mode, op0, op1));
3272 : /* Create new version of i2pat if needed; the below PARALLEL
3273 : creation needs this to work correctly. */
3274 515442 : if (! rtx_equal_p (i2src, op0))
3275 27 : i2pat = gen_rtx_SET (i2dest, op0);
3276 : i2_is_used = 1;
3277 : }
3278 : }
3279 :
3280 821174 : if (i2_is_used == 0)
3281 : {
3282 : /* It is possible that the source of I2 or I1 may be performing
3283 : an unneeded operation, such as a ZERO_EXTEND of something
3284 : that is known to have the high part zero. Handle that case
3285 : by letting subst look at the inner insns.
3286 :
3287 : Another way to do this would be to have a function that tries
3288 : to simplify a single insn instead of merging two or more
3289 : insns. We don't do this because of the potential of infinite
3290 : loops and because of the potential extra memory required.
3291 : However, doing it the way we are is a bit of a kludge and
3292 : doesn't catch all cases.
3293 :
3294 : But only do this if -fexpensive-optimizations since it slows
3295 : things down and doesn't usually win.
3296 :
3297 : This is not done in the COMPARE case above because the
3298 : unmodified I2PAT is used in the PARALLEL and so a pattern
3299 : with a modified I2SRC would not match. */
3300 :
3301 32875985 : if (flag_expensive_optimizations)
3302 : {
3303 : /* Pass pc_rtx so no substitutions are done, just
3304 : simplifications. */
3305 30631274 : if (i1)
3306 : {
3307 10029519 : subst_low_luid = DF_INSN_LUID (i1);
3308 10029519 : i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3309 : }
3310 :
3311 30631274 : subst_low_luid = DF_INSN_LUID (i2);
3312 30631274 : i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3313 : }
3314 :
3315 32875985 : n_occurrences = 0; /* `subst' counts here */
3316 32875985 : subst_low_luid = DF_INSN_LUID (i2);
3317 :
3318 : /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3319 : copy of I2SRC each time we substitute it, in order to avoid creating
3320 : self-referential RTL when we will be substituting I1SRC for I1DEST
3321 : later. Likewise if I0 feeds into I2, either directly or indirectly
3322 : through I1, and I0DEST is in I0SRC. */
3323 65148886 : newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3324 32875985 : (i1_feeds_i2_n && i1dest_in_i1src)
3325 31680478 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3326 : && i0dest_in_i0src));
3327 32875985 : substed_i2 = true;
3328 :
3329 : /* Record whether I2's body now appears within I3's body. */
3330 32875985 : i2_is_used = n_occurrences;
3331 : }
3332 :
3333 : /* If we already got a failure, don't try to do more. Otherwise, try to
3334 : substitute I1 if we have it. */
3335 :
3336 33391427 : if (i1 && GET_CODE (newpat) != CLOBBER)
3337 : {
3338 : /* Before we can do this substitution, we must redo the test done
3339 : above (see detailed comments there) that ensures I1DEST isn't
3340 : mentioned in any SETs in NEWPAT that are field assignments. */
3341 10650782 : if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3342 : false, false, 0))
3343 : {
3344 22 : undo_all ();
3345 22 : return 0;
3346 : }
3347 :
3348 10650760 : n_occurrences = 0;
3349 10650760 : subst_low_luid = DF_INSN_LUID (i1);
3350 :
3351 : /* If the following substitution will modify I1SRC, make a copy of it
3352 : for the case where it is substituted for I1DEST in I2PAT later. */
3353 10650760 : if (added_sets_2 && i1_feeds_i2_n)
3354 1502251 : i1src_copy = copy_rtx (i1src);
3355 :
3356 : /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3357 : copy of I1SRC each time we substitute it, in order to avoid creating
3358 : self-referential RTL when we will be substituting I0SRC for I0DEST
3359 : later. */
3360 10650760 : newpat = subst (newpat, i1dest, i1src, false, false,
3361 : i0_feeds_i1_n && i0dest_in_i0src);
3362 10650760 : substed_i1 = true;
3363 :
3364 : /* Record whether I1's body now appears within I3's body. */
3365 10650760 : i1_is_used = n_occurrences;
3366 : }
3367 :
3368 : /* Likewise for I0 if we have it. */
3369 :
3370 33391405 : if (i0 && GET_CODE (newpat) != CLOBBER)
3371 : {
3372 1871013 : if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3373 : false, false, 0))
3374 : {
3375 2 : undo_all ();
3376 2 : return 0;
3377 : }
3378 :
3379 : /* If the following substitution will modify I0SRC, make a copy of it
3380 : for the case where it is substituted for I0DEST in I1PAT later. */
3381 1871011 : if (added_sets_1 && i0_feeds_i1_n)
3382 364399 : i0src_copy = copy_rtx (i0src);
3383 : /* And a copy for I0DEST in I2PAT substitution. */
3384 1871011 : if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3385 212959 : || (i0_feeds_i2_n)))
3386 339661 : i0src_copy2 = copy_rtx (i0src);
3387 :
3388 1871011 : n_occurrences = 0;
3389 1871011 : subst_low_luid = DF_INSN_LUID (i0);
3390 1871011 : newpat = subst (newpat, i0dest, i0src, false, false, false);
3391 1871011 : substed_i0 = true;
3392 : }
3393 :
3394 33391403 : if (n_auto_inc)
3395 : {
3396 520153 : int new_n_auto_inc = 0;
3397 520153 : for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3398 :
3399 520153 : if (n_auto_inc != new_n_auto_inc)
3400 : {
3401 1088 : if (dump_file && (dump_flags & TDF_DETAILS))
3402 0 : fprintf (dump_file, "Number of auto_inc expressions changed\n");
3403 1088 : undo_all ();
3404 1088 : return 0;
3405 : }
3406 : }
3407 :
3408 : /* Fail if an autoincrement side-effect has been duplicated. Be careful
3409 : to count all the ways that I2SRC and I1SRC can be used. */
3410 33390315 : if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3411 : && i2_is_used + added_sets_2 > 1)
3412 : || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3413 : && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3414 : || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3415 : && (n_occurrences + added_sets_0
3416 : + (added_sets_1 && i0_feeds_i1_n)
3417 : + (added_sets_2 && i0_feeds_i2_n) > 1))
3418 : /* Fail if we tried to make a new register. */
3419 33390315 : || max_reg_num () != maxreg
3420 : /* Fail if we couldn't do something and have a CLOBBER. */
3421 33390315 : || GET_CODE (newpat) == CLOBBER
3422 : /* Fail if this new pattern is a MULT and we didn't have one before
3423 : at the outer level. */
3424 66423690 : || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3425 305843 : && ! have_mult))
3426 : {
3427 385418 : undo_all ();
3428 385418 : return 0;
3429 : }
3430 :
3431 : /* If the actions of the earlier insns must be kept
3432 : in addition to substituting them into the latest one,
3433 : we must make a new PARALLEL for the latest insn
3434 : to hold additional the SETs. */
3435 :
3436 33004897 : if (added_sets_0 || added_sets_1 || added_sets_2)
3437 : {
3438 10943950 : int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3439 10943950 : combine_extras++;
3440 :
3441 10943950 : if (GET_CODE (newpat) == PARALLEL)
3442 : {
3443 2211711 : rtvec old = XVEC (newpat, 0);
3444 2211711 : total_sets = XVECLEN (newpat, 0) + extra_sets;
3445 2211711 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3446 2211711 : memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3447 2211711 : sizeof (old->elem[0]) * old->num_elem);
3448 : }
3449 : else
3450 : {
3451 8732239 : rtx old = newpat;
3452 8732239 : total_sets = 1 + extra_sets;
3453 8732239 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3454 8732239 : XVECEXP (newpat, 0, 0) = old;
3455 : }
3456 :
3457 10943950 : if (added_sets_0)
3458 504687 : XVECEXP (newpat, 0, --total_sets) = i0pat;
3459 :
3460 10943950 : if (added_sets_1)
3461 : {
3462 3982144 : rtx t = i1pat;
3463 3982144 : if (i0_feeds_i1_n)
3464 361476 : t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3465 : false, false, false);
3466 :
3467 3982144 : XVECEXP (newpat, 0, --total_sets) = t;
3468 : }
3469 10943950 : if (added_sets_2)
3470 : {
3471 7381660 : rtx t = i2pat;
3472 7381660 : if (i1_feeds_i2_n)
3473 1484267 : t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3474 : i0_feeds_i1_n && i0dest_in_i0src);
3475 7381660 : if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3476 335425 : t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3477 : false, false, false);
3478 :
3479 7381660 : XVECEXP (newpat, 0, --total_sets) = t;
3480 : }
3481 : }
3482 :
3483 25623237 : validate_replacement:
3484 :
3485 : /* Note which hard regs this insn has as inputs. */
3486 33358153 : mark_used_regs_combine (newpat);
3487 :
3488 : /* If recog_for_combine fails, it strips existing clobbers. If we'll
3489 : consider splitting this pattern, we might need these clobbers. */
3490 33358153 : if (i1 && GET_CODE (newpat) == PARALLEL
3491 7361049 : && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3492 : {
3493 1727988 : int len = XVECLEN (newpat, 0);
3494 :
3495 1727988 : newpat_vec_with_clobbers = rtvec_alloc (len);
3496 6961825 : for (i = 0; i < len; i++)
3497 3505849 : RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3498 : }
3499 :
3500 : /* We have recognized nothing yet. */
3501 33358153 : insn_code_number = -1;
3502 :
3503 : /* See if this is a PARALLEL of two SETs where one SET's destination is
3504 : a register that is unused and this isn't marked as an instruction that
3505 : might trap in an EH region. In that case, we just need the other SET.
3506 : We prefer this over the PARALLEL.
3507 :
3508 : This can occur when simplifying a divmod insn. We *must* test for this
3509 : case here because the code below that splits two independent SETs doesn't
3510 : handle this case correctly when it updates the register status.
3511 :
3512 : It's pointless doing this if we originally had two sets, one from
3513 : i3, and one from i2. Combining then splitting the parallel results
3514 : in the original i2 again plus an invalid insn (which we delete).
3515 : The net effect is only to move instructions around, which makes
3516 : debug info less accurate.
3517 :
3518 : If the remaining SET came from I2 its destination should not be used
3519 : between I2 and I3. See PR82024. */
3520 :
3521 7381660 : if (!(added_sets_2 && i1 == 0)
3522 27980041 : && is_parallel_of_n_reg_sets (newpat, 2)
3523 34953753 : && asm_noperands (newpat) < 0)
3524 : {
3525 1594706 : rtx set0 = XVECEXP (newpat, 0, 0);
3526 1594706 : rtx set1 = XVECEXP (newpat, 0, 1);
3527 1594706 : rtx oldpat = newpat;
3528 :
3529 1594706 : if (((REG_P (SET_DEST (set1))
3530 1594706 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3531 1553814 : || (GET_CODE (SET_DEST (set1)) == SUBREG
3532 0 : && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3533 40892 : && insn_nothrow_p (i3)
3534 1634366 : && !side_effects_p (SET_SRC (set1)))
3535 : {
3536 39393 : newpat = set0;
3537 39393 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3538 : }
3539 :
3540 1555313 : else if (((REG_P (SET_DEST (set0))
3541 1555313 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3542 1530212 : || (GET_CODE (SET_DEST (set0)) == SUBREG
3543 0 : && find_reg_note (i3, REG_UNUSED,
3544 0 : SUBREG_REG (SET_DEST (set0)))))
3545 25101 : && insn_nothrow_p (i3)
3546 1579810 : && !side_effects_p (SET_SRC (set0)))
3547 : {
3548 24454 : rtx dest = SET_DEST (set1);
3549 24454 : if (GET_CODE (dest) == SUBREG)
3550 0 : dest = SUBREG_REG (dest);
3551 24454 : if (!reg_used_between_p (dest, i2, i3))
3552 : {
3553 24453 : newpat = set1;
3554 24453 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3555 :
3556 24453 : if (insn_code_number >= 0)
3557 : changed_i3_dest = true;
3558 : }
3559 : }
3560 :
3561 39393 : if (insn_code_number < 0)
3562 1589116 : newpat = oldpat;
3563 : }
3564 :
3565 : /* Is the result of combination a valid instruction? */
3566 1589116 : if (insn_code_number < 0)
3567 33352563 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3568 :
3569 : /* If we were combining three insns and the result is a simple SET
3570 : with no ASM_OPERANDS that wasn't recognized, try to split it into two
3571 : insns. There are two ways to do this. It can be split using a
3572 : machine-specific method (like when you have an addition of a large
3573 : constant) or by combine in the function find_split_point. */
3574 :
3575 10492947 : if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3576 38131580 : && asm_noperands (newpat) < 0)
3577 : {
3578 4772950 : rtx parallel, *split;
3579 4772950 : rtx_insn *m_split_insn;
3580 4772950 : unsigned int old_nregs, new_nregs;
3581 :
3582 : /* See if the MD file can split NEWPAT. If it can't, see if letting it
3583 : use I2DEST as a scratch register will help. In the latter case,
3584 : convert I2DEST to the mode of the source of NEWPAT if we can. */
3585 :
3586 4772950 : m_split_insn = combine_split_insns (newpat, i3, &old_nregs, &new_nregs);
3587 :
3588 : /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3589 : inputs of NEWPAT. */
3590 :
3591 : /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3592 : possible to try that as a scratch reg. This would require adding
3593 : more code to make it work though. */
3594 :
3595 4772950 : if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3596 : {
3597 4635509 : machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3598 :
3599 : /* ??? Reusing i2dest without resetting the reg_stat entry for it
3600 : (temporarily, until we are committed to this instruction
3601 : combination) does not work: for example, any call to nonzero_bits
3602 : on the register (from a splitter in the MD file, for example)
3603 : will get the old information, which is invalid.
3604 :
3605 : Since nowadays we can create registers during combine just fine,
3606 : we should just create a new one here, not reuse i2dest. */
3607 :
3608 : /* First try to split using the original register as a
3609 : scratch register. */
3610 4635509 : parallel = gen_rtx_PARALLEL (VOIDmode,
3611 : gen_rtvec (2, newpat,
3612 : gen_rtx_CLOBBER (VOIDmode,
3613 : i2dest)));
3614 4635509 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3615 :
3616 : /* If that didn't work, try changing the mode of I2DEST if
3617 : we can. */
3618 4635509 : if (m_split_insn == 0
3619 4635509 : && new_mode != GET_MODE (i2dest)
3620 1786981 : && new_mode != VOIDmode
3621 5838913 : && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3622 : {
3623 892169 : machine_mode old_mode = GET_MODE (i2dest);
3624 892169 : rtx ni2dest;
3625 :
3626 892169 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3627 8682 : ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3628 : else
3629 : {
3630 883487 : subst_mode (REGNO (i2dest), new_mode);
3631 883487 : ni2dest = regno_reg_rtx[REGNO (i2dest)];
3632 : }
3633 :
3634 892169 : parallel = (gen_rtx_PARALLEL
3635 : (VOIDmode,
3636 : gen_rtvec (2, newpat,
3637 : gen_rtx_CLOBBER (VOIDmode,
3638 : ni2dest))));
3639 892169 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3640 :
3641 892169 : if (m_split_insn == 0
3642 892169 : && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3643 : {
3644 883487 : struct undo *buf;
3645 :
3646 883487 : adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3647 883487 : buf = undobuf.undos;
3648 883487 : undobuf.undos = buf->next;
3649 883487 : buf->next = undobuf.frees;
3650 883487 : undobuf.frees = buf;
3651 : }
3652 : }
3653 :
3654 4635509 : i2scratch = m_split_insn != 0;
3655 : }
3656 :
3657 : /* If recog_for_combine has discarded clobbers, try to use them
3658 : again for the split. */
3659 4772950 : if (m_split_insn == 0 && newpat_vec_with_clobbers)
3660 : {
3661 1677417 : parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3662 1677417 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3663 : }
3664 :
3665 4784656 : if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3666 : {
3667 1630 : rtx m_split_pat = PATTERN (m_split_insn);
3668 1630 : insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes,
3669 : old_nregs, new_nregs);
3670 1630 : if (insn_code_number >= 0)
3671 244 : newpat = m_split_pat;
3672 : }
3673 10076 : else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3674 4781396 : && (next_nonnote_nondebug_insn (i2) == i3
3675 6 : || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3676 : {
3677 10076 : rtx i2set, i3set;
3678 10076 : rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3679 10076 : newi2pat = PATTERN (m_split_insn);
3680 :
3681 10076 : i3set = single_set (NEXT_INSN (m_split_insn));
3682 10076 : i2set = single_set (m_split_insn);
3683 :
3684 10076 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3685 :
3686 : /* If I2 or I3 has multiple SETs, we won't know how to track
3687 : register status, so don't use these insns. If I2's destination
3688 : is used between I2 and I3, we also can't use these insns. */
3689 :
3690 10076 : if (i2_code_number >= 0 && i2set && i3set
3691 20152 : && (next_nonnote_nondebug_insn (i2) == i3
3692 6 : || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3693 10076 : insn_code_number = recog_for_combine (&newi3pat, i3,
3694 : &new_i3_notes,
3695 : old_nregs, new_nregs);
3696 10076 : if (insn_code_number >= 0)
3697 10076 : newpat = newi3pat;
3698 :
3699 : /* It is possible that both insns now set the destination of I3.
3700 : If so, we must show an extra use of it. */
3701 :
3702 10076 : if (insn_code_number >= 0)
3703 : {
3704 10076 : rtx new_i3_dest = SET_DEST (i3set);
3705 10076 : rtx new_i2_dest = SET_DEST (i2set);
3706 :
3707 10076 : while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3708 10116 : || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3709 20214 : || GET_CODE (new_i3_dest) == SUBREG)
3710 40 : new_i3_dest = XEXP (new_i3_dest, 0);
3711 :
3712 10076 : while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3713 10076 : || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3714 20152 : || GET_CODE (new_i2_dest) == SUBREG)
3715 0 : new_i2_dest = XEXP (new_i2_dest, 0);
3716 :
3717 10076 : if (REG_P (new_i3_dest)
3718 5716 : && REG_P (new_i2_dest)
3719 5716 : && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3720 10076 : && REGNO (new_i2_dest) < reg_n_sets_max)
3721 0 : INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3722 : }
3723 : }
3724 :
3725 : /* If we can split it and use I2DEST, go ahead and see if that
3726 : helps things be recognized. Verify that none of the registers
3727 : are set between I2 and I3. */
3728 1386 : if (insn_code_number < 0
3729 4762630 : && (split = find_split_point (&newpat, i3, false)) != 0
3730 : /* We need I2DEST in the proper mode. If it is a hard register
3731 : or the only use of a pseudo, we can change its mode.
3732 : Make sure we don't change a hard register to have a mode that
3733 : isn't valid for it, or change the number of registers. */
3734 4493906 : && (GET_MODE (*split) == GET_MODE (i2dest)
3735 1684051 : || GET_MODE (*split) == VOIDmode
3736 1314663 : || can_change_dest_mode (i2dest, added_sets_2,
3737 : GET_MODE (*split)))
3738 3753682 : && (next_nonnote_nondebug_insn (i2) == i3
3739 591624 : || !modified_between_p (*split, i2, i3))
3740 : /* We can't overwrite I2DEST if its value is still used by
3741 : NEWPAT. */
3742 3724482 : && ! reg_referenced_p (i2dest, newpat)
3743 : /* We should not split a possibly trapping part when we
3744 : care about non-call EH and have REG_EH_REGION notes
3745 : to distribute. */
3746 8423743 : && ! (cfun->can_throw_non_call_exceptions
3747 387302 : && has_non_call_exception
3748 121 : && may_trap_p (*split)))
3749 : {
3750 3652058 : rtx newdest = i2dest;
3751 3652058 : enum rtx_code split_code = GET_CODE (*split);
3752 3652058 : machine_mode split_mode = GET_MODE (*split);
3753 3652058 : bool subst_done = false;
3754 3652058 : newi2pat = NULL_RTX;
3755 :
3756 3652058 : i2scratch = true;
3757 :
3758 : /* *SPLIT may be part of I2SRC, so make sure we have the
3759 : original expression around for later debug processing.
3760 : We should not need I2SRC any more in other cases. */
3761 3652058 : if (MAY_HAVE_DEBUG_BIND_INSNS)
3762 1792263 : i2src = copy_rtx (i2src);
3763 : else
3764 : i2src = NULL;
3765 :
3766 : /* Get NEWDEST as a register in the proper mode. We have already
3767 : validated that we can do this. */
3768 3652058 : if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3769 : {
3770 570988 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3771 0 : newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3772 : else
3773 : {
3774 570988 : subst_mode (REGNO (i2dest), split_mode);
3775 570988 : newdest = regno_reg_rtx[REGNO (i2dest)];
3776 : }
3777 : }
3778 :
3779 : /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3780 : an ASHIFT. This can occur if it was inside a PLUS and hence
3781 : appeared to be a memory address. This is a kludge. */
3782 3652058 : if (split_code == MULT
3783 205441 : && CONST_INT_P (XEXP (*split, 1))
3784 104041 : && INTVAL (XEXP (*split, 1)) > 0
3785 3751763 : && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3786 : {
3787 70403 : rtx i_rtx = gen_int_shift_amount (split_mode, i);
3788 70403 : SUBST (*split, gen_rtx_ASHIFT (split_mode,
3789 : XEXP (*split, 0), i_rtx));
3790 : /* Update split_code because we may not have a multiply
3791 : anymore. */
3792 70403 : split_code = GET_CODE (*split);
3793 : }
3794 :
3795 : /* Similarly for (plus (mult FOO (const_int pow2))). */
3796 3652058 : if (split_code == PLUS
3797 677354 : && GET_CODE (XEXP (*split, 0)) == MULT
3798 111918 : && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3799 39399 : && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3800 3687871 : && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3801 : {
3802 6869 : rtx nsplit = XEXP (*split, 0);
3803 6869 : rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3804 6869 : SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3805 : XEXP (nsplit, 0),
3806 : i_rtx));
3807 : /* Update split_code because we may not have a multiply
3808 : anymore. */
3809 6869 : split_code = GET_CODE (*split);
3810 : }
3811 :
3812 : #ifdef INSN_SCHEDULING
3813 : /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3814 : be written as a ZERO_EXTEND. */
3815 3652058 : if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3816 : {
3817 : /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3818 : what it really is. */
3819 10297 : if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3820 : == SIGN_EXTEND)
3821 : SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3822 : SUBREG_REG (*split)));
3823 : else
3824 10297 : SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3825 : SUBREG_REG (*split)));
3826 : }
3827 : #endif
3828 :
3829 : /* Attempt to split binary operators using arithmetic identities. */
3830 3652058 : if (BINARY_P (SET_SRC (newpat))
3831 3066294 : && split_mode == GET_MODE (SET_SRC (newpat))
3832 5755312 : && ! side_effects_p (SET_SRC (newpat)))
3833 : {
3834 2088719 : rtx setsrc = SET_SRC (newpat);
3835 2088719 : machine_mode mode = GET_MODE (setsrc);
3836 2088719 : enum rtx_code code = GET_CODE (setsrc);
3837 2088719 : rtx src_op0 = XEXP (setsrc, 0);
3838 2088719 : rtx src_op1 = XEXP (setsrc, 1);
3839 :
3840 : /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3841 2088719 : if (rtx_equal_p (src_op0, src_op1))
3842 : {
3843 1569 : newi2pat = gen_rtx_SET (newdest, src_op0);
3844 1569 : SUBST (XEXP (setsrc, 0), newdest);
3845 1569 : SUBST (XEXP (setsrc, 1), newdest);
3846 1569 : subst_done = true;
3847 : }
3848 : /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3849 2087150 : else if ((code == PLUS || code == MULT)
3850 1021989 : && GET_CODE (src_op0) == code
3851 410863 : && GET_CODE (XEXP (src_op0, 0)) == code
3852 174178 : && (INTEGRAL_MODE_P (mode)
3853 : || (FLOAT_MODE_P (mode)
3854 98644 : && flag_unsafe_math_optimizations)))
3855 : {
3856 79328 : rtx p = XEXP (XEXP (src_op0, 0), 0);
3857 79328 : rtx q = XEXP (XEXP (src_op0, 0), 1);
3858 79328 : rtx r = XEXP (src_op0, 1);
3859 79328 : rtx s = src_op1;
3860 :
3861 : /* Split both "((X op Y) op X) op Y" and
3862 : "((X op Y) op Y) op X" as "T op T" where T is
3863 : "X op Y". */
3864 79575 : if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3865 79492 : || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3866 : {
3867 83 : newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3868 83 : SUBST (XEXP (setsrc, 0), newdest);
3869 83 : SUBST (XEXP (setsrc, 1), newdest);
3870 83 : subst_done = true;
3871 : }
3872 : /* Split "((X op X) op Y) op Y)" as "T op T" where
3873 : T is "X op Y". */
3874 79245 : else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3875 : {
3876 41 : rtx tmp = simplify_gen_binary (code, mode, p, r);
3877 41 : newi2pat = gen_rtx_SET (newdest, tmp);
3878 41 : SUBST (XEXP (setsrc, 0), newdest);
3879 41 : SUBST (XEXP (setsrc, 1), newdest);
3880 41 : subst_done = true;
3881 : }
3882 : }
3883 : }
3884 :
3885 1693 : if (!subst_done)
3886 : {
3887 3650365 : newi2pat = gen_rtx_SET (newdest, *split);
3888 3650365 : SUBST (*split, newdest);
3889 : }
3890 :
3891 3652058 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3892 :
3893 : /* recog_for_combine might have added CLOBBERs to newi2pat.
3894 : Make sure NEWPAT does not depend on the clobbered regs. */
3895 3652058 : if (GET_CODE (newi2pat) == PARALLEL)
3896 2567785 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3897 1723927 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3898 : {
3899 880069 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3900 880069 : if (reg_overlap_mentioned_p (reg, newpat))
3901 : {
3902 21809 : undo_all ();
3903 21809 : return 0;
3904 : }
3905 : }
3906 :
3907 : /* If the split point was a MULT and we didn't have one before,
3908 : don't use one now. */
3909 3630249 : if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3910 2186353 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3911 : }
3912 : }
3913 :
3914 : /* Check for a case where we loaded from memory in a narrow mode and
3915 : then sign extended it, but we need both registers. In that case,
3916 : we have a PARALLEL with both loads from the same memory location.
3917 : We can split this into a load from memory followed by a register-register
3918 : copy. This saves at least one insn, more if register allocation can
3919 : eliminate the copy.
3920 :
3921 : We cannot do this if the involved modes have more than one elements,
3922 : like for vector or complex modes.
3923 :
3924 : We cannot do this if the destination of the first assignment is a
3925 : condition code register. We eliminate this case by making sure
3926 : the SET_DEST and SET_SRC have the same mode.
3927 :
3928 : We cannot do this if the destination of the second assignment is
3929 : a register that we have already assumed is zero-extended. Similarly
3930 : for a SUBREG of such a register. */
3931 :
3932 5719997 : else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3933 5661978 : && GET_CODE (newpat) == PARALLEL
3934 5660134 : && XVECLEN (newpat, 0) == 2
3935 4690303 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3936 4690068 : && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3937 23207 : && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3938 23207 : == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3939 23207 : && ! VECTOR_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3940 : && ! COMPLEX_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3941 21761 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3942 21761 : && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3943 21761 : XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3944 6446 : && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3945 6446 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3946 6446 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3947 6446 : && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3948 : (REG_P (temp_expr)
3949 6446 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3950 6544 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3951 : BITS_PER_WORD)
3952 6322 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3953 : HOST_BITS_PER_INT)
3954 1135 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3955 1135 : != GET_MODE_MASK (word_mode))))
3956 6428 : && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3957 0 : && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3958 0 : (REG_P (temp_expr)
3959 0 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3960 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3961 : BITS_PER_WORD)
3962 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3963 : HOST_BITS_PER_INT)
3964 0 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3965 0 : != GET_MODE_MASK (word_mode)))))
3966 6428 : && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3967 6428 : SET_SRC (XVECEXP (newpat, 0, 1)))
3968 28591575 : && ! find_reg_note (i3, REG_UNUSED,
3969 6372 : SET_DEST (XVECEXP (newpat, 0, 0))))
3970 : {
3971 6372 : rtx ni2dest;
3972 :
3973 6372 : newi2pat = XVECEXP (newpat, 0, 0);
3974 6372 : ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3975 6372 : newpat = XVECEXP (newpat, 0, 1);
3976 6372 : SUBST (SET_SRC (newpat),
3977 : gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3978 6372 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3979 :
3980 6372 : if (i2_code_number >= 0)
3981 0 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3982 :
3983 6372 : if (insn_code_number >= 0)
3984 : swap_i2i3 = 1;
3985 : }
3986 :
3987 : /* Similarly, check for a case where we have a PARALLEL of two independent
3988 : SETs but we started with three insns. In this case, we can do the sets
3989 : as two separate insns. This case occurs when some SET allows two
3990 : other insns to combine, but the destination of that SET is still live.
3991 :
3992 : Also do this if we started with two insns and (at least) one of the
3993 : resulting sets is a noop; this noop will be deleted later.
3994 :
3995 : Also do this if we started with two insns neither of which was a simple
3996 : move. */
3997 :
3998 24511124 : else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3999 24492775 : && GET_CODE (newpat) == PARALLEL
4000 11148485 : && XVECLEN (newpat, 0) == 2
4001 10076182 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4002 9968890 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4003 9906621 : && (i1
4004 5244992 : || set_noop_p (XVECEXP (newpat, 0, 0))
4005 5244530 : || set_noop_p (XVECEXP (newpat, 0, 1))
4006 5244528 : || (!i2_was_move && !i3_was_move))
4007 6552166 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4008 6551459 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4009 6551303 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4010 6550728 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4011 6550714 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4012 : XVECEXP (newpat, 0, 0))
4013 5469260 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4014 5469260 : XVECEXP (newpat, 0, 1))
4015 34350416 : && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4016 433065 : && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4017 : {
4018 5092416 : rtx set0 = XVECEXP (newpat, 0, 0);
4019 5092416 : rtx set1 = XVECEXP (newpat, 0, 1);
4020 :
4021 : /* Normally, it doesn't matter which of the two is done first, but
4022 : one which uses any regs/memory set or used in between i2 and i3
4023 : can't be first. The PARALLEL might also have been pre-existing
4024 : in i3, so we need to make sure that we won't wrongly hoist a SET
4025 : to i2 that would conflict with a death note present in there, or
4026 : would have its dest modified or used between i2 and i3. */
4027 5092416 : if ((set_noop_p (set1)
4028 5092416 : || (!modified_between_p (SET_SRC (set1), i2, i3)
4029 10147437 : && !(REG_P (SET_DEST (set1))
4030 5061650 : && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4031 5109626 : && !(GET_CODE (SET_DEST (set1)) == SUBREG
4032 24137 : && find_reg_note (i2, REG_DEAD,
4033 24137 : SUBREG_REG (SET_DEST (set1))))
4034 5085489 : && !modified_between_p (SET_DEST (set1), i2, i3)
4035 5085489 : && !reg_used_between_p (SET_DEST (set1), i2, i3)))
4036 : /* If I3 is a jump, ensure that set0 is a jump so that
4037 : we do not create invalid RTL. */
4038 10177899 : && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx))
4039 : {
4040 5085483 : newi2pat = set1;
4041 5085483 : newpat = set0;
4042 : }
4043 6933 : else if ((set_noop_p (set0)
4044 6927 : || (!modified_between_p (SET_SRC (set0), i2, i3)
4045 600 : && !(REG_P (SET_DEST (set0))
4046 300 : && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4047 300 : && !(GET_CODE (SET_DEST (set0)) == SUBREG
4048 0 : && find_reg_note (i2, REG_DEAD,
4049 0 : SUBREG_REG (SET_DEST (set0))))
4050 300 : && !modified_between_p (SET_DEST (set0), i2, i3)
4051 299 : && !reg_used_between_p (SET_DEST (set0), i2, i3)))
4052 : /* If I3 is a jump, ensure that set1 is a jump so that
4053 : we do not create invalid RTL. */
4054 7232 : && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx))
4055 : {
4056 305 : newi2pat = set0;
4057 305 : newpat = set1;
4058 : }
4059 : else
4060 : {
4061 6628 : undo_all ();
4062 6628 : return 0;
4063 : }
4064 :
4065 5085788 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4066 :
4067 5085788 : if (i2_code_number >= 0)
4068 : {
4069 : /* recog_for_combine might have added CLOBBERs to newi2pat.
4070 : Make sure NEWPAT does not depend on the clobbered regs. */
4071 3742571 : if (GET_CODE (newi2pat) == PARALLEL)
4072 : {
4073 1375173 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4074 920726 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4075 : {
4076 466279 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4077 466279 : if (reg_overlap_mentioned_p (reg, newpat))
4078 : {
4079 3221 : undo_all ();
4080 3221 : return 0;
4081 : }
4082 : }
4083 : }
4084 :
4085 3739350 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4086 :
4087 : /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4088 : Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4089 : mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4090 3739350 : if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4091 : {
4092 71024 : for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4093 47360 : if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4094 : {
4095 23696 : rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4096 23696 : if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4097 23696 : || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4098 : {
4099 0 : undo_all ();
4100 0 : return 0;
4101 : }
4102 : }
4103 : }
4104 :
4105 : if (insn_code_number >= 0)
4106 : split_i2i3 = true;
4107 : }
4108 : }
4109 :
4110 : /* If it still isn't recognized, fail and change things back the way they
4111 : were. */
4112 29580773 : if ((insn_code_number < 0
4113 : /* Is the result a reasonable ASM_OPERANDS? */
4114 33164684 : && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4115 : {
4116 29039871 : undo_all ();
4117 29039871 : return 0;
4118 : }
4119 :
4120 : /* If we had to change another insn, make sure it is valid also. */
4121 4286624 : if (undobuf.other_insn)
4122 : {
4123 230381 : CLEAR_HARD_REG_SET (newpat_used_regs);
4124 :
4125 230381 : other_pat = PATTERN (undobuf.other_insn);
4126 230381 : other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4127 : &new_other_notes);
4128 :
4129 230381 : if (other_code_number < 0 && ! check_asm_operands (other_pat))
4130 : {
4131 6543 : undo_all ();
4132 6543 : return 0;
4133 : }
4134 : }
4135 :
4136 : /* Reject this combination if insn_cost reports that the replacement
4137 : instructions are more expensive than the originals. */
4138 4280081 : if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat,
4139 : insn_code_number, i2_code_number,
4140 : other_code_number))
4141 : {
4142 213016 : undo_all ();
4143 213016 : return 0;
4144 : }
4145 :
4146 4067065 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4147 : {
4148 2195328 : struct undo *undo;
4149 :
4150 6565951 : for (undo = undobuf.undos; undo; undo = undo->next)
4151 4370623 : if (undo->kind == UNDO_MODE)
4152 : {
4153 2771 : rtx reg = regno_reg_rtx[undo->where.regno];
4154 2771 : machine_mode new_mode = GET_MODE (reg);
4155 2771 : machine_mode old_mode = undo->old_contents.m;
4156 :
4157 : /* Temporarily revert mode back. */
4158 2771 : adjust_reg_mode (reg, old_mode);
4159 :
4160 2771 : if (reg == i2dest && i2scratch)
4161 : {
4162 : /* If we used i2dest as a scratch register with a
4163 : different mode, substitute it for the original
4164 : i2src while its original mode is temporarily
4165 : restored, and then clear i2scratch so that we don't
4166 : do it again later. */
4167 2771 : propagate_for_debug (i2, last_combined_insn, reg, i2src,
4168 : this_basic_block);
4169 2771 : i2scratch = false;
4170 : /* Put back the new mode. */
4171 2771 : adjust_reg_mode (reg, new_mode);
4172 : }
4173 : else
4174 : {
4175 0 : rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4176 0 : rtx_insn *first, *last;
4177 :
4178 0 : if (reg == i2dest)
4179 : {
4180 : first = i2;
4181 : last = last_combined_insn;
4182 : }
4183 : else
4184 : {
4185 0 : first = i3;
4186 0 : last = undobuf.other_insn;
4187 0 : gcc_assert (last);
4188 0 : if (DF_INSN_LUID (last)
4189 0 : < DF_INSN_LUID (last_combined_insn))
4190 0 : last = last_combined_insn;
4191 : }
4192 :
4193 : /* We're dealing with a reg that changed mode but not
4194 : meaning, so we want to turn it into a subreg for
4195 : the new mode. However, because of REG sharing and
4196 : because its mode had already changed, we have to do
4197 : it in two steps. First, replace any debug uses of
4198 : reg, with its original mode temporarily restored,
4199 : with this copy we have created; then, replace the
4200 : copy with the SUBREG of the original shared reg,
4201 : once again changed to the new mode. */
4202 0 : propagate_for_debug (first, last, reg, tempreg,
4203 : this_basic_block);
4204 0 : adjust_reg_mode (reg, new_mode);
4205 0 : propagate_for_debug (first, last, tempreg,
4206 : lowpart_subreg (old_mode, reg, new_mode),
4207 : this_basic_block);
4208 : }
4209 : }
4210 : }
4211 :
4212 : /* If we will be able to accept this, we have made a
4213 : change to the destination of I3. This requires us to
4214 : do a few adjustments. */
4215 :
4216 4067065 : if (changed_i3_dest)
4217 : {
4218 17215 : PATTERN (i3) = newpat;
4219 17215 : adjust_for_new_dest (i3);
4220 : }
4221 :
4222 4067065 : bool only_i3_changed = !i0 && !i1 && rtx_equal_p (newi2pat, PATTERN (i2));
4223 :
4224 : /* If only i3 has changed, any split of the combined instruction just
4225 : restored i2 to its original state. No destinations moved from i3
4226 : to i2. */
4227 : if (only_i3_changed)
4228 : split_i2i3 = false;
4229 :
4230 : /* We now know that we can do this combination. Merge the insns and
4231 : update the status of registers and LOG_LINKS. */
4232 :
4233 4067065 : if (undobuf.other_insn)
4234 : {
4235 223678 : rtx note, next;
4236 :
4237 223678 : PATTERN (undobuf.other_insn) = other_pat;
4238 :
4239 : /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4240 : ensure that they are still valid. Then add any non-duplicate
4241 : notes added by recog_for_combine. */
4242 668158 : for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4243 : {
4244 444480 : next = XEXP (note, 1);
4245 :
4246 444480 : if ((REG_NOTE_KIND (note) == REG_DEAD
4247 226797 : && !reg_referenced_p (XEXP (note, 0),
4248 226797 : PATTERN (undobuf.other_insn)))
4249 439954 : ||(REG_NOTE_KIND (note) == REG_UNUSED
4250 5 : && !reg_set_p (XEXP (note, 0),
4251 5 : PATTERN (undobuf.other_insn)))
4252 : /* Simply drop equal note since it may be no longer valid
4253 : for other_insn. It may be possible to record that CC
4254 : register is changed and only discard those notes, but
4255 : in practice it's unnecessary complication and doesn't
4256 : give any meaningful improvement.
4257 :
4258 : See PR78559. */
4259 439954 : || REG_NOTE_KIND (note) == REG_EQUAL
4260 884300 : || REG_NOTE_KIND (note) == REG_EQUIV)
4261 4660 : remove_note (undobuf.other_insn, note);
4262 : }
4263 :
4264 223678 : distribute_notes (new_other_notes, undobuf.other_insn,
4265 : undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4266 : NULL_RTX);
4267 : }
4268 :
4269 4067065 : if (swap_i2i3)
4270 : {
4271 : /* I3 now uses what used to be its destination and which is now
4272 : I2's destination. This requires us to do a few adjustments. */
4273 0 : PATTERN (i3) = newpat;
4274 0 : adjust_for_new_dest (i3);
4275 : }
4276 :
4277 4067065 : if (swap_i2i3 || split_i2i3)
4278 : {
4279 : /* We might need a LOG_LINK from I3 to I2. But then we used to
4280 : have one, so we still will.
4281 :
4282 : However, some later insn might be using I2's dest and have
4283 : a LOG_LINK pointing at I3. We should change it to point at
4284 : I2 instead. */
4285 :
4286 : /* newi2pat is usually a SET here; however, recog_for_combine might
4287 : have added some clobbers. */
4288 27297 : rtx x = newi2pat;
4289 27297 : if (GET_CODE (x) == PARALLEL)
4290 549 : x = XVECEXP (newi2pat, 0, 0);
4291 :
4292 27297 : if (REG_P (SET_DEST (x))
4293 8 : || (GET_CODE (SET_DEST (x)) == SUBREG
4294 2 : && REG_P (SUBREG_REG (SET_DEST (x)))))
4295 : {
4296 27291 : unsigned int regno = reg_or_subregno (SET_DEST (x));
4297 :
4298 27291 : bool done = false;
4299 375711 : for (rtx_insn *insn = NEXT_INSN (i3);
4300 375711 : !done
4301 375711 : && insn
4302 374418 : && INSN_P (insn)
4303 724131 : && BLOCK_FOR_INSN (insn) == this_basic_block;
4304 348420 : insn = NEXT_INSN (insn))
4305 : {
4306 348420 : if (DEBUG_INSN_P (insn))
4307 70415 : continue;
4308 278005 : struct insn_link *link;
4309 522482 : FOR_EACH_LOG_LINK (link, insn)
4310 244487 : if (link->insn == i3 && link->regno == regno)
4311 : {
4312 10 : link->insn = i2;
4313 10 : done = true;
4314 10 : break;
4315 : }
4316 : }
4317 : }
4318 : }
4319 :
4320 4067065 : {
4321 4067065 : rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4322 4067065 : struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4323 4067065 : rtx midnotes = 0;
4324 4067065 : int from_luid;
4325 : /* Compute which registers we expect to eliminate. newi2pat may be setting
4326 : either i3dest or i2dest, so we must check it. */
4327 103910 : rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4328 3974257 : || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4329 3889580 : || !i2dest_killed
4330 7955573 : ? 0 : i2dest);
4331 : /* For i1, we need to compute both local elimination and global
4332 : elimination information with respect to newi2pat because i1dest
4333 : may be the same as i3dest, in which case newi2pat may be setting
4334 : i1dest. Global information is used when distributing REG_DEAD
4335 : note for i2 and i3, in which case it does matter if newi2pat sets
4336 : i1dest or not.
4337 :
4338 : Local information is used when distributing REG_DEAD note for i1,
4339 : in which case it doesn't matter if newi2pat sets i1dest or not.
4340 : See PR62151, if we have four insns combination:
4341 : i0: r0 <- i0src
4342 : i1: r1 <- i1src (using r0)
4343 : REG_DEAD (r0)
4344 : i2: r0 <- i2src (using r1)
4345 : i3: r3 <- i3src (using r0)
4346 : ix: using r0
4347 : From i1's point of view, r0 is eliminated, no matter if it is set
4348 : by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4349 : should be discarded.
4350 :
4351 : Note local information only affects cases in forms like "I1->I2->I3",
4352 : "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4353 : "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4354 : i0dest anyway. */
4355 103010 : rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4356 102944 : || !i1dest_killed
4357 4067065 : ? 0 : i1dest);
4358 102943 : rtx elim_i1 = (local_elim_i1 == 0
4359 102943 : || (newi2pat && reg_set_p (i1dest, newi2pat))
4360 102943 : ? 0 : i1dest);
4361 : /* Same case as i1. */
4362 4592 : rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4363 4067065 : ? 0 : i0dest);
4364 4573 : rtx elim_i0 = (local_elim_i0 == 0
4365 4573 : || (newi2pat && reg_set_p (i0dest, newi2pat))
4366 4573 : ? 0 : i0dest);
4367 :
4368 : /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4369 : clear them. */
4370 4067065 : i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4371 4067065 : i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4372 4067065 : if (i1)
4373 103010 : i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4374 4067065 : if (i0)
4375 4592 : i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4376 :
4377 : /* Ensure that we do not have something that should not be shared but
4378 : occurs multiple times in the new insns. Check this by first
4379 : resetting all the `used' flags and then copying anything is shared. */
4380 :
4381 4067065 : reset_used_flags (i3notes);
4382 4067065 : reset_used_flags (i2notes);
4383 4067065 : reset_used_flags (i1notes);
4384 4067065 : reset_used_flags (i0notes);
4385 4067065 : reset_used_flags (newpat);
4386 4067065 : reset_used_flags (newi2pat);
4387 4067065 : if (undobuf.other_insn)
4388 223678 : reset_used_flags (PATTERN (undobuf.other_insn));
4389 :
4390 4067065 : i3notes = copy_rtx_if_shared (i3notes);
4391 4067065 : i2notes = copy_rtx_if_shared (i2notes);
4392 4067065 : i1notes = copy_rtx_if_shared (i1notes);
4393 4067065 : i0notes = copy_rtx_if_shared (i0notes);
4394 4067065 : newpat = copy_rtx_if_shared (newpat);
4395 4067065 : newi2pat = copy_rtx_if_shared (newi2pat);
4396 4067065 : if (undobuf.other_insn)
4397 223678 : reset_used_flags (PATTERN (undobuf.other_insn));
4398 :
4399 4067065 : INSN_CODE (i3) = insn_code_number;
4400 4067065 : PATTERN (i3) = newpat;
4401 :
4402 4067065 : if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4403 : {
4404 241623 : for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4405 163546 : link = XEXP (link, 1))
4406 : {
4407 163546 : if (substed_i2)
4408 : {
4409 : /* I2SRC must still be meaningful at this point. Some
4410 : splitting operations can invalidate I2SRC, but those
4411 : operations do not apply to calls. */
4412 163546 : gcc_assert (i2src);
4413 163546 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4414 : i2dest, i2src);
4415 : }
4416 163546 : if (substed_i1)
4417 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4418 : i1dest, i1src);
4419 163546 : if (substed_i0)
4420 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4421 : i0dest, i0src);
4422 : }
4423 : }
4424 :
4425 4067065 : if (undobuf.other_insn)
4426 223678 : INSN_CODE (undobuf.other_insn) = other_code_number;
4427 :
4428 : /* We had one special case above where I2 had more than one set and
4429 : we replaced a destination of one of those sets with the destination
4430 : of I3. In that case, we have to update LOG_LINKS of insns later
4431 : in this basic block. Note that this (expensive) case is rare.
4432 :
4433 : Also, in this case, we must pretend that all REG_NOTEs for I2
4434 : actually came from I3, so that REG_UNUSED notes from I2 will be
4435 : properly handled. */
4436 :
4437 4067065 : if (i3_subst_into_i2)
4438 : {
4439 204793 : for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4440 140702 : if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4441 65392 : || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4442 139879 : && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4443 124981 : && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4444 265683 : && ! find_reg_note (i2, REG_UNUSED,
4445 124981 : SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4446 31529696 : for (temp_insn = NEXT_INSN (i2);
4447 : temp_insn
4448 31529696 : && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4449 31283219 : || BB_HEAD (this_basic_block) != temp_insn);
4450 31473379 : temp_insn = NEXT_INSN (temp_insn))
4451 31473379 : if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4452 20134869 : FOR_EACH_LOG_LINK (link, temp_insn)
4453 7440298 : if (link->insn == i2)
4454 445 : link->insn = i3;
4455 :
4456 64091 : if (i3notes)
4457 : {
4458 : rtx link = i3notes;
4459 71305 : while (XEXP (link, 1))
4460 : link = XEXP (link, 1);
4461 64091 : XEXP (link, 1) = i2notes;
4462 : }
4463 : else
4464 : i3notes = i2notes;
4465 : i2notes = 0;
4466 : }
4467 :
4468 4067065 : LOG_LINKS (i3) = NULL;
4469 4067065 : REG_NOTES (i3) = 0;
4470 4067065 : LOG_LINKS (i2) = NULL;
4471 4067065 : REG_NOTES (i2) = 0;
4472 :
4473 4067065 : if (newi2pat)
4474 : {
4475 103910 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4476 10087 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4477 : this_basic_block);
4478 103910 : INSN_CODE (i2) = i2_code_number;
4479 103910 : PATTERN (i2) = newi2pat;
4480 : }
4481 : else
4482 : {
4483 3963155 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4484 2130223 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4485 : this_basic_block);
4486 3963155 : SET_INSN_DELETED (i2);
4487 : }
4488 :
4489 4067065 : if (i1)
4490 : {
4491 103010 : LOG_LINKS (i1) = NULL;
4492 103010 : REG_NOTES (i1) = 0;
4493 103010 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4494 52990 : propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4495 : this_basic_block);
4496 103010 : SET_INSN_DELETED (i1);
4497 : }
4498 :
4499 4067065 : if (i0)
4500 : {
4501 4592 : LOG_LINKS (i0) = NULL;
4502 4592 : REG_NOTES (i0) = 0;
4503 4592 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4504 2855 : propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4505 : this_basic_block);
4506 4592 : SET_INSN_DELETED (i0);
4507 : }
4508 :
4509 : /* Get death notes for everything that is now used in either I3 or
4510 : I2 and used to die in a previous insn. If we built two new
4511 : patterns, move from I1 to I2 then I2 to I3 so that we get the
4512 : proper movement on registers that I2 modifies. */
4513 :
4514 4592 : if (i0)
4515 4592 : from_luid = DF_INSN_LUID (i0);
4516 4062473 : else if (i1)
4517 98418 : from_luid = DF_INSN_LUID (i1);
4518 : else
4519 3964055 : from_luid = DF_INSN_LUID (i2);
4520 4067065 : if (newi2pat)
4521 103910 : move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4522 4067065 : move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4523 :
4524 : /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4525 4067065 : if (i3notes)
4526 7359987 : distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4527 : elim_i2, elim_i1, elim_i0);
4528 4067065 : if (i2notes)
4529 5671187 : distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4530 : elim_i2, elim_i1, elim_i0);
4531 4067065 : if (i1notes)
4532 61132 : distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4533 : elim_i2, local_elim_i1, local_elim_i0);
4534 4067065 : if (i0notes)
4535 3974 : distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4536 : elim_i2, elim_i1, local_elim_i0);
4537 4067065 : if (midnotes)
4538 4857259 : distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4539 : elim_i2, elim_i1, elim_i0);
4540 :
4541 : /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4542 : know these are REG_UNUSED and want them to go to the desired insn,
4543 : so we always pass it as i3. */
4544 :
4545 4067065 : if (newi2pat && new_i2_notes)
4546 42232 : distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4547 : NULL_RTX);
4548 :
4549 4067065 : if (new_i3_notes)
4550 153309 : distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4551 : NULL_RTX);
4552 :
4553 : /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4554 : put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4555 : I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4556 : in that case, it might delete I2. Similarly for I2 and I1.
4557 : Show an additional death due to the REG_DEAD note we make here. If
4558 : we discard it in distribute_notes, we will decrement it again. */
4559 :
4560 4067065 : if (i3dest_killed)
4561 : {
4562 337760 : rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4563 337760 : if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4564 665 : distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4565 : elim_i1, elim_i0);
4566 : else
4567 672365 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4568 : elim_i2, elim_i1, elim_i0);
4569 : }
4570 :
4571 4067065 : if (i2dest_in_i2src)
4572 : {
4573 83719 : rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4574 83719 : if (newi2pat && reg_set_p (i2dest, newi2pat))
4575 762 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4576 : NULL_RTX, NULL_RTX);
4577 : else
4578 165876 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4579 : NULL_RTX, NULL_RTX, NULL_RTX);
4580 : }
4581 :
4582 4067065 : if (i1dest_in_i1src)
4583 : {
4584 64 : rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4585 64 : if (newi2pat && reg_set_p (i1dest, newi2pat))
4586 5 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4587 : NULL_RTX, NULL_RTX);
4588 : else
4589 101 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4590 : NULL_RTX, NULL_RTX, NULL_RTX);
4591 : }
4592 :
4593 4067065 : if (i0dest_in_i0src)
4594 : {
4595 19 : rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4596 19 : if (newi2pat && reg_set_p (i0dest, newi2pat))
4597 0 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4598 : NULL_RTX, NULL_RTX);
4599 : else
4600 38 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4601 : NULL_RTX, NULL_RTX, NULL_RTX);
4602 : }
4603 :
4604 4067065 : if (only_i3_changed)
4605 33191 : distribute_links (i3links, i3, param_max_combine_search_insns);
4606 : else
4607 : {
4608 4033874 : distribute_links (i3links);
4609 4033874 : distribute_links (i2links, i2);
4610 4033874 : distribute_links (i1links);
4611 4033874 : distribute_links (i0links);
4612 : }
4613 :
4614 4067065 : if (REG_P (i2dest))
4615 : {
4616 4067065 : struct insn_link *link;
4617 4067065 : rtx_insn *i2_insn = 0;
4618 4067065 : rtx i2_val = 0, set;
4619 :
4620 : /* The insn that used to set this register doesn't exist, and
4621 : this life of the register may not exist either. See if one of
4622 : I3's links points to an insn that sets I2DEST. If it does,
4623 : that is now the last known value for I2DEST. If we don't update
4624 : this and I2 set the register to a value that depended on its old
4625 : contents, we will get confused. If this insn is used, thing
4626 : will be set correctly in combine_instructions. */
4627 7490324 : FOR_EACH_LOG_LINK (link, i3)
4628 3423259 : if ((set = single_set (link->insn)) != 0
4629 3423259 : && rtx_equal_p (i2dest, SET_DEST (set)))
4630 48934 : i2_insn = link->insn, i2_val = SET_SRC (set);
4631 :
4632 4067065 : record_value_for_reg (i2dest, i2_insn, i2_val);
4633 :
4634 : /* If the reg formerly set in I2 died only once and that was in I3,
4635 : zero its use count so it won't make `reload' do any work. */
4636 4067065 : if (! added_sets_2
4637 3939028 : && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4638 3899387 : && ! i2dest_in_i2src
4639 7902965 : && REGNO (i2dest) < reg_n_sets_max)
4640 3835898 : INC_REG_N_SETS (REGNO (i2dest), -1);
4641 : }
4642 :
4643 4067065 : if (i1 && REG_P (i1dest))
4644 : {
4645 103010 : struct insn_link *link;
4646 103010 : rtx_insn *i1_insn = 0;
4647 103010 : rtx i1_val = 0, set;
4648 :
4649 179997 : FOR_EACH_LOG_LINK (link, i3)
4650 76987 : if ((set = single_set (link->insn)) != 0
4651 76987 : && rtx_equal_p (i1dest, SET_DEST (set)))
4652 492 : i1_insn = link->insn, i1_val = SET_SRC (set);
4653 :
4654 103010 : record_value_for_reg (i1dest, i1_insn, i1_val);
4655 :
4656 103010 : if (! added_sets_1
4657 : && ! i1dest_in_i1src
4658 103010 : && REGNO (i1dest) < reg_n_sets_max)
4659 97112 : INC_REG_N_SETS (REGNO (i1dest), -1);
4660 : }
4661 :
4662 4067065 : if (i0 && REG_P (i0dest))
4663 : {
4664 4592 : struct insn_link *link;
4665 4592 : rtx_insn *i0_insn = 0;
4666 4592 : rtx i0_val = 0, set;
4667 :
4668 7097 : FOR_EACH_LOG_LINK (link, i3)
4669 2505 : if ((set = single_set (link->insn)) != 0
4670 2505 : && rtx_equal_p (i0dest, SET_DEST (set)))
4671 0 : i0_insn = link->insn, i0_val = SET_SRC (set);
4672 :
4673 4592 : record_value_for_reg (i0dest, i0_insn, i0_val);
4674 :
4675 4592 : if (! added_sets_0
4676 : && ! i0dest_in_i0src
4677 4592 : && REGNO (i0dest) < reg_n_sets_max)
4678 4525 : INC_REG_N_SETS (REGNO (i0dest), -1);
4679 : }
4680 :
4681 : /* Update reg_stat[].nonzero_bits et al for any changes that may have
4682 : been made to this insn. The order is important, because newi2pat
4683 : can affect nonzero_bits of newpat. */
4684 4067065 : if (newi2pat)
4685 103910 : note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4686 4067065 : note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4687 : }
4688 :
4689 4067065 : if (undobuf.other_insn != NULL_RTX)
4690 : {
4691 223678 : if (dump_file)
4692 : {
4693 12 : fprintf (dump_file, "modifying other_insn ");
4694 12 : dump_insn_slim (dump_file, undobuf.other_insn);
4695 : }
4696 223678 : df_insn_rescan (undobuf.other_insn);
4697 : }
4698 :
4699 4067065 : if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4700 : {
4701 0 : if (dump_file)
4702 : {
4703 0 : fprintf (dump_file, "modifying insn i0 ");
4704 0 : dump_insn_slim (dump_file, i0);
4705 : }
4706 0 : df_insn_rescan (i0);
4707 : }
4708 :
4709 4067065 : if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4710 : {
4711 0 : if (dump_file)
4712 : {
4713 0 : fprintf (dump_file, "modifying insn i1 ");
4714 0 : dump_insn_slim (dump_file, i1);
4715 : }
4716 0 : df_insn_rescan (i1);
4717 : }
4718 :
4719 4067065 : if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4720 : {
4721 103910 : if (dump_file)
4722 : {
4723 15 : fprintf (dump_file, "modifying insn i2 ");
4724 15 : dump_insn_slim (dump_file, i2);
4725 : }
4726 103910 : df_insn_rescan (i2);
4727 : }
4728 :
4729 4067065 : if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4730 : {
4731 4067065 : if (dump_file)
4732 : {
4733 240 : fprintf (dump_file, "modifying insn i3 ");
4734 240 : dump_insn_slim (dump_file, i3);
4735 : }
4736 4067065 : df_insn_rescan (i3);
4737 : }
4738 :
4739 : /* Set new_direct_jump_p if a new return or simple jump instruction
4740 : has been created. Adjust the CFG accordingly. */
4741 4067065 : if (returnjump_p (i3) || any_uncondjump_p (i3))
4742 : {
4743 195 : *new_direct_jump_p = 1;
4744 195 : mark_jump_label (PATTERN (i3), i3, 0);
4745 195 : update_cfg_for_uncondjump (i3);
4746 : }
4747 :
4748 4067065 : if (undobuf.other_insn != NULL_RTX
4749 4067065 : && (returnjump_p (undobuf.other_insn)
4750 223678 : || any_uncondjump_p (undobuf.other_insn)))
4751 : {
4752 1960 : *new_direct_jump_p = 1;
4753 1960 : update_cfg_for_uncondjump (undobuf.other_insn);
4754 : }
4755 :
4756 4067065 : if (GET_CODE (PATTERN (i3)) == TRAP_IF
4757 4067065 : && XEXP (PATTERN (i3), 0) == const1_rtx)
4758 : {
4759 0 : basic_block bb = BLOCK_FOR_INSN (i3);
4760 0 : gcc_assert (bb);
4761 0 : remove_edge (split_block (bb, i3));
4762 0 : emit_barrier_after_bb (bb);
4763 0 : *new_direct_jump_p = 1;
4764 : }
4765 :
4766 4067065 : if (undobuf.other_insn
4767 223678 : && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4768 4067065 : && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4769 : {
4770 0 : basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4771 0 : gcc_assert (bb);
4772 0 : remove_edge (split_block (bb, undobuf.other_insn));
4773 0 : emit_barrier_after_bb (bb);
4774 0 : *new_direct_jump_p = 1;
4775 : }
4776 :
4777 : /* A noop might also need cleaning up of CFG, if it comes from the
4778 : simplification of a jump. */
4779 4067065 : if (JUMP_P (i3)
4780 46007 : && GET_CODE (newpat) == SET
4781 34703 : && SET_SRC (newpat) == pc_rtx
4782 424 : && SET_DEST (newpat) == pc_rtx)
4783 : {
4784 424 : *new_direct_jump_p = 1;
4785 424 : update_cfg_for_uncondjump (i3);
4786 : }
4787 :
4788 4067065 : if (undobuf.other_insn != NULL_RTX
4789 223678 : && JUMP_P (undobuf.other_insn)
4790 217616 : && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4791 217616 : && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4792 4069072 : && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4793 : {
4794 2007 : *new_direct_jump_p = 1;
4795 2007 : update_cfg_for_uncondjump (undobuf.other_insn);
4796 : }
4797 :
4798 4067065 : combine_successes++;
4799 4067065 : undo_commit ();
4800 :
4801 4067065 : if (only_i3_changed)
4802 : return i3;
4803 :
4804 4033874 : rtx_insn *ret = newi2pat ? i2 : i3;
4805 4033874 : if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4806 : ret = added_links_insn;
4807 4033874 : if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4808 : ret = added_notes_insn;
4809 :
4810 : return ret;
4811 : }
4812 :
4813 : /* Get a marker for undoing to the current state. */
4814 :
4815 : static void *
4816 38022626 : get_undo_marker (void)
4817 : {
4818 38022626 : return undobuf.undos;
4819 : }
4820 :
4821 : /* Undo the modifications up to the marker. */
4822 :
4823 : static void
4824 44829781 : undo_to_marker (void *marker)
4825 : {
4826 44829781 : struct undo *undo, *next;
4827 :
4828 141123542 : for (undo = undobuf.undos; undo != marker; undo = next)
4829 : {
4830 96293761 : gcc_assert (undo);
4831 :
4832 96293761 : next = undo->next;
4833 96293761 : switch (undo->kind)
4834 : {
4835 89022904 : case UNDO_RTX:
4836 89022904 : *undo->where.r = undo->old_contents.r;
4837 89022904 : break;
4838 6633376 : case UNDO_INT:
4839 6633376 : *undo->where.i = undo->old_contents.i;
4840 6633376 : break;
4841 566015 : case UNDO_MODE:
4842 566015 : adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4843 : undo->old_contents.m);
4844 566015 : break;
4845 71466 : case UNDO_LINKS:
4846 71466 : *undo->where.l = undo->old_contents.l;
4847 71466 : break;
4848 0 : default:
4849 0 : gcc_unreachable ();
4850 : }
4851 :
4852 96293761 : undo->next = undobuf.frees;
4853 96293761 : undobuf.frees = undo;
4854 : }
4855 :
4856 44829781 : undobuf.undos = (struct undo *) marker;
4857 44829781 : }
4858 :
4859 : /* Undo all the modifications recorded in undobuf. */
4860 :
4861 : static void
4862 43703030 : undo_all (void)
4863 : {
4864 43703030 : undo_to_marker (0);
4865 0 : }
4866 :
4867 : /* We've committed to accepting the changes we made. Move all
4868 : of the undos to the free list. */
4869 :
4870 : static void
4871 4067065 : undo_commit (void)
4872 : {
4873 4067065 : struct undo *undo, *next;
4874 :
4875 11974422 : for (undo = undobuf.undos; undo; undo = next)
4876 : {
4877 7907357 : next = undo->next;
4878 7907357 : undo->next = undobuf.frees;
4879 7907357 : undobuf.frees = undo;
4880 : }
4881 4067065 : undobuf.undos = 0;
4882 4067065 : }
4883 :
4884 : /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4885 : where we have an arithmetic expression and return that point. LOC will
4886 : be inside INSN.
4887 :
4888 : try_combine will call this function to see if an insn can be split into
4889 : two insns. */
4890 :
4891 : static rtx *
4892 31597514 : find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4893 : {
4894 32647898 : rtx x = *loc;
4895 32647898 : enum rtx_code code = GET_CODE (x);
4896 32647898 : rtx *split;
4897 32647898 : unsigned HOST_WIDE_INT len = 0;
4898 32647898 : HOST_WIDE_INT pos = 0;
4899 32647898 : bool unsignedp = false;
4900 32647898 : rtx inner = NULL_RTX;
4901 32647898 : scalar_int_mode mode, inner_mode;
4902 :
4903 : /* First special-case some codes. */
4904 32647898 : switch (code)
4905 : {
4906 1055558 : case SUBREG:
4907 : #ifdef INSN_SCHEDULING
4908 : /* If we are making a paradoxical SUBREG invalid, it becomes a split
4909 : point. */
4910 1055558 : if (MEM_P (SUBREG_REG (x)))
4911 : return loc;
4912 : #endif
4913 1043660 : return find_split_point (&SUBREG_REG (x), insn, false);
4914 :
4915 1528321 : case MEM:
4916 : /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4917 : using LO_SUM and HIGH. */
4918 1528321 : if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4919 : || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4920 : {
4921 : machine_mode address_mode = get_address_mode (x);
4922 :
4923 : SUBST (XEXP (x, 0),
4924 : gen_rtx_LO_SUM (address_mode,
4925 : gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4926 : XEXP (x, 0)));
4927 : return &XEXP (XEXP (x, 0), 0);
4928 : }
4929 :
4930 : /* If we have a PLUS whose second operand is a constant and the
4931 : address is not valid, perhaps we can split it up using
4932 : the machine-specific way to split large constants. We use
4933 : the first pseudo-reg (one of the virtual regs) as a placeholder;
4934 : it will not remain in the result. */
4935 1528321 : if (GET_CODE (XEXP (x, 0)) == PLUS
4936 1010252 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4937 3271061 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4938 732488 : MEM_ADDR_SPACE (x)))
4939 : {
4940 116991 : rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4941 116991 : unsigned int old_nregs, new_nregs;
4942 116991 : rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4943 : subst_insn, &old_nregs, &new_nregs);
4944 :
4945 : /* This should have produced two insns, each of which sets our
4946 : placeholder. If the source of the second is a valid address,
4947 : we can put both sources together and make a split point
4948 : in the middle. */
4949 :
4950 116991 : if (seq
4951 56 : && NEXT_INSN (seq) != NULL_RTX
4952 0 : && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4953 0 : && NONJUMP_INSN_P (seq)
4954 0 : && GET_CODE (PATTERN (seq)) == SET
4955 0 : && SET_DEST (PATTERN (seq)) == reg
4956 0 : && ! reg_mentioned_p (reg,
4957 0 : SET_SRC (PATTERN (seq)))
4958 0 : && NONJUMP_INSN_P (NEXT_INSN (seq))
4959 0 : && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4960 0 : && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4961 116991 : && memory_address_addr_space_p
4962 116991 : (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4963 0 : MEM_ADDR_SPACE (x)))
4964 : {
4965 0 : rtx src1 = SET_SRC (PATTERN (seq));
4966 0 : rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4967 :
4968 : /* Replace the placeholder in SRC2 with SRC1. If we can
4969 : find where in SRC2 it was placed, that can become our
4970 : split point and we can replace this address with SRC2.
4971 : Just try two obvious places. */
4972 :
4973 0 : src2 = replace_rtx (src2, reg, src1);
4974 0 : split = 0;
4975 0 : if (XEXP (src2, 0) == src1)
4976 0 : split = &XEXP (src2, 0);
4977 0 : else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4978 0 : && XEXP (XEXP (src2, 0), 0) == src1)
4979 0 : split = &XEXP (XEXP (src2, 0), 0);
4980 :
4981 0 : if (split)
4982 : {
4983 0 : SUBST (XEXP (x, 0), src2);
4984 91963 : return split;
4985 : }
4986 : }
4987 :
4988 : /* If that didn't work and we have a nested plus, like:
4989 : ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4990 : is valid address, try to split (REG1 * CONST1). */
4991 116991 : if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4992 78642 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4993 62228 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4994 62220 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4995 10 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4996 : 0), 0)))))
4997 : {
4998 62220 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
4999 62220 : XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
5000 124440 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5001 62220 : MEM_ADDR_SPACE (x)))
5002 : {
5003 50852 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5004 50852 : return &XEXP (XEXP (XEXP (x, 0), 0), 0);
5005 : }
5006 11368 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5007 11368 : }
5008 54771 : else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5009 16422 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5010 16414 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5011 286 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
5012 286 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5013 : 0), 1)))))
5014 : {
5015 0 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
5016 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
5017 0 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5018 0 : MEM_ADDR_SPACE (x)))
5019 : {
5020 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5021 0 : return &XEXP (XEXP (XEXP (x, 0), 0), 1);
5022 : }
5023 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5024 : }
5025 :
5026 : /* If that didn't work, perhaps the first operand is complex and
5027 : needs to be computed separately, so make a split point there.
5028 : This will occur on machines that just support REG + CONST
5029 : and have a constant moved through some previous computation. */
5030 66139 : if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5031 41111 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5032 0 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5033 41111 : return &XEXP (XEXP (x, 0), 0);
5034 : }
5035 :
5036 : /* If we have a PLUS whose first operand is complex, try computing it
5037 : separately by making a split there. */
5038 1436358 : if (GET_CODE (XEXP (x, 0)) == PLUS
5039 2521992 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5040 918289 : MEM_ADDR_SPACE (x))
5041 167345 : && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5042 1548399 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5043 590 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5044 112037 : return &XEXP (XEXP (x, 0), 0);
5045 : break;
5046 :
5047 4762630 : case SET:
5048 : /* See if we can split SET_SRC as it stands. */
5049 4762630 : split = find_split_point (&SET_SRC (x), insn, true);
5050 4762630 : if (split && split != &SET_SRC (x))
5051 : return split;
5052 :
5053 : /* See if we can split SET_DEST as it stands. */
5054 512215 : split = find_split_point (&SET_DEST (x), insn, false);
5055 512215 : if (split && split != &SET_DEST (x))
5056 : return split;
5057 :
5058 : /* See if this is a bitfield assignment with everything constant. If
5059 : so, this is an IOR of an AND, so split it into that. */
5060 479979 : if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5061 4098 : && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5062 : &inner_mode)
5063 4098 : && HWI_COMPUTABLE_MODE_P (inner_mode)
5064 4098 : && CONST_INT_P (XEXP (SET_DEST (x), 1))
5065 4098 : && CONST_INT_P (XEXP (SET_DEST (x), 2))
5066 3936 : && CONST_INT_P (SET_SRC (x))
5067 424 : && ((INTVAL (XEXP (SET_DEST (x), 1))
5068 424 : + INTVAL (XEXP (SET_DEST (x), 2)))
5069 424 : <= GET_MODE_PRECISION (inner_mode))
5070 480403 : && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5071 : {
5072 407 : HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5073 407 : unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5074 407 : rtx dest = XEXP (SET_DEST (x), 0);
5075 407 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5076 407 : unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5077 407 : rtx or_mask;
5078 :
5079 407 : if (BITS_BIG_ENDIAN)
5080 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5081 :
5082 407 : or_mask = gen_int_mode (src << pos, inner_mode);
5083 407 : if (src == mask)
5084 0 : SUBST (SET_SRC (x),
5085 : simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5086 : else
5087 : {
5088 407 : rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5089 407 : SUBST (SET_SRC (x),
5090 : simplify_gen_binary (IOR, inner_mode,
5091 : simplify_gen_binary (AND, inner_mode,
5092 : dest, negmask),
5093 : or_mask));
5094 : }
5095 :
5096 407 : SUBST (SET_DEST (x), dest);
5097 :
5098 407 : split = find_split_point (&SET_SRC (x), insn, true);
5099 407 : if (split && split != &SET_SRC (x))
5100 : return split;
5101 : }
5102 :
5103 : /* Otherwise, see if this is an operation that we can split into two.
5104 : If so, try to split that. */
5105 479572 : code = GET_CODE (SET_SRC (x));
5106 :
5107 479572 : switch (code)
5108 : {
5109 16496 : case AND:
5110 : /* If we are AND'ing with a large constant that is only a single
5111 : bit and the result is only being used in a context where we
5112 : need to know if it is zero or nonzero, replace it with a bit
5113 : extraction. This will avoid the large constant, which might
5114 : have taken more than one insn to make. If the constant were
5115 : not a valid argument to the AND but took only one insn to make,
5116 : this is no worse, but if it took more than one insn, it will
5117 : be better. */
5118 :
5119 16496 : if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5120 11012 : && REG_P (XEXP (SET_SRC (x), 0))
5121 450 : && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5122 2 : && REG_P (SET_DEST (x))
5123 1 : && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5124 1 : && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5125 0 : && XEXP (*split, 0) == SET_DEST (x)
5126 16496 : && XEXP (*split, 1) == const0_rtx)
5127 : {
5128 0 : rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5129 0 : XEXP (SET_SRC (x), 0),
5130 : pos, NULL_RTX, 1,
5131 : true, false, false);
5132 0 : if (extraction != 0)
5133 : {
5134 0 : SUBST (SET_SRC (x), extraction);
5135 0 : return find_split_point (loc, insn, false);
5136 : }
5137 : }
5138 : break;
5139 :
5140 : case NE:
5141 : /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5142 : is known to be on, this can be converted into a NEG of a shift. */
5143 : if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5144 : && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5145 : && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5146 : GET_MODE (XEXP (SET_SRC (x),
5147 : 0))))) >= 1))
5148 : {
5149 : machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5150 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5151 : SUBST (SET_SRC (x),
5152 : gen_rtx_NEG (mode,
5153 : gen_rtx_LSHIFTRT (mode,
5154 : XEXP (SET_SRC (x), 0),
5155 : pos_rtx)));
5156 :
5157 : split = find_split_point (&SET_SRC (x), insn, true);
5158 : if (split && split != &SET_SRC (x))
5159 : return split;
5160 : }
5161 : break;
5162 :
5163 515 : case SIGN_EXTEND:
5164 515 : inner = XEXP (SET_SRC (x), 0);
5165 :
5166 : /* We can't optimize if either mode is a partial integer
5167 : mode as we don't know how many bits are significant
5168 : in those modes. */
5169 515 : if (!is_int_mode (GET_MODE (inner), &inner_mode)
5170 509 : || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5171 : break;
5172 :
5173 509 : pos = 0;
5174 509 : len = GET_MODE_PRECISION (inner_mode);
5175 509 : unsignedp = false;
5176 509 : break;
5177 :
5178 12317 : case SIGN_EXTRACT:
5179 12317 : case ZERO_EXTRACT:
5180 12317 : if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5181 : &inner_mode)
5182 12024 : && CONST_INT_P (XEXP (SET_SRC (x), 1))
5183 12024 : && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5184 : {
5185 11596 : inner = XEXP (SET_SRC (x), 0);
5186 11596 : len = INTVAL (XEXP (SET_SRC (x), 1));
5187 11596 : pos = INTVAL (XEXP (SET_SRC (x), 2));
5188 :
5189 11596 : if (BITS_BIG_ENDIAN)
5190 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5191 11596 : unsignedp = (code == ZERO_EXTRACT);
5192 : }
5193 : break;
5194 :
5195 : default:
5196 : break;
5197 : }
5198 :
5199 479572 : if (len
5200 12105 : && known_subrange_p (pos, len,
5201 12105 : 0, GET_MODE_PRECISION (GET_MODE (inner)))
5202 491677 : && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5203 : {
5204 : /* For unsigned, we have a choice of a shift followed by an
5205 : AND or two shifts. Use two shifts for field sizes where the
5206 : constant might be too large. We assume here that we can
5207 : always at least get 8-bit constants in an AND insn, which is
5208 : true for every current RISC. */
5209 :
5210 12105 : if (unsignedp && len <= 8)
5211 : {
5212 4953 : unsigned HOST_WIDE_INT mask
5213 4953 : = (HOST_WIDE_INT_1U << len) - 1;
5214 4953 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5215 4953 : SUBST (SET_SRC (x),
5216 : gen_rtx_AND (mode,
5217 : gen_rtx_LSHIFTRT
5218 : (mode, gen_lowpart (mode, inner), pos_rtx),
5219 : gen_int_mode (mask, mode)));
5220 :
5221 4953 : split = find_split_point (&SET_SRC (x), insn, true);
5222 4953 : if (split && split != &SET_SRC (x))
5223 31597514 : return split;
5224 : }
5225 : else
5226 : {
5227 7152 : int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5228 7152 : int right_bits = GET_MODE_PRECISION (mode) - len;
5229 14304 : SUBST (SET_SRC (x),
5230 : gen_rtx_fmt_ee
5231 : (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5232 : gen_rtx_ASHIFT (mode,
5233 : gen_lowpart (mode, inner),
5234 : gen_int_shift_amount (mode, left_bits)),
5235 : gen_int_shift_amount (mode, right_bits)));
5236 :
5237 7152 : split = find_split_point (&SET_SRC (x), insn, true);
5238 7152 : if (split && split != &SET_SRC (x))
5239 31597514 : return split;
5240 : }
5241 : }
5242 :
5243 : /* See if this is a simple operation with a constant as the second
5244 : operand. It might be that this constant is out of range and hence
5245 : could be used as a split point. */
5246 467467 : if (BINARY_P (SET_SRC (x))
5247 204511 : && CONSTANT_P (XEXP (SET_SRC (x), 1))
5248 113668 : && (OBJECT_P (XEXP (SET_SRC (x), 0))
5249 37547 : || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5250 11240 : && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5251 77939 : return &XEXP (SET_SRC (x), 1);
5252 :
5253 : /* Finally, see if this is a simple operation with its first operand
5254 : not in a register. The operation might require this operand in a
5255 : register, so return it as a split point. We can always do this
5256 : because if the first operand were another operation, we would have
5257 : already found it as a split point. */
5258 389528 : if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5259 389528 : && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5260 120804 : return &XEXP (SET_SRC (x), 0);
5261 :
5262 : return 0;
5263 :
5264 1191144 : case AND:
5265 1191144 : case IOR:
5266 : /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5267 : it is better to write this as (not (ior A B)) so we can split it.
5268 : Similarly for IOR. */
5269 1191144 : if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5270 : {
5271 1808 : SUBST (*loc,
5272 : gen_rtx_NOT (GET_MODE (x),
5273 : gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5274 : GET_MODE (x),
5275 : XEXP (XEXP (x, 0), 0),
5276 : XEXP (XEXP (x, 1), 0))));
5277 904 : return find_split_point (loc, insn, set_src);
5278 : }
5279 :
5280 : /* Many RISC machines have a large set of logical insns. If the
5281 : second operand is a NOT, put it first so we will try to split the
5282 : other operand first. */
5283 1190240 : if (GET_CODE (XEXP (x, 1)) == NOT)
5284 : {
5285 5271 : rtx tem = XEXP (x, 0);
5286 5271 : SUBST (XEXP (x, 0), XEXP (x, 1));
5287 5271 : SUBST (XEXP (x, 1), tem);
5288 : }
5289 : /* Many targets have a `(and (not X) Y)` and/or `(ior (not X) Y)` instructions.
5290 : Split at that insns. However if this is
5291 : the SET_SRC, we likely do not have such an instruction and it's
5292 : worthless to try this split. */
5293 1190240 : if (!set_src && GET_CODE (XEXP (x, 0)) == NOT)
5294 : return loc;
5295 : break;
5296 :
5297 3229200 : case PLUS:
5298 3229200 : case MINUS:
5299 : /* Canonicalization can produce (minus A (mult B C)), where C is a
5300 : constant. It may be better to try splitting (plus (mult B -C) A)
5301 : instead if this isn't a multiply by a power of two. */
5302 197762 : if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5303 21447 : && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5304 3235020 : && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5305 : {
5306 5820 : machine_mode mode = GET_MODE (x);
5307 5820 : unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5308 5820 : HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5309 5820 : SUBST (*loc, gen_rtx_PLUS (mode,
5310 : gen_rtx_MULT (mode,
5311 : XEXP (XEXP (x, 1), 0),
5312 : gen_int_mode (other_int,
5313 : mode)),
5314 : XEXP (x, 0)));
5315 5820 : return find_split_point (loc, insn, set_src);
5316 : }
5317 :
5318 : /* Split at a multiply-accumulate instruction. However if this is
5319 : the SET_SRC, we likely do not have such an instruction and it's
5320 : worthless to try this split. */
5321 3223380 : if (!set_src
5322 1934152 : && (GET_CODE (XEXP (x, 0)) == MULT
5323 1821310 : || (GET_CODE (XEXP (x, 0)) == ASHIFT
5324 111446 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5325 : return loc;
5326 :
5327 : default:
5328 : break;
5329 : }
5330 :
5331 : /* Otherwise, select our actions depending on our rtx class. */
5332 26389404 : switch (GET_RTX_CLASS (code))
5333 : {
5334 1504708 : case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5335 1504708 : case RTX_TERNARY:
5336 1504708 : split = find_split_point (&XEXP (x, 2), insn, false);
5337 1504708 : if (split)
5338 : return split;
5339 : /* fall through */
5340 10394228 : case RTX_BIN_ARITH:
5341 10394228 : case RTX_COMM_ARITH:
5342 10394228 : case RTX_COMPARE:
5343 10394228 : case RTX_COMM_COMPARE:
5344 10394228 : split = find_split_point (&XEXP (x, 1), insn, false);
5345 10394228 : if (split)
5346 : return split;
5347 : /* fall through */
5348 10011498 : case RTX_UNARY:
5349 : /* Some machines have (and (shift ...) ...) insns. If X is not
5350 : an AND, but XEXP (X, 0) is, use it as our split point. */
5351 10011498 : if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5352 362907 : return &XEXP (x, 0);
5353 :
5354 9648591 : split = find_split_point (&XEXP (x, 0), insn, false);
5355 9648591 : if (split)
5356 5923577 : return split;
5357 : return loc;
5358 :
5359 : default:
5360 : /* Otherwise, we don't have a split point. */
5361 : return 0;
5362 : }
5363 : }
5364 :
5365 : /* Throughout X, replace FROM with TO, and return the result.
5366 : The result is TO if X is FROM;
5367 : otherwise the result is X, but its contents may have been modified.
5368 : If they were modified, a record was made in undobuf so that
5369 : undo_all will (among other things) return X to its original state.
5370 :
5371 : If the number of changes necessary is too much to record to undo,
5372 : the excess changes are not made, so the result is invalid.
5373 : The changes already made can still be undone.
5374 : undobuf.num_undo is incremented for such changes, so by testing that
5375 : the caller can tell whether the result is valid.
5376 :
5377 : `n_occurrences' is incremented each time FROM is replaced.
5378 :
5379 : IN_DEST is true if we are processing the SET_DEST of a SET.
5380 :
5381 : IN_COND is true if we are at the top level of a condition.
5382 :
5383 : UNIQUE_COPY is true if each substitution must be unique. We do this
5384 : by copying if `n_occurrences' is nonzero. */
5385 :
5386 : static rtx
5387 421750049 : subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5388 : {
5389 421750049 : enum rtx_code code = GET_CODE (x);
5390 421750049 : machine_mode op0_mode = VOIDmode;
5391 421750049 : const char *fmt;
5392 421750049 : int len, i;
5393 421750049 : rtx new_rtx;
5394 :
5395 : /* Two expressions are equal if they are identical copies of a shared
5396 : RTX or if they are both registers with the same register number
5397 : and mode. */
5398 :
5399 : #define COMBINE_RTX_EQUAL_P(X,Y) \
5400 : ((X) == (Y) \
5401 : || (REG_P (X) && REG_P (Y) \
5402 : && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5403 :
5404 : /* Do not substitute into clobbers of regs -- this will never result in
5405 : valid RTL. */
5406 421750049 : if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5407 : return x;
5408 :
5409 411144681 : if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5410 : {
5411 0 : n_occurrences++;
5412 0 : return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5413 : }
5414 :
5415 : /* If X and FROM are the same register but different modes, they
5416 : will not have been seen as equal above. However, the log links code
5417 : will make a LOG_LINKS entry for that case. If we do nothing, we
5418 : will try to rerecognize our original insn and, when it succeeds,
5419 : we will delete the feeding insn, which is incorrect.
5420 :
5421 : So force this insn not to match in this (rare) case. */
5422 91226852 : if (! in_dest && code == REG && REG_P (from)
5423 443819883 : && reg_overlap_mentioned_p (x, from))
5424 4283 : return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5425 :
5426 : /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5427 : of which may contain things that can be combined. */
5428 411140398 : if (code != MEM && code != LO_SUM && OBJECT_P (x))
5429 : return x;
5430 :
5431 : /* It is possible to have a subexpression appear twice in the insn.
5432 : Suppose that FROM is a register that appears within TO.
5433 : Then, after that subexpression has been scanned once by `subst',
5434 : the second time it is scanned, TO may be found. If we were
5435 : to scan TO here, we would find FROM within it and create a
5436 : self-referent rtl structure which is completely wrong. */
5437 220285562 : if (COMBINE_RTX_EQUAL_P (x, to))
5438 : return to;
5439 :
5440 : /* Parallel asm_operands need special attention because all of the
5441 : inputs are shared across the arms. Furthermore, unsharing the
5442 : rtl results in recognition failures. Failure to handle this case
5443 : specially can result in circular rtl.
5444 :
5445 : Solve this by doing a normal pass across the first entry of the
5446 : parallel, and only processing the SET_DESTs of the subsequent
5447 : entries. Ug. */
5448 :
5449 220142014 : if (code == PARALLEL
5450 13312761 : && GET_CODE (XVECEXP (x, 0, 0)) == SET
5451 11199055 : && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5452 : {
5453 21278 : new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5454 :
5455 : /* If this substitution failed, this whole thing fails. */
5456 21278 : if (GET_CODE (new_rtx) == CLOBBER
5457 0 : && XEXP (new_rtx, 0) == const0_rtx)
5458 : return new_rtx;
5459 :
5460 21278 : SUBST (XVECEXP (x, 0, 0), new_rtx);
5461 :
5462 103931 : for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5463 : {
5464 82653 : rtx dest = SET_DEST (XVECEXP (x, 0, i));
5465 :
5466 82653 : if (!REG_P (dest) && GET_CODE (dest) != PC)
5467 : {
5468 3327 : new_rtx = subst (dest, from, to, false, false, unique_copy);
5469 :
5470 : /* If this substitution failed, this whole thing fails. */
5471 3327 : if (GET_CODE (new_rtx) == CLOBBER
5472 0 : && XEXP (new_rtx, 0) == const0_rtx)
5473 : return new_rtx;
5474 :
5475 3327 : SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5476 : }
5477 : }
5478 : }
5479 : else
5480 : {
5481 220120736 : len = GET_RTX_LENGTH (code);
5482 220120736 : fmt = GET_RTX_FORMAT (code);
5483 :
5484 : /* We don't need to process a SET_DEST that is a register or PC, so
5485 : set up to skip this common case. All other cases where we want
5486 : to suppress replacing something inside a SET_SRC are handled via
5487 : the IN_DEST operand. */
5488 220120736 : if (code == SET
5489 48090363 : && (REG_P (SET_DEST (x))
5490 48090363 : || GET_CODE (SET_DEST (x)) == PC))
5491 220120736 : fmt = "ie";
5492 :
5493 : /* Trying to simplify the operands of a widening MULT is not likely
5494 : to create RTL matching a machine insn. */
5495 220120736 : if (code == MULT
5496 4881069 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5497 4881069 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5498 300011 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5499 300011 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5500 223573 : && REG_P (XEXP (XEXP (x, 0), 0))
5501 108181 : && REG_P (XEXP (XEXP (x, 1), 0))
5502 95546 : && from == to)
5503 : return x;
5504 :
5505 :
5506 : /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5507 : constant. */
5508 220062077 : if (fmt[0] == 'e')
5509 162105138 : op0_mode = GET_MODE (XEXP (x, 0));
5510 :
5511 651706328 : for (i = 0; i < len; i++)
5512 : {
5513 432623687 : if (fmt[i] == 'E')
5514 : {
5515 15775758 : int j;
5516 50101572 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5517 : {
5518 34457798 : if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5519 : {
5520 1609 : new_rtx = (unique_copy && n_occurrences
5521 303535 : ? copy_rtx (to) : to);
5522 303511 : n_occurrences++;
5523 : }
5524 : else
5525 : {
5526 34154287 : new_rtx = subst (XVECEXP (x, i, j), from, to,
5527 : false, false, unique_copy);
5528 :
5529 : /* If this substitution failed, this whole thing
5530 : fails. */
5531 34154287 : if (GET_CODE (new_rtx) == CLOBBER
5532 11061307 : && XEXP (new_rtx, 0) == const0_rtx)
5533 : return new_rtx;
5534 : }
5535 :
5536 34325814 : SUBST (XVECEXP (x, i, j), new_rtx);
5537 : }
5538 : }
5539 416847929 : else if (fmt[i] == 'e')
5540 : {
5541 : /* If this is a register being set, ignore it. */
5542 339894670 : new_rtx = XEXP (x, i);
5543 339894670 : if (in_dest
5544 339894670 : && i == 0
5545 5943991 : && (((code == SUBREG || code == ZERO_EXTRACT)
5546 363282 : && REG_P (new_rtx))
5547 5583171 : || code == STRICT_LOW_PART))
5548 : ;
5549 :
5550 339523182 : else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5551 : {
5552 : /* In general, don't install a subreg involving two
5553 : modes not tieable. It can worsen register
5554 : allocation, and can even make invalid reload
5555 : insns, since the reg inside may need to be copied
5556 : from in the outside mode, and that may be invalid
5557 : if it is an fp reg copied in integer mode.
5558 :
5559 : We allow an exception to this: It is valid if
5560 : it is inside another SUBREG and the mode of that
5561 : SUBREG and the mode of the inside of TO is
5562 : tieable. */
5563 :
5564 48283492 : if (GET_CODE (to) == SUBREG
5565 606295 : && !targetm.modes_tieable_p (GET_MODE (to),
5566 606295 : GET_MODE (SUBREG_REG (to)))
5567 48616316 : && ! (code == SUBREG
5568 28679 : && (targetm.modes_tieable_p
5569 28679 : (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5570 301866 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5571 :
5572 47981626 : if (code == SUBREG
5573 2593451 : && REG_P (to)
5574 97345 : && REGNO (to) < FIRST_PSEUDO_REGISTER
5575 47981631 : && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5576 5 : SUBREG_BYTE (x),
5577 5 : GET_MODE (x)) < 0)
5578 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5579 :
5580 47981626 : new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5581 47981626 : n_occurrences++;
5582 : }
5583 : else
5584 : /* If we are in a SET_DEST, suppress most cases unless we
5585 : have gone inside a MEM, in which case we want to
5586 : simplify the address. We assume here that things that
5587 : are actually part of the destination have their inner
5588 : parts in the first expression. This is true for SUBREG,
5589 : STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5590 : things aside from REG and MEM that should appear in a
5591 : SET_DEST. */
5592 334905751 : new_rtx = subst (XEXP (x, i), from, to,
5593 : (((in_dest
5594 5292828 : && (code == SUBREG || code == STRICT_LOW_PART
5595 5292828 : || code == ZERO_EXTRACT))
5596 291231781 : || code == SET)
5597 : && i == 0),
5598 291239690 : code == IF_THEN_ELSE && i == 0,
5599 : unique_copy);
5600 :
5601 : /* If we found that we will have to reject this combination,
5602 : indicate that by returning the CLOBBER ourselves, rather than
5603 : an expression containing it. This will speed things up as
5604 : well as prevent accidents where two CLOBBERs are considered
5605 : to be equal, thus producing an incorrect simplification. */
5606 :
5607 339592804 : if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5608 : return new_rtx;
5609 :
5610 339047470 : if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5611 : {
5612 31074 : machine_mode mode = GET_MODE (x);
5613 :
5614 62148 : x = simplify_subreg (GET_MODE (x), new_rtx,
5615 31074 : GET_MODE (SUBREG_REG (x)),
5616 31074 : SUBREG_BYTE (x));
5617 31074 : if (! x)
5618 2 : x = gen_rtx_CLOBBER (mode, const0_rtx);
5619 : }
5620 339016396 : else if (CONST_SCALAR_INT_P (new_rtx)
5621 : && (GET_CODE (x) == ZERO_EXTEND
5622 61175065 : || GET_CODE (x) == SIGN_EXTEND
5623 : || GET_CODE (x) == FLOAT
5624 : || GET_CODE (x) == UNSIGNED_FLOAT))
5625 : {
5626 136816 : x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5627 : new_rtx,
5628 68408 : GET_MODE (XEXP (x, 0)));
5629 68408 : if (!x)
5630 252 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5631 : }
5632 : /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5633 : etc. arguments, otherwise we can ICE before trying to recog
5634 : it. See PR104446. */
5635 338947988 : else if (CONST_SCALAR_INT_P (new_rtx)
5636 61106657 : && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5637 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5638 : else
5639 338947988 : SUBST (XEXP (x, i), new_rtx);
5640 : }
5641 : }
5642 : }
5643 :
5644 : /* Check if we are loading something from the constant pool via float
5645 : extension; in this case we would undo compress_float_constant
5646 : optimization and degenerate constant load to an immediate value. */
5647 219103919 : if (GET_CODE (x) == FLOAT_EXTEND
5648 309669 : && MEM_P (XEXP (x, 0))
5649 219167914 : && MEM_READONLY_P (XEXP (x, 0)))
5650 : {
5651 36604 : rtx tmp = avoid_constant_pool_reference (x);
5652 36604 : if (x != tmp)
5653 : return x;
5654 : }
5655 :
5656 : /* Try to simplify X. If the simplification changed the code, it is likely
5657 : that further simplification will help, so loop, but limit the number
5658 : of repetitions that will be performed. */
5659 :
5660 227196193 : for (i = 0; i < 4; i++)
5661 : {
5662 : /* If X is sufficiently simple, don't bother trying to do anything
5663 : with it. */
5664 227142590 : if (code != CONST_INT && code != REG && code != CLOBBER)
5665 226465669 : x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5666 :
5667 227142590 : if (GET_CODE (x) == code)
5668 : break;
5669 :
5670 8128748 : code = GET_CODE (x);
5671 :
5672 : /* We no longer know the original mode of operand 0 since we
5673 : have changed the form of X) */
5674 8128748 : op0_mode = VOIDmode;
5675 : }
5676 :
5677 : return x;
5678 : }
5679 :
5680 : /* If X is a commutative operation whose operands are not in the canonical
5681 : order, use substitutions to swap them. */
5682 :
5683 : static void
5684 662172934 : maybe_swap_commutative_operands (rtx x)
5685 : {
5686 662172934 : if (COMMUTATIVE_ARITH_P (x)
5687 662172934 : && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5688 : {
5689 3554172 : rtx temp = XEXP (x, 0);
5690 3554172 : SUBST (XEXP (x, 0), XEXP (x, 1));
5691 3554172 : SUBST (XEXP (x, 1), temp);
5692 : }
5693 :
5694 : /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5695 : (vec_merge (fma op1 op2 op3) op1 mask). */
5696 662172934 : if (GET_CODE (x) == VEC_MERGE
5697 1129929 : && GET_CODE (XEXP (x, 0)) == FMA)
5698 : {
5699 25100 : rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5700 25100 : rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5701 25100 : rtx masked_op = XEXP (x, 1);
5702 25100 : if (rtx_equal_p (masked_op, fma_op2))
5703 : {
5704 218 : if (GET_CODE (fma_op1) == NEG)
5705 : {
5706 : /* Keep the negate canonicalized to the first operand. */
5707 150 : fma_op1 = XEXP (fma_op1, 0);
5708 150 : SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5709 150 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5710 : }
5711 : else
5712 : {
5713 68 : SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5714 68 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5715 : }
5716 : }
5717 : }
5718 :
5719 662172934 : unsigned n_elts = 0;
5720 662172934 : if (GET_CODE (x) == VEC_MERGE
5721 1129929 : && CONST_INT_P (XEXP (x, 2))
5722 1494294 : && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5723 662920081 : && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5724 : /* Two operands have same precedence, then
5725 : first bit of mask select first operand. */
5726 713245 : || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5727 149446 : && !(UINTVAL (XEXP (x, 2)) & 1))))
5728 : {
5729 63401 : rtx temp = XEXP (x, 0);
5730 63401 : unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5731 63401 : unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5732 63401 : if (n_elts == HOST_BITS_PER_WIDE_INT)
5733 : mask = -1;
5734 : else
5735 63260 : mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5736 63401 : SUBST (XEXP (x, 0), XEXP (x, 1));
5737 63401 : SUBST (XEXP (x, 1), temp);
5738 63401 : SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5739 : }
5740 662172934 : }
5741 :
5742 : /* Simplify X, a piece of RTL. We just operate on the expression at the
5743 : outer level; call `subst' to simplify recursively. Return the new
5744 : expression.
5745 :
5746 : OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5747 : if we are inside a SET_DEST. IN_COND is true if we are at the top level
5748 : of a condition. */
5749 :
5750 : static rtx
5751 226800650 : combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5752 : {
5753 226800650 : enum rtx_code code = GET_CODE (x);
5754 226800650 : machine_mode mode = GET_MODE (x);
5755 226800650 : scalar_int_mode int_mode;
5756 226800650 : rtx temp;
5757 226800650 : int i;
5758 :
5759 : /* If this is a commutative operation, put a constant last and a complex
5760 : expression first. We don't need to do this for comparisons here. */
5761 226800650 : maybe_swap_commutative_operands (x);
5762 :
5763 : /* Try to fold this expression in case we have constants that weren't
5764 : present before. */
5765 226800650 : temp = 0;
5766 226800650 : switch (GET_RTX_CLASS (code))
5767 : {
5768 7490532 : case RTX_UNARY:
5769 7490532 : if (op0_mode == VOIDmode)
5770 164410 : op0_mode = GET_MODE (XEXP (x, 0));
5771 7490532 : temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5772 7490532 : break;
5773 18437059 : case RTX_COMPARE:
5774 18437059 : case RTX_COMM_COMPARE:
5775 18437059 : {
5776 18437059 : machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5777 18437059 : if (cmp_mode == VOIDmode)
5778 : {
5779 49155 : cmp_mode = GET_MODE (XEXP (x, 1));
5780 49155 : if (cmp_mode == VOIDmode)
5781 8121 : cmp_mode = op0_mode;
5782 : }
5783 18437059 : temp = simplify_relational_operation (code, mode, cmp_mode,
5784 : XEXP (x, 0), XEXP (x, 1));
5785 : }
5786 18437059 : break;
5787 89025984 : case RTX_COMM_ARITH:
5788 89025984 : case RTX_BIN_ARITH:
5789 89025984 : temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5790 89025984 : break;
5791 14679793 : case RTX_BITFIELD_OPS:
5792 14679793 : case RTX_TERNARY:
5793 14679793 : temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5794 : XEXP (x, 1), XEXP (x, 2));
5795 14679793 : break;
5796 : default:
5797 : break;
5798 : }
5799 :
5800 129633368 : if (temp)
5801 : {
5802 16841088 : x = temp;
5803 16841088 : code = GET_CODE (temp);
5804 16841088 : op0_mode = VOIDmode;
5805 16841088 : mode = GET_MODE (temp);
5806 : }
5807 :
5808 : /* If this is a simple operation applied to an IF_THEN_ELSE, try
5809 : applying it to the arms of the IF_THEN_ELSE. This often simplifies
5810 : things. Check for cases where both arms are testing the same
5811 : condition.
5812 :
5813 : Don't do anything if all operands are very simple. */
5814 :
5815 226800650 : if ((BINARY_P (x)
5816 107205640 : && ((!OBJECT_P (XEXP (x, 0))
5817 42020343 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5818 5277007 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5819 68148198 : || (!OBJECT_P (XEXP (x, 1))
5820 5030786 : && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5821 1956226 : && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5822 184392582 : || (UNARY_P (x)
5823 7368982 : && (!OBJECT_P (XEXP (x, 0))
5824 3328138 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5825 894541 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5826 : {
5827 44933539 : rtx cond, true_rtx, false_rtx;
5828 :
5829 44933539 : cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5830 44933539 : if (cond != 0
5831 : /* If everything is a comparison, what we have is highly unlikely
5832 : to be simpler, so don't use it. */
5833 4586283 : && ! (COMPARISON_P (x)
5834 1267954 : && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5835 : /* Similarly, if we end up with one of the expressions the same
5836 : as the original, it is certainly not simpler. */
5837 4411859 : && ! rtx_equal_p (x, true_rtx)
5838 49345398 : && ! rtx_equal_p (x, false_rtx))
5839 : {
5840 4411859 : rtx cop1 = const0_rtx;
5841 4411859 : enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5842 :
5843 4411859 : if (cond_code == NE && COMPARISON_P (cond))
5844 665986 : return x;
5845 :
5846 : /* Simplify the alternative arms; this may collapse the true and
5847 : false arms to store-flag values. Be careful to use copy_rtx
5848 : here since true_rtx or false_rtx might share RTL with x as a
5849 : result of the if_then_else_cond call above. */
5850 3745873 : true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5851 : false, false, false);
5852 3745873 : false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5853 : false, false, false);
5854 :
5855 : /* If true_rtx and false_rtx are not general_operands, an if_then_else
5856 : is unlikely to be simpler. */
5857 3745873 : if (general_operand (true_rtx, VOIDmode)
5858 3745873 : && general_operand (false_rtx, VOIDmode))
5859 : {
5860 1403073 : enum rtx_code reversed;
5861 :
5862 : /* Restarting if we generate a store-flag expression will cause
5863 : us to loop. Just drop through in this case. */
5864 :
5865 : /* If the result values are STORE_FLAG_VALUE and zero, we can
5866 : just make the comparison operation. */
5867 1403073 : if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5868 625454 : x = simplify_gen_relational (cond_code, mode, VOIDmode,
5869 : cond, cop1);
5870 513673 : else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5871 777619 : && ((reversed = reversed_comparison_code_parts
5872 457313 : (cond_code, cond, cop1, NULL))
5873 : != UNKNOWN))
5874 457313 : x = simplify_gen_relational (reversed, mode, VOIDmode,
5875 : cond, cop1);
5876 :
5877 : /* Likewise, we can make the negate of a comparison operation
5878 : if the result values are - STORE_FLAG_VALUE and zero. */
5879 320306 : else if (CONST_INT_P (true_rtx)
5880 221503 : && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5881 46809 : && false_rtx == const0_rtx)
5882 44594 : x = simplify_gen_unary (NEG, mode,
5883 : simplify_gen_relational (cond_code,
5884 : mode, VOIDmode,
5885 : cond, cop1),
5886 : mode);
5887 275712 : else if (CONST_INT_P (false_rtx)
5888 213371 : && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5889 23783 : && true_rtx == const0_rtx
5890 275712 : && ((reversed = reversed_comparison_code_parts
5891 21410 : (cond_code, cond, cop1, NULL))
5892 : != UNKNOWN))
5893 21407 : x = simplify_gen_unary (NEG, mode,
5894 : simplify_gen_relational (reversed,
5895 : mode, VOIDmode,
5896 : cond, cop1),
5897 : mode);
5898 :
5899 1403073 : code = GET_CODE (x);
5900 1403073 : op0_mode = VOIDmode;
5901 : }
5902 : }
5903 : }
5904 :
5905 : /* First see if we can apply the inverse distributive law. */
5906 226134664 : if (code == PLUS || code == MINUS
5907 226134664 : || code == AND || code == IOR || code == XOR)
5908 : {
5909 50315312 : x = apply_distributive_law (x);
5910 50315312 : code = GET_CODE (x);
5911 50315312 : op0_mode = VOIDmode;
5912 : }
5913 :
5914 : /* If CODE is an associative operation not otherwise handled, see if we
5915 : can associate some operands. This can win if they are constants or
5916 : if they are logically related (i.e. (a & b) & a). */
5917 226134664 : if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5918 : || code == AND || code == IOR || code == XOR
5919 : || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5920 54712707 : && ((INTEGRAL_MODE_P (mode) && code != DIV)
5921 4735377 : || (flag_associative_math && FLOAT_MODE_P (mode))))
5922 : {
5923 50616810 : if (GET_CODE (XEXP (x, 0)) == code)
5924 : {
5925 4013148 : rtx other = XEXP (XEXP (x, 0), 0);
5926 4013148 : rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5927 4013148 : rtx inner_op1 = XEXP (x, 1);
5928 4013148 : rtx inner;
5929 :
5930 : /* Make sure we pass the constant operand if any as the second
5931 : one if this is a commutative operation. */
5932 4013148 : if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5933 : std::swap (inner_op0, inner_op1);
5934 4013148 : inner = simplify_binary_operation (code == MINUS ? PLUS
5935 3908837 : : code == DIV ? MULT
5936 : : code,
5937 : mode, inner_op0, inner_op1);
5938 :
5939 : /* For commutative operations, try the other pair if that one
5940 : didn't simplify. */
5941 4013148 : if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5942 : {
5943 3879063 : other = XEXP (XEXP (x, 0), 1);
5944 3879063 : inner = simplify_binary_operation (code, mode,
5945 : XEXP (XEXP (x, 0), 0),
5946 : XEXP (x, 1));
5947 : }
5948 :
5949 3980256 : if (inner)
5950 238021 : return simplify_gen_binary (code, mode, other, inner);
5951 : }
5952 : }
5953 :
5954 : /* A little bit of algebraic simplification here. */
5955 225896643 : switch (code)
5956 : {
5957 22764619 : case MEM:
5958 : /* Ensure that our address has any ASHIFTs converted to MULT in case
5959 : address-recognizing predicates are called later. */
5960 22764619 : temp = make_compound_operation (XEXP (x, 0), MEM);
5961 22764619 : SUBST (XEXP (x, 0), temp);
5962 22764619 : break;
5963 :
5964 9683234 : case SUBREG:
5965 9683234 : if (op0_mode == VOIDmode)
5966 157413 : op0_mode = GET_MODE (SUBREG_REG (x));
5967 :
5968 : /* See if this can be moved to simplify_subreg. */
5969 9683234 : if (CONSTANT_P (SUBREG_REG (x))
5970 45448 : && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5971 : /* Don't call gen_lowpart if the inner mode
5972 : is VOIDmode and we cannot simplify it, as SUBREG without
5973 : inner mode is invalid. */
5974 9705958 : && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5975 0 : || gen_lowpart_common (mode, SUBREG_REG (x))))
5976 22724 : return gen_lowpart (mode, SUBREG_REG (x));
5977 :
5978 9660510 : if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5979 : break;
5980 9660510 : {
5981 9660510 : rtx temp;
5982 19321020 : temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5983 9660510 : SUBREG_BYTE (x));
5984 9660510 : if (temp)
5985 226800650 : return temp;
5986 :
5987 : /* If op is known to have all lower bits zero, the result is zero. */
5988 9014076 : scalar_int_mode int_mode, int_op0_mode;
5989 9014076 : if (!in_dest
5990 5452552 : && is_a <scalar_int_mode> (mode, &int_mode)
5991 5326581 : && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5992 5326581 : && (GET_MODE_PRECISION (int_mode)
5993 5326581 : < GET_MODE_PRECISION (int_op0_mode))
5994 4782031 : && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5995 : SUBREG_BYTE (x))
5996 4288016 : && HWI_COMPUTABLE_MODE_P (int_op0_mode)
5997 4091701 : && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
5998 4091701 : & GET_MODE_MASK (int_mode)) == 0)
5999 9015076 : && !side_effects_p (SUBREG_REG (x)))
6000 1000 : return CONST0_RTX (int_mode);
6001 : }
6002 :
6003 : /* Don't change the mode of the MEM if that would change the meaning
6004 : of the address. */
6005 9013076 : if (MEM_P (SUBREG_REG (x))
6006 9013076 : && (MEM_VOLATILE_P (SUBREG_REG (x))
6007 68169 : || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
6008 68211 : MEM_ADDR_SPACE (SUBREG_REG (x)))))
6009 45274 : return gen_rtx_CLOBBER (mode, const0_rtx);
6010 :
6011 : /* Note that we cannot do any narrowing for non-constants since
6012 : we might have been counting on using the fact that some bits were
6013 : zero. We now do this in the SET. */
6014 :
6015 : break;
6016 :
6017 379990 : case NEG:
6018 379990 : temp = expand_compound_operation (XEXP (x, 0));
6019 :
6020 : /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6021 : replaced by (lshiftrt X C). This will convert
6022 : (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6023 :
6024 379990 : if (GET_CODE (temp) == ASHIFTRT
6025 14504 : && CONST_INT_P (XEXP (temp, 1))
6026 408924 : && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
6027 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
6028 0 : INTVAL (XEXP (temp, 1)));
6029 :
6030 : /* If X has only a single bit that might be nonzero, say, bit I, convert
6031 : (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6032 : MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6033 : (sign_extract X 1 Y). But only do this if TEMP isn't a register
6034 : or a SUBREG of one since we'd be making the expression more
6035 : complex if it was just a register. */
6036 :
6037 379990 : if (!REG_P (temp)
6038 183852 : && ! (GET_CODE (temp) == SUBREG
6039 19380 : && REG_P (SUBREG_REG (temp)))
6040 226940318 : && is_a <scalar_int_mode> (mode, &int_mode)
6041 519658 : && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6042 : {
6043 66924 : rtx temp1 = simplify_shift_const
6044 66924 : (NULL_RTX, ASHIFTRT, int_mode,
6045 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6046 66924 : GET_MODE_PRECISION (int_mode) - 1 - i),
6047 66924 : GET_MODE_PRECISION (int_mode) - 1 - i);
6048 :
6049 : /* If all we did was surround TEMP with the two shifts, we
6050 : haven't improved anything, so don't use it. Otherwise,
6051 : we are better off with TEMP1. */
6052 66924 : if (GET_CODE (temp1) != ASHIFTRT
6053 66486 : || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6054 66448 : || XEXP (XEXP (temp1, 0), 0) != temp)
6055 6490 : return temp1;
6056 : }
6057 : break;
6058 :
6059 9696 : case TRUNCATE:
6060 : /* We can't handle truncation to a partial integer mode here
6061 : because we don't know the real bitsize of the partial
6062 : integer mode. */
6063 9696 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6064 : break;
6065 :
6066 9696 : if (HWI_COMPUTABLE_MODE_P (mode))
6067 0 : SUBST (XEXP (x, 0),
6068 : force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6069 : GET_MODE_MASK (mode), false));
6070 :
6071 : /* We can truncate a constant value and return it. */
6072 9696 : {
6073 9696 : poly_int64 c;
6074 9696 : if (poly_int_rtx_p (XEXP (x, 0), &c))
6075 0 : return gen_int_mode (c, mode);
6076 : }
6077 :
6078 : /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6079 : whose value is a comparison can be replaced with a subreg if
6080 : STORE_FLAG_VALUE permits. */
6081 9696 : if (HWI_COMPUTABLE_MODE_P (mode)
6082 0 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6083 0 : && (temp = get_last_value (XEXP (x, 0)))
6084 0 : && COMPARISON_P (temp)
6085 9696 : && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6086 0 : return gen_lowpart (mode, XEXP (x, 0));
6087 : break;
6088 :
6089 5866 : case CONST:
6090 : /* (const (const X)) can become (const X). Do it this way rather than
6091 : returning the inner CONST since CONST can be shared with a
6092 : REG_EQUAL note. */
6093 5866 : if (GET_CODE (XEXP (x, 0)) == CONST)
6094 0 : SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6095 : break;
6096 :
6097 : case LO_SUM:
6098 : /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6099 : can add in an offset. find_split_point will split this address up
6100 : again if it doesn't match. */
6101 : if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6102 : && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6103 : return XEXP (x, 1);
6104 : break;
6105 :
6106 33995924 : case PLUS:
6107 : /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6108 : when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6109 : bit-field and can be replaced by either a sign_extend or a
6110 : sign_extract. The `and' may be a zero_extend and the two
6111 : <c>, -<c> constants may be reversed. */
6112 33995924 : if (GET_CODE (XEXP (x, 0)) == XOR
6113 33995924 : && is_a <scalar_int_mode> (mode, &int_mode)
6114 13849 : && CONST_INT_P (XEXP (x, 1))
6115 3664 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6116 3017 : && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6117 77 : && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6118 2 : || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6119 39 : && HWI_COMPUTABLE_MODE_P (int_mode)
6120 33995963 : && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6121 0 : && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6122 0 : && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6123 0 : == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6124 39 : || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6125 0 : && known_eq ((GET_MODE_PRECISION
6126 : (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6127 : (unsigned int) i + 1))))
6128 0 : return simplify_shift_const
6129 0 : (NULL_RTX, ASHIFTRT, int_mode,
6130 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6131 : XEXP (XEXP (XEXP (x, 0), 0), 0),
6132 0 : GET_MODE_PRECISION (int_mode) - (i + 1)),
6133 0 : GET_MODE_PRECISION (int_mode) - (i + 1));
6134 :
6135 : /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6136 : can become (ashiftrt (ashift (xor x 1) C) C) where C is
6137 : the bitsize of the mode - 1. This allows simplification of
6138 : "a = (b & 8) == 0;" */
6139 33995924 : if (XEXP (x, 1) == constm1_rtx
6140 735522 : && !REG_P (XEXP (x, 0))
6141 324971 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6142 33754 : && REG_P (SUBREG_REG (XEXP (x, 0))))
6143 34283579 : && is_a <scalar_int_mode> (mode, &int_mode)
6144 34293326 : && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6145 9747 : return simplify_shift_const
6146 9747 : (NULL_RTX, ASHIFTRT, int_mode,
6147 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6148 : gen_rtx_XOR (int_mode, XEXP (x, 0),
6149 : const1_rtx),
6150 9747 : GET_MODE_PRECISION (int_mode) - 1),
6151 19494 : GET_MODE_PRECISION (int_mode) - 1);
6152 :
6153 : /* If we are adding two things that have no bits in common, convert
6154 : the addition into an IOR. This will often be further simplified,
6155 : for example in cases like ((a & 1) + (a & 2)), which can
6156 : become a & 3. */
6157 :
6158 33986177 : if (HWI_COMPUTABLE_MODE_P (mode)
6159 30119053 : && (nonzero_bits (XEXP (x, 0), mode)
6160 30119053 : & nonzero_bits (XEXP (x, 1), mode)) == 0)
6161 : {
6162 : /* Try to simplify the expression further. */
6163 334981 : rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6164 334981 : temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6165 :
6166 : /* If we could, great. If not, do not go ahead with the IOR
6167 : replacement, since PLUS appears in many special purpose
6168 : address arithmetic instructions. */
6169 334981 : if (GET_CODE (temp) != CLOBBER
6170 334981 : && (GET_CODE (temp) != IOR
6171 329925 : || ((XEXP (temp, 0) != XEXP (x, 0)
6172 328787 : || XEXP (temp, 1) != XEXP (x, 1))
6173 1138 : && (XEXP (temp, 0) != XEXP (x, 1)
6174 0 : || XEXP (temp, 1) != XEXP (x, 0)))))
6175 : return temp;
6176 : }
6177 :
6178 : /* Canonicalize x + x into x << 1. */
6179 33979983 : if (GET_MODE_CLASS (mode) == MODE_INT
6180 30435717 : && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6181 33983169 : && !side_effects_p (XEXP (x, 0)))
6182 3181 : return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6183 :
6184 : break;
6185 :
6186 4169717 : case MINUS:
6187 : /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6188 : (and <foo> (const_int pow2-1)) */
6189 4169717 : if (is_a <scalar_int_mode> (mode, &int_mode)
6190 3536518 : && GET_CODE (XEXP (x, 1)) == AND
6191 99376 : && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6192 96653 : && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6193 48072 : && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6194 0 : return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6195 0 : -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6196 : break;
6197 :
6198 3185919 : case MULT:
6199 : /* If we have (mult (plus A B) C), apply the distributive law and then
6200 : the inverse distributive law to see if things simplify. This
6201 : occurs mostly in addresses, often when unrolling loops. */
6202 :
6203 3185919 : if (GET_CODE (XEXP (x, 0)) == PLUS)
6204 : {
6205 280500 : rtx result = distribute_and_simplify_rtx (x, 0);
6206 280500 : if (result)
6207 : return result;
6208 : }
6209 :
6210 : /* Try simplify a*(b/c) as (a*b)/c. */
6211 3185105 : if (FLOAT_MODE_P (mode) && flag_associative_math
6212 203040 : && GET_CODE (XEXP (x, 0)) == DIV)
6213 : {
6214 245 : rtx tem = simplify_binary_operation (MULT, mode,
6215 : XEXP (XEXP (x, 0), 0),
6216 : XEXP (x, 1));
6217 245 : if (tem)
6218 32 : return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6219 : }
6220 : break;
6221 :
6222 119275 : case UDIV:
6223 : /* If this is a divide by a power of two, treat it as a shift if
6224 : its first operand is a shift. */
6225 119275 : if (is_a <scalar_int_mode> (mode, &int_mode)
6226 119275 : && CONST_INT_P (XEXP (x, 1))
6227 1993 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6228 0 : && (GET_CODE (XEXP (x, 0)) == ASHIFT
6229 0 : || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6230 0 : || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6231 0 : || GET_CODE (XEXP (x, 0)) == ROTATE
6232 0 : || GET_CODE (XEXP (x, 0)) == ROTATERT))
6233 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6234 0 : XEXP (x, 0), i);
6235 : break;
6236 :
6237 18367655 : case EQ: case NE:
6238 18367655 : case GT: case GTU: case GE: case GEU:
6239 18367655 : case LT: case LTU: case LE: case LEU:
6240 18367655 : case UNEQ: case LTGT:
6241 18367655 : case UNGT: case UNGE:
6242 18367655 : case UNLT: case UNLE:
6243 18367655 : case UNORDERED: case ORDERED:
6244 : /* If the first operand is a condition code, we can't do anything
6245 : with it. */
6246 18367655 : if (GET_CODE (XEXP (x, 0)) == COMPARE
6247 18367655 : || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6248 : {
6249 13816428 : rtx op0 = XEXP (x, 0);
6250 13816428 : rtx op1 = XEXP (x, 1);
6251 13816428 : enum rtx_code new_code;
6252 :
6253 13816428 : if (GET_CODE (op0) == COMPARE)
6254 0 : op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6255 :
6256 : /* Simplify our comparison, if possible. */
6257 13816428 : new_code = simplify_comparison (code, &op0, &op1);
6258 :
6259 : /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6260 : if only the low-order bit is possibly nonzero in X (such as when
6261 : X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6262 : (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6263 : known to be either 0 or -1, NE becomes a NEG and EQ becomes
6264 : (plus X 1).
6265 :
6266 : Remove any ZERO_EXTRACT we made when thinking this was a
6267 : comparison. It may now be simpler to use, e.g., an AND. If a
6268 : ZERO_EXTRACT is indeed appropriate, it will be placed back by
6269 : the call to make_compound_operation in the SET case.
6270 :
6271 : Don't apply these optimizations if the caller would
6272 : prefer a comparison rather than a value.
6273 : E.g., for the condition in an IF_THEN_ELSE most targets need
6274 : an explicit comparison. */
6275 :
6276 13816428 : if (in_cond)
6277 : ;
6278 :
6279 2181113 : else if (STORE_FLAG_VALUE == 1
6280 : && new_code == NE
6281 2618935 : && is_int_mode (mode, &int_mode)
6282 438037 : && op1 == const0_rtx
6283 227168 : && int_mode == GET_MODE (op0)
6284 2273489 : && nonzero_bits (op0, int_mode) == 1)
6285 215 : return gen_lowpart (int_mode,
6286 483233 : expand_compound_operation (op0));
6287 :
6288 2180898 : else if (STORE_FLAG_VALUE == 1
6289 : && new_code == NE
6290 2617691 : && is_int_mode (mode, &int_mode)
6291 437822 : && op1 == const0_rtx
6292 226953 : && int_mode == GET_MODE (op0)
6293 2273059 : && (num_sign_bit_copies (op0, int_mode)
6294 92161 : == GET_MODE_PRECISION (int_mode)))
6295 : {
6296 1029 : op0 = expand_compound_operation (op0);
6297 1029 : return simplify_gen_unary (NEG, int_mode,
6298 1029 : gen_lowpart (int_mode, op0),
6299 1029 : int_mode);
6300 : }
6301 :
6302 2179869 : else if (STORE_FLAG_VALUE == 1
6303 : && new_code == EQ
6304 2509197 : && is_int_mode (mode, &int_mode)
6305 331688 : && op1 == const0_rtx
6306 136587 : && int_mode == GET_MODE (op0)
6307 2223898 : && nonzero_bits (op0, int_mode) == 1)
6308 : {
6309 2360 : op0 = expand_compound_operation (op0);
6310 2360 : return simplify_gen_binary (XOR, int_mode,
6311 2360 : gen_lowpart (int_mode, op0),
6312 2360 : const1_rtx);
6313 : }
6314 :
6315 2177509 : else if (STORE_FLAG_VALUE == 1
6316 : && new_code == EQ
6317 14141577 : && is_int_mode (mode, &int_mode)
6318 329328 : && op1 == const0_rtx
6319 134227 : && int_mode == GET_MODE (op0)
6320 2219178 : && (num_sign_bit_copies (op0, int_mode)
6321 41669 : == GET_MODE_PRECISION (int_mode)))
6322 : {
6323 575 : op0 = expand_compound_operation (op0);
6324 575 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6325 : }
6326 :
6327 : /* If STORE_FLAG_VALUE is -1, we have cases similar to
6328 : those above. */
6329 13812249 : if (in_cond)
6330 : ;
6331 :
6332 13812249 : else if (STORE_FLAG_VALUE == -1
6333 : && new_code == NE
6334 : && is_int_mode (mode, &int_mode)
6335 : && op1 == const0_rtx
6336 : && int_mode == GET_MODE (op0)
6337 : && (num_sign_bit_copies (op0, int_mode)
6338 : == GET_MODE_PRECISION (int_mode)))
6339 : return gen_lowpart (int_mode, expand_compound_operation (op0));
6340 :
6341 13812249 : else if (STORE_FLAG_VALUE == -1
6342 : && new_code == NE
6343 : && is_int_mode (mode, &int_mode)
6344 : && op1 == const0_rtx
6345 : && int_mode == GET_MODE (op0)
6346 : && nonzero_bits (op0, int_mode) == 1)
6347 : {
6348 : op0 = expand_compound_operation (op0);
6349 : return simplify_gen_unary (NEG, int_mode,
6350 : gen_lowpart (int_mode, op0),
6351 : int_mode);
6352 : }
6353 :
6354 13812249 : else if (STORE_FLAG_VALUE == -1
6355 : && new_code == EQ
6356 : && is_int_mode (mode, &int_mode)
6357 : && op1 == const0_rtx
6358 : && int_mode == GET_MODE (op0)
6359 : && (num_sign_bit_copies (op0, int_mode)
6360 : == GET_MODE_PRECISION (int_mode)))
6361 : {
6362 : op0 = expand_compound_operation (op0);
6363 : return simplify_gen_unary (NOT, int_mode,
6364 : gen_lowpart (int_mode, op0),
6365 : int_mode);
6366 : }
6367 :
6368 : /* If X is 0/1, (eq X 0) is X-1. */
6369 13812249 : else if (STORE_FLAG_VALUE == -1
6370 : && new_code == EQ
6371 : && is_int_mode (mode, &int_mode)
6372 : && op1 == const0_rtx
6373 : && int_mode == GET_MODE (op0)
6374 : && nonzero_bits (op0, int_mode) == 1)
6375 : {
6376 : op0 = expand_compound_operation (op0);
6377 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6378 : }
6379 :
6380 : /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6381 : one bit that might be nonzero, we can convert (ne x 0) to
6382 : (ashift x c) where C puts the bit in the sign bit. Remove any
6383 : AND with STORE_FLAG_VALUE when we are done, since we are only
6384 : going to test the sign bit. */
6385 13812249 : if (new_code == NE
6386 14244763 : && is_int_mode (mode, &int_mode)
6387 436873 : && HWI_COMPUTABLE_MODE_P (int_mode)
6388 432514 : && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6389 0 : && op1 == const0_rtx
6390 0 : && int_mode == GET_MODE (op0)
6391 13812249 : && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6392 : {
6393 0 : x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6394 : expand_compound_operation (op0),
6395 0 : GET_MODE_PRECISION (int_mode) - 1 - i);
6396 0 : if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6397 0 : return XEXP (x, 0);
6398 : else
6399 : return x;
6400 : }
6401 :
6402 : /* If the code changed, return a whole new comparison.
6403 : We also need to avoid using SUBST in cases where
6404 : simplify_comparison has widened a comparison with a CONST_INT,
6405 : since in that case the wider CONST_INT may fail the sanity
6406 : checks in do_SUBST. */
6407 13812249 : if (new_code != code
6408 13340917 : || (CONST_INT_P (op1)
6409 7547692 : && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6410 9004 : && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6411 479054 : return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6412 :
6413 : /* Otherwise, keep this operation, but maybe change its operands.
6414 : This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6415 13333195 : SUBST (XEXP (x, 0), op0);
6416 13333195 : SUBST (XEXP (x, 1), op1);
6417 : }
6418 : break;
6419 :
6420 13410062 : case IF_THEN_ELSE:
6421 13410062 : return simplify_if_then_else (x);
6422 :
6423 4818681 : case ZERO_EXTRACT:
6424 4818681 : case SIGN_EXTRACT:
6425 4818681 : case ZERO_EXTEND:
6426 4818681 : case SIGN_EXTEND:
6427 : /* If we are processing SET_DEST, we are done. */
6428 4818681 : if (in_dest)
6429 : return x;
6430 :
6431 4815884 : return expand_compound_operation (x);
6432 :
6433 47732129 : case SET:
6434 47732129 : return simplify_set (x);
6435 :
6436 11312173 : case AND:
6437 11312173 : case IOR:
6438 11312173 : return simplify_logical (x);
6439 :
6440 13457232 : case ASHIFT:
6441 13457232 : case LSHIFTRT:
6442 13457232 : case ASHIFTRT:
6443 13457232 : case ROTATE:
6444 13457232 : case ROTATERT:
6445 : /* If this is a shift by a constant amount, simplify it. */
6446 13457232 : if (CONST_INT_P (XEXP (x, 1)))
6447 12962602 : return simplify_shift_const (x, code, mode, XEXP (x, 0),
6448 12962602 : INTVAL (XEXP (x, 1)));
6449 :
6450 : else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6451 : SUBST (XEXP (x, 1),
6452 : force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6453 : (HOST_WIDE_INT_1U
6454 : << exact_log2 (GET_MODE_UNIT_BITSIZE
6455 : (GET_MODE (x)))) - 1, false));
6456 : break;
6457 2137306 : case VEC_SELECT:
6458 2137306 : {
6459 2137306 : rtx trueop0 = XEXP (x, 0);
6460 2137306 : mode = GET_MODE (trueop0);
6461 2137306 : rtx trueop1 = XEXP (x, 1);
6462 : /* If we select a low-part subreg, return that. */
6463 2137306 : if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6464 : {
6465 1187 : rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6466 1187 : if (new_rtx != NULL_RTX)
6467 1187 : return new_rtx;
6468 : }
6469 : }
6470 :
6471 : default:
6472 : break;
6473 : }
6474 :
6475 : return x;
6476 : }
6477 :
6478 : /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6479 :
6480 : static rtx
6481 13410062 : simplify_if_then_else (rtx x)
6482 : {
6483 13410062 : machine_mode mode = GET_MODE (x);
6484 13410062 : rtx cond = XEXP (x, 0);
6485 13410062 : rtx true_rtx = XEXP (x, 1);
6486 13410062 : rtx false_rtx = XEXP (x, 2);
6487 13410062 : enum rtx_code true_code = GET_CODE (cond);
6488 13410062 : bool comparison_p = COMPARISON_P (cond);
6489 13410062 : rtx temp;
6490 13410062 : int i;
6491 13410062 : enum rtx_code false_code;
6492 13410062 : rtx reversed;
6493 13410062 : scalar_int_mode int_mode, inner_mode;
6494 :
6495 : /* Simplify storing of the truth value. */
6496 13410062 : if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6497 0 : return simplify_gen_relational (true_code, mode, VOIDmode,
6498 0 : XEXP (cond, 0), XEXP (cond, 1));
6499 :
6500 : /* Also when the truth value has to be reversed. */
6501 13409517 : if (comparison_p
6502 13409517 : && true_rtx == const0_rtx && false_rtx == const_true_rtx
6503 0 : && (reversed = reversed_comparison (cond, mode)))
6504 : return reversed;
6505 :
6506 : /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6507 : in it is being compared against certain values. Get the true and false
6508 : comparisons and see if that says anything about the value of each arm. */
6509 :
6510 13410062 : if (comparison_p
6511 13409517 : && ((false_code = reversed_comparison_code (cond, NULL))
6512 : != UNKNOWN)
6513 26665538 : && REG_P (XEXP (cond, 0)))
6514 : {
6515 8260087 : HOST_WIDE_INT nzb;
6516 8260087 : rtx from = XEXP (cond, 0);
6517 8260087 : rtx true_val = XEXP (cond, 1);
6518 8260087 : rtx false_val = true_val;
6519 8260087 : bool swapped = false;
6520 :
6521 : /* If FALSE_CODE is EQ, swap the codes and arms. */
6522 :
6523 8260087 : if (false_code == EQ)
6524 : {
6525 2990045 : swapped = true, true_code = EQ, false_code = NE;
6526 2990045 : std::swap (true_rtx, false_rtx);
6527 : }
6528 :
6529 8260087 : scalar_int_mode from_mode;
6530 8260087 : if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6531 : {
6532 : /* If we are comparing against zero and the expression being
6533 : tested has only a single bit that might be nonzero, that is
6534 : its value when it is not equal to zero. Similarly if it is
6535 : known to be -1 or 0. */
6536 6884347 : if (true_code == EQ
6537 4989879 : && true_val == const0_rtx
6538 8967976 : && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6539 : {
6540 239475 : false_code = EQ;
6541 239475 : false_val = gen_int_mode (nzb, from_mode);
6542 : }
6543 6644872 : else if (true_code == EQ
6544 4750404 : && true_val == const0_rtx
6545 8489026 : && (num_sign_bit_copies (from, from_mode)
6546 1844154 : == GET_MODE_PRECISION (from_mode)))
6547 : {
6548 715 : false_code = EQ;
6549 715 : false_val = constm1_rtx;
6550 : }
6551 : }
6552 :
6553 : /* Now simplify an arm if we know the value of the register in the
6554 : branch and it is used in the arm. Be careful due to the potential
6555 : of locally-shared RTL. */
6556 :
6557 8260087 : if (reg_mentioned_p (from, true_rtx))
6558 317890 : true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6559 : from, true_val),
6560 : pc_rtx, pc_rtx, false, false, false);
6561 8260087 : if (reg_mentioned_p (from, false_rtx))
6562 133848 : false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6563 : from, false_val),
6564 : pc_rtx, pc_rtx, false, false, false);
6565 :
6566 13530129 : SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6567 13530129 : SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6568 :
6569 8260087 : true_rtx = XEXP (x, 1);
6570 8260087 : false_rtx = XEXP (x, 2);
6571 8260087 : true_code = GET_CODE (cond);
6572 : }
6573 :
6574 : /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6575 : reversed, do so to avoid needing two sets of patterns for
6576 : subtract-and-branch insns. Similarly if we have a constant in the true
6577 : arm, the false arm is the same as the first operand of the comparison, or
6578 : the false arm is more complicated than the true arm. */
6579 :
6580 13410062 : if (comparison_p
6581 13409517 : && reversed_comparison_code (cond, NULL) != UNKNOWN
6582 26665538 : && (true_rtx == pc_rtx
6583 13255476 : || (CONSTANT_P (true_rtx)
6584 10952830 : && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6585 13217472 : || true_rtx == const0_rtx
6586 13214544 : || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6587 13156458 : || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6588 14081 : && !OBJECT_P (false_rtx))
6589 13154240 : || reg_mentioned_p (true_rtx, false_rtx)
6590 13154152 : || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6591 : {
6592 156557 : SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6593 156557 : SUBST (XEXP (x, 1), false_rtx);
6594 156557 : SUBST (XEXP (x, 2), true_rtx);
6595 :
6596 156557 : std::swap (true_rtx, false_rtx);
6597 156557 : cond = XEXP (x, 0);
6598 :
6599 : /* It is possible that the conditional has been simplified out. */
6600 156557 : true_code = GET_CODE (cond);
6601 156557 : comparison_p = COMPARISON_P (cond);
6602 : }
6603 :
6604 : /* If the two arms are identical, we don't need the comparison. */
6605 :
6606 13410062 : if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6607 : return true_rtx;
6608 :
6609 : /* Convert a == b ? b : a to "a". */
6610 3946761 : if (true_code == EQ && ! side_effects_p (cond)
6611 3927773 : && !HONOR_NANS (mode)
6612 3924714 : && rtx_equal_p (XEXP (cond, 0), false_rtx)
6613 13410521 : && rtx_equal_p (XEXP (cond, 1), true_rtx))
6614 : return false_rtx;
6615 4851040 : else if (true_code == NE && ! side_effects_p (cond)
6616 4802396 : && !HONOR_NANS (mode)
6617 4648629 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6618 13477654 : && rtx_equal_p (XEXP (cond, 1), false_rtx))
6619 : return true_rtx;
6620 :
6621 : /* Look for cases where we have (abs x) or (neg (abs X)). */
6622 :
6623 13410056 : if (GET_MODE_CLASS (mode) == MODE_INT
6624 2107430 : && comparison_p
6625 2107410 : && XEXP (cond, 1) == const0_rtx
6626 1618849 : && GET_CODE (false_rtx) == NEG
6627 144 : && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6628 20 : && rtx_equal_p (true_rtx, XEXP (cond, 0))
6629 13410076 : && ! side_effects_p (true_rtx))
6630 20 : switch (true_code)
6631 : {
6632 20 : case GT:
6633 20 : case GE:
6634 20 : return simplify_gen_unary (ABS, mode, true_rtx, mode);
6635 0 : case LT:
6636 0 : case LE:
6637 0 : return
6638 0 : simplify_gen_unary (NEG, mode,
6639 : simplify_gen_unary (ABS, mode, true_rtx, mode),
6640 0 : mode);
6641 : default:
6642 : break;
6643 : }
6644 :
6645 : /* Look for MIN or MAX. */
6646 :
6647 13410036 : if ((! FLOAT_MODE_P (mode)
6648 170122 : || (flag_unsafe_math_optimizations
6649 438 : && !HONOR_NANS (mode)
6650 438 : && !HONOR_SIGNED_ZEROS (mode)))
6651 13240352 : && comparison_p
6652 13239975 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6653 139562 : && rtx_equal_p (XEXP (cond, 1), false_rtx)
6654 13403 : && ! side_effects_p (cond))
6655 13399 : switch (true_code)
6656 : {
6657 5054 : case GE:
6658 5054 : case GT:
6659 5054 : return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6660 4575 : case LE:
6661 4575 : case LT:
6662 4575 : return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6663 2862 : case GEU:
6664 2862 : case GTU:
6665 2862 : return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6666 908 : case LEU:
6667 908 : case LTU:
6668 908 : return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6669 : default:
6670 : break;
6671 : }
6672 :
6673 : /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6674 : second operand is zero, this can be done as (OP Z (mult COND C2)) where
6675 : C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6676 : SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6677 : We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6678 : neither 1 or -1, but it isn't worth checking for. */
6679 :
6680 13396637 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6681 : && comparison_p
6682 15416517 : && is_int_mode (mode, &int_mode)
6683 15490650 : && ! side_effects_p (x))
6684 : {
6685 2089954 : rtx t = make_compound_operation (true_rtx, SET);
6686 2089954 : rtx f = make_compound_operation (false_rtx, SET);
6687 2089954 : rtx cond_op0 = XEXP (cond, 0);
6688 2089954 : rtx cond_op1 = XEXP (cond, 1);
6689 2089954 : enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6690 2089954 : scalar_int_mode m = int_mode;
6691 2089954 : rtx z = 0, c1 = NULL_RTX;
6692 :
6693 2089954 : if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6694 : || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6695 : || GET_CODE (t) == ASHIFT
6696 : || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6697 191401 : && rtx_equal_p (XEXP (t, 0), f))
6698 65694 : c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6699 :
6700 : /* If an identity-zero op is commutative, check whether there
6701 : would be a match if we swapped the operands. */
6702 1962561 : else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6703 1951664 : || GET_CODE (t) == XOR)
6704 2035859 : && rtx_equal_p (XEXP (t, 1), f))
6705 8439 : c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6706 2015821 : else if (GET_CODE (t) == SIGN_EXTEND
6707 2532 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6708 2532 : && (GET_CODE (XEXP (t, 0)) == PLUS
6709 2532 : || GET_CODE (XEXP (t, 0)) == MINUS
6710 : || GET_CODE (XEXP (t, 0)) == IOR
6711 : || GET_CODE (XEXP (t, 0)) == XOR
6712 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6713 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6714 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6715 111 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6716 66 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6717 66 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6718 2015821 : && (num_sign_bit_copies (f, GET_MODE (f))
6719 0 : > (unsigned int)
6720 0 : (GET_MODE_PRECISION (int_mode)
6721 0 : - GET_MODE_PRECISION (inner_mode))))
6722 : {
6723 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6724 0 : extend_op = SIGN_EXTEND;
6725 0 : m = inner_mode;
6726 : }
6727 2015821 : else if (GET_CODE (t) == SIGN_EXTEND
6728 2532 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6729 2532 : && (GET_CODE (XEXP (t, 0)) == PLUS
6730 2439 : || GET_CODE (XEXP (t, 0)) == IOR
6731 2435 : || GET_CODE (XEXP (t, 0)) == XOR)
6732 97 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6733 4 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6734 4 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6735 2015825 : && (num_sign_bit_copies (f, GET_MODE (f))
6736 4 : > (unsigned int)
6737 4 : (GET_MODE_PRECISION (int_mode)
6738 4 : - GET_MODE_PRECISION (inner_mode))))
6739 : {
6740 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6741 0 : extend_op = SIGN_EXTEND;
6742 0 : m = inner_mode;
6743 : }
6744 2015821 : else if (GET_CODE (t) == ZERO_EXTEND
6745 4695 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6746 4695 : && (GET_CODE (XEXP (t, 0)) == PLUS
6747 4695 : || GET_CODE (XEXP (t, 0)) == MINUS
6748 : || GET_CODE (XEXP (t, 0)) == IOR
6749 : || GET_CODE (XEXP (t, 0)) == XOR
6750 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6751 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6752 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6753 1375 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6754 91 : && HWI_COMPUTABLE_MODE_P (int_mode)
6755 91 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6756 91 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6757 2015821 : && ((nonzero_bits (f, GET_MODE (f))
6758 0 : & ~GET_MODE_MASK (inner_mode))
6759 : == 0))
6760 : {
6761 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6762 0 : extend_op = ZERO_EXTEND;
6763 0 : m = inner_mode;
6764 : }
6765 2015821 : else if (GET_CODE (t) == ZERO_EXTEND
6766 4695 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6767 4695 : && (GET_CODE (XEXP (t, 0)) == PLUS
6768 3880 : || GET_CODE (XEXP (t, 0)) == IOR
6769 3880 : || GET_CODE (XEXP (t, 0)) == XOR)
6770 815 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6771 16 : && HWI_COMPUTABLE_MODE_P (int_mode)
6772 16 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6773 16 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6774 2015821 : && ((nonzero_bits (f, GET_MODE (f))
6775 0 : & ~GET_MODE_MASK (inner_mode))
6776 : == 0))
6777 : {
6778 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6779 0 : extend_op = ZERO_EXTEND;
6780 0 : m = inner_mode;
6781 : }
6782 :
6783 74133 : if (z)
6784 : {
6785 74133 : machine_mode cm = m;
6786 74133 : if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6787 2205 : && GET_MODE (c1) != VOIDmode)
6788 1615 : cm = GET_MODE (c1);
6789 74133 : temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6790 : cond_op0, cond_op1),
6791 : pc_rtx, pc_rtx, false, false, false);
6792 74133 : temp = simplify_gen_binary (MULT, cm, temp,
6793 : simplify_gen_binary (MULT, cm, c1,
6794 : const_true_rtx));
6795 74133 : temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6796 74133 : temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6797 :
6798 74133 : if (extend_op != UNKNOWN)
6799 0 : temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6800 :
6801 13410062 : return temp;
6802 : }
6803 : }
6804 :
6805 : /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6806 : 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6807 : negation of a single bit, we can convert this operation to a shift. We
6808 : can actually do this more generally, but it doesn't seem worth it. */
6809 :
6810 13322504 : if (true_code == NE
6811 13322504 : && is_a <scalar_int_mode> (mode, &int_mode)
6812 414670 : && XEXP (cond, 1) == const0_rtx
6813 306560 : && false_rtx == const0_rtx
6814 49082 : && CONST_INT_P (true_rtx)
6815 13324543 : && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6816 0 : && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6817 2039 : || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6818 2039 : == GET_MODE_PRECISION (int_mode))
6819 0 : && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6820 0 : return
6821 0 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6822 0 : gen_lowpart (int_mode, XEXP (cond, 0)), i);
6823 :
6824 : /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6825 : non-zero bit in A is C1. */
6826 4836968 : if (true_code == NE && XEXP (cond, 1) == const0_rtx
6827 2288569 : && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6828 13412101 : && is_a <scalar_int_mode> (mode, &int_mode)
6829 2039 : && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6830 35 : && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6831 35 : == nonzero_bits (XEXP (cond, 0), inner_mode)
6832 13322504 : && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6833 : {
6834 0 : rtx val = XEXP (cond, 0);
6835 0 : if (inner_mode == int_mode)
6836 : return val;
6837 0 : else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6838 0 : return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6839 : }
6840 :
6841 : return x;
6842 : }
6843 :
6844 : /* Simplify X, a SET expression. Return the new expression. */
6845 :
6846 : static rtx
6847 47732129 : simplify_set (rtx x)
6848 : {
6849 47732129 : rtx src = SET_SRC (x);
6850 47732129 : rtx dest = SET_DEST (x);
6851 106908672 : machine_mode mode
6852 47732129 : = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6853 47732129 : rtx_insn *other_insn;
6854 47732129 : rtx *cc_use;
6855 47732129 : scalar_int_mode int_mode;
6856 :
6857 : /* (set (pc) (return)) gets written as (return). */
6858 47732129 : if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6859 : return src;
6860 :
6861 : /* Now that we know for sure which bits of SRC we are using, see if we can
6862 : simplify the expression for the object knowing that we only need the
6863 : low-order bits. */
6864 :
6865 47732129 : if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6866 : {
6867 21235936 : src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6868 21235936 : SUBST (SET_SRC (x), src);
6869 : }
6870 :
6871 : /* If the source is a COMPARE, look for the use of the comparison result
6872 : and try to simplify it unless we already have used undobuf.other_insn. */
6873 40988895 : if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6874 6743234 : && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6875 6128390 : && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6876 6128390 : && COMPARISON_P (*cc_use)
6877 53860007 : && rtx_equal_p (XEXP (*cc_use, 0), dest))
6878 : {
6879 6126305 : enum rtx_code old_code = GET_CODE (*cc_use);
6880 6126305 : enum rtx_code new_code;
6881 6126305 : rtx op0, op1, tmp;
6882 6126305 : bool other_changed = false;
6883 6126305 : rtx inner_compare = NULL_RTX;
6884 6126305 : machine_mode compare_mode = GET_MODE (dest);
6885 :
6886 6126305 : if (GET_CODE (src) == COMPARE)
6887 : {
6888 5678478 : op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6889 5678478 : if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6890 : {
6891 0 : inner_compare = op0;
6892 0 : op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6893 : }
6894 : }
6895 : else
6896 447827 : op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6897 :
6898 6126305 : tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6899 : op0, op1);
6900 6126305 : if (!tmp)
6901 : new_code = old_code;
6902 485523 : else if (!CONSTANT_P (tmp))
6903 : {
6904 480448 : new_code = GET_CODE (tmp);
6905 480448 : op0 = XEXP (tmp, 0);
6906 480448 : op1 = XEXP (tmp, 1);
6907 : }
6908 : else
6909 : {
6910 5075 : rtx pat = PATTERN (other_insn);
6911 5075 : undobuf.other_insn = other_insn;
6912 5075 : SUBST (*cc_use, tmp);
6913 :
6914 : /* Attempt to simplify CC user. */
6915 5075 : if (GET_CODE (pat) == SET)
6916 : {
6917 4575 : rtx new_rtx = simplify_rtx (SET_SRC (pat));
6918 4575 : if (new_rtx != NULL_RTX)
6919 4039 : SUBST (SET_SRC (pat), new_rtx);
6920 : }
6921 :
6922 : /* Convert X into a no-op move. */
6923 5075 : SUBST (SET_DEST (x), pc_rtx);
6924 5075 : SUBST (SET_SRC (x), pc_rtx);
6925 5075 : return x;
6926 : }
6927 :
6928 : /* Simplify our comparison, if possible. */
6929 6121230 : new_code = simplify_comparison (new_code, &op0, &op1);
6930 :
6931 : #ifdef SELECT_CC_MODE
6932 : /* If this machine has CC modes other than CCmode, check to see if we
6933 : need to use a different CC mode here. */
6934 6121230 : if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6935 684085 : compare_mode = GET_MODE (op0);
6936 5437145 : else if (inner_compare
6937 0 : && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6938 0 : && new_code == old_code
6939 0 : && op0 == XEXP (inner_compare, 0)
6940 0 : && op1 == XEXP (inner_compare, 1))
6941 0 : compare_mode = GET_MODE (inner_compare);
6942 : else
6943 5437145 : compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6944 :
6945 : /* If the mode changed, we have to change SET_DEST, the mode in the
6946 : compare, and the mode in the place SET_DEST is used. If SET_DEST is
6947 : a hard register, just build new versions with the proper mode. If it
6948 : is a pseudo, we lose unless it is only time we set the pseudo, in
6949 : which case we can safely change its mode. */
6950 6121230 : if (compare_mode != GET_MODE (dest))
6951 : {
6952 211686 : if (can_change_dest_mode (dest, 0, compare_mode))
6953 : {
6954 211686 : unsigned int regno = REGNO (dest);
6955 211686 : rtx new_dest;
6956 :
6957 211686 : if (regno < FIRST_PSEUDO_REGISTER)
6958 211686 : new_dest = gen_rtx_REG (compare_mode, regno);
6959 : else
6960 : {
6961 0 : subst_mode (regno, compare_mode);
6962 0 : new_dest = regno_reg_rtx[regno];
6963 : }
6964 :
6965 211686 : SUBST (SET_DEST (x), new_dest);
6966 211686 : SUBST (XEXP (*cc_use, 0), new_dest);
6967 211686 : other_changed = true;
6968 :
6969 211686 : dest = new_dest;
6970 : }
6971 : }
6972 : #endif /* SELECT_CC_MODE */
6973 :
6974 : /* If the code changed, we have to build a new comparison in
6975 : undobuf.other_insn. */
6976 6121230 : if (new_code != old_code)
6977 : {
6978 627935 : bool other_changed_previously = other_changed;
6979 627935 : unsigned HOST_WIDE_INT mask;
6980 627935 : rtx old_cc_use = *cc_use;
6981 :
6982 627935 : SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6983 : dest, const0_rtx));
6984 627935 : other_changed = true;
6985 :
6986 : /* If the only change we made was to change an EQ into an NE or
6987 : vice versa, OP0 has only one bit that might be nonzero, and OP1
6988 : is zero, check if changing the user of the condition code will
6989 : produce a valid insn. If it won't, we can keep the original code
6990 : in that insn by surrounding our operation with an XOR. */
6991 :
6992 627935 : if (((old_code == NE && new_code == EQ)
6993 588044 : || (old_code == EQ && new_code == NE))
6994 89198 : && ! other_changed_previously && op1 == const0_rtx
6995 86455 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6996 637719 : && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
6997 : {
6998 9773 : rtx pat = PATTERN (other_insn), note = 0;
6999 :
7000 9773 : if ((recog_for_combine (&pat, other_insn, ¬e) < 0
7001 9773 : && ! check_asm_operands (pat)))
7002 : {
7003 3 : *cc_use = old_cc_use;
7004 3 : other_changed = false;
7005 :
7006 3 : op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
7007 3 : gen_int_mode (mask,
7008 3 : GET_MODE (op0)));
7009 : }
7010 : }
7011 : }
7012 :
7013 5503068 : if (other_changed)
7014 645255 : undobuf.other_insn = other_insn;
7015 :
7016 : /* Don't generate a compare of a CC with 0, just use that CC. */
7017 6121230 : if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
7018 : {
7019 684085 : SUBST (SET_SRC (x), op0);
7020 684085 : src = SET_SRC (x);
7021 : }
7022 : /* Otherwise, if we didn't previously have the same COMPARE we
7023 : want, create it from scratch. */
7024 5437145 : else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
7025 5316678 : || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
7026 : {
7027 1390558 : SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
7028 1390558 : src = SET_SRC (x);
7029 : }
7030 : }
7031 : else
7032 : {
7033 : /* Get SET_SRC in a form where we have placed back any
7034 : compound expressions. Then do the checks below. */
7035 41605824 : src = make_compound_operation (src, SET);
7036 41605824 : SUBST (SET_SRC (x), src);
7037 : }
7038 :
7039 : /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7040 : and X being a REG or (subreg (reg)), we may be able to convert this to
7041 : (set (subreg:m2 x) (op)).
7042 :
7043 : We can always do this if M1 is narrower than M2 because that means that
7044 : we only care about the low bits of the result.
7045 :
7046 : However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7047 : perform a narrower operation than requested since the high-order bits will
7048 : be undefined. On machine where it is defined, this transformation is safe
7049 : as long as M1 and M2 have the same number of words. */
7050 :
7051 427686 : if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7052 411879 : && !OBJECT_P (SUBREG_REG (src))
7053 : && (known_equal_after_align_up
7054 265965 : (GET_MODE_SIZE (GET_MODE (src)),
7055 531930 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7056 265965 : UNITS_PER_WORD))
7057 237500 : && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7058 225196 : && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7059 231 : && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7060 : GET_MODE (SUBREG_REG (src)),
7061 : GET_MODE (src)))
7062 47952019 : && (REG_P (dest)
7063 123997 : || (GET_CODE (dest) == SUBREG
7064 308 : && REG_P (SUBREG_REG (dest)))))
7065 : {
7066 101276 : SUBST (SET_DEST (x),
7067 : gen_lowpart (GET_MODE (SUBREG_REG (src)),
7068 : dest));
7069 101276 : SUBST (SET_SRC (x), SUBREG_REG (src));
7070 :
7071 101276 : src = SET_SRC (x), dest = SET_DEST (x);
7072 : }
7073 :
7074 : /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7075 : would require a paradoxical subreg. Replace the subreg with a
7076 : zero_extend to avoid the reload that would otherwise be required.
7077 : Don't do this unless we have a scalar integer mode, otherwise the
7078 : transformation is incorrect. */
7079 :
7080 47727054 : enum rtx_code extend_op;
7081 47727054 : if (paradoxical_subreg_p (src)
7082 : && MEM_P (SUBREG_REG (src))
7083 : && SCALAR_INT_MODE_P (GET_MODE (src))
7084 : && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7085 : {
7086 : SUBST (SET_SRC (x),
7087 : gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7088 :
7089 : src = SET_SRC (x);
7090 : }
7091 :
7092 : /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7093 : are comparing an item known to be 0 or -1 against 0, use a logical
7094 : operation instead. Check for one of the arms being an IOR of the other
7095 : arm with some value. We compute three terms to be IOR'ed together. In
7096 : practice, at most two will be nonzero. Then we do the IOR's. */
7097 :
7098 47727054 : if (GET_CODE (dest) != PC
7099 36715272 : && GET_CODE (src) == IF_THEN_ELSE
7100 1259002 : && is_int_mode (GET_MODE (src), &int_mode)
7101 1128653 : && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7102 435256 : && XEXP (XEXP (src, 0), 1) == const0_rtx
7103 320794 : && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7104 106104 : && (!HAVE_conditional_move
7105 106104 : || ! can_conditionally_move_p (int_mode))
7106 0 : && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7107 0 : == GET_MODE_PRECISION (int_mode))
7108 47727054 : && ! side_effects_p (src))
7109 : {
7110 0 : rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7111 0 : ? XEXP (src, 1) : XEXP (src, 2));
7112 0 : rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7113 0 : ? XEXP (src, 2) : XEXP (src, 1));
7114 0 : rtx term1 = const0_rtx, term2, term3;
7115 :
7116 0 : if (GET_CODE (true_rtx) == IOR
7117 0 : && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7118 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7119 0 : else if (GET_CODE (true_rtx) == IOR
7120 0 : && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7121 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7122 0 : else if (GET_CODE (false_rtx) == IOR
7123 0 : && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7124 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7125 0 : else if (GET_CODE (false_rtx) == IOR
7126 0 : && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7127 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7128 :
7129 0 : term2 = simplify_gen_binary (AND, int_mode,
7130 0 : XEXP (XEXP (src, 0), 0), true_rtx);
7131 0 : term3 = simplify_gen_binary (AND, int_mode,
7132 : simplify_gen_unary (NOT, int_mode,
7133 0 : XEXP (XEXP (src, 0), 0),
7134 : int_mode),
7135 : false_rtx);
7136 :
7137 0 : SUBST (SET_SRC (x),
7138 : simplify_gen_binary (IOR, int_mode,
7139 : simplify_gen_binary (IOR, int_mode,
7140 : term1, term2),
7141 : term3));
7142 :
7143 0 : src = SET_SRC (x);
7144 : }
7145 :
7146 : /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7147 : whole thing fail. */
7148 47727054 : if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7149 : return src;
7150 47727034 : else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7151 : return dest;
7152 : else
7153 : /* Convert this into a field assignment operation, if possible. */
7154 47727034 : return make_field_assignment (x);
7155 : }
7156 :
7157 : /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7158 : result. */
7159 :
7160 : static rtx
7161 11312173 : simplify_logical (rtx x)
7162 : {
7163 11312173 : rtx op0 = XEXP (x, 0);
7164 11312173 : rtx op1 = XEXP (x, 1);
7165 11312173 : scalar_int_mode mode;
7166 :
7167 11312173 : switch (GET_CODE (x))
7168 : {
7169 7070343 : case AND:
7170 : /* We can call simplify_and_const_int only if we don't lose
7171 : any (sign) bits when converting INTVAL (op1) to
7172 : "unsigned HOST_WIDE_INT". */
7173 7070343 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7174 6538353 : && CONST_INT_P (op1)
7175 5181622 : && (HWI_COMPUTABLE_MODE_P (mode)
7176 6647 : || INTVAL (op1) > 0))
7177 : {
7178 5178282 : x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7179 5178282 : if (GET_CODE (x) != AND)
7180 : return x;
7181 :
7182 5153023 : op0 = XEXP (x, 0);
7183 5153023 : op1 = XEXP (x, 1);
7184 : }
7185 :
7186 : /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7187 : apply the distributive law and then the inverse distributive
7188 : law to see if things simplify. */
7189 7045084 : if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7190 : {
7191 119291 : rtx result = distribute_and_simplify_rtx (x, 0);
7192 119291 : if (result)
7193 : return result;
7194 : }
7195 7031472 : if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7196 : {
7197 1821 : rtx result = distribute_and_simplify_rtx (x, 1);
7198 1821 : if (result)
7199 0 : return result;
7200 : }
7201 : break;
7202 :
7203 4241830 : case IOR:
7204 : /* If we have (ior (and A B) C), apply the distributive law and then
7205 : the inverse distributive law to see if things simplify. */
7206 :
7207 4241830 : if (GET_CODE (op0) == AND)
7208 : {
7209 1181569 : rtx result = distribute_and_simplify_rtx (x, 0);
7210 1181569 : if (result)
7211 : return result;
7212 : }
7213 :
7214 4239078 : if (GET_CODE (op1) == AND)
7215 : {
7216 53953 : rtx result = distribute_and_simplify_rtx (x, 1);
7217 53953 : if (result)
7218 4 : return result;
7219 : }
7220 : break;
7221 :
7222 0 : default:
7223 0 : gcc_unreachable ();
7224 : }
7225 :
7226 : return x;
7227 : }
7228 :
7229 : /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7230 : operations" because they can be replaced with two more basic operations.
7231 : ZERO_EXTEND is also considered "compound" because it can be replaced with
7232 : an AND operation, which is simpler, though only one operation.
7233 :
7234 : The function expand_compound_operation is called with an rtx expression
7235 : and will convert it to the appropriate shifts and AND operations,
7236 : simplifying at each stage.
7237 :
7238 : The function make_compound_operation is called to convert an expression
7239 : consisting of shifts and ANDs into the equivalent compound expression.
7240 : It is the inverse of this function, loosely speaking. */
7241 :
7242 : static rtx
7243 17258419 : expand_compound_operation (rtx x)
7244 : {
7245 17258419 : unsigned HOST_WIDE_INT pos = 0, len;
7246 17258419 : bool unsignedp = false;
7247 17258419 : unsigned int modewidth;
7248 17258419 : rtx tem;
7249 17258419 : scalar_int_mode inner_mode;
7250 :
7251 17258419 : switch (GET_CODE (x))
7252 : {
7253 4690347 : case ZERO_EXTEND:
7254 4690347 : unsignedp = true;
7255 : /* FALLTHRU */
7256 6040478 : case SIGN_EXTEND:
7257 : /* We can't necessarily use a const_int for a multiword mode;
7258 : it depends on implicitly extending the value.
7259 : Since we don't know the right way to extend it,
7260 : we can't tell whether the implicit way is right.
7261 :
7262 : Even for a mode that is no wider than a const_int,
7263 : we can't win, because we need to sign extend one of its bits through
7264 : the rest of it, and we don't know which bit. */
7265 6040478 : if (CONST_INT_P (XEXP (x, 0)))
7266 : return x;
7267 :
7268 : /* Reject modes that aren't scalar integers because turning vector
7269 : or complex modes into shifts causes problems. */
7270 6040478 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7271 : return x;
7272 :
7273 : /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7274 : (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7275 : because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7276 : reloaded. If not for that, MEM's would very rarely be safe.
7277 :
7278 : Reject modes bigger than a word, because we might not be able
7279 : to reference a two-register group starting with an arbitrary register
7280 : (and currently gen_lowpart might crash for a SUBREG). */
7281 :
7282 12237872 : if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7283 : return x;
7284 :
7285 5689347 : len = GET_MODE_PRECISION (inner_mode);
7286 : /* If the inner object has VOIDmode (the only way this can happen
7287 : is if it is an ASM_OPERANDS), we can't do anything since we don't
7288 : know how much masking to do. */
7289 5689347 : if (len == 0)
7290 : return x;
7291 :
7292 : break;
7293 :
7294 913721 : case ZERO_EXTRACT:
7295 913721 : unsignedp = true;
7296 :
7297 : /* fall through */
7298 :
7299 943198 : case SIGN_EXTRACT:
7300 : /* If the operand is a CLOBBER, just return it. */
7301 943198 : if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7302 : return XEXP (x, 0);
7303 :
7304 943192 : if (!CONST_INT_P (XEXP (x, 1))
7305 943057 : || !CONST_INT_P (XEXP (x, 2)))
7306 : return x;
7307 :
7308 : /* Reject modes that aren't scalar integers because turning vector
7309 : or complex modes into shifts causes problems. */
7310 869052 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7311 : return x;
7312 :
7313 869050 : len = INTVAL (XEXP (x, 1));
7314 869050 : pos = INTVAL (XEXP (x, 2));
7315 :
7316 : /* This should stay within the object being extracted, fail otherwise. */
7317 869050 : if (len + pos > GET_MODE_PRECISION (inner_mode))
7318 : return x;
7319 :
7320 : if (BITS_BIG_ENDIAN)
7321 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7322 :
7323 : break;
7324 :
7325 : default:
7326 : return x;
7327 : }
7328 :
7329 : /* We've rejected non-scalar operations by now. */
7330 6558348 : scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7331 :
7332 : /* Convert sign extension to zero extension, if we know that the high
7333 : bit is not set, as this is easier to optimize. It will be converted
7334 : back to cheaper alternative in make_extraction. */
7335 6558348 : if (GET_CODE (x) == SIGN_EXTEND
7336 1194626 : && HWI_COMPUTABLE_MODE_P (mode)
7337 7637826 : && ((nonzero_bits (XEXP (x, 0), inner_mode)
7338 1079478 : & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7339 : == 0))
7340 : {
7341 587 : rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7342 587 : rtx temp2 = expand_compound_operation (temp);
7343 :
7344 : /* Make sure this is a profitable operation. */
7345 587 : if (set_src_cost (x, mode, optimize_this_for_speed_p)
7346 587 : > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7347 : return temp2;
7348 573 : else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7349 573 : > set_src_cost (temp, mode, optimize_this_for_speed_p))
7350 : return temp;
7351 : else
7352 43 : return x;
7353 : }
7354 :
7355 : /* We can optimize some special cases of ZERO_EXTEND. */
7356 6557761 : if (GET_CODE (x) == ZERO_EXTEND)
7357 : {
7358 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7359 : know that the last value didn't have any inappropriate bits
7360 : set. */
7361 4494721 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7362 204 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7363 204 : && HWI_COMPUTABLE_MODE_P (mode)
7364 4494925 : && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7365 204 : & ~GET_MODE_MASK (inner_mode)) == 0)
7366 37 : return XEXP (XEXP (x, 0), 0);
7367 :
7368 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7369 4494684 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7370 682014 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7371 620005 : && subreg_lowpart_p (XEXP (x, 0))
7372 257627 : && HWI_COMPUTABLE_MODE_P (mode)
7373 4729890 : && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7374 235206 : & ~GET_MODE_MASK (inner_mode)) == 0)
7375 65 : return SUBREG_REG (XEXP (x, 0));
7376 :
7377 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7378 : is a comparison and STORE_FLAG_VALUE permits. This is like
7379 : the first case, but it works even when MODE is larger
7380 : than HOST_WIDE_INT. */
7381 4494619 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7382 167 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7383 167 : && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7384 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7385 4494619 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7386 : return XEXP (XEXP (x, 0), 0);
7387 :
7388 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7389 4494619 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7390 681949 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7391 619940 : && subreg_lowpart_p (XEXP (x, 0))
7392 257562 : && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7393 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7394 4494619 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7395 : return SUBREG_REG (XEXP (x, 0));
7396 :
7397 : }
7398 :
7399 : /* If we reach here, we want to return a pair of shifts. The inner
7400 : shift is a left shift of BITSIZE - POS - LEN bits. The outer
7401 : shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7402 : logical depending on the value of UNSIGNEDP.
7403 :
7404 : If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7405 : converted into an AND of a shift.
7406 :
7407 : We must check for the case where the left shift would have a negative
7408 : count. This can happen in a case like (x >> 31) & 255 on machines
7409 : that can't shift by a constant. On those machines, we would first
7410 : combine the shift with the AND to produce a variable-position
7411 : extraction. Then the constant of 31 would be substituted in
7412 : to produce such a position. */
7413 :
7414 6557659 : modewidth = GET_MODE_PRECISION (mode);
7415 6557659 : if (modewidth >= pos + len)
7416 : {
7417 6557658 : tem = gen_lowpart (mode, XEXP (x, 0));
7418 6557658 : if (!tem || GET_CODE (tem) == CLOBBER)
7419 : return x;
7420 6974706 : tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7421 3487353 : tem, modewidth - pos - len);
7422 3487353 : tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7423 3487353 : mode, tem, modewidth - len);
7424 : }
7425 1 : else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7426 : {
7427 1 : tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7428 : XEXP (x, 0), pos);
7429 1 : tem = gen_lowpart (mode, tem);
7430 1 : if (!tem || GET_CODE (tem) == CLOBBER)
7431 : return x;
7432 1 : tem = simplify_and_const_int (NULL_RTX, mode, tem,
7433 1 : (HOST_WIDE_INT_1U << len) - 1);
7434 : }
7435 : else
7436 : /* Any other cases we can't handle. */
7437 : return x;
7438 :
7439 : /* If we couldn't do this for some reason, return the original
7440 : expression. */
7441 3487354 : if (GET_CODE (tem) == CLOBBER)
7442 25 : return x;
7443 :
7444 : return tem;
7445 : }
7446 :
7447 : /* X is a SET which contains an assignment of one object into
7448 : a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7449 : or certain SUBREGS). If possible, convert it into a series of
7450 : logical operations.
7451 :
7452 : We half-heartedly support variable positions, but do not at all
7453 : support variable lengths. */
7454 :
7455 : static const_rtx
7456 85382267 : expand_field_assignment (const_rtx x)
7457 : {
7458 85382267 : rtx inner;
7459 85382267 : rtx pos; /* Always counts from low bit. */
7460 85382267 : int len, inner_len;
7461 85382267 : rtx mask, cleared, masked;
7462 85382267 : scalar_int_mode compute_mode;
7463 :
7464 : /* Loop until we find something we can't simplify. */
7465 85649742 : while (1)
7466 : {
7467 85649742 : if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7468 14419 : && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7469 : {
7470 14419 : rtx x0 = XEXP (SET_DEST (x), 0);
7471 14419 : if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7472 : break;
7473 14419 : inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7474 14419 : pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7475 : MAX_MODE_INT);
7476 14419 : }
7477 85635323 : else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7478 4626 : && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7479 : {
7480 4626 : inner = XEXP (SET_DEST (x), 0);
7481 4626 : if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7482 : break;
7483 :
7484 4626 : len = INTVAL (XEXP (SET_DEST (x), 1));
7485 4626 : pos = XEXP (SET_DEST (x), 2);
7486 :
7487 : /* A constant position should stay within the width of INNER. */
7488 4626 : if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7489 : break;
7490 :
7491 : if (BITS_BIG_ENDIAN)
7492 : {
7493 : if (CONST_INT_P (pos))
7494 : pos = GEN_INT (inner_len - len - INTVAL (pos));
7495 : else if (GET_CODE (pos) == MINUS
7496 : && CONST_INT_P (XEXP (pos, 1))
7497 : && INTVAL (XEXP (pos, 1)) == inner_len - len)
7498 : /* If position is ADJUST - X, new position is X. */
7499 : pos = XEXP (pos, 0);
7500 : else
7501 : pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7502 : gen_int_mode (inner_len - len,
7503 : GET_MODE (pos)),
7504 : pos);
7505 : }
7506 : }
7507 :
7508 : /* If the destination is a subreg that overwrites the whole of the inner
7509 : register, we can move the subreg to the source. */
7510 85885682 : else if (GET_CODE (SET_DEST (x)) == SUBREG
7511 : /* We need SUBREGs to compute nonzero_bits properly. */
7512 910610 : && nonzero_sign_valid
7513 86453006 : && !read_modify_subreg_p (SET_DEST (x)))
7514 : {
7515 254985 : x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7516 : gen_lowpart
7517 : (GET_MODE (SUBREG_REG (SET_DEST (x))),
7518 : SET_SRC (x)));
7519 254985 : continue;
7520 : }
7521 : else
7522 : break;
7523 :
7524 21222 : while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7525 2177 : inner = SUBREG_REG (inner);
7526 :
7527 : /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7528 19045 : if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7529 : {
7530 : /* Don't do anything for vector or complex integral types. */
7531 : if (! FLOAT_MODE_P (GET_MODE (inner)))
7532 : break;
7533 :
7534 : /* Try to find an integral mode to pun with. */
7535 38 : if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7536 0 : .exists (&compute_mode))
7537 : break;
7538 :
7539 19 : inner = gen_lowpart (compute_mode, inner);
7540 : }
7541 :
7542 : /* Compute a mask of LEN bits, if we can do this on the host machine. */
7543 14437 : if (len >= HOST_BITS_PER_WIDE_INT)
7544 : break;
7545 :
7546 : /* Don't try to compute in too wide unsupported modes. */
7547 14437 : if (!targetm.scalar_mode_supported_p (compute_mode))
7548 : break;
7549 :
7550 : /* gen_lowpart_for_combine returns CLOBBER on failure. */
7551 14437 : rtx lowpart = gen_lowpart (compute_mode, SET_SRC (x));
7552 14437 : if (GET_CODE (lowpart) == CLOBBER)
7553 : break;
7554 :
7555 : /* Now compute the equivalent expression. Make a copy of INNER
7556 : for the SET_DEST in case it is a MEM into which we will substitute;
7557 : we don't want shared RTL in that case. */
7558 12490 : mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7559 : compute_mode);
7560 12490 : cleared = simplify_gen_binary (AND, compute_mode,
7561 : simplify_gen_unary (NOT, compute_mode,
7562 : simplify_gen_binary (ASHIFT,
7563 : compute_mode,
7564 : mask, pos),
7565 : compute_mode),
7566 : inner);
7567 12490 : masked = simplify_gen_binary (ASHIFT, compute_mode,
7568 : simplify_gen_binary (
7569 : AND, compute_mode, lowpart, mask),
7570 : pos);
7571 :
7572 12490 : x = gen_rtx_SET (copy_rtx (inner),
7573 : simplify_gen_binary (IOR, compute_mode,
7574 : cleared, masked));
7575 : }
7576 :
7577 85382267 : return x;
7578 : }
7579 :
7580 : /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7581 : it is an RTX that represents the (variable) starting position; otherwise,
7582 : POS is the (constant) starting bit position. Both are counted from the LSB.
7583 :
7584 : UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7585 :
7586 : IN_DEST is true if this is a reference in the destination of a SET.
7587 : This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7588 : a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7589 : be used.
7590 :
7591 : IN_COMPARE is true if we are in a COMPARE. This means that a
7592 : ZERO_EXTRACT should be built even for bits starting at bit 0.
7593 :
7594 : MODE is the desired mode of the result (if IN_DEST == 0).
7595 :
7596 : The result is an RTX for the extraction or NULL_RTX if the target
7597 : can't handle it. */
7598 :
7599 : static rtx
7600 5159992 : make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7601 : rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7602 : bool in_dest, bool in_compare)
7603 : {
7604 : /* This mode describes the size of the storage area
7605 : to fetch the overall value from. Within that, we
7606 : ignore the POS lowest bits, etc. */
7607 5159992 : machine_mode is_mode = GET_MODE (inner);
7608 5159992 : machine_mode inner_mode;
7609 5159992 : scalar_int_mode wanted_inner_mode;
7610 5159992 : scalar_int_mode wanted_inner_reg_mode = word_mode;
7611 5159992 : scalar_int_mode pos_mode = word_mode;
7612 5159992 : machine_mode extraction_mode = word_mode;
7613 5159992 : rtx new_rtx = 0;
7614 5159992 : rtx orig_pos_rtx = pos_rtx;
7615 5159992 : HOST_WIDE_INT orig_pos;
7616 :
7617 5159992 : if (pos_rtx && CONST_INT_P (pos_rtx))
7618 939737 : pos = INTVAL (pos_rtx), pos_rtx = 0;
7619 :
7620 5159992 : if (GET_CODE (inner) == SUBREG
7621 2655289 : && subreg_lowpart_p (inner)
7622 7811378 : && (paradoxical_subreg_p (inner)
7623 : /* If trying or potentially trying to extract
7624 : bits outside of is_mode, don't look through
7625 : non-paradoxical SUBREGs. See PR82192. */
7626 186642 : || (pos_rtx == NULL_RTX
7627 186591 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7628 : {
7629 : /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7630 : consider just the QI as the memory to extract from.
7631 : The subreg adds or removes high bits; its mode is
7632 : irrelevant to the meaning of this extraction,
7633 : since POS and LEN count from the lsb. */
7634 2651335 : if (MEM_P (SUBREG_REG (inner)))
7635 493548 : is_mode = GET_MODE (SUBREG_REG (inner));
7636 : inner = SUBREG_REG (inner);
7637 : }
7638 2508657 : else if (GET_CODE (inner) == ASHIFT
7639 138692 : && CONST_INT_P (XEXP (inner, 1))
7640 137535 : && pos_rtx == 0 && pos == 0
7641 137512 : && len > UINTVAL (XEXP (inner, 1)))
7642 : {
7643 : /* We're extracting the least significant bits of an rtx
7644 : (ashift X (const_int C)), where LEN > C. Extract the
7645 : least significant (LEN - C) bits of X, giving an rtx
7646 : whose mode is MODE, then shift it left C times. */
7647 137512 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7648 : 0, 0, len - INTVAL (XEXP (inner, 1)),
7649 : unsignedp, in_dest, in_compare);
7650 137512 : if (new_rtx != 0)
7651 135866 : return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7652 : }
7653 2371145 : else if (GET_CODE (inner) == MULT
7654 173517 : && CONST_INT_P (XEXP (inner, 1))
7655 133515 : && pos_rtx == 0 && pos == 0)
7656 : {
7657 : /* We're extracting the least significant bits of an rtx
7658 : (mult X (const_int 2^C)), where LEN > C. Extract the
7659 : least significant (LEN - C) bits of X, giving an rtx
7660 : whose mode is MODE, then multiply it by 2^C. */
7661 113536 : const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7662 113536 : if (len > 1 && IN_RANGE (shift_amt, 1, len - 1))
7663 : {
7664 108946 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7665 : 0, 0, len - shift_amt,
7666 : unsignedp, in_dest, in_compare);
7667 108946 : if (new_rtx)
7668 108946 : return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7669 : }
7670 : }
7671 2257609 : else if (GET_CODE (inner) == TRUNCATE
7672 : /* If trying or potentially trying to extract
7673 : bits outside of is_mode, don't look through
7674 : TRUNCATE. See PR82192. */
7675 0 : && pos_rtx == NULL_RTX
7676 2257609 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7677 0 : inner = XEXP (inner, 0);
7678 :
7679 4915180 : inner_mode = GET_MODE (inner);
7680 :
7681 : /* See if this can be done without an extraction. We never can if the
7682 : width of the field is not the same as that of some integer mode. For
7683 : registers, we can only avoid the extraction if the position is at the
7684 : low-order bit and this is either not in the destination or we have the
7685 : appropriate STRICT_LOW_PART operation available.
7686 :
7687 : For MEM, we can avoid an extract if the field starts on an appropriate
7688 : boundary and we can change the mode of the memory reference. */
7689 :
7690 4915180 : scalar_int_mode tmode;
7691 4915180 : if (int_mode_for_size (len, 1).exists (&tmode)
7692 2392755 : && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7693 2071612 : && !MEM_P (inner)
7694 1686547 : && (pos == 0 || REG_P (inner))
7695 1686547 : && (inner_mode == tmode
7696 262600 : || !REG_P (inner)
7697 2296483 : || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7698 0 : || reg_truncated_to_mode (tmode, inner))
7699 1686547 : && (! in_dest
7700 29 : || (REG_P (inner)
7701 29 : && have_insn_for (STRICT_LOW_PART, tmode))))
7702 565761 : || (MEM_P (inner) && pos_rtx == 0
7703 386424 : && (pos
7704 : % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7705 : : BITS_PER_UNIT)) == 0
7706 : /* We can't do this if we are widening INNER_MODE (it
7707 : may not be aligned, for one thing). */
7708 385402 : && !paradoxical_subreg_p (tmode, inner_mode)
7709 385402 : && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7710 385402 : && (inner_mode == tmode
7711 609 : || (! mode_dependent_address_p (XEXP (inner, 0),
7712 609 : MEM_ADDR_SPACE (inner))
7713 609 : && ! MEM_VOLATILE_P (inner))))))
7714 : {
7715 : /* If INNER is a MEM, make a new MEM that encompasses just the desired
7716 : field. If the original and current mode are the same, we need not
7717 : adjust the offset. Otherwise, we do if bytes big endian.
7718 :
7719 : If INNER is not a MEM, get a piece consisting of just the field
7720 : of interest (in this case POS % BITS_PER_WORD must be 0). */
7721 :
7722 2071920 : if (MEM_P (inner))
7723 : {
7724 385389 : poly_int64 offset;
7725 :
7726 : /* POS counts from lsb, but make OFFSET count in memory order. */
7727 385389 : if (BYTES_BIG_ENDIAN)
7728 : offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7729 : - len - pos);
7730 : else
7731 385389 : offset = pos / BITS_PER_UNIT;
7732 :
7733 385389 : new_rtx = adjust_address_nv (inner, tmode, offset);
7734 : }
7735 1686531 : else if (REG_P (inner))
7736 : {
7737 1052462 : if (tmode != inner_mode)
7738 : {
7739 : /* We can't call gen_lowpart in a DEST since we
7740 : always want a SUBREG (see below) and it would sometimes
7741 : return a new hard register. */
7742 224547 : if (pos || in_dest)
7743 : {
7744 16 : poly_uint64 offset
7745 16 : = subreg_offset_from_lsb (tmode, inner_mode, pos);
7746 :
7747 : /* Avoid creating invalid subregs, for example when
7748 : simplifying (x>>32)&255. */
7749 16 : if (!validate_subreg (tmode, inner_mode, inner, offset))
7750 0 : return NULL_RTX;
7751 :
7752 16 : new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7753 16 : }
7754 : else
7755 224531 : new_rtx = gen_lowpart (tmode, inner);
7756 : }
7757 : else
7758 : new_rtx = inner;
7759 : }
7760 : else
7761 1268138 : new_rtx = force_to_mode (inner, tmode,
7762 : len >= HOST_BITS_PER_WIDE_INT
7763 : ? HOST_WIDE_INT_M1U
7764 634069 : : (HOST_WIDE_INT_1U << len) - 1, false);
7765 :
7766 : /* If this extraction is going into the destination of a SET,
7767 : make a STRICT_LOW_PART unless we made a MEM. */
7768 :
7769 2071920 : if (in_dest)
7770 55 : return (MEM_P (new_rtx) ? new_rtx
7771 : : (GET_CODE (new_rtx) != SUBREG
7772 13 : ? gen_rtx_CLOBBER (tmode, const0_rtx)
7773 13 : : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7774 :
7775 2071865 : if (mode == tmode)
7776 : return new_rtx;
7777 :
7778 2071836 : if (CONST_SCALAR_INT_P (new_rtx))
7779 5 : return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7780 5 : mode, new_rtx, tmode);
7781 :
7782 : /* If we know that no extraneous bits are set, and that the high
7783 : bit is not set, convert the extraction to the cheaper of
7784 : sign and zero extension, that are equivalent in these cases. */
7785 2071831 : if (flag_expensive_optimizations
7786 2071831 : && (HWI_COMPUTABLE_MODE_P (tmode)
7787 1919875 : && ((nonzero_bits (new_rtx, tmode)
7788 1919875 : & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7789 : == 0)))
7790 : {
7791 6857 : rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7792 6857 : rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7793 :
7794 : /* Prefer ZERO_EXTENSION, since it gives more information to
7795 : backends. */
7796 6857 : if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7797 6857 : <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7798 : return temp;
7799 0 : return temp1;
7800 : }
7801 :
7802 : /* Otherwise, sign- or zero-extend unless we already are in the
7803 : proper mode. */
7804 :
7805 2064974 : return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7806 2064974 : mode, new_rtx));
7807 : }
7808 :
7809 : /* Unless this is a COMPARE or we have a funny memory reference,
7810 : don't do anything with zero-extending field extracts starting at
7811 : the low-order bit since they are simple AND operations. */
7812 2843260 : if (pos_rtx == 0 && pos == 0 && ! in_dest
7813 1771978 : && ! in_compare && unsignedp)
7814 : return 0;
7815 :
7816 : /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7817 : if the position is not a constant and the length is not 1. In all
7818 : other cases, we would only be going outside our object in cases when
7819 : an original shift would have been undefined. */
7820 1475465 : if (MEM_P (inner)
7821 1475465 : && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7822 2987 : || (pos_rtx != 0 && len != 1)))
7823 : return 0;
7824 :
7825 1598126 : enum extraction_pattern pattern = (in_dest ? EP_insv
7826 1468899 : : unsignedp ? EP_extzv : EP_extv);
7827 :
7828 : /* If INNER is not from memory, we want it to have the mode of a register
7829 : extraction pattern's structure operand, or word_mode if there is no
7830 : such pattern. The same applies to extraction_mode and pos_mode
7831 : and their respective operands.
7832 :
7833 : For memory, assume that the desired extraction_mode and pos_mode
7834 : are the same as for a register operation, since at present we don't
7835 : have named patterns for aligned memory structures. */
7836 1475425 : class extraction_insn insn;
7837 1475425 : unsigned int inner_size;
7838 2950850 : if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7839 1475425 : && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7840 : {
7841 1368479 : wanted_inner_reg_mode = insn.struct_mode.require ();
7842 1368479 : pos_mode = insn.pos_mode;
7843 1368479 : extraction_mode = insn.field_mode;
7844 : }
7845 :
7846 : /* Never narrow an object, since that might not be safe. */
7847 :
7848 1475425 : if (mode != VOIDmode
7849 1475425 : && partial_subreg_p (extraction_mode, mode))
7850 : extraction_mode = mode;
7851 :
7852 : /* Punt if len is too large for extraction_mode. */
7853 1475425 : if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7854 : return NULL_RTX;
7855 :
7856 1475413 : if (!MEM_P (inner))
7857 1301088 : wanted_inner_mode = wanted_inner_reg_mode;
7858 : else
7859 : {
7860 : /* Be careful not to go beyond the extracted object and maintain the
7861 : natural alignment of the memory. */
7862 174325 : wanted_inner_mode = smallest_int_mode_for_size (len).require ();
7863 351855 : while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7864 355060 : > GET_MODE_BITSIZE (wanted_inner_mode))
7865 3205 : wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7866 : }
7867 :
7868 1475413 : orig_pos = pos;
7869 :
7870 1475413 : if (BITS_BIG_ENDIAN)
7871 : {
7872 : /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7873 : BITS_BIG_ENDIAN style. If position is constant, compute new
7874 : position. Otherwise, build subtraction.
7875 : Note that POS is relative to the mode of the original argument.
7876 : If it's a MEM we need to recompute POS relative to that.
7877 : However, if we're extracting from (or inserting into) a register,
7878 : we want to recompute POS relative to wanted_inner_mode. */
7879 : int width;
7880 : if (!MEM_P (inner))
7881 : width = GET_MODE_BITSIZE (wanted_inner_mode);
7882 : else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7883 : return NULL_RTX;
7884 :
7885 : if (pos_rtx == 0)
7886 : pos = width - len - pos;
7887 : else
7888 : pos_rtx
7889 : = gen_rtx_MINUS (GET_MODE (pos_rtx),
7890 : gen_int_mode (width - len, GET_MODE (pos_rtx)),
7891 : pos_rtx);
7892 : /* POS may be less than 0 now, but we check for that below.
7893 : Note that it can only be less than 0 if !MEM_P (inner). */
7894 : }
7895 :
7896 : /* If INNER has a wider mode, and this is a constant extraction, try to
7897 : make it smaller and adjust the byte to point to the byte containing
7898 : the value. */
7899 1475413 : if (wanted_inner_mode != VOIDmode
7900 1475413 : && inner_mode != wanted_inner_mode
7901 224121 : && ! pos_rtx
7902 215661 : && partial_subreg_p (wanted_inner_mode, is_mode)
7903 114179 : && MEM_P (inner)
7904 26069 : && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7905 1501482 : && ! MEM_VOLATILE_P (inner))
7906 : {
7907 24516 : poly_int64 offset = 0;
7908 :
7909 : /* The computations below will be correct if the machine is big
7910 : endian in both bits and bytes or little endian in bits and bytes.
7911 : If it is mixed, we must adjust. */
7912 :
7913 : /* If bytes are big endian and we had a paradoxical SUBREG, we must
7914 : adjust OFFSET to compensate. */
7915 24516 : if (BYTES_BIG_ENDIAN
7916 : && paradoxical_subreg_p (is_mode, inner_mode))
7917 : offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7918 :
7919 : /* We can now move to the desired byte. */
7920 49032 : offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7921 24516 : * GET_MODE_SIZE (wanted_inner_mode);
7922 24516 : pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7923 :
7924 24516 : if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7925 : && is_mode != wanted_inner_mode)
7926 : offset = (GET_MODE_SIZE (is_mode)
7927 : - GET_MODE_SIZE (wanted_inner_mode) - offset);
7928 :
7929 24516 : inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7930 : }
7931 :
7932 : /* If INNER is not memory, get it into the proper mode. If we are changing
7933 : its mode, POS must be a constant and smaller than the size of the new
7934 : mode. */
7935 1450897 : else if (!MEM_P (inner))
7936 : {
7937 : /* On the LHS, don't create paradoxical subregs implicitly truncating
7938 : the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7939 1301088 : if (in_dest
7940 1301088 : && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7941 : wanted_inner_mode))
7942 0 : return NULL_RTX;
7943 :
7944 1301088 : if (GET_MODE (inner) != wanted_inner_mode
7945 1301088 : && (pos_rtx != 0
7946 379184 : || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7947 : return NULL_RTX;
7948 :
7949 1235131 : if (orig_pos < 0)
7950 : return NULL_RTX;
7951 :
7952 2451046 : inner = force_to_mode (inner, wanted_inner_mode,
7953 : pos_rtx
7954 1215915 : || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7955 : ? HOST_WIDE_INT_M1U
7956 1055889 : : (((HOST_WIDE_INT_1U << len) - 1)
7957 1055889 : << orig_pos), false);
7958 : }
7959 :
7960 : /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7961 : have to zero extend. Otherwise, we can just use a SUBREG.
7962 :
7963 : We dealt with constant rtxes earlier, so pos_rtx cannot
7964 : have VOIDmode at this point. */
7965 1409456 : if (pos_rtx != 0
7966 1409456 : && (GET_MODE_SIZE (pos_mode)
7967 1431619 : > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7968 : {
7969 79 : rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7970 : GET_MODE (pos_rtx));
7971 :
7972 : /* If we know that no extraneous bits are set, and that the high
7973 : bit is not set, convert extraction to cheaper one - either
7974 : SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7975 : cases. */
7976 79 : if (flag_expensive_optimizations
7977 79 : && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7978 79 : && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7979 79 : & ~(((unsigned HOST_WIDE_INT)
7980 79 : GET_MODE_MASK (GET_MODE (pos_rtx)))
7981 79 : >> 1))
7982 : == 0)))
7983 : {
7984 57 : rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7985 : GET_MODE (pos_rtx));
7986 :
7987 : /* Prefer ZERO_EXTENSION, since it gives more information to
7988 : backends. */
7989 57 : if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7990 57 : < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7991 1409456 : temp = temp1;
7992 : }
7993 : pos_rtx = temp;
7994 : }
7995 :
7996 : /* Make POS_RTX unless we already have it and it is correct. If we don't
7997 : have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7998 : be a CONST_INT. */
7999 1409456 : if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
8000 : pos_rtx = orig_pos_rtx;
8001 :
8002 493832 : else if (pos_rtx == 0)
8003 471669 : pos_rtx = GEN_INT (pos);
8004 :
8005 : /* Make the required operation. See if we can use existing rtx. */
8006 1409456 : new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
8007 : extraction_mode, inner, GEN_INT (len), pos_rtx);
8008 1409456 : if (! in_dest)
8009 1402974 : new_rtx = gen_lowpart (mode, new_rtx);
8010 :
8011 : return new_rtx;
8012 : }
8013 :
8014 : /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8015 : can be commuted with any other operations in X. Return X without
8016 : that shift if so. */
8017 :
8018 : static rtx
8019 1596403 : extract_left_shift (scalar_int_mode mode, rtx x, int count)
8020 : {
8021 1596403 : enum rtx_code code = GET_CODE (x);
8022 1596403 : rtx tem;
8023 :
8024 1596403 : switch (code)
8025 : {
8026 262164 : case ASHIFT:
8027 : /* This is the shift itself. If it is wide enough, we will return
8028 : either the value being shifted if the shift count is equal to
8029 : COUNT or a shift for the difference. */
8030 262164 : if (CONST_INT_P (XEXP (x, 1))
8031 256914 : && INTVAL (XEXP (x, 1)) >= count)
8032 255878 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8033 255878 : INTVAL (XEXP (x, 1)) - count);
8034 : break;
8035 :
8036 5363 : case NEG: case NOT:
8037 5363 : if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8038 2577 : return simplify_gen_unary (code, mode, tem, mode);
8039 :
8040 : break;
8041 :
8042 561620 : case PLUS: case IOR: case XOR: case AND:
8043 : /* If we can safely shift this constant and we find the inner shift,
8044 : make a new operation. */
8045 561620 : if (CONST_INT_P (XEXP (x, 1))
8046 304902 : && (UINTVAL (XEXP (x, 1))
8047 304902 : & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8048 711240 : && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8049 : {
8050 7073 : HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8051 7073 : return simplify_gen_binary (code, mode, tem,
8052 7073 : gen_int_mode (val, mode));
8053 : }
8054 : break;
8055 :
8056 : default:
8057 : break;
8058 : }
8059 :
8060 : return 0;
8061 : }
8062 :
8063 : /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8064 : level of the expression and MODE is its mode. IN_CODE is as for
8065 : make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8066 : that should be used when recursing on operands of *X_PTR.
8067 :
8068 : There are two possible actions:
8069 :
8070 : - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8071 : equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8072 :
8073 : - Return a new rtx, which the caller returns directly. */
8074 :
8075 : static rtx
8076 282362893 : make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8077 : enum rtx_code in_code,
8078 : enum rtx_code *next_code_ptr)
8079 : {
8080 282362893 : rtx x = *x_ptr;
8081 282362893 : enum rtx_code next_code = *next_code_ptr;
8082 282362893 : enum rtx_code code = GET_CODE (x);
8083 282362893 : int mode_width = GET_MODE_PRECISION (mode);
8084 282362893 : rtx rhs, lhs;
8085 282362893 : rtx new_rtx = 0;
8086 282362893 : int i;
8087 282362893 : rtx tem;
8088 282362893 : scalar_int_mode inner_mode;
8089 282362893 : bool equality_comparison = false;
8090 :
8091 282362893 : if (in_code == EQ)
8092 : {
8093 9155706 : equality_comparison = true;
8094 9155706 : in_code = COMPARE;
8095 : }
8096 :
8097 : /* Process depending on the code of this operation. If NEW is set
8098 : nonzero, it will be returned. */
8099 :
8100 282362893 : switch (code)
8101 : {
8102 6505035 : case ASHIFT:
8103 : /* Convert shifts by constants into multiplications if inside
8104 : an address. */
8105 6505035 : if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8106 1991689 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8107 1991689 : && INTVAL (XEXP (x, 1)) >= 0)
8108 : {
8109 1991689 : HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8110 1991689 : HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8111 :
8112 1991689 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8113 1991689 : if (GET_CODE (new_rtx) == NEG)
8114 : {
8115 9 : new_rtx = XEXP (new_rtx, 0);
8116 9 : multval = -multval;
8117 : }
8118 1991689 : multval = trunc_int_for_mode (multval, mode);
8119 1991689 : new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8120 : }
8121 : break;
8122 :
8123 55171100 : case PLUS:
8124 55171100 : case MINUS:
8125 55171100 : lhs = make_compound_operation (XEXP (x, 0), next_code);
8126 55171100 : rhs = make_compound_operation (XEXP (x, 1), next_code);
8127 55171100 : if (lhs != XEXP (x, 0) || rhs != XEXP (x, 1))
8128 3196567 : return simplify_gen_binary (code, mode, lhs, rhs);
8129 : return x;
8130 :
8131 7431841 : case AND:
8132 : /* If the second operand is not a constant, we can't do anything
8133 : with it. */
8134 7431841 : if (!CONST_INT_P (XEXP (x, 1)))
8135 : break;
8136 :
8137 : /* If the constant is a power of two minus one and the first operand
8138 : is a logical right shift, make an extraction. */
8139 5915797 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8140 5915797 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8141 : {
8142 647977 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8143 647977 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8144 : i, true, false, in_code == COMPARE);
8145 : }
8146 :
8147 : /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8148 5267820 : else if (GET_CODE (XEXP (x, 0)) == SUBREG
8149 1384800 : && subreg_lowpart_p (XEXP (x, 0))
8150 6607343 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8151 : &inner_mode)
8152 1370075 : && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8153 5300357 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8154 : {
8155 30552 : rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8156 30552 : new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8157 30552 : new_rtx = make_extraction (inner_mode, new_rtx, 0,
8158 : XEXP (inner_x0, 1),
8159 : i, true, false, in_code == COMPARE);
8160 :
8161 : /* If we narrowed the mode when dropping the subreg, then we lose. */
8162 91656 : if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8163 30552 : new_rtx = NULL;
8164 :
8165 : /* If that didn't give anything, see if the AND simplifies on
8166 : its own. */
8167 30552 : if (!new_rtx && i >= 0)
8168 : {
8169 3301 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8170 3301 : new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i,
8171 : true, false, in_code == COMPARE);
8172 : }
8173 : }
8174 : /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8175 5237268 : else if ((GET_CODE (XEXP (x, 0)) == XOR
8176 5237268 : || GET_CODE (XEXP (x, 0)) == IOR)
8177 28812 : && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8178 2567 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8179 5237278 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8180 : {
8181 : /* Apply the distributive law, and then try to make extractions. */
8182 10 : new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8183 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8184 : XEXP (x, 1)),
8185 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8186 : XEXP (x, 1)));
8187 10 : new_rtx = make_compound_operation (new_rtx, in_code);
8188 : }
8189 :
8190 : /* If we are have (and (rotate X C) M) and C is larger than the number
8191 : of bits in M, this is an extraction. */
8192 :
8193 5237258 : else if (GET_CODE (XEXP (x, 0)) == ROTATE
8194 935 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8195 925 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8196 5237295 : && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8197 : {
8198 0 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8199 0 : new_rtx = make_extraction (mode, new_rtx,
8200 0 : (GET_MODE_PRECISION (mode)
8201 0 : - INTVAL (XEXP (XEXP (x, 0), 1))),
8202 : NULL_RTX, i, true, false,
8203 : in_code == COMPARE);
8204 : }
8205 :
8206 : /* On machines without logical shifts, if the operand of the AND is
8207 : a logical shift and our mask turns off all the propagated sign
8208 : bits, we can replace the logical shift with an arithmetic shift. */
8209 5237258 : else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8210 86202 : && !have_insn_for (LSHIFTRT, mode)
8211 0 : && have_insn_for (ASHIFTRT, mode)
8212 0 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8213 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8214 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8215 5237258 : && mode_width <= HOST_BITS_PER_WIDE_INT)
8216 : {
8217 0 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8218 :
8219 0 : mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8220 0 : if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8221 0 : SUBST (XEXP (x, 0),
8222 : gen_rtx_ASHIFTRT (mode,
8223 : make_compound_operation (XEXP (XEXP (x,
8224 : 0),
8225 : 0),
8226 : next_code),
8227 : XEXP (XEXP (x, 0), 1)));
8228 : }
8229 :
8230 : /* If the constant is one less than a power of two, this might be
8231 : representable by an extraction even if no shift is present.
8232 : If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8233 : we are in a COMPARE. */
8234 5237258 : else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8235 2695032 : new_rtx = make_extraction (mode,
8236 : make_compound_operation (XEXP (x, 0),
8237 : next_code),
8238 : 0, NULL_RTX, i,
8239 : true, false, in_code == COMPARE);
8240 :
8241 : /* If we are in a comparison and this is an AND with a power of two,
8242 : convert this into the appropriate bit extract. */
8243 2542226 : else if (in_code == COMPARE
8244 464055 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8245 2621447 : && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8246 79221 : new_rtx = make_extraction (mode,
8247 : make_compound_operation (XEXP (x, 0),
8248 : next_code),
8249 : i, NULL_RTX, 1, true, false, true);
8250 :
8251 : /* If the one operand is a paradoxical subreg of a register or memory and
8252 : the constant (limited to the smaller mode) has only zero bits where
8253 : the sub expression has known zero bits, this can be expressed as
8254 : a zero_extend. */
8255 2463005 : else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8256 : {
8257 73703 : rtx sub;
8258 :
8259 73703 : sub = XEXP (XEXP (x, 0), 0);
8260 73703 : machine_mode sub_mode = GET_MODE (sub);
8261 73703 : int sub_width;
8262 30329 : if ((REG_P (sub) || MEM_P (sub))
8263 44252 : && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8264 44252 : && sub_width < mode_width
8265 73703 : && (!WORD_REGISTER_OPERATIONS
8266 : || sub_width >= BITS_PER_WORD
8267 : /* On WORD_REGISTER_OPERATIONS targets the bits
8268 : beyond sub_mode aren't considered undefined,
8269 : so optimize only if it is a MEM load when MEM loads
8270 : zero extend, because then the upper bits are all zero. */
8271 : || (MEM_P (sub)
8272 : && load_extend_op (sub_mode) == ZERO_EXTEND)))
8273 : {
8274 20714 : unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8275 20714 : unsigned HOST_WIDE_INT mask;
8276 :
8277 : /* Original AND constant with all the known zero bits set. */
8278 20714 : mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8279 20714 : if ((mask & mode_mask) == mode_mask)
8280 : {
8281 16714 : new_rtx = make_compound_operation (sub, next_code);
8282 16714 : new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8283 : true, false, in_code == COMPARE);
8284 : }
8285 : }
8286 : }
8287 :
8288 : break;
8289 :
8290 1954909 : case LSHIFTRT:
8291 : /* If the sign bit is known to be zero, replace this with an
8292 : arithmetic shift. */
8293 1954909 : if (have_insn_for (ASHIFTRT, mode)
8294 1954909 : && ! have_insn_for (LSHIFTRT, mode)
8295 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
8296 1954909 : && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8297 : {
8298 0 : new_rtx = gen_rtx_ASHIFTRT (mode,
8299 : make_compound_operation (XEXP (x, 0),
8300 : next_code),
8301 : XEXP (x, 1));
8302 0 : break;
8303 : }
8304 :
8305 : /* fall through */
8306 :
8307 4805623 : case ASHIFTRT:
8308 4805623 : lhs = XEXP (x, 0);
8309 4805623 : rhs = XEXP (x, 1);
8310 :
8311 : /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8312 : this is a SIGN_EXTRACT. */
8313 4805623 : if (CONST_INT_P (rhs)
8314 4630479 : && GET_CODE (lhs) == ASHIFT
8315 1141097 : && CONST_INT_P (XEXP (lhs, 1))
8316 1135851 : && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8317 889365 : && INTVAL (XEXP (lhs, 1)) >= 0
8318 889361 : && INTVAL (rhs) < mode_width)
8319 : {
8320 889360 : new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8321 889360 : new_rtx = make_extraction (mode, new_rtx,
8322 889360 : INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8323 889360 : NULL_RTX, mode_width - INTVAL (rhs),
8324 : code == LSHIFTRT, false,
8325 : in_code == COMPARE);
8326 889360 : break;
8327 : }
8328 :
8329 : /* See if we have operations between an ASHIFTRT and an ASHIFT.
8330 : If so, try to merge the shifts into a SIGN_EXTEND. We could
8331 : also do this for some cases of SIGN_EXTRACT, but it doesn't
8332 : seem worth the effort; the case checked for occurs on Alpha. */
8333 :
8334 3916263 : if (!OBJECT_P (lhs)
8335 1545040 : && ! (GET_CODE (lhs) == SUBREG
8336 88591 : && (OBJECT_P (SUBREG_REG (lhs))))
8337 1471342 : && CONST_INT_P (rhs)
8338 1447438 : && INTVAL (rhs) >= 0
8339 1447438 : && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8340 1441421 : && INTVAL (rhs) < mode_width
8341 5357683 : && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8342 255878 : new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8343 : next_code),
8344 255878 : 0, NULL_RTX, mode_width - INTVAL (rhs),
8345 : code == LSHIFTRT, false, in_code == COMPARE);
8346 :
8347 : break;
8348 :
8349 9641655 : case SUBREG:
8350 : /* Call ourselves recursively on the inner expression. If we are
8351 : narrowing the object and it has a different RTL code from
8352 : what it originally did, do this SUBREG as a force_to_mode. */
8353 9641655 : {
8354 9641655 : rtx inner = SUBREG_REG (x), simplified;
8355 9641655 : enum rtx_code subreg_code = in_code;
8356 :
8357 : /* If the SUBREG is masking of a logical right shift,
8358 : make an extraction. */
8359 9641655 : if (GET_CODE (inner) == LSHIFTRT
8360 9652257 : && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8361 599040 : && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8362 295703 : && CONST_INT_P (XEXP (inner, 1))
8363 290292 : && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8364 9931947 : && subreg_lowpart_p (x))
8365 : {
8366 288918 : new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8367 288918 : int width = GET_MODE_PRECISION (inner_mode)
8368 288918 : - INTVAL (XEXP (inner, 1));
8369 288918 : if (width > mode_width)
8370 : width = mode_width;
8371 288918 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8372 : width, true, false, in_code == COMPARE);
8373 288918 : break;
8374 : }
8375 :
8376 : /* If in_code is COMPARE, it isn't always safe to pass it through
8377 : to the recursive make_compound_operation call. */
8378 9352737 : if (subreg_code == COMPARE
8379 9352737 : && (!subreg_lowpart_p (x)
8380 237187 : || GET_CODE (inner) == SUBREG
8381 : /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8382 : is (const_int 0), rather than
8383 : (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8384 : Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8385 : for non-equality comparisons against 0 is not equivalent
8386 : to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8387 237187 : || (GET_CODE (inner) == AND
8388 1199 : && CONST_INT_P (XEXP (inner, 1))
8389 143 : && partial_subreg_p (x)
8390 286 : && exact_log2 (UINTVAL (XEXP (inner, 1)))
8391 143 : >= GET_MODE_BITSIZE (mode) - 1)))
8392 : subreg_code = SET;
8393 :
8394 9352737 : tem = make_compound_operation (inner, subreg_code);
8395 :
8396 : /* TEM's code might be CLOBBER if combine_simplify_rtx
8397 : could not transform a subexpression, e.g. a volatile MEM.
8398 : simplify_subreg cannot be called with clobber, so bail out. */
8399 9352737 : if (GET_CODE (tem) == CLOBBER)
8400 : return NULL_RTX;
8401 :
8402 9352718 : simplified
8403 9352718 : = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8404 9352718 : if (simplified)
8405 16475 : tem = simplified;
8406 :
8407 9352718 : if (GET_CODE (tem) != GET_CODE (inner)
8408 22199 : && partial_subreg_p (x)
8409 9371745 : && subreg_lowpart_p (x))
8410 : {
8411 19011 : rtx newer
8412 19011 : = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8413 :
8414 : /* If we have something other than a SUBREG, we might have
8415 : done an expansion, so rerun ourselves. */
8416 19011 : if (GET_CODE (newer) != SUBREG)
8417 17007 : newer = make_compound_operation (newer, in_code);
8418 :
8419 : /* force_to_mode can expand compounds. If it just re-expanded
8420 : the compound, use gen_lowpart to convert to the desired
8421 : mode. */
8422 19011 : if (rtx_equal_p (newer, x)
8423 : /* Likewise if it re-expanded the compound only partially.
8424 : This happens for SUBREG of ZERO_EXTRACT if they extract
8425 : the same number of bits. */
8426 19011 : || (GET_CODE (newer) == SUBREG
8427 2153 : && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8428 2153 : || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8429 136 : && GET_CODE (inner) == AND
8430 56 : && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8431 1372 : return gen_lowpart (GET_MODE (x), tem);
8432 :
8433 : return newer;
8434 : }
8435 :
8436 9333707 : if (simplified)
8437 : return tem;
8438 : }
8439 : break;
8440 :
8441 : default:
8442 : break;
8443 : }
8444 :
8445 10555736 : if (new_rtx)
8446 5466339 : *x_ptr = gen_lowpart (mode, new_rtx);
8447 227172374 : *next_code_ptr = next_code;
8448 227172374 : return NULL_RTX;
8449 : }
8450 :
8451 : /* Look at the expression rooted at X. Look for expressions
8452 : equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8453 : Form these expressions.
8454 :
8455 : Return the new rtx, usually just X.
8456 :
8457 : Also, for machines like the VAX that don't have logical shift insns,
8458 : try to convert logical to arithmetic shift operations in cases where
8459 : they are equivalent. This undoes the canonicalizations to logical
8460 : shifts done elsewhere.
8461 :
8462 : We try, as much as possible, to re-use rtl expressions to save memory.
8463 :
8464 : IN_CODE says what kind of expression we are processing. Normally, it is
8465 : SET. In a memory address it is MEM. When processing the arguments of
8466 : a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8467 : precisely it is an equality comparison against zero. */
8468 :
8469 : rtx
8470 485198456 : make_compound_operation (rtx x, enum rtx_code in_code)
8471 : {
8472 485198456 : enum rtx_code code = GET_CODE (x);
8473 485198456 : const char *fmt;
8474 485198456 : int i, j;
8475 485198456 : enum rtx_code next_code;
8476 485198456 : rtx new_rtx, tem;
8477 :
8478 : /* Select the code to be used in recursive calls. Once we are inside an
8479 : address, we stay there. If we have a comparison, set to COMPARE,
8480 : but once inside, go back to our default of SET. */
8481 :
8482 485198456 : next_code = (code == MEM ? MEM
8483 456571375 : : ((code == COMPARE || COMPARISON_P (x))
8484 477308766 : && XEXP (x, 1) == const0_rtx) ? COMPARE
8485 448385206 : : in_code == COMPARE || in_code == EQ ? SET : in_code);
8486 :
8487 485198456 : scalar_int_mode mode;
8488 485198456 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8489 : {
8490 282362893 : rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8491 : &next_code);
8492 282362893 : if (new_rtx)
8493 : return new_rtx;
8494 227172393 : code = GET_CODE (x);
8495 : }
8496 :
8497 : /* Now recursively process each operand of this operation. We need to
8498 : handle ZERO_EXTEND specially so that we don't lose track of the
8499 : inner mode. */
8500 430007956 : if (code == ZERO_EXTEND)
8501 : {
8502 3344245 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8503 6688490 : tem = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8504 3344245 : new_rtx, GET_MODE (XEXP (x, 0)));
8505 3344245 : if (tem)
8506 : return tem;
8507 3333724 : SUBST (XEXP (x, 0), new_rtx);
8508 3333724 : return x;
8509 : }
8510 :
8511 426663711 : fmt = GET_RTX_FORMAT (code);
8512 993257039 : for (i = 0; i < GET_RTX_LENGTH (code); i++)
8513 566593328 : if (fmt[i] == 'e')
8514 : {
8515 217325552 : new_rtx = make_compound_operation (XEXP (x, i), next_code);
8516 217325552 : SUBST (XEXP (x, i), new_rtx);
8517 : }
8518 349267776 : else if (fmt[i] == 'E')
8519 28162670 : for (j = 0; j < XVECLEN (x, i); j++)
8520 : {
8521 20478290 : new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8522 20478290 : SUBST (XVECEXP (x, i, j), new_rtx);
8523 : }
8524 :
8525 426663711 : maybe_swap_commutative_operands (x);
8526 426663711 : return x;
8527 : }
8528 :
8529 : /* Given M see if it is a value that would select a field of bits
8530 : within an item, but not the entire word. Return -1 if not.
8531 : Otherwise, return the starting position of the field, where 0 is the
8532 : low-order bit.
8533 :
8534 : *PLEN is set to the length of the field. */
8535 :
8536 : static int
8537 9159 : get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8538 : {
8539 : /* Get the bit number of the first 1 bit from the right, -1 if none. */
8540 9159 : int pos = m ? ctz_hwi (m) : -1;
8541 9159 : int len = 0;
8542 :
8543 9159 : if (pos >= 0)
8544 : /* Now shift off the low-order zero bits and see if we have a
8545 : power of two minus 1. */
8546 9159 : len = exact_log2 ((m >> pos) + 1);
8547 :
8548 6909 : if (len <= 0)
8549 : pos = -1;
8550 :
8551 9159 : *plen = len;
8552 9159 : return pos;
8553 : }
8554 :
8555 : /* If X refers to a register that equals REG in value, replace these
8556 : references with REG. */
8557 : static rtx
8558 9372 : canon_reg_for_combine (rtx x, rtx reg)
8559 : {
8560 9372 : rtx op0, op1, op2;
8561 9372 : const char *fmt;
8562 9372 : int i;
8563 9372 : bool copied;
8564 :
8565 9372 : enum rtx_code code = GET_CODE (x);
8566 9372 : switch (GET_RTX_CLASS (code))
8567 : {
8568 0 : case RTX_UNARY:
8569 0 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8570 0 : if (op0 != XEXP (x, 0))
8571 0 : return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8572 0 : GET_MODE (reg));
8573 : break;
8574 :
8575 1705 : case RTX_BIN_ARITH:
8576 1705 : case RTX_COMM_ARITH:
8577 1705 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8578 1705 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8579 1705 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8580 0 : return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8581 : break;
8582 :
8583 17 : case RTX_COMPARE:
8584 17 : case RTX_COMM_COMPARE:
8585 17 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8586 17 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8587 17 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8588 0 : return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8589 0 : GET_MODE (op0), op0, op1);
8590 : break;
8591 :
8592 2 : case RTX_TERNARY:
8593 2 : case RTX_BITFIELD_OPS:
8594 2 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8595 2 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8596 2 : op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8597 2 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8598 0 : return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8599 0 : GET_MODE (op0), op0, op1, op2);
8600 : /* FALLTHRU */
8601 :
8602 5410 : case RTX_OBJ:
8603 5410 : if (REG_P (x))
8604 : {
8605 5402 : if (rtx_equal_p (get_last_value (reg), x)
8606 5402 : || rtx_equal_p (reg, get_last_value (x)))
8607 0 : return reg;
8608 : else
8609 : break;
8610 : }
8611 :
8612 : /* fall through */
8613 :
8614 2248 : default:
8615 2248 : fmt = GET_RTX_FORMAT (code);
8616 2248 : copied = false;
8617 4564 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8618 2316 : if (fmt[i] == 'e')
8619 : {
8620 70 : rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8621 70 : if (op != XEXP (x, i))
8622 : {
8623 0 : if (!copied)
8624 : {
8625 0 : copied = true;
8626 0 : x = copy_rtx (x);
8627 : }
8628 0 : XEXP (x, i) = op;
8629 : }
8630 : }
8631 2246 : else if (fmt[i] == 'E')
8632 : {
8633 : int j;
8634 0 : for (j = 0; j < XVECLEN (x, i); j++)
8635 : {
8636 0 : rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8637 0 : if (op != XVECEXP (x, i, j))
8638 : {
8639 0 : if (!copied)
8640 : {
8641 0 : copied = true;
8642 0 : x = copy_rtx (x);
8643 : }
8644 0 : XVECEXP (x, i, j) = op;
8645 : }
8646 : }
8647 : }
8648 :
8649 : break;
8650 : }
8651 :
8652 : return x;
8653 : }
8654 :
8655 : /* Return X converted to MODE. If the value is already truncated to
8656 : MODE we can just return a subreg even though in the general case we
8657 : would need an explicit truncation. */
8658 :
8659 : static rtx
8660 118401291 : gen_lowpart_or_truncate (machine_mode mode, rtx x)
8661 : {
8662 118401291 : if (!CONST_INT_P (x)
8663 112753052 : && partial_subreg_p (mode, GET_MODE (x))
8664 118401291 : && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8665 118401291 : && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8666 : {
8667 : /* Bit-cast X into an integer mode. */
8668 0 : if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8669 0 : x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8670 0 : x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8671 0 : x, GET_MODE (x));
8672 : }
8673 :
8674 118401291 : return gen_lowpart (mode, x);
8675 : }
8676 :
8677 : /* See if X can be simplified knowing that we will only refer to it in
8678 : MODE and will only refer to those bits that are nonzero in MASK.
8679 : If other bits are being computed or if masking operations are done
8680 : that select a superset of the bits in MASK, they can sometimes be
8681 : ignored.
8682 :
8683 : Return a possibly simplified expression, but always convert X to
8684 : MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8685 :
8686 : If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8687 : are all off in X. This is used when X will be complemented, by either
8688 : NOT, NEG, or XOR. */
8689 :
8690 : static rtx
8691 81855119 : force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8692 : bool just_select)
8693 : {
8694 88918409 : enum rtx_code code = GET_CODE (x);
8695 88918409 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8696 88918409 : machine_mode op_mode;
8697 88918409 : unsigned HOST_WIDE_INT nonzero;
8698 :
8699 : /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8700 : code below will do the wrong thing since the mode of such an
8701 : expression is VOIDmode.
8702 :
8703 : Also do nothing if X is a CLOBBER; this can happen if X was
8704 : the return value from a call to gen_lowpart. */
8705 88918409 : if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8706 : return x;
8707 :
8708 : /* We want to perform the operation in its present mode unless we know
8709 : that the operation is valid in MODE, in which case we do the operation
8710 : in MODE. */
8711 145456691 : op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8712 82692499 : && have_insn_for (code, mode))
8713 139309261 : ? mode : GET_MODE (x));
8714 :
8715 : /* It is not valid to do a right-shift in a narrower mode
8716 : than the one it came in with. */
8717 88839929 : if ((code == LSHIFTRT || code == ASHIFTRT)
8718 88839929 : && partial_subreg_p (mode, GET_MODE (x)))
8719 395794 : op_mode = GET_MODE (x);
8720 :
8721 : /* Truncate MASK to fit OP_MODE. */
8722 88839929 : if (op_mode)
8723 82765887 : mask &= GET_MODE_MASK (op_mode);
8724 :
8725 : /* Determine what bits of X are guaranteed to be (non)zero. */
8726 88839929 : nonzero = nonzero_bits (x, mode);
8727 :
8728 : /* If none of the bits in X are needed, return a zero. */
8729 88839929 : if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8730 661356 : x = const0_rtx;
8731 :
8732 : /* If X is a CONST_INT, return a new one. Do this here since the
8733 : test below will fail. */
8734 88839929 : if (CONST_INT_P (x))
8735 : {
8736 6278917 : if (SCALAR_INT_MODE_P (mode))
8737 6278917 : return gen_int_mode (INTVAL (x) & mask, mode);
8738 : else
8739 : {
8740 0 : x = GEN_INT (INTVAL (x) & mask);
8741 0 : return gen_lowpart_common (mode, x);
8742 : }
8743 : }
8744 :
8745 : /* If X is narrower than MODE and we want all the bits in X's mode, just
8746 : get X in the proper mode. */
8747 82561012 : if (paradoxical_subreg_p (mode, GET_MODE (x))
8748 82561012 : && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8749 3435702 : return gen_lowpart (mode, x);
8750 :
8751 : /* We can ignore the effect of a SUBREG if it narrows the mode or
8752 : if the constant masks to zero all the bits the mode doesn't have. */
8753 79125310 : if (GET_CODE (x) == SUBREG
8754 7253199 : && subreg_lowpart_p (x)
8755 86223819 : && (partial_subreg_p (x)
8756 5317955 : || (mask
8757 5317955 : & GET_MODE_MASK (GET_MODE (x))
8758 5317955 : & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8759 7063290 : return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8760 :
8761 72062020 : scalar_int_mode int_mode, xmode;
8762 72062020 : if (is_a <scalar_int_mode> (mode, &int_mode)
8763 72062020 : && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8764 : /* OP_MODE is either MODE or XMODE, so it must be a scalar
8765 : integer too. */
8766 72024222 : return force_int_to_mode (x, int_mode, xmode,
8767 : as_a <scalar_int_mode> (op_mode),
8768 72024222 : mask, just_select);
8769 :
8770 37798 : return gen_lowpart_or_truncate (mode, x);
8771 : }
8772 :
8773 : /* Subroutine of force_to_mode that handles cases in which both X and
8774 : the result are scalar integers. MODE is the mode of the result,
8775 : XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8776 : is preferred for simplified versions of X. The other arguments
8777 : are as for force_to_mode. */
8778 :
8779 : static rtx
8780 72024222 : force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8781 : scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8782 : bool just_select)
8783 : {
8784 72024222 : enum rtx_code code = GET_CODE (x);
8785 72024222 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8786 72024222 : unsigned HOST_WIDE_INT fuller_mask;
8787 72024222 : rtx op0, op1, temp;
8788 72024222 : poly_int64 const_op0;
8789 :
8790 : /* When we have an arithmetic operation, or a shift whose count we
8791 : do not know, we need to assume that all bits up to the highest-order
8792 : bit in MASK will be needed. This is how we form such a mask. */
8793 72024222 : if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8794 : fuller_mask = HOST_WIDE_INT_M1U;
8795 : else
8796 78186359 : fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) - 1);
8797 :
8798 72024222 : switch (code)
8799 : {
8800 : case CLOBBER:
8801 : /* If X is a (clobber (const_int)), return it since we know we are
8802 : generating something that won't match. */
8803 : return x;
8804 :
8805 320795 : case SIGN_EXTEND:
8806 320795 : case ZERO_EXTEND:
8807 320795 : case ZERO_EXTRACT:
8808 320795 : case SIGN_EXTRACT:
8809 320795 : x = expand_compound_operation (x);
8810 320795 : if (GET_CODE (x) != code)
8811 195364 : return force_to_mode (x, mode, mask, next_select);
8812 : break;
8813 :
8814 149 : case TRUNCATE:
8815 : /* Similarly for a truncate. */
8816 149 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8817 :
8818 3546850 : case AND:
8819 : /* If this is an AND with a constant, convert it into an AND
8820 : whose constant is the AND of that constant with MASK. If it
8821 : remains an AND of MASK, delete it since it is redundant. */
8822 :
8823 3546850 : if (CONST_INT_P (XEXP (x, 1)))
8824 : {
8825 5730096 : x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8826 2865048 : mask & INTVAL (XEXP (x, 1)));
8827 2865048 : xmode = op_mode;
8828 :
8829 : /* If X is still an AND, see if it is an AND with a mask that
8830 : is just some low-order bits. If so, and it is MASK, we don't
8831 : need it. */
8832 :
8833 2839411 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8834 5704459 : && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8835 36808 : x = XEXP (x, 0);
8836 :
8837 : /* If it remains an AND, try making another AND with the bits
8838 : in the mode mask that aren't in MASK turned on. If the
8839 : constant in the AND is wide enough, this might make a
8840 : cheaper constant. */
8841 :
8842 2802693 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8843 2802603 : && GET_MODE_MASK (xmode) != mask
8844 2964989 : && HWI_COMPUTABLE_MODE_P (xmode))
8845 : {
8846 99941 : unsigned HOST_WIDE_INT cval
8847 99941 : = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8848 99941 : rtx y;
8849 :
8850 99941 : y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8851 99941 : gen_int_mode (cval, xmode));
8852 99941 : if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8853 99941 : < set_src_cost (x, xmode, optimize_this_for_speed_p))
8854 71720119 : x = y;
8855 : }
8856 :
8857 : break;
8858 : }
8859 :
8860 681802 : goto binop;
8861 :
8862 9846842 : case PLUS:
8863 : /* In (and (plus FOO C1) M), if M is a mask that just turns off
8864 : low-order bits (as in an alignment operation) and FOO is already
8865 : aligned to that boundary, mask C1 to that boundary as well.
8866 : This may eliminate that PLUS and, later, the AND. */
8867 :
8868 9846842 : {
8869 9846842 : unsigned int width = GET_MODE_PRECISION (mode);
8870 9846842 : unsigned HOST_WIDE_INT smask = mask;
8871 :
8872 : /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8873 : number, sign extend it. */
8874 :
8875 9846842 : if (width < HOST_BITS_PER_WIDE_INT
8876 3083104 : && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8877 2761104 : smask |= HOST_WIDE_INT_M1U << width;
8878 :
8879 9846842 : if (CONST_INT_P (XEXP (x, 1))
8880 3643512 : && pow2p_hwi (- smask)
8881 3107109 : && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8882 12558887 : && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8883 10749 : return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8884 10749 : (INTVAL (XEXP (x, 1)) & smask)),
8885 : mode, smask, next_select);
8886 : }
8887 :
8888 : /* fall through */
8889 :
8890 11915184 : case MULT:
8891 : /* Substituting into the operands of a widening MULT is not likely to
8892 : create RTL matching a machine insn. */
8893 11915184 : if (code == MULT
8894 2079091 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8895 2079091 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8896 89010 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8897 89010 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8898 48383 : && REG_P (XEXP (XEXP (x, 0), 0))
8899 42191 : && REG_P (XEXP (XEXP (x, 1), 0)))
8900 34705 : return gen_lowpart_or_truncate (mode, x);
8901 :
8902 : /* For PLUS, MINUS and MULT, we need any bits less significant than the
8903 : most significant bit in MASK since carries from those bits will
8904 : affect the bits we are interested in. */
8905 11880479 : mask = fuller_mask;
8906 11880479 : goto binop;
8907 :
8908 2462355 : case MINUS:
8909 : /* If X is (minus C Y) where C's least set bit is larger than any bit
8910 : in the mask, then we may replace with (neg Y). */
8911 2462355 : if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8912 181542 : && known_alignment (poly_uint64 (const_op0)) > mask)
8913 : {
8914 20 : x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8915 20 : return force_to_mode (x, mode, mask, next_select);
8916 : }
8917 :
8918 : /* Similarly, if C contains every bit in the fuller_mask, then we may
8919 : replace with (not Y). */
8920 2462335 : if (CONST_INT_P (XEXP (x, 0))
8921 181522 : && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8922 : {
8923 326 : x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8924 326 : return force_to_mode (x, mode, mask, next_select);
8925 : }
8926 :
8927 2462009 : mask = fuller_mask;
8928 2462009 : goto binop;
8929 :
8930 2417570 : case IOR:
8931 2417570 : case XOR:
8932 : /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8933 : LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8934 : operation which may be a bitfield extraction. Ensure that the
8935 : constant we form is not wider than the mode of X. */
8936 :
8937 2417570 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8938 62378 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8939 51809 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8940 51809 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8941 51809 : && CONST_INT_P (XEXP (x, 1))
8942 8980 : && ((INTVAL (XEXP (XEXP (x, 0), 1))
8943 17960 : + floor_log2 (INTVAL (XEXP (x, 1))))
8944 8980 : < GET_MODE_PRECISION (xmode))
8945 2417570 : && (UINTVAL (XEXP (x, 1))
8946 4635 : & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8947 : {
8948 8586 : temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8949 4293 : << INTVAL (XEXP (XEXP (x, 0), 1)),
8950 : xmode);
8951 8586 : temp = simplify_gen_binary (GET_CODE (x), xmode,
8952 4293 : XEXP (XEXP (x, 0), 0), temp);
8953 8586 : x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8954 4293 : XEXP (XEXP (x, 0), 1));
8955 4293 : return force_to_mode (x, mode, mask, next_select);
8956 : }
8957 :
8958 17437567 : binop:
8959 : /* For most binary operations, just propagate into the operation and
8960 : change the mode if we have an operation of that mode. */
8961 :
8962 17437567 : op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8963 17437567 : op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8964 :
8965 : /* If we ended up truncating both operands, truncate the result of the
8966 : operation instead. */
8967 17437567 : if (GET_CODE (op0) == TRUNCATE
8968 0 : && GET_CODE (op1) == TRUNCATE)
8969 : {
8970 0 : op0 = XEXP (op0, 0);
8971 0 : op1 = XEXP (op1, 0);
8972 : }
8973 :
8974 17437567 : op0 = gen_lowpart_or_truncate (op_mode, op0);
8975 17437567 : op1 = gen_lowpart_or_truncate (op_mode, op1);
8976 :
8977 17437567 : if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8978 : {
8979 2170726 : x = simplify_gen_binary (code, op_mode, op0, op1);
8980 2170726 : xmode = op_mode;
8981 : }
8982 : break;
8983 :
8984 4240489 : case ASHIFT:
8985 : /* For left shifts, do the same, but just for the first operand.
8986 : However, we cannot do anything with shifts where we cannot
8987 : guarantee that the counts are smaller than the size of the mode
8988 : because such a count will have a different meaning in a
8989 : wider mode. */
8990 :
8991 4036485 : if (! (CONST_INT_P (XEXP (x, 1))
8992 4036489 : && INTVAL (XEXP (x, 1)) >= 0
8993 4036485 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8994 4243138 : && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8995 204000 : && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8996 204000 : < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8997 : break;
8998 :
8999 : /* If the shift count is a constant and we can do arithmetic in
9000 : the mode of the shift, refine which bits we need. Otherwise, use the
9001 : conservative form of the mask. */
9002 4099456 : if (CONST_INT_P (XEXP (x, 1))
9003 4033840 : && INTVAL (XEXP (x, 1)) >= 0
9004 4033840 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9005 8133296 : && HWI_COMPUTABLE_MODE_P (op_mode))
9006 4033106 : mask >>= INTVAL (XEXP (x, 1));
9007 : else
9008 : mask = fuller_mask;
9009 :
9010 4099456 : op0 = gen_lowpart_or_truncate (op_mode,
9011 : force_to_mode (XEXP (x, 0), mode,
9012 : mask, next_select));
9013 :
9014 4099456 : if (op_mode != xmode || op0 != XEXP (x, 0))
9015 : {
9016 1011128 : x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9017 1011128 : xmode = op_mode;
9018 : }
9019 : break;
9020 :
9021 3059223 : case LSHIFTRT:
9022 : /* Here we can only do something if the shift count is a constant,
9023 : this shift constant is valid for the host, and we can do arithmetic
9024 : in OP_MODE. */
9025 :
9026 3059223 : if (CONST_INT_P (XEXP (x, 1))
9027 2949653 : && INTVAL (XEXP (x, 1)) >= 0
9028 2949652 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9029 6008857 : && HWI_COMPUTABLE_MODE_P (op_mode))
9030 : {
9031 2946304 : rtx inner = XEXP (x, 0);
9032 2946304 : unsigned HOST_WIDE_INT inner_mask;
9033 :
9034 : /* Select the mask of the bits we need for the shift operand. */
9035 2946304 : inner_mask = mask << INTVAL (XEXP (x, 1));
9036 :
9037 : /* We can only change the mode of the shift if we can do arithmetic
9038 : in the mode of the shift and INNER_MASK is no wider than the
9039 : width of X's mode. */
9040 2946304 : if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9041 260219 : op_mode = xmode;
9042 :
9043 2946304 : inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9044 :
9045 2946304 : if (xmode != op_mode || inner != XEXP (x, 0))
9046 : {
9047 792192 : x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9048 792192 : xmode = op_mode;
9049 : }
9050 : }
9051 :
9052 : /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9053 : shift and AND produces only copies of the sign bit (C2 is one less
9054 : than a power of two), we can do this with just a shift. */
9055 :
9056 3059223 : if (GET_CODE (x) == LSHIFTRT
9057 3059181 : && CONST_INT_P (XEXP (x, 1))
9058 : /* The shift puts one of the sign bit copies in the least significant
9059 : bit. */
9060 5899222 : && ((INTVAL (XEXP (x, 1))
9061 2949611 : + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9062 2949611 : >= GET_MODE_PRECISION (xmode))
9063 227127 : && pow2p_hwi (mask + 1)
9064 : /* Number of bits left after the shift must be more than the mask
9065 : needs. */
9066 78344 : && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9067 78344 : <= GET_MODE_PRECISION (xmode))
9068 : /* Must be more sign bit copies than the mask needs. */
9069 3088395 : && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9070 29172 : >= exact_log2 (mask + 1)))
9071 : {
9072 29172 : int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9073 29172 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9074 29172 : gen_int_shift_amount (xmode, nbits));
9075 : }
9076 3059223 : goto shiftrt;
9077 :
9078 2051153 : case ASHIFTRT:
9079 : /* If we are just looking for the sign bit, we don't need this shift at
9080 : all, even if it has a variable count. */
9081 2051153 : if (val_signbit_p (xmode, mask))
9082 1301 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9083 :
9084 : /* If this is a shift by a constant, get a mask that contains those bits
9085 : that are not copies of the sign bit. We then have two cases: If
9086 : MASK only includes those bits, this can be a logical shift, which may
9087 : allow simplifications. If MASK is a single-bit field not within
9088 : those bits, we are requesting a copy of the sign bit and hence can
9089 : shift the sign bit to the appropriate location. */
9090 :
9091 2049852 : if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9092 2004923 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9093 : {
9094 2004812 : unsigned HOST_WIDE_INT nonzero;
9095 2004812 : int i;
9096 :
9097 : /* If the considered data is wider than HOST_WIDE_INT, we can't
9098 : represent a mask for all its bits in a single scalar.
9099 : But we only care about the lower bits, so calculate these. */
9100 :
9101 2004812 : if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9102 : {
9103 400 : nonzero = HOST_WIDE_INT_M1U;
9104 :
9105 : /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9106 : is the number of bits a full-width mask would have set.
9107 : We need only shift if these are fewer than nonzero can
9108 : hold. If not, we must keep all bits set in nonzero. */
9109 :
9110 400 : if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9111 : < HOST_BITS_PER_WIDE_INT)
9112 0 : nonzero >>= INTVAL (XEXP (x, 1))
9113 0 : + HOST_BITS_PER_WIDE_INT
9114 0 : - GET_MODE_PRECISION (xmode);
9115 : }
9116 : else
9117 : {
9118 2004412 : nonzero = GET_MODE_MASK (xmode);
9119 2004412 : nonzero >>= INTVAL (XEXP (x, 1));
9120 : }
9121 :
9122 2004812 : if ((mask & ~nonzero) == 0)
9123 : {
9124 49276 : x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9125 : XEXP (x, 0), INTVAL (XEXP (x, 1)));
9126 49276 : if (GET_CODE (x) != ASHIFTRT)
9127 49276 : return force_to_mode (x, mode, mask, next_select);
9128 : }
9129 :
9130 1955536 : else if ((i = exact_log2 (mask)) >= 0)
9131 : {
9132 178 : x = simplify_shift_const
9133 356 : (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9134 178 : GET_MODE_PRECISION (xmode) - 1 - i);
9135 :
9136 178 : if (GET_CODE (x) != ASHIFTRT)
9137 178 : return force_to_mode (x, mode, mask, next_select);
9138 : }
9139 : }
9140 :
9141 : /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9142 : even if the shift count isn't a constant. */
9143 2000398 : if (mask == 1)
9144 3141 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9145 :
9146 1997257 : shiftrt:
9147 :
9148 : /* If this is a zero- or sign-extension operation that just affects bits
9149 : we don't care about, remove it. Be sure the call above returned
9150 : something that is still a shift. */
9151 :
9152 5059621 : if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9153 5059579 : && CONST_INT_P (XEXP (x, 1))
9154 4905080 : && INTVAL (XEXP (x, 1)) >= 0
9155 4905079 : && (INTVAL (XEXP (x, 1))
9156 9810158 : <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9157 1764701 : && GET_CODE (XEXP (x, 0)) == ASHIFT
9158 5060530 : && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9159 772 : return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, next_select);
9160 :
9161 : break;
9162 :
9163 36836 : case ROTATE:
9164 36836 : case ROTATERT:
9165 : /* If the shift count is constant and we can do computations
9166 : in the mode of X, compute where the bits we care about are.
9167 : Otherwise, we can't do anything. Don't change the mode of
9168 : the shift or propagate MODE into the shift, though. */
9169 36836 : if (CONST_INT_P (XEXP (x, 1))
9170 26639 : && INTVAL (XEXP (x, 1)) >= 0)
9171 : {
9172 26637 : temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9173 26637 : xmode, gen_int_mode (mask, xmode),
9174 : XEXP (x, 1));
9175 26637 : if (temp && CONST_INT_P (temp))
9176 26637 : x = simplify_gen_binary (code, xmode,
9177 : force_to_mode (XEXP (x, 0), xmode,
9178 26637 : INTVAL (temp), next_select),
9179 : XEXP (x, 1));
9180 : }
9181 : break;
9182 :
9183 156941 : case NEG:
9184 : /* If we just want the low-order bit, the NEG isn't needed since it
9185 : won't change the low-order bit. */
9186 156941 : if (mask == 1)
9187 365 : return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9188 :
9189 : /* We need any bits less significant than the most significant bit in
9190 : MASK since carries from those bits will affect the bits we are
9191 : interested in. */
9192 156576 : mask = fuller_mask;
9193 156576 : goto unop;
9194 :
9195 459607 : case NOT:
9196 : /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9197 : same as the XOR case above. Ensure that the constant we form is not
9198 : wider than the mode of X. */
9199 :
9200 459607 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9201 21049 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9202 20446 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9203 40892 : && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9204 20446 : < GET_MODE_PRECISION (xmode))
9205 466212 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9206 : {
9207 6605 : temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9208 6605 : temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9209 13210 : x = simplify_gen_binary (LSHIFTRT, xmode,
9210 6605 : temp, XEXP (XEXP (x, 0), 1));
9211 :
9212 6605 : return force_to_mode (x, mode, mask, next_select);
9213 : }
9214 :
9215 : /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9216 : use the full mask inside the NOT. */
9217 : mask = fuller_mask;
9218 :
9219 609578 : unop:
9220 609578 : op0 = gen_lowpart_or_truncate (op_mode,
9221 : force_to_mode (XEXP (x, 0), mode, mask,
9222 : next_select));
9223 609578 : if (op_mode != xmode || op0 != XEXP (x, 0))
9224 : {
9225 79326 : x = simplify_gen_unary (code, op_mode, op0, op_mode);
9226 79326 : xmode = op_mode;
9227 : }
9228 : break;
9229 :
9230 576863 : case NE:
9231 : /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9232 : in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9233 : which is equal to STORE_FLAG_VALUE. */
9234 576863 : if ((mask & ~STORE_FLAG_VALUE) == 0
9235 2447 : && XEXP (x, 1) == const0_rtx
9236 2426 : && GET_MODE (XEXP (x, 0)) == mode
9237 9 : && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9238 576863 : && (nonzero_bits (XEXP (x, 0), mode)
9239 : == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9240 0 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9241 :
9242 : break;
9243 :
9244 1544460 : case IF_THEN_ELSE:
9245 : /* We have no way of knowing if the IF_THEN_ELSE can itself be
9246 : written in a narrower mode. We play it safe and do not do so. */
9247 :
9248 1544460 : op0 = gen_lowpart_or_truncate (xmode,
9249 : force_to_mode (XEXP (x, 1), mode,
9250 : mask, next_select));
9251 1544460 : op1 = gen_lowpart_or_truncate (xmode,
9252 : force_to_mode (XEXP (x, 2), mode,
9253 : mask, next_select));
9254 1544460 : if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9255 251496 : x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9256 251496 : GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9257 : op0, op1);
9258 : break;
9259 :
9260 : default:
9261 : break;
9262 : }
9263 :
9264 : /* Ensure we return a value of the proper mode. */
9265 71720119 : return gen_lowpart_or_truncate (mode, x);
9266 : }
9267 :
9268 : /* Return nonzero if X is an expression that has one of two values depending on
9269 : whether some other value is zero or nonzero. In that case, we return the
9270 : value that is being tested, *PTRUE is set to the value if the rtx being
9271 : returned has a nonzero value, and *PFALSE is set to the other alternative.
9272 :
9273 : If we return zero, we set *PTRUE and *PFALSE to X. */
9274 :
9275 : static rtx
9276 240972645 : if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9277 : {
9278 240972645 : machine_mode mode = GET_MODE (x);
9279 240972645 : enum rtx_code code = GET_CODE (x);
9280 240972645 : rtx cond0, cond1, true0, true1, false0, false1;
9281 240972645 : unsigned HOST_WIDE_INT nz;
9282 240972645 : scalar_int_mode int_mode;
9283 :
9284 : /* If we are comparing a value against zero, we are done. */
9285 240972645 : if ((code == NE || code == EQ)
9286 2653146 : && XEXP (x, 1) == const0_rtx)
9287 : {
9288 1619375 : *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9289 1619375 : *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9290 1619375 : return XEXP (x, 0);
9291 : }
9292 :
9293 : /* If this is a unary operation whose operand has one of two values, apply
9294 : our opcode to compute those values. */
9295 239353270 : else if (UNARY_P (x)
9296 239353270 : && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9297 : {
9298 480419 : *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9299 960838 : *pfalse = simplify_gen_unary (code, mode, false0,
9300 480419 : GET_MODE (XEXP (x, 0)));
9301 480419 : return cond0;
9302 : }
9303 :
9304 : /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9305 : make can't possibly match and would suppress other optimizations. */
9306 238872851 : else if (code == COMPARE)
9307 : ;
9308 :
9309 : /* If this is a binary operation, see if either side has only one of two
9310 : values. If either one does or if both do and they are conditional on
9311 : the same value, compute the new true and false values. */
9312 234509925 : else if (BINARY_P (x))
9313 : {
9314 86651847 : rtx op0 = XEXP (x, 0);
9315 86651847 : rtx op1 = XEXP (x, 1);
9316 86651847 : cond0 = if_then_else_cond (op0, &true0, &false0);
9317 86651847 : cond1 = if_then_else_cond (op1, &true1, &false1);
9318 :
9319 578626 : if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9320 87176118 : && (REG_P (op0) || REG_P (op1)))
9321 : {
9322 : /* Try to enable a simplification by undoing work done by
9323 : if_then_else_cond if it converted a REG into something more
9324 : complex. */
9325 455634 : if (REG_P (op0))
9326 : {
9327 117280 : cond0 = 0;
9328 117280 : true0 = false0 = op0;
9329 : }
9330 : else
9331 : {
9332 338354 : cond1 = 0;
9333 338354 : true1 = false1 = op1;
9334 : }
9335 : }
9336 :
9337 86651847 : if ((cond0 != 0 || cond1 != 0)
9338 86651847 : && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9339 : {
9340 : /* If if_then_else_cond returned zero, then true/false are the
9341 : same rtl. We must copy one of them to prevent invalid rtl
9342 : sharing. */
9343 4902941 : if (cond0 == 0)
9344 1437749 : true0 = copy_rtx (true0);
9345 3465192 : else if (cond1 == 0)
9346 3410837 : true1 = copy_rtx (true1);
9347 :
9348 4902941 : if (COMPARISON_P (x))
9349 : {
9350 269069 : *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9351 : true0, true1);
9352 269069 : *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9353 : false0, false1);
9354 : }
9355 : else
9356 : {
9357 4633872 : *ptrue = simplify_gen_binary (code, mode, true0, true1);
9358 4633872 : *pfalse = simplify_gen_binary (code, mode, false0, false1);
9359 : }
9360 :
9361 4902941 : return cond0 ? cond0 : cond1;
9362 : }
9363 :
9364 : /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9365 : operands is zero when the other is nonzero, and vice-versa,
9366 : and STORE_FLAG_VALUE is 1 or -1. */
9367 :
9368 81748906 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9369 81748906 : && (code == PLUS || code == IOR || code == XOR || code == MINUS
9370 : || code == UMAX)
9371 33894013 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9372 : {
9373 37781 : rtx op0 = XEXP (XEXP (x, 0), 1);
9374 37781 : rtx op1 = XEXP (XEXP (x, 1), 1);
9375 :
9376 37781 : cond0 = XEXP (XEXP (x, 0), 0);
9377 37781 : cond1 = XEXP (XEXP (x, 1), 0);
9378 :
9379 37781 : if (COMPARISON_P (cond0)
9380 11 : && COMPARISON_P (cond1)
9381 0 : && SCALAR_INT_MODE_P (mode)
9382 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9383 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9384 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9385 0 : || ((swap_condition (GET_CODE (cond0))
9386 0 : == reversed_comparison_code (cond1, NULL))
9387 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9388 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9389 37781 : && ! side_effects_p (x))
9390 : {
9391 0 : *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9392 0 : *pfalse = simplify_gen_binary (MULT, mode,
9393 : (code == MINUS
9394 0 : ? simplify_gen_unary (NEG, mode,
9395 : op1, mode)
9396 : : op1),
9397 : const_true_rtx);
9398 0 : return cond0;
9399 : }
9400 : }
9401 :
9402 : /* Similarly for MULT, AND and UMIN, except that for these the result
9403 : is always zero. */
9404 81748906 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9405 81748906 : && (code == MULT || code == AND || code == UMIN)
9406 11535791 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9407 : {
9408 961 : cond0 = XEXP (XEXP (x, 0), 0);
9409 961 : cond1 = XEXP (XEXP (x, 1), 0);
9410 :
9411 961 : if (COMPARISON_P (cond0)
9412 0 : && COMPARISON_P (cond1)
9413 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9414 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9415 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9416 0 : || ((swap_condition (GET_CODE (cond0))
9417 0 : == reversed_comparison_code (cond1, NULL))
9418 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9419 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9420 961 : && ! side_effects_p (x))
9421 : {
9422 0 : *ptrue = *pfalse = const0_rtx;
9423 0 : return cond0;
9424 : }
9425 : }
9426 : }
9427 :
9428 147858078 : else if (code == IF_THEN_ELSE)
9429 : {
9430 : /* If we have IF_THEN_ELSE already, extract the condition and
9431 : canonicalize it if it is NE or EQ. */
9432 741114 : cond0 = XEXP (x, 0);
9433 741114 : *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9434 741114 : if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9435 261299 : return XEXP (cond0, 0);
9436 479815 : else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9437 : {
9438 32050 : *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9439 32050 : return XEXP (cond0, 0);
9440 : }
9441 : else
9442 : return cond0;
9443 : }
9444 :
9445 : /* If X is a SUBREG, we can narrow both the true and false values
9446 : if the inner expression, if there is a condition. */
9447 147116964 : else if (code == SUBREG
9448 147116964 : && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9449 : &false0)) != 0)
9450 : {
9451 1225894 : true0 = simplify_gen_subreg (mode, true0,
9452 612947 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9453 1225894 : false0 = simplify_gen_subreg (mode, false0,
9454 612947 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9455 612947 : if (true0 && false0)
9456 : {
9457 612947 : *ptrue = true0;
9458 612947 : *pfalse = false0;
9459 612947 : return cond0;
9460 : }
9461 : }
9462 :
9463 : /* If X is a constant, this isn't special and will cause confusions
9464 : if we treat it as such. Likewise if it is equivalent to a constant. */
9465 146504017 : else if (CONSTANT_P (x)
9466 146504017 : || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9467 : ;
9468 :
9469 : /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9470 : will be least confusing to the rest of the compiler. */
9471 99565330 : else if (mode == BImode)
9472 : {
9473 0 : *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9474 0 : return x;
9475 : }
9476 :
9477 : /* If X is known to be either 0 or -1, those are the true and
9478 : false values when testing X. */
9479 99565330 : else if (x == constm1_rtx || x == const0_rtx
9480 99565330 : || (is_a <scalar_int_mode> (mode, &int_mode)
9481 70481275 : && (num_sign_bit_copies (x, int_mode)
9482 70481275 : == GET_MODE_PRECISION (int_mode))))
9483 : {
9484 971399 : *ptrue = constm1_rtx, *pfalse = const0_rtx;
9485 971399 : return x;
9486 : }
9487 :
9488 : /* Likewise for 0 or a single bit. */
9489 98593931 : else if (HWI_COMPUTABLE_MODE_P (mode)
9490 66222461 : && pow2p_hwi (nz = nonzero_bits (x, mode)))
9491 : {
9492 1901658 : *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9493 1901658 : return x;
9494 : }
9495 :
9496 : /* Otherwise fail; show no condition with true and false values the same. */
9497 229742792 : *ptrue = *pfalse = x;
9498 229742792 : return 0;
9499 : }
9500 :
9501 : /* Return the value of expression X given the fact that condition COND
9502 : is known to be true when applied to REG as its first operand and VAL
9503 : as its second. X is known to not be shared and so can be modified in
9504 : place.
9505 :
9506 : We only handle the simplest cases, and specifically those cases that
9507 : arise with IF_THEN_ELSE expressions. */
9508 :
9509 : static rtx
9510 658215 : known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9511 : {
9512 658215 : enum rtx_code code = GET_CODE (x);
9513 658215 : const char *fmt;
9514 658215 : int i, j;
9515 :
9516 658215 : if (side_effects_p (x))
9517 : return x;
9518 :
9519 : /* If either operand of the condition is a floating point value,
9520 : then we have to avoid collapsing an EQ comparison. */
9521 658215 : if (cond == EQ
9522 124509 : && rtx_equal_p (x, reg)
9523 82720 : && ! FLOAT_MODE_P (GET_MODE (x))
9524 740935 : && ! FLOAT_MODE_P (GET_MODE (val)))
9525 : return val;
9526 :
9527 575495 : if (cond == UNEQ && rtx_equal_p (x, reg))
9528 : return val;
9529 :
9530 : /* If X is (abs REG) and we know something about REG's relationship
9531 : with zero, we may be able to simplify this. */
9532 :
9533 575495 : if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9534 3 : switch (cond)
9535 : {
9536 1 : case GE: case GT: case EQ:
9537 1 : return XEXP (x, 0);
9538 2 : case LT: case LE:
9539 4 : return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9540 : XEXP (x, 0),
9541 2 : GET_MODE (XEXP (x, 0)));
9542 : default:
9543 : break;
9544 : }
9545 :
9546 : /* The only other cases we handle are MIN, MAX, and comparisons if the
9547 : operands are the same as REG and VAL. */
9548 :
9549 575492 : else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9550 : {
9551 239877 : if (rtx_equal_p (XEXP (x, 0), val))
9552 : {
9553 2 : std::swap (val, reg);
9554 2 : cond = swap_condition (cond);
9555 : }
9556 :
9557 239877 : if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9558 : {
9559 220398 : if (COMPARISON_P (x))
9560 : {
9561 220196 : if (comparison_dominates_p (cond, code))
9562 455 : return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9563 :
9564 219741 : code = reversed_comparison_code (x, NULL);
9565 219741 : if (code != UNKNOWN
9566 219741 : && comparison_dominates_p (cond, code))
9567 50 : return CONST0_RTX (GET_MODE (x));
9568 : else
9569 : return x;
9570 : }
9571 202 : else if (code == SMAX || code == SMIN
9572 202 : || code == UMIN || code == UMAX)
9573 : {
9574 39 : int unsignedp = (code == UMIN || code == UMAX);
9575 :
9576 : /* Do not reverse the condition when it is NE or EQ.
9577 : This is because we cannot conclude anything about
9578 : the value of 'SMAX (x, y)' when x is not equal to y,
9579 : but we can when x equals y. */
9580 39 : if ((code == SMAX || code == UMAX)
9581 36 : && ! (cond == EQ || cond == NE))
9582 3 : cond = reverse_condition (cond);
9583 :
9584 6 : switch (cond)
9585 : {
9586 2 : case GE: case GT:
9587 2 : return unsignedp ? x : XEXP (x, 1);
9588 4 : case LE: case LT:
9589 4 : return unsignedp ? x : XEXP (x, 0);
9590 0 : case GEU: case GTU:
9591 0 : return unsignedp ? XEXP (x, 1) : x;
9592 0 : case LEU: case LTU:
9593 0 : return unsignedp ? XEXP (x, 0) : x;
9594 : default:
9595 : break;
9596 : }
9597 : }
9598 : }
9599 : }
9600 335615 : else if (code == SUBREG)
9601 : {
9602 8576 : machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9603 8576 : rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9604 :
9605 8576 : if (SUBREG_REG (x) != r)
9606 : {
9607 : /* We must simplify subreg here, before we lose track of the
9608 : original inner_mode. */
9609 34 : new_rtx = simplify_subreg (GET_MODE (x), r,
9610 17 : inner_mode, SUBREG_BYTE (x));
9611 17 : if (new_rtx)
9612 : return new_rtx;
9613 : else
9614 17 : SUBST (SUBREG_REG (x), r);
9615 : }
9616 :
9617 : return x;
9618 : }
9619 : /* We don't have to handle SIGN_EXTEND here, because even in the
9620 : case of replacing something with a modeless CONST_INT, a
9621 : CONST_INT is already (supposed to be) a valid sign extension for
9622 : its narrower mode, which implies it's already properly
9623 : sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9624 : story is different. */
9625 327039 : else if (code == ZERO_EXTEND)
9626 : {
9627 1222 : machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9628 1222 : rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9629 :
9630 1222 : if (XEXP (x, 0) != r)
9631 : {
9632 : /* We must simplify the zero_extend here, before we lose
9633 : track of the original inner_mode. */
9634 0 : new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9635 : r, inner_mode);
9636 0 : if (new_rtx)
9637 : return new_rtx;
9638 : else
9639 0 : SUBST (XEXP (x, 0), r);
9640 : }
9641 :
9642 : return x;
9643 : }
9644 :
9645 345492 : fmt = GET_RTX_FORMAT (code);
9646 780955 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9647 : {
9648 435463 : if (fmt[i] == 'e')
9649 184467 : SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9650 250996 : else if (fmt[i] == 'E')
9651 15148 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9652 12212 : SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9653 : cond, reg, val));
9654 : }
9655 :
9656 : return x;
9657 : }
9658 :
9659 : /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9660 : assignment as a field assignment. */
9661 :
9662 : static bool
9663 545041 : rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9664 : {
9665 545041 : if (widen_x && GET_MODE (x) != GET_MODE (y))
9666 : {
9667 56590 : if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9668 : return false;
9669 56590 : if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9670 : return false;
9671 56590 : x = adjust_address_nv (x, GET_MODE (y),
9672 : byte_lowpart_offset (GET_MODE (y),
9673 : GET_MODE (x)));
9674 : }
9675 :
9676 545041 : if (x == y || rtx_equal_p (x, y))
9677 : return true;
9678 :
9679 535222 : if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9680 : return false;
9681 :
9682 : /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9683 : Note that all SUBREGs of MEM are paradoxical; otherwise they
9684 : would have been rewritten. */
9685 92967 : if (MEM_P (x) && GET_CODE (y) == SUBREG
9686 6340 : && MEM_P (SUBREG_REG (y))
9687 535220 : && rtx_equal_p (SUBREG_REG (y),
9688 0 : gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9689 : return true;
9690 :
9691 60191 : if (MEM_P (y) && GET_CODE (x) == SUBREG
9692 4790 : && MEM_P (SUBREG_REG (x))
9693 535454 : && rtx_equal_p (SUBREG_REG (x),
9694 234 : gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9695 : return true;
9696 :
9697 : /* We used to see if get_last_value of X and Y were the same but that's
9698 : not correct. In one direction, we'll cause the assignment to have
9699 : the wrong destination and in the case, we'll import a register into this
9700 : insn that might have already have been dead. So fail if none of the
9701 : above cases are true. */
9702 : return false;
9703 : }
9704 :
9705 : /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9706 : Return that assignment if so.
9707 :
9708 : We only handle the most common cases. */
9709 :
9710 : static rtx
9711 47727034 : make_field_assignment (rtx x)
9712 : {
9713 47727034 : rtx dest = SET_DEST (x);
9714 47727034 : rtx src = SET_SRC (x);
9715 47727034 : rtx assign;
9716 47727034 : rtx rhs, lhs;
9717 47727034 : HOST_WIDE_INT c1;
9718 47727034 : HOST_WIDE_INT pos;
9719 47727034 : unsigned HOST_WIDE_INT len;
9720 47727034 : rtx other;
9721 :
9722 : /* All the rules in this function are specific to scalar integers. */
9723 47727034 : scalar_int_mode mode;
9724 47727034 : if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9725 : return x;
9726 :
9727 : /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9728 : a clear of a one-bit field. We will have changed it to
9729 : (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9730 : for a SUBREG. */
9731 :
9732 1262852 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9733 1607 : && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9734 545 : && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9735 21868587 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9736 : {
9737 156 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9738 : 1, true, true, false);
9739 156 : if (assign != 0)
9740 153 : return gen_rtx_SET (assign, const0_rtx);
9741 : return x;
9742 : }
9743 :
9744 1262696 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9745 85719 : && subreg_lowpart_p (XEXP (src, 0))
9746 85686 : && partial_subreg_p (XEXP (src, 0))
9747 20195 : && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9748 125 : && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9749 57 : && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9750 21867943 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9751 : {
9752 14 : assign = make_extraction (VOIDmode, dest, 0,
9753 7 : XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9754 : 1, true, true, false);
9755 7 : if (assign != 0)
9756 7 : return gen_rtx_SET (assign, const0_rtx);
9757 : return x;
9758 : }
9759 :
9760 : /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9761 : one-bit field. */
9762 1753358 : if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9763 417925 : && XEXP (XEXP (src, 0), 0) == const1_rtx
9764 21870172 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9765 : {
9766 554 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9767 : 1, true, true, false);
9768 554 : if (assign != 0)
9769 525 : return gen_rtx_SET (assign, const1_rtx);
9770 : return x;
9771 : }
9772 :
9773 : /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9774 : SRC is an AND with all bits of that field set, then we can discard
9775 : the AND. */
9776 21867325 : if (GET_CODE (dest) == ZERO_EXTRACT
9777 2796 : && CONST_INT_P (XEXP (dest, 1))
9778 2796 : && GET_CODE (src) == AND
9779 840 : && CONST_INT_P (XEXP (src, 1)))
9780 : {
9781 840 : HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9782 840 : unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9783 840 : unsigned HOST_WIDE_INT ze_mask;
9784 :
9785 840 : if (width >= HOST_BITS_PER_WIDE_INT)
9786 : ze_mask = -1;
9787 : else
9788 840 : ze_mask = (HOST_WIDE_INT_1U << width) - 1;
9789 :
9790 : /* Complete overlap. We can remove the source AND. */
9791 840 : if ((and_mask & ze_mask) == ze_mask)
9792 792 : return gen_rtx_SET (dest, XEXP (src, 0));
9793 :
9794 : /* Partial overlap. We can reduce the source AND. */
9795 48 : if ((and_mask & ze_mask) != and_mask)
9796 : {
9797 6 : src = gen_rtx_AND (mode, XEXP (src, 0),
9798 : gen_int_mode (and_mask & ze_mask, mode));
9799 6 : return gen_rtx_SET (dest, src);
9800 : }
9801 : }
9802 :
9803 : /* The other case we handle is assignments into a constant-position
9804 : field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9805 : a mask that has all one bits except for a group of zero bits and
9806 : OTHER is known to have zeros where C1 has ones, this is such an
9807 : assignment. Compute the position and length from C1. Shift OTHER
9808 : to the appropriate position, force it to the required mode, and
9809 : make the extraction. Check for the AND in both operands. */
9810 :
9811 : /* One or more SUBREGs might obscure the constant-position field
9812 : assignment. The first one we are likely to encounter is an outer
9813 : narrowing SUBREG, which we can just strip for the purposes of
9814 : identifying the constant-field assignment. */
9815 21866527 : scalar_int_mode src_mode = mode;
9816 21866527 : if (GET_CODE (src) == SUBREG
9817 210255 : && subreg_lowpart_p (src)
9818 22060957 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9819 21866527 : src = SUBREG_REG (src);
9820 :
9821 21866527 : if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9822 : return x;
9823 :
9824 1936587 : rhs = expand_compound_operation (XEXP (src, 0));
9825 1936587 : lhs = expand_compound_operation (XEXP (src, 1));
9826 :
9827 1936587 : if (GET_CODE (rhs) == AND
9828 758959 : && CONST_INT_P (XEXP (rhs, 1))
9829 2349582 : && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9830 9129 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9831 : /* The second SUBREG that might get in the way is a paradoxical
9832 : SUBREG around the first operand of the AND. We want to
9833 : pretend the operand is as wide as the destination here. We
9834 : do this by adjusting the MEM to wider mode for the sole
9835 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9836 : note this trick only works for MEMs. */
9837 1927458 : else if (GET_CODE (rhs) == AND
9838 749830 : && paradoxical_subreg_p (XEXP (rhs, 0))
9839 72001 : && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9840 31385 : && CONST_INT_P (XEXP (rhs, 1))
9841 1958843 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9842 : dest, true))
9843 0 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9844 1927458 : else if (GET_CODE (lhs) == AND
9845 80827 : && CONST_INT_P (XEXP (lhs, 1))
9846 2000019 : && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9847 30 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9848 : /* The second SUBREG that might get in the way is a paradoxical
9849 : SUBREG around the first operand of the AND. We want to
9850 : pretend the operand is as wide as the destination here. We
9851 : do this by adjusting the MEM to wider mode for the sole
9852 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9853 : note this trick only works for MEMs. */
9854 1927428 : else if (GET_CODE (lhs) == AND
9855 80797 : && paradoxical_subreg_p (XEXP (lhs, 0))
9856 42280 : && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9857 25205 : && CONST_INT_P (XEXP (lhs, 1))
9858 1952633 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9859 : dest, true))
9860 0 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9861 : else
9862 : return x;
9863 :
9864 9159 : pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9865 9159 : if (pos < 0
9866 6909 : || pos + len > GET_MODE_PRECISION (mode)
9867 6909 : || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9868 16056 : || (c1 & nonzero_bits (other, mode)) != 0)
9869 : return x;
9870 :
9871 5864 : assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len,
9872 : true, true, false);
9873 5864 : if (assign == 0)
9874 : return x;
9875 :
9876 : /* The mode to use for the source is the mode of the assignment, or of
9877 : what is inside a possible STRICT_LOW_PART. */
9878 11704 : machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9879 5852 : ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9880 :
9881 : /* Shift OTHER right POS places and make it the source, restricting it
9882 : to the proper length and mode. */
9883 :
9884 5852 : src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9885 : src_mode, other, pos),
9886 : dest);
9887 11704 : src = force_to_mode (src, new_mode,
9888 : len >= HOST_BITS_PER_WIDE_INT
9889 : ? HOST_WIDE_INT_M1U
9890 5852 : : (HOST_WIDE_INT_1U << len) - 1, false);
9891 :
9892 : /* If SRC is masked by an AND that does not make a difference in
9893 : the value being stored, strip it. */
9894 5852 : if (GET_CODE (assign) == ZERO_EXTRACT
9895 5797 : && CONST_INT_P (XEXP (assign, 1))
9896 5797 : && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9897 5797 : && GET_CODE (src) == AND
9898 0 : && CONST_INT_P (XEXP (src, 1))
9899 0 : && UINTVAL (XEXP (src, 1))
9900 0 : == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9901 0 : src = XEXP (src, 0);
9902 :
9903 5852 : return gen_rtx_SET (assign, src);
9904 : }
9905 :
9906 : /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9907 : if so. */
9908 :
9909 : static rtx
9910 51959208 : apply_distributive_law (rtx x)
9911 : {
9912 51959208 : enum rtx_code code = GET_CODE (x);
9913 51959208 : enum rtx_code inner_code;
9914 51959208 : rtx lhs, rhs, other;
9915 51959208 : rtx tem;
9916 :
9917 : /* Distributivity is not true for floating point as it can change the
9918 : value. So we don't do it unless -funsafe-math-optimizations. */
9919 51959208 : if (FLOAT_MODE_P (GET_MODE (x))
9920 3633867 : && ! flag_unsafe_math_optimizations)
9921 : return x;
9922 :
9923 : /* The outer operation can only be one of the following: */
9924 48758805 : if (code != IOR && code != AND && code != XOR
9925 48758805 : && code != PLUS && code != MINUS)
9926 : return x;
9927 :
9928 48744879 : lhs = XEXP (x, 0);
9929 48744879 : rhs = XEXP (x, 1);
9930 :
9931 : /* If either operand is a primitive we can't do anything, so get out
9932 : fast. */
9933 48744879 : if (OBJECT_P (lhs) || OBJECT_P (rhs))
9934 : return x;
9935 :
9936 3488487 : lhs = expand_compound_operation (lhs);
9937 3488487 : rhs = expand_compound_operation (rhs);
9938 3488487 : inner_code = GET_CODE (lhs);
9939 3488487 : if (inner_code != GET_CODE (rhs))
9940 : return x;
9941 :
9942 : /* See if the inner and outer operations distribute. */
9943 1002008 : switch (inner_code)
9944 : {
9945 241175 : case LSHIFTRT:
9946 241175 : case ASHIFTRT:
9947 241175 : case AND:
9948 241175 : case IOR:
9949 : /* These all distribute except over PLUS. */
9950 241175 : if (code == PLUS || code == MINUS)
9951 : return x;
9952 : break;
9953 :
9954 100877 : case MULT:
9955 100877 : if (code != PLUS && code != MINUS)
9956 : return x;
9957 : break;
9958 :
9959 : case ASHIFT:
9960 : /* This is also a multiply, so it distributes over everything. */
9961 : break;
9962 :
9963 : /* This used to handle SUBREG, but this turned out to be counter-
9964 : productive, since (subreg (op ...)) usually is not handled by
9965 : insn patterns, and this "optimization" therefore transformed
9966 : recognizable patterns into unrecognizable ones. Therefore the
9967 : SUBREG case was removed from here.
9968 :
9969 : It is possible that distributing SUBREG over arithmetic operations
9970 : leads to an intermediate result than can then be optimized further,
9971 : e.g. by moving the outer SUBREG to the other side of a SET as done
9972 : in simplify_set. This seems to have been the original intent of
9973 : handling SUBREGs here.
9974 :
9975 : However, with current GCC this does not appear to actually happen,
9976 : at least on major platforms. If some case is found where removing
9977 : the SUBREG case here prevents follow-on optimizations, distributing
9978 : SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9979 :
9980 : default:
9981 : return x;
9982 : }
9983 :
9984 : /* Set LHS and RHS to the inner operands (A and B in the example
9985 : above) and set OTHER to the common operand (C in the example).
9986 : There is only one way to do this unless the inner operation is
9987 : commutative. */
9988 270186 : if (COMMUTATIVE_ARITH_P (lhs)
9989 270186 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9990 2509 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9991 267677 : else if (COMMUTATIVE_ARITH_P (lhs)
9992 267677 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9993 21 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9994 267656 : else if (COMMUTATIVE_ARITH_P (lhs)
9995 267656 : && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9996 11317 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9997 256339 : else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9998 70077 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9999 : else
10000 : return x;
10001 :
10002 : /* Form the new inner operation, seeing if it simplifies first. */
10003 83924 : tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10004 :
10005 : /* There is one exception to the general way of distributing:
10006 : (a | c) ^ (b | c) -> (a ^ b) & ~c */
10007 83924 : if (code == XOR && inner_code == IOR)
10008 : {
10009 1251 : inner_code = AND;
10010 1251 : other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10011 : }
10012 :
10013 : /* We may be able to continuing distributing the result, so call
10014 : ourselves recursively on the inner operation before forming the
10015 : outer operation, which we return. */
10016 83924 : return simplify_gen_binary (inner_code, GET_MODE (x),
10017 83924 : apply_distributive_law (tem), other);
10018 : }
10019 :
10020 : /* See if X is of the form (* (+ A B) C), and if so convert to
10021 : (+ (* A C) (* B C)) and try to simplify.
10022 :
10023 : Most of the time, this results in no change. However, if some of
10024 : the operands are the same or inverses of each other, simplifications
10025 : will result.
10026 :
10027 : For example, (and (ior A B) (not B)) can occur as the result of
10028 : expanding a bit field assignment. When we apply the distributive
10029 : law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10030 : which then simplifies to (and (A (not B))).
10031 :
10032 : Note that no checks happen on the validity of applying the inverse
10033 : distributive law. This is pointless since we can do it in the
10034 : few places where this routine is called.
10035 :
10036 : N is the index of the term that is decomposed (the arithmetic operation,
10037 : i.e. (+ A B) in the first example above). !N is the index of the term that
10038 : is distributed, i.e. of C in the first example above. */
10039 : static rtx
10040 1637134 : distribute_and_simplify_rtx (rtx x, int n)
10041 : {
10042 1637134 : machine_mode mode;
10043 1637134 : enum rtx_code outer_code, inner_code;
10044 1637134 : rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10045 :
10046 : /* Distributivity is not true for floating point as it can change the
10047 : value. So we don't do it unless -funsafe-math-optimizations. */
10048 1637134 : if (FLOAT_MODE_P (GET_MODE (x))
10049 164449 : && ! flag_unsafe_math_optimizations)
10050 : return NULL_RTX;
10051 :
10052 1476102 : decomposed = XEXP (x, n);
10053 1476102 : if (!ARITHMETIC_P (decomposed))
10054 : return NULL_RTX;
10055 :
10056 1476102 : mode = GET_MODE (x);
10057 1476102 : outer_code = GET_CODE (x);
10058 1476102 : distributed = XEXP (x, !n);
10059 :
10060 1476102 : inner_code = GET_CODE (decomposed);
10061 1476102 : inner_op0 = XEXP (decomposed, 0);
10062 1476102 : inner_op1 = XEXP (decomposed, 1);
10063 :
10064 : /* Special case (and (xor B C) (not A)), which is equivalent to
10065 : (xor (ior A B) (ior A C)) */
10066 1476102 : if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10067 : {
10068 1246 : distributed = XEXP (distributed, 0);
10069 1246 : outer_code = IOR;
10070 : }
10071 :
10072 1476102 : if (n == 0)
10073 : {
10074 : /* Distribute the second term. */
10075 1428724 : new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10076 1428724 : new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10077 : }
10078 : else
10079 : {
10080 : /* Distribute the first term. */
10081 47378 : new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10082 47378 : new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10083 : }
10084 :
10085 1476102 : tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10086 : new_op0, new_op1));
10087 1476102 : if (GET_CODE (tmp) != outer_code
10088 1476102 : && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10089 262140 : < set_src_cost (x, mode, optimize_this_for_speed_p)))
10090 17182 : return tmp;
10091 :
10092 : return NULL_RTX;
10093 : }
10094 :
10095 : /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10096 : in MODE. Return an equivalent form, if different from (and VAROP
10097 : (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10098 :
10099 : static rtx
10100 12349217 : simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10101 : unsigned HOST_WIDE_INT constop)
10102 : {
10103 12349217 : unsigned HOST_WIDE_INT nonzero;
10104 12349217 : unsigned HOST_WIDE_INT orig_constop;
10105 12349217 : rtx orig_varop;
10106 12349217 : int i;
10107 :
10108 12349217 : orig_varop = varop;
10109 12349217 : orig_constop = constop;
10110 12349217 : if (GET_CODE (varop) == CLOBBER)
10111 : return NULL_RTX;
10112 :
10113 : /* Simplify VAROP knowing that we will be only looking at some of the
10114 : bits in it.
10115 :
10116 : Note by passing in CONSTOP, we guarantee that the bits not set in
10117 : CONSTOP are not significant and will never be examined. We must
10118 : ensure that is the case by explicitly masking out those bits
10119 : before returning. */
10120 12349202 : varop = force_to_mode (varop, mode, constop, false);
10121 :
10122 : /* If VAROP is a CLOBBER, we will fail so return it. */
10123 12349202 : if (GET_CODE (varop) == CLOBBER)
10124 : return varop;
10125 :
10126 : /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10127 : to VAROP and return the new constant. */
10128 12349156 : if (CONST_INT_P (varop))
10129 304140 : return gen_int_mode (INTVAL (varop) & constop, mode);
10130 :
10131 : /* See what bits may be nonzero in VAROP. Unlike the general case of
10132 : a call to nonzero_bits, here we don't care about bits outside
10133 : MODE unless WORD_REGISTER_OPERATIONS is true. */
10134 :
10135 12045016 : scalar_int_mode tmode = mode;
10136 12045016 : if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10137 : tmode = word_mode;
10138 12045016 : nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10139 :
10140 : /* Turn off all bits in the constant that are known to already be zero.
10141 : Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10142 : which is tested below. */
10143 :
10144 12045016 : constop &= nonzero;
10145 :
10146 : /* If we don't have any bits left, return zero. */
10147 12045016 : if (constop == 0 && !side_effects_p (varop))
10148 0 : return const0_rtx;
10149 :
10150 : /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10151 : a power of two, we can replace this with an ASHIFT. */
10152 36337 : if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10153 12052333 : && (i = exact_log2 (constop)) >= 0)
10154 163 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10155 :
10156 : /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10157 : or XOR, then try to apply the distributive law. This may eliminate
10158 : operations if either branch can be simplified because of the AND.
10159 : It may also make some cases more complex, but those cases probably
10160 : won't match a pattern either with or without this. */
10161 :
10162 12044853 : if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10163 : {
10164 82585 : scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10165 82585 : return
10166 82585 : gen_lowpart
10167 82585 : (mode,
10168 : apply_distributive_law
10169 82585 : (simplify_gen_binary (GET_CODE (varop), varop_mode,
10170 : simplify_and_const_int (NULL_RTX, varop_mode,
10171 : XEXP (varop, 0),
10172 : constop),
10173 : simplify_and_const_int (NULL_RTX, varop_mode,
10174 : XEXP (varop, 1),
10175 : constop))));
10176 : }
10177 :
10178 : /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10179 : the AND and see if one of the operands simplifies to zero. If so, we
10180 : may eliminate it. */
10181 :
10182 11962268 : if (GET_CODE (varop) == PLUS
10183 11962268 : && pow2p_hwi (constop + 1))
10184 : {
10185 434164 : rtx o0, o1;
10186 :
10187 434164 : o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10188 434164 : o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10189 434164 : if (o0 == const0_rtx)
10190 : return o1;
10191 434164 : if (o1 == const0_rtx)
10192 : return o0;
10193 : }
10194 :
10195 : /* Make a SUBREG if necessary. If we can't make it, fail. */
10196 11962193 : varop = gen_lowpart (mode, varop);
10197 11962193 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10198 : return NULL_RTX;
10199 :
10200 : /* If we are only masking insignificant bits, return VAROP. */
10201 11962193 : if (constop == nonzero)
10202 : return varop;
10203 :
10204 11517429 : if (varop == orig_varop && constop == orig_constop)
10205 : return NULL_RTX;
10206 :
10207 : /* Otherwise, return an AND. */
10208 6245121 : return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10209 : }
10210 :
10211 :
10212 : /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10213 : in MODE.
10214 :
10215 : Return an equivalent form, if different from X. Otherwise, return X. If
10216 : X is zero, we are to always construct the equivalent form. */
10217 :
10218 : static rtx
10219 12349217 : simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10220 : unsigned HOST_WIDE_INT constop)
10221 : {
10222 12349217 : rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10223 12349217 : if (tem)
10224 : return tem;
10225 :
10226 5272323 : if (!x)
10227 1328008 : x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10228 1328008 : gen_int_mode (constop, mode));
10229 5272323 : if (GET_MODE (x) != mode)
10230 2 : x = gen_lowpart (mode, x);
10231 : return x;
10232 : }
10233 :
10234 : /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10235 : We don't care about bits outside of those defined in MODE.
10236 : We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10237 :
10238 : For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10239 : a shift, AND, or zero_extract, we can do better. */
10240 :
10241 : static rtx
10242 455312916 : reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10243 : scalar_int_mode mode,
10244 : unsigned HOST_WIDE_INT *nonzero)
10245 : {
10246 455312916 : rtx tem;
10247 455312916 : reg_stat_type *rsp;
10248 :
10249 : /* If X is a register whose nonzero bits value is current, use it.
10250 : Otherwise, if X is a register whose value we can find, use that
10251 : value. Otherwise, use the previously-computed global nonzero bits
10252 : for this register. */
10253 :
10254 455312916 : rsp = ®_stat[REGNO (x)];
10255 455312916 : if (rsp->last_set_value != 0
10256 420040759 : && (rsp->last_set_mode == mode
10257 1278 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10258 0 : && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10259 0 : && GET_MODE_CLASS (mode) == MODE_INT))
10260 875352397 : && ((rsp->last_set_label >= label_tick_ebb_start
10261 318687575 : && rsp->last_set_label < label_tick)
10262 397189530 : || (rsp->last_set_label == label_tick
10263 295837624 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10264 129609189 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10265 129556204 : && REGNO (x) < reg_n_sets_max
10266 129556074 : && REG_N_SETS (REGNO (x)) == 1
10267 149650760 : && !REGNO_REG_SET_P
10268 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10269 : REGNO (x)))))
10270 : {
10271 : /* Note that, even if the precision of last_set_mode is lower than that
10272 : of mode, record_value_for_reg invoked nonzero_bits on the register
10273 : with nonzero_bits_mode (because last_set_mode is necessarily integral
10274 : and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10275 : are all valid, hence in mode too since nonzero_bits_mode is defined
10276 : to the largest HWI_COMPUTABLE_MODE_P mode. */
10277 365161048 : *nonzero &= rsp->last_set_nonzero_bits;
10278 365161048 : return NULL;
10279 : }
10280 :
10281 90151868 : tem = get_last_value (x);
10282 90151868 : if (tem)
10283 : {
10284 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
10285 : tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10286 :
10287 : return tem;
10288 : }
10289 :
10290 90151862 : if (nonzero_sign_valid && rsp->nonzero_bits)
10291 : {
10292 56628557 : unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10293 :
10294 56628557 : if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10295 : /* We don't know anything about the upper bits. */
10296 0 : mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10297 :
10298 56628557 : *nonzero &= mask;
10299 : }
10300 :
10301 : return NULL;
10302 : }
10303 :
10304 : /* Given a reg X of mode XMODE, return the number of bits at the high-order
10305 : end of X that are known to be equal to the sign bit. X will be used
10306 : in mode MODE; the returned value will always be between 1 and the
10307 : number of bits in MODE. */
10308 :
10309 : static rtx
10310 132870290 : reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10311 : scalar_int_mode mode,
10312 : unsigned int *result)
10313 : {
10314 132870290 : rtx tem;
10315 132870290 : reg_stat_type *rsp;
10316 :
10317 132870290 : rsp = ®_stat[REGNO (x)];
10318 132870290 : if (rsp->last_set_value != 0
10319 120612153 : && rsp->last_set_mode == mode
10320 253482274 : && ((rsp->last_set_label >= label_tick_ebb_start
10321 91390055 : && rsp->last_set_label < label_tick)
10322 114486875 : || (rsp->last_set_label == label_tick
10323 85264946 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10324 36976381 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10325 36966505 : && REGNO (x) < reg_n_sets_max
10326 36966419 : && REG_N_SETS (REGNO (x)) == 1
10327 42774160 : && !REGNO_REG_SET_P
10328 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10329 : REGNO (x)))))
10330 : {
10331 104998318 : *result = rsp->last_set_sign_bit_copies;
10332 104998318 : return NULL;
10333 : }
10334 :
10335 27871972 : tem = get_last_value (x);
10336 27871972 : if (tem != 0)
10337 : return tem;
10338 :
10339 18449564 : if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10340 42235027 : && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10341 14363060 : *result = rsp->sign_bit_copies;
10342 :
10343 : return NULL;
10344 : }
10345 :
10346 : /* Return the number of "extended" bits there are in X, when interpreted
10347 : as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10348 : unsigned quantities, this is the number of high-order zero bits.
10349 : For signed quantities, this is the number of copies of the sign bit
10350 : minus 1. In both case, this function returns the number of "spare"
10351 : bits. For example, if two quantities for which this function returns
10352 : at least 1 are added, the addition is known not to overflow.
10353 :
10354 : This function will always return 0 unless called during combine, which
10355 : implies that it must be called from a define_split. */
10356 :
10357 : unsigned int
10358 0 : extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10359 : {
10360 0 : if (nonzero_sign_valid == 0)
10361 : return 0;
10362 :
10363 0 : scalar_int_mode int_mode;
10364 0 : return (unsignedp
10365 0 : ? (is_a <scalar_int_mode> (mode, &int_mode)
10366 0 : && HWI_COMPUTABLE_MODE_P (int_mode)
10367 0 : ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10368 0 : - floor_log2 (nonzero_bits (x, int_mode)))
10369 : : 0)
10370 0 : : num_sign_bit_copies (x, mode) - 1);
10371 : }
10372 :
10373 : /* This function is called from `simplify_shift_const' to merge two
10374 : outer operations. Specifically, we have already found that we need
10375 : to perform operation *POP0 with constant *PCONST0 at the outermost
10376 : position. We would now like to also perform OP1 with constant CONST1
10377 : (with *POP0 being done last).
10378 :
10379 : Return true if we can do the operation and update *POP0 and *PCONST0 with
10380 : the resulting operation. *PCOMP_P is set to true if we would need to
10381 : complement the innermost operand, otherwise it is unchanged.
10382 :
10383 : MODE is the mode in which the operation will be done. No bits outside
10384 : the width of this mode matter. It is assumed that the width of this mode
10385 : is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10386 :
10387 : If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10388 : IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10389 : result is simply *PCONST0.
10390 :
10391 : If the resulting operation cannot be expressed as one operation, we
10392 : return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10393 :
10394 : static bool
10395 3775680 : merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10396 : enum rtx_code op1, HOST_WIDE_INT const1,
10397 : machine_mode mode, bool *pcomp_p)
10398 : {
10399 3775680 : enum rtx_code op0 = *pop0;
10400 3775680 : HOST_WIDE_INT const0 = *pconst0;
10401 :
10402 3775680 : const0 &= GET_MODE_MASK (mode);
10403 3775680 : const1 &= GET_MODE_MASK (mode);
10404 :
10405 : /* If OP0 is an AND, clear unimportant bits in CONST1. */
10406 3775680 : if (op0 == AND)
10407 9696 : const1 &= const0;
10408 :
10409 : /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10410 : if OP0 is SET. */
10411 :
10412 3775680 : if (op1 == UNKNOWN || op0 == SET)
10413 : return true;
10414 :
10415 3775680 : else if (op0 == UNKNOWN)
10416 : op0 = op1, const0 = const1;
10417 :
10418 61540 : else if (op0 == op1)
10419 : {
10420 9413 : switch (op0)
10421 : {
10422 9408 : case AND:
10423 9408 : const0 &= const1;
10424 9408 : break;
10425 5 : case IOR:
10426 5 : const0 |= const1;
10427 5 : break;
10428 0 : case XOR:
10429 0 : const0 ^= const1;
10430 0 : break;
10431 0 : case PLUS:
10432 0 : const0 += const1;
10433 0 : break;
10434 : case NEG:
10435 3747398 : op0 = UNKNOWN;
10436 : break;
10437 : default:
10438 : break;
10439 : }
10440 : }
10441 :
10442 : /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10443 52127 : else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10444 : return false;
10445 :
10446 : /* If the two constants aren't the same, we can't do anything. The
10447 : remaining six cases can all be done. */
10448 25192 : else if (const0 != const1)
10449 : return false;
10450 :
10451 : else
10452 23845 : switch (op0)
10453 : {
10454 8 : case IOR:
10455 8 : if (op1 == AND)
10456 : /* (a & b) | b == b */
10457 0 : op0 = SET;
10458 : else /* op1 == XOR */
10459 : /* (a ^ b) | b == a | b */
10460 : {;}
10461 : break;
10462 :
10463 23553 : case XOR:
10464 23553 : if (op1 == AND)
10465 : /* (a & b) ^ b == (~a) & b */
10466 23553 : op0 = AND, *pcomp_p = true;
10467 : else /* op1 == IOR */
10468 : /* (a | b) ^ b == a & ~b */
10469 0 : op0 = AND, const0 = ~const0;
10470 : break;
10471 :
10472 284 : case AND:
10473 284 : if (op1 == IOR)
10474 : /* (a | b) & b == b */
10475 : op0 = SET;
10476 : else /* op1 == XOR */
10477 : /* (a ^ b) & b) == (~a) & b */
10478 284 : *pcomp_p = true;
10479 : break;
10480 : default:
10481 : break;
10482 : }
10483 :
10484 : /* Check for NO-OP cases. */
10485 3747398 : const0 &= GET_MODE_MASK (mode);
10486 3747398 : if (const0 == 0
10487 19924 : && (op0 == IOR || op0 == XOR || op0 == PLUS))
10488 : op0 = UNKNOWN;
10489 3745890 : else if (const0 == 0 && op0 == AND)
10490 : op0 = SET;
10491 3745890 : else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10492 24472 : && op0 == AND)
10493 3747398 : op0 = UNKNOWN;
10494 :
10495 3747398 : *pop0 = op0;
10496 :
10497 : /* ??? Slightly redundant with the above mask, but not entirely.
10498 : Moving this above means we'd have to sign-extend the mode mask
10499 : for the final test. */
10500 3747398 : if (op0 != UNKNOWN && op0 != NEG)
10501 3711064 : *pconst0 = trunc_int_for_mode (const0, mode);
10502 :
10503 : return true;
10504 : }
10505 :
10506 : /* A helper to simplify_shift_const_1 to determine the mode we can perform
10507 : the shift in. The original shift operation CODE is performed on OP in
10508 : ORIG_MODE. Return the wider mode MODE if we can perform the operation
10509 : in that mode. Return ORIG_MODE otherwise. We can also assume that the
10510 : result of the shift is subject to operation OUTER_CODE with operand
10511 : OUTER_CONST. */
10512 :
10513 : static scalar_int_mode
10514 404102 : try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10515 : scalar_int_mode orig_mode, scalar_int_mode mode,
10516 : enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10517 : {
10518 404102 : gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10519 :
10520 : /* In general we can't perform in wider mode for right shift and rotate. */
10521 404102 : switch (code)
10522 : {
10523 34262 : case ASHIFTRT:
10524 : /* We can still widen if the bits brought in from the left are identical
10525 : to the sign bit of ORIG_MODE. */
10526 34262 : if (num_sign_bit_copies (op, mode)
10527 34262 : > (unsigned) (GET_MODE_PRECISION (mode)
10528 34262 : - GET_MODE_PRECISION (orig_mode)))
10529 344 : return mode;
10530 33918 : return orig_mode;
10531 :
10532 72700 : case LSHIFTRT:
10533 : /* Similarly here but with zero bits. */
10534 72700 : if (HWI_COMPUTABLE_MODE_P (mode)
10535 72700 : && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10536 6105 : return mode;
10537 :
10538 : /* We can also widen if the bits brought in will be masked off. This
10539 : operation is performed in ORIG_MODE. */
10540 66595 : if (outer_code == AND)
10541 : {
10542 26105 : int care_bits = low_bitmask_len (orig_mode, outer_const);
10543 :
10544 26105 : if (care_bits >= 0
10545 26105 : && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10546 26087 : return mode;
10547 : }
10548 : /* fall through */
10549 :
10550 40994 : case ROTATE:
10551 40994 : return orig_mode;
10552 :
10553 0 : case ROTATERT:
10554 0 : gcc_unreachable ();
10555 :
10556 296654 : default:
10557 296654 : return mode;
10558 : }
10559 : }
10560 :
10561 : /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10562 : of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10563 : if we cannot simplify it. Otherwise, return a simplified value.
10564 :
10565 : The shift is normally computed in the widest mode we find in VAROP, as
10566 : long as it isn't a different number of words than RESULT_MODE. Exceptions
10567 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
10568 :
10569 : static rtx
10570 24126691 : simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10571 : rtx varop, int orig_count)
10572 : {
10573 24126691 : enum rtx_code orig_code = code;
10574 24126691 : rtx orig_varop = varop;
10575 24126691 : int count, log2;
10576 24126691 : machine_mode mode = result_mode;
10577 24126691 : machine_mode shift_mode;
10578 24126691 : scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10579 : /* We form (outer_op (code varop count) (outer_const)). */
10580 24126691 : enum rtx_code outer_op = UNKNOWN;
10581 24126691 : HOST_WIDE_INT outer_const = 0;
10582 24126691 : bool complement_p = false;
10583 24126691 : rtx new_rtx, x;
10584 :
10585 : /* Make sure and truncate the "natural" shift on the way in. We don't
10586 : want to do this inside the loop as it makes it more difficult to
10587 : combine shifts. */
10588 24126691 : if (SHIFT_COUNT_TRUNCATED)
10589 : orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10590 :
10591 : /* If we were given an invalid count, don't do anything except exactly
10592 : what was requested. */
10593 :
10594 48253322 : if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10595 : return NULL_RTX;
10596 :
10597 : count = orig_count;
10598 :
10599 : /* Unless one of the branches of the `if' in this loop does a `continue',
10600 : we will `break' the loop after the `if'. */
10601 :
10602 28242568 : while (count != 0)
10603 : {
10604 : /* If we have an operand of (clobber (const_int 0)), fail. */
10605 24316743 : if (GET_CODE (varop) == CLOBBER)
10606 24126691 : return NULL_RTX;
10607 :
10608 : /* Convert ROTATERT to ROTATE. */
10609 24316743 : if (code == ROTATERT)
10610 : {
10611 11683 : unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10612 11683 : code = ROTATE;
10613 11683 : count = bitsize - count;
10614 : }
10615 :
10616 24316743 : shift_mode = result_mode;
10617 24316743 : if (shift_mode != mode)
10618 : {
10619 : /* We only change the modes of scalar shifts. */
10620 207916 : int_mode = as_a <scalar_int_mode> (mode);
10621 207916 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10622 207916 : shift_mode = try_widen_shift_mode (code, varop, count,
10623 : int_result_mode, int_mode,
10624 : outer_op, outer_const);
10625 : }
10626 :
10627 24316743 : scalar_int_mode shift_unit_mode;
10628 48633486 : if (!is_a <scalar_int_mode> (GET_MODE_INNER (shift_mode),
10629 : &shift_unit_mode))
10630 : return NULL_RTX;
10631 :
10632 : /* Handle cases where the count is greater than the size of the mode
10633 : minus 1. For ASHIFT, use the size minus one as the count (this can
10634 : occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10635 : take the count modulo the size. For other shifts, the result is
10636 : zero.
10637 :
10638 : Since these shifts are being produced by the compiler by combining
10639 : multiple operations, each of which are defined, we know what the
10640 : result is supposed to be. */
10641 :
10642 24316743 : if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10643 : {
10644 12925 : if (code == ASHIFTRT)
10645 12919 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10646 6 : else if (code == ROTATE || code == ROTATERT)
10647 6 : count %= GET_MODE_PRECISION (shift_unit_mode);
10648 : else
10649 : {
10650 : /* We can't simply return zero because there may be an
10651 : outer op. */
10652 0 : varop = const0_rtx;
10653 0 : count = 0;
10654 0 : break;
10655 : }
10656 : }
10657 :
10658 : /* If we discovered we had to complement VAROP, leave. Making a NOT
10659 : here would cause an infinite loop. */
10660 24316743 : if (complement_p)
10661 : break;
10662 :
10663 24303817 : if (shift_mode == shift_unit_mode)
10664 : {
10665 : /* An arithmetic right shift of a quantity known to be -1 or 0
10666 : is a no-op. */
10667 23644682 : if (code == ASHIFTRT
10668 23644682 : && (num_sign_bit_copies (varop, shift_unit_mode)
10669 4421880 : == GET_MODE_PRECISION (shift_unit_mode)))
10670 : {
10671 : count = 0;
10672 : break;
10673 : }
10674 :
10675 : /* If we are doing an arithmetic right shift and discarding all but
10676 : the sign bit copies, this is equivalent to doing a shift by the
10677 : bitsize minus one. Convert it into that shift because it will
10678 : often allow other simplifications. */
10679 :
10680 23644612 : if (code == ASHIFTRT
10681 23644612 : && (count + num_sign_bit_copies (varop, shift_unit_mode)
10682 4421810 : >= GET_MODE_PRECISION (shift_unit_mode)))
10683 337268 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10684 :
10685 : /* We simplify the tests below and elsewhere by converting
10686 : ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10687 : `make_compound_operation' will convert it to an ASHIFTRT for
10688 : those machines (such as VAX) that don't have an LSHIFTRT. */
10689 23644612 : if (code == ASHIFTRT
10690 4421810 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10691 28041187 : && val_signbit_known_clear_p (shift_unit_mode,
10692 : nonzero_bits (varop,
10693 : shift_unit_mode)))
10694 : code = LSHIFTRT;
10695 :
10696 23615308 : if (((code == LSHIFTRT
10697 5905982 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10698 5884132 : && !(nonzero_bits (varop, shift_unit_mode) >> count))
10699 23642666 : || (code == ASHIFT
10700 13317214 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10701 12851048 : && !((nonzero_bits (varop, shift_unit_mode) << count)
10702 12851048 : & GET_MODE_MASK (shift_unit_mode))))
10703 23619385 : && !side_effects_p (varop))
10704 4077 : varop = const0_rtx;
10705 : }
10706 :
10707 24303747 : switch (GET_CODE (varop))
10708 : {
10709 503183 : case SIGN_EXTEND:
10710 503183 : case ZERO_EXTEND:
10711 503183 : case SIGN_EXTRACT:
10712 503183 : case ZERO_EXTRACT:
10713 503183 : new_rtx = expand_compound_operation (varop);
10714 503183 : if (new_rtx != varop)
10715 : {
10716 68309 : varop = new_rtx;
10717 4116149 : continue;
10718 : }
10719 : break;
10720 :
10721 329228 : case MEM:
10722 : /* The following rules apply only to scalars. */
10723 329228 : if (shift_mode != shift_unit_mode)
10724 : break;
10725 314014 : int_mode = as_a <scalar_int_mode> (mode);
10726 :
10727 : /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10728 : minus the width of a smaller mode, we can do this with a
10729 : SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10730 317780 : if ((code == ASHIFTRT || code == LSHIFTRT)
10731 119557 : && ! mode_dependent_address_p (XEXP (varop, 0),
10732 119557 : MEM_ADDR_SPACE (varop))
10733 119557 : && ! MEM_VOLATILE_P (varop)
10734 432064 : && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10735 310248 : .exists (&tmode)))
10736 : {
10737 3766 : new_rtx = adjust_address_nv (varop, tmode,
10738 : BYTES_BIG_ENDIAN ? 0
10739 : : count / BITS_PER_UNIT);
10740 :
10741 3766 : varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10742 : : ZERO_EXTEND, int_mode, new_rtx);
10743 3766 : count = 0;
10744 3766 : continue;
10745 : }
10746 : break;
10747 :
10748 5044416 : case SUBREG:
10749 : /* The following rules apply only to scalars. */
10750 5044416 : if (shift_mode != shift_unit_mode)
10751 : break;
10752 4585122 : int_mode = as_a <scalar_int_mode> (mode);
10753 4585122 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10754 :
10755 : /* If VAROP is a SUBREG, strip it as long as the inner operand has
10756 : the same number of words as what we've seen so far. Then store
10757 : the widest mode in MODE. */
10758 4585122 : if (subreg_lowpart_p (varop)
10759 28669856 : && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10760 9086874 : && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10761 227893 : && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10762 209755 : == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10763 4781882 : && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10764 : {
10765 196760 : varop = SUBREG_REG (varop);
10766 590280 : if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10767 196760 : mode = inner_mode;
10768 196760 : continue;
10769 : }
10770 : break;
10771 :
10772 406771 : case MULT:
10773 : /* Some machines use MULT instead of ASHIFT because MULT
10774 : is cheaper. But it is still better on those machines to
10775 : merge two shifts into one. */
10776 406771 : if (CONST_INT_P (XEXP (varop, 1))
10777 406771 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10778 : {
10779 0 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10780 0 : varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10781 : XEXP (varop, 0), log2_rtx);
10782 0 : continue;
10783 0 : }
10784 : break;
10785 :
10786 8819 : case UDIV:
10787 : /* Similar, for when divides are cheaper. */
10788 8819 : if (CONST_INT_P (XEXP (varop, 1))
10789 8819 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10790 : {
10791 9 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10792 9 : varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10793 : XEXP (varop, 0), log2_rtx);
10794 9 : continue;
10795 9 : }
10796 : break;
10797 :
10798 378688 : case ASHIFTRT:
10799 : /* If we are extracting just the sign bit of an arithmetic
10800 : right shift, that shift is not needed. However, the sign
10801 : bit of a wider mode may be different from what would be
10802 : interpreted as the sign bit in a narrower mode, so, if
10803 : the result is narrower, don't discard the shift. */
10804 380584 : if (code == LSHIFTRT
10805 14962 : && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10806 378688 : && (GET_MODE_UNIT_BITSIZE (result_mode)
10807 3818 : >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10808 : {
10809 1896 : varop = XEXP (varop, 0);
10810 1896 : continue;
10811 : }
10812 :
10813 : /* fall through */
10814 :
10815 5969765 : case LSHIFTRT:
10816 5969765 : case ASHIFT:
10817 5969765 : case ROTATE:
10818 : /* The following rules apply only to scalars. */
10819 5969765 : if (shift_mode != shift_unit_mode)
10820 : break;
10821 5961933 : int_mode = as_a <scalar_int_mode> (mode);
10822 5961933 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10823 5961933 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10824 :
10825 : /* Here we have two nested shifts. The result is usually the
10826 : AND of a new shift with a mask. We compute the result below. */
10827 5961933 : if (CONST_INT_P (XEXP (varop, 1))
10828 5941966 : && INTVAL (XEXP (varop, 1)) >= 0
10829 5941963 : && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10830 5941963 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
10831 11870683 : && HWI_COMPUTABLE_MODE_P (int_mode))
10832 : {
10833 5908750 : enum rtx_code first_code = GET_CODE (varop);
10834 5908750 : unsigned int first_count = INTVAL (XEXP (varop, 1));
10835 5908750 : unsigned HOST_WIDE_INT mask;
10836 5908750 : rtx mask_rtx;
10837 :
10838 : /* We have one common special case. We can't do any merging if
10839 : the inner code is an ASHIFTRT of a smaller mode. However, if
10840 : we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10841 : with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10842 : we can convert it to
10843 : (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10844 : This simplifies certain SIGN_EXTEND operations. */
10845 5908750 : if (code == ASHIFT && first_code == ASHIFTRT
10846 5908750 : && count == (GET_MODE_PRECISION (int_result_mode)
10847 339754 : - GET_MODE_PRECISION (int_varop_mode)))
10848 : {
10849 : /* C3 has the low-order C1 bits zero. */
10850 :
10851 0 : mask = GET_MODE_MASK (int_mode)
10852 0 : & ~((HOST_WIDE_INT_1U << first_count) - 1);
10853 :
10854 0 : varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10855 : XEXP (varop, 0), mask);
10856 0 : varop = simplify_shift_const (NULL_RTX, ASHIFT,
10857 : int_result_mode, varop, count);
10858 0 : count = first_count;
10859 0 : code = ASHIFTRT;
10860 0 : continue;
10861 : }
10862 :
10863 : /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10864 : than C1 high-order bits equal to the sign bit, we can convert
10865 : this to either an ASHIFT or an ASHIFTRT depending on the
10866 : two counts.
10867 :
10868 : We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10869 :
10870 5910237 : if (code == ASHIFTRT && first_code == ASHIFT
10871 2893452 : && int_varop_mode == shift_unit_mode
10872 8795402 : && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10873 : > first_count))
10874 : {
10875 1487 : varop = XEXP (varop, 0);
10876 1487 : count -= first_count;
10877 1487 : if (count < 0)
10878 : {
10879 4 : count = -count;
10880 4 : code = ASHIFT;
10881 : }
10882 :
10883 1487 : continue;
10884 : }
10885 :
10886 : /* There are some cases we can't do. If CODE is ASHIFTRT,
10887 : we can only do this if FIRST_CODE is also ASHIFTRT.
10888 :
10889 : We can't do the case when CODE is ROTATE and FIRST_CODE is
10890 : ASHIFTRT.
10891 :
10892 : If the mode of this shift is not the mode of the outer shift,
10893 : we can't do this if either shift is a right shift or ROTATE.
10894 :
10895 : Finally, we can't do any of these if the mode is too wide
10896 : unless the codes are the same.
10897 :
10898 : Handle the case where the shift codes are the same
10899 : first. */
10900 :
10901 5907263 : if (code == first_code)
10902 : {
10903 31084 : if (int_varop_mode != int_result_mode
10904 31084 : && (code == ASHIFTRT || code == LSHIFTRT
10905 653 : || code == ROTATE))
10906 : break;
10907 :
10908 30459 : count += first_count;
10909 30459 : varop = XEXP (varop, 0);
10910 30459 : continue;
10911 : }
10912 :
10913 5876179 : if (code == ASHIFTRT
10914 2984178 : || (code == ROTATE && first_code == ASHIFTRT)
10915 2984148 : || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10916 8860327 : || (int_varop_mode != int_result_mode
10917 78870 : && (first_code == ASHIFTRT || first_code == LSHIFTRT
10918 78870 : || first_code == ROTATE
10919 25464 : || code == ROTATE)))
10920 : break;
10921 :
10922 : /* To compute the mask to apply after the shift, shift the
10923 : nonzero bits of the inner shift the same way the
10924 : outer shift will. */
10925 :
10926 2930742 : mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10927 : int_result_mode);
10928 2930742 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10929 2930742 : mask_rtx
10930 2930742 : = simplify_const_binary_operation (code, int_result_mode,
10931 : mask_rtx, count_rtx);
10932 :
10933 : /* Give up if we can't compute an outer operation to use. */
10934 2930742 : if (mask_rtx == 0
10935 2930742 : || !CONST_INT_P (mask_rtx)
10936 5861484 : || ! merge_outer_ops (&outer_op, &outer_const, AND,
10937 : INTVAL (mask_rtx),
10938 : int_result_mode, &complement_p))
10939 : break;
10940 :
10941 : /* If the shifts are in the same direction, we add the
10942 : counts. Otherwise, we subtract them. */
10943 2903920 : if ((code == ASHIFTRT || code == LSHIFTRT)
10944 2903920 : == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10945 11418 : count += first_count;
10946 : else
10947 2892502 : count -= first_count;
10948 :
10949 : /* If COUNT is positive, the new shift is usually CODE,
10950 : except for the two exceptions below, in which case it is
10951 : FIRST_CODE. If the count is negative, FIRST_CODE should
10952 : always be used */
10953 2903920 : if (count > 0
10954 667229 : && ((first_code == ROTATE && code == ASHIFT)
10955 666723 : || (first_code == ASHIFTRT && code == LSHIFTRT)))
10956 : code = first_code;
10957 2892508 : else if (count < 0)
10958 317422 : code = first_code, count = -count;
10959 :
10960 2903920 : varop = XEXP (varop, 0);
10961 2903920 : continue;
10962 2903920 : }
10963 :
10964 : /* If we have (A << B << C) for any shift, we can convert this to
10965 : (A << C << B). This wins if A is a constant. Only try this if
10966 : B is not a constant. */
10967 :
10968 53183 : else if (GET_CODE (varop) == code
10969 5180 : && CONST_INT_P (XEXP (varop, 0))
10970 1021 : && !CONST_INT_P (XEXP (varop, 1)))
10971 : {
10972 : /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10973 : sure the result will be masked. See PR70222. */
10974 1021 : if (code == LSHIFTRT
10975 7 : && int_mode != int_result_mode
10976 1028 : && !merge_outer_ops (&outer_op, &outer_const, AND,
10977 7 : GET_MODE_MASK (int_result_mode)
10978 7 : >> orig_count, int_result_mode,
10979 : &complement_p))
10980 : break;
10981 : /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10982 : up outer sign extension (often left and right shift) is
10983 : hardly more efficient than the original. See PR70429.
10984 : Similarly punt for rotates with different modes.
10985 : See PR97386. */
10986 1021 : if ((code == ASHIFTRT || code == ROTATE)
10987 1021 : && int_mode != int_result_mode)
10988 : break;
10989 :
10990 1007 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10991 1007 : rtx new_rtx = simplify_const_binary_operation (code, int_mode,
10992 : XEXP (varop, 0),
10993 : count_rtx);
10994 1007 : varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
10995 1007 : count = 0;
10996 1007 : continue;
10997 1007 : }
10998 : break;
10999 :
11000 60040 : case NOT:
11001 : /* The following rules apply only to scalars. */
11002 60040 : if (shift_mode != shift_unit_mode)
11003 : break;
11004 :
11005 : /* Make this fit the case below. */
11006 59978 : varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11007 59978 : continue;
11008 :
11009 804991 : case IOR:
11010 804991 : case AND:
11011 804991 : case XOR:
11012 : /* The following rules apply only to scalars. */
11013 804991 : if (shift_mode != shift_unit_mode)
11014 : break;
11015 803190 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11016 803190 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11017 :
11018 : /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11019 : with C the size of VAROP - 1 and the shift is logical if
11020 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11021 : we have an (le X 0) operation. If we have an arithmetic shift
11022 : and STORE_FLAG_VALUE is 1 or we have a logical shift with
11023 : STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11024 :
11025 269130 : if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11026 1556 : && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11027 : && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11028 113 : && (code == LSHIFTRT || code == ASHIFTRT)
11029 113 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11030 803303 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11031 : {
11032 53 : count = 0;
11033 53 : varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11034 : const0_rtx);
11035 :
11036 53 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11037 53 : varop = gen_rtx_NEG (int_varop_mode, varop);
11038 :
11039 53 : continue;
11040 : }
11041 :
11042 : /* If we have (shift (logical)), move the logical to the outside
11043 : to allow it to possibly combine with another logical and the
11044 : shift to combine with another shift. This also canonicalizes to
11045 : what a ZERO_EXTRACT looks like. Also, some machines have
11046 : (and (shift)) insns. */
11047 :
11048 1242337 : if (CONST_INT_P (XEXP (varop, 1))
11049 : /* We can't do this if we have (ashiftrt (xor)) and the
11050 : constant has its sign bit set in shift_unit_mode with
11051 : shift_unit_mode wider than result_mode. */
11052 440485 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11053 8266 : && int_result_mode != shift_unit_mode
11054 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11055 : shift_unit_mode) < 0)
11056 440485 : && (new_rtx = simplify_const_binary_operation
11057 440485 : (code, int_result_mode,
11058 440485 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11059 440485 : gen_int_shift_amount (int_result_mode, count))) != 0
11060 440485 : && CONST_INT_P (new_rtx)
11061 1243622 : && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11062 : INTVAL (new_rtx), int_result_mode,
11063 : &complement_p))
11064 : {
11065 439200 : varop = XEXP (varop, 0);
11066 439200 : continue;
11067 : }
11068 :
11069 : /* If we can't do that, try to simplify the shift in each arm of the
11070 : logical expression, make a new logical expression, and apply
11071 : the inverse distributive law. This also can't be done for
11072 : (ashiftrt (xor)) where we've widened the shift and the constant
11073 : changes the sign bit. */
11074 363937 : if (CONST_INT_P (XEXP (varop, 1))
11075 363937 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11076 48 : && int_result_mode != shift_unit_mode
11077 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11078 : shift_unit_mode) < 0))
11079 : {
11080 1285 : rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11081 : XEXP (varop, 0), count);
11082 1285 : rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11083 : XEXP (varop, 1), count);
11084 :
11085 1285 : varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11086 : lhs, rhs);
11087 1285 : varop = apply_distributive_law (varop);
11088 :
11089 1285 : count = 0;
11090 1285 : continue;
11091 1285 : }
11092 : break;
11093 :
11094 32520 : case EQ:
11095 : /* The following rules apply only to scalars. */
11096 32520 : if (shift_mode != shift_unit_mode)
11097 : break;
11098 32520 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11099 :
11100 : /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11101 : says that the sign bit can be tested, FOO has mode MODE, C is
11102 : GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11103 : that may be nonzero. */
11104 32520 : if (code == LSHIFTRT
11105 0 : && XEXP (varop, 1) == const0_rtx
11106 0 : && GET_MODE (XEXP (varop, 0)) == int_result_mode
11107 0 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11108 32520 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11109 : && STORE_FLAG_VALUE == -1
11110 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11111 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11112 : int_result_mode, &complement_p))
11113 : {
11114 : varop = XEXP (varop, 0);
11115 : count = 0;
11116 : continue;
11117 : }
11118 : break;
11119 :
11120 27705 : case NEG:
11121 : /* The following rules apply only to scalars. */
11122 27705 : if (shift_mode != shift_unit_mode)
11123 : break;
11124 27564 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11125 :
11126 : /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11127 : than the number of bits in the mode is equivalent to A. */
11128 27569 : if (code == LSHIFTRT
11129 5817 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11130 30106 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11131 : {
11132 5 : varop = XEXP (varop, 0);
11133 5 : count = 0;
11134 5 : continue;
11135 : }
11136 :
11137 : /* NEG commutes with ASHIFT since it is multiplication. Move the
11138 : NEG outside to allow shifts to combine. */
11139 45975 : if (code == ASHIFT
11140 27559 : && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11141 : int_result_mode, &complement_p))
11142 : {
11143 18416 : varop = XEXP (varop, 0);
11144 18416 : continue;
11145 : }
11146 : break;
11147 :
11148 1911467 : case PLUS:
11149 : /* The following rules apply only to scalars. */
11150 1911467 : if (shift_mode != shift_unit_mode)
11151 : break;
11152 1865535 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11153 :
11154 : /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11155 : is one less than the number of bits in the mode is
11156 : equivalent to (xor A 1). */
11157 1865535 : if (code == LSHIFTRT
11158 395471 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11159 31894 : && XEXP (varop, 1) == constm1_rtx
11160 14781 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11161 1865535 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11162 : int_result_mode, &complement_p))
11163 : {
11164 0 : count = 0;
11165 0 : varop = XEXP (varop, 0);
11166 0 : continue;
11167 : }
11168 :
11169 : /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11170 : that might be nonzero in BAR are those being shifted out and those
11171 : bits are known zero in FOO, we can replace the PLUS with FOO.
11172 : Similarly in the other operand order. This code occurs when
11173 : we are computing the size of a variable-size array. */
11174 :
11175 1868719 : if ((code == ASHIFTRT || code == LSHIFTRT)
11176 556377 : && count < HOST_BITS_PER_WIDE_INT
11177 555208 : && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11178 2041914 : && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11179 176379 : & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11180 : {
11181 3184 : varop = XEXP (varop, 0);
11182 3184 : continue;
11183 : }
11184 1862386 : else if ((code == ASHIFTRT || code == LSHIFTRT)
11185 553193 : && count < HOST_BITS_PER_WIDE_INT
11186 552024 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11187 550794 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11188 550794 : >> count) == 0
11189 1952459 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11190 90108 : & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11191 : {
11192 35 : varop = XEXP (varop, 1);
11193 35 : continue;
11194 : }
11195 :
11196 : /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11197 2240026 : if (code == ASHIFT
11198 1300467 : && CONST_INT_P (XEXP (varop, 1))
11199 377881 : && (new_rtx = simplify_const_binary_operation
11200 377881 : (ASHIFT, int_result_mode,
11201 377881 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11202 377881 : gen_int_shift_amount (int_result_mode, count))) != 0
11203 377881 : && CONST_INT_P (new_rtx)
11204 2240197 : && merge_outer_ops (&outer_op, &outer_const, PLUS,
11205 : INTVAL (new_rtx), int_result_mode,
11206 : &complement_p))
11207 : {
11208 377710 : varop = XEXP (varop, 0);
11209 377710 : continue;
11210 : }
11211 :
11212 : /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11213 : signbit', and attempt to change the PLUS to an XOR and move it to
11214 : the outer operation as is done above in the AND/IOR/XOR case
11215 : leg for shift(logical). See details in logical handling above
11216 : for reasoning in doing so. */
11217 1492751 : if (code == LSHIFTRT
11218 392342 : && CONST_INT_P (XEXP (varop, 1))
11219 284565 : && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11220 8145 : && (new_rtx = simplify_const_binary_operation
11221 1484606 : (code, int_result_mode,
11222 8145 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11223 8145 : gen_int_shift_amount (int_result_mode, count))) != 0
11224 8145 : && CONST_INT_P (new_rtx)
11225 1492751 : && merge_outer_ops (&outer_op, &outer_const, XOR,
11226 : INTVAL (new_rtx), int_result_mode,
11227 : &complement_p))
11228 : {
11229 8145 : varop = XEXP (varop, 0);
11230 8145 : continue;
11231 : }
11232 :
11233 : break;
11234 :
11235 623534 : case MINUS:
11236 : /* The following rules apply only to scalars. */
11237 623534 : if (shift_mode != shift_unit_mode)
11238 : break;
11239 610736 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11240 :
11241 : /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11242 : with C the size of VAROP - 1 and the shift is logical if
11243 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11244 : we have a (gt X 0) operation. If the shift is arithmetic with
11245 : STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11246 : we have a (neg (gt X 0)) operation. */
11247 :
11248 610736 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11249 610736 : && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11250 12329 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11251 48 : && (code == LSHIFTRT || code == ASHIFTRT)
11252 13 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11253 13 : && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11254 610736 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11255 : {
11256 0 : count = 0;
11257 0 : varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11258 : const0_rtx);
11259 :
11260 0 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11261 0 : varop = gen_rtx_NEG (int_varop_mode, varop);
11262 :
11263 0 : continue;
11264 : }
11265 : break;
11266 :
11267 683 : case TRUNCATE:
11268 : /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11269 : if the truncate does not affect the value. */
11270 683 : if (code == LSHIFTRT
11271 525 : && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11272 525 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11273 683 : && (INTVAL (XEXP (XEXP (varop, 0), 1))
11274 525 : >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11275 1050 : - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11276 : {
11277 525 : rtx varop_inner = XEXP (varop, 0);
11278 525 : int new_count = count + INTVAL (XEXP (varop_inner, 1));
11279 525 : rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11280 525 : new_count);
11281 525 : varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11282 : XEXP (varop_inner, 0),
11283 : new_count_rtx);
11284 525 : varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11285 525 : count = 0;
11286 525 : continue;
11287 525 : }
11288 : break;
11289 :
11290 : default:
11291 : break;
11292 59978 : }
11293 :
11294 : break;
11295 : }
11296 :
11297 24126419 : shift_mode = result_mode;
11298 24126419 : if (shift_mode != mode)
11299 : {
11300 : /* We only change the modes of scalar shifts. */
11301 196186 : int_mode = as_a <scalar_int_mode> (mode);
11302 196186 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11303 196186 : shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11304 : int_mode, outer_op, outer_const);
11305 : }
11306 :
11307 : /* We have now finished analyzing the shift. The result should be
11308 : a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11309 : OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11310 : to the result of the shift. OUTER_CONST is the relevant constant,
11311 : but we must turn off all bits turned off in the shift. */
11312 :
11313 24126419 : if (outer_op == UNKNOWN
11314 20430197 : && orig_code == code && orig_count == count
11315 20381004 : && varop == orig_varop
11316 20209487 : && shift_mode == GET_MODE (varop))
11317 : return NULL_RTX;
11318 :
11319 : /* Make a SUBREG if necessary. If we can't make it, fail. */
11320 3919456 : varop = gen_lowpart (shift_mode, varop);
11321 3919456 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11322 : return NULL_RTX;
11323 :
11324 : /* If we have an outer operation and we just made a shift, it is
11325 : possible that we could have simplified the shift were it not
11326 : for the outer operation. So try to do the simplification
11327 : recursively. */
11328 :
11329 3919456 : if (outer_op != UNKNOWN)
11330 3696222 : x = simplify_shift_const_1 (code, shift_mode, varop, count);
11331 : else
11332 : x = NULL_RTX;
11333 :
11334 3696222 : if (x == NULL_RTX)
11335 3883362 : x = simplify_gen_binary (code, shift_mode, varop,
11336 3883362 : gen_int_shift_amount (shift_mode, count));
11337 :
11338 : /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11339 : turn off all the bits that the shift would have turned off. */
11340 3919456 : if (orig_code == LSHIFTRT && result_mode != shift_mode)
11341 : /* We only change the modes of scalar shifts. */
11342 26283 : x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11343 26283 : x, GET_MODE_MASK (result_mode) >> orig_count);
11344 :
11345 : /* Do the remainder of the processing in RESULT_MODE. */
11346 3919456 : x = gen_lowpart_or_truncate (result_mode, x);
11347 :
11348 : /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11349 : operation. */
11350 3919456 : if (complement_p)
11351 23837 : x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11352 :
11353 3919456 : if (outer_op != UNKNOWN)
11354 : {
11355 3696222 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11356 :
11357 3696222 : if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11358 3696222 : && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11359 1340592 : outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11360 :
11361 3696222 : if (outer_op == AND)
11362 3228266 : x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11363 467956 : else if (outer_op == SET)
11364 : {
11365 : /* This means that we have determined that the result is
11366 : equivalent to a constant. This should be rare. */
11367 0 : if (!side_effects_p (x))
11368 0 : x = GEN_INT (outer_const);
11369 : }
11370 467956 : else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11371 18416 : x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11372 : else
11373 449540 : x = simplify_gen_binary (outer_op, int_result_mode, x,
11374 : GEN_INT (outer_const));
11375 : }
11376 :
11377 : return x;
11378 : }
11379 :
11380 : /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11381 : The result of the shift is RESULT_MODE. If we cannot simplify it,
11382 : return X or, if it is NULL, synthesize the expression with
11383 : simplify_gen_binary. Otherwise, return a simplified value.
11384 :
11385 : The shift is normally computed in the widest mode we find in VAROP, as
11386 : long as it isn't a different number of words than RESULT_MODE. Exceptions
11387 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
11388 :
11389 : static rtx
11390 20430469 : simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11391 : rtx varop, int count)
11392 : {
11393 20430469 : rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11394 20430469 : if (tem)
11395 : return tem;
11396 :
11397 16547107 : if (!x)
11398 4961459 : x = simplify_gen_binary (code, GET_MODE (varop), varop,
11399 4961459 : gen_int_shift_amount (GET_MODE (varop), count));
11400 16547107 : if (GET_MODE (x) != result_mode)
11401 0 : x = gen_lowpart (result_mode, x);
11402 : return x;
11403 : }
11404 :
11405 :
11406 : /* A subroutine of recog_for_combine. See there for arguments and
11407 : return value. */
11408 :
11409 : static int
11410 49637060 : recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11411 : unsigned old_nregs, unsigned new_nregs)
11412 : {
11413 49637060 : rtx pat = *pnewpat;
11414 49637060 : rtx pat_without_clobbers;
11415 49637060 : int insn_code_number;
11416 49637060 : int num_clobbers_to_add = 0;
11417 49637060 : int i;
11418 49637060 : rtx notes = NULL_RTX;
11419 49637060 : rtx old_notes, old_pat;
11420 49637060 : int old_icode;
11421 :
11422 : /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11423 : we use to indicate that something didn't match. If we find such a
11424 : thing, force rejection. */
11425 49637060 : if (GET_CODE (pat) == PARALLEL)
11426 53692647 : for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11427 37022326 : if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11428 7491082 : && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11429 : return -1;
11430 :
11431 49635000 : old_pat = PATTERN (insn);
11432 49635000 : old_notes = REG_NOTES (insn);
11433 49635000 : PATTERN (insn) = pat;
11434 49635000 : REG_NOTES (insn) = NULL_RTX;
11435 :
11436 49635000 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11437 49635000 : if (dump_file && (dump_flags & TDF_DETAILS))
11438 : {
11439 277 : if (insn_code_number < 0)
11440 177 : fputs ("Failed to match this instruction:\n", dump_file);
11441 : else
11442 100 : fputs ("Successfully matched this instruction:\n", dump_file);
11443 277 : print_rtl_single (dump_file, pat);
11444 : }
11445 :
11446 : /* If it isn't, there is the possibility that we previously had an insn
11447 : that clobbered some register as a side effect, but the combined
11448 : insn doesn't need to do that. So try once more without the clobbers
11449 : unless this represents an ASM insn. */
11450 :
11451 39570013 : if (insn_code_number < 0 && ! check_asm_operands (pat)
11452 89202645 : && GET_CODE (pat) == PARALLEL)
11453 : {
11454 : int pos;
11455 :
11456 52185073 : for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11457 35995993 : if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11458 : {
11459 28919413 : if (i != pos)
11460 2411426 : SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11461 28919413 : pos++;
11462 : }
11463 :
11464 16189080 : SUBST_INT (XVECLEN (pat, 0), pos);
11465 :
11466 16189080 : if (pos == 1)
11467 4753002 : pat = XVECEXP (pat, 0, 0);
11468 :
11469 16189080 : PATTERN (insn) = pat;
11470 16189080 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11471 16189080 : if (dump_file && (dump_flags & TDF_DETAILS))
11472 : {
11473 82 : if (insn_code_number < 0)
11474 81 : fputs ("Failed to match this instruction:\n", dump_file);
11475 : else
11476 1 : fputs ("Successfully matched this instruction:\n", dump_file);
11477 82 : print_rtl_single (dump_file, pat);
11478 : }
11479 : }
11480 :
11481 49635000 : pat_without_clobbers = pat;
11482 :
11483 49635000 : PATTERN (insn) = old_pat;
11484 49635000 : REG_NOTES (insn) = old_notes;
11485 :
11486 : /* Recognize all noop sets, these will be killed by followup pass. */
11487 49635000 : if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11488 242199 : insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11489 :
11490 : /* If we had any clobbers to add, make a new pattern than contains
11491 : them. Then check to make sure that all of them are dead. */
11492 49635000 : if (num_clobbers_to_add)
11493 : {
11494 1652559 : rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11495 : rtvec_alloc (GET_CODE (pat) == PARALLEL
11496 : ? (XVECLEN (pat, 0)
11497 : + num_clobbers_to_add)
11498 : : num_clobbers_to_add + 1));
11499 :
11500 1652559 : if (GET_CODE (pat) == PARALLEL)
11501 1449 : for (i = 0; i < XVECLEN (pat, 0); i++)
11502 966 : XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11503 : else
11504 1652076 : XVECEXP (newpat, 0, 0) = pat;
11505 :
11506 1652559 : add_clobbers (newpat, insn_code_number);
11507 :
11508 3192340 : for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11509 3192340 : i < XVECLEN (newpat, 0); i++)
11510 : {
11511 1675782 : if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11512 1675782 : && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11513 : return -1;
11514 1539781 : if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11515 : {
11516 1488822 : gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11517 1488822 : notes = alloc_reg_note (REG_UNUSED,
11518 : XEXP (XVECEXP (newpat, 0, i), 0), notes);
11519 : }
11520 : }
11521 : pat = newpat;
11522 : }
11523 :
11524 49498999 : if (insn_code_number >= 0
11525 49498999 : && insn_code_number != NOOP_MOVE_INSN_CODE)
11526 : {
11527 : /* Create the reg dead notes if needed for the regs that were created via split. */
11528 10249013 : for (; old_nregs < new_nregs; old_nregs++)
11529 2251 : notes = alloc_reg_note (REG_DEAD, regno_reg_rtx[old_nregs], notes);
11530 10246762 : old_pat = PATTERN (insn);
11531 10246762 : old_notes = REG_NOTES (insn);
11532 10246762 : old_icode = INSN_CODE (insn);
11533 10246762 : PATTERN (insn) = pat;
11534 10246762 : REG_NOTES (insn) = notes;
11535 10246762 : INSN_CODE (insn) = insn_code_number;
11536 :
11537 : /* Do not accept an insn if hard register constraints are used. For
11538 : example, assume that the first insn is combined into the last one:
11539 :
11540 : r100=...
11541 : %5=...
11542 : r101=exp(r100)
11543 :
11544 : If the resulting insn has an operand which is constrained to hard
11545 : register %5, then this introduces a conflict since register %5 is live
11546 : at this point. Therefore, skip for now. This is a sledge hammer
11547 : approach. Ideally we would skip based on the fact whether a
11548 : combination crosses a hard register assignment and the corresponding
11549 : hard register is also referred by a single register constraint of the
11550 : resulting insn. */
11551 10246762 : bool has_hard_reg_cstr = false;
11552 10246762 : extract_insn (insn);
11553 34932621 : for (int nop = recog_data.n_operands - 1; nop >= 0; --nop)
11554 24685859 : if (strchr (recog_data.constraints[nop], '{'))
11555 : {
11556 : has_hard_reg_cstr = true;
11557 : break;
11558 : }
11559 :
11560 : /* Don't accept hard register constraints. Allow targets to reject
11561 : combined insn. */
11562 10246762 : if (has_hard_reg_cstr || !targetm.legitimate_combined_insn (insn))
11563 : {
11564 3646 : if (dump_file && (dump_flags & TDF_DETAILS))
11565 : {
11566 0 : if (has_hard_reg_cstr)
11567 0 : fputs ("Instruction makes use of hard register constraints.",
11568 : dump_file);
11569 : else
11570 0 : fputs ("Instruction not appropriate for target.",
11571 : dump_file);
11572 : }
11573 :
11574 : /* Callers expect recog_for_combine to strip
11575 : clobbers from the pattern on failure. */
11576 : pat = pat_without_clobbers;
11577 : notes = NULL_RTX;
11578 :
11579 : insn_code_number = -1;
11580 : }
11581 :
11582 10246762 : PATTERN (insn) = old_pat;
11583 10246762 : REG_NOTES (insn) = old_notes;
11584 10246762 : INSN_CODE (insn) = old_icode;
11585 : }
11586 :
11587 49498999 : *pnewpat = pat;
11588 49498999 : *pnotes = notes;
11589 :
11590 49498999 : return insn_code_number;
11591 : }
11592 :
11593 : /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11594 : expressed as an AND and maybe an LSHIFTRT, to that formulation.
11595 : Return whether anything was so changed. */
11596 :
11597 : static bool
11598 49807056 : change_zero_ext (rtx pat)
11599 : {
11600 49807056 : bool changed = false;
11601 49807056 : rtx *src = &SET_SRC (pat);
11602 :
11603 49807056 : subrtx_ptr_iterator::array_type array;
11604 347599396 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11605 : {
11606 297792340 : rtx x = **iter;
11607 297792340 : scalar_int_mode mode, inner_mode;
11608 297792340 : if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11609 297792340 : continue;
11610 156054147 : int size;
11611 :
11612 156054147 : if (GET_CODE (x) == ZERO_EXTRACT
11613 809970 : && CONST_INT_P (XEXP (x, 1))
11614 809948 : && CONST_INT_P (XEXP (x, 2))
11615 767795 : && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11616 156821938 : && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11617 : {
11618 767773 : size = INTVAL (XEXP (x, 1));
11619 :
11620 767773 : int start = INTVAL (XEXP (x, 2));
11621 767773 : if (BITS_BIG_ENDIAN)
11622 : start = GET_MODE_PRECISION (inner_mode) - size - start;
11623 :
11624 767773 : if (start != 0)
11625 650902 : x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11626 : gen_int_shift_amount (inner_mode, start));
11627 : else
11628 : x = XEXP (x, 0);
11629 :
11630 767773 : if (mode != inner_mode)
11631 : {
11632 147 : if (REG_P (x) && HARD_REGISTER_P (x)
11633 217376 : && !can_change_dest_mode (x, 0, mode))
11634 0 : continue;
11635 :
11636 217376 : x = gen_lowpart_SUBREG (mode, x);
11637 : }
11638 : }
11639 155286374 : else if (GET_CODE (x) == ZERO_EXTEND
11640 2280789 : && GET_CODE (XEXP (x, 0)) == SUBREG
11641 429847 : && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11642 422378 : && !paradoxical_subreg_p (XEXP (x, 0))
11643 155708752 : && subreg_lowpart_p (XEXP (x, 0)))
11644 : {
11645 294180 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11646 294180 : size = GET_MODE_PRECISION (inner_mode);
11647 294180 : x = SUBREG_REG (XEXP (x, 0));
11648 294180 : if (GET_MODE (x) != mode)
11649 : {
11650 17132 : if (REG_P (x) && HARD_REGISTER_P (x)
11651 19999 : && !can_change_dest_mode (x, 0, mode))
11652 0 : continue;
11653 :
11654 19999 : x = gen_lowpart_SUBREG (mode, x);
11655 : }
11656 : }
11657 309984315 : else if (GET_CODE (x) == ZERO_EXTEND
11658 1986609 : && REG_P (XEXP (x, 0))
11659 1012433 : && HARD_REGISTER_P (XEXP (x, 0))
11660 154992267 : && can_change_dest_mode (XEXP (x, 0), 0, mode))
11661 : {
11662 73 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11663 73 : size = GET_MODE_PRECISION (inner_mode);
11664 73 : x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11665 : }
11666 : else
11667 154992121 : continue;
11668 :
11669 1513671 : if (!(GET_CODE (x) == LSHIFTRT
11670 451645 : && CONST_INT_P (XEXP (x, 1))
11671 451645 : && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11672 : {
11673 876774 : wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11674 876774 : x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11675 876774 : }
11676 :
11677 1062026 : SUBST (**iter, x);
11678 1062026 : changed = true;
11679 : }
11680 :
11681 49807056 : if (changed)
11682 9757496 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11683 8708573 : maybe_swap_commutative_operands (**iter);
11684 :
11685 49807056 : rtx *dst = &SET_DEST (pat);
11686 49807056 : scalar_int_mode mode;
11687 49807056 : if (GET_CODE (*dst) == ZERO_EXTRACT
11688 9105 : && REG_P (XEXP (*dst, 0))
11689 355 : && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11690 355 : && CONST_INT_P (XEXP (*dst, 1))
11691 49807411 : && CONST_INT_P (XEXP (*dst, 2)))
11692 : {
11693 252 : rtx reg = XEXP (*dst, 0);
11694 252 : int width = INTVAL (XEXP (*dst, 1));
11695 252 : int offset = INTVAL (XEXP (*dst, 2));
11696 252 : int reg_width = GET_MODE_PRECISION (mode);
11697 252 : if (BITS_BIG_ENDIAN)
11698 : offset = reg_width - width - offset;
11699 :
11700 252 : rtx x, y, z, w;
11701 252 : wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11702 252 : wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11703 252 : x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11704 252 : if (offset)
11705 202 : y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11706 : else
11707 50 : y = SET_SRC (pat);
11708 252 : z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11709 252 : w = gen_rtx_IOR (mode, x, z);
11710 252 : SUBST (SET_DEST (pat), reg);
11711 252 : SUBST (SET_SRC (pat), w);
11712 :
11713 252 : changed = true;
11714 252 : }
11715 :
11716 49807056 : return changed;
11717 49807056 : }
11718 :
11719 : /* Like recog, but we receive the address of a pointer to a new pattern.
11720 : We try to match the rtx that the pointer points to.
11721 : If that fails, we may try to modify or replace the pattern,
11722 : storing the replacement into the same pointer object.
11723 :
11724 : Modifications include deletion or addition of CLOBBERs. If the
11725 : instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11726 : to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11727 : (and undo if that fails).
11728 :
11729 : PNOTES is a pointer to a location where any REG_UNUSED notes added for
11730 : the CLOBBERs are placed.
11731 : If OLD_NREGS != NEW_NREGS, then PNOTES also includes REG_DEAD notes added.
11732 :
11733 : The value is the final insn code from the pattern ultimately matched,
11734 : or -1. */
11735 :
11736 : static int
11737 48348266 : recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11738 : unsigned int old_nregs, unsigned int new_nregs)
11739 : {
11740 48348266 : rtx pat = *pnewpat;
11741 48348266 : int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11742 : old_nregs, new_nregs);
11743 48348266 : if (insn_code_number >= 0 || check_asm_operands (pat))
11744 : return insn_code_number;
11745 :
11746 38022626 : void *marker = get_undo_marker ();
11747 38022626 : bool changed = false;
11748 :
11749 38022626 : if (GET_CODE (pat) == SET)
11750 : {
11751 : /* For an unrecognized single set of a constant, try placing it in
11752 : the constant pool, if this function already uses one. */
11753 22407640 : rtx src = SET_SRC (pat);
11754 22407640 : if (CONSTANT_P (src)
11755 466818 : && !CONST_INT_P (src)
11756 417449 : && crtl->uses_const_pool
11757 365050 : && SET_DEST (pat) != pc_rtx)
11758 : {
11759 365048 : machine_mode mode = GET_MODE (src);
11760 365048 : if (mode == VOIDmode)
11761 1337 : mode = GET_MODE (SET_DEST (pat));
11762 365048 : src = force_const_mem (mode, src);
11763 365048 : if (src)
11764 : {
11765 365038 : SUBST (SET_SRC (pat), src);
11766 365038 : changed = true;
11767 : }
11768 : }
11769 : else
11770 22042592 : changed = change_zero_ext (pat);
11771 : }
11772 15614986 : else if (GET_CODE (pat) == PARALLEL)
11773 : {
11774 : int i;
11775 43618448 : for (i = 0; i < XVECLEN (pat, 0); i++)
11776 : {
11777 28018904 : rtx set = XVECEXP (pat, 0, i);
11778 28018904 : if (GET_CODE (set) == SET)
11779 27764464 : changed |= change_zero_ext (set);
11780 : }
11781 : }
11782 :
11783 38007174 : if (changed)
11784 : {
11785 1288794 : insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11786 : old_nregs, new_nregs);
11787 :
11788 1288794 : if (insn_code_number < 0)
11789 1126751 : undo_to_marker (marker);
11790 : }
11791 :
11792 : return insn_code_number;
11793 : }
11794 :
11795 : /* Like gen_lowpart_general but for use by combine. In combine it
11796 : is not possible to create any new pseudoregs. However, it is
11797 : safe to create invalid memory addresses, because combine will
11798 : try to recognize them and all they will do is make the combine
11799 : attempt fail.
11800 :
11801 : If for some reason this cannot do its job, an rtx
11802 : (clobber (const_int 0)) is returned.
11803 : An insn containing that will not be recognized. */
11804 :
11805 : static rtx
11806 158098018 : gen_lowpart_for_combine (machine_mode omode, rtx x)
11807 : {
11808 158098018 : machine_mode imode = GET_MODE (x);
11809 158098018 : rtx result;
11810 :
11811 158098018 : if (omode == imode)
11812 : return x;
11813 :
11814 : /* We can only support MODE being wider than a word if X is a
11815 : constant integer or has a mode the same size. */
11816 55910377 : if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11817 26490910 : && ! (CONST_SCALAR_INT_P (x)
11818 10078410 : || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11819 3053506 : goto fail;
11820 :
11821 : /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11822 : won't know what to do. So we will strip off the SUBREG here and
11823 : process normally. */
11824 23437404 : if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11825 : {
11826 13556 : x = SUBREG_REG (x);
11827 :
11828 : /* For use in case we fall down into the address adjustments
11829 : further below, we need to adjust the known mode and size of
11830 : x; imode and isize, since we just adjusted x. */
11831 13556 : imode = GET_MODE (x);
11832 :
11833 13556 : if (imode == omode)
11834 : return x;
11835 : }
11836 :
11837 23428352 : result = gen_lowpart_common (omode, x);
11838 :
11839 23428352 : if (result)
11840 : return result;
11841 :
11842 9880966 : if (MEM_P (x))
11843 : {
11844 : /* Refuse to work on a volatile memory ref or one with a mode-dependent
11845 : address. */
11846 1931342 : if (MEM_VOLATILE_P (x)
11847 3814401 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11848 48314 : goto fail;
11849 :
11850 : /* If we want to refer to something bigger than the original memref,
11851 : generate a paradoxical subreg instead. That will force a reload
11852 : of the original memref X. */
11853 1883028 : if (paradoxical_subreg_p (omode, imode)
11854 1883028 : && validate_subreg (omode, GET_MODE (x), x, 0))
11855 1673334 : return gen_rtx_SUBREG (omode, x, 0);
11856 :
11857 209694 : poly_int64 offset = byte_lowpart_offset (omode, imode);
11858 209694 : return adjust_address_nv (x, omode, offset);
11859 : }
11860 :
11861 : /* If X is a comparison operator, rewrite it in a new mode. This
11862 : probably won't match, but may allow further simplifications. */
11863 7949624 : else if (COMPARISON_P (x)
11864 147516 : && SCALAR_INT_MODE_P (imode)
11865 53679 : && SCALAR_INT_MODE_P (omode))
11866 53668 : return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11867 :
11868 : /* If we couldn't simplify X any other way, just enclose it in a
11869 : SUBREG. Normally, this SUBREG won't match, but some patterns may
11870 : include an explicit SUBREG or we may simplify it further in combine. */
11871 : else
11872 : {
11873 7895956 : rtx res;
11874 :
11875 7895956 : if (imode == VOIDmode)
11876 : {
11877 8 : imode = int_mode_for_mode (omode).require ();
11878 8 : x = gen_lowpart_common (imode, x);
11879 8 : if (x == NULL)
11880 0 : goto fail;
11881 : }
11882 7895956 : res = lowpart_subreg (omode, x, imode);
11883 7895956 : if (res)
11884 : return res;
11885 : }
11886 :
11887 17826 : fail:
11888 3119646 : return gen_rtx_CLOBBER (omode, const0_rtx);
11889 : }
11890 :
11891 : /* Like gen_lowpart_for_combine but returns NULL_RTX
11892 : for an error instead of CLOBBER.
11893 : Note no_emit is not called directly from combine but rather from
11894 : simplify_rtx and is expecting a NULL on failure rather than
11895 : a CLOBBER. */
11896 :
11897 : static rtx
11898 1561319 : gen_lowpart_for_combine_no_emit (machine_mode omode, rtx x)
11899 : {
11900 1561319 : rtx tem = gen_lowpart_for_combine (omode, x);
11901 1561319 : if (!tem || GET_CODE (tem) == CLOBBER)
11902 16036 : return NULL_RTX;
11903 : return tem;
11904 : }
11905 :
11906 :
11907 : /* Try to simplify a comparison between OP0 and a constant OP1,
11908 : where CODE is the comparison code that will be tested, into a
11909 : (CODE OP0 const0_rtx) form.
11910 :
11911 : The result is a possibly different comparison code to use.
11912 : *POP0 and *POP1 may be updated. */
11913 :
11914 : static enum rtx_code
11915 16037724 : simplify_compare_const (enum rtx_code code, machine_mode mode,
11916 : rtx *pop0, rtx *pop1)
11917 : {
11918 16037724 : scalar_int_mode int_mode;
11919 16037724 : rtx op0 = *pop0;
11920 16037724 : HOST_WIDE_INT const_op = INTVAL (*pop1);
11921 :
11922 : /* Get the constant we are comparing against and turn off all bits
11923 : not on in our mode. */
11924 16037724 : if (mode != VOIDmode)
11925 15644368 : const_op = trunc_int_for_mode (const_op, mode);
11926 :
11927 : /* If we are comparing against a constant power of two and the value
11928 : being compared can only have that single bit nonzero (e.g., it was
11929 : `and'ed with that bit), we can replace this with a comparison
11930 : with zero. */
11931 16037724 : if (const_op
11932 4197481 : && (code == EQ || code == NE || code == GEU || code == LTU
11933 : /* This optimization is incorrect for signed >= INT_MIN or
11934 : < INT_MIN, those are always true or always false. */
11935 24180 : || ((code == GE || code == LT) && const_op > 0))
11936 2803933 : && is_a <scalar_int_mode> (mode, &int_mode)
11937 2803933 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11938 2784625 : && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11939 16940085 : && (nonzero_bits (op0, int_mode)
11940 902361 : == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11941 : {
11942 4956 : code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11943 : const_op = 0;
11944 : }
11945 :
11946 : /* Similarly, if we are comparing a value known to be either -1 or
11947 : 0 with -1, change it to the opposite comparison against zero. */
11948 2350 : if (const_op == -1
11949 258108 : && (code == EQ || code == NE || code == GT || code == LE
11950 : || code == GEU || code == LTU)
11951 16281073 : && is_a <scalar_int_mode> (mode, &int_mode)
11952 16288167 : && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11953 : {
11954 12050 : code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11955 : const_op = 0;
11956 : }
11957 :
11958 : /* Do some canonicalizations based on the comparison code. We prefer
11959 : comparisons against zero and then prefer equality comparisons.
11960 : If we can reduce the size of a constant, we will do that too. */
11961 16025674 : switch (code)
11962 : {
11963 268087 : case LT:
11964 : /* < C is equivalent to <= (C - 1) */
11965 268087 : if (const_op > 0)
11966 : {
11967 5219 : const_op -= 1;
11968 5219 : code = LE;
11969 : /* ... fall through to LE case below. */
11970 461662 : gcc_fallthrough ();
11971 : }
11972 : else
11973 : break;
11974 :
11975 461662 : case LE:
11976 : /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11977 461662 : if (const_op < 0)
11978 : {
11979 52 : const_op += 1;
11980 52 : code = LT;
11981 : }
11982 :
11983 : /* If we are doing a <= 0 comparison on a value known to have
11984 : a zero sign bit, we can replace this with == 0. */
11985 461610 : else if (const_op == 0
11986 319294 : && is_a <scalar_int_mode> (mode, &int_mode)
11987 319294 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11988 780904 : && (nonzero_bits (op0, int_mode)
11989 319294 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11990 319294 : == 0)
11991 : code = EQ;
11992 : break;
11993 :
11994 243849 : case GE:
11995 : /* >= C is equivalent to > (C - 1). */
11996 243849 : if (const_op > 0)
11997 : {
11998 995 : const_op -= 1;
11999 995 : code = GT;
12000 : /* ... fall through to GT below. */
12001 260943 : gcc_fallthrough ();
12002 : }
12003 : else
12004 : break;
12005 :
12006 260943 : case GT:
12007 : /* > C is equivalent to >= (C + 1); we do this for C < 0. */
12008 260943 : if (const_op < 0)
12009 : {
12010 272 : const_op += 1;
12011 272 : code = GE;
12012 : }
12013 :
12014 : /* If we are doing a > 0 comparison on a value known to have
12015 : a zero sign bit, we can replace this with != 0. */
12016 260671 : else if (const_op == 0
12017 133858 : && is_a <scalar_int_mode> (mode, &int_mode)
12018 133858 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12019 394529 : && (nonzero_bits (op0, int_mode)
12020 133858 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12021 133858 : == 0)
12022 : code = NE;
12023 : break;
12024 :
12025 97141 : case LTU:
12026 : /* < C is equivalent to <= (C - 1). */
12027 97141 : if (const_op > 0)
12028 : {
12029 87573 : const_op -= 1;
12030 87573 : code = LEU;
12031 : /* ... fall through ... */
12032 87573 : gcc_fallthrough ();
12033 : }
12034 : /* (unsigned) < 0x80000000 is equivalent to >= 0. */
12035 9568 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12036 9568 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12037 8795 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12038 8795 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12039 : {
12040 : const_op = 0;
12041 : code = GE;
12042 : break;
12043 : }
12044 : else
12045 : break;
12046 :
12047 699508 : case LEU:
12048 : /* unsigned <= 0 is equivalent to == 0 */
12049 699508 : if (const_op == 0)
12050 : code = EQ;
12051 : /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12052 699092 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12053 699092 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12054 697151 : && ((unsigned HOST_WIDE_INT) const_op
12055 : == ((HOST_WIDE_INT_1U
12056 697151 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12057 : {
12058 : const_op = 0;
12059 : code = GE;
12060 : }
12061 : break;
12062 :
12063 30867 : case GEU:
12064 : /* >= C is equivalent to > (C - 1). */
12065 30867 : if (const_op > 1)
12066 : {
12067 22211 : const_op -= 1;
12068 22211 : code = GTU;
12069 : /* ... fall through ... */
12070 22211 : gcc_fallthrough ();
12071 : }
12072 :
12073 : /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12074 8656 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12075 8656 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12076 7400 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12077 7400 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12078 : {
12079 : const_op = 0;
12080 : code = LT;
12081 : break;
12082 : }
12083 : else
12084 : break;
12085 :
12086 522619 : case GTU:
12087 : /* unsigned > 0 is equivalent to != 0 */
12088 522619 : if (const_op == 0)
12089 : code = NE;
12090 : /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12091 522619 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12092 522619 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12093 521442 : && ((unsigned HOST_WIDE_INT) const_op
12094 : == (HOST_WIDE_INT_1U
12095 521442 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12096 : {
12097 : const_op = 0;
12098 : code = LT;
12099 : }
12100 : break;
12101 :
12102 : default:
12103 : break;
12104 : }
12105 :
12106 : /* Narrow non-symmetric comparison of memory and constant as e.g.
12107 : x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12108 : significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
12109 : x0 >= 0x40. */
12110 15321210 : if ((code == LEU || code == LTU || code == GEU || code == GTU)
12111 1236741 : && is_a <scalar_int_mode> (GET_MODE (op0), &int_mode)
12112 1236716 : && HWI_COMPUTABLE_MODE_P (int_mode)
12113 1231569 : && MEM_P (op0)
12114 79165 : && !MEM_VOLATILE_P (op0)
12115 : /* The optimization makes only sense for constants which are big enough
12116 : so that we have a chance to chop off something at all. */
12117 78303 : && ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12118 : /* Ensure that we do not overflow during normalization. */
12119 21597 : && (code != GTU
12120 3830 : || ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12121 : < HOST_WIDE_INT_M1U)
12122 16059321 : && trunc_int_for_mode (const_op, int_mode) == const_op)
12123 : {
12124 21597 : unsigned HOST_WIDE_INT n
12125 21597 : = (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12126 21597 : enum rtx_code adjusted_code;
12127 :
12128 : /* Normalize code to either LEU or GEU. */
12129 21597 : if (code == LTU)
12130 : {
12131 116 : --n;
12132 116 : adjusted_code = LEU;
12133 : }
12134 21481 : else if (code == GTU)
12135 : {
12136 3830 : ++n;
12137 3830 : adjusted_code = GEU;
12138 : }
12139 : else
12140 : adjusted_code = code;
12141 :
12142 21597 : scalar_int_mode narrow_mode_iter;
12143 66970 : FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12144 : {
12145 46035 : unsigned nbits = GET_MODE_PRECISION (int_mode)
12146 46035 : - GET_MODE_PRECISION (narrow_mode_iter);
12147 46035 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12148 46035 : unsigned HOST_WIDE_INT lower_bits = n & mask;
12149 46035 : if ((adjusted_code == LEU && lower_bits == mask)
12150 45780 : || (adjusted_code == GEU && lower_bits == 0))
12151 : {
12152 662 : n >>= nbits;
12153 662 : break;
12154 : }
12155 : }
12156 :
12157 21597 : if (narrow_mode_iter < int_mode)
12158 : {
12159 662 : if (dump_file && (dump_flags & TDF_DETAILS))
12160 : {
12161 12 : fprintf (
12162 : dump_file, "narrow comparison from mode %s to %s: (MEM %s "
12163 : HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12164 12 : HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12165 12 : GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12166 12 : (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12167 12 : GET_RTX_NAME (adjusted_code), n);
12168 : }
12169 662 : poly_int64 offset = (BYTES_BIG_ENDIAN
12170 662 : ? 0
12171 662 : : (GET_MODE_SIZE (int_mode)
12172 662 : - GET_MODE_SIZE (narrow_mode_iter)));
12173 662 : *pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12174 662 : *pop1 = gen_int_mode (n, narrow_mode_iter);
12175 662 : return adjusted_code;
12176 : }
12177 : }
12178 :
12179 16037062 : *pop1 = GEN_INT (const_op);
12180 16037062 : return code;
12181 : }
12182 :
12183 : /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12184 : comparison code that will be tested.
12185 :
12186 : The result is a possibly different comparison code to use. *POP0 and
12187 : *POP1 may be updated.
12188 :
12189 : It is possible that we might detect that a comparison is either always
12190 : true or always false. However, we do not perform general constant
12191 : folding in combine, so this knowledge isn't useful. Such tautologies
12192 : should have been detected earlier. Hence we ignore all such cases. */
12193 :
12194 : static enum rtx_code
12195 24349517 : simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12196 : {
12197 24349517 : rtx op0 = *pop0;
12198 24349517 : rtx op1 = *pop1;
12199 24349517 : rtx tem, tem1;
12200 24349517 : int i;
12201 24349517 : scalar_int_mode mode, inner_mode, tmode;
12202 24349517 : opt_scalar_int_mode tmode_iter;
12203 :
12204 : /* Try a few ways of applying the same transformation to both operands. */
12205 24349774 : while (1)
12206 : {
12207 : /* The test below this one won't handle SIGN_EXTENDs on these machines,
12208 : so check specially. */
12209 24349774 : if (!WORD_REGISTER_OPERATIONS
12210 24349774 : && code != GTU && code != GEU && code != LTU && code != LEU
12211 21113516 : && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12212 1447 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12213 1096 : && GET_CODE (XEXP (op1, 0)) == ASHIFT
12214 726 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12215 726 : && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12216 726 : && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12217 : && (is_a <scalar_int_mode>
12218 726 : (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12219 726 : && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12220 726 : && CONST_INT_P (XEXP (op0, 1))
12221 726 : && XEXP (op0, 1) == XEXP (op1, 1)
12222 93 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12223 93 : && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12224 93 : && (INTVAL (XEXP (op0, 1))
12225 93 : == (GET_MODE_PRECISION (mode)
12226 93 : - GET_MODE_PRECISION (inner_mode))))
12227 : {
12228 93 : op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12229 93 : op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12230 : }
12231 :
12232 : /* If both operands are the same constant shift, see if we can ignore the
12233 : shift. We can if the shift is a rotate or if the bits shifted out of
12234 : this shift are known to be zero for both inputs and if the type of
12235 : comparison is compatible with the shift. */
12236 24349774 : if (GET_CODE (op0) == GET_CODE (op1)
12237 3544108 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12238 3202346 : && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12239 3202346 : || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12240 782 : && (code != GT && code != LT && code != GE && code != LE))
12241 3201616 : || (GET_CODE (op0) == ASHIFTRT
12242 1399 : && (code != GTU && code != LTU
12243 1391 : && code != GEU && code != LEU)))
12244 2084 : && CONST_INT_P (XEXP (op0, 1))
12245 2056 : && INTVAL (XEXP (op0, 1)) >= 0
12246 2056 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12247 24351830 : && XEXP (op0, 1) == XEXP (op1, 1))
12248 : {
12249 982 : machine_mode mode = GET_MODE (op0);
12250 982 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12251 982 : int shift_count = INTVAL (XEXP (op0, 1));
12252 :
12253 982 : if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12254 467 : mask &= (mask >> shift_count) << shift_count;
12255 515 : else if (GET_CODE (op0) == ASHIFT)
12256 515 : mask = (mask & (mask << shift_count)) >> shift_count;
12257 :
12258 982 : if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12259 982 : && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12260 87 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12261 : else
12262 : break;
12263 : }
12264 :
12265 : /* If both operands are AND's of a paradoxical SUBREG by constant, the
12266 : SUBREGs are of the same mode, and, in both cases, the AND would
12267 : be redundant if the comparison was done in the narrower mode,
12268 : do the comparison in the narrower mode (e.g., we are AND'ing with 1
12269 : and the operand's possibly nonzero bits are 0xffffff01; in that case
12270 : if we only care about QImode, we don't need the AND). This case
12271 : occurs if the output mode of an scc insn is not SImode and
12272 : STORE_FLAG_VALUE == 1 (e.g., the 386).
12273 :
12274 : Similarly, check for a case where the AND's are ZERO_EXTEND
12275 : operations from some narrower mode even though a SUBREG is not
12276 : present. */
12277 :
12278 24348792 : else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12279 2579 : && CONST_INT_P (XEXP (op0, 1))
12280 2497 : && CONST_INT_P (XEXP (op1, 1)))
12281 : {
12282 2481 : rtx inner_op0 = XEXP (op0, 0);
12283 2481 : rtx inner_op1 = XEXP (op1, 0);
12284 2481 : HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12285 2481 : HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12286 2481 : bool changed = false;
12287 :
12288 2481 : if (paradoxical_subreg_p (inner_op0)
12289 1035 : && GET_CODE (inner_op1) == SUBREG
12290 497 : && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12291 497 : && (GET_MODE (SUBREG_REG (inner_op0))
12292 497 : == GET_MODE (SUBREG_REG (inner_op1)))
12293 207 : && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12294 : GET_MODE (SUBREG_REG (inner_op0)))) == 0
12295 1731 : && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12296 137 : GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12297 : {
12298 121 : op0 = SUBREG_REG (inner_op0);
12299 121 : op1 = SUBREG_REG (inner_op1);
12300 :
12301 : /* The resulting comparison is always unsigned since we masked
12302 : off the original sign bit. */
12303 121 : code = unsigned_condition (code);
12304 :
12305 121 : changed = true;
12306 : }
12307 :
12308 2360 : else if (c0 == c1)
12309 5095 : FOR_EACH_MODE_UNTIL (tmode,
12310 : as_a <scalar_int_mode> (GET_MODE (op0)))
12311 3124 : if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12312 : {
12313 38 : op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12314 38 : op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12315 38 : code = unsigned_condition (code);
12316 38 : changed = true;
12317 38 : break;
12318 : }
12319 :
12320 2130 : if (! changed)
12321 : break;
12322 : }
12323 :
12324 : /* If both operands are NOT, we can strip off the outer operation
12325 : and adjust the comparison code for swapped operands; similarly for
12326 : NEG, except that this must be an equality comparison. */
12327 24346311 : else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12328 24346311 : || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12329 11 : && (code == EQ || code == NE)))
12330 11 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12331 :
12332 : else
12333 : break;
12334 : }
12335 :
12336 : /* If the first operand is a constant, swap the operands and adjust the
12337 : comparison code appropriately, but don't do this if the second operand
12338 : is already a constant integer. */
12339 24349517 : if (swap_commutative_operands_p (op0, op1))
12340 : {
12341 1561622 : std::swap (op0, op1);
12342 1561622 : code = swap_condition (code);
12343 : }
12344 :
12345 : /* We now enter a loop during which we will try to simplify the comparison.
12346 : For the most part, we only are concerned with comparisons with zero,
12347 : but some things may really be comparisons with zero but not start
12348 : out looking that way. */
12349 :
12350 25465600 : while (CONST_INT_P (op1))
12351 : {
12352 16523295 : machine_mode raw_mode = GET_MODE (op0);
12353 16523295 : scalar_int_mode int_mode;
12354 16523295 : int equality_comparison_p;
12355 16523295 : int sign_bit_comparison_p;
12356 16523295 : int unsigned_comparison_p;
12357 16523295 : HOST_WIDE_INT const_op;
12358 :
12359 : /* We only want to handle integral modes. This catches VOIDmode,
12360 : CCmode, and the floating-point modes. An exception is that we
12361 : can handle VOIDmode if OP0 is a COMPARE or a comparison
12362 : operation. */
12363 :
12364 16523295 : if (GET_MODE_CLASS (raw_mode) != MODE_INT
12365 1693716 : && ! (raw_mode == VOIDmode
12366 393386 : && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12367 : break;
12368 :
12369 : /* Try to simplify the compare to constant, possibly changing the
12370 : comparison op, and/or changing op1 to zero. */
12371 15222935 : code = simplify_compare_const (code, raw_mode, &op0, &op1);
12372 15222935 : const_op = INTVAL (op1);
12373 :
12374 : /* Compute some predicates to simplify code below. */
12375 :
12376 15222935 : equality_comparison_p = (code == EQ || code == NE);
12377 15222935 : sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12378 15222935 : unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12379 15222935 : || code == GEU);
12380 :
12381 : /* If this is a sign bit comparison and we can do arithmetic in
12382 : MODE, say that we will only be needing the sign bit of OP0. */
12383 15222935 : if (sign_bit_comparison_p
12384 460883 : && is_a <scalar_int_mode> (raw_mode, &int_mode)
12385 15683818 : && HWI_COMPUTABLE_MODE_P (int_mode))
12386 460491 : op0 = force_to_mode (op0, int_mode,
12387 : HOST_WIDE_INT_1U
12388 460491 : << (GET_MODE_PRECISION (int_mode) - 1), false);
12389 :
12390 15222935 : if (COMPARISON_P (op0))
12391 : {
12392 : /* We can't do anything if OP0 is a condition code value, rather
12393 : than an actual data value. */
12394 717689 : if (const_op != 0
12395 717689 : || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12396 : break;
12397 :
12398 : /* Get the two operands being compared. */
12399 136213 : if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12400 0 : tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12401 : else
12402 136213 : tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12403 :
12404 : /* Check for the cases where we simply want the result of the
12405 : earlier test or the opposite of that result. */
12406 136213 : if (code == NE || code == EQ
12407 136213 : || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12408 0 : && (code == LT || code == GE)))
12409 : {
12410 136213 : enum rtx_code new_code;
12411 136213 : if (code == LT || code == NE)
12412 136213 : new_code = GET_CODE (op0);
12413 : else
12414 0 : new_code = reversed_comparison_code (op0, NULL);
12415 :
12416 136213 : if (new_code != UNKNOWN)
12417 : {
12418 136213 : code = new_code;
12419 136213 : op0 = tem;
12420 136213 : op1 = tem1;
12421 1116083 : continue;
12422 : }
12423 : }
12424 : break;
12425 : }
12426 :
12427 14505246 : if (raw_mode == VOIDmode)
12428 : break;
12429 14505246 : scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12430 :
12431 : /* Now try cases based on the opcode of OP0. If none of the cases
12432 : does a "continue", we exit this loop immediately after the
12433 : switch. */
12434 :
12435 14505246 : unsigned int mode_width = GET_MODE_PRECISION (mode);
12436 14505246 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12437 14505246 : switch (GET_CODE (op0))
12438 : {
12439 383649 : case ZERO_EXTRACT:
12440 : /* If we are extracting a single bit from a variable position in
12441 : a constant that has only a single bit set and are comparing it
12442 : with zero, we can convert this into an equality comparison
12443 : between the position and the location of the single bit. */
12444 : /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12445 : have already reduced the shift count modulo the word size. */
12446 383649 : if (!SHIFT_COUNT_TRUNCATED
12447 383649 : && CONST_INT_P (XEXP (op0, 0))
12448 9131 : && XEXP (op0, 1) == const1_rtx
12449 9113 : && equality_comparison_p && const_op == 0
12450 392762 : && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12451 : {
12452 0 : if (BITS_BIG_ENDIAN)
12453 : i = BITS_PER_WORD - 1 - i;
12454 :
12455 0 : op0 = XEXP (op0, 2);
12456 0 : op1 = GEN_INT (i);
12457 0 : const_op = i;
12458 :
12459 : /* Result is nonzero iff shift count is equal to I. */
12460 0 : code = reverse_condition (code);
12461 0 : continue;
12462 : }
12463 :
12464 : /* fall through */
12465 :
12466 383653 : case SIGN_EXTRACT:
12467 383653 : tem = expand_compound_operation (op0);
12468 383653 : if (tem != op0)
12469 : {
12470 350649 : op0 = tem;
12471 350649 : continue;
12472 : }
12473 : break;
12474 :
12475 28611 : case NOT:
12476 : /* If testing for equality, we can take the NOT of the constant. */
12477 40713 : if (equality_comparison_p
12478 28611 : && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12479 : {
12480 12102 : op0 = XEXP (op0, 0);
12481 12102 : op1 = tem;
12482 12102 : continue;
12483 : }
12484 :
12485 : /* If just looking at the sign bit, reverse the sense of the
12486 : comparison. */
12487 16509 : if (sign_bit_comparison_p)
12488 : {
12489 16161 : op0 = XEXP (op0, 0);
12490 16161 : code = (code == GE ? LT : GE);
12491 16161 : continue;
12492 : }
12493 : break;
12494 :
12495 245761 : case NEG:
12496 : /* If testing for equality, we can take the NEG of the constant. */
12497 487999 : if (equality_comparison_p
12498 245761 : && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12499 : {
12500 242238 : op0 = XEXP (op0, 0);
12501 242238 : op1 = tem;
12502 242238 : continue;
12503 : }
12504 :
12505 : /* The remaining cases only apply to comparisons with zero. */
12506 3523 : if (const_op != 0)
12507 : break;
12508 :
12509 : /* When X is ABS or is known positive,
12510 : (neg X) is < 0 if and only if X != 0. */
12511 :
12512 2948 : if (sign_bit_comparison_p
12513 2910 : && (GET_CODE (XEXP (op0, 0)) == ABS
12514 2905 : || (mode_width <= HOST_BITS_PER_WIDE_INT
12515 2905 : && (nonzero_bits (XEXP (op0, 0), mode)
12516 2905 : & (HOST_WIDE_INT_1U << (mode_width - 1)))
12517 2905 : == 0)))
12518 : {
12519 38 : op0 = XEXP (op0, 0);
12520 38 : code = (code == LT ? NE : EQ);
12521 38 : continue;
12522 : }
12523 :
12524 : /* If we have NEG of something whose two high-order bits are the
12525 : same, we know that "(-a) < 0" is equivalent to "a > 0". */
12526 2872 : if (num_sign_bit_copies (op0, mode) >= 2)
12527 : {
12528 22 : op0 = XEXP (op0, 0);
12529 22 : code = swap_condition (code);
12530 22 : continue;
12531 : }
12532 : break;
12533 :
12534 146 : case ROTATE:
12535 : /* If we are testing equality and our count is a constant, we
12536 : can perform the inverse operation on our RHS. */
12537 146 : if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12538 146 : && (tem = simplify_binary_operation (ROTATERT, mode,
12539 : op1, XEXP (op0, 1))) != 0)
12540 : {
12541 0 : op0 = XEXP (op0, 0);
12542 0 : op1 = tem;
12543 0 : continue;
12544 : }
12545 :
12546 : /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12547 : a particular bit. Convert it to an AND of a constant of that
12548 : bit. This will be converted into a ZERO_EXTRACT. */
12549 146 : if (const_op == 0 && sign_bit_comparison_p
12550 0 : && CONST_INT_P (XEXP (op0, 1))
12551 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
12552 0 : && UINTVAL (XEXP (op0, 1)) < mode_width)
12553 : {
12554 0 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12555 : (HOST_WIDE_INT_1U
12556 : << (mode_width - 1
12557 0 : - INTVAL (XEXP (op0, 1)))));
12558 0 : code = (code == LT ? NE : EQ);
12559 0 : continue;
12560 : }
12561 :
12562 : /* Fall through. */
12563 :
12564 2200 : case ABS:
12565 : /* ABS is ignorable inside an equality comparison with zero. */
12566 2200 : if (const_op == 0 && equality_comparison_p)
12567 : {
12568 1 : op0 = XEXP (op0, 0);
12569 1 : continue;
12570 : }
12571 : break;
12572 :
12573 1754 : case SIGN_EXTEND:
12574 : /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12575 : (compare FOO CONST) if CONST fits in FOO's mode and we
12576 : are either testing inequality or have an unsigned
12577 : comparison with ZERO_EXTEND or a signed comparison with
12578 : SIGN_EXTEND. But don't do it if we don't have a compare
12579 : insn of the given mode, since we'd have to revert it
12580 : later on, and then we wouldn't know whether to sign- or
12581 : zero-extend. */
12582 1754 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12583 1754 : && ! unsigned_comparison_p
12584 986 : && HWI_COMPUTABLE_MODE_P (mode)
12585 986 : && trunc_int_for_mode (const_op, mode) == const_op
12586 986 : && have_insn_for (COMPARE, mode))
12587 : {
12588 986 : op0 = XEXP (op0, 0);
12589 986 : continue;
12590 : }
12591 : break;
12592 :
12593 484797 : case SUBREG:
12594 : /* Check for the case where we are comparing A - C1 with C2, that is
12595 :
12596 : (subreg:MODE (plus (A) (-C1))) op (C2)
12597 :
12598 : with C1 a constant, and try to lift the SUBREG, i.e. to do the
12599 : comparison in the wider mode. One of the following two conditions
12600 : must be true in order for this to be valid:
12601 :
12602 : 1. The mode extension results in the same bit pattern being added
12603 : on both sides and the comparison is equality or unsigned. As
12604 : C2 has been truncated to fit in MODE, the pattern can only be
12605 : all 0s or all 1s.
12606 :
12607 : 2. The mode extension results in the sign bit being copied on
12608 : each side.
12609 :
12610 : The difficulty here is that we have predicates for A but not for
12611 : (A - C1) so we need to check that C1 is within proper bounds so
12612 : as to perturb A as little as possible. */
12613 :
12614 484797 : if (mode_width <= HOST_BITS_PER_WIDE_INT
12615 484721 : && subreg_lowpart_p (op0)
12616 453834 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12617 : &inner_mode)
12618 451751 : && GET_MODE_PRECISION (inner_mode) > mode_width
12619 451751 : && GET_CODE (SUBREG_REG (op0)) == PLUS
12620 484797 : && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12621 : {
12622 0 : rtx a = XEXP (SUBREG_REG (op0), 0);
12623 0 : HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12624 :
12625 0 : if ((c1 > 0
12626 0 : && (unsigned HOST_WIDE_INT) c1
12627 0 : < HOST_WIDE_INT_1U << (mode_width - 1)
12628 0 : && (equality_comparison_p || unsigned_comparison_p)
12629 : /* (A - C1) zero-extends if it is positive and sign-extends
12630 : if it is negative, C2 both zero- and sign-extends. */
12631 0 : && (((nonzero_bits (a, inner_mode)
12632 0 : & ~GET_MODE_MASK (mode)) == 0
12633 0 : && const_op >= 0)
12634 : /* (A - C1) sign-extends if it is positive and 1-extends
12635 : if it is negative, C2 both sign- and 1-extends. */
12636 0 : || (num_sign_bit_copies (a, inner_mode)
12637 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12638 0 : - mode_width)
12639 0 : && const_op < 0)))
12640 0 : || ((unsigned HOST_WIDE_INT) c1
12641 0 : < HOST_WIDE_INT_1U << (mode_width - 2)
12642 : /* (A - C1) always sign-extends, like C2. */
12643 0 : && num_sign_bit_copies (a, inner_mode)
12644 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12645 0 : - (mode_width - 1))))
12646 : {
12647 0 : op0 = SUBREG_REG (op0);
12648 0 : continue;
12649 : }
12650 : }
12651 :
12652 : /* If the inner mode is narrower and we are extracting the low part,
12653 : we can treat the SUBREG as if it were a ZERO_EXTEND ... */
12654 484797 : if (paradoxical_subreg_p (op0))
12655 : {
12656 : if (WORD_REGISTER_OPERATIONS
12657 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12658 : &inner_mode)
12659 : && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD
12660 : /* On WORD_REGISTER_OPERATIONS targets the bits
12661 : beyond sub_mode aren't considered undefined,
12662 : so optimize only if it is a MEM load when MEM loads
12663 : zero extend, because then the upper bits are all zero. */
12664 : && !(MEM_P (SUBREG_REG (op0))
12665 : && load_extend_op (inner_mode) == ZERO_EXTEND))
12666 : break;
12667 : /* FALLTHROUGH to case ZERO_EXTEND */
12668 : }
12669 484797 : else if (subreg_lowpart_p (op0)
12670 453910 : && GET_MODE_CLASS (mode) == MODE_INT
12671 453910 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12672 451751 : && (code == NE || code == EQ)
12673 320228 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12674 314354 : && !paradoxical_subreg_p (op0)
12675 799151 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12676 314354 : & ~GET_MODE_MASK (mode)) == 0)
12677 : {
12678 : /* Remove outer subregs that don't do anything. */
12679 63339 : tem = gen_lowpart (inner_mode, op1);
12680 :
12681 63339 : if ((nonzero_bits (tem, inner_mode)
12682 63339 : & ~GET_MODE_MASK (mode)) == 0)
12683 : {
12684 62651 : op0 = SUBREG_REG (op0);
12685 62651 : op1 = tem;
12686 62651 : continue;
12687 : }
12688 : break;
12689 : }
12690 : else
12691 : break;
12692 :
12693 : /* FALLTHROUGH */
12694 :
12695 41877 : case ZERO_EXTEND:
12696 41877 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12697 41877 : && (unsigned_comparison_p || equality_comparison_p)
12698 41835 : && HWI_COMPUTABLE_MODE_P (mode)
12699 41835 : && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12700 41835 : && const_op >= 0
12701 41826 : && have_insn_for (COMPARE, mode))
12702 : {
12703 41826 : op0 = XEXP (op0, 0);
12704 41826 : continue;
12705 : }
12706 : break;
12707 :
12708 466612 : case PLUS:
12709 : /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12710 : this for equality comparisons due to pathological cases involving
12711 : overflows. */
12712 521144 : if (equality_comparison_p
12713 466612 : && (tem = simplify_binary_operation (MINUS, mode,
12714 : op1, XEXP (op0, 1))) != 0)
12715 : {
12716 54532 : op0 = XEXP (op0, 0);
12717 54532 : op1 = tem;
12718 54532 : continue;
12719 : }
12720 :
12721 : /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12722 412080 : if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12723 15503 : && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12724 : {
12725 0 : op0 = XEXP (XEXP (op0, 0), 0);
12726 0 : code = (code == LT ? EQ : NE);
12727 0 : continue;
12728 : }
12729 : break;
12730 :
12731 182646 : case MINUS:
12732 : /* We used to optimize signed comparisons against zero, but that
12733 : was incorrect. Unsigned comparisons against zero (GTU, LEU)
12734 : arrive here as equality comparisons, or (GEU, LTU) are
12735 : optimized away. No need to special-case them. */
12736 :
12737 : /* (eq (minus A B) C) -> (eq A (plus B C)) or
12738 : (eq B (minus A C)), whichever simplifies. We can only do
12739 : this for equality comparisons due to pathological cases involving
12740 : overflows. */
12741 215013 : if (equality_comparison_p
12742 182646 : && (tem = simplify_binary_operation (PLUS, mode,
12743 : XEXP (op0, 1), op1)) != 0)
12744 : {
12745 32367 : op0 = XEXP (op0, 0);
12746 32367 : op1 = tem;
12747 32367 : continue;
12748 : }
12749 :
12750 181872 : if (equality_comparison_p
12751 150279 : && (tem = simplify_binary_operation (MINUS, mode,
12752 : XEXP (op0, 0), op1)) != 0)
12753 : {
12754 31593 : op0 = XEXP (op0, 1);
12755 31593 : op1 = tem;
12756 31593 : continue;
12757 : }
12758 :
12759 : /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12760 : of bits in X minus 1, is one iff X > 0. */
12761 15825 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12762 489 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12763 489 : && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12764 118710 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12765 : {
12766 0 : op0 = XEXP (op0, 1);
12767 0 : code = (code == GE ? LE : GT);
12768 0 : continue;
12769 : }
12770 : break;
12771 :
12772 8861 : case XOR:
12773 : /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12774 : if C is zero or B is a constant. */
12775 8877 : if (equality_comparison_p
12776 8861 : && (tem = simplify_binary_operation (XOR, mode,
12777 : XEXP (op0, 1), op1)) != 0)
12778 : {
12779 16 : op0 = XEXP (op0, 0);
12780 16 : op1 = tem;
12781 16 : continue;
12782 : }
12783 : break;
12784 :
12785 :
12786 412045 : case IOR:
12787 : /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12788 : iff X <= 0. */
12789 7541 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12790 1257 : && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12791 412093 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12792 : {
12793 48 : op0 = XEXP (op0, 1);
12794 48 : code = (code == GE ? GT : LE);
12795 48 : continue;
12796 : }
12797 : break;
12798 :
12799 1657768 : case AND:
12800 : /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12801 : will be converted to a ZERO_EXTRACT later. */
12802 1657768 : if (const_op == 0 && equality_comparison_p
12803 1543858 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12804 61099 : && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12805 : {
12806 6871 : op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12807 : XEXP (XEXP (op0, 0), 1));
12808 6871 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12809 6871 : continue;
12810 : }
12811 :
12812 : /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12813 : zero and X is a comparison and C1 and C2 describe only bits set
12814 : in STORE_FLAG_VALUE, we can compare with X. */
12815 1650897 : if (const_op == 0 && equality_comparison_p
12816 1536987 : && mode_width <= HOST_BITS_PER_WIDE_INT
12817 1533098 : && CONST_INT_P (XEXP (op0, 1))
12818 1183677 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12819 505534 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12820 491769 : && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12821 491769 : && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12822 : {
12823 491769 : mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12824 491769 : << INTVAL (XEXP (XEXP (op0, 0), 1)));
12825 491769 : if ((~STORE_FLAG_VALUE & mask) == 0
12826 491769 : && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12827 0 : || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12828 0 : && COMPARISON_P (tem))))
12829 : {
12830 0 : op0 = XEXP (XEXP (op0, 0), 0);
12831 0 : continue;
12832 : }
12833 : }
12834 :
12835 : /* If we are doing an equality comparison of an AND of a bit equal
12836 : to the sign bit, replace this with a LT or GE comparison of
12837 : the underlying value. */
12838 1651450 : if (equality_comparison_p
12839 : && const_op == 0
12840 1536987 : && CONST_INT_P (XEXP (op0, 1))
12841 1183988 : && mode_width <= HOST_BITS_PER_WIDE_INT
12842 1650897 : && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12843 1183677 : == HOST_WIDE_INT_1U << (mode_width - 1)))
12844 : {
12845 553 : op0 = XEXP (op0, 0);
12846 553 : code = (code == EQ ? GE : LT);
12847 553 : continue;
12848 : }
12849 :
12850 : /* If this AND operation is really a ZERO_EXTEND from a narrower
12851 : mode, the constant fits within that mode, and this is either an
12852 : equality or unsigned comparison, try to do this comparison in
12853 : the narrower mode.
12854 :
12855 : Note that in:
12856 :
12857 : (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12858 : -> (ne:DI (reg:SI 4) (const_int 0))
12859 :
12860 : unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12861 : known to hold a value of the required mode the
12862 : transformation is invalid. */
12863 1666393 : if ((equality_comparison_p || unsigned_comparison_p)
12864 1634881 : && CONST_INT_P (XEXP (op0, 1))
12865 3798409 : && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12866 1277056 : & GET_MODE_MASK (mode))
12867 : + 1)) >= 0
12868 887058 : && const_op >> i == 0
12869 2537402 : && int_mode_for_size (i, 1).exists (&tmode))
12870 : {
12871 16049 : op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12872 16049 : continue;
12873 : }
12874 :
12875 : /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12876 1634295 : if (const_op == 0 && equality_comparison_p
12877 1525646 : && XEXP (op0, 1) == const1_rtx
12878 668189 : && GET_CODE (XEXP (op0, 0)) == NOT)
12879 : {
12880 6161 : op0 = simplify_and_const_int (NULL_RTX, mode,
12881 : XEXP (XEXP (op0, 0), 0), 1);
12882 6161 : code = (code == NE ? EQ : NE);
12883 6161 : continue;
12884 : }
12885 :
12886 : /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12887 : (eq (and (lshiftrt X) 1) 0).
12888 : Also handle the case where (not X) is expressed using xor. */
12889 1628134 : if (const_op == 0 && equality_comparison_p
12890 1519485 : && XEXP (op0, 1) == const1_rtx
12891 662028 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12892 : {
12893 499414 : rtx shift_op = XEXP (XEXP (op0, 0), 0);
12894 499414 : rtx shift_count = XEXP (XEXP (op0, 0), 1);
12895 :
12896 502262 : if (GET_CODE (shift_op) == NOT
12897 499414 : || (GET_CODE (shift_op) == XOR
12898 4269 : && CONST_INT_P (XEXP (shift_op, 1))
12899 2848 : && CONST_INT_P (shift_count)
12900 2848 : && HWI_COMPUTABLE_MODE_P (mode)
12901 2848 : && (UINTVAL (XEXP (shift_op, 1))
12902 : == HOST_WIDE_INT_1U
12903 2848 : << INTVAL (shift_count))))
12904 : {
12905 2848 : op0
12906 2848 : = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12907 2848 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12908 2848 : code = (code == NE ? EQ : NE);
12909 2848 : continue;
12910 : }
12911 : }
12912 : break;
12913 :
12914 47183 : case ASHIFT:
12915 : /* If we have (compare (ashift FOO N) (const_int C)) and
12916 : the high order N bits of FOO (N+1 if an inequality comparison)
12917 : are known to be zero, we can do this by comparing FOO with C
12918 : shifted right N bits so long as the low-order N bits of C are
12919 : zero. */
12920 47183 : if (CONST_INT_P (XEXP (op0, 1))
12921 43517 : && INTVAL (XEXP (op0, 1)) >= 0
12922 43517 : && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12923 : < HOST_BITS_PER_WIDE_INT)
12924 43517 : && (((unsigned HOST_WIDE_INT) const_op
12925 43517 : & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12926 : - 1)) == 0)
12927 36622 : && mode_width <= HOST_BITS_PER_WIDE_INT
12928 83775 : && (nonzero_bits (XEXP (op0, 0), mode)
12929 36592 : & ~(mask >> (INTVAL (XEXP (op0, 1))
12930 36592 : + ! equality_comparison_p))) == 0)
12931 : {
12932 : /* We must perform a logical shift, not an arithmetic one,
12933 : as we want the top N bits of C to be zero. */
12934 766 : unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12935 :
12936 766 : temp >>= INTVAL (XEXP (op0, 1));
12937 766 : op1 = gen_int_mode (temp, mode);
12938 766 : op0 = XEXP (op0, 0);
12939 766 : continue;
12940 766 : }
12941 :
12942 : /* If we are doing a sign bit comparison, it means we are testing
12943 : a particular bit. Convert it to the appropriate AND. */
12944 46417 : if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12945 1649 : && mode_width <= HOST_BITS_PER_WIDE_INT)
12946 : {
12947 3298 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12948 : (HOST_WIDE_INT_1U
12949 : << (mode_width - 1
12950 1649 : - INTVAL (XEXP (op0, 1)))));
12951 1649 : code = (code == LT ? NE : EQ);
12952 1649 : continue;
12953 : }
12954 :
12955 : /* If this an equality comparison with zero and we are shifting
12956 : the low bit to the sign bit, we can convert this to an AND of the
12957 : low-order bit. */
12958 44768 : if (const_op == 0 && equality_comparison_p
12959 14872 : && CONST_INT_P (XEXP (op0, 1))
12960 12424 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12961 : {
12962 310 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12963 310 : continue;
12964 : }
12965 : break;
12966 :
12967 36522 : case ASHIFTRT:
12968 : /* If this is an equality comparison with zero, we can do this
12969 : as a logical shift, which might be much simpler. */
12970 36522 : if (equality_comparison_p && const_op == 0
12971 26710 : && CONST_INT_P (XEXP (op0, 1)))
12972 : {
12973 51802 : op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12974 : XEXP (op0, 0),
12975 25901 : INTVAL (XEXP (op0, 1)));
12976 25901 : continue;
12977 : }
12978 :
12979 : /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12980 : do the comparison in a narrower mode. */
12981 15623 : if (! unsigned_comparison_p
12982 9368 : && CONST_INT_P (XEXP (op0, 1))
12983 8523 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12984 5600 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12985 5490 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12986 10621 : .exists (&tmode))
12987 10621 : && (((unsigned HOST_WIDE_INT) const_op
12988 5002 : + (GET_MODE_MASK (tmode) >> 1) + 1)
12989 5002 : <= GET_MODE_MASK (tmode)))
12990 : {
12991 5002 : op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12992 5002 : continue;
12993 : }
12994 :
12995 : /* Likewise if OP0 is a PLUS of a sign extension with a
12996 : constant, which is usually represented with the PLUS
12997 : between the shifts. */
12998 5619 : if (! unsigned_comparison_p
12999 4366 : && CONST_INT_P (XEXP (op0, 1))
13000 3521 : && GET_CODE (XEXP (op0, 0)) == PLUS
13001 54 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
13002 22 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
13003 2 : && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
13004 0 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13005 5619 : .exists (&tmode))
13006 5619 : && (((unsigned HOST_WIDE_INT) const_op
13007 0 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13008 0 : <= GET_MODE_MASK (tmode)))
13009 : {
13010 0 : rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
13011 0 : rtx add_const = XEXP (XEXP (op0, 0), 1);
13012 0 : rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
13013 : add_const, XEXP (op0, 1));
13014 :
13015 0 : op0 = simplify_gen_binary (PLUS, tmode,
13016 0 : gen_lowpart (tmode, inner),
13017 : new_const);
13018 0 : continue;
13019 0 : }
13020 :
13021 : /* FALLTHROUGH */
13022 126109 : case LSHIFTRT:
13023 : /* If we have (compare (xshiftrt FOO N) (const_int C)) and
13024 : the low order N bits of FOO are known to be zero, we can do this
13025 : by comparing FOO with C shifted left N bits so long as no
13026 : overflow occurs. Even if the low order N bits of FOO aren't known
13027 : to be zero, if the comparison is >= or < we can use the same
13028 : optimization and for > or <= by setting all the low
13029 : order N bits in the comparison constant. */
13030 126109 : if (CONST_INT_P (XEXP (op0, 1))
13031 121383 : && INTVAL (XEXP (op0, 1)) > 0
13032 121383 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
13033 121023 : && mode_width <= HOST_BITS_PER_WIDE_INT
13034 126109 : && (((unsigned HOST_WIDE_INT) const_op
13035 240532 : + (GET_CODE (op0) != LSHIFTRT
13036 120266 : ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
13037 : + 1)
13038 : : 0))
13039 120266 : <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
13040 : {
13041 120089 : unsigned HOST_WIDE_INT low_bits
13042 120089 : = (nonzero_bits (XEXP (op0, 0), mode)
13043 120089 : & ((HOST_WIDE_INT_1U
13044 120089 : << INTVAL (XEXP (op0, 1))) - 1));
13045 120089 : if (low_bits == 0 || !equality_comparison_p)
13046 : {
13047 : /* If the shift was logical, then we must make the condition
13048 : unsigned. */
13049 19412 : if (GET_CODE (op0) == LSHIFTRT)
13050 16769 : code = unsigned_condition (code);
13051 :
13052 19412 : const_op = (unsigned HOST_WIDE_INT) const_op
13053 19412 : << INTVAL (XEXP (op0, 1));
13054 19412 : if (low_bits != 0
13055 2946 : && (code == GT || code == GTU
13056 1026 : || code == LE || code == LEU))
13057 2878 : const_op
13058 2878 : |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
13059 19412 : op1 = GEN_INT (const_op);
13060 19412 : op0 = XEXP (op0, 0);
13061 19412 : continue;
13062 : }
13063 : }
13064 :
13065 : /* If we are using this shift to extract just the sign bit, we
13066 : can replace this with an LT or GE comparison. */
13067 106697 : if (const_op == 0
13068 98917 : && (equality_comparison_p || sign_bit_comparison_p)
13069 98881 : && CONST_INT_P (XEXP (op0, 1))
13070 94366 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13071 : {
13072 49118 : op0 = XEXP (op0, 0);
13073 49118 : code = (code == NE || code == GT ? LT : GE);
13074 49118 : continue;
13075 : }
13076 : break;
13077 :
13078 : default:
13079 : break;
13080 : }
13081 :
13082 : break;
13083 : }
13084 :
13085 : /* Now make any compound operations involved in this comparison. Then,
13086 : check for an outermost SUBREG on OP0 that is not doing anything or is
13087 : paradoxical. The latter transformation must only be performed when
13088 : it is known that the "extra" bits will be the same in op0 and op1 or
13089 : that they don't matter. There are three cases to consider:
13090 :
13091 : 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13092 : care bits and we can assume they have any convenient value. So
13093 : making the transformation is safe.
13094 :
13095 : 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13096 : In this case the upper bits of op0 are undefined. We should not make
13097 : the simplification in that case as we do not know the contents of
13098 : those bits.
13099 :
13100 : 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13101 : In that case we know those bits are zeros or ones. We must also be
13102 : sure that they are the same as the upper bits of op1.
13103 :
13104 : We can never remove a SUBREG for a non-equality comparison because
13105 : the sign bit is in a different place in the underlying object. */
13106 :
13107 24349517 : rtx_code op0_mco_code = SET;
13108 24349517 : if (op1 == const0_rtx)
13109 11578596 : op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13110 :
13111 24349517 : op0 = make_compound_operation (op0, op0_mco_code);
13112 24349517 : op1 = make_compound_operation (op1, SET);
13113 :
13114 607880 : if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13115 575895 : && is_int_mode (GET_MODE (op0), &mode)
13116 543948 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13117 24889743 : && (code == NE || code == EQ))
13118 : {
13119 284561 : if (paradoxical_subreg_p (op0))
13120 : {
13121 : /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13122 : implemented. */
13123 0 : if (REG_P (SUBREG_REG (op0)))
13124 : {
13125 0 : op0 = SUBREG_REG (op0);
13126 0 : op1 = gen_lowpart (inner_mode, op1);
13127 : }
13128 : }
13129 284561 : else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13130 284561 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13131 277645 : & ~GET_MODE_MASK (mode)) == 0)
13132 : {
13133 14054 : tem = gen_lowpart (inner_mode, op1);
13134 :
13135 14054 : if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13136 4789 : op0 = SUBREG_REG (op0), op1 = tem;
13137 : }
13138 : }
13139 :
13140 : /* We now do the opposite procedure: Some machines don't have compare
13141 : insns in all modes. If OP0's mode is an integer mode smaller than a
13142 : word and we can't do a compare in that mode, see if there is a larger
13143 : mode for which we can do the compare. There are a number of cases in
13144 : which we can use the wider mode. */
13145 :
13146 24349517 : if (is_int_mode (GET_MODE (op0), &mode)
13147 25041109 : && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13148 8949940 : && ! have_insn_for (COMPARE, mode))
13149 0 : FOR_EACH_WIDER_MODE (tmode_iter, mode)
13150 : {
13151 0 : tmode = tmode_iter.require ();
13152 0 : if (!HWI_COMPUTABLE_MODE_P (tmode))
13153 : break;
13154 0 : if (have_insn_for (COMPARE, tmode))
13155 : {
13156 0 : int zero_extended;
13157 :
13158 : /* If this is a test for negative, we can make an explicit
13159 : test of the sign bit. Test this first so we can use
13160 : a paradoxical subreg to extend OP0. */
13161 :
13162 0 : if (op1 == const0_rtx && (code == LT || code == GE)
13163 0 : && HWI_COMPUTABLE_MODE_P (mode))
13164 : {
13165 0 : unsigned HOST_WIDE_INT sign
13166 0 : = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13167 0 : op0 = simplify_gen_binary (AND, tmode,
13168 0 : gen_lowpart (tmode, op0),
13169 0 : gen_int_mode (sign, tmode));
13170 0 : code = (code == LT) ? NE : EQ;
13171 : break;
13172 : }
13173 :
13174 : /* If the only nonzero bits in OP0 and OP1 are those in the
13175 : narrower mode and this is an equality or unsigned comparison,
13176 : we can use the wider mode. Similarly for sign-extended
13177 : values, in which case it is true for all comparisons. */
13178 0 : zero_extended = ((code == EQ || code == NE
13179 0 : || code == GEU || code == GTU
13180 0 : || code == LEU || code == LTU)
13181 0 : && (nonzero_bits (op0, tmode)
13182 0 : & ~GET_MODE_MASK (mode)) == 0
13183 0 : && ((CONST_INT_P (op1)
13184 0 : || (nonzero_bits (op1, tmode)
13185 0 : & ~GET_MODE_MASK (mode)) == 0)));
13186 :
13187 0 : if (zero_extended
13188 0 : || ((num_sign_bit_copies (op0, tmode)
13189 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13190 0 : - GET_MODE_PRECISION (mode)))
13191 0 : && (num_sign_bit_copies (op1, tmode)
13192 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13193 0 : - GET_MODE_PRECISION (mode)))))
13194 : {
13195 : /* If OP0 is an AND and we don't have an AND in MODE either,
13196 : make a new AND in the proper mode. */
13197 0 : if (GET_CODE (op0) == AND
13198 0 : && !have_insn_for (AND, mode))
13199 0 : op0 = simplify_gen_binary (AND, tmode,
13200 0 : gen_lowpart (tmode,
13201 : XEXP (op0, 0)),
13202 0 : gen_lowpart (tmode,
13203 : XEXP (op0, 1)));
13204 : else
13205 : {
13206 0 : if (zero_extended)
13207 : {
13208 0 : op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13209 : op0, mode);
13210 0 : op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13211 : op1, mode);
13212 : }
13213 : else
13214 : {
13215 0 : op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13216 : op0, mode);
13217 0 : op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13218 : op1, mode);
13219 : }
13220 : break;
13221 : }
13222 : }
13223 : }
13224 : }
13225 :
13226 : /* We may have changed the comparison operands. Re-canonicalize. */
13227 24349517 : if (swap_commutative_operands_p (op0, op1))
13228 : {
13229 60252 : std::swap (op0, op1);
13230 60252 : code = swap_condition (code);
13231 : }
13232 :
13233 : /* If this machine only supports a subset of valid comparisons, see if we
13234 : can convert an unsupported one into a supported one. */
13235 24349517 : target_canonicalize_comparison (&code, &op0, &op1, 0);
13236 :
13237 24349517 : *pop0 = op0;
13238 24349517 : *pop1 = op1;
13239 :
13240 24349517 : return code;
13241 : }
13242 :
13243 : /* Utility function for record_value_for_reg. Count number of
13244 : rtxs in X. */
13245 : static int
13246 2654 : count_rtxs (rtx x)
13247 : {
13248 2654 : enum rtx_code code = GET_CODE (x);
13249 2654 : const char *fmt;
13250 2654 : int i, j, ret = 1;
13251 :
13252 2654 : if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13253 2654 : || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13254 : {
13255 83 : rtx x0 = XEXP (x, 0);
13256 83 : rtx x1 = XEXP (x, 1);
13257 :
13258 83 : if (x0 == x1)
13259 0 : return 1 + 2 * count_rtxs (x0);
13260 :
13261 83 : if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13262 83 : || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13263 0 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13264 0 : return 2 + 2 * count_rtxs (x0)
13265 0 : + count_rtxs (x == XEXP (x1, 0)
13266 0 : ? XEXP (x1, 1) : XEXP (x1, 0));
13267 :
13268 83 : if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13269 83 : || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13270 0 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13271 0 : return 2 + 2 * count_rtxs (x1)
13272 0 : + count_rtxs (x == XEXP (x0, 0)
13273 0 : ? XEXP (x0, 1) : XEXP (x0, 0));
13274 : }
13275 :
13276 2654 : fmt = GET_RTX_FORMAT (code);
13277 5953 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13278 3299 : if (fmt[i] == 'e')
13279 1564 : ret += count_rtxs (XEXP (x, i));
13280 1735 : else if (fmt[i] == 'E')
13281 208 : for (j = 0; j < XVECLEN (x, i); j++)
13282 156 : ret += count_rtxs (XVECEXP (x, i, j));
13283 :
13284 : return ret;
13285 : }
13286 :
13287 : /* Utility function for following routine. Called when X is part of a value
13288 : being stored into last_set_value. Sets last_set_table_tick
13289 : for each register mentioned. Similar to mention_regs in cse.cc */
13290 :
13291 : static void
13292 234303765 : update_table_tick (rtx x)
13293 : {
13294 234974959 : enum rtx_code code = GET_CODE (x);
13295 234974959 : const char *fmt = GET_RTX_FORMAT (code);
13296 234974959 : int i, j;
13297 :
13298 234974959 : if (code == REG)
13299 : {
13300 83701391 : unsigned int regno = REGNO (x);
13301 83701391 : unsigned int endregno = END_REGNO (x);
13302 83701391 : unsigned int r;
13303 :
13304 167513644 : for (r = regno; r < endregno; r++)
13305 : {
13306 83812253 : reg_stat_type *rsp = ®_stat[r];
13307 83812253 : rsp->last_set_table_tick = label_tick;
13308 : }
13309 :
13310 : return;
13311 : }
13312 :
13313 391080787 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13314 240603923 : if (fmt[i] == 'e')
13315 : {
13316 : /* Check for identical subexpressions. If x contains
13317 : identical subexpression we only have to traverse one of
13318 : them. */
13319 139726031 : if (i == 0 && ARITHMETIC_P (x))
13320 : {
13321 : /* Note that at this point x1 has already been
13322 : processed. */
13323 52840497 : rtx x0 = XEXP (x, 0);
13324 52840497 : rtx x1 = XEXP (x, 1);
13325 :
13326 : /* If x0 and x1 are identical then there is no need to
13327 : process x0. */
13328 52840497 : if (x0 == x1)
13329 : break;
13330 :
13331 : /* If x0 is identical to a subexpression of x1 then while
13332 : processing x1, x0 has already been processed. Thus we
13333 : are done with x. */
13334 52715126 : if (ARITHMETIC_P (x1)
13335 411877 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13336 : break;
13337 :
13338 : /* If x1 is identical to a subexpression of x0 then we
13339 : still have to process the rest of x0. */
13340 52714987 : if (ARITHMETIC_P (x0)
13341 9587535 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13342 : {
13343 671194 : update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13344 671194 : break;
13345 : }
13346 : }
13347 :
13348 138929327 : update_table_tick (XEXP (x, i));
13349 : }
13350 100877892 : else if (fmt[i] == 'E')
13351 10448370 : for (j = 0; j < XVECLEN (x, i); j++)
13352 7690318 : update_table_tick (XVECEXP (x, i, j));
13353 : }
13354 :
13355 : /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13356 : are saying that the register is clobbered and we no longer know its
13357 : value. If INSN is zero, don't update reg_stat[].last_set; this is
13358 : only permitted with VALUE also zero and is used to invalidate the
13359 : register. */
13360 :
13361 : static void
13362 114731250 : record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13363 : {
13364 114731250 : unsigned int regno = REGNO (reg);
13365 114731250 : unsigned int endregno = END_REGNO (reg);
13366 114731250 : unsigned int i;
13367 114731250 : reg_stat_type *rsp;
13368 :
13369 : /* If VALUE contains REG and we have a previous value for REG, substitute
13370 : the previous value. */
13371 114731250 : if (value && insn && reg_overlap_mentioned_p (reg, value))
13372 : {
13373 6202776 : rtx tem;
13374 :
13375 : /* Set things up so get_last_value is allowed to see anything set up to
13376 : our insn. */
13377 6202776 : subst_low_luid = DF_INSN_LUID (insn);
13378 6202776 : tem = get_last_value (reg);
13379 :
13380 : /* If TEM is simply a binary operation with two CLOBBERs as operands,
13381 : it isn't going to be useful and will take a lot of time to process,
13382 : so just use the CLOBBER. */
13383 :
13384 6202776 : if (tem)
13385 : {
13386 2455753 : if (ARITHMETIC_P (tem)
13387 2225743 : && GET_CODE (XEXP (tem, 0)) == CLOBBER
13388 1101472 : && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13389 : tem = XEXP (tem, 0);
13390 2454393 : else if (count_occurrences (value, reg, 1) >= 2)
13391 : {
13392 : /* If there are two or more occurrences of REG in VALUE,
13393 : prevent the value from growing too much. */
13394 934 : if (count_rtxs (tem) > param_max_last_value_rtl)
13395 0 : tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13396 : }
13397 :
13398 2455753 : value = replace_rtx (copy_rtx (value), reg, tem);
13399 : }
13400 : }
13401 :
13402 : /* For each register modified, show we don't know its value, that
13403 : we don't know about its bitwise content, that its value has been
13404 : updated, and that we don't know the location of the death of the
13405 : register. */
13406 229818297 : for (i = regno; i < endregno; i++)
13407 : {
13408 115087047 : rsp = ®_stat[i];
13409 :
13410 115087047 : if (insn)
13411 105703261 : rsp->last_set = insn;
13412 :
13413 115087047 : rsp->last_set_value = 0;
13414 115087047 : rsp->last_set_mode = VOIDmode;
13415 115087047 : rsp->last_set_nonzero_bits = 0;
13416 115087047 : rsp->last_set_sign_bit_copies = 0;
13417 115087047 : rsp->last_death = 0;
13418 115087047 : rsp->truncated_to_mode = VOIDmode;
13419 : }
13420 :
13421 : /* Mark registers that are being referenced in this value. */
13422 114731250 : if (value)
13423 87684120 : update_table_tick (value);
13424 :
13425 : /* Now update the status of each register being set.
13426 : If someone is using this register in this block, set this register
13427 : to invalid since we will get confused between the two lives in this
13428 : basic block. This makes using this register always invalid. In cse, we
13429 : scan the table to invalidate all entries using this register, but this
13430 : is too much work for us. */
13431 :
13432 229818297 : for (i = regno; i < endregno; i++)
13433 : {
13434 115087047 : rsp = ®_stat[i];
13435 115087047 : rsp->last_set_label = label_tick;
13436 115087047 : if (!insn
13437 105703261 : || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13438 19961184 : rsp->last_set_invalid = true;
13439 : else
13440 95125863 : rsp->last_set_invalid = false;
13441 : }
13442 :
13443 : /* The value being assigned might refer to X (like in "x++;"). In that
13444 : case, we must replace it with (clobber (const_int 0)) to prevent
13445 : infinite loops. */
13446 114731250 : rsp = ®_stat[regno];
13447 114731250 : if (value && !get_last_value_validate (&value, insn, label_tick, false))
13448 : {
13449 11227203 : value = copy_rtx (value);
13450 11227203 : if (!get_last_value_validate (&value, insn, label_tick, true))
13451 0 : value = 0;
13452 : }
13453 :
13454 : /* For the main register being modified, update the value, the mode, the
13455 : nonzero bits, and the number of sign bit copies. */
13456 :
13457 114731250 : rsp->last_set_value = value;
13458 :
13459 114731250 : if (value)
13460 : {
13461 87684120 : machine_mode mode = GET_MODE (reg);
13462 87684120 : subst_low_luid = DF_INSN_LUID (insn);
13463 87684120 : rsp->last_set_mode = mode;
13464 87684120 : if (GET_MODE_CLASS (mode) == MODE_INT
13465 87684120 : && HWI_COMPUTABLE_MODE_P (mode))
13466 66021088 : mode = nonzero_bits_mode;
13467 87684120 : rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13468 87684120 : rsp->last_set_sign_bit_copies
13469 87684120 : = num_sign_bit_copies (value, GET_MODE (reg));
13470 : }
13471 114731250 : }
13472 :
13473 : /* Called via note_stores from record_dead_and_set_regs to handle one
13474 : SET or CLOBBER in an insn. DATA is the instruction in which the
13475 : set is occurring. */
13476 :
13477 : static void
13478 137264810 : record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13479 : {
13480 137264810 : rtx_insn *record_dead_insn = (rtx_insn *) data;
13481 :
13482 137264810 : if (GET_CODE (dest) == SUBREG)
13483 5 : dest = SUBREG_REG (dest);
13484 :
13485 137264810 : if (!record_dead_insn)
13486 : {
13487 4257655 : if (REG_P (dest))
13488 4257655 : record_value_for_reg (dest, NULL, NULL_RTX);
13489 : return;
13490 : }
13491 :
13492 133007155 : if (REG_P (dest))
13493 : {
13494 : /* If we are setting the whole register, we know its value. */
13495 105527448 : if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13496 87500966 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13497 : /* We can handle a SUBREG if it's the low part, but we must be
13498 : careful with paradoxical SUBREGs on RISC architectures because
13499 : we cannot strip e.g. an extension around a load and record the
13500 : naked load since the RTL middle-end considers that the upper bits
13501 : are defined according to LOAD_EXTEND_OP. */
13502 18026482 : else if (GET_CODE (setter) == SET
13503 628760 : && GET_CODE (SET_DEST (setter)) == SUBREG
13504 616544 : && SUBREG_REG (SET_DEST (setter)) == dest
13505 982907 : && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13506 : BITS_PER_WORD)
13507 18160110 : && subreg_lowpart_p (SET_DEST (setter)))
13508 : {
13509 133628 : if (WORD_REGISTER_OPERATIONS
13510 : && word_register_operation_p (SET_SRC (setter))
13511 : && paradoxical_subreg_p (SET_DEST (setter)))
13512 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13513 133628 : else if (!partial_subreg_p (SET_DEST (setter)))
13514 121562 : record_value_for_reg (dest, record_dead_insn,
13515 121562 : gen_lowpart (GET_MODE (dest),
13516 121562 : SET_SRC (setter)));
13517 : else
13518 : {
13519 12066 : record_value_for_reg (dest, record_dead_insn,
13520 12066 : gen_lowpart (GET_MODE (dest),
13521 12066 : SET_SRC (setter)));
13522 :
13523 12066 : unsigned HOST_WIDE_INT mask;
13524 12066 : reg_stat_type *rsp = ®_stat[REGNO (dest)];
13525 12066 : mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13526 12066 : rsp->last_set_nonzero_bits |= ~mask;
13527 12066 : rsp->last_set_sign_bit_copies = 1;
13528 : }
13529 : }
13530 : /* Otherwise show that we don't know the value. */
13531 : else
13532 17892854 : record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13533 : }
13534 27479707 : else if (MEM_P (dest)
13535 : /* Ignore pushes, they clobber nothing. */
13536 27479707 : && ! push_operand (dest, GET_MODE (dest)))
13537 14131950 : mem_last_set = DF_INSN_LUID (record_dead_insn);
13538 : }
13539 :
13540 : /* Update the records of when each REG was most recently set or killed
13541 : for the things done by INSN. This is the last thing done in processing
13542 : INSN in the combiner loop.
13543 :
13544 : We update reg_stat[], in particular fields last_set, last_set_value,
13545 : last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13546 : last_death, and also the similar information mem_last_set (which insn
13547 : most recently modified memory) and last_call_luid (which insn was the
13548 : most recent subroutine call). */
13549 :
13550 : static void
13551 179458873 : record_dead_and_set_regs (rtx_insn *insn)
13552 : {
13553 179458873 : rtx link;
13554 179458873 : unsigned int i;
13555 :
13556 318408714 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13557 : {
13558 138949841 : if (REG_NOTE_KIND (link) == REG_DEAD
13559 79376774 : && REG_P (XEXP (link, 0)))
13560 : {
13561 79376774 : unsigned int regno = REGNO (XEXP (link, 0));
13562 79376774 : unsigned int endregno = END_REGNO (XEXP (link, 0));
13563 :
13564 158958551 : for (i = regno; i < endregno; i++)
13565 : {
13566 79581777 : reg_stat_type *rsp;
13567 :
13568 79581777 : rsp = ®_stat[i];
13569 79581777 : rsp->last_death = insn;
13570 : }
13571 : }
13572 59573067 : else if (REG_NOTE_KIND (link) == REG_INC)
13573 0 : record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13574 : }
13575 :
13576 179458873 : if (CALL_P (insn))
13577 : {
13578 9552110 : HARD_REG_SET callee_clobbers
13579 9552110 : = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13580 9552110 : hard_reg_set_iterator hrsi;
13581 789459548 : EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13582 : {
13583 779907438 : reg_stat_type *rsp;
13584 :
13585 : /* ??? We could try to preserve some information from the last
13586 : set of register I if the call doesn't actually clobber
13587 : (reg:last_set_mode I), which might be true for ABIs with
13588 : partial clobbers. However, it would be difficult to
13589 : update last_set_nonzero_bits and last_sign_bit_copies
13590 : to account for the part of I that actually was clobbered.
13591 : It wouldn't help much anyway, since we rarely see this
13592 : situation before RA. */
13593 779907438 : rsp = ®_stat[i];
13594 779907438 : rsp->last_set_invalid = true;
13595 779907438 : rsp->last_set = insn;
13596 779907438 : rsp->last_set_value = 0;
13597 779907438 : rsp->last_set_mode = VOIDmode;
13598 779907438 : rsp->last_set_nonzero_bits = 0;
13599 779907438 : rsp->last_set_sign_bit_copies = 0;
13600 779907438 : rsp->last_death = 0;
13601 779907438 : rsp->truncated_to_mode = VOIDmode;
13602 : }
13603 :
13604 9552110 : last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13605 :
13606 : /* We can't combine into a call pattern. Remember, though, that
13607 : the return value register is set at this LUID. We could
13608 : still replace a register with the return value from the
13609 : wrong subroutine call! */
13610 9552110 : note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13611 : }
13612 : else
13613 169906763 : note_stores (insn, record_dead_and_set_regs_1, insn);
13614 179458873 : }
13615 :
13616 : /* If a SUBREG has the promoted bit set, it is in fact a property of the
13617 : register present in the SUBREG, so for each such SUBREG go back and
13618 : adjust nonzero and sign bit information of the registers that are
13619 : known to have some zero/sign bits set.
13620 :
13621 : This is needed because when combine blows the SUBREGs away, the
13622 : information on zero/sign bits is lost and further combines can be
13623 : missed because of that. */
13624 :
13625 : static void
13626 6610 : record_promoted_value (rtx_insn *insn, rtx subreg)
13627 : {
13628 6610 : struct insn_link *links;
13629 6610 : rtx set;
13630 6610 : unsigned int regno = REGNO (SUBREG_REG (subreg));
13631 6610 : machine_mode mode = GET_MODE (subreg);
13632 :
13633 6610 : if (!HWI_COMPUTABLE_MODE_P (mode))
13634 : return;
13635 :
13636 7373 : for (links = LOG_LINKS (insn); links;)
13637 : {
13638 6306 : reg_stat_type *rsp;
13639 :
13640 6306 : insn = links->insn;
13641 6306 : set = single_set (insn);
13642 :
13643 6306 : if (! set || !REG_P (SET_DEST (set))
13644 6302 : || REGNO (SET_DEST (set)) != regno
13645 11991 : || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13646 : {
13647 621 : links = links->next;
13648 621 : continue;
13649 : }
13650 :
13651 5685 : rsp = ®_stat[regno];
13652 5685 : if (rsp->last_set == insn)
13653 : {
13654 5685 : if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13655 5685 : rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13656 : }
13657 :
13658 5685 : if (REG_P (SET_SRC (set)))
13659 : {
13660 142 : regno = REGNO (SET_SRC (set));
13661 142 : links = LOG_LINKS (insn);
13662 : }
13663 : else
13664 : break;
13665 : }
13666 : }
13667 :
13668 : /* Check if X, a register, is known to contain a value already
13669 : truncated to MODE. In this case we can use a subreg to refer to
13670 : the truncated value even though in the generic case we would need
13671 : an explicit truncation. */
13672 :
13673 : static bool
13674 0 : reg_truncated_to_mode (machine_mode mode, const_rtx x)
13675 : {
13676 0 : reg_stat_type *rsp = ®_stat[REGNO (x)];
13677 0 : machine_mode truncated = rsp->truncated_to_mode;
13678 :
13679 0 : if (truncated == 0
13680 0 : || rsp->truncation_label < label_tick_ebb_start)
13681 : return false;
13682 0 : if (!partial_subreg_p (mode, truncated))
13683 : return true;
13684 0 : if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13685 : return true;
13686 : return false;
13687 : }
13688 :
13689 : /* If X is a hard reg or a subreg record the mode that the register is
13690 : accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13691 : able to turn a truncate into a subreg using this information. Return true
13692 : if traversing X is complete. */
13693 :
13694 : static bool
13695 201443293 : record_truncated_value (rtx x)
13696 : {
13697 201443293 : machine_mode truncated_mode;
13698 201443293 : reg_stat_type *rsp;
13699 :
13700 201443293 : if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13701 : {
13702 1874642 : machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13703 1874642 : truncated_mode = GET_MODE (x);
13704 :
13705 1874642 : if (!partial_subreg_p (truncated_mode, original_mode))
13706 : return true;
13707 :
13708 1117203 : truncated_mode = GET_MODE (x);
13709 1117203 : if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13710 : return true;
13711 :
13712 0 : x = SUBREG_REG (x);
13713 0 : }
13714 : /* ??? For hard-regs we now record everything. We might be able to
13715 : optimize this using last_set_mode. */
13716 199568651 : else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13717 21219316 : truncated_mode = GET_MODE (x);
13718 : else
13719 : return false;
13720 :
13721 21219316 : rsp = ®_stat[REGNO (x)];
13722 21219316 : if (rsp->truncated_to_mode == 0
13723 9856551 : || rsp->truncation_label < label_tick_ebb_start
13724 29800593 : || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13725 : {
13726 12638677 : rsp->truncated_to_mode = truncated_mode;
13727 12638677 : rsp->truncation_label = label_tick;
13728 : }
13729 :
13730 : return true;
13731 : }
13732 :
13733 : /* Callback for note_uses. Find hardregs and subregs of pseudos and
13734 : the modes they are used in. This can help turning TRUNCATEs into
13735 : SUBREGs. */
13736 :
13737 : static void
13738 77113904 : record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13739 : {
13740 77113904 : subrtx_var_iterator::array_type array;
13741 278557197 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13742 201443293 : if (record_truncated_value (*iter))
13743 23093958 : iter.skip_subrtxes ();
13744 77113904 : }
13745 :
13746 : /* Scan X for promoted SUBREGs. For each one found,
13747 : note what it implies to the registers used in it. */
13748 :
13749 : static void
13750 366847842 : check_promoted_subreg (rtx_insn *insn, rtx x)
13751 : {
13752 366847842 : if (GET_CODE (x) == SUBREG
13753 2265116 : && SUBREG_PROMOTED_VAR_P (x)
13754 366854452 : && REG_P (SUBREG_REG (x)))
13755 6610 : record_promoted_value (insn, x);
13756 : else
13757 : {
13758 366841232 : const char *format = GET_RTX_FORMAT (GET_CODE (x));
13759 366841232 : int i, j;
13760 :
13761 882868376 : for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13762 516027144 : switch (format[i])
13763 : {
13764 274316625 : case 'e':
13765 274316625 : check_promoted_subreg (insn, XEXP (x, i));
13766 274316625 : break;
13767 11955521 : case 'V':
13768 11955521 : case 'E':
13769 11955521 : if (XVEC (x, i) != 0)
13770 37171279 : for (j = 0; j < XVECLEN (x, i); j++)
13771 25215758 : check_promoted_subreg (insn, XVECEXP (x, i, j));
13772 : break;
13773 : }
13774 : }
13775 366847842 : }
13776 :
13777 : /* Verify that all the registers and memory references mentioned in *LOC are
13778 : still valid. *LOC was part of a value set in INSN when label_tick was
13779 : equal to TICK. Return false if some are not. If REPLACE is true, replace
13780 : the invalid references with (clobber (const_int 0)) and return true. This
13781 : replacement is useful because we often can get useful information about
13782 : the form of a value (e.g., if it was produced by a shift that always
13783 : produces -1 or 0) even though we don't know exactly what registers it
13784 : was produced from. */
13785 :
13786 : static bool
13787 483305040 : get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13788 : {
13789 483305517 : rtx x = *loc;
13790 483305517 : const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13791 483305517 : int len = GET_RTX_LENGTH (GET_CODE (x));
13792 483305517 : int i, j;
13793 :
13794 483305517 : if (REG_P (x))
13795 : {
13796 161960274 : unsigned int regno = REGNO (x);
13797 161960274 : unsigned int endregno = END_REGNO (x);
13798 161960274 : unsigned int j;
13799 :
13800 299788169 : for (j = regno; j < endregno; j++)
13801 : {
13802 161985759 : reg_stat_type *rsp = ®_stat[j];
13803 161985759 : if (rsp->last_set_invalid
13804 : /* If this is a pseudo-register that was only set once and not
13805 : live at the beginning of the function, it is always valid. */
13806 268908632 : || (! (regno >= FIRST_PSEUDO_REGISTER
13807 122766210 : && regno < reg_n_sets_max
13808 122744143 : && REG_N_SETS (regno) == 1
13809 213845746 : && (!REGNO_REG_SET_P
13810 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13811 : regno)))
13812 31110350 : && rsp->last_set_label > tick))
13813 : {
13814 24157864 : if (replace)
13815 12470589 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13816 : return replace;
13817 : }
13818 : }
13819 :
13820 : return true;
13821 : }
13822 : /* If this is a memory reference, make sure that there were no stores after
13823 : it that might have clobbered the value. We don't have alias info, so we
13824 : assume any store invalidates it. Moreover, we only have local UIDs, so
13825 : we also assume that there were stores in the intervening basic blocks. */
13826 35378250 : else if (MEM_P (x) && !MEM_READONLY_P (x)
13827 354603982 : && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13828 : {
13829 7987948 : if (replace)
13830 3996949 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13831 : return replace;
13832 : }
13833 :
13834 783882132 : for (i = 0; i < len; i++)
13835 : {
13836 482470488 : if (fmt[i] == 'e')
13837 : {
13838 : /* Check for identical subexpressions. If x contains
13839 : identical subexpression we only have to traverse one of
13840 : them. */
13841 294981344 : if (i == 1 && ARITHMETIC_P (x))
13842 : {
13843 : /* Note that at this point x0 has already been checked
13844 : and found valid. */
13845 105640004 : rtx x0 = XEXP (x, 0);
13846 105640004 : rtx x1 = XEXP (x, 1);
13847 :
13848 : /* If x0 and x1 are identical then x is also valid. */
13849 105640004 : if (x0 == x1)
13850 : return true;
13851 :
13852 : /* If x1 is identical to a subexpression of x0 then
13853 : while checking x0, x1 has already been checked. Thus
13854 : it is valid and so as x. */
13855 105242670 : if (ARITHMETIC_P (x0)
13856 19927868 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13857 : return true;
13858 :
13859 : /* If x0 is identical to a subexpression of x1 then x is
13860 : valid iff the rest of x1 is valid. */
13861 103225575 : if (ARITHMETIC_P (x1)
13862 1261899 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13863 477 : return
13864 477 : get_last_value_validate (&XEXP (x1,
13865 : x0 == XEXP (x1, 0) ? 1 : 0),
13866 477 : insn, tick, replace);
13867 : }
13868 :
13869 292566438 : if (!get_last_value_validate (&XEXP (x, i), insn, tick, replace))
13870 : return false;
13871 : }
13872 187489144 : else if (fmt[i] == 'E')
13873 34136802 : for (j = 0; j < XVECLEN (x, i); j++)
13874 27028544 : if (!get_last_value_validate (&XVECEXP (x, i, j),
13875 : insn, tick, replace))
13876 : return false;
13877 : }
13878 :
13879 : /* If we haven't found a reason for it to be invalid, it is valid. */
13880 : return true;
13881 : }
13882 :
13883 : /* Get the last value assigned to X, if known. Some registers
13884 : in the value may be replaced with (clobber (const_int 0)) if their value
13885 : is known longer known reliably. */
13886 :
13887 : static rtx
13888 234739775 : get_last_value (const_rtx x)
13889 : {
13890 234739775 : unsigned int regno;
13891 234739775 : rtx value;
13892 234739775 : reg_stat_type *rsp;
13893 :
13894 : /* If this is a non-paradoxical SUBREG, get the value of its operand and
13895 : then convert it to the desired mode. If this is a paradoxical SUBREG,
13896 : we cannot predict what values the "extra" bits might have. */
13897 234739775 : if (GET_CODE (x) == SUBREG
13898 13979466 : && subreg_lowpart_p (x)
13899 13470463 : && !paradoxical_subreg_p (x)
13900 243338069 : && (value = get_last_value (SUBREG_REG (x))) != 0)
13901 4376080 : return gen_lowpart (GET_MODE (x), value);
13902 :
13903 230363695 : if (!REG_P (x))
13904 : return 0;
13905 :
13906 199433450 : regno = REGNO (x);
13907 199433450 : rsp = ®_stat[regno];
13908 199433450 : value = rsp->last_set_value;
13909 :
13910 : /* If we don't have a value, or if it isn't for this basic block and
13911 : it's either a hard register, set more than once, or it's a live
13912 : at the beginning of the function, return 0.
13913 :
13914 : Because if it's not live at the beginning of the function then the reg
13915 : is always set before being used (is never used without being set).
13916 : And, if it's set only once, and it's always set before use, then all
13917 : uses must have the same last value, even if it's not from this basic
13918 : block. */
13919 :
13920 199433450 : if (value == 0
13921 199433450 : || (rsp->last_set_label < label_tick_ebb_start
13922 75707750 : && (regno < FIRST_PSEUDO_REGISTER
13923 74848738 : || regno >= reg_n_sets_max
13924 74848738 : || REG_N_SETS (regno) != 1
13925 16778546 : || REGNO_REG_SET_P
13926 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13927 : return 0;
13928 :
13929 : /* If the value was set in a later insn than the ones we are processing,
13930 : we can't use it even if the register was only set once. */
13931 80410166 : if (rsp->last_set_label == label_tick
13932 80410166 : && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13933 : return 0;
13934 :
13935 : /* If fewer bits were set than what we are asked for now, we cannot use
13936 : the value. */
13937 60349086 : if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13938 60349086 : GET_MODE_PRECISION (GET_MODE (x))))
13939 : return 0;
13940 :
13941 : /* If the value has all its registers valid, return it. */
13942 60347664 : if (get_last_value_validate (&value, rsp->last_set,
13943 : rsp->last_set_label, false))
13944 55896593 : return value;
13945 :
13946 : /* Otherwise, make a copy and replace any invalid register with
13947 : (clobber (const_int 0)). If that fails for some reason, return 0. */
13948 :
13949 4451071 : value = copy_rtx (value);
13950 4451071 : if (get_last_value_validate (&value, rsp->last_set,
13951 : rsp->last_set_label, true))
13952 4451071 : return value;
13953 :
13954 : return 0;
13955 : }
13956 :
13957 : /* Define three variables used for communication between the following
13958 : routines. */
13959 :
13960 : static unsigned int reg_dead_regno, reg_dead_endregno;
13961 : static int reg_dead_flag;
13962 : rtx reg_dead_reg;
13963 :
13964 : /* Function called via note_stores from reg_dead_at_p.
13965 :
13966 : If DEST is within [reg_dead_regno, reg_dead_endregno), set
13967 : reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13968 :
13969 : static void
13970 627629 : reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13971 : {
13972 627629 : unsigned int regno, endregno;
13973 :
13974 627629 : if (!REG_P (dest))
13975 : return;
13976 :
13977 575473 : regno = REGNO (dest);
13978 575473 : endregno = END_REGNO (dest);
13979 575473 : if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13980 272002 : reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13981 : }
13982 :
13983 : /* Return true if REG is known to be dead at INSN.
13984 :
13985 : We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13986 : referencing REG, it is dead. If we hit a SET referencing REG, it is
13987 : live. Otherwise, see if it is live or dead at the start of the basic
13988 : block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13989 : must be assumed to be always live. */
13990 :
13991 : static bool
13992 1624823 : reg_dead_at_p (rtx reg, rtx_insn *insn)
13993 : {
13994 1624823 : basic_block block;
13995 1624823 : unsigned int i;
13996 :
13997 : /* Set variables for reg_dead_at_p_1. */
13998 1624823 : reg_dead_regno = REGNO (reg);
13999 1624823 : reg_dead_endregno = END_REGNO (reg);
14000 1624823 : reg_dead_reg = reg;
14001 :
14002 1624823 : reg_dead_flag = 0;
14003 :
14004 : /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
14005 : we allow the machine description to decide whether use-and-clobber
14006 : patterns are OK. */
14007 1624823 : if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
14008 : {
14009 3249646 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14010 1624823 : if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
14011 : return false;
14012 : }
14013 :
14014 : /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
14015 : beginning of basic block. */
14016 1624823 : block = BLOCK_FOR_INSN (insn);
14017 769021 : for (;;)
14018 : {
14019 2393844 : if (INSN_P (insn))
14020 : {
14021 2244146 : if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
14022 : return true;
14023 :
14024 813550 : note_stores (insn, reg_dead_at_p_1, NULL);
14025 813550 : if (reg_dead_flag)
14026 136001 : return reg_dead_flag == 1 ? 1 : 0;
14027 :
14028 677549 : if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
14029 : return true;
14030 : }
14031 :
14032 798493 : if (insn == BB_HEAD (block))
14033 : break;
14034 :
14035 769021 : insn = PREV_INSN (insn);
14036 : }
14037 :
14038 : /* Look at live-in sets for the basic block that we were in. */
14039 58944 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14040 29472 : if (REGNO_REG_SET_P (df_get_live_in (block), i))
14041 : return false;
14042 :
14043 : return true;
14044 : }
14045 :
14046 : /* Note hard registers in X that are used. */
14047 :
14048 : static void
14049 293487080 : mark_used_regs_combine (rtx x)
14050 : {
14051 339080447 : RTX_CODE code = GET_CODE (x);
14052 339080447 : unsigned int regno;
14053 339080447 : int i;
14054 :
14055 339080447 : switch (code)
14056 : {
14057 : case LABEL_REF:
14058 : case SYMBOL_REF:
14059 : case CONST:
14060 : CASE_CONST_ANY:
14061 : case PC:
14062 : case ADDR_VEC:
14063 : case ADDR_DIFF_VEC:
14064 : case ASM_INPUT:
14065 : return;
14066 :
14067 7487623 : case CLOBBER:
14068 : /* If we are clobbering a MEM, mark any hard registers inside the
14069 : address as used. */
14070 7487623 : if (MEM_P (XEXP (x, 0)))
14071 5485 : mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
14072 : return;
14073 :
14074 77102948 : case REG:
14075 77102948 : regno = REGNO (x);
14076 : /* A hard reg in a wide mode may really be multiple registers.
14077 : If so, mark all of them just like the first. */
14078 77102948 : if (regno < FIRST_PSEUDO_REGISTER)
14079 : {
14080 : /* None of this applies to the stack, frame or arg pointers. */
14081 9185257 : if (regno == STACK_POINTER_REGNUM
14082 9185257 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14083 : && regno == HARD_FRAME_POINTER_REGNUM)
14084 8251002 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14085 1107542 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14086 7143460 : || regno == FRAME_POINTER_REGNUM)
14087 : return;
14088 :
14089 1749344 : add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
14090 : }
14091 : return;
14092 :
14093 45587882 : case SET:
14094 45587882 : {
14095 : /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14096 : the address. */
14097 45587882 : rtx testreg = SET_DEST (x);
14098 :
14099 45587882 : while (GET_CODE (testreg) == SUBREG
14100 45603242 : || GET_CODE (testreg) == ZERO_EXTRACT
14101 91521613 : || GET_CODE (testreg) == STRICT_LOW_PART)
14102 338209 : testreg = XEXP (testreg, 0);
14103 :
14104 45587882 : if (MEM_P (testreg))
14105 4855988 : mark_used_regs_combine (XEXP (testreg, 0));
14106 :
14107 45587882 : mark_used_regs_combine (SET_SRC (x));
14108 : }
14109 45587882 : return;
14110 :
14111 135482493 : default:
14112 135482493 : break;
14113 : }
14114 :
14115 : /* Recursively scan the operands of this expression. */
14116 :
14117 135482493 : {
14118 135482493 : const char *fmt = GET_RTX_FORMAT (code);
14119 :
14120 392987707 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14121 : {
14122 257505214 : if (fmt[i] == 'e')
14123 208614814 : mark_used_regs_combine (XEXP (x, i));
14124 48890400 : else if (fmt[i] == 'E')
14125 : {
14126 : int j;
14127 :
14128 67223388 : for (j = 0; j < XVECLEN (x, i); j++)
14129 46658125 : mark_used_regs_combine (XVECEXP (x, i, j));
14130 : }
14131 : }
14132 : }
14133 : }
14134 :
14135 : /* Remove register number REGNO from the dead registers list of INSN.
14136 :
14137 : Return the note used to record the death, if there was one. */
14138 :
14139 : rtx
14140 3183759 : remove_death (unsigned int regno, rtx_insn *insn)
14141 : {
14142 3183759 : rtx note = find_regno_note (insn, REG_DEAD, regno);
14143 :
14144 3183759 : if (note)
14145 517880 : remove_note (insn, note);
14146 :
14147 3183759 : return note;
14148 : }
14149 :
14150 : /* For each register (hardware or pseudo) used within expression X, if its
14151 : death is in an instruction with luid between FROM_LUID (inclusive) and
14152 : TO_INSN (exclusive), put a REG_DEAD note for that register in the
14153 : list headed by PNOTES.
14154 :
14155 : That said, don't move registers killed by maybe_kill_insn.
14156 :
14157 : This is done when X is being merged by combination into TO_INSN. These
14158 : notes will then be distributed as needed. */
14159 :
14160 : static void
14161 24506158 : move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14162 : rtx *pnotes)
14163 : {
14164 25047247 : const char *fmt;
14165 25047247 : int len, i;
14166 25047247 : enum rtx_code code = GET_CODE (x);
14167 :
14168 25047247 : if (code == REG)
14169 : {
14170 6205065 : unsigned int regno = REGNO (x);
14171 6205065 : rtx_insn *where_dead = reg_stat[regno].last_death;
14172 :
14173 : /* If we do not know where the register died, it may still die between
14174 : FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14175 6205065 : if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14176 : {
14177 3371682 : rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14178 3371682 : while (insn
14179 5046906 : && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14180 9352160 : && DF_INSN_LUID (insn) >= from_luid)
14181 : {
14182 2279152 : if (dead_or_set_regno_p (insn, regno))
14183 : {
14184 572196 : if (find_regno_note (insn, REG_DEAD, regno))
14185 6205065 : where_dead = insn;
14186 : break;
14187 : }
14188 :
14189 1706956 : insn = prev_real_nondebug_insn (insn);
14190 : }
14191 : }
14192 :
14193 : /* Don't move the register if it gets killed in between from and to. */
14194 146202 : if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14195 6248508 : && ! reg_referenced_p (x, maybe_kill_insn))
14196 : return;
14197 :
14198 6161622 : if (where_dead
14199 3192361 : && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14200 3032995 : && DF_INSN_LUID (where_dead) >= from_luid
14201 9194396 : && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14202 : {
14203 2740660 : rtx note = remove_death (regno, where_dead);
14204 :
14205 : /* It is possible for the call above to return 0. This can occur
14206 : when last_death points to I2 or I1 that we combined with.
14207 : In that case make a new note.
14208 :
14209 : We must also check for the case where X is a hard register
14210 : and NOTE is a death note for a range of hard registers
14211 : including X. In that case, we must put REG_DEAD notes for
14212 : the remaining registers in place of NOTE. */
14213 :
14214 2740660 : if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14215 2740660 : && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14216 : {
14217 0 : unsigned int deadregno = REGNO (XEXP (note, 0));
14218 0 : unsigned int deadend = END_REGNO (XEXP (note, 0));
14219 0 : unsigned int ourend = END_REGNO (x);
14220 0 : unsigned int i;
14221 :
14222 0 : for (i = deadregno; i < deadend; i++)
14223 0 : if (i < regno || i >= ourend)
14224 0 : add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14225 : }
14226 :
14227 : /* If we didn't find any note, or if we found a REG_DEAD note that
14228 : covers only part of the given reg, and we have a multi-reg hard
14229 : register, then to be safe we must check for REG_DEAD notes
14230 : for each register other than the first. They could have
14231 : their own REG_DEAD notes lying around. */
14232 2740660 : else if ((note == 0
14233 : || (note != 0
14234 74826 : && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14235 74826 : GET_MODE (x))))
14236 2665834 : && regno < FIRST_PSEUDO_REGISTER
14237 3077288 : && REG_NREGS (x) > 1)
14238 : {
14239 0 : unsigned int ourend = END_REGNO (x);
14240 0 : unsigned int i, offset;
14241 0 : rtx oldnotes = 0;
14242 :
14243 0 : if (note)
14244 0 : offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14245 : else
14246 : offset = 1;
14247 :
14248 0 : for (i = regno + offset; i < ourend; i++)
14249 0 : move_deaths (regno_reg_rtx[i],
14250 : maybe_kill_insn, from_luid, to_insn, &oldnotes);
14251 : }
14252 :
14253 2740660 : if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14254 : {
14255 74802 : XEXP (note, 1) = *pnotes;
14256 74802 : *pnotes = note;
14257 : }
14258 : else
14259 2665858 : *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14260 : }
14261 :
14262 : return;
14263 : }
14264 :
14265 18842182 : else if (GET_CODE (x) == SET)
14266 : {
14267 4245744 : rtx dest = SET_DEST (x);
14268 :
14269 4245744 : move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14270 :
14271 : /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14272 : that accesses one word of a multi-word item, some
14273 : piece of everything register in the expression is used by
14274 : this insn, so remove any old death. */
14275 : /* ??? So why do we test for equality of the sizes? */
14276 :
14277 4245744 : if (GET_CODE (dest) == ZERO_EXTRACT
14278 4245307 : || GET_CODE (dest) == STRICT_LOW_PART
14279 8489319 : || (GET_CODE (dest) == SUBREG
14280 78240 : && !read_modify_subreg_p (dest)))
14281 : {
14282 : move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14283 : return;
14284 : }
14285 :
14286 : /* If this is some other SUBREG, we know it replaces the entire
14287 : value, so use that as the destination. */
14288 4183227 : if (GET_CODE (dest) == SUBREG)
14289 17892 : dest = SUBREG_REG (dest);
14290 :
14291 : /* If this is a MEM, adjust deaths of anything used in the address.
14292 : For a REG (the only other possibility), the entire value is
14293 : being replaced so the old value is not used in this insn. */
14294 :
14295 4183227 : if (MEM_P (dest))
14296 478572 : move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14297 : to_insn, pnotes);
14298 : return;
14299 : }
14300 :
14301 14596438 : else if (GET_CODE (x) == CLOBBER)
14302 : return;
14303 :
14304 13971160 : len = GET_RTX_LENGTH (code);
14305 13971160 : fmt = GET_RTX_FORMAT (code);
14306 :
14307 36413756 : for (i = 0; i < len; i++)
14308 : {
14309 22442596 : if (fmt[i] == 'E')
14310 : {
14311 1015918 : int j;
14312 3613463 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14313 2597545 : move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14314 : to_insn, pnotes);
14315 : }
14316 21426678 : else if (fmt[i] == 'e')
14317 13491894 : move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14318 : }
14319 : }
14320 :
14321 : /* Return true if X is the target of a bit-field assignment in BODY, the
14322 : pattern of an insn. X must be a REG. */
14323 :
14324 : static bool
14325 4784291 : reg_bitfield_target_p (rtx x, rtx body)
14326 : {
14327 4784291 : int i;
14328 :
14329 4784291 : if (GET_CODE (body) == SET)
14330 : {
14331 3480177 : rtx dest = SET_DEST (body);
14332 3480177 : rtx target;
14333 3480177 : unsigned int regno, tregno, endregno, endtregno;
14334 :
14335 3480177 : if (GET_CODE (dest) == ZERO_EXTRACT)
14336 428 : target = XEXP (dest, 0);
14337 3479749 : else if (GET_CODE (dest) == STRICT_LOW_PART)
14338 1994 : target = SUBREG_REG (XEXP (dest, 0));
14339 : else
14340 : return false;
14341 :
14342 2422 : if (GET_CODE (target) == SUBREG)
14343 221 : target = SUBREG_REG (target);
14344 :
14345 2422 : if (!REG_P (target))
14346 : return false;
14347 :
14348 2343 : tregno = REGNO (target), regno = REGNO (x);
14349 2343 : if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14350 2333 : return target == x;
14351 :
14352 10 : endtregno = end_hard_regno (GET_MODE (target), tregno);
14353 10 : endregno = end_hard_regno (GET_MODE (x), regno);
14354 :
14355 10 : return endregno > tregno && regno < endtregno;
14356 : }
14357 :
14358 1304114 : else if (GET_CODE (body) == PARALLEL)
14359 1962032 : for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14360 1322111 : if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14361 : return true;
14362 :
14363 : return false;
14364 : }
14365 :
14366 : /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14367 : as appropriate. I3 and I2 are the insns resulting from the combination
14368 : insns including FROM (I2 may be zero).
14369 :
14370 : ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14371 : not need REG_DEAD notes because they are being substituted for. This
14372 : saves searching in the most common cases.
14373 :
14374 : Each note in the list is either ignored or placed on some insns, depending
14375 : on the type of note. */
14376 :
14377 : static void
14378 9954542 : distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14379 : rtx elim_i2, rtx elim_i1, rtx elim_i0)
14380 : {
14381 9954542 : rtx note, next_note;
14382 9954542 : rtx tem_note;
14383 9954542 : rtx_insn *tem_insn;
14384 :
14385 23073392 : for (note = notes; note; note = next_note)
14386 : {
14387 13118850 : rtx_insn *place = 0, *place2 = 0;
14388 :
14389 13118850 : next_note = XEXP (note, 1);
14390 13118850 : switch (REG_NOTE_KIND (note))
14391 : {
14392 : case REG_BR_PROB:
14393 : case REG_BR_PRED:
14394 : /* Doesn't matter much where we put this, as long as it's somewhere.
14395 : It is preferable to keep these notes on branches, which is most
14396 : likely to be i3. */
14397 : place = i3;
14398 : break;
14399 :
14400 0 : case REG_NON_LOCAL_GOTO:
14401 0 : if (JUMP_P (i3))
14402 : place = i3;
14403 : else
14404 : {
14405 0 : gcc_assert (i2 && JUMP_P (i2));
14406 : place = i2;
14407 : }
14408 : break;
14409 :
14410 21250 : case REG_EH_REGION:
14411 21250 : {
14412 : /* The landing pad handling needs to be kept in sync with the
14413 : prerequisite checking in try_combine. */
14414 21250 : int lp_nr = INTVAL (XEXP (note, 0));
14415 : /* A REG_EH_REGION note transferring control can only ever come
14416 : from i3. */
14417 21250 : if (lp_nr > 0)
14418 11632 : gcc_assert (from_insn == i3);
14419 : /* We are making sure there is a single effective REG_EH_REGION
14420 : note and it's valid to put it on i3. */
14421 21250 : if (!insn_could_throw_p (from_insn)
14422 21250 : && !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14423 : /* Throw away stray notes on insns that can never throw or
14424 : make a nonlocal goto. */
14425 : ;
14426 : else
14427 : {
14428 21173 : if (CALL_P (i3))
14429 : place = i3;
14430 : else
14431 : {
14432 2084 : gcc_assert (cfun->can_throw_non_call_exceptions);
14433 : /* If i3 can still trap preserve the note, otherwise we've
14434 : combined things such that we can now prove that the
14435 : instructions can't trap. Drop the note in this case. */
14436 2084 : if (may_trap_p (i3))
14437 : place = i3;
14438 : }
14439 : }
14440 : break;
14441 : }
14442 :
14443 126642 : case REG_ARGS_SIZE:
14444 : /* ??? How to distribute between i3-i1. Assume i3 contains the
14445 : entire adjustment. Assert i3 contains at least some adjust. */
14446 126642 : if (!noop_move_p (i3))
14447 : {
14448 126641 : poly_int64 old_size, args_size = get_args_size (note);
14449 : /* fixup_args_size_notes looks at REG_NORETURN note,
14450 : so ensure the note is placed there first. */
14451 126641 : if (CALL_P (i3))
14452 : {
14453 : rtx *np;
14454 1639 : for (np = &next_note; *np; np = &XEXP (*np, 1))
14455 20 : if (REG_NOTE_KIND (*np) == REG_NORETURN)
14456 : {
14457 9 : rtx n = *np;
14458 9 : *np = XEXP (n, 1);
14459 9 : XEXP (n, 1) = REG_NOTES (i3);
14460 9 : REG_NOTES (i3) = n;
14461 9 : break;
14462 : }
14463 : }
14464 126641 : old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14465 : /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14466 : REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14467 126641 : gcc_assert (maybe_ne (old_size, args_size)
14468 : || (CALL_P (i3)
14469 : && !ACCUMULATE_OUTGOING_ARGS
14470 : && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14471 : }
14472 : break;
14473 :
14474 80310 : case REG_NORETURN:
14475 80310 : case REG_SETJMP:
14476 80310 : case REG_TM:
14477 80310 : case REG_CALL_DECL:
14478 80310 : case REG_UNTYPED_CALL:
14479 80310 : case REG_CALL_NOCF_CHECK:
14480 : /* These notes must remain with the call. It should not be
14481 : possible for both I2 and I3 to be a call. */
14482 80310 : if (CALL_P (i3))
14483 : place = i3;
14484 : else
14485 : {
14486 0 : gcc_assert (i2 && CALL_P (i2));
14487 : place = i2;
14488 : }
14489 : break;
14490 :
14491 1963798 : case REG_UNUSED:
14492 : /* Any clobbers for i3 may still exist, and so we must process
14493 : REG_UNUSED notes from that insn.
14494 :
14495 : Any clobbers from i2 or i1 can only exist if they were added by
14496 : recog_for_combine. In that case, recog_for_combine created the
14497 : necessary REG_UNUSED notes. Trying to keep any original
14498 : REG_UNUSED notes from these insns can cause incorrect output
14499 : if it is for the same register as the original i3 dest.
14500 : In that case, we will notice that the register is set in i3,
14501 : and then add a REG_UNUSED note for the destination of i3, which
14502 : is wrong. However, it is possible to have REG_UNUSED notes from
14503 : i2 or i1 for register which were both used and clobbered, so
14504 : we keep notes from i2 or i1 if they will turn into REG_DEAD
14505 : notes. */
14506 :
14507 : /* If this register is set or clobbered between FROM_INSN and I3,
14508 : we should not create a note for it. */
14509 1963798 : if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14510 : break;
14511 :
14512 : /* If this register is set or clobbered in I3, put the note there
14513 : unless there is one already. */
14514 1877123 : if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14515 : {
14516 1108675 : if (from_insn != i3)
14517 : break;
14518 :
14519 649221 : if (! (REG_P (XEXP (note, 0))
14520 649221 : ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14521 0 : : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14522 : place = i3;
14523 : }
14524 : /* Otherwise, if this register is used by I3, then this register
14525 : now dies here, so we must put a REG_DEAD note here unless there
14526 : is one already. */
14527 768448 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14528 : {
14529 7511 : if (! (REG_P (XEXP (note, 0))
14530 7511 : ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
14531 0 : : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14532 : {
14533 7275 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14534 7275 : place = i3;
14535 : }
14536 : }
14537 :
14538 : /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14539 : but we can't tell which at this point. We must reset any
14540 : expectations we had about the value that was previously
14541 : stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14542 : and, if appropriate, restore its previous value, but we
14543 : don't have enough information for that at this point. */
14544 : else
14545 : {
14546 760937 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14547 :
14548 : /* Otherwise, if this register is now referenced in i2
14549 : then the register used to be modified in one of the
14550 : original insns. If it was i3 (say, in an unused
14551 : parallel), it's now completely gone, so the note can
14552 : be discarded. But if it was modified in i2, i1 or i0
14553 : and we still reference it in i2, then we're
14554 : referencing the previous value, and since the
14555 : register was modified and REG_UNUSED, we know that
14556 : the previous value is now dead. So, if we only
14557 : reference the register in i2, we change the note to
14558 : REG_DEAD, to reflect the previous value. However, if
14559 : we're also setting or clobbering the register as
14560 : scratch, we know (because the register was not
14561 : referenced in i3) that it's unused, just as it was
14562 : unused before, and we place the note in i2. */
14563 18741 : if (from_insn != i3 && i2 && INSN_P (i2)
14564 779678 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14565 : {
14566 24 : if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14567 24 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14568 24 : if (! (REG_P (XEXP (note, 0))
14569 24 : ? find_regno_note (i2, REG_NOTE_KIND (note),
14570 24 : REGNO (XEXP (note, 0)))
14571 0 : : find_reg_note (i2, REG_NOTE_KIND (note),
14572 : XEXP (note, 0))))
14573 : place = i2;
14574 : }
14575 : }
14576 :
14577 : break;
14578 :
14579 392204 : case REG_EQUAL:
14580 392204 : case REG_EQUIV:
14581 392204 : case REG_NOALIAS:
14582 : /* These notes say something about results of an insn. We can
14583 : only support them if they used to be on I3 in which case they
14584 : remain on I3. Otherwise they are ignored.
14585 :
14586 : If the note refers to an expression that is not a constant, we
14587 : must also ignore the note since we cannot tell whether the
14588 : equivalence is still true. It might be possible to do
14589 : slightly better than this (we only have a problem if I2DEST
14590 : or I1DEST is present in the expression), but it doesn't
14591 : seem worth the trouble. */
14592 :
14593 392204 : if (from_insn == i3
14594 192825 : && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14595 : place = i3;
14596 : break;
14597 :
14598 0 : case REG_INC:
14599 : /* These notes say something about how a register is used. They must
14600 : be present on any use of the register in I2 or I3. */
14601 0 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14602 0 : place = i3;
14603 :
14604 0 : if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14605 : {
14606 0 : if (place)
14607 : place2 = i2;
14608 : else
14609 : place = i2;
14610 : }
14611 : break;
14612 :
14613 6828 : case REG_LABEL_TARGET:
14614 6828 : case REG_LABEL_OPERAND:
14615 : /* This can show up in several ways -- either directly in the
14616 : pattern, or hidden off in the constant pool with (or without?)
14617 : a REG_EQUAL note. */
14618 : /* ??? Ignore the without-reg_equal-note problem for now. */
14619 6828 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14620 6828 : || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14621 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14622 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14623 : place = i3;
14624 :
14625 6828 : if (i2
14626 6828 : && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14627 0 : || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14628 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14629 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14630 : {
14631 0 : if (place)
14632 : place2 = i2;
14633 : else
14634 : place = i2;
14635 : }
14636 :
14637 : /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14638 : as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14639 : there. */
14640 6828 : if (place && JUMP_P (place)
14641 5582 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14642 0 : && (JUMP_LABEL (place) == NULL
14643 0 : || JUMP_LABEL (place) == XEXP (note, 0)))
14644 : {
14645 0 : rtx label = JUMP_LABEL (place);
14646 :
14647 0 : if (!label)
14648 0 : JUMP_LABEL (place) = XEXP (note, 0);
14649 0 : else if (LABEL_P (label))
14650 0 : LABEL_NUSES (label)--;
14651 : }
14652 :
14653 6828 : if (place2 && JUMP_P (place2)
14654 0 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14655 0 : && (JUMP_LABEL (place2) == NULL
14656 0 : || JUMP_LABEL (place2) == XEXP (note, 0)))
14657 : {
14658 0 : rtx label = JUMP_LABEL (place2);
14659 :
14660 0 : if (!label)
14661 0 : JUMP_LABEL (place2) = XEXP (note, 0);
14662 0 : else if (LABEL_P (label))
14663 0 : LABEL_NUSES (label)--;
14664 : place2 = 0;
14665 : }
14666 : break;
14667 :
14668 : case REG_NONNEG:
14669 : /* This note says something about the value of a register prior
14670 : to the execution of an insn. It is too much trouble to see
14671 : if the note is still correct in all situations. It is better
14672 : to simply delete it. */
14673 : break;
14674 :
14675 10487807 : case REG_DEAD:
14676 : /* If we replaced the right hand side of FROM_INSN with a
14677 : REG_EQUAL note, the original use of the dying register
14678 : will not have been combined into I3 and I2. In such cases,
14679 : FROM_INSN is guaranteed to be the first of the combined
14680 : instructions, so we simply need to search back before
14681 : FROM_INSN for the previous use or set of this register,
14682 : then alter the notes there appropriately.
14683 :
14684 : If the register is used as an input in I3, it dies there.
14685 : Similarly for I2, if it is nonzero and adjacent to I3.
14686 :
14687 : If the register is not used as an input in either I3 or I2
14688 : and it is not one of the registers we were supposed to eliminate,
14689 : there are two possibilities. We might have a non-adjacent I2
14690 : or we might have somehow eliminated an additional register
14691 : from a computation. For example, we might have had A & B where
14692 : we discover that B will always be zero. In this case we will
14693 : eliminate the reference to A.
14694 :
14695 : In both cases, we must search to see if we can find a previous
14696 : use of A and put the death note there. */
14697 :
14698 10487807 : if (from_insn
14699 7325585 : && from_insn == i2mod
14700 10489438 : && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14701 : tem_insn = from_insn;
14702 : else
14703 : {
14704 10486469 : if (from_insn
14705 7324247 : && CALL_P (from_insn)
14706 10716784 : && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14707 : place = from_insn;
14708 10336457 : else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14709 : {
14710 : /* If the new I2 sets the same register that is marked
14711 : dead in the note, we do not in general know where to
14712 : put the note. One important case we _can_ handle is
14713 : when the note comes from I3. */
14714 41000 : if (from_insn == i3)
14715 : place = i3;
14716 : else
14717 : break;
14718 : }
14719 10295457 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14720 : place = i3;
14721 105003 : else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14722 4108926 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14723 : place = i2;
14724 3962144 : else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14725 3842198 : && !(i2mod
14726 26888 : && reg_overlap_mentioned_p (XEXP (note, 0),
14727 : i2mod_old_rhs)))
14728 146844 : || rtx_equal_p (XEXP (note, 0), elim_i1)
14729 4016306 : || rtx_equal_p (XEXP (note, 0), elim_i0))
14730 : break;
14731 : tem_insn = i3;
14732 : }
14733 :
14734 235819 : if (place == 0)
14735 : {
14736 50976 : basic_block bb = this_basic_block;
14737 :
14738 1530727 : for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14739 : {
14740 1530727 : if (!NONDEBUG_INSN_P (tem_insn))
14741 : {
14742 1079523 : if (tem_insn == BB_HEAD (bb))
14743 : break;
14744 1044763 : continue;
14745 : }
14746 :
14747 : /* If the register is being set at TEM_INSN, see if that is all
14748 : TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14749 : into a REG_UNUSED note instead. Don't delete sets to
14750 : global register vars. */
14751 451204 : if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14752 1396 : || !global_regs[REGNO (XEXP (note, 0))])
14753 452600 : && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14754 : {
14755 15888 : rtx set = single_set (tem_insn);
14756 15888 : rtx inner_dest = 0;
14757 :
14758 15888 : if (set != 0)
14759 12418 : for (inner_dest = SET_DEST (set);
14760 12667 : (GET_CODE (inner_dest) == STRICT_LOW_PART
14761 12667 : || GET_CODE (inner_dest) == SUBREG
14762 12667 : || GET_CODE (inner_dest) == ZERO_EXTRACT);
14763 249 : inner_dest = XEXP (inner_dest, 0))
14764 : ;
14765 :
14766 : /* Verify that it was the set, and not a clobber that
14767 : modified the register.
14768 :
14769 : If we cannot delete the setter due to side
14770 : effects, mark the user with an UNUSED note instead
14771 : of deleting it. */
14772 :
14773 12418 : if (set != 0 && ! side_effects_p (SET_SRC (set))
14774 12048 : && rtx_equal_p (XEXP (note, 0), inner_dest))
14775 : {
14776 : /* Move the notes and links of TEM_INSN elsewhere.
14777 : This might delete other dead insns recursively.
14778 : First set the pattern to something that won't use
14779 : any register. */
14780 11834 : rtx old_notes = REG_NOTES (tem_insn);
14781 :
14782 11834 : PATTERN (tem_insn) = pc_rtx;
14783 11834 : REG_NOTES (tem_insn) = NULL;
14784 :
14785 11834 : distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14786 : NULL_RTX, NULL_RTX, NULL_RTX);
14787 11834 : distribute_links (LOG_LINKS (tem_insn));
14788 :
14789 11834 : unsigned int regno = REGNO (XEXP (note, 0));
14790 11834 : reg_stat_type *rsp = ®_stat[regno];
14791 11834 : if (rsp->last_set == tem_insn)
14792 10443 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14793 :
14794 11834 : SET_INSN_DELETED (tem_insn);
14795 11834 : if (tem_insn == i2)
14796 434988 : i2 = NULL;
14797 : }
14798 : else
14799 : {
14800 4054 : PUT_REG_NOTE_KIND (note, REG_UNUSED);
14801 :
14802 : /* If there isn't already a REG_UNUSED note, put one
14803 : here. Do not place a REG_DEAD note, even if
14804 : the register is also used here; that would not
14805 : match the algorithm used in lifetime analysis
14806 : and can cause the consistency check in the
14807 : scheduler to fail. */
14808 4054 : if (! find_regno_note (tem_insn, REG_UNUSED,
14809 4054 : REGNO (XEXP (note, 0))))
14810 2181 : place = tem_insn;
14811 : break;
14812 : }
14813 : }
14814 435316 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14815 435316 : || (CALL_P (tem_insn)
14816 14273 : && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14817 : {
14818 12162 : place = tem_insn;
14819 :
14820 : /* If we are doing a 3->2 combination, and we have a
14821 : register which formerly died in i3 and was not used
14822 : by i2, which now no longer dies in i3 and is used in
14823 : i2 but does not die in i2, and place is between i2
14824 : and i3, then we may need to move a link from place to
14825 : i2. */
14826 3774 : if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14827 83 : && from_insn
14828 83 : && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14829 12245 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14830 : {
14831 82 : struct insn_link *links = LOG_LINKS (place);
14832 82 : LOG_LINKS (place) = NULL;
14833 82 : distribute_links (links);
14834 : }
14835 : break;
14836 : }
14837 :
14838 434988 : if (tem_insn == BB_HEAD (bb))
14839 : break;
14840 : }
14841 :
14842 : }
14843 :
14844 : /* If the register is set or already dead at PLACE, we needn't do
14845 : anything with this note if it is still a REG_DEAD note.
14846 : We check here if it is set at all, not if is it totally replaced,
14847 : which is what `dead_or_set_p' checks, so also check for it being
14848 : set partially. */
14849 :
14850 6571697 : if (place && REG_NOTE_KIND (note) == REG_DEAD)
14851 : {
14852 6532883 : unsigned int regno = REGNO (XEXP (note, 0));
14853 6532883 : reg_stat_type *rsp = ®_stat[regno];
14854 :
14855 6532883 : if (dead_or_set_p (place, XEXP (note, 0))
14856 6532883 : || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14857 : {
14858 : /* Unless the register previously died in PLACE, clear
14859 : last_death. [I no longer understand why this is
14860 : being done.] */
14861 3070729 : if (rsp->last_death != place)
14862 631764 : rsp->last_death = 0;
14863 : place = 0;
14864 : }
14865 : else
14866 3462154 : rsp->last_death = place;
14867 :
14868 : /* If this is a death note for a hard reg that is occupying
14869 : multiple registers, ensure that we are still using all
14870 : parts of the object. If we find a piece of the object
14871 : that is unused, we must arrange for an appropriate REG_DEAD
14872 : note to be added for it. However, we can't just emit a USE
14873 : and tag the note to it, since the register might actually
14874 : be dead; so we recurse, and the recursive call then finds
14875 : the previous insn that used this register. */
14876 :
14877 4093918 : if (place && REG_NREGS (XEXP (note, 0)) > 1)
14878 : {
14879 776 : unsigned int endregno = END_REGNO (XEXP (note, 0));
14880 776 : bool all_used = true;
14881 776 : unsigned int i;
14882 :
14883 2328 : for (i = regno; i < endregno; i++)
14884 1552 : if ((! refers_to_regno_p (i, PATTERN (place))
14885 1552 : && ! find_regno_fusage (place, USE, i))
14886 3104 : || dead_or_set_regno_p (place, i))
14887 : {
14888 : all_used = false;
14889 : break;
14890 : }
14891 :
14892 776 : if (! all_used)
14893 : {
14894 : /* Put only REG_DEAD notes for pieces that are
14895 : not already dead or set. */
14896 :
14897 0 : for (i = regno; i < endregno;
14898 0 : i += hard_regno_nregs (i, reg_raw_mode[i]))
14899 : {
14900 0 : rtx piece = regno_reg_rtx[i];
14901 0 : basic_block bb = this_basic_block;
14902 :
14903 0 : if (! dead_or_set_p (place, piece)
14904 0 : && ! reg_bitfield_target_p (piece,
14905 0 : PATTERN (place)))
14906 : {
14907 0 : rtx new_note = alloc_reg_note (REG_DEAD, piece,
14908 : NULL_RTX);
14909 :
14910 0 : distribute_notes (new_note, place, place,
14911 : NULL, NULL_RTX, NULL_RTX,
14912 : NULL_RTX);
14913 : }
14914 0 : else if (! refers_to_regno_p (i, PATTERN (place))
14915 0 : && ! find_regno_fusage (place, USE, i))
14916 0 : for (tem_insn = PREV_INSN (place); ;
14917 0 : tem_insn = PREV_INSN (tem_insn))
14918 : {
14919 0 : if (!NONDEBUG_INSN_P (tem_insn))
14920 : {
14921 0 : if (tem_insn == BB_HEAD (bb))
14922 : break;
14923 0 : continue;
14924 : }
14925 0 : if (dead_or_set_p (tem_insn, piece)
14926 0 : || reg_bitfield_target_p (piece,
14927 0 : PATTERN (tem_insn)))
14928 : {
14929 0 : add_reg_note (tem_insn, REG_UNUSED, piece);
14930 0 : break;
14931 : }
14932 : }
14933 : }
14934 :
14935 : place = 0;
14936 : }
14937 : }
14938 : }
14939 : break;
14940 :
14941 0 : default:
14942 : /* Any other notes should not be present at this point in the
14943 : compilation. */
14944 0 : gcc_unreachable ();
14945 : }
14946 :
14947 4284024 : if (place)
14948 : {
14949 4256782 : XEXP (note, 1) = REG_NOTES (place);
14950 4256782 : REG_NOTES (place) = note;
14951 :
14952 : /* Set added_notes_insn to the earliest insn we added a note to. */
14953 4256782 : if (added_notes_insn == 0
14954 4256782 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14955 2819781 : added_notes_insn = place;
14956 : }
14957 :
14958 13118850 : if (place2)
14959 : {
14960 0 : add_shallow_copy_of_reg_note (place2, note);
14961 :
14962 : /* Set added_notes_insn to the earliest insn we added a note to. */
14963 0 : if (added_notes_insn == 0
14964 0 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14965 0 : added_notes_insn = place2;
14966 : }
14967 : }
14968 9954542 : }
14969 :
14970 : /* Similarly to above, distribute the LOG_LINKS that used to be present on
14971 : I3, I2, and I1 to new locations. This is also called to add a link
14972 : pointing at I3 when I3's destination is changed.
14973 :
14974 : If START is nonnull and an insn, we know that the next location for each
14975 : link is no earlier than START. LIMIT is the maximum number of nondebug
14976 : instructions that can be scanned when looking for the next use of a
14977 : definition. */
14978 :
14979 : static void
14980 16197818 : distribute_links (struct insn_link *links, rtx_insn *start, int limit)
14981 : {
14982 16197818 : struct insn_link *link, *next_link;
14983 :
14984 23870762 : for (link = links; link; link = next_link)
14985 : {
14986 7672944 : rtx_insn *place = 0;
14987 7672944 : rtx_insn *insn;
14988 7672944 : rtx set, reg;
14989 :
14990 7672944 : next_link = link->next;
14991 :
14992 : /* If the insn that this link points to is a NOTE, ignore it. */
14993 7672944 : if (NOTE_P (link->insn))
14994 4080421 : continue;
14995 :
14996 3592523 : set = 0;
14997 3592523 : rtx pat = PATTERN (link->insn);
14998 3592523 : if (GET_CODE (pat) == SET)
14999 : set = pat;
15000 627636 : else if (GET_CODE (pat) == PARALLEL)
15001 : {
15002 : int i;
15003 741306 : for (i = 0; i < XVECLEN (pat, 0); i++)
15004 : {
15005 737734 : set = XVECEXP (pat, 0, i);
15006 737734 : if (GET_CODE (set) != SET)
15007 3581 : continue;
15008 :
15009 734153 : reg = SET_DEST (set);
15010 734153 : while (GET_CODE (reg) == ZERO_EXTRACT
15011 742796 : || GET_CODE (reg) == STRICT_LOW_PART
15012 1485508 : || GET_CODE (reg) == SUBREG)
15013 8650 : reg = XEXP (reg, 0);
15014 :
15015 734153 : if (!REG_P (reg))
15016 44413 : continue;
15017 :
15018 689740 : if (REGNO (reg) == link->regno)
15019 : break;
15020 : }
15021 625460 : if (i == XVECLEN (pat, 0))
15022 3572 : continue;
15023 : }
15024 : else
15025 2176 : continue;
15026 :
15027 3586775 : reg = SET_DEST (set);
15028 :
15029 3586775 : while (GET_CODE (reg) == ZERO_EXTRACT
15030 3609940 : || GET_CODE (reg) == STRICT_LOW_PART
15031 7220021 : || GET_CODE (reg) == SUBREG)
15032 23744 : reg = XEXP (reg, 0);
15033 :
15034 3586775 : if (reg == pc_rtx)
15035 477 : continue;
15036 :
15037 : /* A LOG_LINK is defined as being placed on the first insn that uses
15038 : a register and points to the insn that sets the register. Start
15039 : searching at the next insn after the target of the link and stop
15040 : when we reach a set of the register or the end of the basic block.
15041 :
15042 : Note that this correctly handles the link that used to point from
15043 : I3 to I2. Also note that not much searching is typically done here
15044 : since most links don't point very far away. */
15045 :
15046 3586298 : int count = 0;
15047 3586298 : insn = start;
15048 3586298 : if (!insn || NOTE_P (insn))
15049 3534901 : insn = NEXT_INSN (link->insn);
15050 : else
15051 51397 : count = link->insn_count;
15052 11903384 : for (;
15053 15489682 : (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
15054 10668206 : || BB_HEAD (this_basic_block->next_bb) != insn));
15055 11903384 : insn = NEXT_INSN (insn))
15056 15450217 : if (DEBUG_INSN_P (insn))
15057 3303767 : continue;
15058 12146450 : else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
15059 : {
15060 3394150 : if (reg_referenced_p (reg, PATTERN (insn)))
15061 3394150 : place = insn;
15062 : break;
15063 : }
15064 8752300 : else if (CALL_P (insn)
15065 8752300 : && find_reg_fusage (insn, USE, reg))
15066 : {
15067 : place = insn;
15068 : break;
15069 : }
15070 8599797 : else if (INSN_P (insn) && reg_set_p (reg, insn))
15071 : break;
15072 8599617 : else if (count >= limit)
15073 : break;
15074 : else
15075 8599617 : count += 1;
15076 3586298 : link->insn_count = count;
15077 :
15078 : /* If we found a place to put the link, place it there unless there
15079 : is already a link to the same insn as LINK at that point. */
15080 :
15081 3586298 : if (place)
15082 : {
15083 3546653 : struct insn_link *link2;
15084 :
15085 4572590 : FOR_EACH_LOG_LINK (link2, place)
15086 1043157 : if (link2->insn == link->insn && link2->regno == link->regno)
15087 : break;
15088 :
15089 3546653 : if (link2 == NULL)
15090 : {
15091 3529433 : link->next = LOG_LINKS (place);
15092 3529433 : LOG_LINKS (place) = link;
15093 :
15094 : /* Set added_links_insn to the earliest insn we added a
15095 : link to. */
15096 3529433 : if (added_links_insn == 0
15097 3529433 : || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15098 2797900 : added_links_insn = place;
15099 : }
15100 : }
15101 : }
15102 16197818 : }
15103 :
15104 : /* Check for any register or memory mentioned in EQUIV that is not
15105 : mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15106 : of EXPR where some registers may have been replaced by constants. */
15107 :
15108 : static bool
15109 2759267 : unmentioned_reg_p (rtx equiv, rtx expr)
15110 : {
15111 2759267 : subrtx_iterator::array_type array;
15112 7234942 : FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15113 : {
15114 5869023 : const_rtx x = *iter;
15115 4029907 : if ((REG_P (x) || MEM_P (x))
15116 6260372 : && !reg_mentioned_p (x, expr))
15117 1393348 : return true;
15118 : }
15119 1365919 : return false;
15120 2759267 : }
15121 :
15122 : /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15123 : the reg-to-reg copy can usefully combine with later instructions, but we
15124 : do not want to combine the hard reg into later instructions, for that
15125 : restricts register allocation. */
15126 : static void
15127 1062343 : make_more_copies (void)
15128 : {
15129 1062343 : basic_block bb;
15130 :
15131 11666367 : FOR_EACH_BB_FN (bb, cfun)
15132 : {
15133 10604024 : rtx_insn *insn;
15134 :
15135 141141761 : FOR_BB_INSNS (bb, insn)
15136 : {
15137 130537737 : if (!NONDEBUG_INSN_P (insn))
15138 70401067 : continue;
15139 :
15140 60136670 : rtx set = single_set (insn);
15141 60136670 : if (!set)
15142 4081521 : continue;
15143 :
15144 56055149 : rtx dest = SET_DEST (set);
15145 56055149 : if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15146 32097922 : continue;
15147 :
15148 23957227 : rtx src = SET_SRC (set);
15149 23957227 : if (!(REG_P (src) && HARD_REGISTER_P (src)))
15150 20931410 : continue;
15151 3025817 : if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15152 9892 : continue;
15153 :
15154 3015925 : rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15155 :
15156 : /* The "original" pseudo copies have important attributes
15157 : attached, like pointerness. We want that for these copies
15158 : too, for use by insn recognition and later passes. */
15159 3015925 : set_reg_attrs_from_value (new_reg, dest);
15160 :
15161 3015925 : rtx_insn *new_insn = gen_move_insn (new_reg, src);
15162 3015925 : SET_SRC (set) = new_reg;
15163 3015925 : emit_insn_before (new_insn, insn);
15164 3015925 : df_insn_rescan (insn);
15165 : }
15166 : }
15167 1062343 : }
15168 :
15169 : /* Try combining insns through substitution. */
15170 : static void
15171 1062343 : rest_of_handle_combine (void)
15172 : {
15173 1062343 : make_more_copies ();
15174 :
15175 1062343 : df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15176 1062343 : df_note_add_problem ();
15177 1062343 : df_analyze ();
15178 :
15179 1062343 : regstat_init_n_sets_and_refs ();
15180 1062343 : reg_n_sets_max = max_reg_num ();
15181 :
15182 1062343 : bool rebuild_jump_labels_after_combine
15183 1062343 : = combine_instructions (get_insns (), max_reg_num ());
15184 :
15185 : /* Combining insns may have turned an indirect jump into a
15186 : direct jump. Rebuild the JUMP_LABEL fields of jumping
15187 : instructions. */
15188 1062343 : if (rebuild_jump_labels_after_combine)
15189 : {
15190 2507 : if (dom_info_available_p (CDI_DOMINATORS))
15191 0 : free_dominance_info (CDI_DOMINATORS);
15192 2507 : timevar_push (TV_JUMP);
15193 2507 : rebuild_jump_labels (get_insns ());
15194 2507 : cleanup_cfg (0);
15195 2507 : timevar_pop (TV_JUMP);
15196 : }
15197 :
15198 1062343 : regstat_free_n_sets_and_refs ();
15199 1062343 : }
15200 :
15201 : namespace {
15202 :
15203 : const pass_data pass_data_combine =
15204 : {
15205 : RTL_PASS, /* type */
15206 : "combine", /* name */
15207 : OPTGROUP_NONE, /* optinfo_flags */
15208 : TV_COMBINE, /* tv_id */
15209 : PROP_cfglayout, /* properties_required */
15210 : 0, /* properties_provided */
15211 : 0, /* properties_destroyed */
15212 : 0, /* todo_flags_start */
15213 : TODO_df_finish, /* todo_flags_finish */
15214 : };
15215 :
15216 : class pass_combine : public rtl_opt_pass
15217 : {
15218 : public:
15219 294196 : pass_combine (gcc::context *ctxt)
15220 588392 : : rtl_opt_pass (pass_data_combine, ctxt)
15221 : {}
15222 :
15223 : /* opt_pass methods: */
15224 1515129 : bool gate (function *) final override { return (optimize > 0); }
15225 1062343 : unsigned int execute (function *) final override
15226 : {
15227 1062343 : rest_of_handle_combine ();
15228 1062343 : return 0;
15229 : }
15230 :
15231 : }; // class pass_combine
15232 :
15233 : } // anon namespace
15234 :
15235 : rtl_opt_pass *
15236 294196 : make_pass_combine (gcc::context *ctxt)
15237 : {
15238 294196 : return new pass_combine (ctxt);
15239 : }
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