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1 : : /* Optimize by combining instructions for GNU compiler.
2 : : Copyright (C) 1987-2024 Free Software Foundation, Inc.
3 : :
4 : : This file is part of GCC.
5 : :
6 : : GCC is free software; you can redistribute it and/or modify it under
7 : : the terms of the GNU General Public License as published by the Free
8 : : Software Foundation; either version 3, or (at your option) any later
9 : : version.
10 : :
11 : : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : : for more details.
15 : :
16 : : You should have received a copy of the GNU General Public License
17 : : along with GCC; see the file COPYING3. If not see
18 : : <http://www.gnu.org/licenses/>. */
19 : :
20 : : /* This module is essentially the "combiner" phase of the U. of Arizona
21 : : Portable Optimizer, but redone to work on our list-structured
22 : : representation for RTL instead of their string representation.
23 : :
24 : : The LOG_LINKS of each insn identify the most recent assignment
25 : : to each REG used in the insn. It is a list of previous insns,
26 : : each of which contains a SET for a REG that is used in this insn
27 : : and not used or set in between. LOG_LINKs never cross basic blocks.
28 : : They were set up by the preceding pass (lifetime analysis).
29 : :
30 : : We try to combine each pair of insns joined by a logical link.
31 : : We also try to combine triplets of insns A, B and C when C has
32 : : a link back to B and B has a link back to A. Likewise for a
33 : : small number of quadruplets of insns A, B, C and D for which
34 : : there's high likelihood of success.
35 : :
36 : : We check (with modified_between_p) to avoid combining in such a way
37 : : as to move a computation to a place where its value would be different.
38 : :
39 : : Combination is done by mathematically substituting the previous
40 : : insn(s) values for the regs they set into the expressions in
41 : : the later insns that refer to these regs. If the result is a valid insn
42 : : for our target machine, according to the machine description,
43 : : we install it, delete the earlier insns, and update the data flow
44 : : information (LOG_LINKS and REG_NOTES) for what we did.
45 : :
46 : : There are a few exceptions where the dataflow information isn't
47 : : completely updated (however this is only a local issue since it is
48 : : regenerated before the next pass that uses it):
49 : :
50 : : - reg_live_length is not updated
51 : : - reg_n_refs is not adjusted in the rare case when a register is
52 : : no longer required in a computation
53 : : - there are extremely rare cases (see distribute_notes) when a
54 : : REG_DEAD note is lost
55 : : - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 : : removed because there is no way to know which register it was
57 : : linking
58 : :
59 : : To simplify substitution, we combine only when the earlier insn(s)
60 : : consist of only a single assignment. To simplify updating afterward,
61 : : we never combine when a subroutine call appears in the middle. */
62 : :
63 : : #include "config.h"
64 : : #include "system.h"
65 : : #include "coretypes.h"
66 : : #include "backend.h"
67 : : #include "target.h"
68 : : #include "rtl.h"
69 : : #include "tree.h"
70 : : #include "cfghooks.h"
71 : : #include "predict.h"
72 : : #include "df.h"
73 : : #include "memmodel.h"
74 : : #include "tm_p.h"
75 : : #include "optabs.h"
76 : : #include "regs.h"
77 : : #include "emit-rtl.h"
78 : : #include "recog.h"
79 : : #include "cgraph.h"
80 : : #include "stor-layout.h"
81 : : #include "cfgrtl.h"
82 : : #include "cfgcleanup.h"
83 : : /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84 : : #include "explow.h"
85 : : #include "insn-attr.h"
86 : : #include "rtlhooks-def.h"
87 : : #include "expr.h"
88 : : #include "tree-pass.h"
89 : : #include "valtrack.h"
90 : : #include "rtl-iter.h"
91 : : #include "print-rtl.h"
92 : : #include "function-abi.h"
93 : : #include "rtlanal.h"
94 : :
95 : : /* Number of attempts to combine instructions in this function. */
96 : :
97 : : static int combine_attempts;
98 : :
99 : : /* Number of attempts that got as far as substitution in this function. */
100 : :
101 : : static int combine_merges;
102 : :
103 : : /* Number of instructions combined with added SETs in this function. */
104 : :
105 : : static int combine_extras;
106 : :
107 : : /* Number of instructions combined in this function. */
108 : :
109 : : static int combine_successes;
110 : :
111 : : /* combine_instructions may try to replace the right hand side of the
112 : : second instruction with the value of an associated REG_EQUAL note
113 : : before throwing it at try_combine. That is problematic when there
114 : : is a REG_DEAD note for a register used in the old right hand side
115 : : and can cause distribute_notes to do wrong things. This is the
116 : : second instruction if it has been so modified, null otherwise. */
117 : :
118 : : static rtx_insn *i2mod;
119 : :
120 : : /* When I2MOD is nonnull, this is a copy of the old right hand side. */
121 : :
122 : : static rtx i2mod_old_rhs;
123 : :
124 : : /* When I2MOD is nonnull, this is a copy of the new right hand side. */
125 : :
126 : : static rtx i2mod_new_rhs;
127 : :
128 : : struct reg_stat_type {
129 : : /* Record last point of death of (hard or pseudo) register n. */
130 : : rtx_insn *last_death;
131 : :
132 : : /* Record last point of modification of (hard or pseudo) register n. */
133 : : rtx_insn *last_set;
134 : :
135 : : /* The next group of fields allows the recording of the last value assigned
136 : : to (hard or pseudo) register n. We use this information to see if an
137 : : operation being processed is redundant given a prior operation performed
138 : : on the register. For example, an `and' with a constant is redundant if
139 : : all the zero bits are already known to be turned off.
140 : :
141 : : We use an approach similar to that used by cse, but change it in the
142 : : following ways:
143 : :
144 : : (1) We do not want to reinitialize at each label.
145 : : (2) It is useful, but not critical, to know the actual value assigned
146 : : to a register. Often just its form is helpful.
147 : :
148 : : Therefore, we maintain the following fields:
149 : :
150 : : last_set_value the last value assigned
151 : : last_set_label records the value of label_tick when the
152 : : register was assigned
153 : : last_set_table_tick records the value of label_tick when a
154 : : value using the register is assigned
155 : : last_set_invalid set to true when it is not valid
156 : : to use the value of this register in some
157 : : register's value
158 : :
159 : : To understand the usage of these tables, it is important to understand
160 : : the distinction between the value in last_set_value being valid and
161 : : the register being validly contained in some other expression in the
162 : : table.
163 : :
164 : : (The next two parameters are out of date).
165 : :
166 : : reg_stat[i].last_set_value is valid if it is nonzero, and either
167 : : reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168 : :
169 : : Register I may validly appear in any expression returned for the value
170 : : of another register if reg_n_sets[i] is 1. It may also appear in the
171 : : value for register J if reg_stat[j].last_set_invalid is zero, or
172 : : reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173 : :
174 : : If an expression is found in the table containing a register which may
175 : : not validly appear in an expression, the register is replaced by
176 : : something that won't match, (clobber (const_int 0)). */
177 : :
178 : : /* Record last value assigned to (hard or pseudo) register n. */
179 : :
180 : : rtx last_set_value;
181 : :
182 : : /* Record the value of label_tick when an expression involving register n
183 : : is placed in last_set_value. */
184 : :
185 : : int last_set_table_tick;
186 : :
187 : : /* Record the value of label_tick when the value for register n is placed in
188 : : last_set_value. */
189 : :
190 : : int last_set_label;
191 : :
192 : : /* These fields are maintained in parallel with last_set_value and are
193 : : used to store the mode in which the register was last set, the bits
194 : : that were known to be zero when it was last set, and the number of
195 : : sign bits copies it was known to have when it was last set. */
196 : :
197 : : unsigned HOST_WIDE_INT last_set_nonzero_bits;
198 : : char last_set_sign_bit_copies;
199 : : ENUM_BITFIELD(machine_mode) last_set_mode : MACHINE_MODE_BITSIZE;
200 : :
201 : : /* Set to true if references to register n in expressions should not be
202 : : used. last_set_invalid is set nonzero when this register is being
203 : : assigned to and last_set_table_tick == label_tick. */
204 : :
205 : : bool last_set_invalid;
206 : :
207 : : /* Some registers that are set more than once and used in more than one
208 : : basic block are nevertheless always set in similar ways. For example,
209 : : a QImode register may be loaded from memory in two places on a machine
210 : : where byte loads zero extend.
211 : :
212 : : We record in the following fields if a register has some leading bits
213 : : that are always equal to the sign bit, and what we know about the
214 : : nonzero bits of a register, specifically which bits are known to be
215 : : zero.
216 : :
217 : : If an entry is zero, it means that we don't know anything special. */
218 : :
219 : : unsigned char sign_bit_copies;
220 : :
221 : : unsigned HOST_WIDE_INT nonzero_bits;
222 : :
223 : : /* Record the value of the label_tick when the last truncation
224 : : happened. The field truncated_to_mode is only valid if
225 : : truncation_label == label_tick. */
226 : :
227 : : int truncation_label;
228 : :
229 : : /* Record the last truncation seen for this register. If truncation
230 : : is not a nop to this mode we might be able to save an explicit
231 : : truncation if we know that value already contains a truncated
232 : : value. */
233 : :
234 : : ENUM_BITFIELD(machine_mode) truncated_to_mode : MACHINE_MODE_BITSIZE;
235 : : };
236 : :
237 : :
238 : : static vec<reg_stat_type> reg_stat;
239 : :
240 : : /* One plus the highest pseudo for which we track REG_N_SETS.
241 : : regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 : : but during combine_split_insns new pseudos can be created. As we don't have
243 : : updated DF information in that case, it is hard to initialize the array
244 : : after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 : : so instead of growing the arrays, just assume all newly created pseudos
246 : : during combine might be set multiple times. */
247 : :
248 : : static unsigned int reg_n_sets_max;
249 : :
250 : : /* Record the luid of the last insn that invalidated memory
251 : : (anything that writes memory, and subroutine calls, but not pushes). */
252 : :
253 : : static int mem_last_set;
254 : :
255 : : /* Record the luid of the last CALL_INSN
256 : : so we can tell whether a potential combination crosses any calls. */
257 : :
258 : : static int last_call_luid;
259 : :
260 : : /* When `subst' is called, this is the insn that is being modified
261 : : (by combining in a previous insn). The PATTERN of this insn
262 : : is still the old pattern partially modified and it should not be
263 : : looked at, but this may be used to examine the successors of the insn
264 : : to judge whether a simplification is valid. */
265 : :
266 : : static rtx_insn *subst_insn;
267 : :
268 : : /* This is the lowest LUID that `subst' is currently dealing with.
269 : : get_last_value will not return a value if the register was set at or
270 : : after this LUID. If not for this mechanism, we could get confused if
271 : : I2 or I1 in try_combine were an insn that used the old value of a register
272 : : to obtain a new value. In that case, we might erroneously get the
273 : : new value of the register when we wanted the old one. */
274 : :
275 : : static int subst_low_luid;
276 : :
277 : : /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 : : must consider all these registers to be always live. */
279 : :
280 : : static HARD_REG_SET newpat_used_regs;
281 : :
282 : : /* This is an insn to which a LOG_LINKS entry has been added. If this
283 : : insn is the earlier than I2 or I3, combine should rescan starting at
284 : : that location. */
285 : :
286 : : static rtx_insn *added_links_insn;
287 : :
288 : : /* And similarly, for notes. */
289 : :
290 : : static rtx_insn *added_notes_insn;
291 : :
292 : : /* Basic block in which we are performing combines. */
293 : : static basic_block this_basic_block;
294 : : static bool optimize_this_for_speed_p;
295 : :
296 : :
297 : : /* Length of the currently allocated uid_insn_cost array. */
298 : :
299 : : static int max_uid_known;
300 : :
301 : : /* The following array records the insn_cost for every insn
302 : : in the instruction stream. */
303 : :
304 : : static int *uid_insn_cost;
305 : :
306 : : /* The following array records the LOG_LINKS for every insn in the
307 : : instruction stream as struct insn_link pointers. */
308 : :
309 : : struct insn_link {
310 : : rtx_insn *insn;
311 : : unsigned int regno;
312 : : struct insn_link *next;
313 : : };
314 : :
315 : : static struct insn_link **uid_log_links;
316 : :
317 : : static inline int
318 : 713933772 : insn_uid_check (const_rtx insn)
319 : : {
320 : 713933772 : int uid = INSN_UID (insn);
321 : 713933772 : gcc_checking_assert (uid <= max_uid_known);
322 : 713933772 : return uid;
323 : : }
324 : :
325 : : #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
326 : : #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
327 : :
328 : : #define FOR_EACH_LOG_LINK(L, INSN) \
329 : : for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
330 : :
331 : : /* Links for LOG_LINKS are allocated from this obstack. */
332 : :
333 : : static struct obstack insn_link_obstack;
334 : :
335 : : /* Allocate a link. */
336 : :
337 : : static inline struct insn_link *
338 : 36493733 : alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
339 : : {
340 : 36493733 : struct insn_link *l
341 : 36493733 : = (struct insn_link *) obstack_alloc (&insn_link_obstack,
342 : : sizeof (struct insn_link));
343 : 36493733 : l->insn = insn;
344 : 36493733 : l->regno = regno;
345 : 36493733 : l->next = next;
346 : 36493733 : return l;
347 : : }
348 : :
349 : : /* Incremented for each basic block. */
350 : :
351 : : static int label_tick;
352 : :
353 : : /* Reset to label_tick for each extended basic block in scanning order. */
354 : :
355 : : static int label_tick_ebb_start;
356 : :
357 : : /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
358 : : largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
359 : :
360 : : static scalar_int_mode nonzero_bits_mode;
361 : :
362 : : /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
363 : : be safely used. It is zero while computing them and after combine has
364 : : completed. This former test prevents propagating values based on
365 : : previously set values, which can be incorrect if a variable is modified
366 : : in a loop. */
367 : :
368 : : static int nonzero_sign_valid;
369 : :
370 : :
371 : : /* Record one modification to rtl structure
372 : : to be undone by storing old_contents into *where. */
373 : :
374 : : enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
375 : :
376 : : struct undo
377 : : {
378 : : struct undo *next;
379 : : enum undo_kind kind;
380 : : union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
381 : : union { rtx *r; int *i; int regno; struct insn_link **l; } where;
382 : : };
383 : :
384 : : /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
385 : : num_undo says how many are currently recorded.
386 : :
387 : : other_insn is nonzero if we have modified some other insn in the process
388 : : of working on subst_insn. It must be verified too. */
389 : :
390 : : struct undobuf
391 : : {
392 : : struct undo *undos;
393 : : struct undo *frees;
394 : : rtx_insn *other_insn;
395 : : };
396 : :
397 : : static struct undobuf undobuf;
398 : :
399 : : /* Number of times the pseudo being substituted for
400 : : was found and replaced. */
401 : :
402 : : static int n_occurrences;
403 : :
404 : : static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
405 : : scalar_int_mode,
406 : : unsigned HOST_WIDE_INT *);
407 : : static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
408 : : scalar_int_mode,
409 : : unsigned int *);
410 : : static void do_SUBST (rtx *, rtx);
411 : : static void do_SUBST_INT (int *, int);
412 : : static void init_reg_last (void);
413 : : static void setup_incoming_promotions (rtx_insn *);
414 : : static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
415 : : static bool cant_combine_insn_p (rtx_insn *);
416 : : static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
417 : : rtx_insn *, rtx_insn *, rtx *, rtx *);
418 : : static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
419 : : bool, bool, rtx *);
420 : : static bool contains_muldiv (rtx);
421 : : static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
422 : : bool *, rtx_insn *);
423 : : static void undo_all (void);
424 : : static void undo_commit (void);
425 : : static rtx *find_split_point (rtx *, rtx_insn *, bool);
426 : : static rtx subst (rtx, rtx, rtx, bool, bool, bool);
427 : : static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
428 : : static rtx simplify_if_then_else (rtx);
429 : : static rtx simplify_set (rtx);
430 : : static rtx simplify_logical (rtx);
431 : : static rtx expand_compound_operation (rtx);
432 : : static const_rtx expand_field_assignment (const_rtx);
433 : : static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
434 : : unsigned HOST_WIDE_INT, bool, bool, bool);
435 : : static int get_pos_from_mask (unsigned HOST_WIDE_INT,
436 : : unsigned HOST_WIDE_INT *);
437 : : static rtx canon_reg_for_combine (rtx, rtx);
438 : : static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
439 : : scalar_int_mode, unsigned HOST_WIDE_INT, bool);
440 : : static rtx force_to_mode (rtx, machine_mode,
441 : : unsigned HOST_WIDE_INT, bool);
442 : : static rtx if_then_else_cond (rtx, rtx *, rtx *);
443 : : static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
444 : : static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
445 : : static rtx make_field_assignment (rtx);
446 : : static rtx apply_distributive_law (rtx);
447 : : static rtx distribute_and_simplify_rtx (rtx, int);
448 : : static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
449 : : unsigned HOST_WIDE_INT);
450 : : static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
451 : : unsigned HOST_WIDE_INT);
452 : : static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
453 : : HOST_WIDE_INT, machine_mode, bool *);
454 : : static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
455 : : static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
456 : : int);
457 : : static int recog_for_combine (rtx *, rtx_insn *, rtx *);
458 : : static rtx gen_lowpart_for_combine (machine_mode, rtx);
459 : : static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
460 : : rtx *, rtx *);
461 : : static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
462 : : static void update_table_tick (rtx);
463 : : static void record_value_for_reg (rtx, rtx_insn *, rtx);
464 : : static void check_promoted_subreg (rtx_insn *, rtx);
465 : : static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
466 : : static void record_dead_and_set_regs (rtx_insn *);
467 : : static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
468 : : static rtx get_last_value (const_rtx);
469 : : static void reg_dead_at_p_1 (rtx, const_rtx, void *);
470 : : static bool reg_dead_at_p (rtx, rtx_insn *);
471 : : static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
472 : : static bool reg_bitfield_target_p (rtx, rtx);
473 : : static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
474 : : rtx, rtx, rtx);
475 : : static void distribute_links (struct insn_link *);
476 : : static void mark_used_regs_combine (rtx);
477 : : static void record_promoted_value (rtx_insn *, rtx);
478 : : static bool unmentioned_reg_p (rtx, rtx);
479 : : static void record_truncated_values (rtx *, void *);
480 : : static bool reg_truncated_to_mode (machine_mode, const_rtx);
481 : : static rtx gen_lowpart_or_truncate (machine_mode, rtx);
482 : :
483 : :
484 : : /* It is not safe to use ordinary gen_lowpart in combine.
485 : : See comments in gen_lowpart_for_combine. */
486 : : #undef RTL_HOOKS_GEN_LOWPART
487 : : #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
488 : :
489 : : /* Our implementation of gen_lowpart never emits a new pseudo. */
490 : : #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
491 : : #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
492 : :
493 : : #undef RTL_HOOKS_REG_NONZERO_REG_BITS
494 : : #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
495 : :
496 : : #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
497 : : #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
498 : :
499 : : #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
500 : : #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
501 : :
502 : : static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
503 : :
504 : :
505 : : /* Convenience wrapper for the canonicalize_comparison target hook.
506 : : Target hooks cannot use enum rtx_code. */
507 : : static inline void
508 : 21945252 : target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
509 : : bool op0_preserve_value)
510 : : {
511 : 21945252 : int code_int = (int)*code;
512 : 21945252 : targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
513 : 21945252 : *code = (enum rtx_code)code_int;
514 : 813165 : }
515 : :
516 : : /* Try to split PATTERN found in INSN. This returns NULL_RTX if
517 : : PATTERN cannot be split. Otherwise, it returns an insn sequence.
518 : : This is a wrapper around split_insns which ensures that the
519 : : reg_stat vector is made larger if the splitter creates a new
520 : : register. */
521 : :
522 : : static rtx_insn *
523 : 10804721 : combine_split_insns (rtx pattern, rtx_insn *insn)
524 : : {
525 : 10804721 : rtx_insn *ret;
526 : 10804721 : unsigned int nregs;
527 : :
528 : 10804721 : ret = split_insns (pattern, insn);
529 : 10804721 : nregs = max_reg_num ();
530 : 21609442 : if (nregs > reg_stat.length ())
531 : 3028 : reg_stat.safe_grow_cleared (nregs, true);
532 : 10804721 : return ret;
533 : : }
534 : :
535 : : /* This is used by find_single_use to locate an rtx in LOC that
536 : : contains exactly one use of DEST, which is typically a REG.
537 : : It returns a pointer to the innermost rtx expression
538 : : containing DEST. Appearances of DEST that are being used to
539 : : totally replace it are not counted. */
540 : :
541 : : static rtx *
542 : 31003462 : find_single_use_1 (rtx dest, rtx *loc)
543 : : {
544 : 37500522 : rtx x = *loc;
545 : 37500522 : enum rtx_code code = GET_CODE (x);
546 : 37500522 : rtx *result = NULL;
547 : 37500522 : rtx *this_result;
548 : 37500522 : int i;
549 : 37500522 : const char *fmt;
550 : :
551 : 37500522 : switch (code)
552 : : {
553 : : case CONST:
554 : : case LABEL_REF:
555 : : case SYMBOL_REF:
556 : : CASE_CONST_ANY:
557 : : case CLOBBER:
558 : : return 0;
559 : :
560 : 6453318 : case SET:
561 : : /* If the destination is anything other than PC, a REG or a SUBREG
562 : : of a REG that occupies all of the REG, the insn uses DEST if
563 : : it is mentioned in the destination or the source. Otherwise, we
564 : : need just check the source. */
565 : 6453318 : if (GET_CODE (SET_DEST (x)) != PC
566 : 6453318 : && !REG_P (SET_DEST (x))
567 : 6453652 : && ! (GET_CODE (SET_DEST (x)) == SUBREG
568 : 334 : && REG_P (SUBREG_REG (SET_DEST (x)))
569 : 334 : && !read_modify_subreg_p (SET_DEST (x))))
570 : : break;
571 : :
572 : 6452206 : return find_single_use_1 (dest, &SET_SRC (x));
573 : :
574 : 44854 : case MEM:
575 : 44854 : case SUBREG:
576 : 44854 : return find_single_use_1 (dest, &XEXP (x, 0));
577 : :
578 : : default:
579 : : break;
580 : : }
581 : :
582 : : /* If it wasn't one of the common cases above, check each expression and
583 : : vector of this code. Look for a unique usage of DEST. */
584 : :
585 : 18679099 : fmt = GET_RTX_FORMAT (code);
586 : 49907347 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
587 : : {
588 : 31237313 : if (fmt[i] == 'e')
589 : : {
590 : 30907751 : if (dest == XEXP (x, i)
591 : 30907751 : || (REG_P (dest) && REG_P (XEXP (x, i))
592 : 740602 : && REGNO (dest) == REGNO (XEXP (x, i))))
593 : : this_result = loc;
594 : : else
595 : 24449765 : this_result = find_single_use_1 (dest, &XEXP (x, i));
596 : :
597 : 30907751 : if (result == NULL)
598 : : result = this_result;
599 : 47708 : else if (this_result)
600 : : /* Duplicate usage. */
601 : : return NULL;
602 : : }
603 : 329562 : else if (fmt[i] == 'E')
604 : : {
605 : 51600 : int j;
606 : :
607 : 157031 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
608 : : {
609 : 109260 : if (XVECEXP (x, i, j) == dest
610 : 109260 : || (REG_P (dest)
611 : 109260 : && REG_P (XVECEXP (x, i, j))
612 : 4441 : && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
613 : : this_result = loc;
614 : : else
615 : 109260 : this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
616 : :
617 : 109260 : if (result == NULL)
618 : : result = this_result;
619 : 18289 : else if (this_result)
620 : : return NULL;
621 : : }
622 : : }
623 : : }
624 : :
625 : : return result;
626 : : }
627 : :
628 : :
629 : : /* See if DEST, produced in INSN, is used only a single time in the
630 : : sequel. If so, return a pointer to the innermost rtx expression in which
631 : : it is used.
632 : :
633 : : If PLOC is nonzero, *PLOC is set to the insn containing the single use.
634 : :
635 : : Otherwise, we find the single use by finding an insn that has a
636 : : LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
637 : : only referenced once in that insn, we know that it must be the first
638 : : and last insn referencing DEST. */
639 : :
640 : : static rtx *
641 : 6894187 : find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
642 : : {
643 : 6894187 : basic_block bb;
644 : 6894187 : rtx_insn *next;
645 : 6894187 : rtx *result;
646 : 6894187 : struct insn_link *link;
647 : :
648 : 6894187 : if (!REG_P (dest))
649 : : return 0;
650 : :
651 : 6894187 : bb = BLOCK_FOR_INSN (insn);
652 : 8762250 : for (next = NEXT_INSN (insn);
653 : 8762250 : next && BLOCK_FOR_INSN (next) == bb;
654 : 1868063 : next = NEXT_INSN (next))
655 : 8312500 : if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
656 : : {
657 : 8316941 : FOR_EACH_LOG_LINK (link, next)
658 : 7489507 : if (link->insn == insn && link->regno == REGNO (dest))
659 : : break;
660 : :
661 : 7271871 : if (link)
662 : : {
663 : 6444437 : result = find_single_use_1 (dest, &PATTERN (next));
664 : 6444437 : if (ploc)
665 : 6444437 : *ploc = next;
666 : 6444437 : return result;
667 : : }
668 : : }
669 : :
670 : : return 0;
671 : : }
672 : :
673 : : /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
674 : : insn. The substitution can be undone by undo_all. If INTO is already
675 : : set to NEWVAL, do not record this change. Because computing NEWVAL might
676 : : also call SUBST, we have to compute it before we put anything into
677 : : the undo table. */
678 : :
679 : : static void
680 : 779910380 : do_SUBST (rtx *into, rtx newval)
681 : : {
682 : 779910380 : struct undo *buf;
683 : 779910380 : rtx oldval = *into;
684 : :
685 : 779910380 : if (oldval == newval)
686 : : return;
687 : :
688 : : /* We'd like to catch as many invalid transformations here as
689 : : possible. Unfortunately, there are way too many mode changes
690 : : that are perfectly valid, so we'd waste too much effort for
691 : : little gain doing the checks here. Focus on catching invalid
692 : : transformations involving integer constants. */
693 : 88790458 : if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
694 : 54098064 : && CONST_INT_P (newval))
695 : : {
696 : : /* Sanity check that we're replacing oldval with a CONST_INT
697 : : that is a valid sign-extension for the original mode. */
698 : 1783668 : gcc_assert (INTVAL (newval)
699 : : == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
700 : :
701 : : /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
702 : : CONST_INT is not valid, because after the replacement, the
703 : : original mode would be gone. Unfortunately, we can't tell
704 : : when do_SUBST is called to replace the operand thereof, so we
705 : : perform this test on oldval instead, checking whether an
706 : : invalid replacement took place before we got here. */
707 : 1783668 : gcc_assert (!(GET_CODE (oldval) == SUBREG
708 : : && CONST_INT_P (SUBREG_REG (oldval))));
709 : 1783668 : gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
710 : : && CONST_INT_P (XEXP (oldval, 0))));
711 : : }
712 : :
713 : 88790458 : if (undobuf.frees)
714 : 84645478 : buf = undobuf.frees, undobuf.frees = buf->next;
715 : : else
716 : 4144980 : buf = XNEW (struct undo);
717 : :
718 : 88790458 : buf->kind = UNDO_RTX;
719 : 88790458 : buf->where.r = into;
720 : 88790458 : buf->old_contents.r = oldval;
721 : 88790458 : *into = newval;
722 : :
723 : 88790458 : buf->next = undobuf.undos, undobuf.undos = buf;
724 : : }
725 : :
726 : : #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
727 : :
728 : : /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
729 : : for the value of a HOST_WIDE_INT value (including CONST_INT) is
730 : : not safe. */
731 : :
732 : : static void
733 : 14708393 : do_SUBST_INT (int *into, int newval)
734 : : {
735 : 14708393 : struct undo *buf;
736 : 14708393 : int oldval = *into;
737 : :
738 : 14708393 : if (oldval == newval)
739 : : return;
740 : :
741 : 6305775 : if (undobuf.frees)
742 : 5824574 : buf = undobuf.frees, undobuf.frees = buf->next;
743 : : else
744 : 481201 : buf = XNEW (struct undo);
745 : :
746 : 6305775 : buf->kind = UNDO_INT;
747 : 6305775 : buf->where.i = into;
748 : 6305775 : buf->old_contents.i = oldval;
749 : 6305775 : *into = newval;
750 : :
751 : 6305775 : buf->next = undobuf.undos, undobuf.undos = buf;
752 : : }
753 : :
754 : : #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
755 : :
756 : : /* Similar to SUBST, but just substitute the mode. This is used when
757 : : changing the mode of a pseudo-register, so that any other
758 : : references to the entry in the regno_reg_rtx array will change as
759 : : well. */
760 : :
761 : : static void
762 : 1347307 : subst_mode (int regno, machine_mode newval)
763 : : {
764 : 1347307 : struct undo *buf;
765 : 1347307 : rtx reg = regno_reg_rtx[regno];
766 : 1347307 : machine_mode oldval = GET_MODE (reg);
767 : :
768 : 1347307 : if (oldval == newval)
769 : : return;
770 : :
771 : 1347307 : if (undobuf.frees)
772 : 1273795 : buf = undobuf.frees, undobuf.frees = buf->next;
773 : : else
774 : 73512 : buf = XNEW (struct undo);
775 : :
776 : 1347307 : buf->kind = UNDO_MODE;
777 : 1347307 : buf->where.regno = regno;
778 : 1347307 : buf->old_contents.m = oldval;
779 : 1347307 : adjust_reg_mode (reg, newval);
780 : :
781 : 1347307 : buf->next = undobuf.undos, undobuf.undos = buf;
782 : : }
783 : :
784 : : /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
785 : :
786 : : static void
787 : 61558 : do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
788 : : {
789 : 61558 : struct undo *buf;
790 : 61558 : struct insn_link * oldval = *into;
791 : :
792 : 61558 : if (oldval == newval)
793 : : return;
794 : :
795 : 61558 : if (undobuf.frees)
796 : 58934 : buf = undobuf.frees, undobuf.frees = buf->next;
797 : : else
798 : 2624 : buf = XNEW (struct undo);
799 : :
800 : 61558 : buf->kind = UNDO_LINKS;
801 : 61558 : buf->where.l = into;
802 : 61558 : buf->old_contents.l = oldval;
803 : 61558 : *into = newval;
804 : :
805 : 61558 : buf->next = undobuf.undos, undobuf.undos = buf;
806 : : }
807 : :
808 : : #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
809 : :
810 : : /* Subroutine of try_combine. Determine whether the replacement patterns
811 : : NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
812 : : than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
813 : : that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
814 : : undobuf.other_insn may also both be NULL_RTX. Return false if the cost
815 : : of all the instructions can be estimated and the replacements are more
816 : : expensive than the original sequence. */
817 : :
818 : : static bool
819 : 3936137 : combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
820 : : rtx newpat, rtx newi2pat, rtx newotherpat)
821 : : {
822 : 3936137 : int i0_cost, i1_cost, i2_cost, i3_cost;
823 : 3936137 : int new_i2_cost, new_i3_cost;
824 : 3936137 : int old_cost, new_cost;
825 : :
826 : : /* Lookup the original insn_costs. */
827 : 3936137 : i2_cost = INSN_COST (i2);
828 : 3936137 : i3_cost = INSN_COST (i3);
829 : :
830 : 3936137 : if (i1)
831 : : {
832 : 103273 : i1_cost = INSN_COST (i1);
833 : 103273 : if (i0)
834 : : {
835 : 4834 : i0_cost = INSN_COST (i0);
836 : 4698 : old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
837 : 9521 : ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
838 : : }
839 : : else
840 : : {
841 : 92676 : old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
842 : 191113 : ? i1_cost + i2_cost + i3_cost : 0);
843 : : i0_cost = 0;
844 : : }
845 : : }
846 : : else
847 : : {
848 : 3832864 : old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
849 : : i1_cost = i0_cost = 0;
850 : : }
851 : :
852 : : /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
853 : : correct that. */
854 : 3936137 : if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
855 : 1184 : old_cost -= i1_cost;
856 : :
857 : :
858 : : /* Calculate the replacement insn_costs. */
859 : 3936137 : rtx tmp = PATTERN (i3);
860 : 3936137 : PATTERN (i3) = newpat;
861 : 3936137 : int tmpi = INSN_CODE (i3);
862 : 3936137 : INSN_CODE (i3) = -1;
863 : 3936137 : new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
864 : 3936137 : PATTERN (i3) = tmp;
865 : 3936137 : INSN_CODE (i3) = tmpi;
866 : 3936137 : if (newi2pat)
867 : : {
868 : 192772 : tmp = PATTERN (i2);
869 : 192772 : PATTERN (i2) = newi2pat;
870 : 192772 : tmpi = INSN_CODE (i2);
871 : 192772 : INSN_CODE (i2) = -1;
872 : 192772 : new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
873 : 192772 : PATTERN (i2) = tmp;
874 : 192772 : INSN_CODE (i2) = tmpi;
875 : 192772 : new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
876 : 192772 : ? new_i2_cost + new_i3_cost : 0;
877 : : }
878 : : else
879 : : {
880 : : new_cost = new_i3_cost;
881 : : new_i2_cost = 0;
882 : : }
883 : :
884 : 3936137 : if (undobuf.other_insn)
885 : : {
886 : 194681 : int old_other_cost, new_other_cost;
887 : :
888 : 194681 : old_other_cost = INSN_COST (undobuf.other_insn);
889 : 194681 : tmp = PATTERN (undobuf.other_insn);
890 : 194681 : PATTERN (undobuf.other_insn) = newotherpat;
891 : 194681 : tmpi = INSN_CODE (undobuf.other_insn);
892 : 194681 : INSN_CODE (undobuf.other_insn) = -1;
893 : 194681 : new_other_cost = insn_cost (undobuf.other_insn,
894 : : optimize_this_for_speed_p);
895 : 194681 : PATTERN (undobuf.other_insn) = tmp;
896 : 194681 : INSN_CODE (undobuf.other_insn) = tmpi;
897 : 194681 : if (old_other_cost > 0 && new_other_cost > 0)
898 : : {
899 : 194681 : old_cost += old_other_cost;
900 : 194681 : new_cost += new_other_cost;
901 : : }
902 : : else
903 : : old_cost = 0;
904 : : }
905 : :
906 : : /* Disallow this combination if both new_cost and old_cost are greater than
907 : : zero, and new_cost is greater than old cost. */
908 : 3936137 : bool reject = old_cost > 0 && new_cost > old_cost;
909 : :
910 : 3936137 : if (dump_file)
911 : : {
912 : 484 : fprintf (dump_file, "%s combination of insns ",
913 : : reject ? "rejecting" : "allowing");
914 : 244 : if (i0)
915 : 0 : fprintf (dump_file, "%d, ", INSN_UID (i0));
916 : 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
917 : 1 : fprintf (dump_file, "%d, ", INSN_UID (i1));
918 : 244 : fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
919 : :
920 : 244 : fprintf (dump_file, "original costs ");
921 : 244 : if (i0)
922 : 0 : fprintf (dump_file, "%d + ", i0_cost);
923 : 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
924 : 1 : fprintf (dump_file, "%d + ", i1_cost);
925 : 244 : fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
926 : :
927 : 244 : if (newi2pat)
928 : 19 : fprintf (dump_file, "replacement costs %d + %d = %d\n",
929 : : new_i2_cost, new_i3_cost, new_cost);
930 : : else
931 : 225 : fprintf (dump_file, "replacement cost %d\n", new_cost);
932 : : }
933 : :
934 : 3936137 : if (reject)
935 : : return false;
936 : :
937 : : /* Update the uid_insn_cost array with the replacement costs. */
938 : 3735448 : INSN_COST (i2) = new_i2_cost;
939 : 3735448 : INSN_COST (i3) = new_i3_cost;
940 : 3735448 : if (i1)
941 : : {
942 : 86168 : INSN_COST (i1) = 0;
943 : 86168 : if (i0)
944 : 4708 : INSN_COST (i0) = 0;
945 : : }
946 : :
947 : : return true;
948 : : }
949 : :
950 : :
951 : : /* Delete any insns that copy a register to itself.
952 : : Return true if the CFG was changed. */
953 : :
954 : : static bool
955 : 1008722 : delete_noop_moves (void)
956 : : {
957 : 1008722 : rtx_insn *insn, *next;
958 : 1008722 : basic_block bb;
959 : :
960 : 1008722 : bool edges_deleted = false;
961 : :
962 : 11204471 : FOR_EACH_BB_FN (bb, cfun)
963 : : {
964 : 125036470 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
965 : : {
966 : 114840721 : next = NEXT_INSN (insn);
967 : 114840721 : if (INSN_P (insn) && noop_move_p (insn))
968 : : {
969 : 5672 : if (dump_file)
970 : 0 : fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
971 : :
972 : 5672 : edges_deleted |= delete_insn_and_edges (insn);
973 : : }
974 : : }
975 : : }
976 : :
977 : 1008722 : return edges_deleted;
978 : : }
979 : :
980 : :
981 : : /* Return false if we do not want to (or cannot) combine DEF. */
982 : : static bool
983 : 40143820 : can_combine_def_p (df_ref def)
984 : : {
985 : : /* Do not consider if it is pre/post modification in MEM. */
986 : 40143820 : if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
987 : : return false;
988 : :
989 : 38515567 : unsigned int regno = DF_REF_REGNO (def);
990 : :
991 : : /* Do not combine frame pointer adjustments. */
992 : 38515567 : if ((regno == FRAME_POINTER_REGNUM
993 : 0 : && (!reload_completed || frame_pointer_needed))
994 : 2062 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
995 : 38515567 : && regno == HARD_FRAME_POINTER_REGNUM
996 : : && (!reload_completed || frame_pointer_needed))
997 : 38513505 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
998 : 0 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
999 : 2062 : return false;
1000 : :
1001 : : return true;
1002 : : }
1003 : :
1004 : : /* Return false if we do not want to (or cannot) combine USE. */
1005 : : static bool
1006 : 72840563 : can_combine_use_p (df_ref use)
1007 : : {
1008 : : /* Do not consider the usage of the stack pointer by function call. */
1009 : 0 : if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1010 : 0 : return false;
1011 : :
1012 : : return true;
1013 : : }
1014 : :
1015 : : /* Fill in log links field for all insns. */
1016 : :
1017 : : static void
1018 : 1008722 : create_log_links (void)
1019 : : {
1020 : 1008722 : basic_block bb;
1021 : 1008722 : rtx_insn **next_use;
1022 : 1008722 : rtx_insn *insn;
1023 : 1008722 : df_ref def, use;
1024 : :
1025 : 1008722 : next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1026 : :
1027 : : /* Pass through each block from the end, recording the uses of each
1028 : : register and establishing log links when def is encountered.
1029 : : Note that we do not clear next_use array in order to save time,
1030 : : so we have to test whether the use is in the same basic block as def.
1031 : :
1032 : : There are a few cases below when we do not consider the definition or
1033 : : usage -- these are taken from original flow.c did. Don't ask me why it is
1034 : : done this way; I don't know and if it works, I don't want to know. */
1035 : :
1036 : 11204471 : FOR_EACH_BB_FN (bb, cfun)
1037 : : {
1038 : 125022928 : FOR_BB_INSNS_REVERSE (bb, insn)
1039 : : {
1040 : 114827179 : if (!NONDEBUG_INSN_P (insn))
1041 : 55465480 : continue;
1042 : :
1043 : : /* Log links are created only once. */
1044 : 59361699 : gcc_assert (!LOG_LINKS (insn));
1045 : :
1046 : 480647798 : FOR_EACH_INSN_DEF (def, insn)
1047 : : {
1048 : 421286099 : unsigned int regno = DF_REF_REGNO (def);
1049 : 421286099 : rtx_insn *use_insn;
1050 : :
1051 : 421286099 : if (!next_use[regno])
1052 : 381142279 : continue;
1053 : :
1054 : 40143820 : if (!can_combine_def_p (def))
1055 : 1630315 : continue;
1056 : :
1057 : 38513505 : use_insn = next_use[regno];
1058 : 38513505 : next_use[regno] = NULL;
1059 : :
1060 : 38513505 : if (BLOCK_FOR_INSN (use_insn) != bb)
1061 : 2097204 : continue;
1062 : :
1063 : : /* flow.c claimed:
1064 : :
1065 : : We don't build a LOG_LINK for hard registers contained
1066 : : in ASM_OPERANDs. If these registers get replaced,
1067 : : we might wind up changing the semantics of the insn,
1068 : : even if reload can make what appear to be valid
1069 : : assignments later. */
1070 : 36417149 : if (regno < FIRST_PSEUDO_REGISTER
1071 : 36416301 : && asm_noperands (PATTERN (use_insn)) >= 0)
1072 : 848 : continue;
1073 : :
1074 : : /* Don't add duplicate links between instructions. */
1075 : 36415453 : struct insn_link *links;
1076 : 48663766 : FOR_EACH_LOG_LINK (links, use_insn)
1077 : 12248313 : if (insn == links->insn && regno == links->regno)
1078 : : break;
1079 : :
1080 : 36415453 : if (!links)
1081 : 36415453 : LOG_LINKS (use_insn)
1082 : 72830906 : = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1083 : : }
1084 : :
1085 : 132202262 : FOR_EACH_INSN_USE (use, insn)
1086 : 141151467 : if (can_combine_use_p (use))
1087 : 68310904 : next_use[DF_REF_REGNO (use)] = insn;
1088 : : }
1089 : : }
1090 : :
1091 : 1008722 : free (next_use);
1092 : 1008722 : }
1093 : :
1094 : : /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095 : : true if we found a LOG_LINK that proves that A feeds B. This only works
1096 : : if there are no instructions between A and B which could have a link
1097 : : depending on A, since in that case we would not record a link for B. */
1098 : :
1099 : : static bool
1100 : 11466130 : insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1101 : : {
1102 : 11466130 : struct insn_link *links;
1103 : 14423906 : FOR_EACH_LOG_LINK (links, b)
1104 : 12153265 : if (links->insn == a)
1105 : : return true;
1106 : : return false;
1107 : : }
1108 : :
1109 : : /* Main entry point for combiner. F is the first insn of the function.
1110 : : NREGS is the first unused pseudo-reg number.
1111 : :
1112 : : Return nonzero if the CFG was changed (e.g. if the combiner has
1113 : : turned an indirect jump instruction into a direct jump). */
1114 : : static bool
1115 : 1051273 : combine_instructions (rtx_insn *f, unsigned int nregs)
1116 : : {
1117 : 1051273 : rtx_insn *insn, *next;
1118 : 1051273 : struct insn_link *links, *nextlinks;
1119 : 1051273 : rtx_insn *first;
1120 : 1051273 : basic_block last_bb;
1121 : :
1122 : 1051273 : bool new_direct_jump_p = false;
1123 : :
1124 : 3161502 : for (first = f; first && !NONDEBUG_INSN_P (first); )
1125 : 2110229 : first = NEXT_INSN (first);
1126 : 1051273 : if (!first)
1127 : : return false;
1128 : :
1129 : 1008722 : combine_attempts = 0;
1130 : 1008722 : combine_merges = 0;
1131 : 1008722 : combine_extras = 0;
1132 : 1008722 : combine_successes = 0;
1133 : :
1134 : 1008722 : rtl_hooks = combine_rtl_hooks;
1135 : :
1136 : 1008722 : reg_stat.safe_grow_cleared (nregs, true);
1137 : :
1138 : 1008722 : init_recog_no_volatile ();
1139 : :
1140 : : /* Allocate array for insn info. */
1141 : 1008722 : max_uid_known = get_max_uid ();
1142 : 1008722 : uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1143 : 1008722 : uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1144 : 1008722 : gcc_obstack_init (&insn_link_obstack);
1145 : :
1146 : 1008722 : nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1147 : :
1148 : : /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1149 : : problems when, for example, we have j <<= 1 in a loop. */
1150 : :
1151 : 1008722 : nonzero_sign_valid = 0;
1152 : 1008722 : label_tick = label_tick_ebb_start = 1;
1153 : :
1154 : : /* Scan all SETs and see if we can deduce anything about what
1155 : : bits are known to be zero for some registers and how many copies
1156 : : of the sign bit are known to exist for those registers.
1157 : :
1158 : : Also set any known values so that we can use it while searching
1159 : : for what bits are known to be set. */
1160 : :
1161 : 1008722 : setup_incoming_promotions (first);
1162 : : /* Allow the entry block and the first block to fall into the same EBB.
1163 : : Conceptually the incoming promotions are assigned to the entry block. */
1164 : 1008722 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1165 : :
1166 : 1008722 : create_log_links ();
1167 : 11204471 : FOR_EACH_BB_FN (this_basic_block, cfun)
1168 : : {
1169 : 10195749 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1170 : 10195749 : last_call_luid = 0;
1171 : 10195749 : mem_last_set = -1;
1172 : :
1173 : 10195749 : label_tick++;
1174 : 10195749 : if (!single_pred_p (this_basic_block)
1175 : 10195749 : || single_pred (this_basic_block) != last_bb)
1176 : 4828783 : label_tick_ebb_start = label_tick;
1177 : 10195749 : last_bb = this_basic_block;
1178 : :
1179 : 125022928 : FOR_BB_INSNS (this_basic_block, insn)
1180 : 114827179 : if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1181 : : {
1182 : 98714429 : rtx links;
1183 : :
1184 : 98714429 : subst_low_luid = DF_INSN_LUID (insn);
1185 : 98714429 : subst_insn = insn;
1186 : :
1187 : 98714429 : note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1188 : 98714429 : record_dead_and_set_regs (insn);
1189 : :
1190 : 98714429 : if (AUTO_INC_DEC)
1191 : : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1192 : : if (REG_NOTE_KIND (links) == REG_INC)
1193 : : set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1194 : : insn);
1195 : :
1196 : : /* Record the current insn_cost of this instruction. */
1197 : 98714429 : INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1198 : 98714429 : if (dump_file)
1199 : : {
1200 : 1723 : fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1201 : 1723 : dump_insn_slim (dump_file, insn);
1202 : : }
1203 : : }
1204 : : }
1205 : :
1206 : 1008722 : nonzero_sign_valid = 1;
1207 : :
1208 : : /* Now scan all the insns in forward order. */
1209 : 1008722 : label_tick = label_tick_ebb_start = 1;
1210 : 1008722 : init_reg_last ();
1211 : 1008722 : setup_incoming_promotions (first);
1212 : 1008722 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1213 : 1008722 : int max_combine = param_max_combine_insns;
1214 : :
1215 : 11204471 : FOR_EACH_BB_FN (this_basic_block, cfun)
1216 : : {
1217 : 10195749 : rtx_insn *last_combined_insn = NULL;
1218 : :
1219 : : /* Ignore instruction combination in basic blocks that are going to
1220 : : be removed as unreachable anyway. See PR82386. */
1221 : 10195749 : if (EDGE_COUNT (this_basic_block->preds) == 0)
1222 : 1837 : continue;
1223 : :
1224 : 10193912 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1225 : 10193912 : last_call_luid = 0;
1226 : 10193912 : mem_last_set = -1;
1227 : :
1228 : 10193912 : label_tick++;
1229 : 10193912 : if (!single_pred_p (this_basic_block)
1230 : 10193912 : || single_pred (this_basic_block) != last_bb)
1231 : 4828591 : label_tick_ebb_start = label_tick;
1232 : 10193912 : last_bb = this_basic_block;
1233 : :
1234 : 10193912 : rtl_profile_for_bb (this_basic_block);
1235 : 10193912 : for (insn = BB_HEAD (this_basic_block);
1236 : 129176164 : insn != NEXT_INSN (BB_END (this_basic_block));
1237 : 115274109 : insn = next ? next : NEXT_INSN (insn))
1238 : : {
1239 : 118982252 : next = 0;
1240 : 118982252 : if (!NONDEBUG_INSN_P (insn))
1241 : 55651740 : continue;
1242 : :
1243 : : while (last_combined_insn
1244 : 63332671 : && (!NONDEBUG_INSN_P (last_combined_insn)
1245 : 53365159 : || last_combined_insn->deleted ()))
1246 : 2159 : last_combined_insn = PREV_INSN (last_combined_insn);
1247 : 63330512 : if (last_combined_insn == NULL_RTX
1248 : 53364482 : || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1249 : 116694786 : || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1250 : : last_combined_insn = insn;
1251 : :
1252 : : /* See if we know about function return values before this
1253 : : insn based upon SUBREG flags. */
1254 : 63330512 : check_promoted_subreg (insn, PATTERN (insn));
1255 : :
1256 : : /* See if we can find hardregs and subreg of pseudos in
1257 : : narrower modes. This could help turning TRUNCATEs
1258 : : into SUBREGs. */
1259 : 63330512 : note_uses (&PATTERN (insn), record_truncated_values, NULL);
1260 : :
1261 : : /* Try this insn with each insn it links back to. */
1262 : :
1263 : 98905675 : FOR_EACH_LOG_LINK (links, insn)
1264 : 39175947 : if ((next = try_combine (insn, links->insn, NULL,
1265 : : NULL, &new_direct_jump_p,
1266 : : last_combined_insn)) != 0)
1267 : : {
1268 : 3600784 : statistics_counter_event (cfun, "two-insn combine", 1);
1269 : 3600784 : goto retry;
1270 : : }
1271 : :
1272 : : /* Try each sequence of three linked insns ending with this one. */
1273 : :
1274 : 59729728 : if (max_combine >= 3)
1275 : 94759494 : FOR_EACH_LOG_LINK (links, insn)
1276 : : {
1277 : 35200003 : rtx_insn *link = links->insn;
1278 : :
1279 : : /* If the linked insn has been replaced by a note, then there
1280 : : is no point in pursuing this chain any further. */
1281 : 35200003 : if (NOTE_P (link))
1282 : 227 : continue;
1283 : :
1284 : 52404053 : FOR_EACH_LOG_LINK (nextlinks, link)
1285 : 17268654 : if ((next = try_combine (insn, link, nextlinks->insn,
1286 : : NULL, &new_direct_jump_p,
1287 : : last_combined_insn)) != 0)
1288 : : {
1289 : 64377 : statistics_counter_event (cfun, "three-insn combine", 1);
1290 : 64377 : goto retry;
1291 : : }
1292 : : }
1293 : :
1294 : : /* Try combining an insn with two different insns whose results it
1295 : : uses. */
1296 : 59559491 : if (max_combine >= 3)
1297 : 94665036 : FOR_EACH_LOG_LINK (links, insn)
1298 : 47111860 : for (nextlinks = links->next; nextlinks;
1299 : 11993456 : nextlinks = nextlinks->next)
1300 : 12006315 : if ((next = try_combine (insn, links->insn,
1301 : : nextlinks->insn, NULL,
1302 : : &new_direct_jump_p,
1303 : : last_combined_insn)) != 0)
1304 : :
1305 : : {
1306 : 12859 : statistics_counter_event (cfun, "three-insn combine", 1);
1307 : 12859 : goto retry;
1308 : : }
1309 : :
1310 : : /* Try four-instruction combinations. */
1311 : 59546632 : if (max_combine >= 4)
1312 : 94643969 : FOR_EACH_LOG_LINK (links, insn)
1313 : : {
1314 : 35101978 : struct insn_link *next1;
1315 : 35101978 : rtx_insn *link = links->insn;
1316 : :
1317 : : /* If the linked insn has been replaced by a note, then there
1318 : : is no point in pursuing this chain any further. */
1319 : 35101978 : if (NOTE_P (link))
1320 : 227 : continue;
1321 : :
1322 : 52288045 : FOR_EACH_LOG_LINK (next1, link)
1323 : : {
1324 : 17187442 : rtx_insn *link1 = next1->insn;
1325 : 17187442 : if (NOTE_P (link1))
1326 : 72 : continue;
1327 : : /* I0 -> I1 -> I2 -> I3. */
1328 : 28158822 : FOR_EACH_LOG_LINK (nextlinks, link1)
1329 : 10972510 : if ((next = try_combine (insn, link, link1,
1330 : : nextlinks->insn,
1331 : : &new_direct_jump_p,
1332 : : last_combined_insn)) != 0)
1333 : : {
1334 : 1058 : statistics_counter_event (cfun, "four-insn combine", 1);
1335 : 1058 : goto retry;
1336 : : }
1337 : : /* I0, I1 -> I2, I2 -> I3. */
1338 : 21106958 : for (nextlinks = next1->next; nextlinks;
1339 : 3920646 : nextlinks = nextlinks->next)
1340 : 3920736 : if ((next = try_combine (insn, link, link1,
1341 : : nextlinks->insn,
1342 : : &new_direct_jump_p,
1343 : : last_combined_insn)) != 0)
1344 : : {
1345 : 90 : statistics_counter_event (cfun, "four-insn combine", 1);
1346 : 90 : goto retry;
1347 : : }
1348 : : }
1349 : :
1350 : 47090320 : for (next1 = links->next; next1; next1 = next1->next)
1351 : : {
1352 : 11993131 : rtx_insn *link1 = next1->insn;
1353 : 11993131 : if (NOTE_P (link1))
1354 : 8 : continue;
1355 : : /* I0 -> I2; I1, I2 -> I3. */
1356 : 15147038 : FOR_EACH_LOG_LINK (nextlinks, link)
1357 : 3157140 : if ((next = try_combine (insn, link, link1,
1358 : : nextlinks->insn,
1359 : : &new_direct_jump_p,
1360 : : last_combined_insn)) != 0)
1361 : : {
1362 : 3225 : statistics_counter_event (cfun, "four-insn combine", 1);
1363 : 3225 : goto retry;
1364 : : }
1365 : : /* I0 -> I1; I1, I2 -> I3. */
1366 : 15342012 : FOR_EACH_LOG_LINK (nextlinks, link1)
1367 : 3352303 : if ((next = try_combine (insn, link, link1,
1368 : : nextlinks->insn,
1369 : : &new_direct_jump_p,
1370 : : last_combined_insn)) != 0)
1371 : : {
1372 : 189 : statistics_counter_event (cfun, "four-insn combine", 1);
1373 : 189 : goto retry;
1374 : : }
1375 : : }
1376 : : }
1377 : :
1378 : : /* Try this insn with each REG_EQUAL note it links back to. */
1379 : 94781756 : FOR_EACH_LOG_LINK (links, insn)
1380 : : {
1381 : 35159387 : rtx set, note;
1382 : 35159387 : rtx_insn *temp = links->insn;
1383 : 35159387 : if ((set = single_set (temp)) != 0
1384 : 34783517 : && (note = find_reg_equal_equiv_note (temp)) != 0
1385 : 2476680 : && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1386 : 2476680 : && ! side_effects_p (SET_SRC (set))
1387 : : /* Avoid using a register that may already been marked
1388 : : dead by an earlier instruction. */
1389 : 2476680 : && ! unmentioned_reg_p (note, SET_SRC (set))
1390 : 36395426 : && (GET_MODE (note) == VOIDmode
1391 : 24272 : ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1392 : 1211767 : : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1393 : 1211739 : && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1394 : 0 : || (GET_MODE (XEXP (SET_DEST (set), 0))
1395 : : == GET_MODE (note))))))
1396 : : {
1397 : : /* Temporarily replace the set's source with the
1398 : : contents of the REG_EQUAL note. The insn will
1399 : : be deleted or recognized by try_combine. */
1400 : 1235994 : rtx orig_src = SET_SRC (set);
1401 : 1235994 : rtx orig_dest = SET_DEST (set);
1402 : 1235994 : if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1403 : 0 : SET_DEST (set) = XEXP (SET_DEST (set), 0);
1404 : 1235994 : SET_SRC (set) = note;
1405 : 1235994 : i2mod = temp;
1406 : 1235994 : i2mod_old_rhs = copy_rtx (orig_src);
1407 : 1235994 : i2mod_new_rhs = copy_rtx (note);
1408 : 1235994 : next = try_combine (insn, i2mod, NULL, NULL,
1409 : : &new_direct_jump_p,
1410 : : last_combined_insn);
1411 : 1235994 : i2mod = NULL;
1412 : 1235994 : if (next)
1413 : : {
1414 : 25561 : statistics_counter_event (cfun, "insn-with-note combine", 1);
1415 : 25561 : goto retry;
1416 : : }
1417 : 1210433 : INSN_CODE (temp) = -1;
1418 : 1210433 : SET_SRC (set) = orig_src;
1419 : 1210433 : SET_DEST (set) = orig_dest;
1420 : : }
1421 : : }
1422 : :
1423 : 59622369 : if (!NOTE_P (insn))
1424 : 59622369 : record_dead_and_set_regs (insn);
1425 : :
1426 : 0 : retry:
1427 : 118982252 : ;
1428 : : }
1429 : : }
1430 : :
1431 : 1008722 : default_rtl_profile ();
1432 : 1008722 : clear_bb_flags ();
1433 : :
1434 : 1008722 : if (purge_all_dead_edges ())
1435 : 1224 : new_direct_jump_p = true;
1436 : 1008722 : if (delete_noop_moves ())
1437 : 0 : new_direct_jump_p = true;
1438 : :
1439 : : /* Clean up. */
1440 : 1008722 : obstack_free (&insn_link_obstack, NULL);
1441 : 1008722 : free (uid_log_links);
1442 : 1008722 : free (uid_insn_cost);
1443 : 1008722 : reg_stat.release ();
1444 : :
1445 : 1008722 : {
1446 : 1008722 : struct undo *undo, *next;
1447 : 5711039 : for (undo = undobuf.frees; undo; undo = next)
1448 : : {
1449 : 4702317 : next = undo->next;
1450 : 4702317 : free (undo);
1451 : : }
1452 : 1008722 : undobuf.frees = 0;
1453 : : }
1454 : :
1455 : 1008722 : statistics_counter_event (cfun, "attempts", combine_attempts);
1456 : 1008722 : statistics_counter_event (cfun, "merges", combine_merges);
1457 : 1008722 : statistics_counter_event (cfun, "extras", combine_extras);
1458 : 1008722 : statistics_counter_event (cfun, "successes", combine_successes);
1459 : :
1460 : 1008722 : nonzero_sign_valid = 0;
1461 : 1008722 : rtl_hooks = general_rtl_hooks;
1462 : :
1463 : : /* Make recognizer allow volatile MEMs again. */
1464 : 1008722 : init_recog ();
1465 : :
1466 : 1008722 : return new_direct_jump_p;
1467 : : }
1468 : :
1469 : : /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1470 : :
1471 : : static void
1472 : 1008722 : init_reg_last (void)
1473 : : {
1474 : 1008722 : unsigned int i;
1475 : 1008722 : reg_stat_type *p;
1476 : :
1477 : 141415625 : FOR_EACH_VEC_ELT (reg_stat, i, p)
1478 : 140406903 : memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1479 : 1008722 : }
1480 : :
1481 : : /* Set up any promoted values for incoming argument registers. */
1482 : :
1483 : : static void
1484 : 2017444 : setup_incoming_promotions (rtx_insn *first)
1485 : : {
1486 : 2017444 : tree arg;
1487 : 2017444 : bool strictly_local = false;
1488 : :
1489 : 5296752 : for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1490 : 3279308 : arg = DECL_CHAIN (arg))
1491 : : {
1492 : 3279308 : rtx x, reg = DECL_INCOMING_RTL (arg);
1493 : 3279308 : int uns1, uns3;
1494 : 3279308 : machine_mode mode1, mode2, mode3, mode4;
1495 : :
1496 : : /* Only continue if the incoming argument is in a register. */
1497 : 3279308 : if (!REG_P (reg))
1498 : 3279232 : continue;
1499 : :
1500 : : /* Determine, if possible, whether all call sites of the current
1501 : : function lie within the current compilation unit. (This does
1502 : : take into account the exporting of a function via taking its
1503 : : address, and so forth.) */
1504 : 2562222 : strictly_local
1505 : 2562222 : = cgraph_node::local_info_node (current_function_decl)->local;
1506 : :
1507 : : /* The mode and signedness of the argument before any promotions happen
1508 : : (equal to the mode of the pseudo holding it at that stage). */
1509 : 2562222 : mode1 = TYPE_MODE (TREE_TYPE (arg));
1510 : 2562222 : uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1511 : :
1512 : : /* The mode and signedness of the argument after any source language and
1513 : : TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1514 : 2562222 : mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1515 : 2562222 : uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1516 : :
1517 : : /* The mode and signedness of the argument as it is actually passed,
1518 : : see assign_parm_setup_reg in function.cc. */
1519 : 2562222 : mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1520 : 2562222 : TREE_TYPE (cfun->decl), 0);
1521 : :
1522 : : /* The mode of the register in which the argument is being passed. */
1523 : 2562222 : mode4 = GET_MODE (reg);
1524 : :
1525 : : /* Eliminate sign extensions in the callee when:
1526 : : (a) A mode promotion has occurred; */
1527 : 2562222 : if (mode1 == mode3)
1528 : 2562146 : continue;
1529 : : /* (b) The mode of the register is the same as the mode of
1530 : : the argument as it is passed; */
1531 : 76 : if (mode3 != mode4)
1532 : 0 : continue;
1533 : : /* (c) There's no language level extension; */
1534 : 76 : if (mode1 == mode2)
1535 : : ;
1536 : : /* (c.1) All callers are from the current compilation unit. If that's
1537 : : the case we don't have to rely on an ABI, we only have to know
1538 : : what we're generating right now, and we know that we will do the
1539 : : mode1 to mode2 promotion with the given sign. */
1540 : 0 : else if (!strictly_local)
1541 : 0 : continue;
1542 : : /* (c.2) The combination of the two promotions is useful. This is
1543 : : true when the signs match, or if the first promotion is unsigned.
1544 : : In the later case, (sign_extend (zero_extend x)) is the same as
1545 : : (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1546 : 0 : else if (uns1)
1547 : 0 : uns3 = true;
1548 : 0 : else if (uns3)
1549 : 0 : continue;
1550 : :
1551 : : /* Record that the value was promoted from mode1 to mode3,
1552 : : so that any sign extension at the head of the current
1553 : : function may be eliminated. */
1554 : 76 : x = gen_rtx_CLOBBER (mode1, const0_rtx);
1555 : 76 : x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1556 : 76 : record_value_for_reg (reg, first, x);
1557 : : }
1558 : 2017444 : }
1559 : :
1560 : : /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1561 : : that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1562 : : because some machines (maybe most) will actually do the sign-extension and
1563 : : this is the conservative approach.
1564 : :
1565 : : ??? For 2.5, try to tighten up the MD files in this regard instead of this
1566 : : kludge. */
1567 : :
1568 : : static rtx
1569 : 0 : sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1570 : : {
1571 : 0 : scalar_int_mode int_mode;
1572 : 0 : if (CONST_INT_P (src)
1573 : 0 : && is_a <scalar_int_mode> (mode, &int_mode)
1574 : 0 : && GET_MODE_PRECISION (int_mode) < prec
1575 : 0 : && INTVAL (src) > 0
1576 : 0 : && val_signbit_known_set_p (int_mode, INTVAL (src)))
1577 : 0 : src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1578 : :
1579 : 0 : return src;
1580 : : }
1581 : :
1582 : : /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1583 : : and SET. */
1584 : :
1585 : : static void
1586 : 22292232 : update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1587 : : rtx x)
1588 : : {
1589 : 22292232 : rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1590 : 22292232 : unsigned HOST_WIDE_INT bits = 0;
1591 : 22292232 : rtx reg_equal = NULL, src = SET_SRC (set);
1592 : 22292232 : unsigned int num = 0;
1593 : :
1594 : 22292232 : if (reg_equal_note)
1595 : 921178 : reg_equal = XEXP (reg_equal_note, 0);
1596 : :
1597 : 22292232 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
1598 : : {
1599 : : src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1600 : : if (reg_equal)
1601 : : reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1602 : : }
1603 : :
1604 : : /* Don't call nonzero_bits if it cannot change anything. */
1605 : 22292232 : if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1606 : : {
1607 : 19334389 : machine_mode mode = GET_MODE (x);
1608 : 19334389 : if (GET_MODE_CLASS (mode) == MODE_INT
1609 : 19334389 : && HWI_COMPUTABLE_MODE_P (mode))
1610 : 19334257 : mode = nonzero_bits_mode;
1611 : 19334389 : bits = nonzero_bits (src, mode);
1612 : 19334389 : if (reg_equal && bits)
1613 : 875806 : bits &= nonzero_bits (reg_equal, mode);
1614 : 19334389 : rsp->nonzero_bits |= bits;
1615 : : }
1616 : :
1617 : : /* Don't call num_sign_bit_copies if it cannot change anything. */
1618 : 22292232 : if (rsp->sign_bit_copies != 1)
1619 : : {
1620 : 19190060 : num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1621 : 19190060 : if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1622 : : {
1623 : 872773 : unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1624 : 872773 : if (num == 0 || numeq > num)
1625 : 19190060 : num = numeq;
1626 : : }
1627 : 19190060 : if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1628 : 18527294 : rsp->sign_bit_copies = num;
1629 : : }
1630 : 22292232 : }
1631 : :
1632 : : /* Called via note_stores. If X is a pseudo that is narrower than
1633 : : HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1634 : :
1635 : : If we are setting only a portion of X and we can't figure out what
1636 : : portion, assume all bits will be used since we don't know what will
1637 : : be happening.
1638 : :
1639 : : Similarly, set how many bits of X are known to be copies of the sign bit
1640 : : at all locations in the function. This is the smallest number implied
1641 : : by any set of X. */
1642 : :
1643 : : static void
1644 : 69223527 : set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1645 : : {
1646 : 69223527 : rtx_insn *insn = (rtx_insn *) data;
1647 : 69223527 : scalar_int_mode mode;
1648 : :
1649 : 69223527 : if (REG_P (x)
1650 : 55822554 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1651 : : /* If this register is undefined at the start of the file, we can't
1652 : : say what its contents were. */
1653 : 55548754 : && ! REGNO_REG_SET_P
1654 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1655 : 27654878 : && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1656 : 92438446 : && HWI_COMPUTABLE_MODE_P (mode))
1657 : : {
1658 : 22497870 : reg_stat_type *rsp = ®_stat[REGNO (x)];
1659 : :
1660 : 22497870 : if (set == 0 || GET_CODE (set) == CLOBBER)
1661 : : {
1662 : 21572 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1663 : 21572 : rsp->sign_bit_copies = 1;
1664 : 21572 : return;
1665 : : }
1666 : :
1667 : : /* If this register is being initialized using itself, and the
1668 : : register is uninitialized in this basic block, and there are
1669 : : no LOG_LINKS which set the register, then part of the
1670 : : register is uninitialized. In that case we can't assume
1671 : : anything about the number of nonzero bits.
1672 : :
1673 : : ??? We could do better if we checked this in
1674 : : reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1675 : : could avoid making assumptions about the insn which initially
1676 : : sets the register, while still using the information in other
1677 : : insns. We would have to be careful to check every insn
1678 : : involved in the combination. */
1679 : :
1680 : 22476298 : if (insn
1681 : 21223125 : && reg_referenced_p (x, PATTERN (insn))
1682 : 25210654 : && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1683 : : REGNO (x)))
1684 : : {
1685 : 280241 : struct insn_link *link;
1686 : :
1687 : 446439 : FOR_EACH_LOG_LINK (link, insn)
1688 : 358126 : if (dead_or_set_p (link->insn, x))
1689 : : break;
1690 : 280241 : if (!link)
1691 : : {
1692 : 88313 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1693 : 88313 : rsp->sign_bit_copies = 1;
1694 : 88313 : return;
1695 : : }
1696 : : }
1697 : :
1698 : : /* If this is a complex assignment, see if we can convert it into a
1699 : : simple assignment. */
1700 : 22387985 : set = expand_field_assignment (set);
1701 : :
1702 : : /* If this is a simple assignment, or we have a paradoxical SUBREG,
1703 : : set what we know about X. */
1704 : :
1705 : 22387985 : if (SET_DEST (set) == x
1706 : 22387985 : || (paradoxical_subreg_p (SET_DEST (set))
1707 : 3100 : && SUBREG_REG (SET_DEST (set)) == x))
1708 : 22292232 : update_rsp_from_reg_equal (rsp, insn, set, x);
1709 : : else
1710 : : {
1711 : 95753 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1712 : 95753 : rsp->sign_bit_copies = 1;
1713 : : }
1714 : : }
1715 : : }
1716 : :
1717 : : /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1718 : : optionally insns that were previously combined into I3 or that will be
1719 : : combined into the merger of INSN and I3. The order is PRED, PRED2,
1720 : : INSN, SUCC, SUCC2, I3.
1721 : :
1722 : : Return false if the combination is not allowed for any reason.
1723 : :
1724 : : If the combination is allowed, *PDEST will be set to the single
1725 : : destination of INSN and *PSRC to the single source, and this function
1726 : : will return true. */
1727 : :
1728 : : static bool
1729 : 57057891 : can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1730 : : rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1731 : : rtx *pdest, rtx *psrc)
1732 : : {
1733 : 57057891 : int i;
1734 : 57057891 : const_rtx set = 0;
1735 : 57057891 : rtx src, dest;
1736 : 57057891 : rtx_insn *p;
1737 : 57057891 : rtx link;
1738 : 57057891 : bool all_adjacent = true;
1739 : 57057891 : bool (*is_volatile_p) (const_rtx);
1740 : :
1741 : 57057891 : if (succ)
1742 : : {
1743 : 12730524 : if (succ2)
1744 : : {
1745 : 1580401 : if (next_active_insn (succ2) != i3)
1746 : 163645 : all_adjacent = false;
1747 : 1580401 : if (next_active_insn (succ) != succ2)
1748 : 1798981 : all_adjacent = false;
1749 : : }
1750 : 11150123 : else if (next_active_insn (succ) != i3)
1751 : 1798981 : all_adjacent = false;
1752 : 12730524 : if (next_active_insn (insn) != succ)
1753 : 15966419 : all_adjacent = false;
1754 : : }
1755 : 44327367 : else if (next_active_insn (insn) != i3)
1756 : 15966419 : all_adjacent = false;
1757 : :
1758 : : /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1759 : : or a PARALLEL consisting of such a SET and CLOBBERs.
1760 : :
1761 : : If INSN has CLOBBER parallel parts, ignore them for our processing.
1762 : : By definition, these happen during the execution of the insn. When it
1763 : : is merged with another insn, all bets are off. If they are, in fact,
1764 : : needed and aren't also supplied in I3, they may be added by
1765 : : recog_for_combine. Otherwise, it won't match.
1766 : :
1767 : : We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1768 : : note.
1769 : :
1770 : : Get the source and destination of INSN. If more than one, can't
1771 : : combine. */
1772 : :
1773 : 57057891 : if (GET_CODE (PATTERN (insn)) == SET)
1774 : : set = PATTERN (insn);
1775 : 15028237 : else if (GET_CODE (PATTERN (insn)) == PARALLEL
1776 : 15028237 : && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1777 : : {
1778 : 44968175 : for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1779 : : {
1780 : 30410322 : rtx elt = XVECEXP (PATTERN (insn), 0, i);
1781 : :
1782 : 30410322 : switch (GET_CODE (elt))
1783 : : {
1784 : : /* This is important to combine floating point insns
1785 : : for the SH4 port. */
1786 : 83082 : case USE:
1787 : : /* Combining an isolated USE doesn't make sense.
1788 : : We depend here on combinable_i3pat to reject them. */
1789 : : /* The code below this loop only verifies that the inputs of
1790 : : the SET in INSN do not change. We call reg_set_between_p
1791 : : to verify that the REG in the USE does not change between
1792 : : I3 and INSN.
1793 : : If the USE in INSN was for a pseudo register, the matching
1794 : : insn pattern will likely match any register; combining this
1795 : : with any other USE would only be safe if we knew that the
1796 : : used registers have identical values, or if there was
1797 : : something to tell them apart, e.g. different modes. For
1798 : : now, we forgo such complicated tests and simply disallow
1799 : : combining of USES of pseudo registers with any other USE. */
1800 : 83082 : if (REG_P (XEXP (elt, 0))
1801 : 83082 : && GET_CODE (PATTERN (i3)) == PARALLEL)
1802 : : {
1803 : 224 : rtx i3pat = PATTERN (i3);
1804 : 224 : int i = XVECLEN (i3pat, 0) - 1;
1805 : 224 : unsigned int regno = REGNO (XEXP (elt, 0));
1806 : :
1807 : 458 : do
1808 : : {
1809 : 458 : rtx i3elt = XVECEXP (i3pat, 0, i);
1810 : :
1811 : 458 : if (GET_CODE (i3elt) == USE
1812 : 208 : && REG_P (XEXP (i3elt, 0))
1813 : 692 : && (REGNO (XEXP (i3elt, 0)) == regno
1814 : 182 : ? reg_set_between_p (XEXP (elt, 0),
1815 : 26 : PREV_INSN (insn), i3)
1816 : : : regno >= FIRST_PSEUDO_REGISTER))
1817 : 182 : return false;
1818 : : }
1819 : 276 : while (--i >= 0);
1820 : : }
1821 : : break;
1822 : :
1823 : : /* We can ignore CLOBBERs. */
1824 : : case CLOBBER:
1825 : : break;
1826 : :
1827 : 15586068 : case SET:
1828 : : /* Ignore SETs whose result isn't used but not those that
1829 : : have side-effects. */
1830 : 15586068 : if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1831 : 186699 : && insn_nothrow_p (insn)
1832 : 15759065 : && !side_effects_p (elt))
1833 : : break;
1834 : :
1835 : : /* If we have already found a SET, this is a second one and
1836 : : so we cannot combine with this insn. */
1837 : 15489988 : if (set)
1838 : : return false;
1839 : :
1840 : : set = elt;
1841 : : break;
1842 : :
1843 : : default:
1844 : : /* Anything else means we can't combine. */
1845 : : return false;
1846 : : }
1847 : : }
1848 : :
1849 : 14557853 : if (set == 0
1850 : : /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1851 : : so don't do anything with it. */
1852 : 14557853 : || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1853 : : return false;
1854 : : }
1855 : : else
1856 : : return false;
1857 : :
1858 : : if (set == 0)
1859 : : return false;
1860 : :
1861 : : /* The simplification in expand_field_assignment may call back to
1862 : : get_last_value, so set safe guard here. */
1863 : 56569246 : subst_low_luid = DF_INSN_LUID (insn);
1864 : :
1865 : 56569246 : set = expand_field_assignment (set);
1866 : 56569246 : src = SET_SRC (set), dest = SET_DEST (set);
1867 : :
1868 : : /* Do not eliminate user-specified register if it is in an
1869 : : asm input because we may break the register asm usage defined
1870 : : in GCC manual if allow to do so.
1871 : : Be aware that this may cover more cases than we expect but this
1872 : : should be harmless. */
1873 : 56040049 : if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1874 : 56569248 : && extract_asm_operands (PATTERN (i3)))
1875 : : return false;
1876 : :
1877 : : /* Don't eliminate a store in the stack pointer. */
1878 : 56569246 : if (dest == stack_pointer_rtx
1879 : : /* Don't combine with an insn that sets a register to itself if it has
1880 : : a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1881 : 54656758 : || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1882 : : /* Can't merge an ASM_OPERANDS. */
1883 : 54656758 : || GET_CODE (src) == ASM_OPERANDS
1884 : : /* Can't merge a function call. */
1885 : 54653476 : || GET_CODE (src) == CALL
1886 : : /* Don't eliminate a function call argument. */
1887 : 54653476 : || (CALL_P (i3)
1888 : 8432425 : && (find_reg_fusage (i3, USE, dest)
1889 : 186787 : || (REG_P (dest)
1890 : 186787 : && REGNO (dest) < FIRST_PSEUDO_REGISTER
1891 : 162 : && global_regs[REGNO (dest)])))
1892 : : /* Don't substitute into an incremented register. */
1893 : : || FIND_REG_INC_NOTE (i3, dest)
1894 : : || (succ && FIND_REG_INC_NOTE (succ, dest))
1895 : 54653476 : || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1896 : : /* Don't substitute into a non-local goto, this confuses CFG. */
1897 : 46407836 : || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1898 : : /* Make sure that DEST is not used after INSN but before SUCC, or
1899 : : after SUCC and before SUCC2, or after SUCC2 but before I3. */
1900 : 46407115 : || (!all_adjacent
1901 : 11276492 : && ((succ2
1902 : 707707 : && (reg_used_between_p (dest, succ2, i3)
1903 : 689134 : || reg_used_between_p (dest, succ, succ2)))
1904 : 11239752 : || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1905 : 11013414 : || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1906 : 11013414 : || (succ
1907 : : /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1908 : : that case SUCC is not in the insn stream, so use SUCC2
1909 : : instead for this test. */
1910 : 8815854 : && reg_used_between_p (dest, insn,
1911 : : succ2
1912 : 670967 : && INSN_UID (succ) == INSN_UID (succ2)
1913 : : ? succ2 : succ))))
1914 : : /* Make sure that the value that is to be substituted for the register
1915 : : does not use any registers whose values alter in between. However,
1916 : : If the insns are adjacent, a use can't cross a set even though we
1917 : : think it might (this can happen for a sequence of insns each setting
1918 : : the same destination; last_set of that register might point to
1919 : : a NOTE). If INSN has a REG_EQUIV note, the register is always
1920 : : equivalent to the memory so the substitution is valid even if there
1921 : : are intervening stores. Also, don't move a volatile asm or
1922 : : UNSPEC_VOLATILE across any other insns. */
1923 : : || (! all_adjacent
1924 : 11013414 : && (((!MEM_P (src)
1925 : 3045337 : || ! find_reg_note (insn, REG_EQUIV, src))
1926 : 10899679 : && modified_between_p (src, insn, i3))
1927 : 10116127 : || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1928 : 10116127 : || GET_CODE (src) == UNSPEC_VOLATILE))
1929 : : /* Don't combine across a CALL_INSN, because that would possibly
1930 : : change whether the life span of some REGs crosses calls or not,
1931 : : and it is a pain to update that information.
1932 : : Exception: if source is a constant, moving it later can't hurt.
1933 : : Accept that as a special case. */
1934 : 101805398 : || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1935 : 11652101 : return false;
1936 : :
1937 : : /* DEST must be a REG. */
1938 : 44917145 : if (REG_P (dest))
1939 : : {
1940 : : /* If register alignment is being enforced for multi-word items in all
1941 : : cases except for parameters, it is possible to have a register copy
1942 : : insn referencing a hard register that is not allowed to contain the
1943 : : mode being copied and which would not be valid as an operand of most
1944 : : insns. Eliminate this problem by not combining with such an insn.
1945 : :
1946 : : Also, on some machines we don't want to extend the life of a hard
1947 : : register. */
1948 : :
1949 : 44393197 : if (REG_P (src)
1950 : 44393197 : && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1951 : 23211 : && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1952 : : /* Don't extend the life of a hard register unless it is
1953 : : user variable (if we have few registers) or it can't
1954 : : fit into the desired register (meaning something special
1955 : : is going on).
1956 : : Also avoid substituting a return register into I3, because
1957 : : reload can't handle a conflict with constraints of other
1958 : : inputs. */
1959 : 2446456 : || (REGNO (src) < FIRST_PSEUDO_REGISTER
1960 : 30995 : && !targetm.hard_regno_mode_ok (REGNO (src),
1961 : 30995 : GET_MODE (src)))))
1962 : 0 : return false;
1963 : : }
1964 : : else
1965 : : return false;
1966 : :
1967 : :
1968 : 44393197 : if (GET_CODE (PATTERN (i3)) == PARALLEL)
1969 : 33747556 : for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1970 : 22910508 : if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1971 : : {
1972 : 10404587 : rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1973 : :
1974 : : /* If the clobber represents an earlyclobber operand, we must not
1975 : : substitute an expression containing the clobbered register.
1976 : : As we do not analyze the constraint strings here, we have to
1977 : : make the conservative assumption. However, if the register is
1978 : : a fixed hard reg, the clobber cannot represent any operand;
1979 : : we leave it up to the machine description to either accept or
1980 : : reject use-and-clobber patterns. */
1981 : 10404587 : if (!REG_P (reg)
1982 : 10041241 : || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1983 : 20399814 : || !fixed_regs[REGNO (reg)])
1984 : 447729 : if (reg_overlap_mentioned_p (reg, src))
1985 : : return false;
1986 : : }
1987 : :
1988 : : /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 : : or not), reject, unless nothing volatile comes between it and I3 */
1990 : :
1991 : 44392550 : if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1992 : : {
1993 : : /* Make sure neither succ nor succ2 contains a volatile reference. */
1994 : 681447 : if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1995 : : return false;
1996 : 681443 : if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1997 : : return false;
1998 : : /* We'll check insns between INSN and I3 below. */
1999 : : }
2000 : :
2001 : : /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 : : to be an explicit register variable, and was chosen for a reason. */
2003 : :
2004 : 44345371 : if (GET_CODE (src) == ASM_OPERANDS
2005 : 44345371 : && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2006 : : return false;
2007 : :
2008 : : /* If INSN contains volatile references (specifically volatile MEMs),
2009 : : we cannot combine across any other volatile references.
2010 : : Even if INSN doesn't contain volatile references, any intervening
2011 : : volatile insn might affect machine state. */
2012 : :
2013 : 44345371 : is_volatile_p = volatile_refs_p (PATTERN (insn))
2014 : 44345371 : ? volatile_refs_p
2015 : : : volatile_insn_p;
2016 : :
2017 : 191733237 : for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2018 : 103256536 : if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2019 : : return false;
2020 : :
2021 : : /* If INSN contains an autoincrement or autodecrement, make sure that
2022 : : register is not used between there and I3, and not already used in
2023 : : I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 : : Also insist that I3 not be a jump if using LRA; if it were one
2025 : : and the incremented register were spilled, we would lose.
2026 : : Reload handles this correctly. */
2027 : :
2028 : 44131330 : if (AUTO_INC_DEC)
2029 : : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2030 : : if (REG_NOTE_KIND (link) == REG_INC
2031 : : && ((JUMP_P (i3) && targetm.lra_p ())
2032 : : || reg_used_between_p (XEXP (link, 0), insn, i3)
2033 : : || (pred != NULL_RTX
2034 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2035 : : || (pred2 != NULL_RTX
2036 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2037 : : || (succ != NULL_RTX
2038 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2039 : : || (succ2 != NULL_RTX
2040 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2041 : : || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2042 : : return false;
2043 : :
2044 : : /* If we get here, we have passed all the tests and the combination is
2045 : : to be allowed. */
2046 : :
2047 : 44131330 : *pdest = dest;
2048 : 44131330 : *psrc = src;
2049 : :
2050 : 44131330 : return true;
2051 : : }
2052 : :
2053 : : /* LOC is the location within I3 that contains its pattern or the component
2054 : : of a PARALLEL of the pattern. We validate that it is valid for combining.
2055 : :
2056 : : One problem is if I3 modifies its output, as opposed to replacing it
2057 : : entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2058 : : doing so would produce an insn that is not equivalent to the original insns.
2059 : :
2060 : : Consider:
2061 : :
2062 : : (set (reg:DI 101) (reg:DI 100))
2063 : : (set (subreg:SI (reg:DI 101) 0) <foo>)
2064 : :
2065 : : This is NOT equivalent to:
2066 : :
2067 : : (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2068 : : (set (reg:DI 101) (reg:DI 100))])
2069 : :
2070 : : Not only does this modify 100 (in which case it might still be valid
2071 : : if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2072 : :
2073 : : We can also run into a problem if I2 sets a register that I1
2074 : : uses and I1 gets directly substituted into I3 (not via I2). In that
2075 : : case, we would be getting the wrong value of I2DEST into I3, so we
2076 : : must reject the combination. This case occurs when I2 and I1 both
2077 : : feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2078 : : If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2079 : : of a SET must prevent combination from occurring. The same situation
2080 : : can occur for I0, in which case I0_NOT_IN_SRC is set.
2081 : :
2082 : : Before doing the above check, we first try to expand a field assignment
2083 : : into a set of logical operations.
2084 : :
2085 : : If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2086 : : we place a register that is both set and used within I3. If more than one
2087 : : such register is detected, we fail.
2088 : :
2089 : : Return true if the combination is valid, false otherwise. */
2090 : :
2091 : : static bool
2092 : 63733654 : combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2093 : : bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2094 : : {
2095 : 63733654 : rtx x = *loc;
2096 : :
2097 : 63733654 : if (GET_CODE (x) == SET)
2098 : : {
2099 : 43088288 : rtx set = x ;
2100 : 43088288 : rtx dest = SET_DEST (set);
2101 : 43088288 : rtx src = SET_SRC (set);
2102 : 43088288 : rtx inner_dest = dest;
2103 : 43088288 : rtx subdest;
2104 : :
2105 : 43088288 : while (GET_CODE (inner_dest) == STRICT_LOW_PART
2106 : 43550290 : || GET_CODE (inner_dest) == SUBREG
2107 : 43550290 : || GET_CODE (inner_dest) == ZERO_EXTRACT)
2108 : 462002 : inner_dest = XEXP (inner_dest, 0);
2109 : :
2110 : : /* Check for the case where I3 modifies its output, as discussed
2111 : : above. We don't want to prevent pseudos from being combined
2112 : : into the address of a MEM, so only prevent the combination if
2113 : : i1 or i2 set the same MEM. */
2114 : 441223 : if ((inner_dest != dest &&
2115 : : (!MEM_P (inner_dest)
2116 : 636 : || rtx_equal_p (i2dest, inner_dest)
2117 : 636 : || (i1dest && rtx_equal_p (i1dest, inner_dest))
2118 : 636 : || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2119 : 440587 : && (reg_overlap_mentioned_p (i2dest, inner_dest)
2120 : 318884 : || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2121 : 317584 : || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2122 : :
2123 : : /* This is the same test done in can_combine_p except we can't test
2124 : : all_adjacent; we don't have to, since this instruction will stay
2125 : : in place, thus we are not considering increasing the lifetime of
2126 : : INNER_DEST.
2127 : :
2128 : : Also, if this insn sets a function argument, combining it with
2129 : : something that might need a spill could clobber a previous
2130 : : function argument; the all_adjacent test in can_combine_p also
2131 : : checks this; here, we do a more specific test for this case. */
2132 : :
2133 : 42965174 : || (REG_P (inner_dest)
2134 : 27527407 : && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2135 : 6788636 : && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2136 : 6788636 : GET_MODE (inner_dest)))
2137 : 42965174 : || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2138 : 86048330 : || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2139 : 150910 : return false;
2140 : :
2141 : : /* If DEST is used in I3, it is being killed in this insn, so
2142 : : record that for later. We have to consider paradoxical
2143 : : subregs here, since they kill the whole register, but we
2144 : : ignore partial subregs, STRICT_LOW_PART, etc.
2145 : : Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2146 : : STACK_POINTER_REGNUM, since these are always considered to be
2147 : : live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2148 : 42937378 : subdest = dest;
2149 : 42937378 : if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2150 : 226420 : subdest = SUBREG_REG (subdest);
2151 : 42937378 : if (pi3dest_killed
2152 : 31768362 : && REG_P (subdest)
2153 : 19908699 : && reg_referenced_p (subdest, PATTERN (i3))
2154 : 1246919 : && REGNO (subdest) != FRAME_POINTER_REGNUM
2155 : 1246919 : && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2156 : 1246919 : || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2157 : 1246919 : && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2158 : 1246919 : || (REGNO (subdest) != ARG_POINTER_REGNUM
2159 : 0 : || ! fixed_regs [REGNO (subdest)]))
2160 : 44184297 : && REGNO (subdest) != STACK_POINTER_REGNUM)
2161 : : {
2162 : 1211138 : if (*pi3dest_killed)
2163 : : return false;
2164 : :
2165 : 1147894 : *pi3dest_killed = subdest;
2166 : : }
2167 : : }
2168 : :
2169 : 20645366 : else if (GET_CODE (x) == PARALLEL)
2170 : : {
2171 : : int i;
2172 : :
2173 : 31601043 : for (i = 0; i < XVECLEN (x, 0); i++)
2174 : 21424120 : if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2175 : : i1_not_in_src, i0_not_in_src, pi3dest_killed))
2176 : : return false;
2177 : : }
2178 : :
2179 : : return true;
2180 : : }
2181 : :
2182 : : /* Return true if X is an arithmetic expression that contains a multiplication
2183 : : and division. We don't count multiplications by powers of two here. */
2184 : :
2185 : : static bool
2186 : 15559643 : contains_muldiv (rtx x)
2187 : : {
2188 : 16184491 : switch (GET_CODE (x))
2189 : : {
2190 : : case MOD: case DIV: case UMOD: case UDIV:
2191 : : return true;
2192 : :
2193 : 466563 : case MULT:
2194 : 466563 : return ! (CONST_INT_P (XEXP (x, 1))
2195 : 147777 : && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2196 : 15574490 : default:
2197 : 15574490 : if (BINARY_P (x))
2198 : 5407904 : return contains_muldiv (XEXP (x, 0))
2199 : 5407904 : || contains_muldiv (XEXP (x, 1));
2200 : :
2201 : 10166586 : if (UNARY_P (x))
2202 : 624848 : return contains_muldiv (XEXP (x, 0));
2203 : :
2204 : : return false;
2205 : : }
2206 : : }
2207 : :
2208 : : /* Determine whether INSN can be used in a combination. Return true if
2209 : : not. This is used in try_combine to detect early some cases where we
2210 : : can't perform combinations. */
2211 : :
2212 : : static bool
2213 : 154777680 : cant_combine_insn_p (rtx_insn *insn)
2214 : : {
2215 : 154777680 : rtx set;
2216 : 154777680 : rtx src, dest;
2217 : :
2218 : : /* If this isn't really an insn, we can't do anything.
2219 : : This can occur when flow deletes an insn that it has merged into an
2220 : : auto-increment address. */
2221 : 154777680 : if (!NONDEBUG_INSN_P (insn))
2222 : : return true;
2223 : :
2224 : : /* Never combine loads and stores involving hard regs that are likely
2225 : : to be spilled. The register allocator can usually handle such
2226 : : reg-reg moves by tying. If we allow the combiner to make
2227 : : substitutions of likely-spilled regs, reload might die.
2228 : : As an exception, we allow combinations involving fixed regs; these are
2229 : : not available to the register allocator so there's no risk involved. */
2230 : :
2231 : 154777286 : set = single_set (insn);
2232 : 154777286 : if (! set)
2233 : : return false;
2234 : 142406144 : src = SET_SRC (set);
2235 : 142406144 : dest = SET_DEST (set);
2236 : 142406144 : if (GET_CODE (src) == SUBREG)
2237 : 982004 : src = SUBREG_REG (src);
2238 : 142406144 : if (GET_CODE (dest) == SUBREG)
2239 : 1610257 : dest = SUBREG_REG (dest);
2240 : 38705334 : if (REG_P (src) && REG_P (dest)
2241 : 174608289 : && ((HARD_REGISTER_P (src)
2242 : 6335988 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2243 : : #ifdef LEAF_REGISTERS
2244 : : && ! LEAF_REGISTERS [REGNO (src)])
2245 : : #else
2246 : : )
2247 : : #endif
2248 : 26130529 : || (HARD_REGISTER_P (dest)
2249 : 18373109 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2250 : 18143465 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2251 : 22608759 : return true;
2252 : :
2253 : : return false;
2254 : : }
2255 : :
2256 : : struct likely_spilled_retval_info
2257 : : {
2258 : : unsigned regno, nregs;
2259 : : unsigned mask;
2260 : : };
2261 : :
2262 : : /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2263 : : hard registers that are known to be written to / clobbered in full. */
2264 : : static void
2265 : 188006 : likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2266 : : {
2267 : 188006 : struct likely_spilled_retval_info *const info =
2268 : : (struct likely_spilled_retval_info *) data;
2269 : 188006 : unsigned regno, nregs;
2270 : 188006 : unsigned new_mask;
2271 : :
2272 : 188006 : if (!REG_P (XEXP (set, 0)))
2273 : : return;
2274 : 188006 : regno = REGNO (x);
2275 : 188006 : if (regno >= info->regno + info->nregs)
2276 : : return;
2277 : 188006 : nregs = REG_NREGS (x);
2278 : 188006 : if (regno + nregs <= info->regno)
2279 : : return;
2280 : 188006 : new_mask = (2U << (nregs - 1)) - 1;
2281 : 188006 : if (regno < info->regno)
2282 : 0 : new_mask >>= info->regno - regno;
2283 : : else
2284 : 188006 : new_mask <<= regno - info->regno;
2285 : 188006 : info->mask &= ~new_mask;
2286 : : }
2287 : :
2288 : : /* Return true iff part of the return value is live during INSN, and
2289 : : it is likely spilled. This can happen when more than one insn is needed
2290 : : to copy the return value, e.g. when we consider to combine into the
2291 : : second copy insn for a complex value. */
2292 : :
2293 : : static bool
2294 : 44639352 : likely_spilled_retval_p (rtx_insn *insn)
2295 : : {
2296 : 44639352 : rtx_insn *use = BB_END (this_basic_block);
2297 : 44639352 : rtx reg;
2298 : 44639352 : rtx_insn *p;
2299 : 44639352 : unsigned regno, nregs;
2300 : : /* We assume here that no machine mode needs more than
2301 : : 32 hard registers when the value overlaps with a register
2302 : : for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2303 : 44639352 : unsigned mask;
2304 : 44639352 : struct likely_spilled_retval_info info;
2305 : :
2306 : 44639352 : if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2307 : : return false;
2308 : 3089580 : reg = XEXP (PATTERN (use), 0);
2309 : 3089580 : if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2310 : 0 : return false;
2311 : 3089580 : regno = REGNO (reg);
2312 : 3089580 : nregs = REG_NREGS (reg);
2313 : 3089580 : if (nregs == 1)
2314 : : return false;
2315 : 185495 : mask = (2U << (nregs - 1)) - 1;
2316 : :
2317 : : /* Disregard parts of the return value that are set later. */
2318 : 185495 : info.regno = regno;
2319 : 185495 : info.nregs = nregs;
2320 : 185495 : info.mask = mask;
2321 : 647845 : for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2322 : 276855 : if (INSN_P (p))
2323 : 276855 : note_stores (p, likely_spilled_retval_1, &info);
2324 : 370988 : mask = info.mask;
2325 : :
2326 : : /* Check if any of the (probably) live return value registers is
2327 : : likely spilled. */
2328 : : nregs --;
2329 : 370988 : do
2330 : : {
2331 : 370988 : if ((mask & 1 << nregs)
2332 : 370988 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2333 : : return true;
2334 : 370976 : } while (nregs--);
2335 : : return false;
2336 : : }
2337 : :
2338 : : /* Adjust INSN after we made a change to its destination.
2339 : :
2340 : : Changing the destination can invalidate notes that say something about
2341 : : the results of the insn and a LOG_LINK pointing to the insn. */
2342 : :
2343 : : static void
2344 : 16722 : adjust_for_new_dest (rtx_insn *insn)
2345 : : {
2346 : : /* For notes, be conservative and simply remove them. */
2347 : 16722 : remove_reg_equal_equiv_notes (insn, true);
2348 : :
2349 : : /* The new insn will have a destination that was previously the destination
2350 : : of an insn just above it. Call distribute_links to make a LOG_LINK from
2351 : : the next use of that destination. */
2352 : :
2353 : 16722 : rtx set = single_set (insn);
2354 : 16722 : gcc_assert (set);
2355 : :
2356 : 16722 : rtx reg = SET_DEST (set);
2357 : :
2358 : 16722 : while (GET_CODE (reg) == ZERO_EXTRACT
2359 : 16722 : || GET_CODE (reg) == STRICT_LOW_PART
2360 : 33444 : || GET_CODE (reg) == SUBREG)
2361 : 0 : reg = XEXP (reg, 0);
2362 : 16722 : gcc_assert (REG_P (reg));
2363 : :
2364 : 16722 : distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2365 : :
2366 : 16722 : df_insn_rescan (insn);
2367 : 16722 : }
2368 : :
2369 : : /* Return TRUE if combine can reuse reg X in mode MODE.
2370 : : ADDED_SETS is trueif the original set is still required. */
2371 : : static bool
2372 : 2446751 : can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2373 : : {
2374 : 2446751 : unsigned int regno;
2375 : :
2376 : 2446751 : if (!REG_P (x))
2377 : : return false;
2378 : :
2379 : : /* Don't change between modes with different underlying register sizes,
2380 : : since this could lead to invalid subregs. */
2381 : 2446751 : if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2382 : 2446751 : REGMODE_NATURAL_SIZE (GET_MODE (x))))
2383 : : return false;
2384 : :
2385 : 2446751 : regno = REGNO (x);
2386 : : /* Allow hard registers if the new mode is legal, and occupies no more
2387 : : registers than the old mode. */
2388 : 2446751 : if (regno < FIRST_PSEUDO_REGISTER)
2389 : 1029309 : return (targetm.hard_regno_mode_ok (regno, mode)
2390 : 1029309 : && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2391 : :
2392 : : /* Or a pseudo that is only used once. */
2393 : 1417442 : return (regno < reg_n_sets_max
2394 : 1417442 : && REG_N_SETS (regno) == 1
2395 : 1355739 : && !added_sets
2396 : 2773181 : && !REG_USERVAR_P (x));
2397 : : }
2398 : :
2399 : :
2400 : : /* Check whether X, the destination of a set, refers to part of
2401 : : the register specified by REG. */
2402 : :
2403 : : static bool
2404 : 16905 : reg_subword_p (rtx x, rtx reg)
2405 : : {
2406 : : /* Check that reg is an integer mode register. */
2407 : 16905 : if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2408 : : return false;
2409 : :
2410 : 16455 : if (GET_CODE (x) == STRICT_LOW_PART
2411 : 15856 : || GET_CODE (x) == ZERO_EXTRACT)
2412 : 620 : x = XEXP (x, 0);
2413 : :
2414 : 16455 : return GET_CODE (x) == SUBREG
2415 : 16278 : && !paradoxical_subreg_p (x)
2416 : 16278 : && SUBREG_REG (x) == reg
2417 : 32733 : && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2418 : : }
2419 : :
2420 : : /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2421 : : by an arbitrary number of CLOBBERs. */
2422 : : static bool
2423 : 96310653 : is_parallel_of_n_reg_sets (rtx pat, int n)
2424 : : {
2425 : 96310653 : if (GET_CODE (pat) != PARALLEL)
2426 : : return false;
2427 : :
2428 : 25238607 : int len = XVECLEN (pat, 0);
2429 : 25238607 : if (len < n)
2430 : : return false;
2431 : :
2432 : : int i;
2433 : 50368381 : for (i = 0; i < n; i++)
2434 : 47746253 : if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2435 : 28147551 : || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2436 : : return false;
2437 : 2953358 : for ( ; i < len; i++)
2438 : 937072 : switch (GET_CODE (XVECEXP (pat, 0, i)))
2439 : : {
2440 : 331230 : case CLOBBER:
2441 : 331230 : if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2442 : : return false;
2443 : 331230 : break;
2444 : : default:
2445 : : return false;
2446 : : }
2447 : : return true;
2448 : : }
2449 : :
2450 : : /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2451 : : CLOBBERs), can be split into individual SETs in that order, without
2452 : : changing semantics. */
2453 : : static bool
2454 : 348707 : can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2455 : : {
2456 : 348707 : if (!insn_nothrow_p (insn))
2457 : : return false;
2458 : :
2459 : 347208 : rtx pat = PATTERN (insn);
2460 : :
2461 : 347208 : int i, j;
2462 : 928504 : for (i = 0; i < n; i++)
2463 : : {
2464 : 637856 : if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2465 : : return false;
2466 : :
2467 : 634912 : rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2468 : :
2469 : 925560 : for (j = i + 1; j < n; j++)
2470 : 344264 : if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2471 : : return false;
2472 : : }
2473 : :
2474 : : return true;
2475 : : }
2476 : :
2477 : : /* Return whether X is just a single_set, with the source
2478 : : a general_operand. */
2479 : : static bool
2480 : 62801152 : is_just_move (rtx_insn *x)
2481 : : {
2482 : 62801152 : rtx set = single_set (x);
2483 : 62801152 : if (!set)
2484 : : return false;
2485 : :
2486 : 62394103 : return general_operand (SET_SRC (set), VOIDmode);
2487 : : }
2488 : :
2489 : : /* Callback function to count autoincs. */
2490 : :
2491 : : static int
2492 : 1004580 : count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2493 : : {
2494 : 1004580 : (*((int *) arg))++;
2495 : :
2496 : 1004580 : return 0;
2497 : : }
2498 : :
2499 : : /* Try to combine the insns I0, I1 and I2 into I3.
2500 : : Here I0, I1 and I2 appear earlier than I3.
2501 : : I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2502 : : I3.
2503 : :
2504 : : If we are combining more than two insns and the resulting insn is not
2505 : : recognized, try splitting it into two insns. If that happens, I2 and I3
2506 : : are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2507 : : Otherwise, I0, I1 and I2 are pseudo-deleted.
2508 : :
2509 : : Return 0 if the combination does not work. Then nothing is changed.
2510 : : If we did the combination, return the insn at which combine should
2511 : : resume scanning.
2512 : :
2513 : : Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2514 : : new direct jump instruction.
2515 : :
2516 : : LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2517 : : been I3 passed to an earlier try_combine within the same basic
2518 : : block. */
2519 : :
2520 : : static rtx_insn *
2521 : 91089599 : try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2522 : : bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2523 : : {
2524 : : /* New patterns for I3 and I2, respectively. */
2525 : 91089599 : rtx newpat, newi2pat = 0;
2526 : 91089599 : rtvec newpat_vec_with_clobbers = 0;
2527 : 91089599 : bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2528 : : /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2529 : : dead. */
2530 : 91089599 : bool added_sets_0, added_sets_1, added_sets_2;
2531 : : /* Total number of SETs to put into I3. */
2532 : 91089599 : int total_sets;
2533 : : /* Nonzero if I2's or I1's body now appears in I3. */
2534 : 91089599 : int i2_is_used = 0, i1_is_used = 0;
2535 : : /* INSN_CODEs for new I3, new I2, and user of condition code. */
2536 : 91089599 : int insn_code_number, i2_code_number = 0, other_code_number = 0;
2537 : : /* Contains I3 if the destination of I3 is used in its source, which means
2538 : : that the old life of I3 is being killed. If that usage is placed into
2539 : : I2 and not in I3, a REG_DEAD note must be made. */
2540 : 91089599 : rtx i3dest_killed = 0;
2541 : : /* SET_DEST and SET_SRC of I2, I1 and I0. */
2542 : 91089599 : rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2543 : : /* Copy of SET_SRC of I1 and I0, if needed. */
2544 : 91089599 : rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2545 : : /* Set if I2DEST was reused as a scratch register. */
2546 : 91089599 : bool i2scratch = false;
2547 : : /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2548 : 91089599 : rtx i0pat = 0, i1pat = 0, i2pat = 0;
2549 : : /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2550 : 91089599 : bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2551 : 91089599 : bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2552 : 91089599 : bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2553 : 91089599 : bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2554 : 91089599 : bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2555 : : /* Notes that must be added to REG_NOTES in I3 and I2. */
2556 : 91089599 : rtx new_i3_notes, new_i2_notes;
2557 : : /* Notes that we substituted I3 into I2 instead of the normal case. */
2558 : 91089599 : bool i3_subst_into_i2 = false;
2559 : : /* Notes that I1, I2 or I3 is a MULT operation. */
2560 : 91089599 : bool have_mult = false;
2561 : 91089599 : bool swap_i2i3 = false;
2562 : 91089599 : bool split_i2i3 = false;
2563 : 91089599 : bool changed_i3_dest = false;
2564 : 91089599 : bool i2_was_move = false, i3_was_move = false;
2565 : 91089599 : int n_auto_inc = 0;
2566 : :
2567 : 91089599 : int maxreg;
2568 : 91089599 : rtx_insn *temp_insn;
2569 : 91089599 : rtx temp_expr;
2570 : 91089599 : struct insn_link *link;
2571 : 91089599 : rtx other_pat = 0;
2572 : 91089599 : rtx new_other_notes;
2573 : 91089599 : int i;
2574 : 91089599 : scalar_int_mode dest_mode, temp_mode;
2575 : 91089599 : bool has_non_call_exception = false;
2576 : :
2577 : : /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2578 : : never be). */
2579 : 91089599 : if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2580 : : return 0;
2581 : :
2582 : : /* Only try four-insn combinations when there's high likelihood of
2583 : : success. Look for simple insns, such as loads of constants or
2584 : : binary operations involving a constant. */
2585 : 21054789 : if (i0)
2586 : : {
2587 : 21054789 : int i;
2588 : 21054789 : int ngood = 0;
2589 : 21054789 : int nshift = 0;
2590 : 21054789 : rtx set0, set3;
2591 : :
2592 : 21054789 : if (!flag_expensive_optimizations)
2593 : : return 0;
2594 : :
2595 : 83251876 : for (i = 0; i < 4; i++)
2596 : : {
2597 : 68014846 : rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2598 : 68014846 : rtx set = single_set (insn);
2599 : 68014846 : rtx src;
2600 : 68014846 : if (!set)
2601 : 2253557 : continue;
2602 : 65761289 : src = SET_SRC (set);
2603 : 65761289 : if (CONSTANT_P (src))
2604 : : {
2605 : 4287939 : ngood += 2;
2606 : 4287939 : break;
2607 : : }
2608 : 61473350 : else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2609 : 7655962 : ngood++;
2610 : 53817388 : else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2611 : 53730098 : || GET_CODE (src) == LSHIFTRT)
2612 : 112591 : nshift++;
2613 : : }
2614 : :
2615 : : /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2616 : : are likely manipulating its value. Ideally we'll be able to combine
2617 : : all four insns into a bitfield insertion of some kind.
2618 : :
2619 : : Note the source in I0 might be inside a sign/zero extension and the
2620 : : memory modes in I0 and I3 might be different. So extract the address
2621 : : from the destination of I3 and search for it in the source of I0.
2622 : :
2623 : : In the event that there's a match but the source/dest do not actually
2624 : : refer to the same memory, the worst that happens is we try some
2625 : : combinations that we wouldn't have otherwise. */
2626 : 19524969 : if ((set0 = single_set (i0))
2627 : : /* Ensure the source of SET0 is a MEM, possibly buried inside
2628 : : an extension. */
2629 : 19402778 : && (GET_CODE (SET_SRC (set0)) == MEM
2630 : 16251071 : || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2631 : 16251071 : || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2632 : 454777 : && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2633 : 3235858 : && (set3 = single_set (i3))
2634 : : /* Ensure the destination of SET3 is a MEM. */
2635 : 2806507 : && GET_CODE (SET_DEST (set3)) == MEM
2636 : : /* Would it be better to extract the base address for the MEM
2637 : : in SET3 and look for that? I don't have cases where it matters
2638 : : but I could envision such cases. */
2639 : 19875206 : && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2640 : 22222 : ngood += 2;
2641 : :
2642 : 19524969 : if (ngood < 2 && nshift < 2)
2643 : : return 0;
2644 : : }
2645 : :
2646 : : /* Exit early if one of the insns involved can't be used for
2647 : : combinations. */
2648 : 75402244 : if (CALL_P (i2)
2649 : 70569927 : || (i1 && CALL_P (i1))
2650 : 67317083 : || (i0 && CALL_P (i0))
2651 : 67248505 : || cant_combine_insn_p (i3)
2652 : 64182749 : || cant_combine_insn_p (i2)
2653 : 49462395 : || (i1 && cant_combine_insn_p (i1))
2654 : 44718463 : || (i0 && cant_combine_insn_p (i0))
2655 : 120041596 : || likely_spilled_retval_p (i3))
2656 : 30762904 : return 0;
2657 : :
2658 : 44639340 : combine_attempts++;
2659 : 44639340 : undobuf.other_insn = 0;
2660 : :
2661 : : /* Reset the hard register usage information. */
2662 : 44639340 : CLEAR_HARD_REG_SET (newpat_used_regs);
2663 : :
2664 : 44639340 : if (dump_file && (dump_flags & TDF_DETAILS))
2665 : : {
2666 : 174 : if (i0)
2667 : 20 : fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2668 : 20 : INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2669 : 154 : else if (i1)
2670 : 26 : fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2671 : 26 : INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2672 : : else
2673 : 128 : fprintf (dump_file, "\nTrying %d -> %d:\n",
2674 : 128 : INSN_UID (i2), INSN_UID (i3));
2675 : :
2676 : 174 : if (i0)
2677 : 20 : dump_insn_slim (dump_file, i0);
2678 : 174 : if (i1)
2679 : 46 : dump_insn_slim (dump_file, i1);
2680 : 174 : dump_insn_slim (dump_file, i2);
2681 : 174 : dump_insn_slim (dump_file, i3);
2682 : : }
2683 : :
2684 : : /* If multiple insns feed into one of I2 or I3, they can be in any
2685 : : order. To simplify the code below, reorder them in sequence. */
2686 : 44639340 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2687 : : std::swap (i0, i2);
2688 : 44639340 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2689 : : std::swap (i0, i1);
2690 : 44639340 : if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2691 : : std::swap (i1, i2);
2692 : :
2693 : 44639340 : added_links_insn = 0;
2694 : 44639340 : added_notes_insn = 0;
2695 : :
2696 : : /* First check for one important special case that the code below will
2697 : : not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2698 : : and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2699 : : we may be able to replace that destination with the destination of I3.
2700 : : This occurs in the common code where we compute both a quotient and
2701 : : remainder into a structure, in which case we want to do the computation
2702 : : directly into the structure to avoid register-register copies.
2703 : :
2704 : : Note that this case handles both multiple sets in I2 and also cases
2705 : : where I2 has a number of CLOBBERs inside the PARALLEL.
2706 : :
2707 : : We make very conservative checks below and only try to handle the
2708 : : most common cases of this. For example, we only handle the case
2709 : : where I2 and I3 are adjacent to avoid making difficult register
2710 : : usage tests. */
2711 : :
2712 : 28208342 : if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2713 : 14643095 : && REG_P (SET_SRC (PATTERN (i3)))
2714 : 5001828 : && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2715 : 4816287 : && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2716 : 4007881 : && GET_CODE (PATTERN (i2)) == PARALLEL
2717 : 1018693 : && ! side_effects_p (SET_DEST (PATTERN (i3)))
2718 : : /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2719 : : below would need to check what is inside (and reg_overlap_mentioned_p
2720 : : doesn't support those codes anyway). Don't allow those destinations;
2721 : : the resulting insn isn't likely to be recognized anyway. */
2722 : 531374 : && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2723 : 531332 : && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2724 : 530468 : && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2725 : 530468 : SET_DEST (PATTERN (i3)))
2726 : 45169726 : && next_active_insn (i2) == i3)
2727 : : {
2728 : 327755 : rtx p2 = PATTERN (i2);
2729 : :
2730 : : /* Make sure that the destination of I3,
2731 : : which we are going to substitute into one output of I2,
2732 : : is not used within another output of I2. We must avoid making this:
2733 : : (parallel [(set (mem (reg 69)) ...)
2734 : : (set (reg 69) ...)])
2735 : : which is not well-defined as to order of actions.
2736 : : (Besides, reload can't handle output reloads for this.)
2737 : :
2738 : : The problem can also happen if the dest of I3 is a memory ref,
2739 : : if another dest in I2 is an indirect memory ref.
2740 : :
2741 : : Neither can this PARALLEL be an asm. We do not allow combining
2742 : : that usually (see can_combine_p), so do not here either. */
2743 : 327755 : bool ok = true;
2744 : 994377 : for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2745 : : {
2746 : 666622 : if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2747 : 327285 : || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2748 : 1331884 : && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2749 : 665262 : SET_DEST (XVECEXP (p2, 0, i))))
2750 : : ok = false;
2751 : 665806 : else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2752 : 338523 : && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2753 : 1908 : ok = false;
2754 : : }
2755 : :
2756 : 327755 : if (ok)
2757 : 388273 : for (i = 0; i < XVECLEN (p2, 0); i++)
2758 : 358133 : if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2759 : 358133 : && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2760 : : {
2761 : 295707 : combine_merges++;
2762 : :
2763 : 295707 : subst_insn = i3;
2764 : 295707 : subst_low_luid = DF_INSN_LUID (i2);
2765 : :
2766 : 295707 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2767 : 295707 : i2src = SET_SRC (XVECEXP (p2, 0, i));
2768 : 295707 : i2dest = SET_DEST (XVECEXP (p2, 0, i));
2769 : 295707 : i2dest_killed = dead_or_set_p (i2, i2dest);
2770 : :
2771 : : /* Replace the dest in I2 with our dest and make the resulting
2772 : : insn the new pattern for I3. Then skip to where we validate
2773 : : the pattern. Everything was set up above. */
2774 : 295707 : SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2775 : 295707 : newpat = p2;
2776 : 295707 : i3_subst_into_i2 = true;
2777 : 295707 : goto validate_replacement;
2778 : : }
2779 : : }
2780 : :
2781 : : /* If I2 is setting a pseudo to a constant and I3 is setting some
2782 : : sub-part of it to another constant, merge them by making a new
2783 : : constant. */
2784 : 44343633 : if (i1 == 0
2785 : 27912635 : && (temp_expr = single_set (i2)) != 0
2786 : 27656754 : && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2787 : 18155035 : && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2788 : 2665793 : && GET_CODE (PATTERN (i3)) == SET
2789 : 1279934 : && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2790 : 44360538 : && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2791 : : {
2792 : 16278 : rtx dest = SET_DEST (PATTERN (i3));
2793 : 16278 : rtx temp_dest = SET_DEST (temp_expr);
2794 : 16278 : int offset = -1;
2795 : 16278 : int width = 0;
2796 : :
2797 : 16278 : if (GET_CODE (dest) == ZERO_EXTRACT)
2798 : : {
2799 : 1 : if (CONST_INT_P (XEXP (dest, 1))
2800 : 1 : && CONST_INT_P (XEXP (dest, 2))
2801 : 2 : && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2802 : : &dest_mode))
2803 : : {
2804 : 1 : width = INTVAL (XEXP (dest, 1));
2805 : 1 : offset = INTVAL (XEXP (dest, 2));
2806 : 1 : dest = XEXP (dest, 0);
2807 : 1 : if (BITS_BIG_ENDIAN)
2808 : : offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2809 : : }
2810 : : }
2811 : : else
2812 : : {
2813 : 16277 : if (GET_CODE (dest) == STRICT_LOW_PART)
2814 : 599 : dest = XEXP (dest, 0);
2815 : 16277 : if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2816 : : {
2817 : 16277 : width = GET_MODE_PRECISION (dest_mode);
2818 : 16277 : offset = 0;
2819 : : }
2820 : : }
2821 : :
2822 : 16278 : if (offset >= 0)
2823 : : {
2824 : : /* If this is the low part, we're done. */
2825 : 16278 : if (subreg_lowpart_p (dest))
2826 : : ;
2827 : : /* Handle the case where inner is twice the size of outer. */
2828 : 4184 : else if (GET_MODE_PRECISION (temp_mode)
2829 : 4184 : == 2 * GET_MODE_PRECISION (dest_mode))
2830 : 4172 : offset += GET_MODE_PRECISION (dest_mode);
2831 : : /* Otherwise give up for now. */
2832 : : else
2833 : : offset = -1;
2834 : : }
2835 : :
2836 : 16266 : if (offset >= 0)
2837 : : {
2838 : 16266 : rtx inner = SET_SRC (PATTERN (i3));
2839 : 16266 : rtx outer = SET_SRC (temp_expr);
2840 : :
2841 : 32532 : wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2842 : 16266 : rtx_mode_t (inner, dest_mode),
2843 : 32532 : offset, width);
2844 : :
2845 : 16266 : combine_merges++;
2846 : 16266 : subst_insn = i3;
2847 : 16266 : subst_low_luid = DF_INSN_LUID (i2);
2848 : 16266 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2849 : 16266 : i2dest = temp_dest;
2850 : 16266 : i2dest_killed = dead_or_set_p (i2, i2dest);
2851 : :
2852 : : /* Replace the source in I2 with the new constant and make the
2853 : : resulting insn the new pattern for I3. Then skip to where we
2854 : : validate the pattern. Everything was set up above. */
2855 : 16266 : SUBST (SET_SRC (temp_expr),
2856 : : immed_wide_int_const (o, temp_mode));
2857 : :
2858 : 16266 : newpat = PATTERN (i2);
2859 : :
2860 : : /* The dest of I3 has been replaced with the dest of I2. */
2861 : 16266 : changed_i3_dest = true;
2862 : 16266 : goto validate_replacement;
2863 : 16266 : }
2864 : : }
2865 : :
2866 : : /* If we have no I1 and I2 looks like:
2867 : : (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2868 : : (set Y OP)])
2869 : : make up a dummy I1 that is
2870 : : (set Y OP)
2871 : : and change I2 to be
2872 : : (set (reg:CC X) (compare:CC Y (const_int 0)))
2873 : :
2874 : : (We can ignore any trailing CLOBBERs.)
2875 : :
2876 : : This undoes a previous combination and allows us to match a branch-and-
2877 : : decrement insn. */
2878 : :
2879 : 44327367 : if (i1 == 0
2880 : 27896369 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2881 : 206398 : && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2882 : : == MODE_CC)
2883 : 132341 : && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2884 : 106720 : && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2885 : 68475 : && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2886 : 68475 : SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2887 : 61558 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2888 : 44388925 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2889 : : {
2890 : : /* We make I1 with the same INSN_UID as I2. This gives it
2891 : : the same DF_INSN_LUID for value tracking. Our fake I1 will
2892 : : never appear in the insn stream so giving it the same INSN_UID
2893 : : as I2 will not cause a problem. */
2894 : :
2895 : 123116 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2896 : 61558 : XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2897 : : -1, NULL_RTX);
2898 : 61558 : INSN_UID (i1) = INSN_UID (i2);
2899 : :
2900 : 61558 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2901 : 61558 : SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2902 : : SET_DEST (PATTERN (i1)));
2903 : 61558 : unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2904 : 61558 : SUBST_LINK (LOG_LINKS (i2),
2905 : : alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2906 : : }
2907 : :
2908 : : /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2909 : : make those two SETs separate I1 and I2 insns, and make an I0 that is
2910 : : the original I1. */
2911 : 44327367 : if (i0 == 0
2912 : 42314097 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2913 : 348707 : && can_split_parallel_of_n_reg_sets (i2, 2)
2914 : 290648 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2915 : 254212 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2916 : 237506 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2917 : 44564869 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2918 : : {
2919 : : /* If there is no I1, there is no I0 either. */
2920 : 237502 : i0 = i1;
2921 : :
2922 : : /* We make I1 with the same INSN_UID as I2. This gives it
2923 : : the same DF_INSN_LUID for value tracking. Our fake I1 will
2924 : : never appear in the insn stream so giving it the same INSN_UID
2925 : : as I2 will not cause a problem. */
2926 : :
2927 : 475004 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2928 : 237502 : XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2929 : : -1, NULL_RTX);
2930 : 237502 : INSN_UID (i1) = INSN_UID (i2);
2931 : :
2932 : 237502 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2933 : : }
2934 : :
2935 : : /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2936 : 44327367 : if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2937 : : {
2938 : 11473105 : if (dump_file && (dump_flags & TDF_DETAILS))
2939 : 8 : fprintf (dump_file, "Can't combine i2 into i3\n");
2940 : 11473105 : undo_all ();
2941 : 11473105 : return 0;
2942 : : }
2943 : 32854262 : if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2944 : : {
2945 : 1298005 : if (dump_file && (dump_flags & TDF_DETAILS))
2946 : 0 : fprintf (dump_file, "Can't combine i1 into i3\n");
2947 : 1298005 : undo_all ();
2948 : 1298005 : return 0;
2949 : : }
2950 : 31556257 : if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2951 : : {
2952 : 155451 : if (dump_file && (dump_flags & TDF_DETAILS))
2953 : 0 : fprintf (dump_file, "Can't combine i0 into i3\n");
2954 : 155451 : undo_all ();
2955 : 155451 : return 0;
2956 : : }
2957 : :
2958 : : /* With non-call exceptions we can end up trying to combine multiple
2959 : : insns with possible EH side effects. Make sure we can combine
2960 : : that to a single insn which means there must be at most one insn
2961 : : in the combination with an EH side effect. */
2962 : 31400806 : if (cfun->can_throw_non_call_exceptions)
2963 : : {
2964 : 6126400 : if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2965 : 6101610 : || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2966 : 6101417 : || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2967 : 12227767 : || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2968 : : {
2969 : 25033 : has_non_call_exception = true;
2970 : 25033 : if (insn_could_throw_p (i3)
2971 : 25033 : + insn_could_throw_p (i2)
2972 : 25033 : + (i1 ? insn_could_throw_p (i1) : 0)
2973 : 25033 : + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2974 : : {
2975 : 230 : if (dump_file && (dump_flags & TDF_DETAILS))
2976 : 0 : fprintf (dump_file, "Can't combine multiple insns with EH "
2977 : : "side-effects\n");
2978 : 230 : undo_all ();
2979 : 230 : return 0;
2980 : : }
2981 : : }
2982 : : }
2983 : :
2984 : : /* Record whether i2 and i3 are trivial moves. */
2985 : 31400576 : i2_was_move = is_just_move (i2);
2986 : 31400576 : i3_was_move = is_just_move (i3);
2987 : :
2988 : : /* Record whether I2DEST is used in I2SRC and similarly for the other
2989 : : cases. Knowing this will help in register status updating below. */
2990 : 31400576 : i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2991 : 31400576 : i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2992 : 9696600 : i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2993 : 31400576 : i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2994 : 1424950 : i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2995 : 1424950 : i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2996 : 31400576 : i2dest_killed = dead_or_set_p (i2, i2dest);
2997 : 31400576 : i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2998 : 31400576 : i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2999 : :
3000 : : /* For the earlier insns, determine which of the subsequent ones they
3001 : : feed. */
3002 : 31400576 : i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3003 : 31400576 : i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3004 : 2505320 : i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3005 : 1080370 : : (!reg_overlap_mentioned_p (i1dest, i0dest)
3006 : 1058699 : && reg_overlap_mentioned_p (i0dest, i2src))));
3007 : :
3008 : : /* Ensure that I3's pattern can be the destination of combines. */
3009 : 31400576 : if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3010 : 31400576 : i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3011 : 1424950 : i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3012 : 1396381 : || (i1dest_in_i0src && !i0_feeds_i1_n)),
3013 : : &i3dest_killed))
3014 : : {
3015 : 214119 : undo_all ();
3016 : 214119 : return 0;
3017 : : }
3018 : :
3019 : : /* See if any of the insns is a MULT operation. Unless one is, we will
3020 : : reject a combination that is, since it must be slower. Be conservative
3021 : : here. */
3022 : 31186457 : if (GET_CODE (i2src) == MULT
3023 : 30416041 : || (i1 != 0 && GET_CODE (i1src) == MULT)
3024 : 30089161 : || (i0 != 0 && GET_CODE (i0src) == MULT)
3025 : 61230843 : || (GET_CODE (PATTERN (i3)) == SET
3026 : 23704379 : && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3027 : : have_mult = true;
3028 : :
3029 : : /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3030 : : We used to do this EXCEPT in one case: I3 has a post-inc in an
3031 : : output operand. However, that exception can give rise to insns like
3032 : : mov r3,(r3)+
3033 : : which is a famous insn on the PDP-11 where the value of r3 used as the
3034 : : source was model-dependent. Avoid this sort of thing. */
3035 : :
3036 : : #if 0
3037 : : if (!(GET_CODE (PATTERN (i3)) == SET
3038 : : && REG_P (SET_SRC (PATTERN (i3)))
3039 : : && MEM_P (SET_DEST (PATTERN (i3)))
3040 : : && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3041 : : || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3042 : : /* It's not the exception. */
3043 : : #endif
3044 : 31186457 : if (AUTO_INC_DEC)
3045 : : {
3046 : : rtx link;
3047 : : for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3048 : : if (REG_NOTE_KIND (link) == REG_INC
3049 : : && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3050 : : || (i1 != 0
3051 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3052 : : {
3053 : : undo_all ();
3054 : : return 0;
3055 : : }
3056 : : }
3057 : :
3058 : : /* See if the SETs in I1 or I2 need to be kept around in the merged
3059 : : instruction: whenever the value set there is still needed past I3.
3060 : : For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3061 : :
3062 : : For the SET in I1, we have two cases: if I1 and I2 independently feed
3063 : : into I3, the set in I1 needs to be kept around unless I1DEST dies
3064 : : or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3065 : : in I1 needs to be kept around unless I1DEST dies or is set in either
3066 : : I2 or I3. The same considerations apply to I0. */
3067 : :
3068 : 31186457 : added_sets_2 = !dead_or_set_p (i3, i2dest);
3069 : :
3070 : 31186457 : if (i1)
3071 : 9623281 : added_sets_1 = !(dead_or_set_p (i3, i1dest)
3072 : 7410835 : || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3073 : : else
3074 : : added_sets_1 = false;
3075 : :
3076 : 31186457 : if (i0)
3077 : 2025361 : added_sets_0 = !(dead_or_set_p (i3, i0dest)
3078 : 1255163 : || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3079 : 235227 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3080 : 578718 : && dead_or_set_p (i2, i0dest)));
3081 : : else
3082 : : added_sets_0 = false;
3083 : :
3084 : : /* We are about to copy insns for the case where they need to be kept
3085 : : around. Check that they can be copied in the merged instruction. */
3086 : :
3087 : 31186457 : if (targetm.cannot_copy_insn_p
3088 : 31186457 : && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3089 : 0 : || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3090 : 0 : || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3091 : : {
3092 : 0 : undo_all ();
3093 : 0 : return 0;
3094 : : }
3095 : :
3096 : : /* We cannot safely duplicate volatile references in any case. */
3097 : :
3098 : 6862423 : if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3099 : 31161669 : || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3100 : 62325382 : || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3101 : : {
3102 : 49681 : undo_all ();
3103 : 49681 : return 0;
3104 : : }
3105 : :
3106 : : /* Count how many auto_inc expressions there were in the original insns;
3107 : : we need to have the same number in the resulting patterns. */
3108 : :
3109 : 31136776 : if (i0)
3110 : 1393369 : for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3111 : 31136776 : if (i1)
3112 : 9598050 : for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3113 : 31136776 : for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3114 : 31136776 : for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3115 : :
3116 : : /* If the set in I2 needs to be kept around, we must make a copy of
3117 : : PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118 : : PATTERN (I2), we are only substituting for the original I1DEST, not into
3119 : : an already-substituted copy. This also prevents making self-referential
3120 : : rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121 : : I2DEST. */
3122 : :
3123 : 31136776 : if (added_sets_2)
3124 : : {
3125 : 6834826 : if (GET_CODE (PATTERN (i2)) == PARALLEL)
3126 : 2227209 : i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3127 : : else
3128 : 4607617 : i2pat = copy_rtx (PATTERN (i2));
3129 : : }
3130 : :
3131 : 31136776 : if (added_sets_1)
3132 : : {
3133 : 3635426 : if (GET_CODE (PATTERN (i1)) == PARALLEL)
3134 : 1281069 : i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3135 : : else
3136 : 2354357 : i1pat = copy_rtx (PATTERN (i1));
3137 : : }
3138 : :
3139 : 31136776 : if (added_sets_0)
3140 : : {
3141 : 323910 : if (GET_CODE (PATTERN (i0)) == PARALLEL)
3142 : 150520 : i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3143 : : else
3144 : 173390 : i0pat = copy_rtx (PATTERN (i0));
3145 : : }
3146 : :
3147 : 31136776 : combine_merges++;
3148 : :
3149 : : /* Substitute in the latest insn for the regs set by the earlier ones. */
3150 : :
3151 : 31136776 : maxreg = max_reg_num ();
3152 : :
3153 : 31136776 : subst_insn = i3;
3154 : :
3155 : : /* Many machines have insns that can both perform an
3156 : : arithmetic operation and set the condition code. These operations will
3157 : : be represented as a PARALLEL with the first element of the vector
3158 : : being a COMPARE of an arithmetic operation with the constant zero.
3159 : : The second element of the vector will set some pseudo to the result
3160 : : of the same arithmetic operation. If we simplify the COMPARE, we won't
3161 : : match such a pattern and so will generate an extra insn. Here we test
3162 : : for this case, where both the comparison and the operation result are
3163 : : needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164 : : I2SRC. Later we will make the PARALLEL that contains I2. */
3165 : :
3166 : 21538726 : if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3167 : 4025448 : && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3168 : 1775065 : && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3169 : 32033557 : && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3170 : : {
3171 : 819528 : rtx newpat_dest;
3172 : 819528 : rtx *cc_use_loc = NULL;
3173 : 819528 : rtx_insn *cc_use_insn = NULL;
3174 : 819528 : rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3175 : 819528 : machine_mode compare_mode, orig_compare_mode;
3176 : 819528 : enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3177 : 819528 : scalar_int_mode mode;
3178 : :
3179 : 819528 : newpat = PATTERN (i3);
3180 : 819528 : newpat_dest = SET_DEST (newpat);
3181 : 819528 : compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3182 : :
3183 : 819528 : if (undobuf.other_insn == 0
3184 : 819528 : && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3185 : : &cc_use_insn)))
3186 : : {
3187 : 813165 : compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3188 : 813165 : if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3189 : 813165 : compare_code = simplify_compare_const (compare_code, mode,
3190 : : &op0, &op1);
3191 : 813165 : target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3192 : : }
3193 : :
3194 : : /* Do the rest only if op1 is const0_rtx, which may be the
3195 : : result of simplification. */
3196 : 819528 : if (op1 == const0_rtx)
3197 : : {
3198 : : /* If a single use of the CC is found, prepare to modify it
3199 : : when SELECT_CC_MODE returns a new CC-class mode, or when
3200 : : the above simplify_compare_const() returned a new comparison
3201 : : operator. undobuf.other_insn is assigned the CC use insn
3202 : : when modifying it. */
3203 : 466308 : if (cc_use_loc)
3204 : : {
3205 : : #ifdef SELECT_CC_MODE
3206 : 463631 : machine_mode new_mode
3207 : 463631 : = SELECT_CC_MODE (compare_code, op0, op1);
3208 : 463631 : if (new_mode != orig_compare_mode
3209 : 463631 : && can_change_dest_mode (SET_DEST (newpat),
3210 : : added_sets_2, new_mode))
3211 : : {
3212 : 315 : unsigned int regno = REGNO (newpat_dest);
3213 : 315 : compare_mode = new_mode;
3214 : 315 : if (regno < FIRST_PSEUDO_REGISTER)
3215 : 315 : newpat_dest = gen_rtx_REG (compare_mode, regno);
3216 : : else
3217 : : {
3218 : 0 : subst_mode (regno, compare_mode);
3219 : 0 : newpat_dest = regno_reg_rtx[regno];
3220 : : }
3221 : : }
3222 : : #endif
3223 : : /* Cases for modifying the CC-using comparison. */
3224 : 463631 : if (compare_code != orig_compare_code
3225 : 329 : && COMPARISON_P (*cc_use_loc))
3226 : : {
3227 : : /* Replace cc_use_loc with entire new RTX. */
3228 : 329 : SUBST (*cc_use_loc,
3229 : : gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3230 : : newpat_dest, const0_rtx));
3231 : 329 : undobuf.other_insn = cc_use_insn;
3232 : : }
3233 : 463302 : else if (compare_mode != orig_compare_mode)
3234 : : {
3235 : 1 : subrtx_ptr_iterator::array_type array;
3236 : :
3237 : : /* Just replace the CC reg with a new mode. */
3238 : 4 : FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3239 : : {
3240 : 3 : rtx *loc = *iter;
3241 : 3 : if (REG_P (*loc)
3242 : 3 : && REGNO (*loc) == REGNO (newpat_dest))
3243 : : {
3244 : 1 : SUBST (*loc, newpat_dest);
3245 : 1 : iter.skip_subrtxes ();
3246 : : }
3247 : : }
3248 : 1 : undobuf.other_insn = cc_use_insn;
3249 : 1 : }
3250 : : }
3251 : :
3252 : : /* Now we modify the current newpat:
3253 : : First, SET_DEST(newpat) is updated if the CC mode has been
3254 : : altered. For targets without SELECT_CC_MODE, this should be
3255 : : optimized away. */
3256 : 466308 : if (compare_mode != orig_compare_mode)
3257 : 315 : SUBST (SET_DEST (newpat), newpat_dest);
3258 : : /* This is always done to propagate i2src into newpat. */
3259 : 466308 : SUBST (SET_SRC (newpat),
3260 : : gen_rtx_COMPARE (compare_mode, op0, op1));
3261 : : /* Create new version of i2pat if needed; the below PARALLEL
3262 : : creation needs this to work correctly. */
3263 : 466308 : if (! rtx_equal_p (i2src, op0))
3264 : 29 : i2pat = gen_rtx_SET (i2dest, op0);
3265 : 466308 : i2_is_used = 1;
3266 : : }
3267 : : }
3268 : :
3269 : 819528 : if (i2_is_used == 0)
3270 : : {
3271 : : /* It is possible that the source of I2 or I1 may be performing
3272 : : an unneeded operation, such as a ZERO_EXTEND of something
3273 : : that is known to have the high part zero. Handle that case
3274 : : by letting subst look at the inner insns.
3275 : :
3276 : : Another way to do this would be to have a function that tries
3277 : : to simplify a single insn instead of merging two or more
3278 : : insns. We don't do this because of the potential of infinite
3279 : : loops and because of the potential extra memory required.
3280 : : However, doing it the way we are is a bit of a kludge and
3281 : : doesn't catch all cases.
3282 : :
3283 : : But only do this if -fexpensive-optimizations since it slows
3284 : : things down and doesn't usually win.
3285 : :
3286 : : This is not done in the COMPARE case above because the
3287 : : unmodified I2PAT is used in the PARALLEL and so a pattern
3288 : : with a modified I2SRC would not match. */
3289 : :
3290 : 30670468 : if (flag_expensive_optimizations)
3291 : : {
3292 : : /* Pass pc_rtx so no substitutions are done, just
3293 : : simplifications. */
3294 : 28649086 : if (i1)
3295 : : {
3296 : 9013908 : subst_low_luid = DF_INSN_LUID (i1);
3297 : 9013908 : i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3298 : : }
3299 : :
3300 : 28649086 : subst_low_luid = DF_INSN_LUID (i2);
3301 : 28649086 : i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3302 : : }
3303 : :
3304 : 30670468 : n_occurrences = 0; /* `subst' counts here */
3305 : 30670468 : subst_low_luid = DF_INSN_LUID (i2);
3306 : :
3307 : : /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3308 : : copy of I2SRC each time we substitute it, in order to avoid creating
3309 : : self-referential RTL when we will be substituting I1SRC for I1DEST
3310 : : later. Likewise if I0 feeds into I2, either directly or indirectly
3311 : : through I1, and I0DEST is in I0SRC. */
3312 : 30670468 : newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3313 : 30670468 : (i1_feeds_i2_n && i1dest_in_i1src)
3314 : 30670468 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3315 : : && i0dest_in_i0src));
3316 : 30670468 : substed_i2 = true;
3317 : :
3318 : : /* Record whether I2's body now appears within I3's body. */
3319 : 30670468 : i2_is_used = n_occurrences;
3320 : : }
3321 : :
3322 : : /* If we already got a failure, don't try to do more. Otherwise, try to
3323 : : substitute I1 if we have it. */
3324 : :
3325 : 31136776 : if (i1 && GET_CODE (newpat) != CLOBBER)
3326 : : {
3327 : : /* Before we can do this substitution, we must redo the test done
3328 : : above (see detailed comments there) that ensures I1DEST isn't
3329 : : mentioned in any SETs in NEWPAT that are field assignments. */
3330 : 9530301 : if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3331 : : false, false, 0))
3332 : : {
3333 : 33 : undo_all ();
3334 : 33 : return 0;
3335 : : }
3336 : :
3337 : 9530268 : n_occurrences = 0;
3338 : 9530268 : subst_low_luid = DF_INSN_LUID (i1);
3339 : :
3340 : : /* If the following substitution will modify I1SRC, make a copy of it
3341 : : for the case where it is substituted for I1DEST in I2PAT later. */
3342 : 9530268 : if (added_sets_2 && i1_feeds_i2_n)
3343 : 1365787 : i1src_copy = copy_rtx (i1src);
3344 : :
3345 : : /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3346 : : copy of I1SRC each time we substitute it, in order to avoid creating
3347 : : self-referential RTL when we will be substituting I0SRC for I0DEST
3348 : : later. */
3349 : 19060536 : newpat = subst (newpat, i1dest, i1src, false, false,
3350 : 9530268 : i0_feeds_i1_n && i0dest_in_i0src);
3351 : 9530268 : substed_i1 = true;
3352 : :
3353 : : /* Record whether I1's body now appears within I3's body. */
3354 : 9530268 : i1_is_used = n_occurrences;
3355 : : }
3356 : :
3357 : : /* Likewise for I0 if we have it. */
3358 : :
3359 : 31136743 : if (i0 && GET_CODE (newpat) != CLOBBER)
3360 : : {
3361 : 1378657 : if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3362 : : false, false, 0))
3363 : : {
3364 : 2 : undo_all ();
3365 : 2 : return 0;
3366 : : }
3367 : :
3368 : : /* If the following substitution will modify I0SRC, make a copy of it
3369 : : for the case where it is substituted for I0DEST in I1PAT later. */
3370 : 1378655 : if (added_sets_1 && i0_feeds_i1_n)
3371 : 211354 : i0src_copy = copy_rtx (i0src);
3372 : : /* And a copy for I0DEST in I2PAT substitution. */
3373 : 1378655 : if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3374 : 178128 : || (i0_feeds_i2_n)))
3375 : 285437 : i0src_copy2 = copy_rtx (i0src);
3376 : :
3377 : 1378655 : n_occurrences = 0;
3378 : 1378655 : subst_low_luid = DF_INSN_LUID (i0);
3379 : 1378655 : newpat = subst (newpat, i0dest, i0src, false, false, false);
3380 : 1378655 : substed_i0 = true;
3381 : : }
3382 : :
3383 : 31136741 : if (n_auto_inc)
3384 : : {
3385 : 502853 : int new_n_auto_inc = 0;
3386 : 502853 : for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3387 : :
3388 : 502853 : if (n_auto_inc != new_n_auto_inc)
3389 : : {
3390 : 1130 : if (dump_file && (dump_flags & TDF_DETAILS))
3391 : 0 : fprintf (dump_file, "Number of auto_inc expressions changed\n");
3392 : 1130 : undo_all ();
3393 : 1130 : return 0;
3394 : : }
3395 : : }
3396 : :
3397 : : /* Fail if an autoincrement side-effect has been duplicated. Be careful
3398 : : to count all the ways that I2SRC and I1SRC can be used. */
3399 : 31135611 : if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3400 : : && i2_is_used + added_sets_2 > 1)
3401 : : || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3402 : : && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3403 : : || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3404 : : && (n_occurrences + added_sets_0
3405 : : + (added_sets_1 && i0_feeds_i1_n)
3406 : : + (added_sets_2 && i0_feeds_i2_n) > 1))
3407 : : /* Fail if we tried to make a new register. */
3408 : 31135611 : || max_reg_num () != maxreg
3409 : : /* Fail if we couldn't do something and have a CLOBBER. */
3410 : 31135611 : || GET_CODE (newpat) == CLOBBER
3411 : : /* Fail if this new pattern is a MULT and we didn't have one before
3412 : : at the outer level. */
3413 : 61908059 : || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3414 : 253563 : && ! have_mult))
3415 : : {
3416 : 379988 : undo_all ();
3417 : 379988 : return 0;
3418 : : }
3419 : :
3420 : : /* If the actions of the earlier insns must be kept
3421 : : in addition to substituting them into the latest one,
3422 : : we must make a new PARALLEL for the latest insn
3423 : : to hold additional the SETs. */
3424 : :
3425 : 30755623 : if (added_sets_0 || added_sets_1 || added_sets_2)
3426 : : {
3427 : 9929817 : int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3428 : 9929817 : combine_extras++;
3429 : :
3430 : 9929817 : if (GET_CODE (newpat) == PARALLEL)
3431 : : {
3432 : 1983422 : rtvec old = XVEC (newpat, 0);
3433 : 1983422 : total_sets = XVECLEN (newpat, 0) + extra_sets;
3434 : 1983422 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3435 : 1983422 : memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3436 : 1983422 : sizeof (old->elem[0]) * old->num_elem);
3437 : : }
3438 : : else
3439 : : {
3440 : 7946395 : rtx old = newpat;
3441 : 7946395 : total_sets = 1 + extra_sets;
3442 : 7946395 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3443 : 7946395 : XVECEXP (newpat, 0, 0) = old;
3444 : : }
3445 : :
3446 : 9929817 : if (added_sets_0)
3447 : 313579 : XVECEXP (newpat, 0, --total_sets) = i0pat;
3448 : :
3449 : 9929817 : if (added_sets_1)
3450 : : {
3451 : 3589244 : rtx t = i1pat;
3452 : 3589244 : if (i0_feeds_i1_n)
3453 : 210994 : t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3454 : : false, false, false);
3455 : :
3456 : 3589244 : XVECEXP (newpat, 0, --total_sets) = t;
3457 : : }
3458 : 9929817 : if (added_sets_2)
3459 : : {
3460 : 6770564 : rtx t = i2pat;
3461 : 6770564 : if (i1_feeds_i2_n)
3462 : 1338320 : t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3463 : 1338320 : i0_feeds_i1_n && i0dest_in_i0src);
3464 : 6770564 : if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3465 : 284227 : t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3466 : : false, false, false);
3467 : :
3468 : 6770564 : XVECEXP (newpat, 0, --total_sets) = t;
3469 : : }
3470 : : }
3471 : :
3472 : 23985059 : validate_replacement:
3473 : :
3474 : : /* Note which hard regs this insn has as inputs. */
3475 : 31067596 : mark_used_regs_combine (newpat);
3476 : :
3477 : : /* If recog_for_combine fails, it strips existing clobbers. If we'll
3478 : : consider splitting this pattern, we might need these clobbers. */
3479 : 31067596 : if (i1 && GET_CODE (newpat) == PARALLEL
3480 : 6593263 : && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3481 : : {
3482 : 1549495 : int len = XVECLEN (newpat, 0);
3483 : :
3484 : 1549495 : newpat_vec_with_clobbers = rtvec_alloc (len);
3485 : 6246596 : for (i = 0; i < len; i++)
3486 : 3147606 : RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3487 : : }
3488 : :
3489 : : /* We have recognized nothing yet. */
3490 : 31067596 : insn_code_number = -1;
3491 : :
3492 : : /* See if this is a PARALLEL of two SETs where one SET's destination is
3493 : : a register that is unused and this isn't marked as an instruction that
3494 : : might trap in an EH region. In that case, we just need the other SET.
3495 : : We prefer this over the PARALLEL.
3496 : :
3497 : : This can occur when simplifying a divmod insn. We *must* test for this
3498 : : case here because the code below that splits two independent SETs doesn't
3499 : : handle this case correctly when it updates the register status.
3500 : :
3501 : : It's pointless doing this if we originally had two sets, one from
3502 : : i3, and one from i2. Combining then splitting the parallel results
3503 : : in the original i2 again plus an invalid insn (which we delete).
3504 : : The net effect is only to move instructions around, which makes
3505 : : debug info less accurate.
3506 : :
3507 : : If the remaining SET came from I2 its destination should not be used
3508 : : between I2 and I3. See PR82024. */
3509 : :
3510 : 6770564 : if (!(added_sets_2 && i1 == 0)
3511 : 26100187 : && is_parallel_of_n_reg_sets (newpat, 2)
3512 : 32528777 : && asm_noperands (newpat) < 0)
3513 : : {
3514 : 1460374 : rtx set0 = XVECEXP (newpat, 0, 0);
3515 : 1460374 : rtx set1 = XVECEXP (newpat, 0, 1);
3516 : 1460374 : rtx oldpat = newpat;
3517 : :
3518 : 1460374 : if (((REG_P (SET_DEST (set1))
3519 : 1460374 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3520 : 1420473 : || (GET_CODE (SET_DEST (set1)) == SUBREG
3521 : 0 : && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3522 : 39901 : && insn_nothrow_p (i3)
3523 : 1499044 : && !side_effects_p (SET_SRC (set1)))
3524 : : {
3525 : 38478 : newpat = set0;
3526 : 38478 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3527 : : }
3528 : :
3529 : 1421896 : else if (((REG_P (SET_DEST (set0))
3530 : 1421896 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3531 : 1400145 : || (GET_CODE (SET_DEST (set0)) == SUBREG
3532 : 0 : && find_reg_note (i3, REG_UNUSED,
3533 : 0 : SUBREG_REG (SET_DEST (set0)))))
3534 : 21751 : && insn_nothrow_p (i3)
3535 : 1442851 : && !side_effects_p (SET_SRC (set0)))
3536 : : {
3537 : 20914 : rtx dest = SET_DEST (set1);
3538 : 20914 : if (GET_CODE (dest) == SUBREG)
3539 : 0 : dest = SUBREG_REG (dest);
3540 : 20914 : if (!reg_used_between_p (dest, i2, i3))
3541 : : {
3542 : 20913 : newpat = set1;
3543 : 20913 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3544 : :
3545 : 20913 : if (insn_code_number >= 0)
3546 : : changed_i3_dest = true;
3547 : : }
3548 : : }
3549 : :
3550 : 38478 : if (insn_code_number < 0)
3551 : 1455117 : newpat = oldpat;
3552 : : }
3553 : :
3554 : : /* Is the result of combination a valid instruction? */
3555 : 1455117 : if (insn_code_number < 0)
3556 : 31062339 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3557 : :
3558 : : /* If we were combining three insns and the result is a simple SET
3559 : : with no ASM_OPERANDS that wasn't recognized, try to split it into two
3560 : : insns. There are two ways to do this. It can be split using a
3561 : : machine-specific method (like when you have an addition of a large
3562 : : constant) or by combine in the function find_split_point. */
3563 : :
3564 : 9377838 : if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3565 : 35330856 : && asm_noperands (newpat) < 0)
3566 : : {
3567 : 4262792 : rtx parallel, *split;
3568 : 4262792 : rtx_insn *m_split_insn;
3569 : :
3570 : : /* See if the MD file can split NEWPAT. If it can't, see if letting it
3571 : : use I2DEST as a scratch register will help. In the latter case,
3572 : : convert I2DEST to the mode of the source of NEWPAT if we can. */
3573 : :
3574 : 4262792 : m_split_insn = combine_split_insns (newpat, i3);
3575 : :
3576 : : /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3577 : : inputs of NEWPAT. */
3578 : :
3579 : : /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3580 : : possible to try that as a scratch reg. This would require adding
3581 : : more code to make it work though. */
3582 : :
3583 : 4262792 : if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3584 : : {
3585 : 4130262 : machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3586 : :
3587 : : /* ??? Reusing i2dest without resetting the reg_stat entry for it
3588 : : (temporarily, until we are committed to this instruction
3589 : : combination) does not work: for example, any call to nonzero_bits
3590 : : on the register (from a splitter in the MD file, for example)
3591 : : will get the old information, which is invalid.
3592 : :
3593 : : Since nowadays we can create registers during combine just fine,
3594 : : we should just create a new one here, not reuse i2dest. */
3595 : :
3596 : : /* First try to split using the original register as a
3597 : : scratch register. */
3598 : 4130262 : parallel = gen_rtx_PARALLEL (VOIDmode,
3599 : : gen_rtvec (2, newpat,
3600 : : gen_rtx_CLOBBER (VOIDmode,
3601 : : i2dest)));
3602 : 4130262 : m_split_insn = combine_split_insns (parallel, i3);
3603 : :
3604 : : /* If that didn't work, try changing the mode of I2DEST if
3605 : : we can. */
3606 : 4130262 : if (m_split_insn == 0
3607 : 4130262 : && new_mode != GET_MODE (i2dest)
3608 : 1537590 : && new_mode != VOIDmode
3609 : 5192015 : && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3610 : : {
3611 : 796411 : machine_mode old_mode = GET_MODE (i2dest);
3612 : 796411 : rtx ni2dest;
3613 : :
3614 : 796411 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3615 : 9081 : ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3616 : : else
3617 : : {
3618 : 787330 : subst_mode (REGNO (i2dest), new_mode);
3619 : 787330 : ni2dest = regno_reg_rtx[REGNO (i2dest)];
3620 : : }
3621 : :
3622 : 796411 : parallel = (gen_rtx_PARALLEL
3623 : : (VOIDmode,
3624 : : gen_rtvec (2, newpat,
3625 : : gen_rtx_CLOBBER (VOIDmode,
3626 : : ni2dest))));
3627 : 796411 : m_split_insn = combine_split_insns (parallel, i3);
3628 : :
3629 : 796411 : if (m_split_insn == 0
3630 : 796411 : && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3631 : : {
3632 : 787330 : struct undo *buf;
3633 : :
3634 : 787330 : adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3635 : 787330 : buf = undobuf.undos;
3636 : 787330 : undobuf.undos = buf->next;
3637 : 787330 : buf->next = undobuf.frees;
3638 : 787330 : undobuf.frees = buf;
3639 : : }
3640 : : }
3641 : :
3642 : 4130262 : i2scratch = m_split_insn != 0;
3643 : : }
3644 : :
3645 : : /* If recog_for_combine has discarded clobbers, try to use them
3646 : : again for the split. */
3647 : 4262792 : if (m_split_insn == 0 && newpat_vec_with_clobbers)
3648 : : {
3649 : 1502305 : parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3650 : 1502305 : m_split_insn = combine_split_insns (parallel, i3);
3651 : : }
3652 : :
3653 : 4273435 : if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3654 : : {
3655 : 1340 : rtx m_split_pat = PATTERN (m_split_insn);
3656 : 1340 : insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3657 : 1340 : if (insn_code_number >= 0)
3658 : 139 : newpat = m_split_pat;
3659 : : }
3660 : 9303 : else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3661 : 4270755 : && (next_nonnote_nondebug_insn (i2) == i3
3662 : 29 : || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3663 : : {
3664 : 9303 : rtx i2set, i3set;
3665 : 9303 : rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3666 : 9303 : newi2pat = PATTERN (m_split_insn);
3667 : :
3668 : 9303 : i3set = single_set (NEXT_INSN (m_split_insn));
3669 : 9303 : i2set = single_set (m_split_insn);
3670 : :
3671 : 9303 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3672 : :
3673 : : /* If I2 or I3 has multiple SETs, we won't know how to track
3674 : : register status, so don't use these insns. If I2's destination
3675 : : is used between I2 and I3, we also can't use these insns. */
3676 : :
3677 : 9303 : if (i2_code_number >= 0 && i2set && i3set
3678 : 18606 : && (next_nonnote_nondebug_insn (i2) == i3
3679 : 29 : || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3680 : 9303 : insn_code_number = recog_for_combine (&newi3pat, i3,
3681 : : &new_i3_notes);
3682 : 9303 : if (insn_code_number >= 0)
3683 : 9301 : newpat = newi3pat;
3684 : :
3685 : : /* It is possible that both insns now set the destination of I3.
3686 : : If so, we must show an extra use of it. */
3687 : :
3688 : 9303 : if (insn_code_number >= 0)
3689 : : {
3690 : 9301 : rtx new_i3_dest = SET_DEST (i3set);
3691 : 9301 : rtx new_i2_dest = SET_DEST (i2set);
3692 : :
3693 : 9301 : while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3694 : 9339 : || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3695 : 18660 : || GET_CODE (new_i3_dest) == SUBREG)
3696 : 38 : new_i3_dest = XEXP (new_i3_dest, 0);
3697 : :
3698 : 9301 : while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3699 : 9301 : || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3700 : 18602 : || GET_CODE (new_i2_dest) == SUBREG)
3701 : 0 : new_i2_dest = XEXP (new_i2_dest, 0);
3702 : :
3703 : 9301 : if (REG_P (new_i3_dest)
3704 : 6077 : && REG_P (new_i2_dest)
3705 : 6077 : && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3706 : 9301 : && REGNO (new_i2_dest) < reg_n_sets_max)
3707 : 0 : INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3708 : : }
3709 : : }
3710 : :
3711 : : /* If we can split it and use I2DEST, go ahead and see if that
3712 : : helps things be recognized. Verify that none of the registers
3713 : : are set between I2 and I3. */
3714 : 1203 : if (insn_code_number < 0
3715 : 4253352 : && (split = find_split_point (&newpat, i3, false)) != 0
3716 : : /* We need I2DEST in the proper mode. If it is a hard register
3717 : : or the only use of a pseudo, we can change its mode.
3718 : : Make sure we don't change a hard register to have a mode that
3719 : : isn't valid for it, or change the number of registers. */
3720 : 4049462 : && (GET_MODE (*split) == GET_MODE (i2dest)
3721 : 1510717 : || GET_MODE (*split) == VOIDmode
3722 : 1165744 : || can_change_dest_mode (i2dest, added_sets_2,
3723 : : GET_MODE (*split)))
3724 : 3445718 : && (next_nonnote_nondebug_insn (i2) == i3
3725 : 549580 : || !modified_between_p (*split, i2, i3))
3726 : : /* We can't overwrite I2DEST if its value is still used by
3727 : : NEWPAT. */
3728 : 3417328 : && ! reg_referenced_p (i2dest, newpat)
3729 : : /* We should not split a possibly trapping part when we
3730 : : care about non-call EH and have REG_EH_REGION notes
3731 : : to distribute. */
3732 : 7617273 : && ! (cfun->can_throw_non_call_exceptions
3733 : 364842 : && has_non_call_exception
3734 : 127 : && may_trap_p (*split)))
3735 : : {
3736 : 3355557 : rtx newdest = i2dest;
3737 : 3355557 : enum rtx_code split_code = GET_CODE (*split);
3738 : 3355557 : machine_mode split_mode = GET_MODE (*split);
3739 : 3355557 : bool subst_done = false;
3740 : 3355557 : newi2pat = NULL_RTX;
3741 : :
3742 : 3355557 : i2scratch = true;
3743 : :
3744 : : /* *SPLIT may be part of I2SRC, so make sure we have the
3745 : : original expression around for later debug processing.
3746 : : We should not need I2SRC any more in other cases. */
3747 : 3355557 : if (MAY_HAVE_DEBUG_BIND_INSNS)
3748 : 1601367 : i2src = copy_rtx (i2src);
3749 : : else
3750 : 1754190 : i2src = NULL;
3751 : :
3752 : : /* Get NEWDEST as a register in the proper mode. We have already
3753 : : validated that we can do this. */
3754 : 3355557 : if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3755 : : {
3756 : 559977 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3757 : 0 : newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3758 : : else
3759 : : {
3760 : 559977 : subst_mode (REGNO (i2dest), split_mode);
3761 : 559977 : newdest = regno_reg_rtx[REGNO (i2dest)];
3762 : : }
3763 : : }
3764 : :
3765 : : /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3766 : : an ASHIFT. This can occur if it was inside a PLUS and hence
3767 : : appeared to be a memory address. This is a kludge. */
3768 : 3355557 : if (split_code == MULT
3769 : 202012 : && CONST_INT_P (XEXP (*split, 1))
3770 : 106601 : && INTVAL (XEXP (*split, 1)) > 0
3771 : 3457437 : && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3772 : : {
3773 : 70496 : rtx i_rtx = gen_int_shift_amount (split_mode, i);
3774 : 70496 : SUBST (*split, gen_rtx_ASHIFT (split_mode,
3775 : : XEXP (*split, 0), i_rtx));
3776 : : /* Update split_code because we may not have a multiply
3777 : : anymore. */
3778 : 70496 : split_code = GET_CODE (*split);
3779 : : }
3780 : :
3781 : : /* Similarly for (plus (mult FOO (const_int pow2))). */
3782 : 3355557 : if (split_code == PLUS
3783 : 639392 : && GET_CODE (XEXP (*split, 0)) == MULT
3784 : 109102 : && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3785 : 40060 : && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3786 : 3391170 : && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3787 : : {
3788 : 6690 : rtx nsplit = XEXP (*split, 0);
3789 : 6690 : rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3790 : 6690 : SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3791 : : XEXP (nsplit, 0),
3792 : : i_rtx));
3793 : : /* Update split_code because we may not have a multiply
3794 : : anymore. */
3795 : 6690 : split_code = GET_CODE (*split);
3796 : : }
3797 : :
3798 : : #ifdef INSN_SCHEDULING
3799 : : /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3800 : : be written as a ZERO_EXTEND. */
3801 : 3355557 : if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3802 : : {
3803 : : /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3804 : : what it really is. */
3805 : 9530 : if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3806 : : == SIGN_EXTEND)
3807 : : SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3808 : : SUBREG_REG (*split)));
3809 : : else
3810 : 9530 : SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3811 : : SUBREG_REG (*split)));
3812 : : }
3813 : : #endif
3814 : :
3815 : : /* Attempt to split binary operators using arithmetic identities. */
3816 : 3355557 : if (BINARY_P (SET_SRC (newpat))
3817 : 2802244 : && split_mode == GET_MODE (SET_SRC (newpat))
3818 : 5258185 : && ! side_effects_p (SET_SRC (newpat)))
3819 : : {
3820 : 1885657 : rtx setsrc = SET_SRC (newpat);
3821 : 1885657 : machine_mode mode = GET_MODE (setsrc);
3822 : 1885657 : enum rtx_code code = GET_CODE (setsrc);
3823 : 1885657 : rtx src_op0 = XEXP (setsrc, 0);
3824 : 1885657 : rtx src_op1 = XEXP (setsrc, 1);
3825 : :
3826 : : /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3827 : 1885657 : if (rtx_equal_p (src_op0, src_op1))
3828 : : {
3829 : 1420 : newi2pat = gen_rtx_SET (newdest, src_op0);
3830 : 1420 : SUBST (XEXP (setsrc, 0), newdest);
3831 : 1420 : SUBST (XEXP (setsrc, 1), newdest);
3832 : 1420 : subst_done = true;
3833 : : }
3834 : : /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3835 : 1884237 : else if ((code == PLUS || code == MULT)
3836 : 916236 : && GET_CODE (src_op0) == code
3837 : 390218 : && GET_CODE (XEXP (src_op0, 0)) == code
3838 : 170089 : && (INTEGRAL_MODE_P (mode)
3839 : : || (FLOAT_MODE_P (mode)
3840 : 98558 : && flag_unsafe_math_optimizations)))
3841 : : {
3842 : 75655 : rtx p = XEXP (XEXP (src_op0, 0), 0);
3843 : 75655 : rtx q = XEXP (XEXP (src_op0, 0), 1);
3844 : 75655 : rtx r = XEXP (src_op0, 1);
3845 : 75655 : rtx s = src_op1;
3846 : :
3847 : : /* Split both "((X op Y) op X) op Y" and
3848 : : "((X op Y) op Y) op X" as "T op T" where T is
3849 : : "X op Y". */
3850 : 75863 : if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3851 : 75794 : || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3852 : : {
3853 : 69 : newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3854 : 69 : SUBST (XEXP (setsrc, 0), newdest);
3855 : 69 : SUBST (XEXP (setsrc, 1), newdest);
3856 : 69 : subst_done = true;
3857 : : }
3858 : : /* Split "((X op X) op Y) op Y)" as "T op T" where
3859 : : T is "X op Y". */
3860 : 75586 : else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3861 : : {
3862 : 25 : rtx tmp = simplify_gen_binary (code, mode, p, r);
3863 : 25 : newi2pat = gen_rtx_SET (newdest, tmp);
3864 : 25 : SUBST (XEXP (setsrc, 0), newdest);
3865 : 25 : SUBST (XEXP (setsrc, 1), newdest);
3866 : 25 : subst_done = true;
3867 : : }
3868 : : }
3869 : : }
3870 : :
3871 : 1514 : if (!subst_done)
3872 : : {
3873 : 3354043 : newi2pat = gen_rtx_SET (newdest, *split);
3874 : 3354043 : SUBST (*split, newdest);
3875 : : }
3876 : :
3877 : 3355557 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3878 : :
3879 : : /* recog_for_combine might have added CLOBBERs to newi2pat.
3880 : : Make sure NEWPAT does not depend on the clobbered regs. */
3881 : 3355557 : if (GET_CODE (newi2pat) == PARALLEL)
3882 : 2334954 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3883 : 1567531 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3884 : : {
3885 : 800108 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3886 : 800108 : if (reg_overlap_mentioned_p (reg, newpat))
3887 : : {
3888 : 16621 : undo_all ();
3889 : 16621 : return 0;
3890 : : }
3891 : : }
3892 : :
3893 : : /* If the split point was a MULT and we didn't have one before,
3894 : : don't use one now. */
3895 : 3338936 : if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3896 : 2033076 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3897 : : }
3898 : : }
3899 : :
3900 : : /* Check for a case where we loaded from memory in a narrow mode and
3901 : : then sign extended it, but we need both registers. In that case,
3902 : : we have a PARALLEL with both loads from the same memory location.
3903 : : We can split this into a load from memory followed by a register-register
3904 : : copy. This saves at least one insn, more if register allocation can
3905 : : eliminate the copy.
3906 : :
3907 : : We cannot do this if the destination of the first assignment is a
3908 : : condition code register. We eliminate this case by making sure
3909 : : the SET_DEST and SET_SRC have the same mode.
3910 : :
3911 : : We cannot do this if the destination of the second assignment is
3912 : : a register that we have already assumed is zero-extended. Similarly
3913 : : for a SUBREG of such a register. */
3914 : :
3915 : 5115046 : else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3916 : 5072448 : && GET_CODE (newpat) == PARALLEL
3917 : 5070372 : && XVECLEN (newpat, 0) == 2
3918 : 4261638 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3919 : 4261277 : && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3920 : 23638 : && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3921 : 23638 : == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3922 : 23638 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3923 : 23638 : && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3924 : 23638 : XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3925 : 5890 : && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3926 : 5890 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3927 : 5890 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3928 : 5890 : && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3929 : : (REG_P (temp_expr)
3930 : 5890 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3931 : 5977 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3932 : : BITS_PER_WORD)
3933 : 5762 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3934 : : HOST_BITS_PER_INT)
3935 : 1101 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3936 : 1101 : != GET_MODE_MASK (word_mode))))
3937 : 5874 : && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3938 : 0 : && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3939 : 0 : (REG_P (temp_expr)
3940 : 0 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3941 : 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3942 : : BITS_PER_WORD)
3943 : 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3944 : : HOST_BITS_PER_INT)
3945 : 0 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3946 : 0 : != GET_MODE_MASK (word_mode)))))
3947 : 5874 : && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3948 : 5874 : SET_SRC (XVECEXP (newpat, 0, 1)))
3949 : 26810593 : && ! find_reg_note (i3, REG_UNUSED,
3950 : 5789 : SET_DEST (XVECEXP (newpat, 0, 0))))
3951 : : {
3952 : 5789 : rtx ni2dest;
3953 : :
3954 : 5789 : newi2pat = XVECEXP (newpat, 0, 0);
3955 : 5789 : ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3956 : 5789 : newpat = XVECEXP (newpat, 0, 1);
3957 : 5789 : SUBST (SET_SRC (newpat),
3958 : : gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3959 : 5789 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3960 : :
3961 : 5789 : if (i2_code_number >= 0)
3962 : 0 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3963 : :
3964 : 5789 : if (insn_code_number >= 0)
3965 : : swap_i2i3 = 1;
3966 : : }
3967 : :
3968 : : /* Similarly, check for a case where we have a PARALLEL of two independent
3969 : : SETs but we started with three insns. In this case, we can do the sets
3970 : : as two separate insns. This case occurs when some SET allows two
3971 : : other insns to combine, but the destination of that SET is still live.
3972 : :
3973 : : Also do this if we started with two insns and (at least) one of the
3974 : : resulting sets is a noop; this noop will be deleted later.
3975 : :
3976 : : Also do this if we started with two insns neither of which was a simple
3977 : : move. */
3978 : :
3979 : 23050731 : else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3980 : 23033963 : && GET_CODE (newpat) == PARALLEL
3981 : 10177615 : && XVECLEN (newpat, 0) == 2
3982 : 9249050 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3983 : 9149756 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3984 : 9100007 : && (i1
3985 : 4861112 : || set_noop_p (XVECEXP (newpat, 0, 0))
3986 : 4860770 : || set_noop_p (XVECEXP (newpat, 0, 1))
3987 : 4860762 : || (!i2_was_move && !i3_was_move))
3988 : 6070516 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3989 : 6069750 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3990 : 6069563 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3991 : 6069000 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3992 : 6068989 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3993 : : XVECEXP (newpat, 0, 0))
3994 : 4757725 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3995 : 4757725 : XVECEXP (newpat, 0, 1))
3996 : 31834246 : && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3997 : 400003 : && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3998 : : {
3999 : 4425230 : rtx set0 = XVECEXP (newpat, 0, 0);
4000 : 4425230 : rtx set1 = XVECEXP (newpat, 0, 1);
4001 : :
4002 : : /* Normally, it doesn't matter which of the two is done first, but
4003 : : one which uses any regs/memory set in between i2 and i3 can't
4004 : : be first. The PARALLEL might also have been pre-existing in i3,
4005 : : so we need to make sure that we won't wrongly hoist a SET to i2
4006 : : that would conflict with a death note present in there, or would
4007 : : have its dest modified between i2 and i3. */
4008 : 4425230 : if (!modified_between_p (SET_SRC (set1), i2, i3)
4009 : 8819862 : && !(REG_P (SET_DEST (set1))
4010 : 4402783 : && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4011 : 4430880 : && !(GET_CODE (SET_DEST (set1)) == SUBREG
4012 : 14296 : && find_reg_note (i2, REG_DEAD,
4013 : 14296 : SUBREG_REG (SET_DEST (set1))))
4014 : 4416584 : && !modified_between_p (SET_DEST (set1), i2, i3)
4015 : : /* If I3 is a jump, ensure that set0 is a jump so that
4016 : : we do not create invalid RTL. */
4017 : 8841814 : && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
4018 : : )
4019 : : {
4020 : 4416584 : newi2pat = set1;
4021 : 4416584 : newpat = set0;
4022 : : }
4023 : 8646 : else if (!modified_between_p (SET_SRC (set0), i2, i3)
4024 : 990 : && !(REG_P (SET_DEST (set0))
4025 : 495 : && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4026 : 495 : && !(GET_CODE (SET_DEST (set0)) == SUBREG
4027 : 0 : && find_reg_note (i2, REG_DEAD,
4028 : 0 : SUBREG_REG (SET_DEST (set0))))
4029 : 495 : && !modified_between_p (SET_DEST (set0), i2, i3)
4030 : : /* If I3 is a jump, ensure that set1 is a jump so that
4031 : : we do not create invalid RTL. */
4032 : 9140 : && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
4033 : : )
4034 : : {
4035 : 494 : newi2pat = set0;
4036 : 494 : newpat = set1;
4037 : : }
4038 : : else
4039 : : {
4040 : 8152 : undo_all ();
4041 : 8152 : return 0;
4042 : : }
4043 : :
4044 : 4417078 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4045 : :
4046 : 4417078 : if (i2_code_number >= 0)
4047 : : {
4048 : : /* recog_for_combine might have added CLOBBERs to newi2pat.
4049 : : Make sure NEWPAT does not depend on the clobbered regs. */
4050 : 3246207 : if (GET_CODE (newi2pat) == PARALLEL)
4051 : : {
4052 : 1201838 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4053 : 804574 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4054 : : {
4055 : 407310 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4056 : 407310 : if (reg_overlap_mentioned_p (reg, newpat))
4057 : : {
4058 : 2462 : undo_all ();
4059 : 2462 : return 0;
4060 : : }
4061 : : }
4062 : : }
4063 : :
4064 : 3243745 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4065 : :
4066 : : /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4067 : : Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4068 : : mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4069 : 3243745 : if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4070 : : {
4071 : 65151 : for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4072 : 43444 : if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4073 : : {
4074 : 21737 : rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4075 : 21737 : if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4076 : 21737 : || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4077 : : {
4078 : 0 : undo_all ();
4079 : 0 : return 0;
4080 : : }
4081 : : }
4082 : : }
4083 : :
4084 : : if (insn_code_number >= 0)
4085 : : split_i2i3 = true;
4086 : : }
4087 : : }
4088 : :
4089 : : /* If it still isn't recognized, fail and change things back the way they
4090 : : were. */
4091 : 27790827 : if ((insn_code_number < 0
4092 : : /* Is the result a reasonable ASM_OPERANDS? */
4093 : 30898387 : && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4094 : : {
4095 : 27096393 : undo_all ();
4096 : 27096393 : return 0;
4097 : : }
4098 : :
4099 : : /* If we had to change another insn, make sure it is valid also. */
4100 : 3943968 : if (undobuf.other_insn)
4101 : : {
4102 : 202512 : CLEAR_HARD_REG_SET (newpat_used_regs);
4103 : :
4104 : 202512 : other_pat = PATTERN (undobuf.other_insn);
4105 : 202512 : other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4106 : : &new_other_notes);
4107 : :
4108 : 202512 : if (other_code_number < 0 && ! check_asm_operands (other_pat))
4109 : : {
4110 : 7831 : undo_all ();
4111 : 7831 : return 0;
4112 : : }
4113 : : }
4114 : :
4115 : : /* Only allow this combination if insn_cost reports that the
4116 : : replacement instructions are cheaper than the originals. */
4117 : 3936137 : if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4118 : : {
4119 : 200689 : undo_all ();
4120 : 200689 : return 0;
4121 : : }
4122 : :
4123 : 3735448 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4124 : : {
4125 : 2081727 : struct undo *undo;
4126 : :
4127 : 6222748 : for (undo = undobuf.undos; undo; undo = undo->next)
4128 : 4141021 : if (undo->kind == UNDO_MODE)
4129 : : {
4130 : 2787 : rtx reg = regno_reg_rtx[undo->where.regno];
4131 : 2787 : machine_mode new_mode = GET_MODE (reg);
4132 : 2787 : machine_mode old_mode = undo->old_contents.m;
4133 : :
4134 : : /* Temporarily revert mode back. */
4135 : 2787 : adjust_reg_mode (reg, old_mode);
4136 : :
4137 : 2787 : if (reg == i2dest && i2scratch)
4138 : : {
4139 : : /* If we used i2dest as a scratch register with a
4140 : : different mode, substitute it for the original
4141 : : i2src while its original mode is temporarily
4142 : : restored, and then clear i2scratch so that we don't
4143 : : do it again later. */
4144 : 2787 : propagate_for_debug (i2, last_combined_insn, reg, i2src,
4145 : : this_basic_block);
4146 : 2787 : i2scratch = false;
4147 : : /* Put back the new mode. */
4148 : 2787 : adjust_reg_mode (reg, new_mode);
4149 : : }
4150 : : else
4151 : : {
4152 : 0 : rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4153 : 0 : rtx_insn *first, *last;
4154 : :
4155 : 0 : if (reg == i2dest)
4156 : : {
4157 : : first = i2;
4158 : : last = last_combined_insn;
4159 : : }
4160 : : else
4161 : : {
4162 : 0 : first = i3;
4163 : 0 : last = undobuf.other_insn;
4164 : 0 : gcc_assert (last);
4165 : 0 : if (DF_INSN_LUID (last)
4166 : 0 : < DF_INSN_LUID (last_combined_insn))
4167 : 0 : last = last_combined_insn;
4168 : : }
4169 : :
4170 : : /* We're dealing with a reg that changed mode but not
4171 : : meaning, so we want to turn it into a subreg for
4172 : : the new mode. However, because of REG sharing and
4173 : : because its mode had already changed, we have to do
4174 : : it in two steps. First, replace any debug uses of
4175 : : reg, with its original mode temporarily restored,
4176 : : with this copy we have created; then, replace the
4177 : : copy with the SUBREG of the original shared reg,
4178 : : once again changed to the new mode. */
4179 : 0 : propagate_for_debug (first, last, reg, tempreg,
4180 : : this_basic_block);
4181 : 0 : adjust_reg_mode (reg, new_mode);
4182 : 0 : propagate_for_debug (first, last, tempreg,
4183 : : lowpart_subreg (old_mode, reg, new_mode),
4184 : : this_basic_block);
4185 : : }
4186 : : }
4187 : : }
4188 : :
4189 : : /* If we will be able to accept this, we have made a
4190 : : change to the destination of I3. This requires us to
4191 : : do a few adjustments. */
4192 : :
4193 : 3735448 : if (changed_i3_dest)
4194 : : {
4195 : 16722 : PATTERN (i3) = newpat;
4196 : 16722 : adjust_for_new_dest (i3);
4197 : : }
4198 : :
4199 : : /* If I2 didn't change, this is not a combination (but a simplification or
4200 : : canonicalisation with context), which should not be done here. Doing
4201 : : it here explodes the algorithm. Don't. */
4202 : 3735448 : if (rtx_equal_p (newi2pat, PATTERN (i2)))
4203 : : {
4204 : 27305 : if (dump_file)
4205 : 1 : fprintf (dump_file, "i2 didn't change, not doing this\n");
4206 : 27305 : undo_all ();
4207 : 27305 : return 0;
4208 : : }
4209 : :
4210 : : /* We now know that we can do this combination. Merge the insns and
4211 : : update the status of registers and LOG_LINKS. */
4212 : :
4213 : 3708143 : if (undobuf.other_insn)
4214 : : {
4215 : 194352 : rtx note, next;
4216 : :
4217 : 194352 : PATTERN (undobuf.other_insn) = other_pat;
4218 : :
4219 : : /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4220 : : ensure that they are still valid. Then add any non-duplicate
4221 : : notes added by recog_for_combine. */
4222 : 581537 : for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4223 : : {
4224 : 387185 : next = XEXP (note, 1);
4225 : :
4226 : 387185 : if ((REG_NOTE_KIND (note) == REG_DEAD
4227 : 196919 : && !reg_referenced_p (XEXP (note, 0),
4228 : 196919 : PATTERN (undobuf.other_insn)))
4229 : 383183 : ||(REG_NOTE_KIND (note) == REG_UNUSED
4230 : 28 : && !reg_set_p (XEXP (note, 0),
4231 : 28 : PATTERN (undobuf.other_insn)))
4232 : : /* Simply drop equal note since it may be no longer valid
4233 : : for other_insn. It may be possible to record that CC
4234 : : register is changed and only discard those notes, but
4235 : : in practice it's unnecessary complication and doesn't
4236 : : give any meaningful improvement.
4237 : :
4238 : : See PR78559. */
4239 : 383183 : || REG_NOTE_KIND (note) == REG_EQUAL
4240 : 770234 : || REG_NOTE_KIND (note) == REG_EQUIV)
4241 : 4136 : remove_note (undobuf.other_insn, note);
4242 : : }
4243 : :
4244 : 194352 : distribute_notes (new_other_notes, undobuf.other_insn,
4245 : : undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4246 : : NULL_RTX);
4247 : : }
4248 : :
4249 : 3708143 : if (swap_i2i3)
4250 : : {
4251 : : /* I3 now uses what used to be its destination and which is now
4252 : : I2's destination. This requires us to do a few adjustments. */
4253 : 0 : PATTERN (i3) = newpat;
4254 : 0 : adjust_for_new_dest (i3);
4255 : : }
4256 : :
4257 : 3708143 : if (swap_i2i3 || split_i2i3)
4258 : : {
4259 : : /* We might need a LOG_LINK from I3 to I2. But then we used to
4260 : : have one, so we still will.
4261 : :
4262 : : However, some later insn might be using I2's dest and have
4263 : : a LOG_LINK pointing at I3. We should change it to point at
4264 : : I2 instead. */
4265 : :
4266 : : /* newi2pat is usually a SET here; however, recog_for_combine might
4267 : : have added some clobbers. */
4268 : 25451 : rtx x = newi2pat;
4269 : 25451 : if (GET_CODE (x) == PARALLEL)
4270 : 986 : x = XVECEXP (newi2pat, 0, 0);
4271 : :
4272 : 25451 : if (REG_P (SET_DEST (x))
4273 : 0 : || (GET_CODE (SET_DEST (x)) == SUBREG
4274 : 0 : && REG_P (SUBREG_REG (SET_DEST (x)))))
4275 : : {
4276 : 25451 : unsigned int regno = reg_or_subregno (SET_DEST (x));
4277 : :
4278 : 25451 : bool done = false;
4279 : 479418 : for (rtx_insn *insn = NEXT_INSN (i3);
4280 : 479418 : !done
4281 : 479418 : && insn
4282 : 477934 : && INSN_P (insn)
4283 : 933385 : && BLOCK_FOR_INSN (insn) == this_basic_block;
4284 : 453967 : insn = NEXT_INSN (insn))
4285 : : {
4286 : 453967 : if (DEBUG_INSN_P (insn))
4287 : 150392 : continue;
4288 : 303575 : struct insn_link *link;
4289 : 571192 : FOR_EACH_LOG_LINK (link, insn)
4290 : 267627 : if (link->insn == i3 && link->regno == regno)
4291 : : {
4292 : 10 : link->insn = i2;
4293 : 10 : done = true;
4294 : 10 : break;
4295 : : }
4296 : : }
4297 : : }
4298 : : }
4299 : :
4300 : 3708143 : {
4301 : 3708143 : rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4302 : 3708143 : struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4303 : 3708143 : rtx midnotes = 0;
4304 : 3708143 : int from_luid;
4305 : : /* Compute which registers we expect to eliminate. newi2pat may be setting
4306 : : either i3dest or i2dest, so we must check it. */
4307 : 64950 : rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4308 : 3655813 : || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4309 : 3578926 : || !i2dest_killed
4310 : 7286027 : ? 0 : i2dest);
4311 : : /* For i1, we need to compute both local elimination and global
4312 : : elimination information with respect to newi2pat because i1dest
4313 : : may be the same as i3dest, in which case newi2pat may be setting
4314 : : i1dest. Global information is used when distributing REG_DEAD
4315 : : note for i2 and i3, in which case it does matter if newi2pat sets
4316 : : i1dest or not.
4317 : :
4318 : : Local information is used when distributing REG_DEAD note for i1,
4319 : : in which case it doesn't matter if newi2pat sets i1dest or not.
4320 : : See PR62151, if we have four insns combination:
4321 : : i0: r0 <- i0src
4322 : : i1: r1 <- i1src (using r0)
4323 : : REG_DEAD (r0)
4324 : : i2: r0 <- i2src (using r1)
4325 : : i3: r3 <- i3src (using r0)
4326 : : ix: using r0
4327 : : From i1's point of view, r0 is eliminated, no matter if it is set
4328 : : by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4329 : : should be discarded.
4330 : :
4331 : : Note local information only affects cases in forms like "I1->I2->I3",
4332 : : "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4333 : : "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4334 : : i0dest anyway. */
4335 : 84222 : rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4336 : 84160 : || !i1dest_killed
4337 : 3708143 : ? 0 : i1dest);
4338 : 84160 : rtx elim_i1 = (local_elim_i1 == 0
4339 : 84160 : || (newi2pat && reg_set_p (i1dest, newi2pat))
4340 : 84160 : ? 0 : i1dest);
4341 : : /* Same case as i1. */
4342 : 4684 : rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4343 : 3708143 : ? 0 : i0dest);
4344 : 4666 : rtx elim_i0 = (local_elim_i0 == 0
4345 : 4666 : || (newi2pat && reg_set_p (i0dest, newi2pat))
4346 : 4666 : ? 0 : i0dest);
4347 : :
4348 : : /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4349 : : clear them. */
4350 : 3708143 : i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4351 : 3708143 : i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4352 : 3708143 : if (i1)
4353 : 84222 : i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4354 : 3708143 : if (i0)
4355 : 4684 : i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4356 : :
4357 : : /* Ensure that we do not have something that should not be shared but
4358 : : occurs multiple times in the new insns. Check this by first
4359 : : resetting all the `used' flags and then copying anything is shared. */
4360 : :
4361 : 3708143 : reset_used_flags (i3notes);
4362 : 3708143 : reset_used_flags (i2notes);
4363 : 3708143 : reset_used_flags (i1notes);
4364 : 3708143 : reset_used_flags (i0notes);
4365 : 3708143 : reset_used_flags (newpat);
4366 : 3708143 : reset_used_flags (newi2pat);
4367 : 3708143 : if (undobuf.other_insn)
4368 : 194352 : reset_used_flags (PATTERN (undobuf.other_insn));
4369 : :
4370 : 3708143 : i3notes = copy_rtx_if_shared (i3notes);
4371 : 3708143 : i2notes = copy_rtx_if_shared (i2notes);
4372 : 3708143 : i1notes = copy_rtx_if_shared (i1notes);
4373 : 3708143 : i0notes = copy_rtx_if_shared (i0notes);
4374 : 3708143 : newpat = copy_rtx_if_shared (newpat);
4375 : 3708143 : newi2pat = copy_rtx_if_shared (newi2pat);
4376 : 3708143 : if (undobuf.other_insn)
4377 : 194352 : reset_used_flags (PATTERN (undobuf.other_insn));
4378 : :
4379 : 3708143 : INSN_CODE (i3) = insn_code_number;
4380 : 3708143 : PATTERN (i3) = newpat;
4381 : :
4382 : 3708143 : if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4383 : : {
4384 : 212531 : for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4385 : 140882 : link = XEXP (link, 1))
4386 : : {
4387 : 140882 : if (substed_i2)
4388 : : {
4389 : : /* I2SRC must still be meaningful at this point. Some
4390 : : splitting operations can invalidate I2SRC, but those
4391 : : operations do not apply to calls. */
4392 : 140882 : gcc_assert (i2src);
4393 : 140882 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4394 : : i2dest, i2src);
4395 : : }
4396 : 140882 : if (substed_i1)
4397 : 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4398 : : i1dest, i1src);
4399 : 140882 : if (substed_i0)
4400 : 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4401 : : i0dest, i0src);
4402 : : }
4403 : : }
4404 : :
4405 : 3708143 : if (undobuf.other_insn)
4406 : 194352 : INSN_CODE (undobuf.other_insn) = other_code_number;
4407 : :
4408 : : /* We had one special case above where I2 had more than one set and
4409 : : we replaced a destination of one of those sets with the destination
4410 : : of I3. In that case, we have to update LOG_LINKS of insns later
4411 : : in this basic block. Note that this (expensive) case is rare.
4412 : :
4413 : : Also, in this case, we must pretend that all REG_NOTEs for I2
4414 : : actually came from I3, so that REG_UNUSED notes from I2 will be
4415 : : properly handled. */
4416 : :
4417 : 3708143 : if (i3_subst_into_i2)
4418 : : {
4419 : 145343 : for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4420 : 98862 : if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4421 : 47740 : || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4422 : 98069 : && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4423 : 89448 : && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4424 : 188310 : && ! find_reg_note (i2, REG_UNUSED,
4425 : 89448 : SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4426 : 21658633 : for (temp_insn = NEXT_INSN (i2);
4427 : : temp_insn
4428 : 21658633 : && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4429 : 21577026 : || BB_HEAD (this_basic_block) != temp_insn);
4430 : 21619024 : temp_insn = NEXT_INSN (temp_insn))
4431 : 21619024 : if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4432 : 14790070 : FOR_EACH_LOG_LINK (link, temp_insn)
4433 : 5501195 : if (link->insn == i2)
4434 : 499 : link->insn = i3;
4435 : :
4436 : 46481 : if (i3notes)
4437 : : {
4438 : : rtx link = i3notes;
4439 : 53320 : while (XEXP (link, 1))
4440 : : link = XEXP (link, 1);
4441 : 46481 : XEXP (link, 1) = i2notes;
4442 : : }
4443 : : else
4444 : : i3notes = i2notes;
4445 : : i2notes = 0;
4446 : : }
4447 : :
4448 : 3708143 : LOG_LINKS (i3) = NULL;
4449 : 3708143 : REG_NOTES (i3) = 0;
4450 : 3708143 : LOG_LINKS (i2) = NULL;
4451 : 3708143 : REG_NOTES (i2) = 0;
4452 : :
4453 : 3708143 : if (newi2pat)
4454 : : {
4455 : 64950 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4456 : 11161 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4457 : : this_basic_block);
4458 : 64950 : INSN_CODE (i2) = i2_code_number;
4459 : 64950 : PATTERN (i2) = newi2pat;
4460 : : }
4461 : : else
4462 : : {
4463 : 3643193 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4464 : 2019972 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4465 : : this_basic_block);
4466 : 3643193 : SET_INSN_DELETED (i2);
4467 : : }
4468 : :
4469 : 3708143 : if (i1)
4470 : : {
4471 : 84222 : LOG_LINKS (i1) = NULL;
4472 : 84222 : REG_NOTES (i1) = 0;
4473 : 84222 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4474 : 42756 : propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4475 : : this_basic_block);
4476 : 84222 : SET_INSN_DELETED (i1);
4477 : : }
4478 : :
4479 : 3708143 : if (i0)
4480 : : {
4481 : 4684 : LOG_LINKS (i0) = NULL;
4482 : 4684 : REG_NOTES (i0) = 0;
4483 : 4684 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4484 : 3517 : propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4485 : : this_basic_block);
4486 : 4684 : SET_INSN_DELETED (i0);
4487 : : }
4488 : :
4489 : : /* Get death notes for everything that is now used in either I3 or
4490 : : I2 and used to die in a previous insn. If we built two new
4491 : : patterns, move from I1 to I2 then I2 to I3 so that we get the
4492 : : proper movement on registers that I2 modifies. */
4493 : :
4494 : 3708143 : if (i0)
4495 : 4684 : from_luid = DF_INSN_LUID (i0);
4496 : 3703459 : else if (i1)
4497 : 79538 : from_luid = DF_INSN_LUID (i1);
4498 : : else
4499 : 3623921 : from_luid = DF_INSN_LUID (i2);
4500 : 3708143 : if (newi2pat)
4501 : 64950 : move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4502 : 3708143 : move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4503 : :
4504 : : /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4505 : 3708143 : if (i3notes)
4506 : 6809674 : distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4507 : : elim_i2, elim_i1, elim_i0);
4508 : 3708143 : if (i2notes)
4509 : 5287405 : distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4510 : : elim_i2, elim_i1, elim_i0);
4511 : 3708143 : if (i1notes)
4512 : 57653 : distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4513 : : elim_i2, local_elim_i1, local_elim_i0);
4514 : 3708143 : if (i0notes)
4515 : 3859 : distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4516 : : elim_i2, elim_i1, local_elim_i0);
4517 : 3708143 : if (midnotes)
4518 : 4537723 : distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4519 : : elim_i2, elim_i1, elim_i0);
4520 : :
4521 : : /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4522 : : know these are REG_UNUSED and want them to go to the desired insn,
4523 : : so we always pass it as i3. */
4524 : :
4525 : 3708143 : if (newi2pat && new_i2_notes)
4526 : 20514 : distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4527 : : NULL_RTX);
4528 : :
4529 : 3708143 : if (new_i3_notes)
4530 : 117918 : distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4531 : : NULL_RTX);
4532 : :
4533 : : /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4534 : : put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4535 : : I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4536 : : in that case, it might delete I2. Similarly for I2 and I1.
4537 : : Show an additional death due to the REG_DEAD note we make here. If
4538 : : we discard it in distribute_notes, we will decrement it again. */
4539 : :
4540 : 3708143 : if (i3dest_killed)
4541 : : {
4542 : 294320 : rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4543 : 294320 : if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4544 : 964 : distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4545 : : elim_i1, elim_i0);
4546 : : else
4547 : 585793 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4548 : : elim_i2, elim_i1, elim_i0);
4549 : : }
4550 : :
4551 : 3708143 : if (i2dest_in_i2src)
4552 : : {
4553 : 75369 : rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4554 : 75369 : if (newi2pat && reg_set_p (i2dest, newi2pat))
4555 : 98 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4556 : : NULL_RTX, NULL_RTX);
4557 : : else
4558 : 150522 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4559 : : NULL_RTX, NULL_RTX, NULL_RTX);
4560 : : }
4561 : :
4562 : 3708143 : if (i1dest_in_i1src)
4563 : : {
4564 : 60 : rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4565 : 60 : if (newi2pat && reg_set_p (i1dest, newi2pat))
4566 : 1 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4567 : : NULL_RTX, NULL_RTX);
4568 : : else
4569 : 102 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4570 : : NULL_RTX, NULL_RTX, NULL_RTX);
4571 : : }
4572 : :
4573 : 3708143 : if (i0dest_in_i0src)
4574 : : {
4575 : 18 : rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4576 : 18 : if (newi2pat && reg_set_p (i0dest, newi2pat))
4577 : 0 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4578 : : NULL_RTX, NULL_RTX);
4579 : : else
4580 : 36 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4581 : : NULL_RTX, NULL_RTX, NULL_RTX);
4582 : : }
4583 : :
4584 : 3708143 : distribute_links (i3links);
4585 : 3708143 : distribute_links (i2links);
4586 : 3708143 : distribute_links (i1links);
4587 : 3708143 : distribute_links (i0links);
4588 : :
4589 : 3708143 : if (REG_P (i2dest))
4590 : : {
4591 : 3708143 : struct insn_link *link;
4592 : 3708143 : rtx_insn *i2_insn = 0;
4593 : 3708143 : rtx i2_val = 0, set;
4594 : :
4595 : : /* The insn that used to set this register doesn't exist, and
4596 : : this life of the register may not exist either. See if one of
4597 : : I3's links points to an insn that sets I2DEST. If it does,
4598 : : that is now the last known value for I2DEST. If we don't update
4599 : : this and I2 set the register to a value that depended on its old
4600 : : contents, we will get confused. If this insn is used, thing
4601 : : will be set correctly in combine_instructions. */
4602 : 6883913 : FOR_EACH_LOG_LINK (link, i3)
4603 : 3175770 : if ((set = single_set (link->insn)) != 0
4604 : 3175770 : && rtx_equal_p (i2dest, SET_DEST (set)))
4605 : 42862 : i2_insn = link->insn, i2_val = SET_SRC (set);
4606 : :
4607 : 3708143 : record_value_for_reg (i2dest, i2_insn, i2_val);
4608 : :
4609 : : /* If the reg formerly set in I2 died only once and that was in I3,
4610 : : zero its use count so it won't make `reload' do any work. */
4611 : 3708143 : if (! added_sets_2
4612 : 3626285 : && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4613 : 3591045 : && ! i2dest_in_i2src
4614 : 7240565 : && REGNO (i2dest) < reg_n_sets_max)
4615 : 3532422 : INC_REG_N_SETS (REGNO (i2dest), -1);
4616 : : }
4617 : :
4618 : 3708143 : if (i1 && REG_P (i1dest))
4619 : : {
4620 : 84222 : struct insn_link *link;
4621 : 84222 : rtx_insn *i1_insn = 0;
4622 : 84222 : rtx i1_val = 0, set;
4623 : :
4624 : 147590 : FOR_EACH_LOG_LINK (link, i3)
4625 : 63368 : if ((set = single_set (link->insn)) != 0
4626 : 63368 : && rtx_equal_p (i1dest, SET_DEST (set)))
4627 : 177 : i1_insn = link->insn, i1_val = SET_SRC (set);
4628 : :
4629 : 84222 : record_value_for_reg (i1dest, i1_insn, i1_val);
4630 : :
4631 : 84222 : if (! added_sets_1
4632 : : && ! i1dest_in_i1src
4633 : 84222 : && REGNO (i1dest) < reg_n_sets_max)
4634 : 77261 : INC_REG_N_SETS (REGNO (i1dest), -1);
4635 : : }
4636 : :
4637 : 3708143 : if (i0 && REG_P (i0dest))
4638 : : {
4639 : 4684 : struct insn_link *link;
4640 : 4684 : rtx_insn *i0_insn = 0;
4641 : 4684 : rtx i0_val = 0, set;
4642 : :
4643 : 6559 : FOR_EACH_LOG_LINK (link, i3)
4644 : 1875 : if ((set = single_set (link->insn)) != 0
4645 : 1875 : && rtx_equal_p (i0dest, SET_DEST (set)))
4646 : 0 : i0_insn = link->insn, i0_val = SET_SRC (set);
4647 : :
4648 : 4684 : record_value_for_reg (i0dest, i0_insn, i0_val);
4649 : :
4650 : 4684 : if (! added_sets_0
4651 : : && ! i0dest_in_i0src
4652 : 4684 : && REGNO (i0dest) < reg_n_sets_max)
4653 : 4623 : INC_REG_N_SETS (REGNO (i0dest), -1);
4654 : : }
4655 : :
4656 : : /* Update reg_stat[].nonzero_bits et al for any changes that may have
4657 : : been made to this insn. The order is important, because newi2pat
4658 : : can affect nonzero_bits of newpat. */
4659 : 3708143 : if (newi2pat)
4660 : 64950 : note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4661 : 3708143 : note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4662 : : }
4663 : :
4664 : 3708143 : if (undobuf.other_insn != NULL_RTX)
4665 : : {
4666 : 194352 : if (dump_file)
4667 : : {
4668 : 12 : fprintf (dump_file, "modifying other_insn ");
4669 : 12 : dump_insn_slim (dump_file, undobuf.other_insn);
4670 : : }
4671 : 194352 : df_insn_rescan (undobuf.other_insn);
4672 : : }
4673 : :
4674 : 3708143 : if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4675 : : {
4676 : 0 : if (dump_file)
4677 : : {
4678 : 0 : fprintf (dump_file, "modifying insn i0 ");
4679 : 0 : dump_insn_slim (dump_file, i0);
4680 : : }
4681 : 0 : df_insn_rescan (i0);
4682 : : }
4683 : :
4684 : 3708143 : if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4685 : : {
4686 : 0 : if (dump_file)
4687 : : {
4688 : 0 : fprintf (dump_file, "modifying insn i1 ");
4689 : 0 : dump_insn_slim (dump_file, i1);
4690 : : }
4691 : 0 : df_insn_rescan (i1);
4692 : : }
4693 : :
4694 : 3708143 : if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4695 : : {
4696 : 64950 : if (dump_file)
4697 : : {
4698 : 14 : fprintf (dump_file, "modifying insn i2 ");
4699 : 14 : dump_insn_slim (dump_file, i2);
4700 : : }
4701 : 64950 : df_insn_rescan (i2);
4702 : : }
4703 : :
4704 : 3708143 : if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4705 : : {
4706 : 3708143 : if (dump_file)
4707 : : {
4708 : 239 : fprintf (dump_file, "modifying insn i3 ");
4709 : 239 : dump_insn_slim (dump_file, i3);
4710 : : }
4711 : 3708143 : df_insn_rescan (i3);
4712 : : }
4713 : :
4714 : : /* Set new_direct_jump_p if a new return or simple jump instruction
4715 : : has been created. Adjust the CFG accordingly. */
4716 : 3708143 : if (returnjump_p (i3) || any_uncondjump_p (i3))
4717 : : {
4718 : 256 : *new_direct_jump_p = 1;
4719 : 256 : mark_jump_label (PATTERN (i3), i3, 0);
4720 : 256 : update_cfg_for_uncondjump (i3);
4721 : : }
4722 : :
4723 : 3708143 : if (undobuf.other_insn != NULL_RTX
4724 : 3708143 : && (returnjump_p (undobuf.other_insn)
4725 : 194352 : || any_uncondjump_p (undobuf.other_insn)))
4726 : : {
4727 : 1933 : *new_direct_jump_p = 1;
4728 : 1933 : update_cfg_for_uncondjump (undobuf.other_insn);
4729 : : }
4730 : :
4731 : 3708143 : if (GET_CODE (PATTERN (i3)) == TRAP_IF
4732 : 3708143 : && XEXP (PATTERN (i3), 0) == const1_rtx)
4733 : : {
4734 : 0 : basic_block bb = BLOCK_FOR_INSN (i3);
4735 : 0 : gcc_assert (bb);
4736 : 0 : remove_edge (split_block (bb, i3));
4737 : 0 : emit_barrier_after_bb (bb);
4738 : 0 : *new_direct_jump_p = 1;
4739 : : }
4740 : :
4741 : 3708143 : if (undobuf.other_insn
4742 : 194352 : && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4743 : 3708143 : && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4744 : : {
4745 : 0 : basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4746 : 0 : gcc_assert (bb);
4747 : 0 : remove_edge (split_block (bb, undobuf.other_insn));
4748 : 0 : emit_barrier_after_bb (bb);
4749 : 0 : *new_direct_jump_p = 1;
4750 : : }
4751 : :
4752 : : /* A noop might also need cleaning up of CFG, if it comes from the
4753 : : simplification of a jump. */
4754 : 3708143 : if (JUMP_P (i3)
4755 : 40032 : && GET_CODE (newpat) == SET
4756 : 28549 : && SET_SRC (newpat) == pc_rtx
4757 : 421 : && SET_DEST (newpat) == pc_rtx)
4758 : : {
4759 : 421 : *new_direct_jump_p = 1;
4760 : 421 : update_cfg_for_uncondjump (i3);
4761 : : }
4762 : :
4763 : 3708143 : if (undobuf.other_insn != NULL_RTX
4764 : 194352 : && JUMP_P (undobuf.other_insn)
4765 : 190175 : && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4766 : 190175 : && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4767 : 3709879 : && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4768 : : {
4769 : 1736 : *new_direct_jump_p = 1;
4770 : 1736 : update_cfg_for_uncondjump (undobuf.other_insn);
4771 : : }
4772 : :
4773 : 3708143 : combine_successes++;
4774 : 3708143 : undo_commit ();
4775 : :
4776 : 3708143 : rtx_insn *ret = newi2pat ? i2 : i3;
4777 : 3708143 : if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4778 : : ret = added_links_insn;
4779 : 3708143 : if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4780 : : ret = added_notes_insn;
4781 : :
4782 : : return ret;
4783 : : }
4784 : :
4785 : : /* Get a marker for undoing to the current state. */
4786 : :
4787 : : static void *
4788 : 35096583 : get_undo_marker (void)
4789 : : {
4790 : 35096583 : return undobuf.undos;
4791 : : }
4792 : :
4793 : : /* Undo the modifications up to the marker. */
4794 : :
4795 : : static void
4796 : 41978310 : undo_to_marker (void *marker)
4797 : : {
4798 : 41978310 : struct undo *undo, *next;
4799 : :
4800 : 130509431 : for (undo = undobuf.undos; undo != marker; undo = next)
4801 : : {
4802 : 88531121 : gcc_assert (undo);
4803 : :
4804 : 88531121 : next = undo->next;
4805 : 88531121 : switch (undo->kind)
4806 : : {
4807 : 81946321 : case UNDO_RTX:
4808 : 81946321 : *undo->where.r = undo->old_contents.r;
4809 : 81946321 : break;
4810 : 5967644 : case UNDO_INT:
4811 : 5967644 : *undo->where.i = undo->old_contents.i;
4812 : 5967644 : break;
4813 : 555915 : case UNDO_MODE:
4814 : 555915 : adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4815 : : undo->old_contents.m);
4816 : 555915 : break;
4817 : 61241 : case UNDO_LINKS:
4818 : 61241 : *undo->where.l = undo->old_contents.l;
4819 : 61241 : break;
4820 : 0 : default:
4821 : 0 : gcc_unreachable ();
4822 : : }
4823 : :
4824 : 88531121 : undo->next = undobuf.frees;
4825 : 88531121 : undobuf.frees = undo;
4826 : : }
4827 : :
4828 : 41978310 : undobuf.undos = (struct undo *) marker;
4829 : 41978310 : }
4830 : :
4831 : : /* Undo all the modifications recorded in undobuf. */
4832 : :
4833 : : static void
4834 : 40931197 : undo_all (void)
4835 : : {
4836 : 40931197 : undo_to_marker (0);
4837 : 0 : }
4838 : :
4839 : : /* We've committed to accepting the changes we made. Move all
4840 : : of the undos to the free list. */
4841 : :
4842 : : static void
4843 : 3708143 : undo_commit (void)
4844 : : {
4845 : 3708143 : struct undo *undo, *next;
4846 : :
4847 : 10894790 : for (undo = undobuf.undos; undo; undo = next)
4848 : : {
4849 : 7186647 : next = undo->next;
4850 : 7186647 : undo->next = undobuf.frees;
4851 : 7186647 : undobuf.frees = undo;
4852 : : }
4853 : 3708143 : undobuf.undos = 0;
4854 : 3708143 : }
4855 : :
4856 : : /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4857 : : where we have an arithmetic expression and return that point. LOC will
4858 : : be inside INSN.
4859 : :
4860 : : try_combine will call this function to see if an insn can be split into
4861 : : two insns. */
4862 : :
4863 : : static rtx *
4864 : 28593859 : find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4865 : : {
4866 : 28593859 : rtx x = *loc;
4867 : 28593859 : enum rtx_code code = GET_CODE (x);
4868 : 28593859 : rtx *split;
4869 : 28593859 : unsigned HOST_WIDE_INT len = 0;
4870 : 28593859 : HOST_WIDE_INT pos = 0;
4871 : 28593859 : bool unsignedp = false;
4872 : 28593859 : rtx inner = NULL_RTX;
4873 : 28593859 : scalar_int_mode mode, inner_mode;
4874 : :
4875 : : /* First special-case some codes. */
4876 : 28593859 : switch (code)
4877 : : {
4878 : 961816 : case SUBREG:
4879 : : #ifdef INSN_SCHEDULING
4880 : : /* If we are making a paradoxical SUBREG invalid, it becomes a split
4881 : : point. */
4882 : 961816 : if (MEM_P (SUBREG_REG (x)))
4883 : : return loc;
4884 : : #endif
4885 : 950679 : return find_split_point (&SUBREG_REG (x), insn, false);
4886 : :
4887 : 1461186 : case MEM:
4888 : : /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4889 : : using LO_SUM and HIGH. */
4890 : 1461186 : if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4891 : : || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4892 : : {
4893 : : machine_mode address_mode = get_address_mode (x);
4894 : :
4895 : : SUBST (XEXP (x, 0),
4896 : : gen_rtx_LO_SUM (address_mode,
4897 : : gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4898 : : XEXP (x, 0)));
4899 : : return &XEXP (XEXP (x, 0), 0);
4900 : : }
4901 : :
4902 : : /* If we have a PLUS whose second operand is a constant and the
4903 : : address is not valid, perhaps we can split it up using
4904 : : the machine-specific way to split large constants. We use
4905 : : the first pseudo-reg (one of the virtual regs) as a placeholder;
4906 : : it will not remain in the result. */
4907 : 1461186 : if (GET_CODE (XEXP (x, 0)) == PLUS
4908 : 916656 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4909 : 3032532 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4910 : 654690 : MEM_ADDR_SPACE (x)))
4911 : : {
4912 : 112951 : rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4913 : 112951 : rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4914 : : subst_insn);
4915 : :
4916 : : /* This should have produced two insns, each of which sets our
4917 : : placeholder. If the source of the second is a valid address,
4918 : : we can put both sources together and make a split point
4919 : : in the middle. */
4920 : :
4921 : 112951 : if (seq
4922 : 54 : && NEXT_INSN (seq) != NULL_RTX
4923 : 0 : && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4924 : 0 : && NONJUMP_INSN_P (seq)
4925 : 0 : && GET_CODE (PATTERN (seq)) == SET
4926 : 0 : && SET_DEST (PATTERN (seq)) == reg
4927 : 0 : && ! reg_mentioned_p (reg,
4928 : 0 : SET_SRC (PATTERN (seq)))
4929 : 0 : && NONJUMP_INSN_P (NEXT_INSN (seq))
4930 : 0 : && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4931 : 0 : && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4932 : 112951 : && memory_address_addr_space_p
4933 : 112951 : (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4934 : 0 : MEM_ADDR_SPACE (x)))
4935 : : {
4936 : 0 : rtx src1 = SET_SRC (PATTERN (seq));
4937 : 0 : rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4938 : :
4939 : : /* Replace the placeholder in SRC2 with SRC1. If we can
4940 : : find where in SRC2 it was placed, that can become our
4941 : : split point and we can replace this address with SRC2.
4942 : : Just try two obvious places. */
4943 : :
4944 : 0 : src2 = replace_rtx (src2, reg, src1);
4945 : 0 : split = 0;
4946 : 0 : if (XEXP (src2, 0) == src1)
4947 : 0 : split = &XEXP (src2, 0);
4948 : 0 : else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4949 : 0 : && XEXP (XEXP (src2, 0), 0) == src1)
4950 : 0 : split = &XEXP (XEXP (src2, 0), 0);
4951 : :
4952 : 0 : if (split)
4953 : : {
4954 : 0 : SUBST (XEXP (x, 0), src2);
4955 : 0 : return split;
4956 : : }
4957 : : }
4958 : :
4959 : : /* If that didn't work and we have a nested plus, like:
4960 : : ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4961 : : is valid address, try to split (REG1 * CONST1). */
4962 : 112951 : if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4963 : 80467 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4964 : 66307 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4965 : 66305 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4966 : 10 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4967 : : 0), 0)))))
4968 : : {
4969 : 66305 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
4970 : 66305 : XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
4971 : 132610 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4972 : 66305 : MEM_ADDR_SPACE (x)))
4973 : : {
4974 : 56110 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4975 : 56110 : return &XEXP (XEXP (XEXP (x, 0), 0), 0);
4976 : : }
4977 : 10195 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4978 : 10195 : }
4979 : 46646 : else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4980 : 14162 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4981 : 14160 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4982 : 592 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
4983 : 592 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4984 : : 0), 1)))))
4985 : : {
4986 : 0 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
4987 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
4988 : 0 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4989 : 0 : MEM_ADDR_SPACE (x)))
4990 : : {
4991 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
4992 : 0 : return &XEXP (XEXP (XEXP (x, 0), 0), 1);
4993 : : }
4994 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
4995 : : }
4996 : :
4997 : : /* If that didn't work, perhaps the first operand is complex and
4998 : : needs to be computed separately, so make a split point there.
4999 : : This will occur on machines that just support REG + CONST
5000 : : and have a constant moved through some previous computation. */
5001 : 56841 : if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5002 : 33038 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5003 : 0 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5004 : 33038 : return &XEXP (XEXP (x, 0), 0);
5005 : : }
5006 : :
5007 : : /* If we have a PLUS whose first operand is complex, try computing it
5008 : : separately by making a split there. */
5009 : 1372038 : if (GET_CODE (XEXP (x, 0)) == PLUS
5010 : 2354597 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5011 : 827508 : MEM_ADDR_SPACE (x))
5012 : 155051 : && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5013 : 1481352 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5014 : 946 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5015 : 109310 : return &XEXP (XEXP (x, 0), 0);
5016 : : break;
5017 : :
5018 : 4253352 : case SET:
5019 : : /* See if we can split SET_SRC as it stands. */
5020 : 4253352 : split = find_split_point (&SET_SRC (x), insn, true);
5021 : 4253352 : if (split && split != &SET_SRC (x))
5022 : : return split;
5023 : :
5024 : : /* See if we can split SET_DEST as it stands. */
5025 : 448184 : split = find_split_point (&SET_DEST (x), insn, false);
5026 : 448184 : if (split && split != &SET_DEST (x))
5027 : : return split;
5028 : :
5029 : : /* See if this is a bitfield assignment with everything constant. If
5030 : : so, this is an IOR of an AND, so split it into that. */
5031 : 414505 : if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5032 : 4172 : && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5033 : : &inner_mode)
5034 : 4172 : && HWI_COMPUTABLE_MODE_P (inner_mode)
5035 : 4172 : && CONST_INT_P (XEXP (SET_DEST (x), 1))
5036 : 4172 : && CONST_INT_P (XEXP (SET_DEST (x), 2))
5037 : 4035 : && CONST_INT_P (SET_SRC (x))
5038 : 477 : && ((INTVAL (XEXP (SET_DEST (x), 1))
5039 : 477 : + INTVAL (XEXP (SET_DEST (x), 2)))
5040 : 477 : <= GET_MODE_PRECISION (inner_mode))
5041 : 414982 : && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5042 : : {
5043 : 460 : HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5044 : 460 : unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5045 : 460 : rtx dest = XEXP (SET_DEST (x), 0);
5046 : 460 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5047 : 460 : unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5048 : 460 : rtx or_mask;
5049 : :
5050 : 460 : if (BITS_BIG_ENDIAN)
5051 : : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5052 : :
5053 : 460 : or_mask = gen_int_mode (src << pos, inner_mode);
5054 : 460 : if (src == mask)
5055 : 0 : SUBST (SET_SRC (x),
5056 : : simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5057 : : else
5058 : : {
5059 : 460 : rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5060 : 460 : SUBST (SET_SRC (x),
5061 : : simplify_gen_binary (IOR, inner_mode,
5062 : : simplify_gen_binary (AND, inner_mode,
5063 : : dest, negmask),
5064 : : or_mask));
5065 : : }
5066 : :
5067 : 460 : SUBST (SET_DEST (x), dest);
5068 : :
5069 : 460 : split = find_split_point (&SET_SRC (x), insn, true);
5070 : 460 : if (split && split != &SET_SRC (x))
5071 : : return split;
5072 : : }
5073 : :
5074 : : /* Otherwise, see if this is an operation that we can split into two.
5075 : : If so, try to split that. */
5076 : 414045 : code = GET_CODE (SET_SRC (x));
5077 : :
5078 : 414045 : switch (code)
5079 : : {
5080 : 14987 : case AND:
5081 : : /* If we are AND'ing with a large constant that is only a single
5082 : : bit and the result is only being used in a context where we
5083 : : need to know if it is zero or nonzero, replace it with a bit
5084 : : extraction. This will avoid the large constant, which might
5085 : : have taken more than one insn to make. If the constant were
5086 : : not a valid argument to the AND but took only one insn to make,
5087 : : this is no worse, but if it took more than one insn, it will
5088 : : be better. */
5089 : :
5090 : 14987 : if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5091 : 10945 : && REG_P (XEXP (SET_SRC (x), 0))
5092 : 566 : && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5093 : 1 : && REG_P (SET_DEST (x))
5094 : 0 : && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5095 : 0 : && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5096 : 0 : && XEXP (*split, 0) == SET_DEST (x)
5097 : 14987 : && XEXP (*split, 1) == const0_rtx)
5098 : : {
5099 : 0 : rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5100 : 0 : XEXP (SET_SRC (x), 0),
5101 : : pos, NULL_RTX, 1,
5102 : : true, false, false);
5103 : 0 : if (extraction != 0)
5104 : : {
5105 : 0 : SUBST (SET_SRC (x), extraction);
5106 : 0 : return find_split_point (loc, insn, false);
5107 : : }
5108 : : }
5109 : : break;
5110 : :
5111 : : case NE:
5112 : : /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5113 : : is known to be on, this can be converted into a NEG of a shift. */
5114 : : if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5115 : : && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5116 : : && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5117 : : GET_MODE (XEXP (SET_SRC (x),
5118 : : 0))))) >= 1))
5119 : : {
5120 : : machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5121 : : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5122 : : SUBST (SET_SRC (x),
5123 : : gen_rtx_NEG (mode,
5124 : : gen_rtx_LSHIFTRT (mode,
5125 : : XEXP (SET_SRC (x), 0),
5126 : : pos_rtx)));
5127 : :
5128 : : split = find_split_point (&SET_SRC (x), insn, true);
5129 : : if (split && split != &SET_SRC (x))
5130 : : return split;
5131 : : }
5132 : : break;
5133 : :
5134 : 741 : case SIGN_EXTEND:
5135 : 741 : inner = XEXP (SET_SRC (x), 0);
5136 : :
5137 : : /* We can't optimize if either mode is a partial integer
5138 : : mode as we don't know how many bits are significant
5139 : : in those modes. */
5140 : 741 : if (!is_int_mode (GET_MODE (inner), &inner_mode)
5141 : 737 : || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5142 : : break;
5143 : :
5144 : 737 : pos = 0;
5145 : 737 : len = GET_MODE_PRECISION (inner_mode);
5146 : 737 : unsignedp = false;
5147 : 737 : break;
5148 : :
5149 : 10656 : case SIGN_EXTRACT:
5150 : 10656 : case ZERO_EXTRACT:
5151 : 10656 : if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5152 : : &inner_mode)
5153 : 10316 : && CONST_INT_P (XEXP (SET_SRC (x), 1))
5154 : 10316 : && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5155 : : {
5156 : 9585 : inner = XEXP (SET_SRC (x), 0);
5157 : 9585 : len = INTVAL (XEXP (SET_SRC (x), 1));
5158 : 9585 : pos = INTVAL (XEXP (SET_SRC (x), 2));
5159 : :
5160 : 9585 : if (BITS_BIG_ENDIAN)
5161 : : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5162 : 9585 : unsignedp = (code == ZERO_EXTRACT);
5163 : : }
5164 : : break;
5165 : :
5166 : : default:
5167 : : break;
5168 : : }
5169 : :
5170 : 414045 : if (len
5171 : 10322 : && known_subrange_p (pos, len,
5172 : 10322 : 0, GET_MODE_PRECISION (GET_MODE (inner)))
5173 : 424367 : && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5174 : : {
5175 : : /* For unsigned, we have a choice of a shift followed by an
5176 : : AND or two shifts. Use two shifts for field sizes where the
5177 : : constant might be too large. We assume here that we can
5178 : : always at least get 8-bit constants in an AND insn, which is
5179 : : true for every current RISC. */
5180 : :
5181 : 10322 : if (unsignedp && len <= 8)
5182 : : {
5183 : 4649 : unsigned HOST_WIDE_INT mask
5184 : 4649 : = (HOST_WIDE_INT_1U << len) - 1;
5185 : 4649 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5186 : 4649 : SUBST (SET_SRC (x),
5187 : : gen_rtx_AND (mode,
5188 : : gen_rtx_LSHIFTRT
5189 : : (mode, gen_lowpart (mode, inner), pos_rtx),
5190 : : gen_int_mode (mask, mode)));
5191 : :
5192 : 4649 : split = find_split_point (&SET_SRC (x), insn, true);
5193 : 4649 : if (split && split != &SET_SRC (x))
5194 : 28593859 : return split;
5195 : : }
5196 : : else
5197 : : {
5198 : 5673 : int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5199 : 5673 : int right_bits = GET_MODE_PRECISION (mode) - len;
5200 : 11346 : SUBST (SET_SRC (x),
5201 : : gen_rtx_fmt_ee
5202 : : (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5203 : : gen_rtx_ASHIFT (mode,
5204 : : gen_lowpart (mode, inner),
5205 : : gen_int_shift_amount (mode, left_bits)),
5206 : : gen_int_shift_amount (mode, right_bits)));
5207 : :
5208 : 5673 : split = find_split_point (&SET_SRC (x), insn, true);
5209 : 5673 : if (split && split != &SET_SRC (x))
5210 : 28593859 : return split;
5211 : : }
5212 : : }
5213 : :
5214 : : /* See if this is a simple operation with a constant as the second
5215 : : operand. It might be that this constant is out of range and hence
5216 : : could be used as a split point. */
5217 : 403723 : if (BINARY_P (SET_SRC (x))
5218 : 199806 : && CONSTANT_P (XEXP (SET_SRC (x), 1))
5219 : 107067 : && (OBJECT_P (XEXP (SET_SRC (x), 0))
5220 : 20895 : || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5221 : 11695 : && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5222 : 88449 : return &XEXP (SET_SRC (x), 1);
5223 : :
5224 : : /* Finally, see if this is a simple operation with its first operand
5225 : : not in a register. The operation might require this operand in a
5226 : : register, so return it as a split point. We can always do this
5227 : : because if the first operand were another operation, we would have
5228 : : already found it as a split point. */
5229 : 315274 : if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5230 : 315274 : && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5231 : 111384 : return &XEXP (SET_SRC (x), 0);
5232 : :
5233 : : return 0;
5234 : :
5235 : 1130905 : case AND:
5236 : 1130905 : case IOR:
5237 : : /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5238 : : it is better to write this as (not (ior A B)) so we can split it.
5239 : : Similarly for IOR. */
5240 : 1130905 : if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5241 : : {
5242 : 1202 : SUBST (*loc,
5243 : : gen_rtx_NOT (GET_MODE (x),
5244 : : gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5245 : : GET_MODE (x),
5246 : : XEXP (XEXP (x, 0), 0),
5247 : : XEXP (XEXP (x, 1), 0))));
5248 : 601 : return find_split_point (loc, insn, set_src);
5249 : : }
5250 : :
5251 : : /* Many RISC machines have a large set of logical insns. If the
5252 : : second operand is a NOT, put it first so we will try to split the
5253 : : other operand first. */
5254 : 1130304 : if (GET_CODE (XEXP (x, 1)) == NOT)
5255 : : {
5256 : 4862 : rtx tem = XEXP (x, 0);
5257 : 4862 : SUBST (XEXP (x, 0), XEXP (x, 1));
5258 : 4862 : SUBST (XEXP (x, 1), tem);
5259 : : }
5260 : : break;
5261 : :
5262 : 2899449 : case PLUS:
5263 : 2899449 : case MINUS:
5264 : : /* Canonicalization can produce (minus A (mult B C)), where C is a
5265 : : constant. It may be better to try splitting (plus (mult B -C) A)
5266 : : instead if this isn't a multiply by a power of two. */
5267 : 190101 : if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5268 : 23394 : && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5269 : 2907215 : && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5270 : : {
5271 : 7766 : machine_mode mode = GET_MODE (x);
5272 : 7766 : unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5273 : 7766 : HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5274 : 7766 : SUBST (*loc, gen_rtx_PLUS (mode,
5275 : : gen_rtx_MULT (mode,
5276 : : XEXP (XEXP (x, 1), 0),
5277 : : gen_int_mode (other_int,
5278 : : mode)),
5279 : : XEXP (x, 0)));
5280 : 7766 : return find_split_point (loc, insn, set_src);
5281 : : }
5282 : :
5283 : : /* Split at a multiply-accumulate instruction. However if this is
5284 : : the SET_SRC, we likely do not have such an instruction and it's
5285 : : worthless to try this split. */
5286 : 2891683 : if (!set_src
5287 : 1691815 : && (GET_CODE (XEXP (x, 0)) == MULT
5288 : 1581899 : || (GET_CODE (XEXP (x, 0)) == ASHIFT
5289 : 110943 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5290 : : return loc;
5291 : :
5292 : : default:
5293 : : break;
5294 : : }
5295 : :
5296 : : /* Otherwise, select our actions depending on our rtx class. */
5297 : 22953193 : switch (GET_RTX_CLASS (code))
5298 : : {
5299 : 1195805 : case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5300 : 1195805 : case RTX_TERNARY:
5301 : 1195805 : split = find_split_point (&XEXP (x, 2), insn, false);
5302 : 1195805 : if (split)
5303 : : return split;
5304 : : /* fall through */
5305 : 9088886 : case RTX_BIN_ARITH:
5306 : 9088886 : case RTX_COMM_ARITH:
5307 : 9088886 : case RTX_COMPARE:
5308 : 9088886 : case RTX_COMM_COMPARE:
5309 : 9088886 : split = find_split_point (&XEXP (x, 1), insn, false);
5310 : 9088886 : if (split)
5311 : : return split;
5312 : : /* fall through */
5313 : 8708329 : case RTX_UNARY:
5314 : : /* Some machines have (and (shift ...) ...) insns. If X is not
5315 : : an AND, but XEXP (X, 0) is, use it as our split point. */
5316 : 8708329 : if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5317 : 323877 : return &XEXP (x, 0);
5318 : :
5319 : 8384452 : split = find_split_point (&XEXP (x, 0), insn, false);
5320 : 8384452 : if (split)
5321 : : return split;
5322 : : return loc;
5323 : :
5324 : : default:
5325 : : /* Otherwise, we don't have a split point. */
5326 : : return 0;
5327 : : }
5328 : : }
5329 : :
5330 : : /* Throughout X, replace FROM with TO, and return the result.
5331 : : The result is TO if X is FROM;
5332 : : otherwise the result is X, but its contents may have been modified.
5333 : : If they were modified, a record was made in undobuf so that
5334 : : undo_all will (among other things) return X to its original state.
5335 : :
5336 : : If the number of changes necessary is too much to record to undo,
5337 : : the excess changes are not made, so the result is invalid.
5338 : : The changes already made can still be undone.
5339 : : undobuf.num_undo is incremented for such changes, so by testing that
5340 : : the caller can tell whether the result is valid.
5341 : :
5342 : : `n_occurrences' is incremented each time FROM is replaced.
5343 : :
5344 : : IN_DEST is true if we are processing the SET_DEST of a SET.
5345 : :
5346 : : IN_COND is true if we are at the top level of a condition.
5347 : :
5348 : : UNIQUE_COPY is true if each substitution must be unique. We do this
5349 : : by copying if `n_occurrences' is nonzero. */
5350 : :
5351 : : static rtx
5352 : 378276758 : subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5353 : : {
5354 : 378276758 : enum rtx_code code = GET_CODE (x);
5355 : 378276758 : machine_mode op0_mode = VOIDmode;
5356 : 378276758 : const char *fmt;
5357 : 378276758 : int len, i;
5358 : 378276758 : rtx new_rtx;
5359 : :
5360 : : /* Two expressions are equal if they are identical copies of a shared
5361 : : RTX or if they are both registers with the same register number
5362 : : and mode. */
5363 : :
5364 : : #define COMBINE_RTX_EQUAL_P(X,Y) \
5365 : : ((X) == (Y) \
5366 : : || (REG_P (X) && REG_P (Y) \
5367 : : && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5368 : :
5369 : : /* Do not substitute into clobbers of regs -- this will never result in
5370 : : valid RTL. */
5371 : 378276758 : if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5372 : : return x;
5373 : :
5374 : 368758218 : if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5375 : : {
5376 : 0 : n_occurrences++;
5377 : 0 : return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5378 : : }
5379 : :
5380 : : /* If X and FROM are the same register but different modes, they
5381 : : will not have been seen as equal above. However, the log links code
5382 : : will make a LOG_LINKS entry for that case. If we do nothing, we
5383 : : will try to rerecognize our original insn and, when it succeeds,
5384 : : we will delete the feeding insn, which is incorrect.
5385 : :
5386 : : So force this insn not to match in this (rare) case. */
5387 : 81153299 : if (! in_dest && code == REG && REG_P (from)
5388 : 397975612 : && reg_overlap_mentioned_p (x, from))
5389 : 4076 : return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5390 : :
5391 : : /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5392 : : of which may contain things that can be combined. */
5393 : 368754142 : if (code != MEM && code != LO_SUM && OBJECT_P (x))
5394 : : return x;
5395 : :
5396 : : /* It is possible to have a subexpression appear twice in the insn.
5397 : : Suppose that FROM is a register that appears within TO.
5398 : : Then, after that subexpression has been scanned once by `subst',
5399 : : the second time it is scanned, TO may be found. If we were
5400 : : to scan TO here, we would find FROM within it and create a
5401 : : self-referent rtl structure which is completely wrong. */
5402 : 197934782 : if (COMBINE_RTX_EQUAL_P (x, to))
5403 : : return to;
5404 : :
5405 : : /* Parallel asm_operands need special attention because all of the
5406 : : inputs are shared across the arms. Furthermore, unsharing the
5407 : : rtl results in recognition failures. Failure to handle this case
5408 : : specially can result in circular rtl.
5409 : :
5410 : : Solve this by doing a normal pass across the first entry of the
5411 : : parallel, and only processing the SET_DESTs of the subsequent
5412 : : entries. Ug. */
5413 : :
5414 : 197839205 : if (code == PARALLEL
5415 : 11812550 : && GET_CODE (XVECEXP (x, 0, 0)) == SET
5416 : 10157916 : && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5417 : : {
5418 : 18926 : new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5419 : :
5420 : : /* If this substitution failed, this whole thing fails. */
5421 : 18926 : if (GET_CODE (new_rtx) == CLOBBER
5422 : 0 : && XEXP (new_rtx, 0) == const0_rtx)
5423 : : return new_rtx;
5424 : :
5425 : 18926 : SUBST (XVECEXP (x, 0, 0), new_rtx);
5426 : :
5427 : 94809 : for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5428 : : {
5429 : 75883 : rtx dest = SET_DEST (XVECEXP (x, 0, i));
5430 : :
5431 : 75883 : if (!REG_P (dest) && GET_CODE (dest) != PC)
5432 : : {
5433 : 1997 : new_rtx = subst (dest, from, to, false, false, unique_copy);
5434 : :
5435 : : /* If this substitution failed, this whole thing fails. */
5436 : 1997 : if (GET_CODE (new_rtx) == CLOBBER
5437 : 0 : && XEXP (new_rtx, 0) == const0_rtx)
5438 : : return new_rtx;
5439 : :
5440 : 1997 : SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5441 : : }
5442 : : }
5443 : : }
5444 : : else
5445 : : {
5446 : 197820279 : len = GET_RTX_LENGTH (code);
5447 : 197820279 : fmt = GET_RTX_FORMAT (code);
5448 : :
5449 : : /* We don't need to process a SET_DEST that is a register or PC, so
5450 : : set up to skip this common case. All other cases where we want
5451 : : to suppress replacing something inside a SET_SRC are handled via
5452 : : the IN_DEST operand. */
5453 : 197820279 : if (code == SET
5454 : 44064908 : && (REG_P (SET_DEST (x))
5455 : 44064908 : || GET_CODE (SET_DEST (x)) == PC))
5456 : 197820279 : fmt = "ie";
5457 : :
5458 : : /* Trying to simplify the operands of a widening MULT is not likely
5459 : : to create RTL matching a machine insn. */
5460 : 197820279 : if (code == MULT
5461 : 4496786 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5462 : 4496786 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5463 : 287385 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5464 : 287385 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5465 : 203899 : && REG_P (XEXP (XEXP (x, 0), 0))
5466 : 90884 : && REG_P (XEXP (XEXP (x, 1), 0))
5467 : 73354 : && from == to)
5468 : : return x;
5469 : :
5470 : :
5471 : : /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5472 : : constant. */
5473 : 197779362 : if (fmt[0] == 'e')
5474 : 145578052 : op0_mode = GET_MODE (XEXP (x, 0));
5475 : :
5476 : 584964275 : for (i = 0; i < len; i++)
5477 : : {
5478 : 388206728 : if (fmt[i] == 'E')
5479 : : {
5480 : 13866781 : int j;
5481 : 44214090 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5482 : : {
5483 : 30507079 : if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5484 : : {
5485 : 1420 : new_rtx = (unique_copy && n_occurrences
5486 : 260719 : ? copy_rtx (to) : to);
5487 : 260694 : n_occurrences++;
5488 : : }
5489 : : else
5490 : : {
5491 : 30246385 : new_rtx = subst (XVECEXP (x, i, j), from, to,
5492 : : false, false, unique_copy);
5493 : :
5494 : : /* If this substitution failed, this whole thing
5495 : : fails. */
5496 : 30246385 : if (GET_CODE (new_rtx) == CLOBBER
5497 : 10012272 : && XEXP (new_rtx, 0) == const0_rtx)
5498 : : return new_rtx;
5499 : : }
5500 : :
5501 : 30347309 : SUBST (XVECEXP (x, i, j), new_rtx);
5502 : : }
5503 : : }
5504 : 374339947 : else if (fmt[i] == 'e')
5505 : : {
5506 : : /* If this is a register being set, ignore it. */
5507 : 305278984 : new_rtx = XEXP (x, i);
5508 : 305278984 : if (in_dest
5509 : 305278984 : && i == 0
5510 : 5765330 : && (((code == SUBREG || code == ZERO_EXTRACT)
5511 : 314909 : && REG_P (new_rtx))
5512 : 5452664 : || code == STRICT_LOW_PART))
5513 : : ;
5514 : :
5515 : 304955424 : else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5516 : : {
5517 : : /* In general, don't install a subreg involving two
5518 : : modes not tieable. It can worsen register
5519 : : allocation, and can even make invalid reload
5520 : : insns, since the reg inside may need to be copied
5521 : : from in the outside mode, and that may be invalid
5522 : : if it is an fp reg copied in integer mode.
5523 : :
5524 : : We allow an exception to this: It is valid if
5525 : : it is inside another SUBREG and the mode of that
5526 : : SUBREG and the mode of the inside of TO is
5527 : : tieable. */
5528 : :
5529 : 44115480 : if (GET_CODE (to) == SUBREG
5530 : 549372 : && !targetm.modes_tieable_p (GET_MODE (to),
5531 : 549372 : GET_MODE (SUBREG_REG (to)))
5532 : 44455905 : && ! (code == SUBREG
5533 : 25381 : && (targetm.modes_tieable_p
5534 : 25381 : (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5535 : 312956 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5536 : :
5537 : 43802524 : if (code == SUBREG
5538 : 2316462 : && REG_P (to)
5539 : 157382 : && REGNO (to) < FIRST_PSEUDO_REGISTER
5540 : 43802535 : && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5541 : 11 : SUBREG_BYTE (x),
5542 : 11 : GET_MODE (x)) < 0)
5543 : 6 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5544 : :
5545 : 43802518 : new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5546 : 43802518 : n_occurrences++;
5547 : : }
5548 : : else
5549 : : /* If we are in a SET_DEST, suppress most cases unless we
5550 : : have gone inside a MEM, in which case we want to
5551 : : simplify the address. We assume here that things that
5552 : : are actually part of the destination have their inner
5553 : : parts in the first expression. This is true for SUBREG,
5554 : : STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5555 : : things aside from REG and MEM that should appear in a
5556 : : SET_DEST. */
5557 : 260839944 : new_rtx = subst (XEXP (x, i), from, to,
5558 : : (((in_dest
5559 : 5160951 : && (code == SUBREG || code == STRICT_LOW_PART
5560 : 5160951 : || code == ZERO_EXTRACT))
5561 : 260832778 : || code == SET)
5562 : 45499191 : && i == 0),
5563 : 260839944 : code == IF_THEN_ELSE && i == 0,
5564 : : unique_copy);
5565 : :
5566 : : /* If we found that we will have to reject this combination,
5567 : : indicate that by returning the CLOBBER ourselves, rather than
5568 : : an expression containing it. This will speed things up as
5569 : : well as prevent accidents where two CLOBBERs are considered
5570 : : to be equal, thus producing an incorrect simplification. */
5571 : :
5572 : 304966022 : if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5573 : : return new_rtx;
5574 : :
5575 : 304417189 : if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5576 : : {
5577 : 30320 : machine_mode mode = GET_MODE (x);
5578 : :
5579 : 60640 : x = simplify_subreg (GET_MODE (x), new_rtx,
5580 : 30320 : GET_MODE (SUBREG_REG (x)),
5581 : 30320 : SUBREG_BYTE (x));
5582 : 30320 : if (! x)
5583 : 2 : x = gen_rtx_CLOBBER (mode, const0_rtx);
5584 : : }
5585 : 304386869 : else if (CONST_SCALAR_INT_P (new_rtx)
5586 : : && (GET_CODE (x) == ZERO_EXTEND
5587 : 55664572 : || GET_CODE (x) == SIGN_EXTEND
5588 : : || GET_CODE (x) == FLOAT
5589 : : || GET_CODE (x) == UNSIGNED_FLOAT))
5590 : : {
5591 : 142176 : x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5592 : : new_rtx,
5593 : 71088 : GET_MODE (XEXP (x, 0)));
5594 : 71088 : if (!x)
5595 : 250 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5596 : : }
5597 : : /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5598 : : etc. arguments, otherwise we can ICE before trying to recog
5599 : : it. See PR104446. */
5600 : 304315781 : else if (CONST_SCALAR_INT_P (new_rtx)
5601 : 55593484 : && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5602 : 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5603 : : else
5604 : 304315781 : SUBST (XEXP (x, i), new_rtx);
5605 : : }
5606 : : }
5607 : : }
5608 : :
5609 : : /* Check if we are loading something from the constant pool via float
5610 : : extension; in this case we would undo compress_float_constant
5611 : : optimization and degenerate constant load to an immediate value. */
5612 : 196776473 : if (GET_CODE (x) == FLOAT_EXTEND
5613 : 303585 : && MEM_P (XEXP (x, 0))
5614 : 196838806 : && MEM_READONLY_P (XEXP (x, 0)))
5615 : : {
5616 : 35617 : rtx tmp = avoid_constant_pool_reference (x);
5617 : 35617 : if (x != tmp)
5618 : : return x;
5619 : : }
5620 : :
5621 : : /* Try to simplify X. If the simplification changed the code, it is likely
5622 : : that further simplification will help, so loop, but limit the number
5623 : : of repetitions that will be performed. */
5624 : :
5625 : 204075467 : for (i = 0; i < 4; i++)
5626 : : {
5627 : : /* If X is sufficiently simple, don't bother trying to do anything
5628 : : with it. */
5629 : 204061387 : if (code != CONST_INT && code != REG && code != CLOBBER)
5630 : 203367466 : x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5631 : :
5632 : 204061387 : if (GET_CODE (x) == code)
5633 : : break;
5634 : :
5635 : 7334473 : code = GET_CODE (x);
5636 : :
5637 : : /* We no longer know the original mode of operand 0 since we
5638 : : have changed the form of X) */
5639 : 7334473 : op0_mode = VOIDmode;
5640 : : }
5641 : :
5642 : : return x;
5643 : : }
5644 : :
5645 : : /* If X is a commutative operation whose operands are not in the canonical
5646 : : order, use substitutions to swap them. */
5647 : :
5648 : : static void
5649 : 634558652 : maybe_swap_commutative_operands (rtx x)
5650 : : {
5651 : 634558652 : if (COMMUTATIVE_ARITH_P (x)
5652 : 634558652 : && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5653 : : {
5654 : 3290140 : rtx temp = XEXP (x, 0);
5655 : 3290140 : SUBST (XEXP (x, 0), XEXP (x, 1));
5656 : 3290140 : SUBST (XEXP (x, 1), temp);
5657 : : }
5658 : :
5659 : : /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5660 : : (vec_merge (fma op1 op2 op3) op1 mask). */
5661 : 634558652 : if (GET_CODE (x) == VEC_MERGE
5662 : 693669 : && GET_CODE (XEXP (x, 0)) == FMA)
5663 : : {
5664 : 26381 : rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5665 : 26381 : rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5666 : 26381 : rtx masked_op = XEXP (x, 1);
5667 : 26381 : if (rtx_equal_p (masked_op, fma_op2))
5668 : : {
5669 : 210 : if (GET_CODE (fma_op1) == NEG)
5670 : : {
5671 : : /* Keep the negate canonicalized to the first operand. */
5672 : 142 : fma_op1 = XEXP (fma_op1, 0);
5673 : 142 : SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5674 : 142 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5675 : : }
5676 : : else
5677 : : {
5678 : 68 : SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5679 : 68 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5680 : : }
5681 : : }
5682 : : }
5683 : :
5684 : 634558652 : unsigned n_elts = 0;
5685 : 634558652 : if (GET_CODE (x) == VEC_MERGE
5686 : 693669 : && CONST_INT_P (XEXP (x, 2))
5687 : 702200 : && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5688 : 634909752 : && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5689 : : /* Two operands have same precedence, then
5690 : : first bit of mask select first operand. */
5691 : 321753 : || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5692 : 64241 : && !(UINTVAL (XEXP (x, 2)) & 1))))
5693 : : {
5694 : 43120 : rtx temp = XEXP (x, 0);
5695 : 43120 : unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5696 : 43120 : unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5697 : 43120 : if (n_elts == HOST_BITS_PER_WIDE_INT)
5698 : : mask = -1;
5699 : : else
5700 : 43110 : mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5701 : 43120 : SUBST (XEXP (x, 0), XEXP (x, 1));
5702 : 43120 : SUBST (XEXP (x, 1), temp);
5703 : 43120 : SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5704 : : }
5705 : 634558652 : }
5706 : :
5707 : : /* Simplify X, a piece of RTL. We just operate on the expression at the
5708 : : outer level; call `subst' to simplify recursively. Return the new
5709 : : expression.
5710 : :
5711 : : OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5712 : : if we are inside a SET_DEST. IN_COND is true if we are at the top level
5713 : : of a condition. */
5714 : :
5715 : : static rtx
5716 : 203615350 : combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5717 : : {
5718 : 203615350 : enum rtx_code code = GET_CODE (x);
5719 : 203615350 : machine_mode mode = GET_MODE (x);
5720 : 203615350 : scalar_int_mode int_mode;
5721 : 203615350 : rtx temp;
5722 : 203615350 : int i;
5723 : :
5724 : : /* If this is a commutative operation, put a constant last and a complex
5725 : : expression first. We don't need to do this for comparisons here. */
5726 : 203615350 : maybe_swap_commutative_operands (x);
5727 : :
5728 : : /* Try to fold this expression in case we have constants that weren't
5729 : : present before. */
5730 : 203615350 : temp = 0;
5731 : 203615350 : switch (GET_RTX_CLASS (code))
5732 : : {
5733 : 6709048 : case RTX_UNARY:
5734 : 6709048 : if (op0_mode == VOIDmode)
5735 : 147277 : op0_mode = GET_MODE (XEXP (x, 0));
5736 : 6709048 : temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5737 : 6709048 : break;
5738 : 16074316 : case RTX_COMPARE:
5739 : 16074316 : case RTX_COMM_COMPARE:
5740 : 16074316 : {
5741 : 16074316 : machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5742 : 16074316 : if (cmp_mode == VOIDmode)
5743 : : {
5744 : 40298 : cmp_mode = GET_MODE (XEXP (x, 1));
5745 : 40298 : if (cmp_mode == VOIDmode)
5746 : 5154 : cmp_mode = op0_mode;
5747 : : }
5748 : 16074316 : temp = simplify_relational_operation (code, mode, cmp_mode,
5749 : : XEXP (x, 0), XEXP (x, 1));
5750 : : }
5751 : 16074316 : break;
5752 : 80359462 : case RTX_COMM_ARITH:
5753 : 80359462 : case RTX_BIN_ARITH:
5754 : 80359462 : temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5755 : 80359462 : break;
5756 : 12746672 : case RTX_BITFIELD_OPS:
5757 : 12746672 : case RTX_TERNARY:
5758 : 12746672 : temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5759 : : XEXP (x, 1), XEXP (x, 2));
5760 : 12746672 : break;
5761 : : default:
5762 : : break;
5763 : : }
5764 : :
5765 : 115889498 : if (temp)
5766 : : {
5767 : 15663654 : x = temp;
5768 : 15663654 : code = GET_CODE (temp);
5769 : 15663654 : op0_mode = VOIDmode;
5770 : 15663654 : mode = GET_MODE (temp);
5771 : : }
5772 : :
5773 : : /* If this is a simple operation applied to an IF_THEN_ELSE, try
5774 : : applying it to the arms of the IF_THEN_ELSE. This often simplifies
5775 : : things. Check for cases where both arms are testing the same
5776 : : condition.
5777 : :
5778 : : Don't do anything if all operands are very simple. */
5779 : :
5780 : 203615350 : if ((BINARY_P (x)
5781 : 96127376 : && ((!OBJECT_P (XEXP (x, 0))
5782 : 37117927 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5783 : 4565507 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5784 : 61617771 : || (!OBJECT_P (XEXP (x, 1))
5785 : 4293704 : && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5786 : 1527610 : && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5787 : 166093929 : || (UNARY_P (x)
5788 : 6605936 : && (!OBJECT_P (XEXP (x, 0))
5789 : 2854321 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5790 : 642541 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5791 : : {
5792 : 39803167 : rtx cond, true_rtx, false_rtx;
5793 : :
5794 : 39803167 : cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5795 : 39803167 : if (cond != 0
5796 : : /* If everything is a comparison, what we have is highly unlikely
5797 : : to be simpler, so don't use it. */
5798 : 3555743 : && ! (COMPARISON_P (x)
5799 : 973242 : && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5800 : : /* Similarly, if we end up with one of the expressions the same
5801 : : as the original, it is certainly not simpler. */
5802 : 3399924 : && ! rtx_equal_p (x, true_rtx)
5803 : 43203091 : && ! rtx_equal_p (x, false_rtx))
5804 : : {
5805 : 3399924 : rtx cop1 = const0_rtx;
5806 : 3399924 : enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5807 : :
5808 : 3399924 : if (cond_code == NE && COMPARISON_P (cond))
5809 : 614183 : return x;
5810 : :
5811 : : /* Simplify the alternative arms; this may collapse the true and
5812 : : false arms to store-flag values. Be careful to use copy_rtx
5813 : : here since true_rtx or false_rtx might share RTL with x as a
5814 : : result of the if_then_else_cond call above. */
5815 : 2785741 : true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5816 : : false, false, false);
5817 : 2785741 : false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5818 : : false, false, false);
5819 : :
5820 : : /* If true_rtx and false_rtx are not general_operands, an if_then_else
5821 : : is unlikely to be simpler. */
5822 : 2785741 : if (general_operand (true_rtx, VOIDmode)
5823 : 2785741 : && general_operand (false_rtx, VOIDmode))
5824 : : {
5825 : 1065079 : enum rtx_code reversed;
5826 : :
5827 : : /* Restarting if we generate a store-flag expression will cause
5828 : : us to loop. Just drop through in this case. */
5829 : :
5830 : : /* If the result values are STORE_FLAG_VALUE and zero, we can
5831 : : just make the comparison operation. */
5832 : 1065079 : if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5833 : 391381 : x = simplify_gen_relational (cond_code, mode, VOIDmode,
5834 : : cond, cop1);
5835 : 467631 : else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5836 : 673698 : && ((reversed = reversed_comparison_code_parts
5837 : 403767 : (cond_code, cond, cop1, NULL))
5838 : : != UNKNOWN))
5839 : 403767 : x = simplify_gen_relational (reversed, mode, VOIDmode,
5840 : : cond, cop1);
5841 : :
5842 : : /* Likewise, we can make the negate of a comparison operation
5843 : : if the result values are - STORE_FLAG_VALUE and zero. */
5844 : 269931 : else if (CONST_INT_P (true_rtx)
5845 : 185073 : && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5846 : 37114 : && false_rtx == const0_rtx)
5847 : 35644 : x = simplify_gen_unary (NEG, mode,
5848 : : simplify_gen_relational (cond_code,
5849 : : mode, VOIDmode,
5850 : : cond, cop1),
5851 : : mode);
5852 : 234287 : else if (CONST_INT_P (false_rtx)
5853 : 170523 : && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5854 : 22624 : && true_rtx == const0_rtx
5855 : 234287 : && ((reversed = reversed_comparison_code_parts
5856 : 20052 : (cond_code, cond, cop1, NULL))
5857 : : != UNKNOWN))
5858 : 20049 : x = simplify_gen_unary (NEG, mode,
5859 : : simplify_gen_relational (reversed,
5860 : : mode, VOIDmode,
5861 : : cond, cop1),
5862 : : mode);
5863 : :
5864 : 1065079 : code = GET_CODE (x);
5865 : 1065079 : op0_mode = VOIDmode;
5866 : : }
5867 : : }
5868 : : }
5869 : :
5870 : : /* First see if we can apply the inverse distributive law. */
5871 : 203001167 : if (code == PLUS || code == MINUS
5872 : 203001167 : || code == AND || code == IOR || code == XOR)
5873 : : {
5874 : 45279179 : x = apply_distributive_law (x);
5875 : 45279179 : code = GET_CODE (x);
5876 : 45279179 : op0_mode = VOIDmode;
5877 : : }
5878 : :
5879 : : /* If CODE is an associative operation not otherwise handled, see if we
5880 : : can associate some operands. This can win if they are constants or
5881 : : if they are logically related (i.e. (a & b) & a). */
5882 : 203001167 : if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5883 : : || code == AND || code == IOR || code == XOR
5884 : : || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5885 : 49024893 : && ((INTEGRAL_MODE_P (mode) && code != DIV)
5886 : 4447270 : || (flag_associative_math && FLOAT_MODE_P (mode))))
5887 : : {
5888 : 45201360 : if (GET_CODE (XEXP (x, 0)) == code)
5889 : : {
5890 : 3781354 : rtx other = XEXP (XEXP (x, 0), 0);
5891 : 3781354 : rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5892 : 3781354 : rtx inner_op1 = XEXP (x, 1);
5893 : 3781354 : rtx inner;
5894 : :
5895 : : /* Make sure we pass the constant operand if any as the second
5896 : : one if this is a commutative operation. */
5897 : 3781354 : if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5898 : : std::swap (inner_op0, inner_op1);
5899 : 3781354 : inner = simplify_binary_operation (code == MINUS ? PLUS
5900 : 3700310 : : code == DIV ? MULT
5901 : : : code,
5902 : : mode, inner_op0, inner_op1);
5903 : :
5904 : : /* For commutative operations, try the other pair if that one
5905 : : didn't simplify. */
5906 : 3781354 : if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5907 : : {
5908 : 3675942 : other = XEXP (XEXP (x, 0), 1);
5909 : 3675942 : inner = simplify_binary_operation (code, mode,
5910 : : XEXP (XEXP (x, 0), 0),
5911 : : XEXP (x, 1));
5912 : : }
5913 : :
5914 : 3753897 : if (inner)
5915 : 227905 : return simplify_gen_binary (code, mode, other, inner);
5916 : : }
5917 : : }
5918 : :
5919 : : /* A little bit of algebraic simplification here. */
5920 : 202773262 : switch (code)
5921 : : {
5922 : 20962198 : case MEM:
5923 : : /* Ensure that our address has any ASHIFTs converted to MULT in case
5924 : : address-recognizing predicates are called later. */
5925 : 20962198 : temp = make_compound_operation (XEXP (x, 0), MEM);
5926 : 20962198 : SUBST (XEXP (x, 0), temp);
5927 : 20962198 : break;
5928 : :
5929 : 7914854 : case SUBREG:
5930 : 7914854 : if (op0_mode == VOIDmode)
5931 : 162753 : op0_mode = GET_MODE (SUBREG_REG (x));
5932 : :
5933 : : /* See if this can be moved to simplify_subreg. */
5934 : 7914854 : if (CONSTANT_P (SUBREG_REG (x))
5935 : 14119 : && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5936 : : /* Don't call gen_lowpart if the inner mode
5937 : : is VOIDmode and we cannot simplify it, as SUBREG without
5938 : : inner mode is invalid. */
5939 : 7928973 : && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5940 : 0 : || gen_lowpart_common (mode, SUBREG_REG (x))))
5941 : 14119 : return gen_lowpart (mode, SUBREG_REG (x));
5942 : :
5943 : 7900735 : if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5944 : : break;
5945 : 7900735 : {
5946 : 7900735 : rtx temp;
5947 : 15801470 : temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5948 : 7900735 : SUBREG_BYTE (x));
5949 : 7900735 : if (temp)
5950 : 203615350 : return temp;
5951 : :
5952 : : /* If op is known to have all lower bits zero, the result is zero. */
5953 : 7388024 : scalar_int_mode int_mode, int_op0_mode;
5954 : 7388024 : if (!in_dest
5955 : 4448916 : && is_a <scalar_int_mode> (mode, &int_mode)
5956 : 4372184 : && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5957 : 4372184 : && (GET_MODE_PRECISION (int_mode)
5958 : 4372184 : < GET_MODE_PRECISION (int_op0_mode))
5959 : 3881295 : && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5960 : : SUBREG_BYTE (x))
5961 : 3417402 : && HWI_COMPUTABLE_MODE_P (int_op0_mode)
5962 : 3161844 : && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
5963 : 3161844 : & GET_MODE_MASK (int_mode)) == 0)
5964 : 7388691 : && !side_effects_p (SUBREG_REG (x)))
5965 : 667 : return CONST0_RTX (int_mode);
5966 : : }
5967 : :
5968 : : /* Don't change the mode of the MEM if that would change the meaning
5969 : : of the address. */
5970 : 7387357 : if (MEM_P (SUBREG_REG (x))
5971 : 7387357 : && (MEM_VOLATILE_P (SUBREG_REG (x))
5972 : 69146 : || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5973 : 69211 : MEM_ADDR_SPACE (SUBREG_REG (x)))))
5974 : 44007 : return gen_rtx_CLOBBER (mode, const0_rtx);
5975 : :
5976 : : /* Note that we cannot do any narrowing for non-constants since
5977 : : we might have been counting on using the fact that some bits were
5978 : : zero. We now do this in the SET. */
5979 : :
5980 : : break;
5981 : :
5982 : 349805 : case NEG:
5983 : 349805 : temp = expand_compound_operation (XEXP (x, 0));
5984 : :
5985 : : /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5986 : : replaced by (lshiftrt X C). This will convert
5987 : : (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5988 : :
5989 : 349805 : if (GET_CODE (temp) == ASHIFTRT
5990 : 13267 : && CONST_INT_P (XEXP (temp, 1))
5991 : 376277 : && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
5992 : 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5993 : 0 : INTVAL (XEXP (temp, 1)));
5994 : :
5995 : : /* If X has only a single bit that might be nonzero, say, bit I, convert
5996 : : (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5997 : : MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5998 : : (sign_extract X 1 Y). But only do this if TEMP isn't a register
5999 : : or a SUBREG of one since we'd be making the expression more
6000 : : complex if it was just a register. */
6001 : :
6002 : 349805 : if (!REG_P (temp)
6003 : 166416 : && ! (GET_CODE (temp) == SUBREG
6004 : 21063 : && REG_P (SUBREG_REG (temp)))
6005 : 203738200 : && is_a <scalar_int_mode> (mode, &int_mode)
6006 : 472655 : && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6007 : : {
6008 : 56670 : rtx temp1 = simplify_shift_const
6009 : 56670 : (NULL_RTX, ASHIFTRT, int_mode,
6010 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6011 : 56670 : GET_MODE_PRECISION (int_mode) - 1 - i),
6012 : 56670 : GET_MODE_PRECISION (int_mode) - 1 - i);
6013 : :
6014 : : /* If all we did was surround TEMP with the two shifts, we
6015 : : haven't improved anything, so don't use it. Otherwise,
6016 : : we are better off with TEMP1. */
6017 : 56670 : if (GET_CODE (temp1) != ASHIFTRT
6018 : 56477 : || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6019 : 56477 : || XEXP (XEXP (temp1, 0), 0) != temp)
6020 : : return temp1;
6021 : : }
6022 : : break;
6023 : :
6024 : 8803 : case TRUNCATE:
6025 : : /* We can't handle truncation to a partial integer mode here
6026 : : because we don't know the real bitsize of the partial
6027 : : integer mode. */
6028 : 8803 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6029 : : break;
6030 : :
6031 : 8803 : if (HWI_COMPUTABLE_MODE_P (mode))
6032 : 0 : SUBST (XEXP (x, 0),
6033 : : force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6034 : : GET_MODE_MASK (mode), false));
6035 : :
6036 : : /* We can truncate a constant value and return it. */
6037 : 8803 : {
6038 : 8803 : poly_int64 c;
6039 : 8803 : if (poly_int_rtx_p (XEXP (x, 0), &c))
6040 : 0 : return gen_int_mode (c, mode);
6041 : : }
6042 : :
6043 : : /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6044 : : whose value is a comparison can be replaced with a subreg if
6045 : : STORE_FLAG_VALUE permits. */
6046 : 8803 : if (HWI_COMPUTABLE_MODE_P (mode)
6047 : 0 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6048 : 0 : && (temp = get_last_value (XEXP (x, 0)))
6049 : 0 : && COMPARISON_P (temp)
6050 : 8803 : && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6051 : 0 : return gen_lowpart (mode, XEXP (x, 0));
6052 : : break;
6053 : :
6054 : 24533 : case CONST:
6055 : : /* (const (const X)) can become (const X). Do it this way rather than
6056 : : returning the inner CONST since CONST can be shared with a
6057 : : REG_EQUAL note. */
6058 : 24533 : if (GET_CODE (XEXP (x, 0)) == CONST)
6059 : 0 : SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6060 : : break;
6061 : :
6062 : : case LO_SUM:
6063 : : /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6064 : : can add in an offset. find_split_point will split this address up
6065 : : again if it doesn't match. */
6066 : : if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6067 : : && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6068 : : return XEXP (x, 1);
6069 : : break;
6070 : :
6071 : 30973956 : case PLUS:
6072 : : /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6073 : : when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6074 : : bit-field and can be replaced by either a sign_extend or a
6075 : : sign_extract. The `and' may be a zero_extend and the two
6076 : : <c>, -<c> constants may be reversed. */
6077 : 30973956 : if (GET_CODE (XEXP (x, 0)) == XOR
6078 : 30973956 : && is_a <scalar_int_mode> (mode, &int_mode)
6079 : 12738 : && CONST_INT_P (XEXP (x, 1))
6080 : 4316 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6081 : 3800 : && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6082 : 86 : && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6083 : 20 : || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6084 : 48 : && HWI_COMPUTABLE_MODE_P (int_mode)
6085 : 30974004 : && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6086 : 0 : && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6087 : 0 : && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6088 : 0 : == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6089 : 48 : || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6090 : 0 : && known_eq ((GET_MODE_PRECISION
6091 : : (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6092 : : (unsigned int) i + 1))))
6093 : 0 : return simplify_shift_const
6094 : 0 : (NULL_RTX, ASHIFTRT, int_mode,
6095 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6096 : : XEXP (XEXP (XEXP (x, 0), 0), 0),
6097 : 0 : GET_MODE_PRECISION (int_mode) - (i + 1)),
6098 : 0 : GET_MODE_PRECISION (int_mode) - (i + 1));
6099 : :
6100 : : /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6101 : : can become (ashiftrt (ashift (xor x 1) C) C) where C is
6102 : : the bitsize of the mode - 1. This allows simplification of
6103 : : "a = (b & 8) == 0;" */
6104 : 30973956 : if (XEXP (x, 1) == constm1_rtx
6105 : 620378 : && !REG_P (XEXP (x, 0))
6106 : 266590 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6107 : 33493 : && REG_P (SUBREG_REG (XEXP (x, 0))))
6108 : 31200677 : && is_a <scalar_int_mode> (mode, &int_mode)
6109 : 31208644 : && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6110 : 7967 : return simplify_shift_const
6111 : 7967 : (NULL_RTX, ASHIFTRT, int_mode,
6112 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6113 : : gen_rtx_XOR (int_mode, XEXP (x, 0),
6114 : : const1_rtx),
6115 : 7967 : GET_MODE_PRECISION (int_mode) - 1),
6116 : 15934 : GET_MODE_PRECISION (int_mode) - 1);
6117 : :
6118 : : /* If we are adding two things that have no bits in common, convert
6119 : : the addition into an IOR. This will often be further simplified,
6120 : : for example in cases like ((a & 1) + (a & 2)), which can
6121 : : become a & 3. */
6122 : :
6123 : 30965989 : if (HWI_COMPUTABLE_MODE_P (mode)
6124 : 27162762 : && (nonzero_bits (XEXP (x, 0), mode)
6125 : 27162762 : & nonzero_bits (XEXP (x, 1), mode)) == 0)
6126 : : {
6127 : : /* Try to simplify the expression further. */
6128 : 247884 : rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6129 : 247884 : temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6130 : :
6131 : : /* If we could, great. If not, do not go ahead with the IOR
6132 : : replacement, since PLUS appears in many special purpose
6133 : : address arithmetic instructions. */
6134 : 247884 : if (GET_CODE (temp) != CLOBBER
6135 : 247884 : && (GET_CODE (temp) != IOR
6136 : 243669 : || ((XEXP (temp, 0) != XEXP (x, 0)
6137 : 242247 : || XEXP (temp, 1) != XEXP (x, 1))
6138 : 1422 : && (XEXP (temp, 0) != XEXP (x, 1)
6139 : 0 : || XEXP (temp, 1) != XEXP (x, 0)))))
6140 : : return temp;
6141 : : }
6142 : :
6143 : : /* Canonicalize x + x into x << 1. */
6144 : 30960352 : if (GET_MODE_CLASS (mode) == MODE_INT
6145 : 27466768 : && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6146 : 30963137 : && !side_effects_p (XEXP (x, 0)))
6147 : 2785 : return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6148 : :
6149 : : break;
6150 : :
6151 : 3463308 : case MINUS:
6152 : : /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6153 : : (and <foo> (const_int pow2-1)) */
6154 : 3463308 : if (is_a <scalar_int_mode> (mode, &int_mode)
6155 : 2916213 : && GET_CODE (XEXP (x, 1)) == AND
6156 : 141773 : && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6157 : 139081 : && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6158 : 85525 : && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6159 : 0 : return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6160 : 0 : -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6161 : : break;
6162 : :
6163 : 2935569 : case MULT:
6164 : : /* If we have (mult (plus A B) C), apply the distributive law and then
6165 : : the inverse distributive law to see if things simplify. This
6166 : : occurs mostly in addresses, often when unrolling loops. */
6167 : :
6168 : 2935569 : if (GET_CODE (XEXP (x, 0)) == PLUS)
6169 : : {
6170 : 274843 : rtx result = distribute_and_simplify_rtx (x, 0);
6171 : 274843 : if (result)
6172 : : return result;
6173 : : }
6174 : :
6175 : : /* Try simplify a*(b/c) as (a*b)/c. */
6176 : 2932754 : if (FLOAT_MODE_P (mode) && flag_associative_math
6177 : 198167 : && GET_CODE (XEXP (x, 0)) == DIV)
6178 : : {
6179 : 304 : rtx tem = simplify_binary_operation (MULT, mode,
6180 : : XEXP (XEXP (x, 0), 0),
6181 : : XEXP (x, 1));
6182 : 304 : if (tem)
6183 : 33 : return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6184 : : }
6185 : : break;
6186 : :
6187 : 104778 : case UDIV:
6188 : : /* If this is a divide by a power of two, treat it as a shift if
6189 : : its first operand is a shift. */
6190 : 104778 : if (is_a <scalar_int_mode> (mode, &int_mode)
6191 : 104778 : && CONST_INT_P (XEXP (x, 1))
6192 : 1719 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6193 : 0 : && (GET_CODE (XEXP (x, 0)) == ASHIFT
6194 : 0 : || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6195 : 0 : || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6196 : 0 : || GET_CODE (XEXP (x, 0)) == ROTATE
6197 : 0 : || GET_CODE (XEXP (x, 0)) == ROTATERT))
6198 : 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6199 : 0 : XEXP (x, 0), i);
6200 : : break;
6201 : :
6202 : 16018666 : case EQ: case NE:
6203 : 16018666 : case GT: case GTU: case GE: case GEU:
6204 : 16018666 : case LT: case LTU: case LE: case LEU:
6205 : 16018666 : case UNEQ: case LTGT:
6206 : 16018666 : case UNGT: case UNGE:
6207 : 16018666 : case UNLT: case UNLE:
6208 : 16018666 : case UNORDERED: case ORDERED:
6209 : : /* If the first operand is a condition code, we can't do anything
6210 : : with it. */
6211 : 16018666 : if (GET_CODE (XEXP (x, 0)) == COMPARE
6212 : 16018666 : || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6213 : : {
6214 : 12112212 : rtx op0 = XEXP (x, 0);
6215 : 12112212 : rtx op1 = XEXP (x, 1);
6216 : 12112212 : enum rtx_code new_code;
6217 : :
6218 : 12112212 : if (GET_CODE (op0) == COMPARE)
6219 : 0 : op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6220 : :
6221 : : /* Simplify our comparison, if possible. */
6222 : 12112212 : new_code = simplify_comparison (code, &op0, &op1);
6223 : :
6224 : : /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6225 : : if only the low-order bit is possibly nonzero in X (such as when
6226 : : X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6227 : : (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6228 : : known to be either 0 or -1, NE becomes a NEG and EQ becomes
6229 : : (plus X 1).
6230 : :
6231 : : Remove any ZERO_EXTRACT we made when thinking this was a
6232 : : comparison. It may now be simpler to use, e.g., an AND. If a
6233 : : ZERO_EXTRACT is indeed appropriate, it will be placed back by
6234 : : the call to make_compound_operation in the SET case.
6235 : :
6236 : : Don't apply these optimizations if the caller would
6237 : : prefer a comparison rather than a value.
6238 : : E.g., for the condition in an IF_THEN_ELSE most targets need
6239 : : an explicit comparison. */
6240 : :
6241 : 12112212 : if (in_cond)
6242 : : ;
6243 : :
6244 : 1893717 : else if (STORE_FLAG_VALUE == 1
6245 : : && new_code == NE
6246 : 2250548 : && is_int_mode (mode, &int_mode)
6247 : 357031 : && op1 == const0_rtx
6248 : 167777 : && int_mode == GET_MODE (op0)
6249 : 1947085 : && nonzero_bits (op0, int_mode) == 1)
6250 : 200 : return gen_lowpart (int_mode,
6251 : 366503 : expand_compound_operation (op0));
6252 : :
6253 : 1893517 : else if (STORE_FLAG_VALUE == 1
6254 : : && new_code == NE
6255 : 2249704 : && is_int_mode (mode, &int_mode)
6256 : 356831 : && op1 == const0_rtx
6257 : 167577 : && int_mode == GET_MODE (op0)
6258 : 1946685 : && (num_sign_bit_copies (op0, int_mode)
6259 : 53168 : == GET_MODE_PRECISION (int_mode)))
6260 : : {
6261 : 644 : op0 = expand_compound_operation (op0);
6262 : 644 : return simplify_gen_unary (NEG, int_mode,
6263 : 644 : gen_lowpart (int_mode, op0),
6264 : 644 : int_mode);
6265 : : }
6266 : :
6267 : 1892873 : else if (STORE_FLAG_VALUE == 1
6268 : : && new_code == EQ
6269 : 2198786 : && is_int_mode (mode, &int_mode)
6270 : 307224 : && op1 == const0_rtx
6271 : 156100 : && int_mode == GET_MODE (op0)
6272 : 1963838 : && nonzero_bits (op0, int_mode) == 1)
6273 : : {
6274 : 1311 : op0 = expand_compound_operation (op0);
6275 : 1311 : return simplify_gen_binary (XOR, int_mode,
6276 : 1311 : gen_lowpart (int_mode, op0),
6277 : 1311 : const1_rtx);
6278 : : }
6279 : :
6280 : 1891562 : else if (STORE_FLAG_VALUE == 1
6281 : : && new_code == EQ
6282 : 12415419 : && is_int_mode (mode, &int_mode)
6283 : 305913 : && op1 == const0_rtx
6284 : 154789 : && int_mode == GET_MODE (op0)
6285 : 1961216 : && (num_sign_bit_copies (op0, int_mode)
6286 : 69654 : == GET_MODE_PRECISION (int_mode)))
6287 : : {
6288 : 551 : op0 = expand_compound_operation (op0);
6289 : 551 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6290 : : }
6291 : :
6292 : : /* If STORE_FLAG_VALUE is -1, we have cases similar to
6293 : : those above. */
6294 : 12109506 : if (in_cond)
6295 : : ;
6296 : :
6297 : 12109506 : else if (STORE_FLAG_VALUE == -1
6298 : : && new_code == NE
6299 : : && is_int_mode (mode, &int_mode)
6300 : : && op1 == const0_rtx
6301 : : && int_mode == GET_MODE (op0)
6302 : : && (num_sign_bit_copies (op0, int_mode)
6303 : : == GET_MODE_PRECISION (int_mode)))
6304 : : return gen_lowpart (int_mode, expand_compound_operation (op0));
6305 : :
6306 : 12109506 : else if (STORE_FLAG_VALUE == -1
6307 : : && new_code == NE
6308 : : && is_int_mode (mode, &int_mode)
6309 : : && op1 == const0_rtx
6310 : : && int_mode == GET_MODE (op0)
6311 : : && nonzero_bits (op0, int_mode) == 1)
6312 : : {
6313 : : op0 = expand_compound_operation (op0);
6314 : : return simplify_gen_unary (NEG, int_mode,
6315 : : gen_lowpart (int_mode, op0),
6316 : : int_mode);
6317 : : }
6318 : :
6319 : 12109506 : else if (STORE_FLAG_VALUE == -1
6320 : : && new_code == EQ
6321 : : && is_int_mode (mode, &int_mode)
6322 : : && op1 == const0_rtx
6323 : : && int_mode == GET_MODE (op0)
6324 : : && (num_sign_bit_copies (op0, int_mode)
6325 : : == GET_MODE_PRECISION (int_mode)))
6326 : : {
6327 : : op0 = expand_compound_operation (op0);
6328 : : return simplify_gen_unary (NOT, int_mode,
6329 : : gen_lowpart (int_mode, op0),
6330 : : int_mode);
6331 : : }
6332 : :
6333 : : /* If X is 0/1, (eq X 0) is X-1. */
6334 : 12109506 : else if (STORE_FLAG_VALUE == -1
6335 : : && new_code == EQ
6336 : : && is_int_mode (mode, &int_mode)
6337 : : && op1 == const0_rtx
6338 : : && int_mode == GET_MODE (op0)
6339 : : && nonzero_bits (op0, int_mode) == 1)
6340 : : {
6341 : : op0 = expand_compound_operation (op0);
6342 : : return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6343 : : }
6344 : :
6345 : : /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6346 : : one bit that might be nonzero, we can convert (ne x 0) to
6347 : : (ashift x c) where C puts the bit in the sign bit. Remove any
6348 : : AND with STORE_FLAG_VALUE when we are done, since we are only
6349 : : going to test the sign bit. */
6350 : 12109506 : if (new_code == NE
6351 : 12462489 : && is_int_mode (mode, &int_mode)
6352 : 356273 : && HWI_COMPUTABLE_MODE_P (int_mode)
6353 : 352983 : && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6354 : 0 : && op1 == const0_rtx
6355 : 0 : && int_mode == GET_MODE (op0)
6356 : 12109506 : && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6357 : : {
6358 : 0 : x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6359 : : expand_compound_operation (op0),
6360 : 0 : GET_MODE_PRECISION (int_mode) - 1 - i);
6361 : 0 : if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6362 : 0 : return XEXP (x, 0);
6363 : : else
6364 : : return x;
6365 : : }
6366 : :
6367 : : /* If the code changed, return a whole new comparison.
6368 : : We also need to avoid using SUBST in cases where
6369 : : simplify_comparison has widened a comparison with a CONST_INT,
6370 : : since in that case the wider CONST_INT may fail the sanity
6371 : : checks in do_SUBST. */
6372 : 12109506 : if (new_code != code
6373 : 11755554 : || (CONST_INT_P (op1)
6374 : 6847764 : && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6375 : 10975 : && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6376 : 363797 : return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6377 : :
6378 : : /* Otherwise, keep this operation, but maybe change its operands.
6379 : : This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6380 : 11745709 : SUBST (XEXP (x, 0), op0);
6381 : 11745709 : SUBST (XEXP (x, 1), op1);
6382 : : }
6383 : : break;
6384 : :
6385 : 11716282 : case IF_THEN_ELSE:
6386 : 11716282 : return simplify_if_then_else (x);
6387 : :
6388 : 4568354 : case ZERO_EXTRACT:
6389 : 4568354 : case SIGN_EXTRACT:
6390 : 4568354 : case ZERO_EXTEND:
6391 : 4568354 : case SIGN_EXTEND:
6392 : : /* If we are processing SET_DEST, we are done. */
6393 : 4568354 : if (in_dest)
6394 : : return x;
6395 : :
6396 : 4565815 : return expand_compound_operation (x);
6397 : :
6398 : 43700747 : case SET:
6399 : 43700747 : return simplify_set (x);
6400 : :
6401 : 10214815 : case AND:
6402 : 10214815 : case IOR:
6403 : 10214815 : return simplify_logical (x);
6404 : :
6405 : 12397214 : case ASHIFT:
6406 : 12397214 : case LSHIFTRT:
6407 : 12397214 : case ASHIFTRT:
6408 : 12397214 : case ROTATE:
6409 : 12397214 : case ROTATERT:
6410 : : /* If this is a shift by a constant amount, simplify it. */
6411 : 12397214 : if (CONST_INT_P (XEXP (x, 1)))
6412 : 11976684 : return simplify_shift_const (x, code, mode, XEXP (x, 0),
6413 : 11976684 : INTVAL (XEXP (x, 1)));
6414 : :
6415 : : else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6416 : : SUBST (XEXP (x, 1),
6417 : : force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6418 : : (HOST_WIDE_INT_1U
6419 : : << exact_log2 (GET_MODE_UNIT_BITSIZE
6420 : : (GET_MODE (x)))) - 1, false));
6421 : : break;
6422 : 1661051 : case VEC_SELECT:
6423 : 1661051 : {
6424 : 1661051 : rtx trueop0 = XEXP (x, 0);
6425 : 1661051 : mode = GET_MODE (trueop0);
6426 : 1661051 : rtx trueop1 = XEXP (x, 1);
6427 : : /* If we select a low-part subreg, return that. */
6428 : 1661051 : if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6429 : : {
6430 : 790 : rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6431 : 790 : if (new_rtx != NULL_RTX)
6432 : : return new_rtx;
6433 : : }
6434 : : }
6435 : :
6436 : : default:
6437 : : break;
6438 : : }
6439 : :
6440 : : return x;
6441 : : }
6442 : :
6443 : : /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6444 : :
6445 : : static rtx
6446 : 11716282 : simplify_if_then_else (rtx x)
6447 : : {
6448 : 11716282 : machine_mode mode = GET_MODE (x);
6449 : 11716282 : rtx cond = XEXP (x, 0);
6450 : 11716282 : rtx true_rtx = XEXP (x, 1);
6451 : 11716282 : rtx false_rtx = XEXP (x, 2);
6452 : 11716282 : enum rtx_code true_code = GET_CODE (cond);
6453 : 11716282 : bool comparison_p = COMPARISON_P (cond);
6454 : 11716282 : rtx temp;
6455 : 11716282 : int i;
6456 : 11716282 : enum rtx_code false_code;
6457 : 11716282 : rtx reversed;
6458 : 11716282 : scalar_int_mode int_mode, inner_mode;
6459 : :
6460 : : /* Simplify storing of the truth value. */
6461 : 11716282 : if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6462 : 0 : return simplify_gen_relational (true_code, mode, VOIDmode,
6463 : 0 : XEXP (cond, 0), XEXP (cond, 1));
6464 : :
6465 : : /* Also when the truth value has to be reversed. */
6466 : 11715837 : if (comparison_p
6467 : 11715837 : && true_rtx == const0_rtx && false_rtx == const_true_rtx
6468 : 0 : && (reversed = reversed_comparison (cond, mode)))
6469 : : return reversed;
6470 : :
6471 : : /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6472 : : in it is being compared against certain values. Get the true and false
6473 : : comparisons and see if that says anything about the value of each arm. */
6474 : :
6475 : 11716282 : if (comparison_p
6476 : 11715837 : && ((false_code = reversed_comparison_code (cond, NULL))
6477 : : != UNKNOWN)
6478 : 23295779 : && REG_P (XEXP (cond, 0)))
6479 : : {
6480 : 7367397 : HOST_WIDE_INT nzb;
6481 : 7367397 : rtx from = XEXP (cond, 0);
6482 : 7367397 : rtx true_val = XEXP (cond, 1);
6483 : 7367397 : rtx false_val = true_val;
6484 : 7367397 : bool swapped = false;
6485 : :
6486 : : /* If FALSE_CODE is EQ, swap the codes and arms. */
6487 : :
6488 : 7367397 : if (false_code == EQ)
6489 : : {
6490 : 2985039 : swapped = true, true_code = EQ, false_code = NE;
6491 : 2985039 : std::swap (true_rtx, false_rtx);
6492 : : }
6493 : :
6494 : 7367397 : scalar_int_mode from_mode;
6495 : 7367397 : if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6496 : : {
6497 : : /* If we are comparing against zero and the expression being
6498 : : tested has only a single bit that might be nonzero, that is
6499 : : its value when it is not equal to zero. Similarly if it is
6500 : : known to be -1 or 0. */
6501 : 6234678 : if (true_code == EQ
6502 : 4741509 : && true_val == const0_rtx
6503 : 8009651 : && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6504 : : {
6505 : 193186 : false_code = EQ;
6506 : 193186 : false_val = gen_int_mode (nzb, from_mode);
6507 : : }
6508 : 6041492 : else if (true_code == EQ
6509 : 4548323 : && true_val == const0_rtx
6510 : 7623279 : && (num_sign_bit_copies (from, from_mode)
6511 : 1581787 : == GET_MODE_PRECISION (from_mode)))
6512 : : {
6513 : 807 : false_code = EQ;
6514 : 807 : false_val = constm1_rtx;
6515 : : }
6516 : : }
6517 : :
6518 : : /* Now simplify an arm if we know the value of the register in the
6519 : : branch and it is used in the arm. Be careful due to the potential
6520 : : of locally-shared RTL. */
6521 : :
6522 : 7367397 : if (reg_mentioned_p (from, true_rtx))
6523 : 261488 : true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6524 : : from, true_val),
6525 : : pc_rtx, pc_rtx, false, false, false);
6526 : 7367397 : if (reg_mentioned_p (from, false_rtx))
6527 : 86794 : false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6528 : : from, false_val),
6529 : : pc_rtx, pc_rtx, false, false, false);
6530 : :
6531 : 11749755 : SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6532 : 11749755 : SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6533 : :
6534 : 7367397 : true_rtx = XEXP (x, 1);
6535 : 7367397 : false_rtx = XEXP (x, 2);
6536 : 7367397 : true_code = GET_CODE (cond);
6537 : : }
6538 : :
6539 : : /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6540 : : reversed, do so to avoid needing two sets of patterns for
6541 : : subtract-and-branch insns. Similarly if we have a constant in the true
6542 : : arm, the false arm is the same as the first operand of the comparison, or
6543 : : the false arm is more complicated than the true arm. */
6544 : :
6545 : 11716282 : if (comparison_p
6546 : 11715837 : && reversed_comparison_code (cond, NULL) != UNKNOWN
6547 : 23295779 : && (true_rtx == pc_rtx
6548 : 11579497 : || (CONSTANT_P (true_rtx)
6549 : 9864670 : && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6550 : 11548017 : || true_rtx == const0_rtx
6551 : 11547797 : || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6552 : 11515119 : || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6553 : 14047 : && !OBJECT_P (false_rtx))
6554 : 11510291 : || reg_mentioned_p (true_rtx, false_rtx)
6555 : 11510198 : || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6556 : : {
6557 : 96303 : SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6558 : 96303 : SUBST (XEXP (x, 1), false_rtx);
6559 : 96303 : SUBST (XEXP (x, 2), true_rtx);
6560 : :
6561 : 96303 : std::swap (true_rtx, false_rtx);
6562 : 96303 : cond = XEXP (x, 0);
6563 : :
6564 : : /* It is possible that the conditional has been simplified out. */
6565 : 96303 : true_code = GET_CODE (cond);
6566 : 96303 : comparison_p = COMPARISON_P (cond);
6567 : : }
6568 : :
6569 : : /* If the two arms are identical, we don't need the comparison. */
6570 : :
6571 : 11716282 : if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6572 : : return true_rtx;
6573 : :
6574 : : /* Convert a == b ? b : a to "a". */
6575 : 3243552 : if (true_code == EQ && ! side_effects_p (cond)
6576 : 3233522 : && !HONOR_NANS (mode)
6577 : 3202044 : && rtx_equal_p (XEXP (cond, 0), false_rtx)
6578 : 11716638 : && rtx_equal_p (XEXP (cond, 1), true_rtx))
6579 : : return false_rtx;
6580 : 4727834 : else if (true_code == NE && ! side_effects_p (cond)
6581 : 4690114 : && !HONOR_NANS (mode)
6582 : 4686092 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6583 : 11757653 : && rtx_equal_p (XEXP (cond, 1), false_rtx))
6584 : : return true_rtx;
6585 : :
6586 : : /* Look for cases where we have (abs x) or (neg (abs X)). */
6587 : :
6588 : 11716270 : if (GET_MODE_CLASS (mode) == MODE_INT
6589 : 1692056 : && comparison_p
6590 : 1692037 : && XEXP (cond, 1) == const0_rtx
6591 : 1314038 : && GET_CODE (false_rtx) == NEG
6592 : 18 : && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6593 : 0 : && rtx_equal_p (true_rtx, XEXP (cond, 0))
6594 : 11716270 : && ! side_effects_p (true_rtx))
6595 : 0 : switch (true_code)
6596 : : {
6597 : 0 : case GT:
6598 : 0 : case GE:
6599 : 0 : return simplify_gen_unary (ABS, mode, true_rtx, mode);
6600 : 0 : case LT:
6601 : 0 : case LE:
6602 : 0 : return
6603 : 0 : simplify_gen_unary (NEG, mode,
6604 : : simplify_gen_unary (ABS, mode, true_rtx, mode),
6605 : 0 : mode);
6606 : : default:
6607 : : break;
6608 : : }
6609 : :
6610 : : /* Look for MIN or MAX. */
6611 : :
6612 : 11716270 : if ((! FLOAT_MODE_P (mode)
6613 : 41184 : || (flag_unsafe_math_optimizations
6614 : 305 : && !HONOR_NANS (mode)
6615 : 305 : && !HONOR_SIGNED_ZEROS (mode)))
6616 : 11675391 : && comparison_p
6617 : 11675055 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6618 : 81267 : && rtx_equal_p (XEXP (cond, 1), false_rtx)
6619 : 9208 : && ! side_effects_p (cond))
6620 : 9208 : switch (true_code)
6621 : : {
6622 : 2829 : case GE:
6623 : 2829 : case GT:
6624 : 2829 : return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6625 : 3068 : case LE:
6626 : 3068 : case LT:
6627 : 3068 : return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6628 : 2489 : case GEU:
6629 : 2489 : case GTU:
6630 : 2489 : return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6631 : 822 : case LEU:
6632 : 822 : case LTU:
6633 : 822 : return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6634 : : default:
6635 : : break;
6636 : : }
6637 : :
6638 : : /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6639 : : second operand is zero, this can be done as (OP Z (mult COND C2)) where
6640 : : C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6641 : : SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6642 : : We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6643 : : neither 1 or -1, but it isn't worth checking for. */
6644 : :
6645 : 11707062 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6646 : : && comparison_p
6647 : 13303003 : && is_int_mode (mode, &int_mode)
6648 : 13389911 : && ! side_effects_p (x))
6649 : : {
6650 : 1680116 : rtx t = make_compound_operation (true_rtx, SET);
6651 : 1680116 : rtx f = make_compound_operation (false_rtx, SET);
6652 : 1680116 : rtx cond_op0 = XEXP (cond, 0);
6653 : 1680116 : rtx cond_op1 = XEXP (cond, 1);
6654 : 1680116 : enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6655 : 1680116 : scalar_int_mode m = int_mode;
6656 : 1680116 : rtx z = 0, c1 = NULL_RTX;
6657 : :
6658 : 1680116 : if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6659 : : || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6660 : : || GET_CODE (t) == ASHIFT
6661 : : || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6662 : 183764 : && rtx_equal_p (XEXP (t, 0), f))
6663 : 80022 : c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6664 : :
6665 : : /* If an identity-zero op is commutative, check whether there
6666 : : would be a match if we swapped the operands. */
6667 : 1545333 : else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6668 : 1535029 : || GET_CODE (t) == XOR)
6669 : 1611562 : && rtx_equal_p (XEXP (t, 1), f))
6670 : 6886 : c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6671 : 1593208 : else if (GET_CODE (t) == SIGN_EXTEND
6672 : 1557 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6673 : 1557 : && (GET_CODE (XEXP (t, 0)) == PLUS
6674 : 1557 : || GET_CODE (XEXP (t, 0)) == MINUS
6675 : : || GET_CODE (XEXP (t, 0)) == IOR
6676 : : || GET_CODE (XEXP (t, 0)) == XOR
6677 : : || GET_CODE (XEXP (t, 0)) == ASHIFT
6678 : : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6679 : : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6680 : 108 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6681 : 45 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6682 : 45 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6683 : 1593208 : && (num_sign_bit_copies (f, GET_MODE (f))
6684 : 0 : > (unsigned int)
6685 : 0 : (GET_MODE_PRECISION (int_mode)
6686 : 0 : - GET_MODE_PRECISION (inner_mode))))
6687 : : {
6688 : 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6689 : 0 : extend_op = SIGN_EXTEND;
6690 : 0 : m = inner_mode;
6691 : : }
6692 : 1593208 : else if (GET_CODE (t) == SIGN_EXTEND
6693 : 1557 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6694 : 1557 : && (GET_CODE (XEXP (t, 0)) == PLUS
6695 : 1467 : || GET_CODE (XEXP (t, 0)) == IOR
6696 : 1464 : || GET_CODE (XEXP (t, 0)) == XOR)
6697 : 93 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6698 : 2 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6699 : 2 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6700 : 1593210 : && (num_sign_bit_copies (f, GET_MODE (f))
6701 : 2 : > (unsigned int)
6702 : 2 : (GET_MODE_PRECISION (int_mode)
6703 : 2 : - GET_MODE_PRECISION (inner_mode))))
6704 : : {
6705 : 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6706 : 0 : extend_op = SIGN_EXTEND;
6707 : 0 : m = inner_mode;
6708 : : }
6709 : 1593208 : else if (GET_CODE (t) == ZERO_EXTEND
6710 : 2476 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6711 : 2476 : && (GET_CODE (XEXP (t, 0)) == PLUS
6712 : 2476 : || GET_CODE (XEXP (t, 0)) == MINUS
6713 : : || GET_CODE (XEXP (t, 0)) == IOR
6714 : : || GET_CODE (XEXP (t, 0)) == XOR
6715 : : || GET_CODE (XEXP (t, 0)) == ASHIFT
6716 : : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6717 : : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6718 : 538 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6719 : 63 : && HWI_COMPUTABLE_MODE_P (int_mode)
6720 : 63 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6721 : 63 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6722 : 1593208 : && ((nonzero_bits (f, GET_MODE (f))
6723 : 0 : & ~GET_MODE_MASK (inner_mode))
6724 : : == 0))
6725 : : {
6726 : 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6727 : 0 : extend_op = ZERO_EXTEND;
6728 : 0 : m = inner_mode;
6729 : : }
6730 : 1593208 : else if (GET_CODE (t) == ZERO_EXTEND
6731 : 2476 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6732 : 2476 : && (GET_CODE (XEXP (t, 0)) == PLUS
6733 : 2252 : || GET_CODE (XEXP (t, 0)) == IOR
6734 : 2252 : || GET_CODE (XEXP (t, 0)) == XOR)
6735 : 224 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6736 : 12 : && HWI_COMPUTABLE_MODE_P (int_mode)
6737 : 12 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6738 : 12 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6739 : 1593208 : && ((nonzero_bits (f, GET_MODE (f))
6740 : 0 : & ~GET_MODE_MASK (inner_mode))
6741 : : == 0))
6742 : : {
6743 : 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6744 : 0 : extend_op = ZERO_EXTEND;
6745 : 0 : m = inner_mode;
6746 : : }
6747 : :
6748 : 86908 : if (z)
6749 : : {
6750 : 86908 : machine_mode cm = m;
6751 : 86908 : if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6752 : 374 : && GET_MODE (c1) != VOIDmode)
6753 : 75 : cm = GET_MODE (c1);
6754 : 86908 : temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6755 : : cond_op0, cond_op1),
6756 : : pc_rtx, pc_rtx, false, false, false);
6757 : 86908 : temp = simplify_gen_binary (MULT, cm, temp,
6758 : : simplify_gen_binary (MULT, cm, c1,
6759 : : const_true_rtx));
6760 : 86908 : temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6761 : 86908 : temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6762 : :
6763 : 86908 : if (extend_op != UNKNOWN)
6764 : 0 : temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6765 : :
6766 : 86908 : return temp;
6767 : : }
6768 : : }
6769 : :
6770 : : /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6771 : : 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6772 : : negation of a single bit, we can convert this operation to a shift. We
6773 : : can actually do this more generally, but it doesn't seem worth it. */
6774 : :
6775 : 11620154 : if (true_code == NE
6776 : 11620154 : && is_a <scalar_int_mode> (mode, &int_mode)
6777 : 330003 : && XEXP (cond, 1) == const0_rtx
6778 : 220002 : && false_rtx == const0_rtx
6779 : 24062 : && CONST_INT_P (true_rtx)
6780 : 11620536 : && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6781 : 0 : && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6782 : 382 : || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6783 : 382 : == GET_MODE_PRECISION (int_mode))
6784 : 0 : && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6785 : 0 : return
6786 : 0 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6787 : 0 : gen_lowpart (int_mode, XEXP (cond, 0)), i);
6788 : :
6789 : : /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6790 : : non-zero bit in A is C1. */
6791 : 4696528 : if (true_code == NE && XEXP (cond, 1) == const0_rtx
6792 : 1778126 : && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6793 : 11716664 : && is_a <scalar_int_mode> (mode, &int_mode)
6794 : 382 : && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6795 : 30 : && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6796 : 30 : == nonzero_bits (XEXP (cond, 0), inner_mode)
6797 : 11620156 : && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6798 : : {
6799 : 0 : rtx val = XEXP (cond, 0);
6800 : 0 : if (inner_mode == int_mode)
6801 : : return val;
6802 : 0 : else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6803 : 0 : return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6804 : : }
6805 : :
6806 : : return x;
6807 : : }
6808 : :
6809 : : /* Simplify X, a SET expression. Return the new expression. */
6810 : :
6811 : : static rtx
6812 : 43700747 : simplify_set (rtx x)
6813 : : {
6814 : 43700747 : rtx src = SET_SRC (x);
6815 : 43700747 : rtx dest = SET_DEST (x);
6816 : 87401494 : machine_mode mode
6817 : 43700747 : = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6818 : 43700747 : rtx_insn *other_insn;
6819 : 43700747 : rtx *cc_use;
6820 : 43700747 : scalar_int_mode int_mode;
6821 : :
6822 : : /* (set (pc) (return)) gets written as (return). */
6823 : 43700747 : if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6824 : : return src;
6825 : :
6826 : : /* Now that we know for sure which bits of SRC we are using, see if we can
6827 : : simplify the expression for the object knowing that we only need the
6828 : : low-order bits. */
6829 : :
6830 : 43700747 : if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6831 : : {
6832 : 19328979 : src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6833 : 19328979 : SUBST (SET_SRC (x), src);
6834 : : }
6835 : :
6836 : : /* If the source is a COMPARE, look for the use of the comparison result
6837 : : and try to simplify it unless we already have used undobuf.other_insn. */
6838 : 37626088 : if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6839 : 6074659 : && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6840 : 5626691 : && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6841 : 5626691 : && COMPARISON_P (*cc_use)
6842 : 49326977 : && rtx_equal_p (XEXP (*cc_use, 0), dest))
6843 : : {
6844 : 5624728 : enum rtx_code old_code = GET_CODE (*cc_use);
6845 : 5624728 : enum rtx_code new_code;
6846 : 5624728 : rtx op0, op1, tmp;
6847 : 5624728 : bool other_changed = false;
6848 : 5624728 : rtx inner_compare = NULL_RTX;
6849 : 5624728 : machine_mode compare_mode = GET_MODE (dest);
6850 : :
6851 : 5624728 : if (GET_CODE (src) == COMPARE)
6852 : : {
6853 : 5313706 : op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6854 : 5313706 : if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6855 : : {
6856 : 0 : inner_compare = op0;
6857 : 0 : op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6858 : : }
6859 : : }
6860 : : else
6861 : 311022 : op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6862 : :
6863 : 5624728 : tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6864 : : op0, op1);
6865 : 5624728 : if (!tmp)
6866 : : new_code = old_code;
6867 : 503387 : else if (!CONSTANT_P (tmp))
6868 : : {
6869 : 498610 : new_code = GET_CODE (tmp);
6870 : 498610 : op0 = XEXP (tmp, 0);
6871 : 498610 : op1 = XEXP (tmp, 1);
6872 : : }
6873 : : else
6874 : : {
6875 : 4777 : rtx pat = PATTERN (other_insn);
6876 : 4777 : undobuf.other_insn = other_insn;
6877 : 4777 : SUBST (*cc_use, tmp);
6878 : :
6879 : : /* Attempt to simplify CC user. */
6880 : 4777 : if (GET_CODE (pat) == SET)
6881 : : {
6882 : 4266 : rtx new_rtx = simplify_rtx (SET_SRC (pat));
6883 : 4266 : if (new_rtx != NULL_RTX)
6884 : 3925 : SUBST (SET_SRC (pat), new_rtx);
6885 : : }
6886 : :
6887 : : /* Convert X into a no-op move. */
6888 : 4777 : SUBST (SET_DEST (x), pc_rtx);
6889 : 4777 : SUBST (SET_SRC (x), pc_rtx);
6890 : 4777 : return x;
6891 : : }
6892 : :
6893 : : /* Simplify our comparison, if possible. */
6894 : 5619951 : new_code = simplify_comparison (new_code, &op0, &op1);
6895 : :
6896 : : #ifdef SELECT_CC_MODE
6897 : : /* If this machine has CC modes other than CCmode, check to see if we
6898 : : need to use a different CC mode here. */
6899 : 5619951 : if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6900 : 491925 : compare_mode = GET_MODE (op0);
6901 : 5128026 : else if (inner_compare
6902 : 0 : && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6903 : 0 : && new_code == old_code
6904 : 0 : && op0 == XEXP (inner_compare, 0)
6905 : 0 : && op1 == XEXP (inner_compare, 1))
6906 : 0 : compare_mode = GET_MODE (inner_compare);
6907 : : else
6908 : 5128026 : compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6909 : :
6910 : : /* If the mode changed, we have to change SET_DEST, the mode in the
6911 : : compare, and the mode in the place SET_DEST is used. If SET_DEST is
6912 : : a hard register, just build new versions with the proper mode. If it
6913 : : is a pseudo, we lose unless it is only time we set the pseudo, in
6914 : : which case we can safely change its mode. */
6915 : 5619951 : if (compare_mode != GET_MODE (dest))
6916 : : {
6917 : 218872 : if (can_change_dest_mode (dest, 0, compare_mode))
6918 : : {
6919 : 218872 : unsigned int regno = REGNO (dest);
6920 : 218872 : rtx new_dest;
6921 : :
6922 : 218872 : if (regno < FIRST_PSEUDO_REGISTER)
6923 : 218872 : new_dest = gen_rtx_REG (compare_mode, regno);
6924 : : else
6925 : : {
6926 : 0 : subst_mode (regno, compare_mode);
6927 : 0 : new_dest = regno_reg_rtx[regno];
6928 : : }
6929 : :
6930 : 218872 : SUBST (SET_DEST (x), new_dest);
6931 : 218872 : SUBST (XEXP (*cc_use, 0), new_dest);
6932 : 218872 : other_changed = true;
6933 : :
6934 : 218872 : dest = new_dest;
6935 : : }
6936 : : }
6937 : : #endif /* SELECT_CC_MODE */
6938 : :
6939 : : /* If the code changed, we have to build a new comparison in
6940 : : undobuf.other_insn. */
6941 : 5619951 : if (new_code != old_code)
6942 : : {
6943 : 577490 : bool other_changed_previously = other_changed;
6944 : 577490 : unsigned HOST_WIDE_INT mask;
6945 : 577490 : rtx old_cc_use = *cc_use;
6946 : :
6947 : 577490 : SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6948 : : dest, const0_rtx));
6949 : 577490 : other_changed = true;
6950 : :
6951 : : /* If the only change we made was to change an EQ into an NE or
6952 : : vice versa, OP0 has only one bit that might be nonzero, and OP1
6953 : : is zero, check if changing the user of the condition code will
6954 : : produce a valid insn. If it won't, we can keep the original code
6955 : : in that insn by surrounding our operation with an XOR. */
6956 : :
6957 : 577490 : if (((old_code == NE && new_code == EQ)
6958 : 547971 : || (old_code == EQ && new_code == NE))
6959 : 62868 : && ! other_changed_previously && op1 == const0_rtx
6960 : 60557 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6961 : 585752 : && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
6962 : : {
6963 : 8251 : rtx pat = PATTERN (other_insn), note = 0;
6964 : :
6965 : 8251 : if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6966 : 8251 : && ! check_asm_operands (pat)))
6967 : : {
6968 : 4 : *cc_use = old_cc_use;
6969 : 4 : other_changed = false;
6970 : :
6971 : 4 : op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6972 : 4 : gen_int_mode (mask,
6973 : 4 : GET_MODE (op0)));
6974 : : }
6975 : : }
6976 : : }
6977 : :
6978 : 5050712 : if (other_changed)
6979 : 591913 : undobuf.other_insn = other_insn;
6980 : :
6981 : : /* Don't generate a compare of a CC with 0, just use that CC. */
6982 : 5619951 : if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6983 : : {
6984 : 491925 : SUBST (SET_SRC (x), op0);
6985 : 491925 : src = SET_SRC (x);
6986 : : }
6987 : : /* Otherwise, if we didn't previously have the same COMPARE we
6988 : : want, create it from scratch. */
6989 : 5128026 : else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
6990 : 4996233 : || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6991 : : {
6992 : 1446187 : SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6993 : 1446187 : src = SET_SRC (x);
6994 : : }
6995 : : }
6996 : : else
6997 : : {
6998 : : /* Get SET_SRC in a form where we have placed back any
6999 : : compound expressions. Then do the checks below. */
7000 : 38076019 : src = make_compound_operation (src, SET);
7001 : 38076019 : SUBST (SET_SRC (x), src);
7002 : : }
7003 : :
7004 : : /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7005 : : and X being a REG or (subreg (reg)), we may be able to convert this to
7006 : : (set (subreg:m2 x) (op)).
7007 : :
7008 : : We can always do this if M1 is narrower than M2 because that means that
7009 : : we only care about the low bits of the result.
7010 : :
7011 : : However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7012 : : perform a narrower operation than requested since the high-order bits will
7013 : : be undefined. On machine where it is defined, this transformation is safe
7014 : : as long as M1 and M2 have the same number of words. */
7015 : :
7016 : 402453 : if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7017 : 382811 : && !OBJECT_P (SUBREG_REG (src))
7018 : : && (known_equal_after_align_up
7019 : 244494 : (GET_MODE_SIZE (GET_MODE (src)),
7020 : 488988 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7021 : 244494 : UNITS_PER_WORD))
7022 : 214564 : && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7023 : 209756 : && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7024 : 141 : && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7025 : : GET_MODE (SUBREG_REG (src)),
7026 : : GET_MODE (src)))
7027 : 43905585 : && (REG_P (dest)
7028 : 97671 : || (GET_CODE (dest) == SUBREG
7029 : 261 : && REG_P (SUBREG_REG (dest)))))
7030 : : {
7031 : 112205 : SUBST (SET_DEST (x),
7032 : : gen_lowpart (GET_MODE (SUBREG_REG (src)),
7033 : : dest));
7034 : 112205 : SUBST (SET_SRC (x), SUBREG_REG (src));
7035 : :
7036 : 112205 : src = SET_SRC (x), dest = SET_DEST (x);
7037 : : }
7038 : :
7039 : : /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7040 : : would require a paradoxical subreg. Replace the subreg with a
7041 : : zero_extend to avoid the reload that would otherwise be required.
7042 : : Don't do this unless we have a scalar integer mode, otherwise the
7043 : : transformation is incorrect. */
7044 : :
7045 : 43695970 : enum rtx_code extend_op;
7046 : 43695970 : if (paradoxical_subreg_p (src)
7047 : : && MEM_P (SUBREG_REG (src))
7048 : : && SCALAR_INT_MODE_P (GET_MODE (src))
7049 : : && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7050 : : {
7051 : : SUBST (SET_SRC (x),
7052 : : gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7053 : :
7054 : : src = SET_SRC (x);
7055 : : }
7056 : :
7057 : : /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7058 : : are comparing an item known to be 0 or -1 against 0, use a logical
7059 : : operation instead. Check for one of the arms being an IOR of the other
7060 : : arm with some value. We compute three terms to be IOR'ed together. In
7061 : : practice, at most two will be nonzero. Then we do the IOR's. */
7062 : :
7063 : 43695970 : if (GET_CODE (dest) != PC
7064 : 33756746 : && GET_CODE (src) == IF_THEN_ELSE
7065 : 968949 : && is_int_mode (GET_MODE (src), &int_mode)
7066 : 919125 : && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7067 : 408014 : && XEXP (XEXP (src, 0), 1) == const0_rtx
7068 : 263500 : && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7069 : 77365 : && (!HAVE_conditional_move
7070 : 77365 : || ! can_conditionally_move_p (int_mode))
7071 : 0 : && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7072 : 0 : == GET_MODE_PRECISION (int_mode))
7073 : 43695970 : && ! side_effects_p (src))
7074 : : {
7075 : 0 : rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7076 : 0 : ? XEXP (src, 1) : XEXP (src, 2));
7077 : 0 : rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7078 : 0 : ? XEXP (src, 2) : XEXP (src, 1));
7079 : 0 : rtx term1 = const0_rtx, term2, term3;
7080 : :
7081 : 0 : if (GET_CODE (true_rtx) == IOR
7082 : 0 : && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7083 : 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7084 : 0 : else if (GET_CODE (true_rtx) == IOR
7085 : 0 : && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7086 : 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7087 : 0 : else if (GET_CODE (false_rtx) == IOR
7088 : 0 : && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7089 : 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7090 : 0 : else if (GET_CODE (false_rtx) == IOR
7091 : 0 : && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7092 : 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7093 : :
7094 : 0 : term2 = simplify_gen_binary (AND, int_mode,
7095 : 0 : XEXP (XEXP (src, 0), 0), true_rtx);
7096 : 0 : term3 = simplify_gen_binary (AND, int_mode,
7097 : : simplify_gen_unary (NOT, int_mode,
7098 : 0 : XEXP (XEXP (src, 0), 0),
7099 : : int_mode),
7100 : : false_rtx);
7101 : :
7102 : 0 : SUBST (SET_SRC (x),
7103 : : simplify_gen_binary (IOR, int_mode,
7104 : : simplify_gen_binary (IOR, int_mode,
7105 : : term1, term2),
7106 : : term3));
7107 : :
7108 : 0 : src = SET_SRC (x);
7109 : : }
7110 : :
7111 : : /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7112 : : whole thing fail. */
7113 : 43695970 : if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7114 : : return src;
7115 : 43695958 : else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7116 : : return dest;
7117 : : else
7118 : : /* Convert this into a field assignment operation, if possible. */
7119 : 43695958 : return make_field_assignment (x);
7120 : : }
7121 : :
7122 : : /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7123 : : result. */
7124 : :
7125 : : static rtx
7126 : 10214815 : simplify_logical (rtx x)
7127 : : {
7128 : 10214815 : rtx op0 = XEXP (x, 0);
7129 : 10214815 : rtx op1 = XEXP (x, 1);
7130 : 10214815 : scalar_int_mode mode;
7131 : :
7132 : 10214815 : switch (GET_CODE (x))
7133 : : {
7134 : 6216739 : case AND:
7135 : : /* We can call simplify_and_const_int only if we don't lose
7136 : : any (sign) bits when converting INTVAL (op1) to
7137 : : "unsigned HOST_WIDE_INT". */
7138 : 6216739 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7139 : 5796600 : && CONST_INT_P (op1)
7140 : 4541633 : && (HWI_COMPUTABLE_MODE_P (mode)
7141 : 7447 : || INTVAL (op1) > 0))
7142 : : {
7143 : 4540554 : x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7144 : 4540554 : if (GET_CODE (x) != AND)
7145 : : return x;
7146 : :
7147 : 4511611 : op0 = XEXP (x, 0);
7148 : 4511611 : op1 = XEXP (x, 1);
7149 : : }
7150 : :
7151 : : /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7152 : : apply the distributive law and then the inverse distributive
7153 : : law to see if things simplify. */
7154 : 6187796 : if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7155 : : {
7156 : 107170 : rtx result = distribute_and_simplify_rtx (x, 0);
7157 : 107170 : if (result)
7158 : : return result;
7159 : : }
7160 : 6174702 : if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7161 : : {
7162 : 1733 : rtx result = distribute_and_simplify_rtx (x, 1);
7163 : 1733 : if (result)
7164 : : return result;
7165 : : }
7166 : : break;
7167 : :
7168 : 3998076 : case IOR:
7169 : : /* If we have (ior (and A B) C), apply the distributive law and then
7170 : : the inverse distributive law to see if things simplify. */
7171 : :
7172 : 3998076 : if (GET_CODE (op0) == AND)
7173 : : {
7174 : 1124708 : rtx result = distribute_and_simplify_rtx (x, 0);
7175 : 1124708 : if (result)
7176 : : return result;
7177 : : }
7178 : :
7179 : 3998074 : if (GET_CODE (op1) == AND)
7180 : : {
7181 |
