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1 : : /* Optimize by combining instructions for GNU compiler.
2 : : Copyright (C) 1987-2025 Free Software Foundation, Inc.
3 : :
4 : : This file is part of GCC.
5 : :
6 : : GCC is free software; you can redistribute it and/or modify it under
7 : : the terms of the GNU General Public License as published by the Free
8 : : Software Foundation; either version 3, or (at your option) any later
9 : : version.
10 : :
11 : : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : : for more details.
15 : :
16 : : You should have received a copy of the GNU General Public License
17 : : along with GCC; see the file COPYING3. If not see
18 : : <http://www.gnu.org/licenses/>. */
19 : :
20 : : /* This module is essentially the "combiner" phase of the U. of Arizona
21 : : Portable Optimizer, but redone to work on our list-structured
22 : : representation for RTL instead of their string representation.
23 : :
24 : : The LOG_LINKS of each insn identify the most recent assignment
25 : : to each REG used in the insn. It is a list of previous insns,
26 : : each of which contains a SET for a REG that is used in this insn
27 : : and not used or set in between. LOG_LINKs never cross basic blocks.
28 : : They were set up by the preceding pass (lifetime analysis).
29 : :
30 : : We try to combine each pair of insns joined by a logical link.
31 : : We also try to combine triplets of insns A, B and C when C has
32 : : a link back to B and B has a link back to A. Likewise for a
33 : : small number of quadruplets of insns A, B, C and D for which
34 : : there's high likelihood of success.
35 : :
36 : : We check (with modified_between_p) to avoid combining in such a way
37 : : as to move a computation to a place where its value would be different.
38 : :
39 : : Combination is done by mathematically substituting the previous
40 : : insn(s) values for the regs they set into the expressions in
41 : : the later insns that refer to these regs. If the result is a valid insn
42 : : for our target machine, according to the machine description,
43 : : we install it, delete the earlier insns, and update the data flow
44 : : information (LOG_LINKS and REG_NOTES) for what we did.
45 : :
46 : : There are a few exceptions where the dataflow information isn't
47 : : completely updated (however this is only a local issue since it is
48 : : regenerated before the next pass that uses it):
49 : :
50 : : - reg_live_length is not updated
51 : : - reg_n_refs is not adjusted in the rare case when a register is
52 : : no longer required in a computation
53 : : - there are extremely rare cases (see distribute_notes) when a
54 : : REG_DEAD note is lost
55 : : - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 : : removed because there is no way to know which register it was
57 : : linking
58 : :
59 : : To simplify substitution, we combine only when the earlier insn(s)
60 : : consist of only a single assignment. To simplify updating afterward,
61 : : we never combine when a subroutine call appears in the middle. */
62 : :
63 : : #include "config.h"
64 : : #include "system.h"
65 : : #include "coretypes.h"
66 : : #include "backend.h"
67 : : #include "target.h"
68 : : #include "rtl.h"
69 : : #include "tree.h"
70 : : #include "cfghooks.h"
71 : : #include "predict.h"
72 : : #include "df.h"
73 : : #include "memmodel.h"
74 : : #include "tm_p.h"
75 : : #include "optabs.h"
76 : : #include "regs.h"
77 : : #include "emit-rtl.h"
78 : : #include "recog.h"
79 : : #include "cgraph.h"
80 : : #include "stor-layout.h"
81 : : #include "cfgrtl.h"
82 : : #include "cfgcleanup.h"
83 : : /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84 : : #include "explow.h"
85 : : #include "insn-attr.h"
86 : : #include "rtlhooks-def.h"
87 : : #include "expr.h"
88 : : #include "tree-pass.h"
89 : : #include "valtrack.h"
90 : : #include "rtl-iter.h"
91 : : #include "print-rtl.h"
92 : : #include "function-abi.h"
93 : : #include "rtlanal.h"
94 : :
95 : : /* Number of attempts to combine instructions in this function. */
96 : :
97 : : static int combine_attempts;
98 : :
99 : : /* Number of attempts that got as far as substitution in this function. */
100 : :
101 : : static int combine_merges;
102 : :
103 : : /* Number of instructions combined with added SETs in this function. */
104 : :
105 : : static int combine_extras;
106 : :
107 : : /* Number of instructions combined in this function. */
108 : :
109 : : static int combine_successes;
110 : :
111 : : /* combine_instructions may try to replace the right hand side of the
112 : : second instruction with the value of an associated REG_EQUAL note
113 : : before throwing it at try_combine. That is problematic when there
114 : : is a REG_DEAD note for a register used in the old right hand side
115 : : and can cause distribute_notes to do wrong things. This is the
116 : : second instruction if it has been so modified, null otherwise. */
117 : :
118 : : static rtx_insn *i2mod;
119 : :
120 : : /* When I2MOD is nonnull, this is a copy of the old right hand side. */
121 : :
122 : : static rtx i2mod_old_rhs;
123 : :
124 : : /* When I2MOD is nonnull, this is a copy of the new right hand side. */
125 : :
126 : : static rtx i2mod_new_rhs;
127 : :
128 : : struct reg_stat_type {
129 : : /* Record last point of death of (hard or pseudo) register n. */
130 : : rtx_insn *last_death;
131 : :
132 : : /* Record last point of modification of (hard or pseudo) register n. */
133 : : rtx_insn *last_set;
134 : :
135 : : /* The next group of fields allows the recording of the last value assigned
136 : : to (hard or pseudo) register n. We use this information to see if an
137 : : operation being processed is redundant given a prior operation performed
138 : : on the register. For example, an `and' with a constant is redundant if
139 : : all the zero bits are already known to be turned off.
140 : :
141 : : We use an approach similar to that used by cse, but change it in the
142 : : following ways:
143 : :
144 : : (1) We do not want to reinitialize at each label.
145 : : (2) It is useful, but not critical, to know the actual value assigned
146 : : to a register. Often just its form is helpful.
147 : :
148 : : Therefore, we maintain the following fields:
149 : :
150 : : last_set_value the last value assigned
151 : : last_set_label records the value of label_tick when the
152 : : register was assigned
153 : : last_set_table_tick records the value of label_tick when a
154 : : value using the register is assigned
155 : : last_set_invalid set to true when it is not valid
156 : : to use the value of this register in some
157 : : register's value
158 : :
159 : : To understand the usage of these tables, it is important to understand
160 : : the distinction between the value in last_set_value being valid and
161 : : the register being validly contained in some other expression in the
162 : : table.
163 : :
164 : : (The next two parameters are out of date).
165 : :
166 : : reg_stat[i].last_set_value is valid if it is nonzero, and either
167 : : reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168 : :
169 : : Register I may validly appear in any expression returned for the value
170 : : of another register if reg_n_sets[i] is 1. It may also appear in the
171 : : value for register J if reg_stat[j].last_set_invalid is zero, or
172 : : reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173 : :
174 : : If an expression is found in the table containing a register which may
175 : : not validly appear in an expression, the register is replaced by
176 : : something that won't match, (clobber (const_int 0)). */
177 : :
178 : : /* Record last value assigned to (hard or pseudo) register n. */
179 : :
180 : : rtx last_set_value;
181 : :
182 : : /* Record the value of label_tick when an expression involving register n
183 : : is placed in last_set_value. */
184 : :
185 : : int last_set_table_tick;
186 : :
187 : : /* Record the value of label_tick when the value for register n is placed in
188 : : last_set_value. */
189 : :
190 : : int last_set_label;
191 : :
192 : : /* These fields are maintained in parallel with last_set_value and are
193 : : used to store the mode in which the register was last set, the bits
194 : : that were known to be zero when it was last set, and the number of
195 : : sign bits copies it was known to have when it was last set. */
196 : :
197 : : unsigned HOST_WIDE_INT last_set_nonzero_bits;
198 : : char last_set_sign_bit_copies;
199 : : ENUM_BITFIELD(machine_mode) last_set_mode : MACHINE_MODE_BITSIZE;
200 : :
201 : : /* Set to true if references to register n in expressions should not be
202 : : used. last_set_invalid is set nonzero when this register is being
203 : : assigned to and last_set_table_tick == label_tick. */
204 : :
205 : : bool last_set_invalid;
206 : :
207 : : /* Some registers that are set more than once and used in more than one
208 : : basic block are nevertheless always set in similar ways. For example,
209 : : a QImode register may be loaded from memory in two places on a machine
210 : : where byte loads zero extend.
211 : :
212 : : We record in the following fields if a register has some leading bits
213 : : that are always equal to the sign bit, and what we know about the
214 : : nonzero bits of a register, specifically which bits are known to be
215 : : zero.
216 : :
217 : : If an entry is zero, it means that we don't know anything special. */
218 : :
219 : : unsigned char sign_bit_copies;
220 : :
221 : : unsigned HOST_WIDE_INT nonzero_bits;
222 : :
223 : : /* Record the value of the label_tick when the last truncation
224 : : happened. The field truncated_to_mode is only valid if
225 : : truncation_label == label_tick. */
226 : :
227 : : int truncation_label;
228 : :
229 : : /* Record the last truncation seen for this register. If truncation
230 : : is not a nop to this mode we might be able to save an explicit
231 : : truncation if we know that value already contains a truncated
232 : : value. */
233 : :
234 : : ENUM_BITFIELD(machine_mode) truncated_to_mode : MACHINE_MODE_BITSIZE;
235 : : };
236 : :
237 : :
238 : : static vec<reg_stat_type> reg_stat;
239 : :
240 : : /* One plus the highest pseudo for which we track REG_N_SETS.
241 : : regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 : : but during combine_split_insns new pseudos can be created. As we don't have
243 : : updated DF information in that case, it is hard to initialize the array
244 : : after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 : : so instead of growing the arrays, just assume all newly created pseudos
246 : : during combine might be set multiple times. */
247 : :
248 : : static unsigned int reg_n_sets_max;
249 : :
250 : : /* Record the luid of the last insn that invalidated memory
251 : : (anything that writes memory, and subroutine calls, but not pushes). */
252 : :
253 : : static int mem_last_set;
254 : :
255 : : /* Record the luid of the last CALL_INSN
256 : : so we can tell whether a potential combination crosses any calls. */
257 : :
258 : : static int last_call_luid;
259 : :
260 : : /* When `subst' is called, this is the insn that is being modified
261 : : (by combining in a previous insn). The PATTERN of this insn
262 : : is still the old pattern partially modified and it should not be
263 : : looked at, but this may be used to examine the successors of the insn
264 : : to judge whether a simplification is valid. */
265 : :
266 : : static rtx_insn *subst_insn;
267 : :
268 : : /* This is the lowest LUID that `subst' is currently dealing with.
269 : : get_last_value will not return a value if the register was set at or
270 : : after this LUID. If not for this mechanism, we could get confused if
271 : : I2 or I1 in try_combine were an insn that used the old value of a register
272 : : to obtain a new value. In that case, we might erroneously get the
273 : : new value of the register when we wanted the old one. */
274 : :
275 : : static int subst_low_luid;
276 : :
277 : : /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 : : must consider all these registers to be always live. */
279 : :
280 : : static HARD_REG_SET newpat_used_regs;
281 : :
282 : : /* This is an insn to which a LOG_LINKS entry has been added. If this
283 : : insn is the earlier than I2 or I3, combine should rescan starting at
284 : : that location. */
285 : :
286 : : static rtx_insn *added_links_insn;
287 : :
288 : : /* And similarly, for notes. */
289 : :
290 : : static rtx_insn *added_notes_insn;
291 : :
292 : : /* Basic block in which we are performing combines. */
293 : : static basic_block this_basic_block;
294 : : static bool optimize_this_for_speed_p;
295 : :
296 : :
297 : : /* Length of the currently allocated uid_insn_cost array. */
298 : :
299 : : static int max_uid_known;
300 : :
301 : : /* The following array records the insn_cost for every insn
302 : : in the instruction stream. */
303 : :
304 : : static int *uid_insn_cost;
305 : :
306 : : /* The following array records the LOG_LINKS for every insn in the
307 : : instruction stream as struct insn_link pointers. */
308 : :
309 : : struct insn_link {
310 : : rtx_insn *insn;
311 : : unsigned int regno;
312 : : int insn_count;
313 : : struct insn_link *next;
314 : : };
315 : :
316 : : static struct insn_link **uid_log_links;
317 : :
318 : : static inline int
319 : 747842696 : insn_uid_check (const_rtx insn)
320 : : {
321 : 747842696 : int uid = INSN_UID (insn);
322 : 747842696 : gcc_checking_assert (uid <= max_uid_known);
323 : 747842696 : return uid;
324 : : }
325 : :
326 : : #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
327 : : #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 : :
329 : : #define FOR_EACH_LOG_LINK(L, INSN) \
330 : : for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 : :
332 : : /* Links for LOG_LINKS are allocated from this obstack. */
333 : :
334 : : static struct obstack insn_link_obstack;
335 : :
336 : : /* Allocate a link. */
337 : :
338 : : static inline struct insn_link *
339 : 37934832 : alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
340 : : {
341 : 37934832 : struct insn_link *l
342 : 37934832 : = (struct insn_link *) obstack_alloc (&insn_link_obstack,
343 : : sizeof (struct insn_link));
344 : 37934832 : l->insn = insn;
345 : 37934832 : l->regno = regno;
346 : 37934832 : l->insn_count = 0;
347 : 37934832 : l->next = next;
348 : 37934832 : return l;
349 : : }
350 : :
351 : : /* Incremented for each basic block. */
352 : :
353 : : static int label_tick;
354 : :
355 : : /* Reset to label_tick for each extended basic block in scanning order. */
356 : :
357 : : static int label_tick_ebb_start;
358 : :
359 : : /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
360 : : largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
361 : :
362 : : static scalar_int_mode nonzero_bits_mode;
363 : :
364 : : /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
365 : : be safely used. It is zero while computing them and after combine has
366 : : completed. This former test prevents propagating values based on
367 : : previously set values, which can be incorrect if a variable is modified
368 : : in a loop. */
369 : :
370 : : static int nonzero_sign_valid;
371 : :
372 : :
373 : : /* Record one modification to rtl structure
374 : : to be undone by storing old_contents into *where. */
375 : :
376 : : enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
377 : :
378 : : struct undo
379 : : {
380 : : struct undo *next;
381 : : enum undo_kind kind;
382 : : union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
383 : : union { rtx *r; int *i; int regno; struct insn_link **l; } where;
384 : : };
385 : :
386 : : /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
387 : : num_undo says how many are currently recorded.
388 : :
389 : : other_insn is nonzero if we have modified some other insn in the process
390 : : of working on subst_insn. It must be verified too. */
391 : :
392 : : struct undobuf
393 : : {
394 : : struct undo *undos;
395 : : struct undo *frees;
396 : : rtx_insn *other_insn;
397 : : };
398 : :
399 : : static struct undobuf undobuf;
400 : :
401 : : /* Number of times the pseudo being substituted for
402 : : was found and replaced. */
403 : :
404 : : static int n_occurrences;
405 : :
406 : : static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
407 : : scalar_int_mode,
408 : : unsigned HOST_WIDE_INT *);
409 : : static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
410 : : scalar_int_mode,
411 : : unsigned int *);
412 : : static void do_SUBST (rtx *, rtx);
413 : : static void do_SUBST_INT (int *, int);
414 : : static void init_reg_last (void);
415 : : static void setup_incoming_promotions (rtx_insn *);
416 : : static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
417 : : static bool cant_combine_insn_p (rtx_insn *);
418 : : static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
419 : : rtx_insn *, rtx_insn *, rtx *, rtx *);
420 : : static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
421 : : bool, bool, rtx *);
422 : : static bool contains_muldiv (rtx);
423 : : static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
424 : : bool *, rtx_insn *);
425 : : static void undo_all (void);
426 : : static void undo_commit (void);
427 : : static rtx *find_split_point (rtx *, rtx_insn *, bool);
428 : : static rtx subst (rtx, rtx, rtx, bool, bool, bool);
429 : : static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
430 : : static rtx simplify_if_then_else (rtx);
431 : : static rtx simplify_set (rtx);
432 : : static rtx simplify_logical (rtx);
433 : : static rtx expand_compound_operation (rtx);
434 : : static const_rtx expand_field_assignment (const_rtx);
435 : : static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
436 : : unsigned HOST_WIDE_INT, bool, bool, bool);
437 : : static int get_pos_from_mask (unsigned HOST_WIDE_INT,
438 : : unsigned HOST_WIDE_INT *);
439 : : static rtx canon_reg_for_combine (rtx, rtx);
440 : : static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
441 : : scalar_int_mode, unsigned HOST_WIDE_INT, bool);
442 : : static rtx force_to_mode (rtx, machine_mode,
443 : : unsigned HOST_WIDE_INT, bool);
444 : : static rtx if_then_else_cond (rtx, rtx *, rtx *);
445 : : static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
446 : : static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
447 : : static rtx make_field_assignment (rtx);
448 : : static rtx apply_distributive_law (rtx);
449 : : static rtx distribute_and_simplify_rtx (rtx, int);
450 : : static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
451 : : unsigned HOST_WIDE_INT);
452 : : static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
453 : : unsigned HOST_WIDE_INT);
454 : : static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
455 : : HOST_WIDE_INT, machine_mode, bool *);
456 : : static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
457 : : static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
458 : : int);
459 : : static int recog_for_combine (rtx *, rtx_insn *, rtx *, unsigned = 0, unsigned = 0);
460 : : static rtx gen_lowpart_for_combine (machine_mode, rtx);
461 : : static rtx gen_lowpart_for_combine_no_emit (machine_mode, rtx);
462 : : static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
463 : : rtx *, rtx *);
464 : : static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
465 : : static void update_table_tick (rtx);
466 : : static void record_value_for_reg (rtx, rtx_insn *, rtx);
467 : : static void check_promoted_subreg (rtx_insn *, rtx);
468 : : static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
469 : : static void record_dead_and_set_regs (rtx_insn *);
470 : : static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
471 : : static rtx get_last_value (const_rtx);
472 : : static void reg_dead_at_p_1 (rtx, const_rtx, void *);
473 : : static bool reg_dead_at_p (rtx, rtx_insn *);
474 : : static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
475 : : static bool reg_bitfield_target_p (rtx, rtx);
476 : : static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
477 : : rtx, rtx, rtx);
478 : : static void distribute_links (struct insn_link *, rtx_insn * = nullptr,
479 : : int limit = INT_MAX);
480 : : static void mark_used_regs_combine (rtx);
481 : : static void record_promoted_value (rtx_insn *, rtx);
482 : : static bool unmentioned_reg_p (rtx, rtx);
483 : : static void record_truncated_values (rtx *, void *);
484 : : static bool reg_truncated_to_mode (machine_mode, const_rtx);
485 : : static rtx gen_lowpart_or_truncate (machine_mode, rtx);
486 : :
487 : :
488 : : /* It is not safe to use ordinary gen_lowpart in combine.
489 : : See comments in gen_lowpart_for_combine. */
490 : : #undef RTL_HOOKS_GEN_LOWPART
491 : : #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 : :
493 : : /* Our implementation of gen_lowpart never emits a new pseudo. */
494 : : #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 : : #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine_no_emit
496 : :
497 : : #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 : : #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 : :
500 : : #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 : : #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 : :
503 : : #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 : : #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
505 : :
506 : : static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
507 : :
508 : :
509 : : /* Convenience wrapper for the canonicalize_comparison target hook.
510 : : Target hooks cannot use enum rtx_code. */
511 : : static inline void
512 : 22725058 : target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
513 : : bool op0_preserve_value)
514 : : {
515 : 22725058 : int code_int = (int)*code;
516 : 22725058 : targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
517 : 22725058 : *code = (enum rtx_code)code_int;
518 : 799199 : }
519 : :
520 : : /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 : : PATTERN cannot be split. Otherwise, it returns an insn sequence.
522 : : Updates OLD_NREGS with the max number of regs before the split
523 : : and NEW_NREGS after the split.
524 : : This is a wrapper around split_insns which ensures that the
525 : : reg_stat vector is made larger if the splitter creates a new
526 : : register. */
527 : :
528 : : static rtx_insn *
529 : 11997008 : combine_split_insns (rtx pattern, rtx_insn *insn,
530 : : unsigned int *old_nregs,
531 : : unsigned int *new_regs)
532 : : {
533 : 11997008 : rtx_insn *ret;
534 : 11997008 : unsigned int nregs;
535 : 11997008 : *old_nregs = max_reg_num ();
536 : 11997008 : ret = split_insns (pattern, insn);
537 : 11997008 : *new_regs = nregs = max_reg_num ();
538 : 23994016 : if (nregs > reg_stat.length ())
539 : 4683 : reg_stat.safe_grow_cleared (nregs, true);
540 : 11997008 : return ret;
541 : : }
542 : :
543 : : /* This is used by find_single_use to locate an rtx in LOC that
544 : : contains exactly one use of DEST, which is typically a REG.
545 : : It returns a pointer to the innermost rtx expression
546 : : containing DEST. Appearances of DEST that are being used to
547 : : totally replace it are not counted. */
548 : :
549 : : static rtx *
550 : 31871072 : find_single_use_1 (rtx dest, rtx *loc)
551 : : {
552 : 38547259 : rtx x = *loc;
553 : 38547259 : enum rtx_code code = GET_CODE (x);
554 : 38547259 : rtx *result = NULL;
555 : 38547259 : rtx *this_result;
556 : 38547259 : int i;
557 : 38547259 : const char *fmt;
558 : :
559 : 38547259 : switch (code)
560 : : {
561 : : case CONST:
562 : : case LABEL_REF:
563 : : case SYMBOL_REF:
564 : : CASE_CONST_ANY:
565 : : case CLOBBER:
566 : : return 0;
567 : :
568 : 6631842 : case SET:
569 : : /* If the destination is anything other than PC, a REG or a SUBREG
570 : : of a REG that occupies all of the REG, the insn uses DEST if
571 : : it is mentioned in the destination or the source. Otherwise, we
572 : : need just check the source. */
573 : 6631842 : if (GET_CODE (SET_DEST (x)) != PC
574 : 6631842 : && !REG_P (SET_DEST (x))
575 : 6632184 : && ! (GET_CODE (SET_DEST (x)) == SUBREG
576 : 342 : && REG_P (SUBREG_REG (SET_DEST (x)))
577 : 342 : && !read_modify_subreg_p (SET_DEST (x))))
578 : : break;
579 : :
580 : 6630730 : return find_single_use_1 (dest, &SET_SRC (x));
581 : :
582 : 45457 : case MEM:
583 : 45457 : case SUBREG:
584 : 45457 : return find_single_use_1 (dest, &XEXP (x, 0));
585 : :
586 : : default:
587 : : break;
588 : : }
589 : :
590 : : /* If it wasn't one of the common cases above, check each expression and
591 : : vector of this code. Look for a unique usage of DEST. */
592 : :
593 : 19207243 : fmt = GET_RTX_FORMAT (code);
594 : 51318307 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
595 : : {
596 : 32120288 : if (fmt[i] == 'e')
597 : : {
598 : 31768967 : if (dest == XEXP (x, i)
599 : 31768967 : || (REG_P (dest) && REG_P (XEXP (x, i))
600 : 796579 : && REGNO (dest) == REGNO (XEXP (x, i))))
601 : : this_result = loc;
602 : : else
603 : 25132441 : this_result = find_single_use_1 (dest, &XEXP (x, i));
604 : :
605 : 31768967 : if (result == NULL)
606 : : result = this_result;
607 : 44838 : else if (this_result)
608 : : /* Duplicate usage. */
609 : : return NULL;
610 : : }
611 : 351321 : else if (fmt[i] == 'E')
612 : : {
613 : 54808 : int j;
614 : :
615 : 166673 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
616 : : {
617 : 115829 : if (XVECEXP (x, i, j) == dest
618 : 115829 : || (REG_P (dest)
619 : 115829 : && REG_P (XVECEXP (x, i, j))
620 : 4531 : && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
621 : : this_result = loc;
622 : : else
623 : 115829 : this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
624 : :
625 : 115829 : if (result == NULL)
626 : : result = this_result;
627 : 18536 : else if (this_result)
628 : : return NULL;
629 : : }
630 : : }
631 : : }
632 : :
633 : : return result;
634 : : }
635 : :
636 : :
637 : : /* See if DEST, produced in INSN, is used only a single time in the
638 : : sequel. If so, return a pointer to the innermost rtx expression in which
639 : : it is used.
640 : :
641 : : If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 : :
643 : : Otherwise, we find the single use by finding an insn that has a
644 : : LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
645 : : only referenced once in that insn, we know that it must be the first
646 : : and last insn referencing DEST. */
647 : :
648 : : static rtx *
649 : 7148443 : find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
650 : : {
651 : 7148443 : basic_block bb;
652 : 7148443 : rtx_insn *next;
653 : 7148443 : rtx *result;
654 : 7148443 : struct insn_link *link;
655 : :
656 : 7148443 : if (!REG_P (dest))
657 : : return 0;
658 : :
659 : 7148443 : bb = BLOCK_FOR_INSN (insn);
660 : 9382839 : for (next = NEXT_INSN (insn);
661 : 9382839 : next && BLOCK_FOR_INSN (next) == bb;
662 : 2234396 : next = NEXT_INSN (next))
663 : 8857198 : if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
664 : : {
665 : 8525084 : FOR_EACH_LOG_LINK (link, next)
666 : 7683606 : if (link->insn == insn && link->regno == REGNO (dest))
667 : : break;
668 : :
669 : 7464280 : if (link)
670 : : {
671 : 6622802 : result = find_single_use_1 (dest, &PATTERN (next));
672 : 6622802 : if (ploc)
673 : 6622802 : *ploc = next;
674 : 6622802 : return result;
675 : : }
676 : : }
677 : :
678 : : return 0;
679 : : }
680 : :
681 : : /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 : : insn. The substitution can be undone by undo_all. If INTO is already
683 : : set to NEWVAL, do not record this change. Because computing NEWVAL might
684 : : also call SUBST, we have to compute it before we put anything into
685 : : the undo table. */
686 : :
687 : : static void
688 : 817336277 : do_SUBST (rtx *into, rtx newval)
689 : : {
690 : 817336277 : struct undo *buf;
691 : 817336277 : rtx oldval = *into;
692 : :
693 : 817336277 : if (oldval == newval)
694 : : return;
695 : :
696 : : /* We'd like to catch as many invalid transformations here as
697 : : possible. Unfortunately, there are way too many mode changes
698 : : that are perfectly valid, so we'd waste too much effort for
699 : : little gain doing the checks here. Focus on catching invalid
700 : : transformations involving integer constants. */
701 : 93684368 : if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 : 58515811 : && CONST_INT_P (newval))
703 : : {
704 : : /* Sanity check that we're replacing oldval with a CONST_INT
705 : : that is a valid sign-extension for the original mode. */
706 : 1922759 : gcc_assert (INTVAL (newval)
707 : : == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 : :
709 : : /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 : : CONST_INT is not valid, because after the replacement, the
711 : : original mode would be gone. Unfortunately, we can't tell
712 : : when do_SUBST is called to replace the operand thereof, so we
713 : : perform this test on oldval instead, checking whether an
714 : : invalid replacement took place before we got here. */
715 : 1922759 : gcc_assert (!(GET_CODE (oldval) == SUBREG
716 : : && CONST_INT_P (SUBREG_REG (oldval))));
717 : 1922759 : gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 : : && CONST_INT_P (XEXP (oldval, 0))));
719 : : }
720 : :
721 : 93684368 : if (undobuf.frees)
722 : 89726153 : buf = undobuf.frees, undobuf.frees = buf->next;
723 : : else
724 : 3958215 : buf = XNEW (struct undo);
725 : :
726 : 93684368 : buf->kind = UNDO_RTX;
727 : 93684368 : buf->where.r = into;
728 : 93684368 : buf->old_contents.r = oldval;
729 : 93684368 : *into = newval;
730 : :
731 : 93684368 : buf->next = undobuf.undos, undobuf.undos = buf;
732 : : }
733 : :
734 : : #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
735 : :
736 : : /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 : : for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 : : not safe. */
739 : :
740 : : static void
741 : 15755626 : do_SUBST_INT (int *into, int newval)
742 : : {
743 : 15755626 : struct undo *buf;
744 : 15755626 : int oldval = *into;
745 : :
746 : 15755626 : if (oldval == newval)
747 : : return;
748 : :
749 : 7118600 : if (undobuf.frees)
750 : 6594078 : buf = undobuf.frees, undobuf.frees = buf->next;
751 : : else
752 : 524522 : buf = XNEW (struct undo);
753 : :
754 : 7118600 : buf->kind = UNDO_INT;
755 : 7118600 : buf->where.i = into;
756 : 7118600 : buf->old_contents.i = oldval;
757 : 7118600 : *into = newval;
758 : :
759 : 7118600 : buf->next = undobuf.undos, undobuf.undos = buf;
760 : : }
761 : :
762 : : #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
763 : :
764 : : /* Similar to SUBST, but just substitute the mode. This is used when
765 : : changing the mode of a pseudo-register, so that any other
766 : : references to the entry in the regno_reg_rtx array will change as
767 : : well. */
768 : :
769 : : static void
770 : 1458481 : subst_mode (int regno, machine_mode newval)
771 : : {
772 : 1458481 : struct undo *buf;
773 : 1458481 : rtx reg = regno_reg_rtx[regno];
774 : 1458481 : machine_mode oldval = GET_MODE (reg);
775 : :
776 : 1458481 : if (oldval == newval)
777 : : return;
778 : :
779 : 1458481 : if (undobuf.frees)
780 : 1383043 : buf = undobuf.frees, undobuf.frees = buf->next;
781 : : else
782 : 75438 : buf = XNEW (struct undo);
783 : :
784 : 1458481 : buf->kind = UNDO_MODE;
785 : 1458481 : buf->where.regno = regno;
786 : 1458481 : buf->old_contents.m = oldval;
787 : 1458481 : adjust_reg_mode (reg, newval);
788 : :
789 : 1458481 : buf->next = undobuf.undos, undobuf.undos = buf;
790 : : }
791 : :
792 : : /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
793 : :
794 : : static void
795 : 69795 : do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
796 : : {
797 : 69795 : struct undo *buf;
798 : 69795 : struct insn_link * oldval = *into;
799 : :
800 : 69795 : if (oldval == newval)
801 : : return;
802 : :
803 : 69795 : if (undobuf.frees)
804 : 66951 : buf = undobuf.frees, undobuf.frees = buf->next;
805 : : else
806 : 2844 : buf = XNEW (struct undo);
807 : :
808 : 69795 : buf->kind = UNDO_LINKS;
809 : 69795 : buf->where.l = into;
810 : 69795 : buf->old_contents.l = oldval;
811 : 69795 : *into = newval;
812 : :
813 : 69795 : buf->next = undobuf.undos, undobuf.undos = buf;
814 : : }
815 : :
816 : : #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
817 : :
818 : : /* Subroutine of try_combine. Determine whether the replacement patterns
819 : : NEWPAT, NEWI2PAT and NEWOTHERPAT are more expensive according to insn_cost
820 : : than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
821 : : that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
822 : : undobuf.other_insn may also both be NULL_RTX. Return false if the cost
823 : : of all the instructions can be estimated and the replacements are more
824 : : expensive than the original sequence. */
825 : :
826 : : static bool
827 : 4073067 : combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
828 : : rtx newpat, rtx newi2pat, rtx newotherpat)
829 : : {
830 : 4073067 : int i0_cost, i1_cost, i2_cost, i3_cost;
831 : 4073067 : int new_i2_cost, new_i3_cost;
832 : 4073067 : int old_cost, new_cost;
833 : :
834 : : /* Lookup the original insn_costs. */
835 : 4073067 : i2_cost = INSN_COST (i2);
836 : 4073067 : i3_cost = INSN_COST (i3);
837 : :
838 : 4073067 : if (i1)
839 : : {
840 : 118387 : i1_cost = INSN_COST (i1);
841 : 118387 : if (i0)
842 : : {
843 : 6602 : i0_cost = INSN_COST (i0);
844 : 6482 : old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
845 : 13072 : ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
846 : : }
847 : : else
848 : : {
849 : 106149 : old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
850 : 217932 : ? i1_cost + i2_cost + i3_cost : 0);
851 : : i0_cost = 0;
852 : : }
853 : : }
854 : : else
855 : : {
856 : 3954680 : old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
857 : : i1_cost = i0_cost = 0;
858 : : }
859 : :
860 : : /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
861 : : correct that. */
862 : 4073067 : if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
863 : 1375 : old_cost -= i1_cost;
864 : :
865 : :
866 : : /* Calculate the replacement insn_costs. */
867 : 4073067 : rtx tmp = PATTERN (i3);
868 : 4073067 : PATTERN (i3) = newpat;
869 : 4073067 : int tmpi = INSN_CODE (i3);
870 : 4073067 : INSN_CODE (i3) = -1;
871 : 4073067 : new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
872 : 4073067 : PATTERN (i3) = tmp;
873 : 4073067 : INSN_CODE (i3) = tmpi;
874 : 4073067 : if (newi2pat)
875 : : {
876 : 219253 : tmp = PATTERN (i2);
877 : 219253 : PATTERN (i2) = newi2pat;
878 : 219253 : tmpi = INSN_CODE (i2);
879 : 219253 : INSN_CODE (i2) = -1;
880 : 219253 : new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
881 : 219253 : PATTERN (i2) = tmp;
882 : 219253 : INSN_CODE (i2) = tmpi;
883 : 219253 : new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
884 : 219253 : ? new_i2_cost + new_i3_cost : 0;
885 : : }
886 : : else
887 : : {
888 : : new_cost = new_i3_cost;
889 : : new_i2_cost = 0;
890 : : }
891 : :
892 : 4073067 : if (undobuf.other_insn)
893 : : {
894 : 209084 : int old_other_cost, new_other_cost;
895 : :
896 : 209084 : old_other_cost = INSN_COST (undobuf.other_insn);
897 : 209084 : tmp = PATTERN (undobuf.other_insn);
898 : 209084 : PATTERN (undobuf.other_insn) = newotherpat;
899 : 209084 : tmpi = INSN_CODE (undobuf.other_insn);
900 : 209084 : INSN_CODE (undobuf.other_insn) = -1;
901 : 209084 : new_other_cost = insn_cost (undobuf.other_insn,
902 : : optimize_this_for_speed_p);
903 : 209084 : PATTERN (undobuf.other_insn) = tmp;
904 : 209084 : INSN_CODE (undobuf.other_insn) = tmpi;
905 : 209084 : if (old_other_cost > 0 && new_other_cost > 0)
906 : : {
907 : 209084 : old_cost += old_other_cost;
908 : 209084 : new_cost += new_other_cost;
909 : : }
910 : : else
911 : : old_cost = 0;
912 : : }
913 : :
914 : : /* Disallow this combination if both new_cost and old_cost are greater than
915 : : zero, and new_cost is greater than old cost. */
916 : 4073067 : bool reject = old_cost > 0 && new_cost > old_cost;
917 : :
918 : 4073067 : if (dump_file)
919 : : {
920 : 488 : fprintf (dump_file, "%s combination of insns ",
921 : : reject ? "rejecting" : "allowing");
922 : 246 : if (i0)
923 : 0 : fprintf (dump_file, "%d, ", INSN_UID (i0));
924 : 246 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
925 : 1 : fprintf (dump_file, "%d, ", INSN_UID (i1));
926 : 246 : fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
927 : :
928 : 246 : fprintf (dump_file, "original costs ");
929 : 246 : if (i0)
930 : 0 : fprintf (dump_file, "%d + ", i0_cost);
931 : 246 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
932 : 1 : fprintf (dump_file, "%d + ", i1_cost);
933 : 246 : fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
934 : :
935 : 246 : if (newi2pat)
936 : 19 : fprintf (dump_file, "replacement costs %d + %d = %d\n",
937 : : new_i2_cost, new_i3_cost, new_cost);
938 : : else
939 : 227 : fprintf (dump_file, "replacement cost %d\n", new_cost);
940 : : }
941 : :
942 : 4073067 : if (reject)
943 : : return false;
944 : :
945 : : /* Update the uid_insn_cost array with the replacement costs. */
946 : 3860596 : INSN_COST (i2) = new_i2_cost;
947 : 3860596 : INSN_COST (i3) = new_i3_cost;
948 : 3860596 : if (i1)
949 : : {
950 : 99452 : INSN_COST (i1) = 0;
951 : 99452 : if (i0)
952 : 6482 : INSN_COST (i0) = 0;
953 : : }
954 : :
955 : : return true;
956 : : }
957 : :
958 : :
959 : : /* Delete any insns that copy a register to itself.
960 : : Return true if the CFG was changed. */
961 : :
962 : : static bool
963 : 980420 : delete_noop_moves (void)
964 : : {
965 : 980420 : rtx_insn *insn, *next;
966 : 980420 : basic_block bb;
967 : :
968 : 980420 : bool edges_deleted = false;
969 : :
970 : 11217574 : FOR_EACH_BB_FN (bb, cfun)
971 : : {
972 : 135245871 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
973 : : {
974 : 125008717 : next = NEXT_INSN (insn);
975 : 125008717 : if (INSN_P (insn) && noop_move_p (insn))
976 : : {
977 : 6766 : if (dump_file)
978 : 0 : fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
979 : :
980 : 6766 : edges_deleted |= delete_insn_and_edges (insn);
981 : : }
982 : : }
983 : : }
984 : :
985 : 980420 : return edges_deleted;
986 : : }
987 : :
988 : :
989 : : /* Return false if we do not want to (or cannot) combine DEF. */
990 : : static bool
991 : 41737130 : can_combine_def_p (df_ref def)
992 : : {
993 : : /* Do not consider if it is pre/post modification in MEM. */
994 : 41737130 : if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
995 : : return false;
996 : :
997 : 40098931 : unsigned int regno = DF_REF_REGNO (def);
998 : :
999 : : /* Do not combine frame pointer adjustments. */
1000 : 40098931 : if ((regno == FRAME_POINTER_REGNUM
1001 : 0 : && (!reload_completed || frame_pointer_needed))
1002 : 2062 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1003 : 40098931 : && regno == HARD_FRAME_POINTER_REGNUM
1004 : : && (!reload_completed || frame_pointer_needed))
1005 : 40096869 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1006 : 0 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1007 : 2062 : return false;
1008 : :
1009 : : return true;
1010 : : }
1011 : :
1012 : : /* Return false if we do not want to (or cannot) combine USE. */
1013 : : static bool
1014 : 76077516 : can_combine_use_p (df_ref use)
1015 : : {
1016 : : /* Do not consider the usage of the stack pointer by function call. */
1017 : 0 : if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1018 : 0 : return false;
1019 : :
1020 : : return true;
1021 : : }
1022 : :
1023 : : /* Fill in log links field for all insns. */
1024 : :
1025 : : static void
1026 : 980420 : create_log_links (void)
1027 : : {
1028 : 980420 : basic_block bb;
1029 : 980420 : rtx_insn **next_use;
1030 : 980420 : rtx_insn *insn;
1031 : 980420 : df_ref def, use;
1032 : :
1033 : 980420 : next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1034 : :
1035 : : /* Pass through each block from the end, recording the uses of each
1036 : : register and establishing log links when def is encountered.
1037 : : Note that we do not clear next_use array in order to save time,
1038 : : so we have to test whether the use is in the same basic block as def.
1039 : :
1040 : : There are a few cases below when we do not consider the definition or
1041 : : usage -- these are taken from original flow.c did. Don't ask me why it is
1042 : : done this way; I don't know and if it works, I don't want to know. */
1043 : :
1044 : 11217574 : FOR_EACH_BB_FN (bb, cfun)
1045 : : {
1046 : 135228780 : FOR_BB_INSNS_REVERSE (bb, insn)
1047 : : {
1048 : 124991626 : if (!NONDEBUG_INSN_P (insn))
1049 : 63657619 : continue;
1050 : :
1051 : : /* Log links are created only once. */
1052 : 61334007 : gcc_assert (!LOG_LINKS (insn));
1053 : :
1054 : 494739495 : FOR_EACH_INSN_DEF (def, insn)
1055 : : {
1056 : 433405488 : unsigned int regno = DF_REF_REGNO (def);
1057 : 433405488 : rtx_insn *use_insn;
1058 : :
1059 : 433405488 : if (!next_use[regno])
1060 : 391668358 : continue;
1061 : :
1062 : 41737130 : if (!can_combine_def_p (def))
1063 : 1640261 : continue;
1064 : :
1065 : 40096869 : use_insn = next_use[regno];
1066 : 40096869 : next_use[regno] = NULL;
1067 : :
1068 : 40096869 : if (BLOCK_FOR_INSN (use_insn) != bb)
1069 : 2249192 : continue;
1070 : :
1071 : : /* flow.c claimed:
1072 : :
1073 : : We don't build a LOG_LINK for hard registers contained
1074 : : in ASM_OPERANDs. If these registers get replaced,
1075 : : we might wind up changing the semantics of the insn,
1076 : : even if reload can make what appear to be valid
1077 : : assignments later. */
1078 : 37848529 : if (regno < FIRST_PSEUDO_REGISTER
1079 : 37847677 : && asm_noperands (PATTERN (use_insn)) >= 0)
1080 : 852 : continue;
1081 : :
1082 : : /* Don't add duplicate links between instructions. */
1083 : 37846825 : struct insn_link *links;
1084 : 51020220 : FOR_EACH_LOG_LINK (links, use_insn)
1085 : 13173395 : if (insn == links->insn && regno == links->regno)
1086 : : break;
1087 : :
1088 : 37846825 : if (!links)
1089 : 37846825 : LOG_LINKS (use_insn)
1090 : 75693650 : = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1091 : : }
1092 : :
1093 : 137411523 : FOR_EACH_INSN_USE (use, insn)
1094 : 147503284 : if (can_combine_use_p (use))
1095 : 71425768 : next_use[DF_REF_REGNO (use)] = insn;
1096 : : }
1097 : : }
1098 : :
1099 : 980420 : free (next_use);
1100 : 980420 : }
1101 : :
1102 : : /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1103 : : true if we found a LOG_LINK that proves that A feeds B. This only works
1104 : : if there are no instructions between A and B which could have a link
1105 : : depending on A, since in that case we would not record a link for B. */
1106 : :
1107 : : static bool
1108 : 12296906 : insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1109 : : {
1110 : 12296906 : struct insn_link *links;
1111 : 15498677 : FOR_EACH_LOG_LINK (links, b)
1112 : 13033696 : if (links->insn == a)
1113 : : return true;
1114 : : return false;
1115 : : }
1116 : :
1117 : : /* Main entry point for combiner. F is the first insn of the function.
1118 : : NREGS is the first unused pseudo-reg number.
1119 : :
1120 : : Return nonzero if the CFG was changed (e.g. if the combiner has
1121 : : turned an indirect jump instruction into a direct jump). */
1122 : : static bool
1123 : 1023804 : combine_instructions (rtx_insn *f, unsigned int nregs)
1124 : : {
1125 : 1023804 : rtx_insn *insn, *next;
1126 : 1023804 : struct insn_link *links, *nextlinks;
1127 : 1023804 : rtx_insn *first;
1128 : 1023804 : basic_block last_bb;
1129 : :
1130 : 1023804 : bool new_direct_jump_p = false;
1131 : :
1132 : 3064476 : for (first = f; first && !NONDEBUG_INSN_P (first); )
1133 : 2040672 : first = NEXT_INSN (first);
1134 : 1023804 : if (!first)
1135 : : return false;
1136 : :
1137 : 980420 : combine_attempts = 0;
1138 : 980420 : combine_merges = 0;
1139 : 980420 : combine_extras = 0;
1140 : 980420 : combine_successes = 0;
1141 : :
1142 : 980420 : rtl_hooks = combine_rtl_hooks;
1143 : :
1144 : 980420 : reg_stat.safe_grow_cleared (nregs, true);
1145 : :
1146 : 980420 : init_recog_no_volatile ();
1147 : :
1148 : : /* Allocate array for insn info. */
1149 : 980420 : max_uid_known = get_max_uid ();
1150 : 980420 : uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1151 : 980420 : uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1152 : 980420 : gcc_obstack_init (&insn_link_obstack);
1153 : :
1154 : 980420 : nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1155 : :
1156 : : /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1157 : : problems when, for example, we have j <<= 1 in a loop. */
1158 : :
1159 : 980420 : nonzero_sign_valid = 0;
1160 : 980420 : label_tick = label_tick_ebb_start = 1;
1161 : :
1162 : : /* Scan all SETs and see if we can deduce anything about what
1163 : : bits are known to be zero for some registers and how many copies
1164 : : of the sign bit are known to exist for those registers.
1165 : :
1166 : : Also set any known values so that we can use it while searching
1167 : : for what bits are known to be set. */
1168 : :
1169 : 980420 : setup_incoming_promotions (first);
1170 : : /* Allow the entry block and the first block to fall into the same EBB.
1171 : : Conceptually the incoming promotions are assigned to the entry block. */
1172 : 980420 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1173 : :
1174 : 980420 : create_log_links ();
1175 : 11217574 : FOR_EACH_BB_FN (this_basic_block, cfun)
1176 : : {
1177 : 10237154 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1178 : 10237154 : last_call_luid = 0;
1179 : 10237154 : mem_last_set = -1;
1180 : :
1181 : 10237154 : label_tick++;
1182 : 10237154 : if (!single_pred_p (this_basic_block)
1183 : 10237154 : || single_pred (this_basic_block) != last_bb)
1184 : 4961645 : label_tick_ebb_start = label_tick;
1185 : 10237154 : last_bb = this_basic_block;
1186 : :
1187 : 135228780 : FOR_BB_INSNS (this_basic_block, insn)
1188 : 124991626 : if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1189 : : {
1190 : 108731652 : rtx links;
1191 : :
1192 : 108731652 : subst_low_luid = DF_INSN_LUID (insn);
1193 : 108731652 : subst_insn = insn;
1194 : :
1195 : 108731652 : note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1196 : 108731652 : record_dead_and_set_regs (insn);
1197 : :
1198 : 108731652 : if (AUTO_INC_DEC)
1199 : : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1200 : : if (REG_NOTE_KIND (links) == REG_INC)
1201 : : set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1202 : : insn);
1203 : :
1204 : : /* Record the current insn_cost of this instruction. */
1205 : 108731652 : INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1206 : 108731652 : if (dump_file)
1207 : : {
1208 : 1709 : fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1209 : 1709 : dump_insn_slim (dump_file, insn);
1210 : : }
1211 : : }
1212 : : }
1213 : :
1214 : 980420 : nonzero_sign_valid = 1;
1215 : :
1216 : : /* Now scan all the insns in forward order. */
1217 : 980420 : label_tick = label_tick_ebb_start = 1;
1218 : 980420 : init_reg_last ();
1219 : 980420 : setup_incoming_promotions (first);
1220 : 980420 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1221 : 980420 : int max_combine = param_max_combine_insns;
1222 : :
1223 : 11217574 : FOR_EACH_BB_FN (this_basic_block, cfun)
1224 : : {
1225 : 10237154 : rtx_insn *last_combined_insn = NULL;
1226 : :
1227 : : /* Ignore instruction combination in basic blocks that are going to
1228 : : be removed as unreachable anyway. See PR82386. */
1229 : 10237154 : if (EDGE_COUNT (this_basic_block->preds) == 0)
1230 : 1951 : continue;
1231 : :
1232 : 10235203 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1233 : 10235203 : last_call_luid = 0;
1234 : 10235203 : mem_last_set = -1;
1235 : :
1236 : 10235203 : label_tick++;
1237 : 10235203 : if (!single_pred_p (this_basic_block)
1238 : 10235203 : || single_pred (this_basic_block) != last_bb)
1239 : 4961430 : label_tick_ebb_start = label_tick;
1240 : 10235203 : last_bb = this_basic_block;
1241 : :
1242 : 10235203 : rtl_profile_for_bb (this_basic_block);
1243 : 10235203 : for (insn = BB_HEAD (this_basic_block);
1244 : 139598417 : insn != NEXT_INSN (BB_END (this_basic_block));
1245 : 125502618 : insn = next ? next : NEXT_INSN (insn))
1246 : : {
1247 : 129363214 : next = 0;
1248 : 129363214 : if (!NONDEBUG_INSN_P (insn))
1249 : 63883086 : continue;
1250 : :
1251 : : while (last_combined_insn
1252 : 65482095 : && (!NONDEBUG_INSN_P (last_combined_insn)
1253 : 55425643 : || last_combined_insn->deleted ()))
1254 : 1967 : last_combined_insn = PREV_INSN (last_combined_insn);
1255 : 65480128 : if (last_combined_insn == NULL_RTX
1256 : 55425066 : || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1257 : 120904994 : || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1258 : : last_combined_insn = insn;
1259 : :
1260 : : /* See if we know about function return values before this
1261 : : insn based upon SUBREG flags. */
1262 : 65480128 : check_promoted_subreg (insn, PATTERN (insn));
1263 : :
1264 : : /* See if we can find hardregs and subreg of pseudos in
1265 : : narrower modes. This could help turning TRUNCATEs
1266 : : into SUBREGs. */
1267 : 65480128 : note_uses (&PATTERN (insn), record_truncated_values, NULL);
1268 : :
1269 : : /* Try this insn with each insn it links back to. */
1270 : :
1271 : 102503276 : FOR_EACH_LOG_LINK (links, insn)
1272 : 40757681 : if ((next = try_combine (insn, links->insn, NULL,
1273 : : NULL, &new_direct_jump_p,
1274 : : last_combined_insn)) != 0)
1275 : : {
1276 : 3734533 : statistics_counter_event (cfun, "two-insn combine", 1);
1277 : 3734533 : goto retry;
1278 : : }
1279 : :
1280 : : /* Try each sequence of three linked insns ending with this one. */
1281 : :
1282 : 61745595 : if (max_combine >= 3)
1283 : 98206121 : FOR_EACH_LOG_LINK (links, insn)
1284 : : {
1285 : 36643285 : rtx_insn *link = links->insn;
1286 : :
1287 : : /* If the linked insn has been replaced by a note, then there
1288 : : is no point in pursuing this chain any further. */
1289 : 36643285 : if (NOTE_P (link))
1290 : 233 : continue;
1291 : :
1292 : 54776518 : FOR_EACH_LOG_LINK (nextlinks, link)
1293 : 18209623 : if ((next = try_combine (insn, link, nextlinks->insn,
1294 : : NULL, &new_direct_jump_p,
1295 : : last_combined_insn)) != 0)
1296 : : {
1297 : 76157 : statistics_counter_event (cfun, "three-insn combine", 1);
1298 : 76157 : goto retry;
1299 : : }
1300 : : }
1301 : :
1302 : : /* Try combining an insn with two different insns whose results it
1303 : : uses. */
1304 : 61562836 : if (max_combine >= 3)
1305 : 98095542 : FOR_EACH_LOG_LINK (links, insn)
1306 : 49465796 : for (nextlinks = links->next; nextlinks;
1307 : 12918860 : nextlinks = nextlinks->next)
1308 : 12933090 : if ((next = try_combine (insn, links->insn,
1309 : : nextlinks->insn, NULL,
1310 : : &new_direct_jump_p,
1311 : : last_combined_insn)) != 0)
1312 : :
1313 : : {
1314 : 14230 : statistics_counter_event (cfun, "three-insn combine", 1);
1315 : 14230 : goto retry;
1316 : : }
1317 : :
1318 : : /* Try four-instruction combinations. */
1319 : 61548606 : if (max_combine >= 4)
1320 : 98069616 : FOR_EACH_LOG_LINK (links, insn)
1321 : : {
1322 : 36527449 : struct insn_link *next1;
1323 : 36527449 : rtx_insn *link = links->insn;
1324 : :
1325 : : /* If the linked insn has been replaced by a note, then there
1326 : : is no point in pursuing this chain any further. */
1327 : 36527449 : if (NOTE_P (link))
1328 : 233 : continue;
1329 : :
1330 : 54639551 : FOR_EACH_LOG_LINK (next1, link)
1331 : : {
1332 : 18113622 : rtx_insn *link1 = next1->insn;
1333 : 18113622 : if (NOTE_P (link1))
1334 : 72 : continue;
1335 : : /* I0 -> I1 -> I2 -> I3. */
1336 : 29756630 : FOR_EACH_LOG_LINK (nextlinks, link1)
1337 : 11644164 : if ((next = try_combine (insn, link, link1,
1338 : : nextlinks->insn,
1339 : : &new_direct_jump_p,
1340 : : last_combined_insn)) != 0)
1341 : : {
1342 : 1084 : statistics_counter_event (cfun, "four-insn combine", 1);
1343 : 1084 : goto retry;
1344 : : }
1345 : : /* I0, I1 -> I2, I2 -> I3. */
1346 : 22317434 : for (nextlinks = next1->next; nextlinks;
1347 : 4204968 : nextlinks = nextlinks->next)
1348 : 4205171 : if ((next = try_combine (insn, link, link1,
1349 : : nextlinks->insn,
1350 : : &new_direct_jump_p,
1351 : : last_combined_insn)) != 0)
1352 : : {
1353 : 203 : statistics_counter_event (cfun, "four-insn combine", 1);
1354 : 203 : goto retry;
1355 : : }
1356 : : }
1357 : :
1358 : 49439331 : for (next1 = links->next; next1; next1 = next1->next)
1359 : : {
1360 : 12918475 : rtx_insn *link1 = next1->insn;
1361 : 12918475 : if (NOTE_P (link1))
1362 : 8 : continue;
1363 : : /* I0 -> I2; I1, I2 -> I3. */
1364 : 16303606 : FOR_EACH_LOG_LINK (nextlinks, link)
1365 : 3390030 : if ((next = try_combine (insn, link, link1,
1366 : : nextlinks->insn,
1367 : : &new_direct_jump_p,
1368 : : last_combined_insn)) != 0)
1369 : : {
1370 : 4891 : statistics_counter_event (cfun, "four-insn combine", 1);
1371 : 4891 : goto retry;
1372 : : }
1373 : : /* I0 -> I1; I1, I2 -> I3. */
1374 : 16490610 : FOR_EACH_LOG_LINK (nextlinks, link1)
1375 : 3577216 : if ((next = try_combine (insn, link, link1,
1376 : : nextlinks->insn,
1377 : : &new_direct_jump_p,
1378 : : last_combined_insn)) != 0)
1379 : : {
1380 : 182 : statistics_counter_event (cfun, "four-insn combine", 1);
1381 : 182 : goto retry;
1382 : : }
1383 : : }
1384 : : }
1385 : :
1386 : : /* Try this insn with each REG_EQUAL note it links back to. */
1387 : 98202939 : FOR_EACH_LOG_LINK (links, insn)
1388 : : {
1389 : 36583407 : rtx set, note;
1390 : 36583407 : rtx_insn *temp = links->insn;
1391 : 36583407 : if ((set = single_set (temp)) != 0
1392 : 36194845 : && (note = find_reg_equal_equiv_note (temp)) != 0
1393 : 2593631 : && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1394 : 2593631 : && ! side_effects_p (SET_SRC (set))
1395 : : /* Avoid using a register that may already been marked
1396 : : dead by an earlier instruction. */
1397 : 2593631 : && ! unmentioned_reg_p (note, SET_SRC (set))
1398 : 37804708 : && (GET_MODE (note) == VOIDmode
1399 : 25946 : ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1400 : 1195355 : : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1401 : 1195328 : && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1402 : 0 : || (GET_MODE (XEXP (SET_DEST (set), 0))
1403 : : == GET_MODE (note))))))
1404 : : {
1405 : : /* Temporarily replace the set's source with the
1406 : : contents of the REG_EQUAL note. The insn will
1407 : : be deleted or recognized by try_combine. */
1408 : 1221257 : rtx orig_src = SET_SRC (set);
1409 : 1221257 : rtx orig_dest = SET_DEST (set);
1410 : 1221257 : if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1411 : 0 : SET_DEST (set) = XEXP (SET_DEST (set), 0);
1412 : 1221257 : SET_SRC (set) = note;
1413 : 1221257 : i2mod = temp;
1414 : 1221257 : i2mod_old_rhs = copy_rtx (orig_src);
1415 : 1221257 : i2mod_new_rhs = copy_rtx (note);
1416 : 1221257 : next = try_combine (insn, i2mod, NULL, NULL,
1417 : : &new_direct_jump_p,
1418 : : last_combined_insn);
1419 : 1221257 : i2mod = NULL;
1420 : 1221257 : if (next)
1421 : : {
1422 : 29316 : statistics_counter_event (cfun, "insn-with-note combine", 1);
1423 : 29316 : goto retry;
1424 : : }
1425 : 1191941 : INSN_CODE (temp) = -1;
1426 : 1191941 : SET_SRC (set) = orig_src;
1427 : 1191941 : SET_DEST (set) = orig_dest;
1428 : : }
1429 : : }
1430 : :
1431 : 61619532 : if (!NOTE_P (insn))
1432 : 61619532 : record_dead_and_set_regs (insn);
1433 : :
1434 : 129363214 : retry:
1435 : 129363214 : ;
1436 : : }
1437 : : }
1438 : :
1439 : 980420 : default_rtl_profile ();
1440 : 980420 : clear_bb_flags ();
1441 : :
1442 : 980420 : if (purge_all_dead_edges ())
1443 : 1419 : new_direct_jump_p = true;
1444 : 980420 : if (delete_noop_moves ())
1445 : 0 : new_direct_jump_p = true;
1446 : :
1447 : : /* Clean up. */
1448 : 980420 : obstack_free (&insn_link_obstack, NULL);
1449 : 980420 : free (uid_log_links);
1450 : 980420 : free (uid_insn_cost);
1451 : 980420 : reg_stat.release ();
1452 : :
1453 : 980420 : {
1454 : 980420 : struct undo *undo, *next;
1455 : 5541439 : for (undo = undobuf.frees; undo; undo = next)
1456 : : {
1457 : 4561019 : next = undo->next;
1458 : 4561019 : free (undo);
1459 : : }
1460 : 980420 : undobuf.frees = 0;
1461 : : }
1462 : :
1463 : 980420 : statistics_counter_event (cfun, "attempts", combine_attempts);
1464 : 980420 : statistics_counter_event (cfun, "merges", combine_merges);
1465 : 980420 : statistics_counter_event (cfun, "extras", combine_extras);
1466 : 980420 : statistics_counter_event (cfun, "successes", combine_successes);
1467 : :
1468 : 980420 : nonzero_sign_valid = 0;
1469 : 980420 : rtl_hooks = general_rtl_hooks;
1470 : :
1471 : : /* Make recognizer allow volatile MEMs again. */
1472 : 980420 : init_recog ();
1473 : :
1474 : 980420 : return new_direct_jump_p;
1475 : : }
1476 : :
1477 : : /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1478 : :
1479 : : static void
1480 : 980420 : init_reg_last (void)
1481 : : {
1482 : 980420 : unsigned int i;
1483 : 980420 : reg_stat_type *p;
1484 : :
1485 : 139908922 : FOR_EACH_VEC_ELT (reg_stat, i, p)
1486 : 138928502 : memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1487 : 980420 : }
1488 : :
1489 : : /* Set up any promoted values for incoming argument registers. */
1490 : :
1491 : : static void
1492 : 1960840 : setup_incoming_promotions (rtx_insn *first)
1493 : : {
1494 : 1960840 : tree arg;
1495 : 1960840 : bool strictly_local = false;
1496 : :
1497 : 5341898 : for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1498 : 3381058 : arg = DECL_CHAIN (arg))
1499 : : {
1500 : 3381058 : rtx x, reg = DECL_INCOMING_RTL (arg);
1501 : 3381058 : int uns1, uns3;
1502 : 3381058 : machine_mode mode1, mode2, mode3, mode4;
1503 : :
1504 : : /* Only continue if the incoming argument is in a register. */
1505 : 3381058 : if (!REG_P (reg))
1506 : 3380980 : continue;
1507 : :
1508 : : /* Determine, if possible, whether all call sites of the current
1509 : : function lie within the current compilation unit. (This does
1510 : : take into account the exporting of a function via taking its
1511 : : address, and so forth.) */
1512 : 2652926 : strictly_local
1513 : 2652926 : = cgraph_node::local_info_node (current_function_decl)->local;
1514 : :
1515 : : /* The mode and signedness of the argument before any promotions happen
1516 : : (equal to the mode of the pseudo holding it at that stage). */
1517 : 2652926 : mode1 = TYPE_MODE (TREE_TYPE (arg));
1518 : 2652926 : uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1519 : :
1520 : : /* The mode and signedness of the argument after any source language and
1521 : : TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1522 : 2652926 : mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1523 : 2652926 : uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1524 : :
1525 : : /* The mode and signedness of the argument as it is actually passed,
1526 : : see assign_parm_setup_reg in function.cc. */
1527 : 2652926 : mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1528 : 2652926 : TREE_TYPE (cfun->decl), 0);
1529 : :
1530 : : /* The mode of the register in which the argument is being passed. */
1531 : 2652926 : mode4 = GET_MODE (reg);
1532 : :
1533 : : /* Eliminate sign extensions in the callee when:
1534 : : (a) A mode promotion has occurred; */
1535 : 2652926 : if (mode1 == mode3)
1536 : 2652848 : continue;
1537 : : /* (b) The mode of the register is the same as the mode of
1538 : : the argument as it is passed; */
1539 : 78 : if (mode3 != mode4)
1540 : 0 : continue;
1541 : : /* (c) There's no language level extension; */
1542 : 78 : if (mode1 == mode2)
1543 : : ;
1544 : : /* (c.1) All callers are from the current compilation unit. If that's
1545 : : the case we don't have to rely on an ABI, we only have to know
1546 : : what we're generating right now, and we know that we will do the
1547 : : mode1 to mode2 promotion with the given sign. */
1548 : 0 : else if (!strictly_local)
1549 : 0 : continue;
1550 : : /* (c.2) The combination of the two promotions is useful. This is
1551 : : true when the signs match, or if the first promotion is unsigned.
1552 : : In the later case, (sign_extend (zero_extend x)) is the same as
1553 : : (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1554 : 0 : else if (uns1)
1555 : 0 : uns3 = true;
1556 : 0 : else if (uns3)
1557 : 0 : continue;
1558 : :
1559 : : /* Record that the value was promoted from mode1 to mode3,
1560 : : so that any sign extension at the head of the current
1561 : : function may be eliminated. */
1562 : 78 : x = gen_rtx_CLOBBER (mode1, const0_rtx);
1563 : 78 : x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1564 : 78 : record_value_for_reg (reg, first, x);
1565 : : }
1566 : 1960840 : }
1567 : :
1568 : : /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1569 : : that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1570 : : because some machines (maybe most) will actually do the sign-extension and
1571 : : this is the conservative approach.
1572 : :
1573 : : ??? For 2.5, try to tighten up the MD files in this regard instead of this
1574 : : kludge. */
1575 : :
1576 : : static rtx
1577 : 0 : sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1578 : : {
1579 : 0 : scalar_int_mode int_mode;
1580 : 0 : if (CONST_INT_P (src)
1581 : 0 : && is_a <scalar_int_mode> (mode, &int_mode)
1582 : 0 : && GET_MODE_PRECISION (int_mode) < prec
1583 : 0 : && INTVAL (src) > 0
1584 : 0 : && val_signbit_known_set_p (int_mode, INTVAL (src)))
1585 : 0 : src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1586 : :
1587 : 0 : return src;
1588 : : }
1589 : :
1590 : : /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1591 : : and SET. */
1592 : :
1593 : : static void
1594 : 23449629 : update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1595 : : rtx x)
1596 : : {
1597 : 23449629 : rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1598 : 23449629 : unsigned HOST_WIDE_INT bits = 0;
1599 : 23449629 : rtx reg_equal = NULL, src = SET_SRC (set);
1600 : 23449629 : unsigned int num = 0;
1601 : :
1602 : 23449629 : if (reg_equal_note)
1603 : 1017702 : reg_equal = XEXP (reg_equal_note, 0);
1604 : :
1605 : 23449629 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
1606 : : {
1607 : : src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1608 : : if (reg_equal)
1609 : : reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1610 : : }
1611 : :
1612 : : /* Don't call nonzero_bits if it cannot change anything. */
1613 : 23449629 : if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1614 : : {
1615 : 20352279 : machine_mode mode = GET_MODE (x);
1616 : 20352279 : if (GET_MODE_CLASS (mode) == MODE_INT
1617 : 20352279 : && HWI_COMPUTABLE_MODE_P (mode))
1618 : 20352147 : mode = nonzero_bits_mode;
1619 : 20352279 : bits = nonzero_bits (src, mode);
1620 : 20352279 : if (reg_equal && bits)
1621 : 966180 : bits &= nonzero_bits (reg_equal, mode);
1622 : 20352279 : rsp->nonzero_bits |= bits;
1623 : : }
1624 : :
1625 : : /* Don't call num_sign_bit_copies if it cannot change anything. */
1626 : 23449629 : if (rsp->sign_bit_copies != 1)
1627 : : {
1628 : 20190263 : num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1629 : 20190263 : if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1630 : : {
1631 : 962282 : unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1632 : 962282 : if (num == 0 || numeq > num)
1633 : 20190263 : num = numeq;
1634 : : }
1635 : 20190263 : if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1636 : 19421889 : rsp->sign_bit_copies = num;
1637 : : }
1638 : 23449629 : }
1639 : :
1640 : : /* Called via note_stores. If X is a pseudo that is narrower than
1641 : : HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1642 : :
1643 : : If we are setting only a portion of X and we can't figure out what
1644 : : portion, assume all bits will be used since we don't know what will
1645 : : be happening.
1646 : :
1647 : : Similarly, set how many bits of X are known to be copies of the sign bit
1648 : : at all locations in the function. This is the smallest number implied
1649 : : by any set of X. */
1650 : :
1651 : : static void
1652 : 71869205 : set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1653 : : {
1654 : 71869205 : rtx_insn *insn = (rtx_insn *) data;
1655 : 71869205 : scalar_int_mode mode;
1656 : :
1657 : 71869205 : if (REG_P (x)
1658 : 58167494 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1659 : : /* If this register is undefined at the start of the file, we can't
1660 : : say what its contents were. */
1661 : 57834480 : && ! REGNO_REG_SET_P
1662 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1663 : 28796463 : && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1664 : 96261351 : && HWI_COMPUTABLE_MODE_P (mode))
1665 : : {
1666 : 23657272 : reg_stat_type *rsp = ®_stat[REGNO (x)];
1667 : :
1668 : 23657272 : if (set == 0 || GET_CODE (set) == CLOBBER)
1669 : : {
1670 : 21812 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1671 : 21812 : rsp->sign_bit_copies = 1;
1672 : 21812 : return;
1673 : : }
1674 : :
1675 : : /* If this register is being initialized using itself, and the
1676 : : register is uninitialized in this basic block, and there are
1677 : : no LOG_LINKS which set the register, then part of the
1678 : : register is uninitialized. In that case we can't assume
1679 : : anything about the number of nonzero bits.
1680 : :
1681 : : ??? We could do better if we checked this in
1682 : : reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1683 : : could avoid making assumptions about the insn which initially
1684 : : sets the register, while still using the information in other
1685 : : insns. We would have to be careful to check every insn
1686 : : involved in the combination. */
1687 : :
1688 : 23635460 : if (insn
1689 : 22258631 : && reg_referenced_p (x, PATTERN (insn))
1690 : 26175292 : && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1691 : : REGNO (x)))
1692 : : {
1693 : 288623 : struct insn_link *link;
1694 : :
1695 : 448247 : FOR_EACH_LOG_LINK (link, insn)
1696 : 355986 : if (dead_or_set_p (link->insn, x))
1697 : : break;
1698 : 288623 : if (!link)
1699 : : {
1700 : 92261 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1701 : 92261 : rsp->sign_bit_copies = 1;
1702 : 92261 : return;
1703 : : }
1704 : : }
1705 : :
1706 : : /* If this is a complex assignment, see if we can convert it into a
1707 : : simple assignment. */
1708 : 23543199 : set = expand_field_assignment (set);
1709 : :
1710 : : /* If this is a simple assignment, or we have a paradoxical SUBREG,
1711 : : set what we know about X. */
1712 : :
1713 : 23543199 : if (SET_DEST (set) == x
1714 : 23543199 : || (paradoxical_subreg_p (SET_DEST (set))
1715 : 3152 : && SUBREG_REG (SET_DEST (set)) == x))
1716 : 23449629 : update_rsp_from_reg_equal (rsp, insn, set, x);
1717 : : else
1718 : : {
1719 : 93570 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1720 : 93570 : rsp->sign_bit_copies = 1;
1721 : : }
1722 : : }
1723 : : }
1724 : :
1725 : : /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1726 : : optionally insns that were previously combined into I3 or that will be
1727 : : combined into the merger of INSN and I3. The order is PRED, PRED2,
1728 : : INSN, SUCC, SUCC2, I3.
1729 : :
1730 : : Return false if the combination is not allowed for any reason.
1731 : :
1732 : : If the combination is allowed, *PDEST will be set to the single
1733 : : destination of INSN and *PSRC to the single source, and this function
1734 : : will return true. */
1735 : :
1736 : : static bool
1737 : 59730619 : can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1738 : : rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1739 : : rtx *pdest, rtx *psrc)
1740 : : {
1741 : 59730619 : int i;
1742 : 59730619 : const_rtx set = 0;
1743 : 59730619 : rtx src, dest;
1744 : 59730619 : rtx_insn *p;
1745 : 59730619 : rtx link;
1746 : 59730619 : bool all_adjacent = true;
1747 : 59730619 : bool (*is_volatile_p) (const_rtx);
1748 : :
1749 : 59730619 : if (succ)
1750 : : {
1751 : 13552370 : if (succ2)
1752 : : {
1753 : 1762814 : if (next_active_insn (succ2) != i3)
1754 : 181678 : all_adjacent = false;
1755 : 1762814 : if (next_active_insn (succ) != succ2)
1756 : 1911310 : all_adjacent = false;
1757 : : }
1758 : 11789556 : else if (next_active_insn (succ) != i3)
1759 : 1911310 : all_adjacent = false;
1760 : 13552370 : if (next_active_insn (insn) != succ)
1761 : 16899854 : all_adjacent = false;
1762 : : }
1763 : 46178249 : else if (next_active_insn (insn) != i3)
1764 : 16899854 : all_adjacent = false;
1765 : :
1766 : : /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1767 : : or a PARALLEL consisting of such a SET and CLOBBERs.
1768 : :
1769 : : If INSN has CLOBBER parallel parts, ignore them for our processing.
1770 : : By definition, these happen during the execution of the insn. When it
1771 : : is merged with another insn, all bets are off. If they are, in fact,
1772 : : needed and aren't also supplied in I3, they may be added by
1773 : : recog_for_combine. Otherwise, it won't match.
1774 : :
1775 : : We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1776 : : note.
1777 : :
1778 : : Get the source and destination of INSN. If more than one, can't
1779 : : combine. */
1780 : :
1781 : 59730619 : if (GET_CODE (PATTERN (insn)) == SET)
1782 : : set = PATTERN (insn);
1783 : 16255981 : else if (GET_CODE (PATTERN (insn)) == PARALLEL
1784 : 16255981 : && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1785 : : {
1786 : 48761448 : for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1787 : : {
1788 : 32982230 : rtx elt = XVECEXP (PATTERN (insn), 0, i);
1789 : :
1790 : 32982230 : switch (GET_CODE (elt))
1791 : : {
1792 : : /* This is important to combine floating point insns
1793 : : for the SH4 port. */
1794 : 112068 : case USE:
1795 : : /* Combining an isolated USE doesn't make sense.
1796 : : We depend here on combinable_i3pat to reject them. */
1797 : : /* The code below this loop only verifies that the inputs of
1798 : : the SET in INSN do not change. We call reg_set_between_p
1799 : : to verify that the REG in the USE does not change between
1800 : : I3 and INSN.
1801 : : If the USE in INSN was for a pseudo register, the matching
1802 : : insn pattern will likely match any register; combining this
1803 : : with any other USE would only be safe if we knew that the
1804 : : used registers have identical values, or if there was
1805 : : something to tell them apart, e.g. different modes. For
1806 : : now, we forgo such complicated tests and simply disallow
1807 : : combining of USES of pseudo registers with any other USE. */
1808 : 112068 : if (REG_P (XEXP (elt, 0))
1809 : 112068 : && GET_CODE (PATTERN (i3)) == PARALLEL)
1810 : : {
1811 : 225 : rtx i3pat = PATTERN (i3);
1812 : 225 : int i = XVECLEN (i3pat, 0) - 1;
1813 : 225 : unsigned int regno = REGNO (XEXP (elt, 0));
1814 : :
1815 : 461 : do
1816 : : {
1817 : 461 : rtx i3elt = XVECEXP (i3pat, 0, i);
1818 : :
1819 : 461 : if (GET_CODE (i3elt) == USE
1820 : 209 : && REG_P (XEXP (i3elt, 0))
1821 : 697 : && (REGNO (XEXP (i3elt, 0)) == regno
1822 : 182 : ? reg_set_between_p (XEXP (elt, 0),
1823 : 27 : PREV_INSN (insn), i3)
1824 : : : regno >= FIRST_PSEUDO_REGISTER))
1825 : 182 : return false;
1826 : : }
1827 : 279 : while (--i >= 0);
1828 : : }
1829 : : break;
1830 : :
1831 : : /* We can ignore CLOBBERs. */
1832 : : case CLOBBER:
1833 : : break;
1834 : :
1835 : 16827822 : case SET:
1836 : : /* Ignore SETs whose result isn't used but not those that
1837 : : have side-effects. */
1838 : 16827822 : if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1839 : 196412 : && insn_nothrow_p (insn)
1840 : 17010522 : && !side_effects_p (elt))
1841 : : break;
1842 : :
1843 : : /* If we have already found a SET, this is a second one and
1844 : : so we cannot combine with this insn. */
1845 : 16721981 : if (set)
1846 : : return false;
1847 : :
1848 : : set = elt;
1849 : : break;
1850 : :
1851 : : default:
1852 : : /* Anything else means we can't combine. */
1853 : : return false;
1854 : : }
1855 : : }
1856 : :
1857 : 15779218 : if (set == 0
1858 : : /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1859 : : so don't do anything with it. */
1860 : 15779218 : || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1861 : : return false;
1862 : : }
1863 : : else
1864 : : return false;
1865 : :
1866 : : if (set == 0)
1867 : : return false;
1868 : :
1869 : : /* The simplification in expand_field_assignment may call back to
1870 : : get_last_value, so set safe guard here. */
1871 : 59235642 : subst_low_luid = DF_INSN_LUID (insn);
1872 : :
1873 : 59235642 : set = expand_field_assignment (set);
1874 : 59235642 : src = SET_SRC (set), dest = SET_DEST (set);
1875 : :
1876 : : /* Do not eliminate user-specified register if it is in an
1877 : : asm input because we may break the register asm usage defined
1878 : : in GCC manual if allow to do so.
1879 : : Be aware that this may cover more cases than we expect but this
1880 : : should be harmless. */
1881 : 58715360 : if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1882 : 59235645 : && extract_asm_operands (PATTERN (i3)))
1883 : : return false;
1884 : :
1885 : : /* Don't eliminate a store in the stack pointer. */
1886 : 59235642 : if (dest == stack_pointer_rtx
1887 : : /* Don't combine with an insn that sets a register to itself if it has
1888 : : a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1889 : 57315265 : || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1890 : : /* Can't merge an ASM_OPERANDS. */
1891 : 57315265 : || GET_CODE (src) == ASM_OPERANDS
1892 : : /* Can't merge a function call. */
1893 : 57311981 : || GET_CODE (src) == CALL
1894 : : /* Don't eliminate a function call argument. */
1895 : 57311981 : || (CALL_P (i3)
1896 : 9133813 : && (find_reg_fusage (i3, USE, dest)
1897 : 201896 : || (REG_P (dest)
1898 : 201896 : && REGNO (dest) < FIRST_PSEUDO_REGISTER
1899 : 163 : && global_regs[REGNO (dest)])))
1900 : : /* Don't substitute into an incremented register. */
1901 : : || FIND_REG_INC_NOTE (i3, dest)
1902 : : || (succ && FIND_REG_INC_NOTE (succ, dest))
1903 : 57311981 : || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1904 : : /* Don't substitute into a non-local goto, this confuses CFG. */
1905 : 48380061 : || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1906 : : /* Make sure that DEST is not used after INSN but before SUCC, or
1907 : : after SUCC and before SUCC2, or after SUCC2 but before I3. */
1908 : 48379340 : || (!all_adjacent
1909 : 11815088 : && ((succ2
1910 : 782259 : && (reg_used_between_p (dest, succ2, i3)
1911 : 763265 : || reg_used_between_p (dest, succ, succ2)))
1912 : 11778649 : || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1913 : 11542174 : || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1914 : 11542174 : || (succ
1915 : : /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1916 : : that case SUCC is not in the insn stream, so use SUCC2
1917 : : instead for this test. */
1918 : 9420474 : && reg_used_between_p (dest, insn,
1919 : : succ2
1920 : 745820 : && INSN_UID (succ) == INSN_UID (succ2)
1921 : : ? succ2 : succ))))
1922 : : /* Make sure that the value that is to be substituted for the register
1923 : : does not use any registers whose values alter in between. However,
1924 : : If the insns are adjacent, a use can't cross a set even though we
1925 : : think it might (this can happen for a sequence of insns each setting
1926 : : the same destination; last_set of that register might point to
1927 : : a NOTE). If INSN has a REG_EQUIV note, the register is always
1928 : : equivalent to the memory so the substitution is valid even if there
1929 : : are intervening stores. Also, don't move a volatile asm or
1930 : : UNSPEC_VOLATILE across any other insns. */
1931 : : || (! all_adjacent
1932 : 11542174 : && (((!MEM_P (src)
1933 : 3130679 : || ! find_reg_note (insn, REG_EQUIV, src))
1934 : 11427768 : && modified_between_p (src, insn, i3))
1935 : 10616727 : || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1936 : 10616727 : || GET_CODE (src) == UNSPEC_VOLATILE))
1937 : : /* Don't combine across a CALL_INSN, because that would possibly
1938 : : change whether the life span of some REGs crosses calls or not,
1939 : : and it is a pain to update that information.
1940 : : Exception: if source is a constant, moving it later can't hurt.
1941 : : Accept that as a special case. */
1942 : 106406023 : || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1943 : 12384006 : return false;
1944 : :
1945 : : /* DEST must be a REG. */
1946 : 46851636 : if (REG_P (dest))
1947 : : {
1948 : : /* If register alignment is being enforced for multi-word items in all
1949 : : cases except for parameters, it is possible to have a register copy
1950 : : insn referencing a hard register that is not allowed to contain the
1951 : : mode being copied and which would not be valid as an operand of most
1952 : : insns. Eliminate this problem by not combining with such an insn.
1953 : :
1954 : : Also, on some machines we don't want to extend the life of a hard
1955 : : register. */
1956 : :
1957 : 46336042 : if (REG_P (src)
1958 : 46336042 : && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1959 : 28982 : && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1960 : : /* Don't extend the life of a hard register unless it is
1961 : : user variable (if we have few registers) or it can't
1962 : : fit into the desired register (meaning something special
1963 : : is going on).
1964 : : Also avoid substituting a return register into I3, because
1965 : : reload can't handle a conflict with constraints of other
1966 : : inputs. */
1967 : 2517831 : || (REGNO (src) < FIRST_PSEUDO_REGISTER
1968 : 36947 : && !targetm.hard_regno_mode_ok (REGNO (src),
1969 : 36947 : GET_MODE (src)))))
1970 : 0 : return false;
1971 : : }
1972 : : else
1973 : : return false;
1974 : :
1975 : :
1976 : 46336042 : if (GET_CODE (PATTERN (i3)) == PARALLEL)
1977 : 37640453 : for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1978 : 25488586 : if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1979 : : {
1980 : 11755396 : rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1981 : :
1982 : : /* If the clobber represents an earlyclobber operand, we must not
1983 : : substitute an expression containing the clobbered register.
1984 : : As we do not analyze the constraint strings here, we have to
1985 : : make the conservative assumption. However, if the register is
1986 : : a fixed hard reg, the clobber cannot represent any operand;
1987 : : we leave it up to the machine description to either accept or
1988 : : reject use-and-clobber patterns. */
1989 : 11755396 : if (!REG_P (reg)
1990 : 11341320 : || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1991 : 23049198 : || !fixed_regs[REGNO (reg)])
1992 : 499830 : if (reg_overlap_mentioned_p (reg, src))
1993 : : return false;
1994 : : }
1995 : :
1996 : : /* If INSN contains anything volatile, or is an `asm' (whether volatile
1997 : : or not), reject, unless nothing volatile comes between it and I3 */
1998 : :
1999 : 46335395 : if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2000 : : {
2001 : : /* Make sure neither succ nor succ2 contains a volatile reference. */
2002 : 678261 : if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2003 : : return false;
2004 : 678257 : if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2005 : : return false;
2006 : : /* We'll check insns between INSN and I3 below. */
2007 : : }
2008 : :
2009 : : /* If INSN is an asm, and DEST is a hard register, reject, since it has
2010 : : to be an explicit register variable, and was chosen for a reason. */
2011 : :
2012 : 46289109 : if (GET_CODE (src) == ASM_OPERANDS
2013 : 46289109 : && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2014 : : return false;
2015 : :
2016 : : /* If INSN contains volatile references (specifically volatile MEMs),
2017 : : we cannot combine across any other volatile references.
2018 : : Even if INSN doesn't contain volatile references, any intervening
2019 : : volatile insn might affect machine state. */
2020 : :
2021 : 91945375 : is_volatile_p = volatile_refs_p (PATTERN (insn))
2022 : 46289109 : ? volatile_refs_p
2023 : : : volatile_insn_p;
2024 : :
2025 : 210257697 : for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2026 : 117891081 : if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2027 : : return false;
2028 : :
2029 : : /* If INSN contains an autoincrement or autodecrement, make sure that
2030 : : register is not used between there and I3, and not already used in
2031 : : I3 either. Neither must it be used in PRED or SUCC, if they exist.
2032 : : Also insist that I3 not be a jump if using LRA; if it were one
2033 : : and the incremented register were spilled, we would lose.
2034 : : Reload handles this correctly. */
2035 : :
2036 : 46077507 : if (AUTO_INC_DEC)
2037 : : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2038 : : if (REG_NOTE_KIND (link) == REG_INC
2039 : : && ((JUMP_P (i3) && targetm.lra_p ())
2040 : : || reg_used_between_p (XEXP (link, 0), insn, i3)
2041 : : || (pred != NULL_RTX
2042 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2043 : : || (pred2 != NULL_RTX
2044 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2045 : : || (succ != NULL_RTX
2046 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2047 : : || (succ2 != NULL_RTX
2048 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2049 : : || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2050 : : return false;
2051 : :
2052 : : /* If we get here, we have passed all the tests and the combination is
2053 : : to be allowed. */
2054 : :
2055 : 46077507 : *pdest = dest;
2056 : 46077507 : *psrc = src;
2057 : :
2058 : 46077507 : return true;
2059 : : }
2060 : :
2061 : : /* LOC is the location within I3 that contains its pattern or the component
2062 : : of a PARALLEL of the pattern. We validate that it is valid for combining.
2063 : :
2064 : : One problem is if I3 modifies its output, as opposed to replacing it
2065 : : entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2066 : : doing so would produce an insn that is not equivalent to the original insns.
2067 : :
2068 : : Consider:
2069 : :
2070 : : (set (reg:DI 101) (reg:DI 100))
2071 : : (set (subreg:SI (reg:DI 101) 0) <foo>)
2072 : :
2073 : : This is NOT equivalent to:
2074 : :
2075 : : (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2076 : : (set (reg:DI 101) (reg:DI 100))])
2077 : :
2078 : : Not only does this modify 100 (in which case it might still be valid
2079 : : if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2080 : :
2081 : : We can also run into a problem if I2 sets a register that I1
2082 : : uses and I1 gets directly substituted into I3 (not via I2). In that
2083 : : case, we would be getting the wrong value of I2DEST into I3, so we
2084 : : must reject the combination. This case occurs when I2 and I1 both
2085 : : feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2086 : : If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2087 : : of a SET must prevent combination from occurring. The same situation
2088 : : can occur for I0, in which case I0_NOT_IN_SRC is set.
2089 : :
2090 : : Before doing the above check, we first try to expand a field assignment
2091 : : into a set of logical operations.
2092 : :
2093 : : If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2094 : : we place a register that is both set and used within I3. If more than one
2095 : : such register is detected, we fail.
2096 : :
2097 : : Return true if the combination is valid, false otherwise. */
2098 : :
2099 : : static bool
2100 : 68206287 : combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2101 : : bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2102 : : {
2103 : 68206287 : rtx x = *loc;
2104 : :
2105 : 68206287 : if (GET_CODE (x) == SET)
2106 : : {
2107 : 44938031 : rtx set = x ;
2108 : 44938031 : rtx dest = SET_DEST (set);
2109 : 44938031 : rtx src = SET_SRC (set);
2110 : 44938031 : rtx inner_dest = dest;
2111 : 44938031 : rtx subdest;
2112 : :
2113 : 44938031 : while (GET_CODE (inner_dest) == STRICT_LOW_PART
2114 : 45417767 : || GET_CODE (inner_dest) == SUBREG
2115 : 45417767 : || GET_CODE (inner_dest) == ZERO_EXTRACT)
2116 : 479736 : inner_dest = XEXP (inner_dest, 0);
2117 : :
2118 : : /* Check for the case where I3 modifies its output, as discussed
2119 : : above. We don't want to prevent pseudos from being combined
2120 : : into the address of a MEM, so only prevent the combination if
2121 : : i1 or i2 set the same MEM. */
2122 : 460431 : if ((inner_dest != dest &&
2123 : : (!MEM_P (inner_dest)
2124 : 687 : || rtx_equal_p (i2dest, inner_dest)
2125 : 687 : || (i1dest && rtx_equal_p (i1dest, inner_dest))
2126 : 687 : || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2127 : 459744 : && (reg_overlap_mentioned_p (i2dest, inner_dest)
2128 : 339059 : || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2129 : 337718 : || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2130 : :
2131 : : /* This is the same test done in can_combine_p except we can't test
2132 : : all_adjacent; we don't have to, since this instruction will stay
2133 : : in place, thus we are not considering increasing the lifetime of
2134 : : INNER_DEST.
2135 : :
2136 : : Also, if this insn sets a function argument, combining it with
2137 : : something that might need a spill could clobber a previous
2138 : : function argument; the all_adjacent test in can_combine_p also
2139 : : checks this; here, we do a more specific test for this case. */
2140 : :
2141 : 44815894 : || (REG_P (inner_dest)
2142 : 29339698 : && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2143 : 7034319 : && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2144 : 7034319 : GET_MODE (inner_dest)))
2145 : 44815894 : || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2146 : 89748531 : || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2147 : 153236 : return false;
2148 : :
2149 : : /* If DEST is used in I3, it is being killed in this insn, so
2150 : : record that for later. We have to consider paradoxical
2151 : : subregs here, since they kill the whole register, but we
2152 : : ignore partial subregs, STRICT_LOW_PART, etc.
2153 : : Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2154 : : STACK_POINTER_REGNUM, since these are always considered to be
2155 : : live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2156 : 44784795 : subdest = dest;
2157 : 44784795 : if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2158 : 256133 : subdest = SUBREG_REG (subdest);
2159 : 44784795 : if (pi3dest_killed
2160 : 32834021 : && REG_P (subdest)
2161 : 21043766 : && reg_referenced_p (subdest, PATTERN (i3))
2162 : 1293055 : && REGNO (subdest) != FRAME_POINTER_REGNUM
2163 : 1293055 : && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2164 : 1293055 : || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2165 : 1293055 : && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2166 : 1293055 : || (REGNO (subdest) != ARG_POINTER_REGNUM
2167 : 0 : || ! fixed_regs [REGNO (subdest)]))
2168 : 46077850 : && REGNO (subdest) != STACK_POINTER_REGNUM)
2169 : : {
2170 : 1256874 : if (*pi3dest_killed)
2171 : : return false;
2172 : :
2173 : 1196340 : *pi3dest_killed = subdest;
2174 : : }
2175 : : }
2176 : :
2177 : 23268256 : else if (GET_CODE (x) == PARALLEL)
2178 : : {
2179 : : int i;
2180 : :
2181 : 35440820 : for (i = 0; i < XVECLEN (x, 0); i++)
2182 : 23968976 : if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2183 : : i1_not_in_src, i0_not_in_src, pi3dest_killed))
2184 : : return false;
2185 : : }
2186 : :
2187 : : return true;
2188 : : }
2189 : :
2190 : : /* Return true if X is an arithmetic expression that contains a multiplication
2191 : : and division. We don't count multiplications by powers of two here. */
2192 : :
2193 : : static bool
2194 : 17070172 : contains_muldiv (rtx x)
2195 : : {
2196 : 17729265 : switch (GET_CODE (x))
2197 : : {
2198 : : case MOD: case DIV: case UMOD: case UDIV:
2199 : : return true;
2200 : :
2201 : 511652 : case MULT:
2202 : 511652 : return ! (CONST_INT_P (XEXP (x, 1))
2203 : 185509 : && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2204 : 17066872 : default:
2205 : 17066872 : if (BINARY_P (x))
2206 : 5961490 : return contains_muldiv (XEXP (x, 0))
2207 : 5961490 : || contains_muldiv (XEXP (x, 1));
2208 : :
2209 : 11105382 : if (UNARY_P (x))
2210 : 659093 : return contains_muldiv (XEXP (x, 0));
2211 : :
2212 : : return false;
2213 : : }
2214 : : }
2215 : :
2216 : : /* Determine whether INSN can be used in a combination. Return true if
2217 : : not. This is used in try_combine to detect early some cases where we
2218 : : can't perform combinations. */
2219 : :
2220 : : static bool
2221 : 162829973 : cant_combine_insn_p (rtx_insn *insn)
2222 : : {
2223 : 162829973 : rtx set;
2224 : 162829973 : rtx src, dest;
2225 : :
2226 : : /* If this isn't really an insn, we can't do anything.
2227 : : This can occur when flow deletes an insn that it has merged into an
2228 : : auto-increment address. */
2229 : 162829973 : if (!NONDEBUG_INSN_P (insn))
2230 : : return true;
2231 : :
2232 : : /* Never combine loads and stores involving hard regs that are likely
2233 : : to be spilled. The register allocator can usually handle such
2234 : : reg-reg moves by tying. If we allow the combiner to make
2235 : : substitutions of likely-spilled regs, reload might die.
2236 : : As an exception, we allow combinations involving fixed regs; these are
2237 : : not available to the register allocator so there's no risk involved. */
2238 : :
2239 : 162829574 : set = single_set (insn);
2240 : 162829574 : if (! set)
2241 : : return false;
2242 : 150008503 : src = SET_SRC (set);
2243 : 150008503 : dest = SET_DEST (set);
2244 : 150008503 : if (GET_CODE (src) == SUBREG)
2245 : 989068 : src = SUBREG_REG (src);
2246 : 150008503 : if (GET_CODE (dest) == SUBREG)
2247 : 1613270 : dest = SUBREG_REG (dest);
2248 : 40503815 : if (REG_P (src) && REG_P (dest)
2249 : 183917820 : && ((HARD_REGISTER_P (src)
2250 : 6576777 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2251 : : #ifdef LEAF_REGISTERS
2252 : : && ! LEAF_REGISTERS [REGNO (src)])
2253 : : #else
2254 : : )
2255 : : #endif
2256 : 27629178 : || (HARD_REGISTER_P (dest)
2257 : 19706867 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2258 : 19447204 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2259 : 24070784 : return true;
2260 : :
2261 : : return false;
2262 : : }
2263 : :
2264 : : struct likely_spilled_retval_info
2265 : : {
2266 : : unsigned regno, nregs;
2267 : : unsigned mask;
2268 : : };
2269 : :
2270 : : /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2271 : : hard registers that are known to be written to / clobbered in full. */
2272 : : static void
2273 : 163497 : likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2274 : : {
2275 : 163497 : struct likely_spilled_retval_info *const info =
2276 : : (struct likely_spilled_retval_info *) data;
2277 : 163497 : unsigned regno, nregs;
2278 : 163497 : unsigned new_mask;
2279 : :
2280 : 163497 : if (!REG_P (XEXP (set, 0)))
2281 : : return;
2282 : 163497 : regno = REGNO (x);
2283 : 163497 : if (regno >= info->regno + info->nregs)
2284 : : return;
2285 : 163497 : nregs = REG_NREGS (x);
2286 : 163497 : if (regno + nregs <= info->regno)
2287 : : return;
2288 : 163497 : new_mask = (2U << (nregs - 1)) - 1;
2289 : 163497 : if (regno < info->regno)
2290 : 0 : new_mask >>= info->regno - regno;
2291 : : else
2292 : 163497 : new_mask <<= regno - info->regno;
2293 : 163497 : info->mask &= ~new_mask;
2294 : : }
2295 : :
2296 : : /* Return true iff part of the return value is live during INSN, and
2297 : : it is likely spilled. This can happen when more than one insn is needed
2298 : : to copy the return value, e.g. when we consider to combine into the
2299 : : second copy insn for a complex value. */
2300 : :
2301 : : static bool
2302 : 46518814 : likely_spilled_retval_p (rtx_insn *insn)
2303 : : {
2304 : 46518814 : rtx_insn *use = BB_END (this_basic_block);
2305 : 46518814 : rtx reg;
2306 : 46518814 : rtx_insn *p;
2307 : 46518814 : unsigned regno, nregs;
2308 : : /* We assume here that no machine mode needs more than
2309 : : 32 hard registers when the value overlaps with a register
2310 : : for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2311 : 46518814 : unsigned mask;
2312 : 46518814 : struct likely_spilled_retval_info info;
2313 : :
2314 : 46518814 : if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2315 : : return false;
2316 : 3029029 : reg = XEXP (PATTERN (use), 0);
2317 : 3029029 : if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2318 : 0 : return false;
2319 : 3029029 : regno = REGNO (reg);
2320 : 3029029 : nregs = REG_NREGS (reg);
2321 : 3029029 : if (nregs == 1)
2322 : : return false;
2323 : 160909 : mask = (2U << (nregs - 1)) - 1;
2324 : :
2325 : : /* Disregard parts of the return value that are set later. */
2326 : 160909 : info.regno = regno;
2327 : 160909 : info.nregs = nregs;
2328 : 160909 : info.mask = mask;
2329 : 545301 : for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2330 : 223483 : if (INSN_P (p))
2331 : 223483 : note_stores (p, likely_spilled_retval_1, &info);
2332 : 321816 : mask = info.mask;
2333 : :
2334 : : /* Check if any of the (probably) live return value registers is
2335 : : likely spilled. */
2336 : : nregs --;
2337 : 321816 : do
2338 : : {
2339 : 321816 : if ((mask & 1 << nregs)
2340 : 321816 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2341 : : return true;
2342 : 321804 : } while (nregs--);
2343 : : return false;
2344 : : }
2345 : :
2346 : : /* Adjust INSN after we made a change to its destination.
2347 : :
2348 : : Changing the destination can invalidate notes that say something about
2349 : : the results of the insn and a LOG_LINK pointing to the insn. */
2350 : :
2351 : : static void
2352 : 18212 : adjust_for_new_dest (rtx_insn *insn)
2353 : : {
2354 : : /* For notes, be conservative and simply remove them. */
2355 : 18212 : remove_reg_equal_equiv_notes (insn, true);
2356 : :
2357 : : /* The new insn will have a destination that was previously the destination
2358 : : of an insn just above it. Call distribute_links to make a LOG_LINK from
2359 : : the next use of that destination. */
2360 : :
2361 : 18212 : rtx set = single_set (insn);
2362 : 18212 : gcc_assert (set);
2363 : :
2364 : 18212 : rtx reg = SET_DEST (set);
2365 : :
2366 : 18212 : while (GET_CODE (reg) == ZERO_EXTRACT
2367 : 18212 : || GET_CODE (reg) == STRICT_LOW_PART
2368 : 36424 : || GET_CODE (reg) == SUBREG)
2369 : 0 : reg = XEXP (reg, 0);
2370 : 18212 : gcc_assert (REG_P (reg));
2371 : :
2372 : 18212 : distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2373 : :
2374 : 18212 : df_insn_rescan (insn);
2375 : 18212 : }
2376 : :
2377 : : /* Return TRUE if combine can reuse reg X in mode MODE.
2378 : : ADDED_SETS is trueif the original set is still required. */
2379 : : static bool
2380 : 2633391 : can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2381 : : {
2382 : 2633391 : unsigned int regno;
2383 : :
2384 : 2633391 : if (!REG_P (x))
2385 : : return false;
2386 : :
2387 : : /* Don't change between modes with different underlying register sizes,
2388 : : since this could lead to invalid subregs. */
2389 : 2633391 : if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2390 : 2633391 : REGMODE_NATURAL_SIZE (GET_MODE (x))))
2391 : : return false;
2392 : :
2393 : 2633391 : regno = REGNO (x);
2394 : : /* Allow hard registers if the new mode is legal, and occupies no more
2395 : : registers than the old mode. */
2396 : 2633391 : if (regno < FIRST_PSEUDO_REGISTER)
2397 : 1118184 : return (targetm.hard_regno_mode_ok (regno, mode)
2398 : 1118184 : && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2399 : :
2400 : : /* Or a pseudo that is only used once. */
2401 : 1515207 : return (regno < reg_n_sets_max
2402 : 1515205 : && REG_N_SETS (regno) == 1
2403 : 1469583 : && !added_sets
2404 : 2984790 : && !REG_USERVAR_P (x));
2405 : : }
2406 : :
2407 : :
2408 : : /* Check whether X, the destination of a set, refers to part of
2409 : : the register specified by REG. */
2410 : :
2411 : : static bool
2412 : 18485 : reg_subword_p (rtx x, rtx reg)
2413 : : {
2414 : : /* Check that reg is an integer mode register. */
2415 : 18485 : if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2416 : : return false;
2417 : :
2418 : 18001 : if (GET_CODE (x) == STRICT_LOW_PART
2419 : 17462 : || GET_CODE (x) == ZERO_EXTRACT)
2420 : 566 : x = XEXP (x, 0);
2421 : :
2422 : 18001 : return GET_CODE (x) == SUBREG
2423 : 17793 : && !paradoxical_subreg_p (x)
2424 : 17793 : && SUBREG_REG (x) == reg
2425 : 35794 : && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2426 : : }
2427 : :
2428 : : /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2429 : : by an arbitrary number of CLOBBERs. */
2430 : : static bool
2431 : 99769631 : is_parallel_of_n_reg_sets (rtx pat, int n)
2432 : : {
2433 : 99769631 : if (GET_CODE (pat) != PARALLEL)
2434 : : return false;
2435 : :
2436 : 27170377 : int len = XVECLEN (pat, 0);
2437 : 27170377 : if (len < n)
2438 : : return false;
2439 : :
2440 : : int i;
2441 : 54247395 : for (i = 0; i < n; i++)
2442 : 51519177 : if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2443 : 30199304 : || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2444 : : return false;
2445 : 3076415 : for ( ; i < len; i++)
2446 : 952896 : switch (GET_CODE (XVECEXP (pat, 0, i)))
2447 : : {
2448 : 348197 : case CLOBBER:
2449 : 348197 : if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2450 : : return false;
2451 : 348197 : break;
2452 : : default:
2453 : : return false;
2454 : : }
2455 : : return true;
2456 : : }
2457 : :
2458 : : /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2459 : : CLOBBERs), can be split into individual SETs in that order, without
2460 : : changing semantics. */
2461 : : static bool
2462 : 367242 : can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2463 : : {
2464 : 367242 : if (!insn_nothrow_p (insn))
2465 : : return false;
2466 : :
2467 : 365751 : rtx pat = PATTERN (insn);
2468 : :
2469 : 365751 : int i, j;
2470 : 984275 : for (i = 0; i < n; i++)
2471 : : {
2472 : 675013 : if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2473 : : return false;
2474 : :
2475 : 672073 : rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2476 : :
2477 : 981335 : for (j = i + 1; j < n; j++)
2478 : 362811 : if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2479 : : return false;
2480 : : }
2481 : :
2482 : : return true;
2483 : : }
2484 : :
2485 : : /* Return whether X is just a single_set, with the source
2486 : : a general_operand. */
2487 : : static bool
2488 : 65049556 : is_just_move (rtx_insn *x)
2489 : : {
2490 : 65049556 : rtx set = single_set (x);
2491 : 65049556 : if (!set)
2492 : : return false;
2493 : :
2494 : 64617060 : return general_operand (SET_SRC (set), VOIDmode);
2495 : : }
2496 : :
2497 : : /* Callback function to count autoincs. */
2498 : :
2499 : : static int
2500 : 1021873 : count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2501 : : {
2502 : 1021873 : (*((int *) arg))++;
2503 : :
2504 : 1021873 : return 0;
2505 : : }
2506 : :
2507 : : /* Try to combine the insns I0, I1 and I2 into I3.
2508 : : Here I0, I1 and I2 appear earlier than I3.
2509 : : I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2510 : : I3.
2511 : :
2512 : : If we are combining more than two insns and the resulting insn is not
2513 : : recognized, try splitting it into two insns. If that happens, I2 and I3
2514 : : are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2515 : : Otherwise, I0, I1 and I2 are pseudo-deleted.
2516 : :
2517 : : Return 0 if the combination does not work. Then nothing is changed.
2518 : : If we did the combination, return the insn at which combine should
2519 : : resume scanning.
2520 : :
2521 : : Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2522 : : new direct jump instruction.
2523 : :
2524 : : LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2525 : : been I3 passed to an earlier try_combine within the same basic
2526 : : block. */
2527 : :
2528 : : static rtx_insn *
2529 : 95938232 : try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2530 : : bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2531 : : {
2532 : : /* New patterns for I3 and I2, respectively. */
2533 : 95938232 : rtx newpat, newi2pat = 0;
2534 : 95938232 : rtvec newpat_vec_with_clobbers = 0;
2535 : 95938232 : bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2536 : : /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2537 : : dead. */
2538 : 95938232 : bool added_sets_0, added_sets_1, added_sets_2;
2539 : : /* Total number of SETs to put into I3. */
2540 : 95938232 : int total_sets;
2541 : : /* Nonzero if I2's or I1's body now appears in I3. */
2542 : 95938232 : int i2_is_used = 0, i1_is_used = 0;
2543 : : /* INSN_CODEs for new I3, new I2, and user of condition code. */
2544 : 95938232 : int insn_code_number, i2_code_number = 0, other_code_number = 0;
2545 : : /* Contains I3 if the destination of I3 is used in its source, which means
2546 : : that the old life of I3 is being killed. If that usage is placed into
2547 : : I2 and not in I3, a REG_DEAD note must be made. */
2548 : 95938232 : rtx i3dest_killed = 0;
2549 : : /* SET_DEST and SET_SRC of I2, I1 and I0. */
2550 : 95938232 : rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2551 : : /* Copy of SET_SRC of I1 and I0, if needed. */
2552 : 95938232 : rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2553 : : /* Set if I2DEST was reused as a scratch register. */
2554 : 95938232 : bool i2scratch = false;
2555 : : /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2556 : 95938232 : rtx i0pat = 0, i1pat = 0, i2pat = 0;
2557 : : /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2558 : 95938232 : bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2559 : 95938232 : bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2560 : 95938232 : bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2561 : 95938232 : bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2562 : 95938232 : bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2563 : : /* Notes that must be added to REG_NOTES in I3 and I2. */
2564 : 95938232 : rtx new_i3_notes, new_i2_notes;
2565 : : /* Notes that we substituted I3 into I2 instead of the normal case. */
2566 : 95938232 : bool i3_subst_into_i2 = false;
2567 : : /* Notes that I1, I2 or I3 is a MULT operation. */
2568 : 95938232 : bool have_mult = false;
2569 : 95938232 : bool swap_i2i3 = false;
2570 : 95938232 : bool split_i2i3 = false;
2571 : 95938232 : bool changed_i3_dest = false;
2572 : 95938232 : bool i2_was_move = false, i3_was_move = false;
2573 : 95938232 : int n_auto_inc = 0;
2574 : :
2575 : 95938232 : int maxreg;
2576 : 95938232 : rtx_insn *temp_insn;
2577 : 95938232 : rtx temp_expr;
2578 : 95938232 : struct insn_link *link;
2579 : 95938232 : rtx other_pat = 0;
2580 : 95938232 : rtx new_other_notes;
2581 : 95938232 : int i;
2582 : 95938232 : scalar_int_mode dest_mode, temp_mode;
2583 : 95938232 : bool has_non_call_exception = false;
2584 : :
2585 : : /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2586 : : never be). */
2587 : 95938232 : if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2588 : : return 0;
2589 : :
2590 : : /* Only try four-insn combinations when there's high likelihood of
2591 : : success. Look for simple insns, such as loads of constants or
2592 : : binary operations involving a constant. */
2593 : 22405064 : if (i0)
2594 : : {
2595 : 22405064 : int i;
2596 : 22405064 : int ngood = 0;
2597 : 22405064 : int nshift = 0;
2598 : 22405064 : rtx set0, set3;
2599 : :
2600 : 22405064 : if (!flag_expensive_optimizations)
2601 : : return 0;
2602 : :
2603 : 88638388 : for (i = 0; i < 4; i++)
2604 : : {
2605 : 72453250 : rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2606 : 72453250 : rtx set = single_set (insn);
2607 : 72453250 : rtx src;
2608 : 72453250 : if (!set)
2609 : 2312719 : continue;
2610 : 70140531 : src = SET_SRC (set);
2611 : 70140531 : if (CONSTANT_P (src))
2612 : : {
2613 : 4637243 : ngood += 2;
2614 : 4637243 : break;
2615 : : }
2616 : 65503288 : else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2617 : 8283547 : ngood++;
2618 : 57219741 : else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2619 : 57134820 : || GET_CODE (src) == LSHIFTRT)
2620 : 112257 : nshift++;
2621 : : }
2622 : :
2623 : : /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2624 : : are likely manipulating its value. Ideally we'll be able to combine
2625 : : all four insns into a bitfield insertion of some kind.
2626 : :
2627 : : Note the source in I0 might be inside a sign/zero extension and the
2628 : : memory modes in I0 and I3 might be different. So extract the address
2629 : : from the destination of I3 and search for it in the source of I0.
2630 : :
2631 : : In the event that there's a match but the source/dest do not actually
2632 : : refer to the same memory, the worst that happens is we try some
2633 : : combinations that we wouldn't have otherwise. */
2634 : 20822381 : if ((set0 = single_set (i0))
2635 : : /* Ensure the source of SET0 is a MEM, possibly buried inside
2636 : : an extension. */
2637 : 20699508 : && (GET_CODE (SET_SRC (set0)) == MEM
2638 : 17311974 : || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2639 : 17311974 : || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2640 : 584704 : && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2641 : 3494641 : && (set3 = single_set (i3))
2642 : : /* Ensure the destination of SET3 is a MEM. */
2643 : 3029259 : && GET_CODE (SET_DEST (set3)) == MEM
2644 : : /* Would it be better to extract the base address for the MEM
2645 : : in SET3 and look for that? I don't have cases where it matters
2646 : : but I could envision such cases. */
2647 : 21175802 : && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2648 : 25310 : ngood += 2;
2649 : :
2650 : 20822381 : if (ngood < 2 && nshift < 2)
2651 : : return 0;
2652 : : }
2653 : :
2654 : : /* Exit early if one of the insns involved can't be used for
2655 : : combinations. */
2656 : 79323347 : if (CALL_P (i2)
2657 : 74118875 : || (i1 && CALL_P (i1))
2658 : 70656400 : || (i0 && CALL_P (i0))
2659 : 70589997 : || cant_combine_insn_p (i3)
2660 : 67332126 : || cant_combine_insn_p (i2)
2661 : 51659315 : || (i1 && cant_combine_insn_p (i1))
2662 : 46599065 : || (i0 && cant_combine_insn_p (i0))
2663 : 125842161 : || likely_spilled_retval_p (i3))
2664 : 32804545 : return 0;
2665 : :
2666 : 46518802 : combine_attempts++;
2667 : 46518802 : undobuf.other_insn = 0;
2668 : :
2669 : : /* Reset the hard register usage information. */
2670 : 46518802 : CLEAR_HARD_REG_SET (newpat_used_regs);
2671 : :
2672 : 46518802 : if (dump_file && (dump_flags & TDF_DETAILS))
2673 : : {
2674 : 174 : if (i0)
2675 : 20 : fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2676 : 20 : INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2677 : 154 : else if (i1)
2678 : 26 : fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2679 : 26 : INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2680 : : else
2681 : 128 : fprintf (dump_file, "\nTrying %d -> %d:\n",
2682 : 128 : INSN_UID (i2), INSN_UID (i3));
2683 : :
2684 : 174 : if (i0)
2685 : 20 : dump_insn_slim (dump_file, i0);
2686 : 174 : if (i1)
2687 : 46 : dump_insn_slim (dump_file, i1);
2688 : 174 : dump_insn_slim (dump_file, i2);
2689 : 174 : dump_insn_slim (dump_file, i3);
2690 : : }
2691 : :
2692 : : /* If multiple insns feed into one of I2 or I3, they can be in any
2693 : : order. To simplify the code below, reorder them in sequence. */
2694 : 46518802 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2695 : : std::swap (i0, i2);
2696 : 46518802 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2697 : : std::swap (i0, i1);
2698 : 46518802 : if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2699 : : std::swap (i1, i2);
2700 : :
2701 : 46518802 : added_links_insn = 0;
2702 : 46518802 : added_notes_insn = 0;
2703 : :
2704 : : /* First check for one important special case that the code below will
2705 : : not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2706 : : and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2707 : : we may be able to replace that destination with the destination of I3.
2708 : : This occurs in the common code where we compute both a quotient and
2709 : : remainder into a structure, in which case we want to do the computation
2710 : : directly into the structure to avoid register-register copies.
2711 : :
2712 : : Note that this case handles both multiple sets in I2 and also cases
2713 : : where I2 has a number of CLOBBERs inside the PARALLEL.
2714 : :
2715 : : We make very conservative checks below and only try to handle the
2716 : : most common cases of this. For example, we only handle the case
2717 : : where I2 and I3 are adjacent to avoid making difficult register
2718 : : usage tests. */
2719 : :
2720 : 29032212 : if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2721 : 14885723 : && REG_P (SET_SRC (PATTERN (i3)))
2722 : 5007658 : && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2723 : 4806158 : && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2724 : 3900434 : && GET_CODE (PATTERN (i2)) == PARALLEL
2725 : 1050666 : && ! side_effects_p (SET_DEST (PATTERN (i3)))
2726 : : /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2727 : : below would need to check what is inside (and reg_overlap_mentioned_p
2728 : : doesn't support those codes anyway). Don't allow those destinations;
2729 : : the resulting insn isn't likely to be recognized anyway. */
2730 : 564261 : && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2731 : 564227 : && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2732 : 563324 : && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2733 : 563324 : SET_DEST (PATTERN (i3)))
2734 : 47082043 : && next_active_insn (i2) == i3)
2735 : : {
2736 : 355676 : rtx p2 = PATTERN (i2);
2737 : :
2738 : : /* Make sure that the destination of I3,
2739 : : which we are going to substitute into one output of I2,
2740 : : is not used within another output of I2. We must avoid making this:
2741 : : (parallel [(set (mem (reg 69)) ...)
2742 : : (set (reg 69) ...)])
2743 : : which is not well-defined as to order of actions.
2744 : : (Besides, reload can't handle output reloads for this.)
2745 : :
2746 : : The problem can also happen if the dest of I3 is a memory ref,
2747 : : if another dest in I2 is an indirect memory ref.
2748 : :
2749 : : Neither can this PARALLEL be an asm. We do not allow combining
2750 : : that usually (see can_combine_p), so do not here either. */
2751 : 355676 : bool ok = true;
2752 : 1078939 : for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2753 : : {
2754 : 723263 : if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2755 : 355230 : || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2756 : 1445127 : && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2757 : 721864 : SET_DEST (XVECEXP (p2, 0, i))))
2758 : : ok = false;
2759 : 722498 : else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2760 : 367270 : && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2761 : 1881 : ok = false;
2762 : : }
2763 : :
2764 : 355676 : if (ok)
2765 : 418796 : for (i = 0; i < XVECLEN (p2, 0); i++)
2766 : 387775 : if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2767 : 387775 : && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2768 : : {
2769 : 322774 : combine_merges++;
2770 : :
2771 : 322774 : subst_insn = i3;
2772 : 322774 : subst_low_luid = DF_INSN_LUID (i2);
2773 : :
2774 : 322774 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2775 : 322774 : i2src = SET_SRC (XVECEXP (p2, 0, i));
2776 : 322774 : i2dest = SET_DEST (XVECEXP (p2, 0, i));
2777 : 322774 : i2dest_killed = dead_or_set_p (i2, i2dest);
2778 : :
2779 : : /* Replace the dest in I2 with our dest and make the resulting
2780 : : insn the new pattern for I3. Then skip to where we validate
2781 : : the pattern. Everything was set up above. */
2782 : 322774 : SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2783 : 322774 : newpat = p2;
2784 : 322774 : i3_subst_into_i2 = true;
2785 : 322774 : goto validate_replacement;
2786 : : }
2787 : : }
2788 : :
2789 : : /* If I2 is setting a pseudo to a constant and I3 is setting some
2790 : : sub-part of it to another constant, merge them by making a new
2791 : : constant. */
2792 : 46196028 : if (i1 == 0
2793 : 28709438 : && (temp_expr = single_set (i2)) != 0
2794 : 28441251 : && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2795 : 19041594 : && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2796 : 2848024 : && GET_CODE (PATTERN (i3)) == SET
2797 : 1409232 : && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2798 : 46214513 : && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2799 : : {
2800 : 17793 : rtx dest = SET_DEST (PATTERN (i3));
2801 : 17793 : rtx temp_dest = SET_DEST (temp_expr);
2802 : 17793 : int offset = -1;
2803 : 17793 : int width = 0;
2804 : :
2805 : 17793 : if (GET_CODE (dest) == ZERO_EXTRACT)
2806 : : {
2807 : 1 : if (CONST_INT_P (XEXP (dest, 1))
2808 : 1 : && CONST_INT_P (XEXP (dest, 2))
2809 : 2 : && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2810 : : &dest_mode))
2811 : : {
2812 : 1 : width = INTVAL (XEXP (dest, 1));
2813 : 1 : offset = INTVAL (XEXP (dest, 2));
2814 : 1 : dest = XEXP (dest, 0);
2815 : 1 : if (BITS_BIG_ENDIAN)
2816 : : offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2817 : : }
2818 : : }
2819 : : else
2820 : : {
2821 : 17792 : if (GET_CODE (dest) == STRICT_LOW_PART)
2822 : 539 : dest = XEXP (dest, 0);
2823 : 17792 : if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2824 : : {
2825 : 17792 : width = GET_MODE_PRECISION (dest_mode);
2826 : 17792 : offset = 0;
2827 : : }
2828 : : }
2829 : :
2830 : 17793 : if (offset >= 0)
2831 : : {
2832 : : /* If this is the low part, we're done. */
2833 : 17793 : if (subreg_lowpart_p (dest))
2834 : : ;
2835 : : /* Handle the case where inner is twice the size of outer. */
2836 : 4539 : else if (GET_MODE_PRECISION (temp_mode)
2837 : 4539 : == 2 * GET_MODE_PRECISION (dest_mode))
2838 : 4525 : offset += GET_MODE_PRECISION (dest_mode);
2839 : : /* Otherwise give up for now. */
2840 : : else
2841 : : offset = -1;
2842 : : }
2843 : :
2844 : 17779 : if (offset >= 0)
2845 : : {
2846 : 17779 : rtx inner = SET_SRC (PATTERN (i3));
2847 : 17779 : rtx outer = SET_SRC (temp_expr);
2848 : :
2849 : 35558 : wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2850 : 17779 : rtx_mode_t (inner, dest_mode),
2851 : 35558 : offset, width);
2852 : :
2853 : 17779 : combine_merges++;
2854 : 17779 : subst_insn = i3;
2855 : 17779 : subst_low_luid = DF_INSN_LUID (i2);
2856 : 17779 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2857 : 17779 : i2dest = temp_dest;
2858 : 17779 : i2dest_killed = dead_or_set_p (i2, i2dest);
2859 : :
2860 : : /* Replace the source in I2 with the new constant and make the
2861 : : resulting insn the new pattern for I3. Then skip to where we
2862 : : validate the pattern. Everything was set up above. */
2863 : 17779 : SUBST (SET_SRC (temp_expr),
2864 : : immed_wide_int_const (o, temp_mode));
2865 : :
2866 : 17779 : newpat = PATTERN (i2);
2867 : :
2868 : : /* The dest of I3 has been replaced with the dest of I2. */
2869 : 17779 : changed_i3_dest = true;
2870 : 17779 : goto validate_replacement;
2871 : 17779 : }
2872 : : }
2873 : :
2874 : : /* If we have no I1 and I2 looks like:
2875 : : (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2876 : : (set Y OP)])
2877 : : make up a dummy I1 that is
2878 : : (set Y OP)
2879 : : and change I2 to be
2880 : : (set (reg:CC X) (compare:CC Y (const_int 0)))
2881 : :
2882 : : (We can ignore any trailing CLOBBERs.)
2883 : :
2884 : : This undoes a previous combination and allows us to match a branch-and-
2885 : : decrement insn. */
2886 : :
2887 : 46178249 : if (i1 == 0
2888 : 28691659 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2889 : 222697 : && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2890 : : == MODE_CC)
2891 : 145378 : && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2892 : 118815 : && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2893 : 79461 : && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2894 : 79461 : SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2895 : 70013 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2896 : 46248262 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2897 : : {
2898 : : /* We make I1 with the same INSN_UID as I2. This gives it
2899 : : the same DF_INSN_LUID for value tracking. Our fake I1 will
2900 : : never appear in the insn stream so giving it the same INSN_UID
2901 : : as I2 will not cause a problem. */
2902 : :
2903 : 139590 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2904 : 69795 : XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2905 : : -1, NULL_RTX);
2906 : 69795 : INSN_UID (i1) = INSN_UID (i2);
2907 : :
2908 : 69795 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2909 : 69795 : SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2910 : : SET_DEST (PATTERN (i1)));
2911 : 69795 : unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2912 : 69795 : SUBST_LINK (LOG_LINKS (i2),
2913 : : alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2914 : : }
2915 : :
2916 : : /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2917 : : make those two SETs separate I1 and I2 insns, and make an I0 that is
2918 : : the original I1. */
2919 : 46178249 : if (i0 == 0
2920 : 43977745 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2921 : 367242 : && can_split_parallel_of_n_reg_sets (i2, 2)
2922 : 309262 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2923 : 272046 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2924 : 254598 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2925 : 46432838 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2926 : : {
2927 : : /* If there is no I1, there is no I0 either. */
2928 : 254589 : i0 = i1;
2929 : :
2930 : : /* We make I1 with the same INSN_UID as I2. This gives it
2931 : : the same DF_INSN_LUID for value tracking. Our fake I1 will
2932 : : never appear in the insn stream so giving it the same INSN_UID
2933 : : as I2 will not cause a problem. */
2934 : :
2935 : 509178 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2936 : 254589 : XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2937 : : -1, NULL_RTX);
2938 : 254589 : INSN_UID (i1) = INSN_UID (i2);
2939 : :
2940 : 254589 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2941 : : }
2942 : :
2943 : : /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2944 : 46178249 : if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2945 : : {
2946 : 12165776 : if (dump_file && (dump_flags & TDF_DETAILS))
2947 : 8 : fprintf (dump_file, "Can't combine i2 into i3\n");
2948 : 12165776 : undo_all ();
2949 : 12165776 : return 0;
2950 : : }
2951 : 34012473 : if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2952 : : {
2953 : 1323578 : if (dump_file && (dump_flags & TDF_DETAILS))
2954 : 0 : fprintf (dump_file, "Can't combine i1 into i3\n");
2955 : 1323578 : undo_all ();
2956 : 1323578 : return 0;
2957 : : }
2958 : 32688895 : if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2959 : : {
2960 : 163758 : if (dump_file && (dump_flags & TDF_DETAILS))
2961 : 0 : fprintf (dump_file, "Can't combine i0 into i3\n");
2962 : 163758 : undo_all ();
2963 : 163758 : return 0;
2964 : : }
2965 : :
2966 : : /* With non-call exceptions we can end up trying to combine multiple
2967 : : insns with possible EH side effects. Make sure we can combine
2968 : : that to a single insn which means there must be at most one insn
2969 : : in the combination with an EH side effect. */
2970 : 32525137 : if (cfun->can_throw_non_call_exceptions)
2971 : : {
2972 : 6004617 : if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2973 : 5980206 : || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2974 : 5980013 : || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2975 : 11984580 : || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2976 : : {
2977 : 24654 : has_non_call_exception = true;
2978 : 24654 : if (insn_could_throw_p (i3)
2979 : 24654 : + insn_could_throw_p (i2)
2980 : 24654 : + (i1 ? insn_could_throw_p (i1) : 0)
2981 : 24654 : + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2982 : : {
2983 : 359 : if (dump_file && (dump_flags & TDF_DETAILS))
2984 : 0 : fprintf (dump_file, "Can't combine multiple insns with EH "
2985 : : "side-effects\n");
2986 : 359 : undo_all ();
2987 : 359 : return 0;
2988 : : }
2989 : : }
2990 : : }
2991 : :
2992 : : /* Record whether i2 and i3 are trivial moves. */
2993 : 32524778 : i2_was_move = is_just_move (i2);
2994 : 32524778 : i3_was_move = is_just_move (i3);
2995 : :
2996 : : /* Record whether I2DEST is used in I2SRC and similarly for the other
2997 : : cases. Knowing this will help in register status updating below. */
2998 : 32524778 : i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2999 : 32524778 : i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3000 : 10302159 : i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3001 : 32524778 : i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3002 : 1599056 : i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3003 : 1599056 : i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3004 : 32524778 : i2dest_killed = dead_or_set_p (i2, i2dest);
3005 : 32524778 : i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3006 : 32524778 : i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3007 : :
3008 : : /* For the earlier insns, determine which of the subsequent ones they
3009 : : feed. */
3010 : 32524778 : i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3011 : 32524778 : i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3012 : 2802421 : i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3013 : 1203365 : : (!reg_overlap_mentioned_p (i1dest, i0dest)
3014 : 1175080 : && reg_overlap_mentioned_p (i0dest, i2src))));
3015 : :
3016 : : /* Ensure that I3's pattern can be the destination of combines. */
3017 : 32524778 : if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3018 : 32524778 : i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3019 : 1599056 : i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3020 : 1575091 : || (i1dest_in_i0src && !i0_feeds_i1_n)),
3021 : : &i3dest_killed))
3022 : : {
3023 : 213731 : undo_all ();
3024 : 213731 : return 0;
3025 : : }
3026 : :
3027 : : /* See if any of the insns is a MULT operation. Unless one is, we will
3028 : : reject a combination that is, since it must be slower. Be conservative
3029 : : here. */
3030 : 32311047 : if (GET_CODE (i2src) == MULT
3031 : 31459841 : || (i1 != 0 && GET_CODE (i1src) == MULT)
3032 : 31089495 : || (i0 != 0 && GET_CODE (i0src) == MULT)
3033 : 63350984 : || (GET_CODE (PATTERN (i3)) == SET
3034 : 23986256 : && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3035 : : have_mult = true;
3036 : :
3037 : : /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3038 : : We used to do this EXCEPT in one case: I3 has a post-inc in an
3039 : : output operand. However, that exception can give rise to insns like
3040 : : mov r3,(r3)+
3041 : : which is a famous insn on the PDP-11 where the value of r3 used as the
3042 : : source was model-dependent. Avoid this sort of thing. */
3043 : :
3044 : : #if 0
3045 : : if (!(GET_CODE (PATTERN (i3)) == SET
3046 : : && REG_P (SET_SRC (PATTERN (i3)))
3047 : : && MEM_P (SET_DEST (PATTERN (i3)))
3048 : : && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3049 : : || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3050 : : /* It's not the exception. */
3051 : : #endif
3052 : 32311047 : if (AUTO_INC_DEC)
3053 : : {
3054 : : rtx link;
3055 : : for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3056 : : if (REG_NOTE_KIND (link) == REG_INC
3057 : : && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3058 : : || (i1 != 0
3059 : : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3060 : : {
3061 : : undo_all ();
3062 : : return 0;
3063 : : }
3064 : : }
3065 : :
3066 : : /* See if the SETs in I1 or I2 need to be kept around in the merged
3067 : : instruction: whenever the value set there is still needed past I3.
3068 : : For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3069 : :
3070 : : For the SET in I1, we have two cases: if I1 and I2 independently feed
3071 : : into I3, the set in I1 needs to be kept around unless I1DEST dies
3072 : : or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3073 : : in I1 needs to be kept around unless I1DEST dies or is set in either
3074 : : I2 or I3. The same considerations apply to I0. */
3075 : :
3076 : 32311047 : added_sets_2 = !dead_or_set_p (i3, i2dest);
3077 : :
3078 : 32311047 : if (i1)
3079 : 10226738 : added_sets_1 = !(dead_or_set_p (i3, i1dest)
3080 : 7833399 : || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3081 : : else
3082 : : added_sets_1 = false;
3083 : :
3084 : 32311047 : if (i0)
3085 : 2253166 : added_sets_0 = !(dead_or_set_p (i3, i0dest)
3086 : 1412092 : || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3087 : 244362 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3088 : 635076 : && dead_or_set_p (i2, i0dest)));
3089 : : else
3090 : : added_sets_0 = false;
3091 : :
3092 : : /* We are about to copy insns for the case where they need to be kept
3093 : : around. Check that they can be copied in the merged instruction. */
3094 : :
3095 : 32311047 : if (targetm.cannot_copy_insn_p
3096 : 32311047 : && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3097 : 0 : || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3098 : 0 : || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3099 : : {
3100 : 0 : undo_all ();
3101 : 0 : return 0;
3102 : : }
3103 : :
3104 : : /* We cannot safely duplicate volatile references in any case. */
3105 : :
3106 : 7196512 : if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3107 : 32285979 : || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3108 : 64574313 : || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3109 : : {
3110 : 49835 : undo_all ();
3111 : 49835 : return 0;
3112 : : }
3113 : :
3114 : : /* Count how many auto_inc expressions there were in the original insns;
3115 : : we need to have the same number in the resulting patterns. */
3116 : :
3117 : 32261212 : if (i0)
3118 : 1564312 : for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3119 : 32261212 : if (i1)
3120 : 10201641 : for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3121 : 32261212 : for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3122 : 32261212 : for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3123 : :
3124 : : /* If the set in I2 needs to be kept around, we must make a copy of
3125 : : PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3126 : : PATTERN (I2), we are only substituting for the original I1DEST, not into
3127 : : an already-substituted copy. This also prevents making self-referential
3128 : : rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3129 : : I2DEST. */
3130 : :
3131 : 32261212 : if (added_sets_2)
3132 : : {
3133 : 7168840 : if (GET_CODE (PATTERN (i2)) == PARALLEL)
3134 : 2291567 : i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3135 : : else
3136 : 4877273 : i2pat = copy_rtx (PATTERN (i2));
3137 : : }
3138 : :
3139 : 32261212 : if (added_sets_1)
3140 : : {
3141 : 3717068 : if (GET_CODE (PATTERN (i1)) == PARALLEL)
3142 : 1221316 : i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3143 : : else
3144 : 2495752 : i1pat = copy_rtx (PATTERN (i1));
3145 : : }
3146 : :
3147 : 32261212 : if (added_sets_0)
3148 : : {
3149 : 343888 : if (GET_CODE (PATTERN (i0)) == PARALLEL)
3150 : 162326 : i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3151 : : else
3152 : 181562 : i0pat = copy_rtx (PATTERN (i0));
3153 : : }
3154 : :
3155 : 32261212 : combine_merges++;
3156 : :
3157 : : /* Substitute in the latest insn for the regs set by the earlier ones. */
3158 : :
3159 : 32261212 : maxreg = max_reg_num ();
3160 : :
3161 : 32261212 : subst_insn = i3;
3162 : :
3163 : : /* Many machines have insns that can both perform an
3164 : : arithmetic operation and set the condition code. These operations will
3165 : : be represented as a PARALLEL with the first element of the vector
3166 : : being a COMPARE of an arithmetic operation with the constant zero.
3167 : : The second element of the vector will set some pseudo to the result
3168 : : of the same arithmetic operation. If we simplify the COMPARE, we won't
3169 : : match such a pattern and so will generate an extra insn. Here we test
3170 : : for this case, where both the comparison and the operation result are
3171 : : needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3172 : : I2SRC. Later we will make the PARALLEL that contains I2. */
3173 : :
3174 : 22059571 : if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3175 : 4163100 : && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3176 : 1753223 : && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3177 : 33136852 : && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3178 : : {
3179 : 805461 : rtx newpat_dest;
3180 : 805461 : rtx *cc_use_loc = NULL;
3181 : 805461 : rtx_insn *cc_use_insn = NULL;
3182 : 805461 : rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3183 : 805461 : machine_mode compare_mode, orig_compare_mode;
3184 : 805461 : enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3185 : 805461 : scalar_int_mode mode;
3186 : :
3187 : 805461 : newpat = PATTERN (i3);
3188 : 805461 : newpat_dest = SET_DEST (newpat);
3189 : 805461 : compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3190 : :
3191 : 805461 : if (undobuf.other_insn == 0
3192 : 805461 : && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3193 : : &cc_use_insn)))
3194 : : {
3195 : 799199 : compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3196 : 799199 : if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3197 : 799199 : compare_code = simplify_compare_const (compare_code, mode,
3198 : : &op0, &op1);
3199 : 799199 : target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3200 : : }
3201 : :
3202 : : /* Do the rest only if op1 is const0_rtx, which may be the
3203 : : result of simplification. */
3204 : 805461 : if (op1 == const0_rtx)
3205 : : {
3206 : : /* If a single use of the CC is found, prepare to modify it
3207 : : when SELECT_CC_MODE returns a new CC-class mode, or when
3208 : : the above simplify_compare_const() returned a new comparison
3209 : : operator. undobuf.other_insn is assigned the CC use insn
3210 : : when modifying it. */
3211 : 495874 : if (cc_use_loc)
3212 : : {
3213 : : #ifdef SELECT_CC_MODE
3214 : 493276 : machine_mode new_mode
3215 : 493276 : = SELECT_CC_MODE (compare_code, op0, op1);
3216 : 493276 : if (new_mode != orig_compare_mode
3217 : 493276 : && can_change_dest_mode (SET_DEST (newpat),
3218 : : added_sets_2, new_mode))
3219 : : {
3220 : 433 : unsigned int regno = REGNO (newpat_dest);
3221 : 433 : compare_mode = new_mode;
3222 : 433 : if (regno < FIRST_PSEUDO_REGISTER)
3223 : 433 : newpat_dest = gen_rtx_REG (compare_mode, regno);
3224 : : else
3225 : : {
3226 : 0 : subst_mode (regno, compare_mode);
3227 : 0 : newpat_dest = regno_reg_rtx[regno];
3228 : : }
3229 : : }
3230 : : #endif
3231 : : /* Cases for modifying the CC-using comparison. */
3232 : 493276 : if (compare_code != orig_compare_code
3233 : 447 : && COMPARISON_P (*cc_use_loc))
3234 : : {
3235 : : /* Replace cc_use_loc with entire new RTX. */
3236 : 447 : SUBST (*cc_use_loc,
3237 : : gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3238 : : newpat_dest, const0_rtx));
3239 : 447 : undobuf.other_insn = cc_use_insn;
3240 : : }
3241 : 492829 : else if (compare_mode != orig_compare_mode)
3242 : : {
3243 : 1 : subrtx_ptr_iterator::array_type array;
3244 : :
3245 : : /* Just replace the CC reg with a new mode. */
3246 : 4 : FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3247 : : {
3248 : 3 : rtx *loc = *iter;
3249 : 3 : if (REG_P (*loc)
3250 : 3 : && REGNO (*loc) == REGNO (newpat_dest))
3251 : : {
3252 : 1 : SUBST (*loc, newpat_dest);
3253 : 1 : iter.skip_subrtxes ();
3254 : : }
3255 : : }
3256 : 1 : undobuf.other_insn = cc_use_insn;
3257 : 1 : }
3258 : : }
3259 : :
3260 : : /* Now we modify the current newpat:
3261 : : First, SET_DEST(newpat) is updated if the CC mode has been
3262 : : altered. For targets without SELECT_CC_MODE, this should be
3263 : : optimized away. */
3264 : 495874 : if (compare_mode != orig_compare_mode)
3265 : 433 : SUBST (SET_DEST (newpat), newpat_dest);
3266 : : /* This is always done to propagate i2src into newpat. */
3267 : 495874 : SUBST (SET_SRC (newpat),
3268 : : gen_rtx_COMPARE (compare_mode, op0, op1));
3269 : : /* Create new version of i2pat if needed; the below PARALLEL
3270 : : creation needs this to work correctly. */
3271 : 495874 : if (! rtx_equal_p (i2src, op0))
3272 : 27 : i2pat = gen_rtx_SET (i2dest, op0);
3273 : 495874 : i2_is_used = 1;
3274 : : }
3275 : : }
3276 : :
3277 : 805461 : if (i2_is_used == 0)
3278 : : {
3279 : : /* It is possible that the source of I2 or I1 may be performing
3280 : : an unneeded operation, such as a ZERO_EXTEND of something
3281 : : that is known to have the high part zero. Handle that case
3282 : : by letting subst look at the inner insns.
3283 : :
3284 : : Another way to do this would be to have a function that tries
3285 : : to simplify a single insn instead of merging two or more
3286 : : insns. We don't do this because of the potential of infinite
3287 : : loops and because of the potential extra memory required.
3288 : : However, doing it the way we are is a bit of a kludge and
3289 : : doesn't catch all cases.
3290 : :
3291 : : But only do this if -fexpensive-optimizations since it slows
3292 : : things down and doesn't usually win.
3293 : :
3294 : : This is not done in the COMPARE case above because the
3295 : : unmodified I2PAT is used in the PARALLEL and so a pattern
3296 : : with a modified I2SRC would not match. */
3297 : :
3298 : 31765338 : if (flag_expensive_optimizations)
3299 : : {
3300 : : /* Pass pc_rtx so no substitutions are done, just
3301 : : simplifications. */
3302 : 29806684 : if (i1)
3303 : : {
3304 : 9624299 : subst_low_luid = DF_INSN_LUID (i1);
3305 : 9624299 : i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3306 : : }
3307 : :
3308 : 29806684 : subst_low_luid = DF_INSN_LUID (i2);
3309 : 29806684 : i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3310 : : }
3311 : :
3312 : 31765338 : n_occurrences = 0; /* `subst' counts here */
3313 : 31765338 : subst_low_luid = DF_INSN_LUID (i2);
3314 : :
3315 : : /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3316 : : copy of I2SRC each time we substitute it, in order to avoid creating
3317 : : self-referential RTL when we will be substituting I1SRC for I1DEST
3318 : : later. Likewise if I0 feeds into I2, either directly or indirectly
3319 : : through I1, and I0DEST is in I0SRC. */
3320 : 31765338 : newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3321 : 31765338 : (i1_feeds_i2_n && i1dest_in_i1src)
3322 : 31765338 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3323 : : && i0dest_in_i0src));
3324 : 31765338 : substed_i2 = true;
3325 : :
3326 : : /* Record whether I2's body now appears within I3's body. */
3327 : 31765338 : i2_is_used = n_occurrences;
3328 : : }
3329 : :
3330 : : /* If we already got a failure, don't try to do more. Otherwise, try to
3331 : : substitute I1 if we have it. */
3332 : :
3333 : 32261212 : if (i1 && GET_CODE (newpat) != CLOBBER)
3334 : : {
3335 : : /* Before we can do this substitution, we must redo the test done
3336 : : above (see detailed comments there) that ensures I1DEST isn't
3337 : : mentioned in any SETs in NEWPAT that are field assignments. */
3338 : 10161243 : if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3339 : : false, false, 0))
3340 : : {
3341 : 37 : undo_all ();
3342 : 37 : return 0;
3343 : : }
3344 : :
3345 : 10161206 : n_occurrences = 0;
3346 : 10161206 : subst_low_luid = DF_INSN_LUID (i1);
3347 : :
3348 : : /* If the following substitution will modify I1SRC, make a copy of it
3349 : : for the case where it is substituted for I1DEST in I2PAT later. */
3350 : 10161206 : if (added_sets_2 && i1_feeds_i2_n)
3351 : 1463303 : i1src_copy = copy_rtx (i1src);
3352 : :
3353 : : /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3354 : : copy of I1SRC each time we substitute it, in order to avoid creating
3355 : : self-referential RTL when we will be substituting I0SRC for I0DEST
3356 : : later. */
3357 : 20322412 : newpat = subst (newpat, i1dest, i1src, false, false,
3358 : 10161206 : i0_feeds_i1_n && i0dest_in_i0src);
3359 : 10161206 : substed_i1 = true;
3360 : :
3361 : : /* Record whether I1's body now appears within I3's body. */
3362 : 10161206 : i1_is_used = n_occurrences;
3363 : : }
3364 : :
3365 : : /* Likewise for I0 if we have it. */
3366 : :
3367 : 32261175 : if (i0 && GET_CODE (newpat) != CLOBBER)
3368 : : {
3369 : 1551290 : if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3370 : : false, false, 0))
3371 : : {
3372 : 2 : undo_all ();
3373 : 2 : return 0;
3374 : : }
3375 : :
3376 : : /* If the following substitution will modify I0SRC, make a copy of it
3377 : : for the case where it is substituted for I0DEST in I1PAT later. */
3378 : 1551288 : if (added_sets_1 && i0_feeds_i1_n)
3379 : 229794 : i0src_copy = copy_rtx (i0src);
3380 : : /* And a copy for I0DEST in I2PAT substitution. */
3381 : 1551288 : if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3382 : 195996 : || (i0_feeds_i2_n)))
3383 : 317760 : i0src_copy2 = copy_rtx (i0src);
3384 : :
3385 : 1551288 : n_occurrences = 0;
3386 : 1551288 : subst_low_luid = DF_INSN_LUID (i0);
3387 : 1551288 : newpat = subst (newpat, i0dest, i0src, false, false, false);
3388 : 1551288 : substed_i0 = true;
3389 : : }
3390 : :
3391 : 32261173 : if (n_auto_inc)
3392 : : {
3393 : 511613 : int new_n_auto_inc = 0;
3394 : 511613 : for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3395 : :
3396 : 511613 : if (n_auto_inc != new_n_auto_inc)
3397 : : {
3398 : 1357 : if (dump_file && (dump_flags & TDF_DETAILS))
3399 : 0 : fprintf (dump_file, "Number of auto_inc expressions changed\n");
3400 : 1357 : undo_all ();
3401 : 1357 : return 0;
3402 : : }
3403 : : }
3404 : :
3405 : : /* Fail if an autoincrement side-effect has been duplicated. Be careful
3406 : : to count all the ways that I2SRC and I1SRC can be used. */
3407 : 32259816 : if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3408 : : && i2_is_used + added_sets_2 > 1)
3409 : : || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3410 : : && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3411 : : || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3412 : : && (n_occurrences + added_sets_0
3413 : : + (added_sets_1 && i0_feeds_i1_n)
3414 : : + (added_sets_2 && i0_feeds_i2_n) > 1))
3415 : : /* Fail if we tried to make a new register. */
3416 : 32259816 : || max_reg_num () != maxreg
3417 : : /* Fail if we couldn't do something and have a CLOBBER. */
3418 : 32259816 : || GET_CODE (newpat) == CLOBBER
3419 : : /* Fail if this new pattern is a MULT and we didn't have one before
3420 : : at the outer level. */
3421 : 64226358 : || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3422 : 260916 : && ! have_mult))
3423 : : {
3424 : 312775 : undo_all ();
3425 : 312775 : return 0;
3426 : : }
3427 : :
3428 : : /* If the actions of the earlier insns must be kept
3429 : : in addition to substituting them into the latest one,
3430 : : we must make a new PARALLEL for the latest insn
3431 : : to hold additional the SETs. */
3432 : :
3433 : 31947041 : if (added_sets_0 || added_sets_1 || added_sets_2)
3434 : : {
3435 : 10366957 : int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3436 : 10366957 : combine_extras++;
3437 : :
3438 : 10366957 : if (GET_CODE (newpat) == PARALLEL)
3439 : : {
3440 : 2184228 : rtvec old = XVEC (newpat, 0);
3441 : 2184228 : total_sets = XVECLEN (newpat, 0) + extra_sets;
3442 : 2184228 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3443 : 2184228 : memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3444 : 2184228 : sizeof (old->elem[0]) * old->num_elem);
3445 : : }
3446 : : else
3447 : : {
3448 : 8182729 : rtx old = newpat;
3449 : 8182729 : total_sets = 1 + extra_sets;
3450 : 8182729 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3451 : 8182729 : XVECEXP (newpat, 0, 0) = old;
3452 : : }
3453 : :
3454 : 10366957 : if (added_sets_0)
3455 : 333577 : XVECEXP (newpat, 0, --total_sets) = i0pat;
3456 : :
3457 : 10366957 : if (added_sets_1)
3458 : : {
3459 : 3678025 : rtx t = i1pat;
3460 : 3678025 : if (i0_feeds_i1_n)
3461 : 229481 : t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3462 : : false, false, false);
3463 : :
3464 : 3678025 : XVECEXP (newpat, 0, --total_sets) = t;
3465 : : }
3466 : 10366957 : if (added_sets_2)
3467 : : {
3468 : 7126889 : rtx t = i2pat;
3469 : 7126889 : if (i1_feeds_i2_n)
3470 : 1451937 : t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3471 : 1451937 : i0_feeds_i1_n && i0dest_in_i0src);
3472 : 7126889 : if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3473 : 316695 : t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3474 : : false, false, false);
3475 : :
3476 : 7126889 : XVECEXP (newpat, 0, --total_sets) = t;
3477 : : }
3478 : : }
3479 : :
3480 : 24820152 : validate_replacement:
3481 : :
3482 : : /* Note which hard regs this insn has as inputs. */
3483 : 32287594 : mark_used_regs_combine (newpat);
3484 : :
3485 : : /* If recog_for_combine fails, it strips existing clobbers. If we'll
3486 : : consider splitting this pattern, we might need these clobbers. */
3487 : 32287594 : if (i1 && GET_CODE (newpat) == PARALLEL
3488 : 7060705 : && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3489 : : {
3490 : 1809244 : int len = XVECLEN (newpat, 0);
3491 : :
3492 : 1809244 : newpat_vec_with_clobbers = rtvec_alloc (len);
3493 : 7288379 : for (i = 0; i < len; i++)
3494 : 3669891 : RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3495 : : }
3496 : :
3497 : : /* We have recognized nothing yet. */
3498 : 32287594 : insn_code_number = -1;
3499 : :
3500 : : /* See if this is a PARALLEL of two SETs where one SET's destination is
3501 : : a register that is unused and this isn't marked as an instruction that
3502 : : might trap in an EH region. In that case, we just need the other SET.
3503 : : We prefer this over the PARALLEL.
3504 : :
3505 : : This can occur when simplifying a divmod insn. We *must* test for this
3506 : : case here because the code below that splits two independent SETs doesn't
3507 : : handle this case correctly when it updates the register status.
3508 : :
3509 : : It's pointless doing this if we originally had two sets, one from
3510 : : i3, and one from i2. Combining then splitting the parallel results
3511 : : in the original i2 again plus an invalid insn (which we delete).
3512 : : The net effect is only to move instructions around, which makes
3513 : : debug info less accurate.
3514 : :
3515 : : If the remaining SET came from I2 its destination should not be used
3516 : : between I2 and I3. See PR82024. */
3517 : :
3518 : 7126889 : if (!(added_sets_2 && i1 == 0)
3519 : 27100227 : && is_parallel_of_n_reg_sets (newpat, 2)
3520 : 33821174 : && asm_noperands (newpat) < 0)
3521 : : {
3522 : 1532773 : rtx set0 = XVECEXP (newpat, 0, 0);
3523 : 1532773 : rtx set1 = XVECEXP (newpat, 0, 1);
3524 : 1532773 : rtx oldpat = newpat;
3525 : :
3526 : 1532773 : if (((REG_P (SET_DEST (set1))
3527 : 1532773 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3528 : 1493334 : || (GET_CODE (SET_DEST (set1)) == SUBREG
3529 : 0 : && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3530 : 39439 : && insn_nothrow_p (i3)
3531 : 1570975 : && !side_effects_p (SET_SRC (set1)))
3532 : : {
3533 : 38010 : newpat = set0;
3534 : 38010 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3535 : : }
3536 : :
3537 : 1494763 : else if (((REG_P (SET_DEST (set0))
3538 : 1494763 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3539 : 1470835 : || (GET_CODE (SET_DEST (set0)) == SUBREG
3540 : 0 : && find_reg_note (i3, REG_UNUSED,
3541 : 0 : SUBREG_REG (SET_DEST (set0)))))
3542 : 23928 : && insn_nothrow_p (i3)
3543 : 1518041 : && !side_effects_p (SET_SRC (set0)))
3544 : : {
3545 : 23237 : rtx dest = SET_DEST (set1);
3546 : 23237 : if (GET_CODE (dest) == SUBREG)
3547 : 0 : dest = SUBREG_REG (dest);
3548 : 23237 : if (!reg_used_between_p (dest, i2, i3))
3549 : : {
3550 : 23236 : newpat = set1;
3551 : 23236 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3552 : :
3553 : 23236 : if (insn_code_number >= 0)
3554 : : changed_i3_dest = true;
3555 : : }
3556 : : }
3557 : :
3558 : 38010 : if (insn_code_number < 0)
3559 : 1527504 : newpat = oldpat;
3560 : : }
3561 : :
3562 : : /* Is the result of combination a valid instruction? */
3563 : 1527504 : if (insn_code_number < 0)
3564 : 32282325 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3565 : :
3566 : : /* If we were combining three insns and the result is a simple SET
3567 : : with no ASM_OPERANDS that wasn't recognized, try to split it into two
3568 : : insns. There are two ways to do this. It can be split using a
3569 : : machine-specific method (like when you have an addition of a large
3570 : : constant) or by combine in the function find_split_point. */
3571 : :
3572 : 10032840 : if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3573 : 36987957 : && asm_noperands (newpat) < 0)
3574 : : {
3575 : 4699922 : rtx parallel, *split;
3576 : 4699922 : rtx_insn *m_split_insn;
3577 : 4699922 : unsigned int old_nregs, new_nregs;
3578 : :
3579 : : /* See if the MD file can split NEWPAT. If it can't, see if letting it
3580 : : use I2DEST as a scratch register will help. In the latter case,
3581 : : convert I2DEST to the mode of the source of NEWPAT if we can. */
3582 : :
3583 : 4699922 : m_split_insn = combine_split_insns (newpat, i3, &old_nregs, &new_nregs);
3584 : :
3585 : : /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3586 : : inputs of NEWPAT. */
3587 : :
3588 : : /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3589 : : possible to try that as a scratch reg. This would require adding
3590 : : more code to make it work though. */
3591 : :
3592 : 4699922 : if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3593 : : {
3594 : 4564355 : machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3595 : :
3596 : : /* ??? Reusing i2dest without resetting the reg_stat entry for it
3597 : : (temporarily, until we are committed to this instruction
3598 : : combination) does not work: for example, any call to nonzero_bits
3599 : : on the register (from a splitter in the MD file, for example)
3600 : : will get the old information, which is invalid.
3601 : :
3602 : : Since nowadays we can create registers during combine just fine,
3603 : : we should just create a new one here, not reuse i2dest. */
3604 : :
3605 : : /* First try to split using the original register as a
3606 : : scratch register. */
3607 : 4564355 : parallel = gen_rtx_PARALLEL (VOIDmode,
3608 : : gen_rtvec (2, newpat,
3609 : : gen_rtx_CLOBBER (VOIDmode,
3610 : : i2dest)));
3611 : 4564355 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3612 : :
3613 : : /* If that didn't work, try changing the mode of I2DEST if
3614 : : we can. */
3615 : 4564355 : if (m_split_insn == 0
3616 : 4564355 : && new_mode != GET_MODE (i2dest)
3617 : 1666476 : && new_mode != VOIDmode
3618 : 5700299 : && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3619 : : {
3620 : 856843 : machine_mode old_mode = GET_MODE (i2dest);
3621 : 856843 : rtx ni2dest;
3622 : :
3623 : 856843 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3624 : 11347 : ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3625 : : else
3626 : : {
3627 : 845496 : subst_mode (REGNO (i2dest), new_mode);
3628 : 845496 : ni2dest = regno_reg_rtx[REGNO (i2dest)];
3629 : : }
3630 : :
3631 : 856843 : parallel = (gen_rtx_PARALLEL
3632 : : (VOIDmode,
3633 : : gen_rtvec (2, newpat,
3634 : : gen_rtx_CLOBBER (VOIDmode,
3635 : : ni2dest))));
3636 : 856843 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3637 : :
3638 : 856843 : if (m_split_insn == 0
3639 : 856843 : && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3640 : : {
3641 : 845496 : struct undo *buf;
3642 : :
3643 : 845496 : adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3644 : 845496 : buf = undobuf.undos;
3645 : 845496 : undobuf.undos = buf->next;
3646 : 845496 : buf->next = undobuf.frees;
3647 : 845496 : undobuf.frees = buf;
3648 : : }
3649 : : }
3650 : :
3651 : 4564355 : i2scratch = m_split_insn != 0;
3652 : : }
3653 : :
3654 : : /* If recog_for_combine has discarded clobbers, try to use them
3655 : : again for the split. */
3656 : 4699922 : if (m_split_insn == 0 && newpat_vec_with_clobbers)
3657 : : {
3658 : 1757407 : parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3659 : 1757407 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3660 : : }
3661 : :
3662 : 4712860 : if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3663 : : {
3664 : 1405 : rtx m_split_pat = PATTERN (m_split_insn);
3665 : 1405 : insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes,
3666 : : old_nregs, new_nregs);
3667 : 1405 : if (insn_code_number >= 0)
3668 : 172 : newpat = m_split_pat;
3669 : : }
3670 : 11533 : else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3671 : 4710050 : && (next_nonnote_nondebug_insn (i2) == i3
3672 : 6 : || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3673 : : {
3674 : 11533 : rtx i2set, i3set;
3675 : 11533 : rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3676 : 11533 : newi2pat = PATTERN (m_split_insn);
3677 : :
3678 : 11533 : i3set = single_set (NEXT_INSN (m_split_insn));
3679 : 11533 : i2set = single_set (m_split_insn);
3680 : :
3681 : 11533 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3682 : :
3683 : : /* If I2 or I3 has multiple SETs, we won't know how to track
3684 : : register status, so don't use these insns. If I2's destination
3685 : : is used between I2 and I3, we also can't use these insns. */
3686 : :
3687 : 11533 : if (i2_code_number >= 0 && i2set && i3set
3688 : 23066 : && (next_nonnote_nondebug_insn (i2) == i3
3689 : 6 : || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3690 : 11533 : insn_code_number = recog_for_combine (&newi3pat, i3,
3691 : : &new_i3_notes,
3692 : : old_nregs, new_nregs);
3693 : 11533 : if (insn_code_number >= 0)
3694 : 11533 : newpat = newi3pat;
3695 : :
3696 : : /* It is possible that both insns now set the destination of I3.
3697 : : If so, we must show an extra use of it. */
3698 : :
3699 : 11533 : if (insn_code_number >= 0)
3700 : : {
3701 : 11533 : rtx new_i3_dest = SET_DEST (i3set);
3702 : 11533 : rtx new_i2_dest = SET_DEST (i2set);
3703 : :
3704 : 11533 : while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3705 : 11573 : || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3706 : 23128 : || GET_CODE (new_i3_dest) == SUBREG)
3707 : 40 : new_i3_dest = XEXP (new_i3_dest, 0);
3708 : :
3709 : 11533 : while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3710 : 11533 : || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3711 : 23066 : || GET_CODE (new_i2_dest) == SUBREG)
3712 : 0 : new_i2_dest = XEXP (new_i2_dest, 0);
3713 : :
3714 : 11533 : if (REG_P (new_i3_dest)
3715 : 7701 : && REG_P (new_i2_dest)
3716 : 7701 : && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3717 : 11533 : && REGNO (new_i2_dest) < reg_n_sets_max)
3718 : 0 : INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3719 : : }
3720 : : }
3721 : :
3722 : : /* If we can split it and use I2DEST, go ahead and see if that
3723 : : helps things be recognized. Verify that none of the registers
3724 : : are set between I2 and I3. */
3725 : 1233 : if (insn_code_number < 0
3726 : 4688217 : && (split = find_split_point (&newpat, i3, false)) != 0
3727 : : /* We need I2DEST in the proper mode. If it is a hard register
3728 : : or the only use of a pseudo, we can change its mode.
3729 : : Make sure we don't change a hard register to have a mode that
3730 : : isn't valid for it, or change the number of registers. */
3731 : 4464840 : && (GET_MODE (*split) == GET_MODE (i2dest)
3732 : 1630108 : || GET_MODE (*split) == VOIDmode
3733 : 1266385 : || can_change_dest_mode (i2dest, added_sets_2,
3734 : : GET_MODE (*split)))
3735 : 3813577 : && (next_nonnote_nondebug_insn (i2) == i3
3736 : 596570 : || !modified_between_p (*split, i2, i3))
3737 : : /* We can't overwrite I2DEST if its value is still used by
3738 : : NEWPAT. */
3739 : 3781288 : && ! reg_referenced_p (i2dest, newpat)
3740 : : /* We should not split a possibly trapping part when we
3741 : : care about non-call EH and have REG_EH_REGION notes
3742 : : to distribute. */
3743 : 8412285 : && ! (cfun->can_throw_non_call_exceptions
3744 : 356879 : && has_non_call_exception
3745 : 126 : && may_trap_p (*split)))
3746 : : {
3747 : 3713470 : rtx newdest = i2dest;
3748 : 3713470 : enum rtx_code split_code = GET_CODE (*split);
3749 : 3713470 : machine_mode split_mode = GET_MODE (*split);
3750 : 3713470 : bool subst_done = false;
3751 : 3713470 : newi2pat = NULL_RTX;
3752 : :
3753 : 3713470 : i2scratch = true;
3754 : :
3755 : : /* *SPLIT may be part of I2SRC, so make sure we have the
3756 : : original expression around for later debug processing.
3757 : : We should not need I2SRC any more in other cases. */
3758 : 3713470 : if (MAY_HAVE_DEBUG_BIND_INSNS)
3759 : 1913349 : i2src = copy_rtx (i2src);
3760 : : else
3761 : 1800121 : i2src = NULL;
3762 : :
3763 : : /* Get NEWDEST as a register in the proper mode. We have already
3764 : : validated that we can do this. */
3765 : 3713470 : if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3766 : : {
3767 : 612985 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3768 : 0 : newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3769 : : else
3770 : : {
3771 : 612985 : subst_mode (REGNO (i2dest), split_mode);
3772 : 612985 : newdest = regno_reg_rtx[REGNO (i2dest)];
3773 : : }
3774 : : }
3775 : :
3776 : : /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3777 : : an ASHIFT. This can occur if it was inside a PLUS and hence
3778 : : appeared to be a memory address. This is a kludge. */
3779 : 3713470 : if (split_code == MULT
3780 : 225387 : && CONST_INT_P (XEXP (*split, 1))
3781 : 128567 : && INTVAL (XEXP (*split, 1)) > 0
3782 : 3837275 : && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3783 : : {
3784 : 72273 : rtx i_rtx = gen_int_shift_amount (split_mode, i);
3785 : 72273 : SUBST (*split, gen_rtx_ASHIFT (split_mode,
3786 : : XEXP (*split, 0), i_rtx));
3787 : : /* Update split_code because we may not have a multiply
3788 : : anymore. */
3789 : 72273 : split_code = GET_CODE (*split);
3790 : : }
3791 : :
3792 : : /* Similarly for (plus (mult FOO (const_int pow2))). */
3793 : 3713470 : if (split_code == PLUS
3794 : 680979 : && GET_CODE (XEXP (*split, 0)) == MULT
3795 : 113988 : && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3796 : 44804 : && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3797 : 3754407 : && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3798 : : {
3799 : 6773 : rtx nsplit = XEXP (*split, 0);
3800 : 6773 : rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3801 : 6773 : SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3802 : : XEXP (nsplit, 0),
3803 : : i_rtx));
3804 : : /* Update split_code because we may not have a multiply
3805 : : anymore. */
3806 : 6773 : split_code = GET_CODE (*split);
3807 : : }
3808 : :
3809 : : #ifdef INSN_SCHEDULING
3810 : : /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3811 : : be written as a ZERO_EXTEND. */
3812 : 3713470 : if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3813 : : {
3814 : : /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3815 : : what it really is. */
3816 : 12677 : if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3817 : : == SIGN_EXTEND)
3818 : : SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3819 : : SUBREG_REG (*split)));
3820 : : else
3821 : 12677 : SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3822 : : SUBREG_REG (*split)));
3823 : : }
3824 : : #endif
3825 : :
3826 : : /* Attempt to split binary operators using arithmetic identities. */
3827 : 3713470 : if (BINARY_P (SET_SRC (newpat))
3828 : 3111650 : && split_mode == GET_MODE (SET_SRC (newpat))
3829 : 5867466 : && ! side_effects_p (SET_SRC (newpat)))
3830 : : {
3831 : 2136933 : rtx setsrc = SET_SRC (newpat);
3832 : 2136933 : machine_mode mode = GET_MODE (setsrc);
3833 : 2136933 : enum rtx_code code = GET_CODE (setsrc);
3834 : 2136933 : rtx src_op0 = XEXP (setsrc, 0);
3835 : 2136933 : rtx src_op1 = XEXP (setsrc, 1);
3836 : :
3837 : : /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3838 : 2136933 : if (rtx_equal_p (src_op0, src_op1))
3839 : : {
3840 : 1456 : newi2pat = gen_rtx_SET (newdest, src_op0);
3841 : 1456 : SUBST (XEXP (setsrc, 0), newdest);
3842 : 1456 : SUBST (XEXP (setsrc, 1), newdest);
3843 : 1456 : subst_done = true;
3844 : : }
3845 : : /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3846 : 2135477 : else if ((code == PLUS || code == MULT)
3847 : 996612 : && GET_CODE (src_op0) == code
3848 : 414823 : && GET_CODE (XEXP (src_op0, 0)) == code
3849 : 172481 : && (INTEGRAL_MODE_P (mode)
3850 : : || (FLOAT_MODE_P (mode)
3851 : 99120 : && flag_unsafe_math_optimizations)))
3852 : : {
3853 : 77392 : rtx p = XEXP (XEXP (src_op0, 0), 0);
3854 : 77392 : rtx q = XEXP (XEXP (src_op0, 0), 1);
3855 : 77392 : rtx r = XEXP (src_op0, 1);
3856 : 77392 : rtx s = src_op1;
3857 : :
3858 : : /* Split both "((X op Y) op X) op Y" and
3859 : : "((X op Y) op Y) op X" as "T op T" where T is
3860 : : "X op Y". */
3861 : 77589 : if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3862 : 77516 : || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3863 : : {
3864 : 73 : newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3865 : 73 : SUBST (XEXP (setsrc, 0), newdest);
3866 : 73 : SUBST (XEXP (setsrc, 1), newdest);
3867 : 73 : subst_done = true;
3868 : : }
3869 : : /* Split "((X op X) op Y) op Y)" as "T op T" where
3870 : : T is "X op Y". */
3871 : 77319 : else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3872 : : {
3873 : 24 : rtx tmp = simplify_gen_binary (code, mode, p, r);
3874 : 24 : newi2pat = gen_rtx_SET (newdest, tmp);
3875 : 24 : SUBST (XEXP (setsrc, 0), newdest);
3876 : 24 : SUBST (XEXP (setsrc, 1), newdest);
3877 : 24 : subst_done = true;
3878 : : }
3879 : : }
3880 : : }
3881 : :
3882 : 1553 : if (!subst_done)
3883 : : {
3884 : 3711917 : newi2pat = gen_rtx_SET (newdest, *split);
3885 : 3711917 : SUBST (*split, newdest);
3886 : : }
3887 : :
3888 : 3713470 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3889 : :
3890 : : /* recog_for_combine might have added CLOBBERs to newi2pat.
3891 : : Make sure NEWPAT does not depend on the clobbered regs. */
3892 : 3713470 : if (GET_CODE (newi2pat) == PARALLEL)
3893 : 2788500 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3894 : 1871732 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3895 : : {
3896 : 954964 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3897 : 954964 : if (reg_overlap_mentioned_p (reg, newpat))
3898 : : {
3899 : 18888 : undo_all ();
3900 : 18888 : return 0;
3901 : : }
3902 : : }
3903 : :
3904 : : /* If the split point was a MULT and we didn't have one before,
3905 : : don't use one now. */
3906 : 3694582 : if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3907 : 2252681 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3908 : : }
3909 : : }
3910 : :
3911 : : /* Check for a case where we loaded from memory in a narrow mode and
3912 : : then sign extended it, but we need both registers. In that case,
3913 : : we have a PARALLEL with both loads from the same memory location.
3914 : : We can split this into a load from memory followed by a register-register
3915 : : copy. This saves at least one insn, more if register allocation can
3916 : : eliminate the copy.
3917 : :
3918 : : We cannot do this if the involved modes have more than one elements,
3919 : : like for vector or complex modes.
3920 : :
3921 : : We cannot do this if the destination of the first assignment is a
3922 : : condition code register. We eliminate this case by making sure
3923 : : the SET_DEST and SET_SRC have the same mode.
3924 : :
3925 : : We cannot do this if the destination of the second assignment is
3926 : : a register that we have already assumed is zero-extended. Similarly
3927 : : for a SUBREG of such a register. */
3928 : :
3929 : 5332918 : else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3930 : 5281051 : && GET_CODE (newpat) == PARALLEL
3931 : 5278908 : && XVECLEN (newpat, 0) == 2
3932 : 4446834 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3933 : 4446643 : && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3934 : 22641 : && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3935 : 22641 : == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3936 : 22641 : && ! VECTOR_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3937 : : && ! COMPLEX_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3938 : 21275 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3939 : 21275 : && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3940 : 21275 : XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3941 : 6071 : && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3942 : 6071 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3943 : 6071 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3944 : 6071 : && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3945 : : (REG_P (temp_expr)
3946 : 6071 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3947 : 6209 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3948 : : BITS_PER_WORD)
3949 : 5942 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3950 : : HOST_BITS_PER_INT)
3951 : 1161 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3952 : 1161 : != GET_MODE_MASK (word_mode))))
3953 : 6002 : && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3954 : 0 : && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3955 : 0 : (REG_P (temp_expr)
3956 : 0 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3957 : 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3958 : : BITS_PER_WORD)
3959 : 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3960 : : HOST_BITS_PER_INT)
3961 : 0 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3962 : 0 : != GET_MODE_MASK (word_mode)))))
3963 : 6002 : && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3964 : 6002 : SET_SRC (XVECEXP (newpat, 0, 1)))
3965 : 27593603 : && ! find_reg_note (i3, REG_UNUSED,
3966 : 5931 : SET_DEST (XVECEXP (newpat, 0, 0))))
3967 : : {
3968 : 5931 : rtx ni2dest;
3969 : :
3970 : 5931 : newi2pat = XVECEXP (newpat, 0, 0);
3971 : 5931 : ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3972 : 5931 : newpat = XVECEXP (newpat, 0, 1);
3973 : 5931 : SUBST (SET_SRC (newpat),
3974 : : gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3975 : 5931 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3976 : :
3977 : 5931 : if (i2_code_number >= 0)
3978 : 0 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3979 : :
3980 : 5931 : if (insn_code_number >= 0)
3981 : : swap_i2i3 = 1;
3982 : : }
3983 : :
3984 : : /* Similarly, check for a case where we have a PARALLEL of two independent
3985 : : SETs but we started with three insns. In this case, we can do the sets
3986 : : as two separate insns. This case occurs when some SET allows two
3987 : : other insns to combine, but the destination of that SET is still live.
3988 : :
3989 : : Also do this if we started with two insns and (at least) one of the
3990 : : resulting sets is a noop; this noop will be deleted later.
3991 : :
3992 : : Also do this if we started with two insns neither of which was a simple
3993 : : move. */
3994 : :
3995 : 23722060 : else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3996 : 23705294 : && GET_CODE (newpat) == PARALLEL
3997 : 10598020 : && XVECLEN (newpat, 0) == 2
3998 : 9651115 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3999 : 9550299 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4000 : 9495668 : && (i1
4001 : 5072170 : || set_noop_p (XVECEXP (newpat, 0, 0))
4002 : 5071782 : || set_noop_p (XVECEXP (newpat, 0, 1))
4003 : 5071774 : || (!i2_was_move && !i3_was_move))
4004 : 6245876 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4005 : 6245161 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4006 : 6244989 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4007 : 6244419 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4008 : 6244407 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4009 : : XVECEXP (newpat, 0, 0))
4010 : 5160974 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4011 : 5160974 : XVECEXP (newpat, 0, 1))
4012 : 33049227 : && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4013 : 438760 : && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4014 : : {
4015 : 4805093 : rtx set0 = XVECEXP (newpat, 0, 0);
4016 : 4805093 : rtx set1 = XVECEXP (newpat, 0, 1);
4017 : :
4018 : : /* Normally, it doesn't matter which of the two is done first, but
4019 : : one which uses any regs/memory set or used in between i2 and i3
4020 : : can't be first. The PARALLEL might also have been pre-existing
4021 : : in i3, so we need to make sure that we won't wrongly hoist a SET
4022 : : to i2 that would conflict with a death note present in there, or
4023 : : would have its dest modified or used between i2 and i3. */
4024 : 4805093 : if ((set_noop_p (set1)
4025 : 4805093 : || (!modified_between_p (SET_SRC (set1), i2, i3)
4026 : 9559587 : && !(REG_P (SET_DEST (set1))
4027 : 4762868 : && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4028 : 4830289 : && !(GET_CODE (SET_DEST (set1)) == SUBREG
4029 : 33851 : && find_reg_note (i2, REG_DEAD,
4030 : 33851 : SUBREG_REG (SET_DEST (set1))))
4031 : 4796438 : && SET_DEST (set1) != pc_rtx
4032 : 4796438 : && !reg_used_between_p (SET_DEST (set1), i2, i3)))
4033 : : /* If I3 is a jump, ensure that set0 is a jump so that
4034 : : we do not create invalid RTL. */
4035 : 9601525 : && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx))
4036 : : {
4037 : 4796432 : newi2pat = set1;
4038 : 4796432 : newpat = set0;
4039 : : }
4040 : 8661 : else if ((set_noop_p (set0)
4041 : 8655 : || (!modified_between_p (SET_SRC (set0), i2, i3)
4042 : 566 : && !(REG_P (SET_DEST (set0))
4043 : 283 : && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4044 : 283 : && !(GET_CODE (SET_DEST (set0)) == SUBREG
4045 : 0 : && find_reg_note (i2, REG_DEAD,
4046 : 0 : SUBREG_REG (SET_DEST (set0))))
4047 : 283 : && SET_DEST (set0) != pc_rtx
4048 : 283 : && !reg_used_between_p (SET_DEST (set0), i2, i3)))
4049 : : /* If I3 is a jump, ensure that set1 is a jump so that
4050 : : we do not create invalid RTL. */
4051 : 8944 : && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx))
4052 : : {
4053 : 289 : newi2pat = set0;
4054 : 289 : newpat = set1;
4055 : : }
4056 : : else
4057 : : {
4058 : 8372 : undo_all ();
4059 : 8372 : return 0;
4060 : : }
4061 : :
4062 : 4796721 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4063 : :
4064 : 4796721 : if (i2_code_number >= 0)
4065 : : {
4066 : : /* recog_for_combine might have added CLOBBERs to newi2pat.
4067 : : Make sure NEWPAT does not depend on the clobbered regs. */
4068 : 3488822 : if (GET_CODE (newi2pat) == PARALLEL)
4069 : : {
4070 : 1329231 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4071 : 890436 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4072 : : {
4073 : 451641 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4074 : 451641 : if (reg_overlap_mentioned_p (reg, newpat))
4075 : : {
4076 : 2767 : undo_all ();
4077 : 2767 : return 0;
4078 : : }
4079 : : }
4080 : : }
4081 : :
4082 : 3486055 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4083 : :
4084 : : /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4085 : : Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4086 : : mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4087 : 3486055 : if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4088 : : {
4089 : 61658 : for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4090 : 41116 : if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4091 : : {
4092 : 20574 : rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4093 : 20574 : if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4094 : 20574 : || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4095 : : {
4096 : 0 : undo_all ();
4097 : 0 : return 0;
4098 : : }
4099 : : }
4100 : : }
4101 : :
4102 : : if (insn_code_number >= 0)
4103 : : split_i2i3 = true;
4104 : : }
4105 : : }
4106 : :
4107 : : /* If it still isn't recognized, fail and change things back the way they
4108 : : were. */
4109 : 28765581 : if ((insn_code_number < 0
4110 : : /* Is the result a reasonable ASM_OPERANDS? */
4111 : 32093822 : && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4112 : : {
4113 : 28175621 : undo_all ();
4114 : 28175621 : return 0;
4115 : : }
4116 : :
4117 : : /* If we had to change another insn, make sure it is valid also. */
4118 : 4081946 : if (undobuf.other_insn)
4119 : : {
4120 : 217963 : CLEAR_HARD_REG_SET (newpat_used_regs);
4121 : :
4122 : 217963 : other_pat = PATTERN (undobuf.other_insn);
4123 : 217963 : other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4124 : : &new_other_notes);
4125 : :
4126 : 217963 : if (other_code_number < 0 && ! check_asm_operands (other_pat))
4127 : : {
4128 : 8879 : undo_all ();
4129 : 8879 : return 0;
4130 : : }
4131 : : }
4132 : :
4133 : : /* Reject this combination if insn_cost reports that the replacement
4134 : : instructions are more expensive than the originals. */
4135 : 4073067 : if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4136 : : {
4137 : 212471 : undo_all ();
4138 : 212471 : return 0;
4139 : : }
4140 : :
4141 : 3860596 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4142 : : {
4143 : 2227312 : struct undo *undo;
4144 : :
4145 : 6814137 : for (undo = undobuf.undos; undo; undo = undo->next)
4146 : 4586825 : if (undo->kind == UNDO_MODE)
4147 : : {
4148 : 3515 : rtx reg = regno_reg_rtx[undo->where.regno];
4149 : 3515 : machine_mode new_mode = GET_MODE (reg);
4150 : 3515 : machine_mode old_mode = undo->old_contents.m;
4151 : :
4152 : : /* Temporarily revert mode back. */
4153 : 3515 : adjust_reg_mode (reg, old_mode);
4154 : :
4155 : 3515 : if (reg == i2dest && i2scratch)
4156 : : {
4157 : : /* If we used i2dest as a scratch register with a
4158 : : different mode, substitute it for the original
4159 : : i2src while its original mode is temporarily
4160 : : restored, and then clear i2scratch so that we don't
4161 : : do it again later. */
4162 : 3515 : propagate_for_debug (i2, last_combined_insn, reg, i2src,
4163 : : this_basic_block);
4164 : 3515 : i2scratch = false;
4165 : : /* Put back the new mode. */
4166 : 3515 : adjust_reg_mode (reg, new_mode);
4167 : : }
4168 : : else
4169 : : {
4170 : 0 : rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4171 : 0 : rtx_insn *first, *last;
4172 : :
4173 : 0 : if (reg == i2dest)
4174 : : {
4175 : : first = i2;
4176 : : last = last_combined_insn;
4177 : : }
4178 : : else
4179 : : {
4180 : 0 : first = i3;
4181 : 0 : last = undobuf.other_insn;
4182 : 0 : gcc_assert (last);
4183 : 0 : if (DF_INSN_LUID (last)
4184 : 0 : < DF_INSN_LUID (last_combined_insn))
4185 : 0 : last = last_combined_insn;
4186 : : }
4187 : :
4188 : : /* We're dealing with a reg that changed mode but not
4189 : : meaning, so we want to turn it into a subreg for
4190 : : the new mode. However, because of REG sharing and
4191 : : because its mode had already changed, we have to do
4192 : : it in two steps. First, replace any debug uses of
4193 : : reg, with its original mode temporarily restored,
4194 : : with this copy we have created; then, replace the
4195 : : copy with the SUBREG of the original shared reg,
4196 : : once again changed to the new mode. */
4197 : 0 : propagate_for_debug (first, last, reg, tempreg,
4198 : : this_basic_block);
4199 : 0 : adjust_reg_mode (reg, new_mode);
4200 : 0 : propagate_for_debug (first, last, tempreg,
4201 : : lowpart_subreg (old_mode, reg, new_mode),
4202 : : this_basic_block);
4203 : : }
4204 : : }
4205 : : }
4206 : :
4207 : : /* If we will be able to accept this, we have made a
4208 : : change to the destination of I3. This requires us to
4209 : : do a few adjustments. */
4210 : :
4211 : 3860596 : if (changed_i3_dest)
4212 : : {
4213 : 18212 : PATTERN (i3) = newpat;
4214 : 18212 : adjust_for_new_dest (i3);
4215 : : }
4216 : :
4217 : 3860596 : bool only_i3_changed = !i0 && !i1 && rtx_equal_p (newi2pat, PATTERN (i2));
4218 : :
4219 : : /* If only i3 has changed, any split of the combined instruction just
4220 : : restored i2 to its original state. No destinations moved from i3
4221 : : to i2. */
4222 : : if (only_i3_changed)
4223 : : split_i2i3 = false;
4224 : :
4225 : : /* We now know that we can do this combination. Merge the insns and
4226 : : update the status of registers and LOG_LINKS. */
4227 : :
4228 : 3860596 : if (undobuf.other_insn)
4229 : : {
4230 : 208967 : rtx note, next;
4231 : :
4232 : 208967 : PATTERN (undobuf.other_insn) = other_pat;
4233 : :
4234 : : /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4235 : : ensure that they are still valid. Then add any non-duplicate
4236 : : notes added by recog_for_combine. */
4237 : 623803 : for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4238 : : {
4239 : 414836 : next = XEXP (note, 1);
4240 : :
4241 : 414836 : if ((REG_NOTE_KIND (note) == REG_DEAD
4242 : 211849 : && !reg_referenced_p (XEXP (note, 0),
4243 : 211849 : PATTERN (undobuf.other_insn)))
4244 : 409757 : ||(REG_NOTE_KIND (note) == REG_UNUSED
4245 : 28 : && !reg_set_p (XEXP (note, 0),
4246 : 28 : PATTERN (undobuf.other_insn)))
4247 : : /* Simply drop equal note since it may be no longer valid
4248 : : for other_insn. It may be possible to record that CC
4249 : : register is changed and only discard those notes, but
4250 : : in practice it's unnecessary complication and doesn't
4251 : : give any meaningful improvement.
4252 : :
4253 : : See PR78559. */
4254 : 409757 : || REG_NOTE_KIND (note) == REG_EQUAL
4255 : 824451 : || REG_NOTE_KIND (note) == REG_EQUIV)
4256 : 5221 : remove_note (undobuf.other_insn, note);
4257 : : }
4258 : :
4259 : 208967 : distribute_notes (new_other_notes, undobuf.other_insn,
4260 : : undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4261 : : NULL_RTX);
4262 : : }
4263 : :
4264 : 3860596 : if (swap_i2i3)
4265 : : {
4266 : : /* I3 now uses what used to be its destination and which is now
4267 : : I2's destination. This requires us to do a few adjustments. */
4268 : 0 : PATTERN (i3) = newpat;
4269 : 0 : adjust_for_new_dest (i3);
4270 : : }
4271 : :
4272 : 3860596 : if (swap_i2i3 || split_i2i3)
4273 : : {
4274 : : /* We might need a LOG_LINK from I3 to I2. But then we used to
4275 : : have one, so we still will.
4276 : :
4277 : : However, some later insn might be using I2's dest and have
4278 : : a LOG_LINK pointing at I3. We should change it to point at
4279 : : I2 instead. */
4280 : :
4281 : : /* newi2pat is usually a SET here; however, recog_for_combine might
4282 : : have added some clobbers. */
4283 : 30436 : rtx x = newi2pat;
4284 : 30436 : if (GET_CODE (x) == PARALLEL)
4285 : 454 : x = XVECEXP (newi2pat, 0, 0);
4286 : :
4287 : 30436 : if (REG_P (SET_DEST (x))
4288 : 6 : || (GET_CODE (SET_DEST (x)) == SUBREG
4289 : 0 : && REG_P (SUBREG_REG (SET_DEST (x)))))
4290 : : {
4291 : 30430 : unsigned int regno = reg_or_subregno (SET_DEST (x));
4292 : :
4293 : 30430 : bool done = false;
4294 : 495227 : for (rtx_insn *insn = NEXT_INSN (i3);
4295 : 495227 : !done
4296 : 495227 : && insn
4297 : 493762 : && INSN_P (insn)
4298 : 960024 : && BLOCK_FOR_INSN (insn) == this_basic_block;
4299 : 464797 : insn = NEXT_INSN (insn))
4300 : : {
4301 : 464797 : if (DEBUG_INSN_P (insn))
4302 : 158015 : continue;
4303 : 306782 : struct insn_link *link;
4304 : 573826 : FOR_EACH_LOG_LINK (link, insn)
4305 : 267054 : if (link->insn == i3 && link->regno == regno)
4306 : : {
4307 : 10 : link->insn = i2;
4308 : 10 : done = true;
4309 : 10 : break;
4310 : : }
4311 : : }
4312 : : }
4313 : : }
4314 : :
4315 : 3860596 : {
4316 : 3860596 : rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4317 : 3860596 : struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4318 : 3860596 : rtx midnotes = 0;
4319 : 3860596 : int from_luid;
4320 : : /* Compute which registers we expect to eliminate. newi2pat may be setting
4321 : : either i3dest or i2dest, so we must check it. */
4322 : 107119 : rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4323 : 3766640 : || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4324 : 3688604 : || !i2dest_killed
4325 : 7548143 : ? 0 : i2dest);
4326 : : /* For i1, we need to compute both local elimination and global
4327 : : elimination information with respect to newi2pat because i1dest
4328 : : may be the same as i3dest, in which case newi2pat may be setting
4329 : : i1dest. Global information is used when distributing REG_DEAD
4330 : : note for i2 and i3, in which case it does matter if newi2pat sets
4331 : : i1dest or not.
4332 : :
4333 : : Local information is used when distributing REG_DEAD note for i1,
4334 : : in which case it doesn't matter if newi2pat sets i1dest or not.
4335 : : See PR62151, if we have four insns combination:
4336 : : i0: r0 <- i0src
4337 : : i1: r1 <- i1src (using r0)
4338 : : REG_DEAD (r0)
4339 : : i2: r0 <- i2src (using r1)
4340 : : i3: r3 <- i3src (using r0)
4341 : : ix: using r0
4342 : : From i1's point of view, r0 is eliminated, no matter if it is set
4343 : : by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4344 : : should be discarded.
4345 : :
4346 : : Note local information only affects cases in forms like "I1->I2->I3",
4347 : : "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4348 : : "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4349 : : i0dest anyway. */
4350 : 99452 : rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4351 : 99359 : || !i1dest_killed
4352 : 3860596 : ? 0 : i1dest);
4353 : 99358 : rtx elim_i1 = (local_elim_i1 == 0
4354 : 99358 : || (newi2pat && reg_set_p (i1dest, newi2pat))
4355 : 99358 : ? 0 : i1dest);
4356 : : /* Same case as i1. */
4357 : 6482 : rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4358 : 3860596 : ? 0 : i0dest);
4359 : 6464 : rtx elim_i0 = (local_elim_i0 == 0
4360 : 6464 : || (newi2pat && reg_set_p (i0dest, newi2pat))
4361 : 6464 : ? 0 : i0dest);
4362 : :
4363 : : /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4364 : : clear them. */
4365 : 3860596 : i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4366 : 3860596 : i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4367 : 3860596 : if (i1)
4368 : 99452 : i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4369 : 3860596 : if (i0)
4370 : 6482 : i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4371 : :
4372 : : /* Ensure that we do not have something that should not be shared but
4373 : : occurs multiple times in the new insns. Check this by first
4374 : : resetting all the `used' flags and then copying anything is shared. */
4375 : :
4376 : 3860596 : reset_used_flags (i3notes);
4377 : 3860596 : reset_used_flags (i2notes);
4378 : 3860596 : reset_used_flags (i1notes);
4379 : 3860596 : reset_used_flags (i0notes);
4380 : 3860596 : reset_used_flags (newpat);
4381 : 3860596 : reset_used_flags (newi2pat);
4382 : 3860596 : if (undobuf.other_insn)
4383 : 208967 : reset_used_flags (PATTERN (undobuf.other_insn));
4384 : :
4385 : 3860596 : i3notes = copy_rtx_if_shared (i3notes);
4386 : 3860596 : i2notes = copy_rtx_if_shared (i2notes);
4387 : 3860596 : i1notes = copy_rtx_if_shared (i1notes);
4388 : 3860596 : i0notes = copy_rtx_if_shared (i0notes);
4389 : 3860596 : newpat = copy_rtx_if_shared (newpat);
4390 : 3860596 : newi2pat = copy_rtx_if_shared (newi2pat);
4391 : 3860596 : if (undobuf.other_insn)
4392 : 208967 : reset_used_flags (PATTERN (undobuf.other_insn));
4393 : :
4394 : 3860596 : INSN_CODE (i3) = insn_code_number;
4395 : 3860596 : PATTERN (i3) = newpat;
4396 : :
4397 : 3860596 : if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4398 : : {
4399 : 230920 : for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4400 : 151376 : link = XEXP (link, 1))
4401 : : {
4402 : 151376 : if (substed_i2)
4403 : : {
4404 : : /* I2SRC must still be meaningful at this point. Some
4405 : : splitting operations can invalidate I2SRC, but those
4406 : : operations do not apply to calls. */
4407 : 151376 : gcc_assert (i2src);
4408 : 151376 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4409 : : i2dest, i2src);
4410 : : }
4411 : 151376 : if (substed_i1)
4412 : 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4413 : : i1dest, i1src);
4414 : 151376 : if (substed_i0)
4415 : 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4416 : : i0dest, i0src);
4417 : : }
4418 : : }
4419 : :
4420 : 3860596 : if (undobuf.other_insn)
4421 : 208967 : INSN_CODE (undobuf.other_insn) = other_code_number;
4422 : :
4423 : : /* We had one special case above where I2 had more than one set and
4424 : : we replaced a destination of one of those sets with the destination
4425 : : of I3. In that case, we have to update LOG_LINKS of insns later
4426 : : in this basic block. Note that this (expensive) case is rare.
4427 : :
4428 : : Also, in this case, we must pretend that all REG_NOTEs for I2
4429 : : actually came from I3, so that REG_UNUSED notes from I2 will be
4430 : : properly handled. */
4431 : :
4432 : 3860596 : if (i3_subst_into_i2)
4433 : : {
4434 : 161027 : for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4435 : 109606 : if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4436 : 52709 : || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4437 : 108783 : && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4438 : 100028 : && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4439 : 209634 : && ! find_reg_note (i2, REG_UNUSED,
4440 : 100028 : SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4441 : 24781370 : for (temp_insn = NEXT_INSN (i2);
4442 : : temp_insn
4443 : 24781370 : && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4444 : 24697700 : || BB_HEAD (this_basic_block) != temp_insn);
4445 : 24736899 : temp_insn = NEXT_INSN (temp_insn))
4446 : 24736899 : if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4447 : 15594458 : FOR_EACH_LOG_LINK (link, temp_insn)
4448 : 5800006 : if (link->insn == i2)
4449 : 508 : link->insn = i3;
4450 : :
4451 : 51421 : if (i3notes)
4452 : : {
4453 : : rtx link = i3notes;
4454 : 58255 : while (XEXP (link, 1))
4455 : : link = XEXP (link, 1);
4456 : 51421 : XEXP (link, 1) = i2notes;
4457 : : }
4458 : : else
4459 : : i3notes = i2notes;
4460 : : i2notes = 0;
4461 : : }
4462 : :
4463 : 3860596 : LOG_LINKS (i3) = NULL;
4464 : 3860596 : REG_NOTES (i3) = 0;
4465 : 3860596 : LOG_LINKS (i2) = NULL;
4466 : 3860596 : REG_NOTES (i2) = 0;
4467 : :
4468 : 3860596 : if (newi2pat)
4469 : : {
4470 : 107119 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4471 : 12681 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4472 : : this_basic_block);
4473 : 107119 : INSN_CODE (i2) = i2_code_number;
4474 : 107119 : PATTERN (i2) = newi2pat;
4475 : : }
4476 : : else
4477 : : {
4478 : 3753477 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4479 : 2150825 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4480 : : this_basic_block);
4481 : 3753477 : SET_INSN_DELETED (i2);
4482 : : }
4483 : :
4484 : 3860596 : if (i1)
4485 : : {
4486 : 99452 : LOG_LINKS (i1) = NULL;
4487 : 99452 : REG_NOTES (i1) = 0;
4488 : 99452 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4489 : 55738 : propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4490 : : this_basic_block);
4491 : 99452 : SET_INSN_DELETED (i1);
4492 : : }
4493 : :
4494 : 3860596 : if (i0)
4495 : : {
4496 : 6482 : LOG_LINKS (i0) = NULL;
4497 : 6482 : REG_NOTES (i0) = 0;
4498 : 6482 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4499 : 5222 : propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4500 : : this_basic_block);
4501 : 6482 : SET_INSN_DELETED (i0);
4502 : : }
4503 : :
4504 : : /* Get death notes for everything that is now used in either I3 or
4505 : : I2 and used to die in a previous insn. If we built two new
4506 : : patterns, move from I1 to I2 then I2 to I3 so that we get the
4507 : : proper movement on registers that I2 modifies. */
4508 : :
4509 : 3860596 : if (i0)
4510 : 6482 : from_luid = DF_INSN_LUID (i0);
4511 : 3854114 : else if (i1)
4512 : 92970 : from_luid = DF_INSN_LUID (i1);
4513 : : else
4514 : 3761144 : from_luid = DF_INSN_LUID (i2);
4515 : 3860596 : if (newi2pat)
4516 : 107119 : move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4517 : 3860596 : move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4518 : :
4519 : : /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4520 : 3860596 : if (i3notes)
4521 : 7016459 : distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4522 : : elim_i2, elim_i1, elim_i0);
4523 : 3860596 : if (i2notes)
4524 : 5633799 : distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4525 : : elim_i2, elim_i1, elim_i0);
4526 : 3860596 : if (i1notes)
4527 : 66654 : distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4528 : : elim_i2, local_elim_i1, local_elim_i0);
4529 : 3860596 : if (i0notes)
4530 : 5793 : distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4531 : : elim_i2, elim_i1, local_elim_i0);
4532 : 3860596 : if (midnotes)
4533 : 4805237 : distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4534 : : elim_i2, elim_i1, elim_i0);
4535 : :
4536 : : /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4537 : : know these are REG_UNUSED and want them to go to the desired insn,
4538 : : so we always pass it as i3. */
4539 : :
4540 : 3860596 : if (newi2pat && new_i2_notes)
4541 : 40135 : distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4542 : : NULL_RTX);
4543 : :
4544 : 3860596 : if (new_i3_notes)
4545 : 155991 : distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4546 : : NULL_RTX);
4547 : :
4548 : : /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4549 : : put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4550 : : I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4551 : : in that case, it might delete I2. Similarly for I2 and I1.
4552 : : Show an additional death due to the REG_DEAD note we make here. If
4553 : : we discard it in distribute_notes, we will decrement it again. */
4554 : :
4555 : 3860596 : if (i3dest_killed)
4556 : : {
4557 : 295358 : rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4558 : 295358 : if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4559 : 1776 : distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4560 : : elim_i1, elim_i0);
4561 : : else
4562 : 585895 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4563 : : elim_i2, elim_i1, elim_i0);
4564 : : }
4565 : :
4566 : 3860596 : if (i2dest_in_i2src)
4567 : : {
4568 : 76833 : rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4569 : 76833 : if (newi2pat && reg_set_p (i2dest, newi2pat))
4570 : 379 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4571 : : NULL_RTX, NULL_RTX);
4572 : : else
4573 : 152864 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4574 : : NULL_RTX, NULL_RTX, NULL_RTX);
4575 : : }
4576 : :
4577 : 3860596 : if (i1dest_in_i1src)
4578 : : {
4579 : 91 : rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4580 : 91 : if (newi2pat && reg_set_p (i1dest, newi2pat))
4581 : 1 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4582 : : NULL_RTX, NULL_RTX);
4583 : : else
4584 : 164 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4585 : : NULL_RTX, NULL_RTX, NULL_RTX);
4586 : : }
4587 : :
4588 : 3860596 : if (i0dest_in_i0src)
4589 : : {
4590 : 18 : rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4591 : 18 : if (newi2pat && reg_set_p (i0dest, newi2pat))
4592 : 0 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4593 : : NULL_RTX, NULL_RTX);
4594 : : else
4595 : 36 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4596 : : NULL_RTX, NULL_RTX, NULL_RTX);
4597 : : }
4598 : :
4599 : 3860596 : if (only_i3_changed)
4600 : 30358 : distribute_links (i3links, i3, param_max_combine_search_insns);
4601 : : else
4602 : : {
4603 : 3830238 : distribute_links (i3links);
4604 : 3830238 : distribute_links (i2links, i2);
4605 : 3830238 : distribute_links (i1links);
4606 : 3830238 : distribute_links (i0links);
4607 : : }
4608 : :
4609 : 3860596 : if (REG_P (i2dest))
4610 : : {
4611 : 3860596 : struct insn_link *link;
4612 : 3860596 : rtx_insn *i2_insn = 0;
4613 : 3860596 : rtx i2_val = 0, set;
4614 : :
4615 : : /* The insn that used to set this register doesn't exist, and
4616 : : this life of the register may not exist either. See if one of
4617 : : I3's links points to an insn that sets I2DEST. If it does,
4618 : : that is now the last known value for I2DEST. If we don't update
4619 : : this and I2 set the register to a value that depended on its old
4620 : : contents, we will get confused. If this insn is used, thing
4621 : : will be set correctly in combine_instructions. */
4622 : 7166087 : FOR_EACH_LOG_LINK (link, i3)
4623 : 3305491 : if ((set = single_set (link->insn)) != 0
4624 : 3305491 : && rtx_equal_p (i2dest, SET_DEST (set)))
4625 : 49473 : i2_insn = link->insn, i2_val = SET_SRC (set);
4626 : :
4627 : 3860596 : record_value_for_reg (i2dest, i2_insn, i2_val);
4628 : :
4629 : : /* If the reg formerly set in I2 died only once and that was in I3,
4630 : : zero its use count so it won't make `reload' do any work. */
4631 : 3860596 : if (! added_sets_2
4632 : 3734182 : && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4633 : 3693766 : && ! i2dest_in_i2src
4634 : 7496233 : && REGNO (i2dest) < reg_n_sets_max)
4635 : 3635635 : INC_REG_N_SETS (REGNO (i2dest), -1);
4636 : : }
4637 : :
4638 : 3860596 : if (i1 && REG_P (i1dest))
4639 : : {
4640 : 99452 : struct insn_link *link;
4641 : 99452 : rtx_insn *i1_insn = 0;
4642 : 99452 : rtx i1_val = 0, set;
4643 : :
4644 : 177125 : FOR_EACH_LOG_LINK (link, i3)
4645 : 77673 : if ((set = single_set (link->insn)) != 0
4646 : 77673 : && rtx_equal_p (i1dest, SET_DEST (set)))
4647 : 166 : i1_insn = link->insn, i1_val = SET_SRC (set);
4648 : :
4649 : 99452 : record_value_for_reg (i1dest, i1_insn, i1_val);
4650 : :
4651 : 99452 : if (! added_sets_1
4652 : : && ! i1dest_in_i1src
4653 : 99452 : && REGNO (i1dest) < reg_n_sets_max)
4654 : 93476 : INC_REG_N_SETS (REGNO (i1dest), -1);
4655 : : }
4656 : :
4657 : 3860596 : if (i0 && REG_P (i0dest))
4658 : : {
4659 : 6482 : struct insn_link *link;
4660 : 6482 : rtx_insn *i0_insn = 0;
4661 : 6482 : rtx i0_val = 0, set;
4662 : :
4663 : 8553 : FOR_EACH_LOG_LINK (link, i3)
4664 : 2071 : if ((set = single_set (link->insn)) != 0
4665 : 2071 : && rtx_equal_p (i0dest, SET_DEST (set)))
4666 : 0 : i0_insn = link->insn, i0_val = SET_SRC (set);
4667 : :
4668 : 6482 : record_value_for_reg (i0dest, i0_insn, i0_val);
4669 : :
4670 : 6482 : if (! added_sets_0
4671 : : && ! i0dest_in_i0src
4672 : 6482 : && REGNO (i0dest) < reg_n_sets_max)
4673 : 6422 : INC_REG_N_SETS (REGNO (i0dest), -1);
4674 : : }
4675 : :
4676 : : /* Update reg_stat[].nonzero_bits et al for any changes that may have
4677 : : been made to this insn. The order is important, because newi2pat
4678 : : can affect nonzero_bits of newpat. */
4679 : 3860596 : if (newi2pat)
4680 : 107119 : note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4681 : 3860596 : note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4682 : : }
4683 : :
4684 : 3860596 : if (undobuf.other_insn != NULL_RTX)
4685 : : {
4686 : 208967 : if (dump_file)
4687 : : {
4688 : 12 : fprintf (dump_file, "modifying other_insn ");
4689 : 12 : dump_insn_slim (dump_file, undobuf.other_insn);
4690 : : }
4691 : 208967 : df_insn_rescan (undobuf.other_insn);
4692 : : }
4693 : :
4694 : 3860596 : if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4695 : : {
4696 : 0 : if (dump_file)
4697 : : {
4698 : 0 : fprintf (dump_file, "modifying insn i0 ");
4699 : 0 : dump_insn_slim (dump_file, i0);
4700 : : }
4701 : 0 : df_insn_rescan (i0);
4702 : : }
4703 : :
4704 : 3860596 : if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4705 : : {
4706 : 0 : if (dump_file)
4707 : : {
4708 : 0 : fprintf (dump_file, "modifying insn i1 ");
4709 : 0 : dump_insn_slim (dump_file, i1);
4710 : : }
4711 : 0 : df_insn_rescan (i1);
4712 : : }
4713 : :
4714 : 3860596 : if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4715 : : {
4716 : 107119 : if (dump_file)
4717 : : {
4718 : 15 : fprintf (dump_file, "modifying insn i2 ");
4719 : 15 : dump_insn_slim (dump_file, i2);
4720 : : }
4721 : 107119 : df_insn_rescan (i2);
4722 : : }
4723 : :
4724 : 3860596 : if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4725 : : {
4726 : 3860596 : if (dump_file)
4727 : : {
4728 : 242 : fprintf (dump_file, "modifying insn i3 ");
4729 : 242 : dump_insn_slim (dump_file, i3);
4730 : : }
4731 : 3860596 : df_insn_rescan (i3);
4732 : : }
4733 : :
4734 : : /* Set new_direct_jump_p if a new return or simple jump instruction
4735 : : has been created. Adjust the CFG accordingly. */
4736 : 3860596 : if (returnjump_p (i3) || any_uncondjump_p (i3))
4737 : : {
4738 : 182 : *new_direct_jump_p = 1;
4739 : 182 : mark_jump_label (PATTERN (i3), i3, 0);
4740 : 182 : update_cfg_for_uncondjump (i3);
4741 : : }
4742 : :
4743 : 3860596 : if (undobuf.other_insn != NULL_RTX
4744 : 3860596 : && (returnjump_p (undobuf.other_insn)
4745 : 208967 : || any_uncondjump_p (undobuf.other_insn)))
4746 : : {
4747 : 2220 : *new_direct_jump_p = 1;
4748 : 2220 : update_cfg_for_uncondjump (undobuf.other_insn);
4749 : : }
4750 : :
4751 : 3860596 : if (GET_CODE (PATTERN (i3)) == TRAP_IF
4752 : 3860596 : && XEXP (PATTERN (i3), 0) == const1_rtx)
4753 : : {
4754 : 0 : basic_block bb = BLOCK_FOR_INSN (i3);
4755 : 0 : gcc_assert (bb);
4756 : 0 : remove_edge (split_block (bb, i3));
4757 : 0 : emit_barrier_after_bb (bb);
4758 : 0 : *new_direct_jump_p = 1;
4759 : : }
4760 : :
4761 : 3860596 : if (undobuf.other_insn
4762 : 208967 : && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4763 : 3860596 : && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4764 : : {
4765 : 0 : basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4766 : 0 : gcc_assert (bb);
4767 : 0 : remove_edge (split_block (bb, undobuf.other_insn));
4768 : 0 : emit_barrier_after_bb (bb);
4769 : 0 : *new_direct_jump_p = 1;
4770 : : }
4771 : :
4772 : : /* A noop might also need cleaning up of CFG, if it comes from the
4773 : : simplification of a jump. */
4774 : 3860596 : if (JUMP_P (i3)
4775 : 49766 : && GET_CODE (newpat) == SET
4776 : 34125 : && SET_SRC (newpat) == pc_rtx
4777 : 395 : && SET_DEST (newpat) == pc_rtx)
4778 : : {
4779 : 395 : *new_direct_jump_p = 1;
4780 : 395 : update_cfg_for_uncondjump (i3);
4781 : : }
4782 : :
4783 : 3860596 : if (undobuf.other_insn != NULL_RTX
4784 : 208967 : && JUMP_P (undobuf.other_insn)
4785 : 202887 : && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4786 : 202887 : && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4787 : 3862661 : && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4788 : : {
4789 : 2065 : *new_direct_jump_p = 1;
4790 : 2065 : update_cfg_for_uncondjump (undobuf.other_insn);
4791 : : }
4792 : :
4793 : 3860596 : combine_successes++;
4794 : 3860596 : undo_commit ();
4795 : :
4796 : 3860596 : if (only_i3_changed)
4797 : : return i3;
4798 : :
4799 : 3830238 : rtx_insn *ret = newi2pat ? i2 : i3;
4800 : 3830238 : if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4801 : : ret = added_links_insn;
4802 : 3830238 : if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4803 : : ret = added_notes_insn;
4804 : :
4805 : : return ret;
4806 : : }
4807 : :
4808 : : /* Get a marker for undoing to the current state. */
4809 : :
4810 : : static void *
4811 : 36938853 : get_undo_marker (void)
4812 : : {
4813 : 36938853 : return undobuf.undos;
4814 : : }
4815 : :
4816 : : /* Undo the modifications up to the marker. */
4817 : :
4818 : : static void
4819 : 43757207 : undo_to_marker (void *marker)
4820 : : {
4821 : 43757207 : struct undo *undo, *next;
4822 : :
4823 : 137475838 : for (undo = undobuf.undos; undo != marker; undo = next)
4824 : : {
4825 : 93718631 : gcc_assert (undo);
4826 : :
4827 : 93718631 : next = undo->next;
4828 : 93718631 : switch (undo->kind)
4829 : : {
4830 : 86308720 : case UNDO_RTX:
4831 : 86308720 : *undo->where.r = undo->old_contents.r;
4832 : 86308720 : break;
4833 : 6732961 : case UNDO_INT:
4834 : 6732961 : *undo->where.i = undo->old_contents.i;
4835 : 6732961 : break;
4836 : 607524 : case UNDO_MODE:
4837 : 607524 : adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4838 : : undo->old_contents.m);
4839 : 607524 : break;
4840 : 69426 : case UNDO_LINKS:
4841 : 69426 : *undo->where.l = undo->old_contents.l;
4842 : 69426 : break;
4843 : 0 : default:
4844 : 0 : gcc_unreachable ();
4845 : : }
4846 : :
4847 : 93718631 : undo->next = undobuf.frees;
4848 : 93718631 : undobuf.frees = undo;
4849 : : }
4850 : :
4851 : 43757207 : undobuf.undos = (struct undo *) marker;
4852 : 43757207 : }
4853 : :
4854 : : /* Undo all the modifications recorded in undobuf. */
4855 : :
4856 : : static void
4857 : 42658206 : undo_all (void)
4858 : : {
4859 : 42658206 : undo_to_marker (0);
4860 : 0 : }
4861 : :
4862 : : /* We've committed to accepting the changes we made. Move all
4863 : : of the undos to the free list. */
4864 : :
4865 : : static void
4866 : 3860596 : undo_commit (void)
4867 : : {
4868 : 3860596 : struct undo *undo, *next;
4869 : :
4870 : 11627713 : for (undo = undobuf.undos; undo; undo = next)
4871 : : {
4872 : 7767117 : next = undo->next;
4873 : 7767117 : undo->next = undobuf.frees;
4874 : 7767117 : undobuf.frees = undo;
4875 : : }
4876 : 3860596 : undobuf.undos = 0;
4877 : 3860596 : }
4878 : :
4879 : : /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4880 : : where we have an arithmetic expression and return that point. LOC will
4881 : : be inside INSN.
4882 : :
4883 : : try_combine will call this function to see if an insn can be split into
4884 : : two insns. */
4885 : :
4886 : : static rtx *
4887 : 31410922 : find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4888 : : {
4889 : 31410922 : rtx x = *loc;
4890 : 31410922 : enum rtx_code code = GET_CODE (x);
4891 : 31410922 : rtx *split;
4892 : 31410922 : unsigned HOST_WIDE_INT len = 0;
4893 : 31410922 : HOST_WIDE_INT pos = 0;
4894 : 31410922 : bool unsignedp = false;
4895 : 31410922 : rtx inner = NULL_RTX;
4896 : 31410922 : scalar_int_mode mode, inner_mode;
4897 : :
4898 : : /* First special-case some codes. */
4899 : 31410922 : switch (code)
4900 : : {
4901 : 1029534 : case SUBREG:
4902 : : #ifdef INSN_SCHEDULING
4903 : : /* If we are making a paradoxical SUBREG invalid, it becomes a split
4904 : : point. */
4905 : 1029534 : if (MEM_P (SUBREG_REG (x)))
4906 : : return loc;
4907 : : #endif
4908 : 1013521 : return find_split_point (&SUBREG_REG (x), insn, false);
4909 : :
4910 : 1544215 : case MEM:
4911 : : /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4912 : : using LO_SUM and HIGH. */
4913 : 1544215 : if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4914 : : || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4915 : : {
4916 : : machine_mode address_mode = get_address_mode (x);
4917 : :
4918 : : SUBST (XEXP (x, 0),
4919 : : gen_rtx_LO_SUM (address_mode,
4920 : : gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4921 : : XEXP (x, 0)));
4922 : : return &XEXP (XEXP (x, 0), 0);
4923 : : }
4924 : :
4925 : : /* If we have a PLUS whose second operand is a constant and the
4926 : : address is not valid, perhaps we can split it up using
4927 : : the machine-specific way to split large constants. We use
4928 : : the first pseudo-reg (one of the virtual regs) as a placeholder;
4929 : : it will not remain in the result. */
4930 : 1544215 : if (GET_CODE (XEXP (x, 0)) == PLUS
4931 : 987005 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4932 : 3232233 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4933 : 701013 : MEM_ADDR_SPACE (x)))
4934 : : {
4935 : 118481 : rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4936 : 118481 : unsigned int old_nregs, new_nregs;
4937 : 118481 : rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4938 : : subst_insn, &old_nregs, &new_nregs);
4939 : :
4940 : : /* This should have produced two insns, each of which sets our
4941 : : placeholder. If the source of the second is a valid address,
4942 : : we can put both sources together and make a split point
4943 : : in the middle. */
4944 : :
4945 : 118481 : if (seq
4946 : 50 : && NEXT_INSN (seq) != NULL_RTX
4947 : 0 : && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4948 : 0 : && NONJUMP_INSN_P (seq)
4949 : 0 : && GET_CODE (PATTERN (seq)) == SET
4950 : 0 : && SET_DEST (PATTERN (seq)) == reg
4951 : 0 : && ! reg_mentioned_p (reg,
4952 : 0 : SET_SRC (PATTERN (seq)))
4953 : 0 : && NONJUMP_INSN_P (NEXT_INSN (seq))
4954 : 0 : && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4955 : 0 : && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4956 : 118481 : && memory_address_addr_space_p
4957 : 118481 : (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4958 : 0 : MEM_ADDR_SPACE (x)))
4959 : : {
4960 : 0 : rtx src1 = SET_SRC (PATTERN (seq));
4961 : 0 : rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4962 : :
4963 : : /* Replace the placeholder in SRC2 with SRC1. If we can
4964 : : find where in SRC2 it was placed, that can become our
4965 : : split point and we can replace this address with SRC2.
4966 : : Just try two obvious places. */
4967 : :
4968 : 0 : src2 = replace_rtx (src2, reg, src1);
4969 : 0 : split = 0;
4970 : 0 : if (XEXP (src2, 0) == src1)
4971 : 0 : split = &XEXP (src2, 0);
4972 : 0 : else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4973 : 0 : && XEXP (XEXP (src2, 0), 0) == src1)
4974 : 0 : split = &XEXP (XEXP (src2, 0), 0);
4975 : :
4976 : 0 : if (split)
4977 : : {
4978 : 0 : SUBST (XEXP (x, 0), src2);
4979 : 93862 : return split;
4980 : : }
4981 : : }
4982 : :
4983 : : /* If that didn't work and we have a nested plus, like:
4984 : : ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4985 : : is valid address, try to split (REG1 * CONST1). */
4986 : 118481 : if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4987 : 85069 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4988 : 73185 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4989 : 73183 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4990 : 10 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4991 : : 0), 0)))))
4992 : : {
4993 : 73183 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
4994 : 73183 : XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
4995 : 146366 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4996 : 73183 : MEM_ADDR_SPACE (x)))
4997 : : {
4998 : 63853 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4999 : 63853 : return &XEXP (XEXP (XEXP (x, 0), 0), 0);
5000 : : }
5001 : 9330 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5002 : 9330 : }
5003 : 45298 : else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5004 : 11886 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5005 : 11884 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5006 : 624 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
5007 : 624 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5008 : : 0), 1)))))
5009 : : {
5010 : 0 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
5011 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
5012 : 0 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5013 : 0 : MEM_ADDR_SPACE (x)))
5014 : : {
5015 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5016 : 0 : return &XEXP (XEXP (XEXP (x, 0), 0), 1);
5017 : : }
5018 : 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5019 : : }
5020 : :
5021 : : /* If that didn't work, perhaps the first operand is complex and
5022 : : needs to be computed separately, so make a split point there.
5023 : : This will occur on machines that just support REG + CONST
5024 : : and have a constant moved through some previous computation. */
5025 : 54628 : if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5026 : 30009 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5027 : 0 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5028 : 30009 : return &XEXP (XEXP (x, 0), 0);
5029 : : }
5030 : :
5031 : : /* If we have a PLUS whose first operand is complex, try computing it
5032 : : separately by making a split there. */
5033 : 1450353 : if (GET_CODE (XEXP (x, 0)) == PLUS
5034 : 2518354 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5035 : 893143 : MEM_ADDR_SPACE (x))
5036 : 174858 : && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5037 : 1577828 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5038 : 1474 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5039 : 127471 : return &XEXP (XEXP (x, 0), 0);
5040 : : break;
5041 : :
5042 : 4688217 : case SET:
5043 : : /* See if we can split SET_SRC as it stands. */
5044 : 4688217 : split = find_split_point (&SET_SRC (x), insn, true);
5045 : 4688217 : if (split && split != &SET_SRC (x))
5046 : : return split;
5047 : :
5048 : : /* See if we can split SET_DEST as it stands. */
5049 : 476554 : split = find_split_point (&SET_DEST (x), insn, false);
5050 : 476554 : if (split && split != &SET_DEST (x))
5051 : : return split;
5052 : :
5053 : : /* See if this is a bitfield assignment with everything constant. If
5054 : : so, this is an IOR of an AND, so split it into that. */
5055 : 441282 : if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5056 : 4790 : && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5057 : : &inner_mode)
5058 : 4790 : && HWI_COMPUTABLE_MODE_P (inner_mode)
5059 : 4790 : && CONST_INT_P (XEXP (SET_DEST (x), 1))
5060 : 4790 : && CONST_INT_P (XEXP (SET_DEST (x), 2))
5061 : 4651 : && CONST_INT_P (SET_SRC (x))
5062 : 507 : && ((INTVAL (XEXP (SET_DEST (x), 1))
5063 : 507 : + INTVAL (XEXP (SET_DEST (x), 2)))
5064 : 507 : <= GET_MODE_PRECISION (inner_mode))
5065 : 441789 : && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5066 : : {
5067 : 490 : HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5068 : 490 : unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5069 : 490 : rtx dest = XEXP (SET_DEST (x), 0);
5070 : 490 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5071 : 490 : unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5072 : 490 : rtx or_mask;
5073 : :
5074 : 490 : if (BITS_BIG_ENDIAN)
5075 : : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5076 : :
5077 : 490 : or_mask = gen_int_mode (src << pos, inner_mode);
5078 : 490 : if (src == mask)
5079 : 0 : SUBST (SET_SRC (x),
5080 : : simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5081 : : else
5082 : : {
5083 : 490 : rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5084 : 490 : SUBST (SET_SRC (x),
5085 : : simplify_gen_binary (IOR, inner_mode,
5086 : : simplify_gen_binary (AND, inner_mode,
5087 : : dest, negmask),
5088 : : or_mask));
5089 : : }
5090 : :
5091 : 490 : SUBST (SET_DEST (x), dest);
5092 : :
5093 : 490 : split = find_split_point (&SET_SRC (x), insn, true);
5094 : 490 : if (split && split != &SET_SRC (x))
5095 : : return split;
5096 : : }
5097 : :
5098 : : /* Otherwise, see if this is an operation that we can split into two.
5099 : : If so, try to split that. */
5100 : 440792 : code = GET_CODE (SET_SRC (x));
5101 : :
5102 : 440792 : switch (code)
5103 : : {
5104 : 15179 : case AND:
5105 : : /* If we are AND'ing with a large constant that is only a single
5106 : : bit and the result is only being used in a context where we
5107 : : need to know if it is zero or nonzero, replace it with a bit
5108 : : extraction. This will avoid the large constant, which might
5109 : : have taken more than one insn to make. If the constant were
5110 : : not a valid argument to the AND but took only one insn to make,
5111 : : this is no worse, but if it took more than one insn, it will
5112 : : be better. */
5113 : :
5114 : 15179 : if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5115 : 10897 : && REG_P (XEXP (SET_SRC (x), 0))
5116 : 426 : && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5117 : 1 : && REG_P (SET_DEST (x))
5118 : 0 : && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5119 : 0 : && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5120 : 0 : && XEXP (*split, 0) == SET_DEST (x)
5121 : 15179 : && XEXP (*split, 1) == const0_rtx)
5122 : : {
5123 : 0 : rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5124 : 0 : XEXP (SET_SRC (x), 0),
5125 : : pos, NULL_RTX, 1,
5126 : : true, false, false);
5127 : 0 : if (extraction != 0)
5128 : : {
5129 : 0 : SUBST (SET_SRC (x), extraction);
5130 : 0 : return find_split_point (loc, insn, false);
5131 : : }
5132 : : }
5133 : : break;
5134 : :
5135 : : case NE:
5136 : : /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5137 : : is known to be on, this can be converted into a NEG of a shift. */
5138 : : if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5139 : : && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5140 : : && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5141 : : GET_MODE (XEXP (SET_SRC (x),
5142 : : 0))))) >= 1))
5143 : : {
5144 : : machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5145 : : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5146 : : SUBST (SET_SRC (x),
5147 : : gen_rtx_NEG (mode,
5148 : : gen_rtx_LSHIFTRT (mode,
5149 : : XEXP (SET_SRC (x), 0),
5150 : : pos_rtx)));
5151 : :
5152 : : split = find_split_point (&SET_SRC (x), insn, true);
5153 : : if (split && split != &SET_SRC (x))
5154 : : return split;
5155 : : }
5156 : : break;
5157 : :
5158 : 999 : case SIGN_EXTEND:
5159 : 999 : inner = XEXP (SET_SRC (x), 0);
5160 : :
5161 : : /* We can't optimize if either mode is a partial integer
5162 : : mode as we don't know how many bits are significant
5163 : : in those modes. */
5164 : 999 : if (!is_int_mode (GET_MODE (inner), &inner_mode)
5165 : 993 : || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5166 : : break;
5167 : :
5168 : 993 : pos = 0;
5169 : 993 : len = GET_MODE_PRECISION (inner_mode);
5170 : 993 : unsignedp = false;
5171 : 993 : break;
5172 : :
5173 : 14766 : case SIGN_EXTRACT:
5174 : 14766 : case ZERO_EXTRACT:
5175 : 14766 : if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5176 : : &inner_mode)
5177 : 14409 : && CONST_INT_P (XEXP (SET_SRC (x), 1))
5178 : 14409 : && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5179 : : {
5180 : 13677 : inner = XEXP (SET_SRC (x), 0);
5181 : 13677 : len = INTVAL (XEXP (SET_SRC (x), 1));
5182 : 13677 : pos = INTVAL (XEXP (SET_SRC (x), 2));
5183 : :
5184 : 13677 : if (BITS_BIG_ENDIAN)
5185 : : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5186 : 13677 : unsignedp = (code == ZERO_EXTRACT);
5187 : : }
5188 : : break;
5189 : :
5190 : : default:
5191 : : break;
5192 : : }
5193 : :
5194 : 440792 : if (len
5195 : 14670 : && known_subrange_p (pos, len,
5196 : 14670 : 0, GET_MODE_PRECISION (GET_MODE (inner)))
5197 : 455462 : && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5198 : : {
5199 : : /* For unsigned, we have a choice of a shift followed by an
5200 : : AND or two shifts. Use two shifts for field sizes where the
5201 : : constant might be too large. We assume here that we can
5202 : : always at least get 8-bit constants in an AND insn, which is
5203 : : true for every current RISC. */
5204 : :
5205 : 14670 : if (unsignedp && len <= 8)
5206 : : {
5207 : 7562 : unsigned HOST_WIDE_INT mask
5208 : 7562 : = (HOST_WIDE_INT_1U << len) - 1;
5209 : 7562 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5210 : 7562 : SUBST (SET_SRC (x),
5211 : : gen_rtx_AND (mode,
5212 : : gen_rtx_LSHIFTRT
5213 : : (mode, gen_lowpart (mode, inner), pos_rtx),
5214 : : gen_int_mode (mask, mode)));
5215 : :
5216 : 7562 : split = find_split_point (&SET_SRC (x), insn, true);
5217 : 7562 : if (split && split != &SET_SRC (x))
5218 : 31410922 : return split;
5219 : : }
5220 : : else
5221 : : {
5222 : 7108 : int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5223 : 7108 : int right_bits = GET_MODE_PRECISION (mode) - len;
5224 : 14216 : SUBST (SET_SRC (x),
5225 : : gen_rtx_fmt_ee
5226 : : (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5227 : : gen_rtx_ASHIFT (mode,
5228 : : gen_lowpart (mode, inner),
5229 : : gen_int_shift_amount (mode, left_bits)),
5230 : : gen_int_shift_amount (mode, right_bits)));
5231 : :
5232 : 7108 : split = find_split_point (&SET_SRC (x), insn, true);
5233 : 7108 : if (split && split != &SET_SRC (x))
5234 : 31410922 : return split;
5235 : : }
5236 : : }
5237 : :
5238 : : /* See if this is a simple operation with a constant as the second
5239 : : operand. It might be that this constant is out of range and hence
5240 : : could be used as a split point. */
5241 : 426122 : if (BINARY_P (SET_SRC (x))
5242 : 202865 : && CONSTANT_P (XEXP (SET_SRC (x), 1))
5243 : 105808 : && (OBJECT_P (XEXP (SET_SRC (x), 0))
5244 : 20444 : || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5245 : 11051 : && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5246 : 86996 : return &XEXP (SET_SRC (x), 1);
5247 : :
5248 : : /* Finally, see if this is a simple operation with its first operand
5249 : : not in a register. The operation might require this operand in a
5250 : : register, so return it as a split point. We can always do this
5251 : : because if the first operand were another operation, we would have
5252 : : already found it as a split point. */
5253 : 339126 : if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5254 : 339126 : && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5255 : 115749 : return &XEXP (SET_SRC (x), 0);
5256 : :
5257 : : return 0;
5258 : :
5259 : 1291828 : case AND:
5260 : 1291828 : case IOR:
5261 : : /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5262 : : it is better to write this as (not (ior A B)) so we can split it.
5263 : : Similarly for IOR. */
5264 : 1291828 : if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5265 : : {
5266 : 1244 : SUBST (*loc,
5267 : : gen_rtx_NOT (GET_MODE (x),
5268 : : gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5269 : : GET_MODE (x),
5270 : : XEXP (XEXP (x, 0), 0),
5271 : : XEXP (XEXP (x, 1), 0))));
5272 : 622 : return find_split_point (loc, insn, set_src);
5273 : : }
5274 : :
5275 : : /* Many RISC machines have a large set of logical insns. If the
5276 : : second operand is a NOT, put it first so we will try to split the
5277 : : other operand first. */
5278 : 1291206 : if (GET_CODE (XEXP (x, 1)) == NOT)
5279 : : {
5280 : 4897 : rtx tem = XEXP (x, 0);
5281 : 4897 : SUBST (XEXP (x, 0), XEXP (x, 1));
5282 : 4897 : SUBST (XEXP (x, 1), tem);
5283 : : }
5284 : : /* Many targets have a `(and (not X) Y)` and/or `(ior (not X) Y)` instructions.
5285 : : Split at that insns. However if this is
5286 : : the SET_SRC, we likely do not have such an instruction and it's
5287 : : worthless to try this split. */
5288 : 1291206 : if (!set_src && GET_CODE (XEXP (x, 0)) == NOT)
5289 : : return loc;
5290 : : break;
5291 : :
5292 : 3220893 : case PLUS:
5293 : 3220893 : case MINUS:
5294 : : /* Canonicalization can produce (minus A (mult B C)), where C is a
5295 : : constant. It may be better to try splitting (plus (mult B -C) A)
5296 : : instead if this isn't a multiply by a power of two. */
5297 : 223309 : if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5298 : 26689 : && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5299 : 3231257 : && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5300 : : {
5301 : 10364 : machine_mode mode = GET_MODE (x);
5302 : 10364 : unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5303 : 10364 : HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5304 : 10364 : SUBST (*loc, gen_rtx_PLUS (mode,
5305 : : gen_rtx_MULT (mode,
5306 : : XEXP (XEXP (x, 1), 0),
5307 : : gen_int_mode (other_int,
5308 : : mode)),
5309 : : XEXP (x, 0)));
5310 : 10364 : return find_split_point (loc, insn, set_src);
5311 : : }
5312 : :
5313 : : /* Split at a multiply-accumulate instruction. However if this is
5314 : : the SET_SRC, we likely do not have such an instruction and it's
5315 : : worthless to try this split. */
5316 : 3210529 : if (!set_src
5317 : 1885257 : && (GET_CODE (XEXP (x, 0)) == MULT
5318 : 1769052 : || (GET_CODE (XEXP (x, 0)) == ASHIFT
5319 : 120616 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5320 : : return loc;
5321 : :
5322 : : default:
5323 : : break;
5324 : : }
5325 : :
5326 : : /* Otherwise, select our actions depending on our rtx class. */
5327 : 25219273 : switch (GET_RTX_CLASS (code))
5328 : : {
5329 : 1303818 : case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5330 : 1303818 : case RTX_TERNARY:
5331 : 1303818 : split = find_split_point (&XEXP (x, 2), insn, false);
5332 : 1303818 : if (split)
5333 : : return split;
5334 : : /* fall through */
5335 : 10022654 : case RTX_BIN_ARITH:
5336 : 10022654 : case RTX_COMM_ARITH:
5337 : 10022654 : case RTX_COMPARE:
5338 : 10022654 : case RTX_COMM_COMPARE:
5339 : 10022654 : split = find_split_point (&XEXP (x, 1), insn, false);
5340 : 10022654 : if (split)
5341 : : return split;
5342 : : /* fall through */
5343 : 9575755 : case RTX_UNARY:
5344 : : /* Some machines have (and (shift ...) ...) insns. If X is not
5345 : : an AND, but XEXP (X, 0) is, use it as our split point. */
5346 : 9575755 : if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5347 : 383960 : return &XEXP (x, 0);
5348 : :
5349 : 9191795 : split = find_split_point (&XEXP (x, 0), insn, false);
5350 : 9191795 : if (split)
5351 : : return split;
5352 : : return loc;
5353 : :
5354 : : default:
5355 : : /* Otherwise, we don't have a split point. */
5356 : : return 0;
5357 : : }
5358 : : }
5359 : :
5360 : : /* Throughout X, replace FROM with TO, and return the result.
5361 : : The result is TO if X is FROM;
5362 : : otherwise the result is X, but its contents may have been modified.
5363 : : If they were modified, a record was made in undobuf so that
5364 : : undo_all will (among other things) return X to its original state.
5365 : :
5366 : : If the number of changes necessary is too much to record to undo,
5367 : : the excess changes are not made, so the result is invalid.
5368 : : The changes already made can still be undone.
5369 : : undobuf.num_undo is incremented for such changes, so by testing that
5370 : : the caller can tell whether the result is valid.
5371 : :
5372 : : `n_occurrences' is incremented each time FROM is replaced.
5373 : :
5374 : : IN_DEST is true if we are processing the SET_DEST of a SET.
5375 : :
5376 : : IN_COND is true if we are at the top level of a condition.
5377 : :
5378 : : UNIQUE_COPY is true if each substitution must be unique. We do this
5379 : : by copying if `n_occurrences' is nonzero. */
5380 : :
5381 : : static rtx
5382 : 399350092 : subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5383 : : {
5384 : 399350092 : enum rtx_code code = GET_CODE (x);
5385 : 399350092 : machine_mode op0_mode = VOIDmode;
5386 : 399350092 : const char *fmt;
5387 : 399350092 : int len, i;
5388 : 399350092 : rtx new_rtx;
5389 : :
5390 : : /* Two expressions are equal if they are identical copies of a shared
5391 : : RTX or if they are both registers with the same register number
5392 : : and mode. */
5393 : :
5394 : : #define COMBINE_RTX_EQUAL_P(X,Y) \
5395 : : ((X) == (Y) \
5396 : : || (REG_P (X) && REG_P (Y) \
5397 : : && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5398 : :
5399 : : /* Do not substitute into clobbers of regs -- this will never result in
5400 : : valid RTL. */
5401 : 399350092 : if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5402 : : return x;
5403 : :
5404 : 388550627 : if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5405 : : {
5406 : 0 : n_occurrences++;
5407 : 0 : return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5408 : : }
5409 : :
5410 : : /* If X and FROM are the same register but different modes, they
5411 : : will not have been seen as equal above. However, the log links code
5412 : : will make a LOG_LINKS entry for that case. If we do nothing, we
5413 : : will try to rerecognize our original insn and, when it succeeds,
5414 : : we will delete the feeding insn, which is incorrect.
5415 : :
5416 : : So force this insn not to match in this (rare) case. */
5417 : 86560922 : if (! in_dest && code == REG && REG_P (from)
5418 : 419689459 : && reg_overlap_mentioned_p (x, from))
5419 : 4129 : return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5420 : :
5421 : : /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5422 : : of which may contain things that can be combined. */
5423 : 388546498 : if (code != MEM && code != LO_SUM && OBJECT_P (x))
5424 : : return x;
5425 : :
5426 : : /* It is possible to have a subexpression appear twice in the insn.
5427 : : Suppose that FROM is a register that appears within TO.
5428 : : Then, after that subexpression has been scanned once by `subst',
5429 : : the second time it is scanned, TO may be found. If we were
5430 : : to scan TO here, we would find FROM within it and create a
5431 : : self-referent rtl structure which is completely wrong. */
5432 : 208528438 : if (COMBINE_RTX_EQUAL_P (x, to))
5433 : : return to;
5434 : :
5435 : : /* Parallel asm_operands need special attention because all of the
5436 : : inputs are shared across the arms. Furthermore, unsharing the
5437 : : rtl results in recognition failures. Failure to handle this case
5438 : : specially can result in circular rtl.
5439 : :
5440 : : Solve this by doing a normal pass across the first entry of the
5441 : : parallel, and only processing the SET_DESTs of the subsequent
5442 : : entries. Ug. */
5443 : :
5444 : 208428853 : if (code == PARALLEL
5445 : 13160675 : && GET_CODE (XVECEXP (x, 0, 0)) == SET
5446 : 11452737 : && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5447 : : {
5448 : 18902 : new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5449 : :
5450 : : /* If this substitution failed, this whole thing fails. */
5451 : 18902 : if (GET_CODE (new_rtx) == CLOBBER
5452 : 0 : && XEXP (new_rtx, 0) == const0_rtx)
5453 : : return new_rtx;
5454 : :
5455 : 18902 : SUBST (XVECEXP (x, 0, 0), new_rtx);
5456 : :
5457 : 94900 : for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5458 : : {
5459 : 75998 : rtx dest = SET_DEST (XVECEXP (x, 0, i));
5460 : :
5461 : 75998 : if (!REG_P (dest) && GET_CODE (dest) != PC)
5462 : : {
5463 : 1993 : new_rtx = subst (dest, from, to, false, false, unique_copy);
5464 : :
5465 : : /* If this substitution failed, this whole thing fails. */
5466 : 1993 : if (GET_CODE (new_rtx) == CLOBBER
5467 : 0 : && XEXP (new_rtx, 0) == const0_rtx)
5468 : : return new_rtx;
5469 : :
5470 : 1993 : SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5471 : : }
5472 : : }
5473 : : }
5474 : : else
5475 : : {
5476 : 208409951 : len = GET_RTX_LENGTH (code);
5477 : 208409951 : fmt = GET_RTX_FORMAT (code);
5478 : :
5479 : : /* We don't need to process a SET_DEST that is a register or PC, so
5480 : : set up to skip this common case. All other cases where we want
5481 : : to suppress replacing something inside a SET_SRC are handled via
5482 : : the IN_DEST operand. */
5483 : 208409951 : if (code == SET
5484 : 46054143 : && (REG_P (SET_DEST (x))
5485 : 46054143 : || GET_CODE (SET_DEST (x)) == PC))
5486 : 208409951 : fmt = "ie";
5487 : :
5488 : : /* Trying to simplify the operands of a widening MULT is not likely
5489 : : to create RTL matching a machine insn. */
5490 : 208409951 : if (code == MULT
5491 : 4945087 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5492 : 4945087 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5493 : 299640 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5494 : 299640 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5495 : 205201 : && REG_P (XEXP (XEXP (x, 0), 0))
5496 : 92448 : && REG_P (XEXP (XEXP (x, 1), 0))
5497 : 74573 : && from == to)
5498 : : return x;
5499 : :
5500 : :
5501 : : /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5502 : : constant. */
5503 : 208367904 : if (fmt[0] == 'e')
5504 : 152936300 : op0_mode = GET_MODE (XEXP (x, 0));
5505 : :
5506 : 615486338 : for (i = 0; i < len; i++)
5507 : : {
5508 : 407892779 : if (fmt[i] == 'E')
5509 : : {
5510 : 15252379 : int j;
5511 : 48361568 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5512 : : {
5513 : 33203890 : if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5514 : : {
5515 : 1443 : new_rtx = (unique_copy && n_occurrences
5516 : 263721 : ? copy_rtx (to) : to);
5517 : 263700 : n_occurrences++;
5518 : : }
5519 : : else
5520 : : {
5521 : 32940190 : new_rtx = subst (XVECEXP (x, i, j), from, to,
5522 : : false, false, unique_copy);
5523 : :
5524 : : /* If this substitution failed, this whole thing
5525 : : fails. */
5526 : 32940190 : if (GET_CODE (new_rtx) == CLOBBER
5527 : 11278230 : && XEXP (new_rtx, 0) == const0_rtx)
5528 : : return new_rtx;
5529 : : }
5530 : :
5531 : 33109189 : SUBST (XVECEXP (x, i, j), new_rtx);
5532 : : }
5533 : : }
5534 : 392640400 : else if (fmt[i] == 'e')
5535 : : {
5536 : : /* If this is a register being set, ignore it. */
5537 : 320997795 : new_rtx = XEXP (x, i);
5538 : 320997795 : if (in_dest
5539 : 320997795 : && i == 0
5540 : 5910007 : && (((code == SUBREG || code == ZERO_EXTRACT)
5541 : 345082 : && REG_P (new_rtx))
5542 : 5567268 : || code == STRICT_LOW_PART))
5543 : : ;
5544 : :
5545 : 320645050 : else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5546 : : {
5547 : : /* In general, don't install a subreg involving two
5548 : : modes not tieable. It can worsen register
5549 : : allocation, and can even make invalid reload
5550 : : insns, since the reg inside may need to be copied
5551 : : from in the outside mode, and that may be invalid
5552 : : if it is an fp reg copied in integer mode.
5553 : :
5554 : : We allow an exception to this: It is valid if
5555 : : it is inside another SUBREG and the mode of that
5556 : : SUBREG and the mode of the inside of TO is
5557 : : tieable. */
5558 : :
5559 : 46163723 : if (GET_CODE (to) == SUBREG
5560 : 561554 : && !targetm.modes_tieable_p (GET_MODE (to),
5561 : 561554 : GET_MODE (SUBREG_REG (to)))
5562 : 46432128 : && ! (code == SUBREG
5563 : 22656 : && (targetm.modes_tieable_p
5564 : 22656 : (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5565 : 243510 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5566 : :
5567 : 45920213 : if (code == SUBREG
5568 : 2345186 : && REG_P (to)
5569 : 99263 : && REGNO (to) < FIRST_PSEUDO_REGISTER
5570 : 45920224 : && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5571 : 11 : SUBREG_BYTE (x),
5572 : 11 : GET_MODE (x)) < 0)
5573 : 6 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5574 : :
5575 : 45920207 : new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5576 : 45920207 : n_occurrences++;
5577 : : }
5578 : : else
5579 : : /* If we are in a SET_DEST, suppress most cases unless we
5580 : : have gone inside a MEM, in which case we want to
5581 : : simplify the address. We assume here that things that
5582 : : are actually part of the destination have their inner
5583 : : parts in the first expression. This is true for SUBREG,
5584 : : STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5585 : : things aside from REG and MEM that should appear in a
5586 : : SET_DEST. */
5587 : 274481327 : new_rtx = subst (XEXP (x, i), from, to,
5588 : : (((in_dest
5589 : 5277965 : && (code == SUBREG || code == STRICT_LOW_PART
5590 : 5277965 : || code == ZERO_EXTRACT))
5591 : 274473785 : || code == SET)
5592 : 47593506 : && i == 0),
5593 : 274481327 : code == IF_THEN_ELSE && i == 0,
5594 : : unique_copy);
5595 : :
5596 : : /* If we found that we will have to reject this combination,
5597 : : indicate that by returning the CLOBBER ourselves, rather than
5598 : : an expression containing it. This will speed things up as
5599 : : well as prevent accidents where two CLOBBERs are considered
5600 : : to be equal, thus producing an incorrect simplification. */
5601 : :
5602 : 320754279 : if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5603 : : return new_rtx;
5604 : :
5605 : 320318401 : if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5606 : : {
5607 : 33264 : machine_mode mode = GET_MODE (x);
5608 : :
5609 : 66528 : x = simplify_subreg (GET_MODE (x), new_rtx,
5610 : 33264 : GET_MODE (SUBREG_REG (x)),
5611 : 33264 : SUBREG_BYTE (x));
5612 : 33264 : if (! x)
5613 : 2 : x = gen_rtx_CLOBBER (mode, const0_rtx);
5614 : : }
5615 : 320285137 : else if (CONST_SCALAR_INT_P (new_rtx)
5616 : : && (GET_CODE (x) == ZERO_EXTEND
5617 : 59748371 : || GET_CODE (x) == SIGN_EXTEND
5618 : : || GET_CODE (x) == FLOAT
5619 : : || GET_CODE (x) == UNSIGNED_FLOAT))
5620 : : {
5621 : 151018 : x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5622 : : new_rtx,
5623 : 75509 : GET_MODE (XEXP (x, 0)));
5624 : 75509 : if (!x)
5625 : 250 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5626 : : }
5627 : : /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5628 : : etc. arguments, otherwise we can ICE before trying to recog
5629 : : it. See PR104446. */
5630 : 320209628 : else if (CONST_SCALAR_INT_P (new_rtx)
5631 : 59672862 : && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5632 : 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5633 : : else
5634 : 320209628 : SUBST (XEXP (x, i), new_rtx);
5635 : : }
5636 : : }
5637 : : }
5638 : :
5639 : : /* Check if we are loading something from the constant pool via float
5640 : : extension; in this case we would undo compress_float_constant
5641 : : optimization and degenerate constant load to an immediate value. */
5642 : 207612461 : if (GET_CODE (x) == FLOAT_EXTEND
5643 : 314881 : && MEM_P (XEXP (x, 0))
5644 : 207675103 : && MEM_READONLY_P (XEXP (x, 0)))
5645 : : {
5646 : 35982 : rtx tmp = avoid_constant_pool_reference (x);
5647 : 35982 : if (x != tmp)
5648 : : return x;
5649 : : }
5650 : :
5651 : : /* Try to simplify X. If the simplification changed the code, it is likely
5652 : : that further simplification will help, so loop, but limit the number
5653 : : of repetitions that will be performed. */
5654 : :
5655 : 215617389 : for (i = 0; i < 4; i++)
5656 : : {
5657 : : /* If X is sufficiently simple, don't bother trying to do anything
5658 : : with it. */
5659 : 215602228 : if (code != CONST_INT && code != REG && code != CLOBBER)
5660 : 214840242 : x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5661 : :
5662 : 215602228 : if (GET_CODE (x) == code)
5663 : : break;
5664 : :
5665 : 8040780 : code = GET_CODE (x);
5666 : :
5667 : : /* We no longer know the original mode of operand 0 since we
5668 : : have changed the form of X) */
5669 : 8040780 : op0_mode = VOIDmode;
5670 : : }
5671 : :
5672 : : return x;
5673 : : }
5674 : :
5675 : : /* If X is a commutative operation whose operands are not in the canonical
5676 : : order, use substitutions to swap them. */
5677 : :
5678 : : static void
5679 : 662943441 : maybe_swap_commutative_operands (rtx x)
5680 : : {
5681 : 662943441 : if (COMMUTATIVE_ARITH_P (x)
5682 : 662943441 : && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5683 : : {
5684 : 3570592 : rtx temp = XEXP (x, 0);
5685 : 3570592 : SUBST (XEXP (x, 0), XEXP (x, 1));
5686 : 3570592 : SUBST (XEXP (x, 1), temp);
5687 : : }
5688 : :
5689 : : /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5690 : : (vec_merge (fma op1 op2 op3) op1 mask). */
5691 : 662943441 : if (GET_CODE (x) == VEC_MERGE
5692 : 706669 : && GET_CODE (XEXP (x, 0)) == FMA)
5693 : : {
5694 : 24996 : rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5695 : 24996 : rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5696 : 24996 : rtx masked_op = XEXP (x, 1);
5697 : 24996 : if (rtx_equal_p (masked_op, fma_op2))
5698 : : {
5699 : 218 : if (GET_CODE (fma_op1) == NEG)
5700 : : {
5701 : : /* Keep the negate canonicalized to the first operand. */
5702 : 150 : fma_op1 = XEXP (fma_op1, 0);
5703 : 150 : SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5704 : 150 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5705 : : }
5706 : : else
5707 : : {
5708 : 68 : SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5709 : 68 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5710 : : }
5711 : : }
5712 : : }
5713 : :
5714 : 662943441 : unsigned n_elts = 0;
5715 : 662943441 : if (GET_CODE (x) == VEC_MERGE
5716 : 706669 : && CONST_INT_P (XEXP (x, 2))
5717 : 760018 : && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5718 : 663323450 : && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5719 : : /* Two operands have same precedence, then
5720 : : first bit of mask select first operand. */
5721 : 352830 : || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5722 : 89187 : && !(UINTVAL (XEXP (x, 2)) & 1))))
5723 : : {
5724 : 41301 : rtx temp = XEXP (x, 0);
5725 : 41301 : unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5726 : 41301 : unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5727 : 41301 : if (n_elts == HOST_BITS_PER_WIDE_INT)
5728 : : mask = -1;
5729 : : else
5730 : 41290 : mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5731 : 41301 : SUBST (XEXP (x, 0), XEXP (x, 1));
5732 : 41301 : SUBST (XEXP (x, 1), temp);
5733 : 41301 : SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5734 : : }
5735 : 662943441 : }
5736 : :
5737 : : /* Simplify X, a piece of RTL. We just operate on the expression at the
5738 : : outer level; call `subst' to simplify recursively. Return the new
5739 : : expression.
5740 : :
5741 : : OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5742 : : if we are inside a SET_DEST. IN_COND is true if we are at the top level
5743 : : of a condition. */
5744 : :
5745 : : static rtx
5746 : 215134586 : combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5747 : : {
5748 : 215134586 : enum rtx_code code = GET_CODE (x);
5749 : 215134586 : machine_mode mode = GET_MODE (x);
5750 : 215134586 : scalar_int_mode int_mode;
5751 : 215134586 : rtx temp;
5752 : 215134586 : int i;
5753 : :
5754 : : /* If this is a commutative operation, put a constant last and a complex
5755 : : expression first. We don't need to do this for comparisons here. */
5756 : 215134586 : maybe_swap_commutative_operands (x);
5757 : :
5758 : : /* Try to fold this expression in case we have constants that weren't
5759 : : present before. */
5760 : 215134586 : temp = 0;
5761 : 215134586 : switch (GET_RTX_CLASS (code))
5762 : : {
5763 : 7120076 : case RTX_UNARY:
5764 : 7120076 : if (op0_mode == VOIDmode)
5765 : 156696 : op0_mode = GET_MODE (XEXP (x, 0));
5766 : 7120076 : temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5767 : 7120076 : break;
5768 : 16341086 : case RTX_COMPARE:
5769 : 16341086 : case RTX_COMM_COMPARE:
5770 : 16341086 : {
5771 : 16341086 : machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5772 : 16341086 : if (cmp_mode == VOIDmode)
5773 : : {
5774 : 50093 : cmp_mode = GET_MODE (XEXP (x, 1));
5775 : 50093 : if (cmp_mode == VOIDmode)
5776 : 7781 : cmp_mode = op0_mode;
5777 : : }
5778 : 16341086 : temp = simplify_relational_operation (code, mode, cmp_mode,
5779 : : XEXP (x, 0), XEXP (x, 1));
5780 : : }
5781 : 16341086 : break;
5782 : 86864091 : case RTX_COMM_ARITH:
5783 : 86864091 : case RTX_BIN_ARITH:
5784 : 86864091 : temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5785 : 86864091 : break;
5786 : 12889290 : case RTX_BITFIELD_OPS:
5787 : 12889290 : case RTX_TERNARY:
5788 : 12889290 : temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5789 : : XEXP (x, 1), XEXP (x, 2));
5790 : 12889290 : break;
5791 : : default:
5792 : : break;
5793 : : }
5794 : :
5795 : 123214543 : if (temp)
5796 : : {
5797 : 16003561 : x = temp;
5798 : 16003561 : code = GET_CODE (temp);
5799 : 16003561 : op0_mode = VOIDmode;
5800 : 16003561 : mode = GET_MODE (temp);
5801 : : }
5802 : :
5803 : : /* If this is a simple operation applied to an IF_THEN_ELSE, try
5804 : : applying it to the arms of the IF_THEN_ELSE. This often simplifies
5805 : : things. Check for cases where both arms are testing the same
5806 : : condition.
5807 : :
5808 : : Don't do anything if all operands are very simple. */
5809 : :
5810 : 215134586 : if ((BINARY_P (x)
5811 : 102939774 : && ((!OBJECT_P (XEXP (x, 0))
5812 : 40815273 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5813 : 5132879 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5814 : 64992040 : || (!OBJECT_P (XEXP (x, 1))
5815 : 4615789 : && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5816 : 1636368 : && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5817 : 173923104 : || (UNARY_P (x)
5818 : 6978024 : && (!OBJECT_P (XEXP (x, 0))
5819 : 2941182 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5820 : 590101 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5821 : : {
5822 : 43634817 : rtx cond, true_rtx, false_rtx;
5823 : :
5824 : 43634817 : cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5825 : 43634817 : if (cond != 0
5826 : : /* If everything is a comparison, what we have is highly unlikely
5827 : : to be simpler, so don't use it. */
5828 : 3959195 : && ! (COMPARISON_P (x)
5829 : 1022403 : && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5830 : : /* Similarly, if we end up with one of the expressions the same
5831 : : as the original, it is certainly not simpler. */
5832 : 3809597 : && ! rtx_equal_p (x, true_rtx)
5833 : 47444414 : && ! rtx_equal_p (x, false_rtx))
5834 : : {
5835 : 3809597 : rtx cop1 = const0_rtx;
5836 : 3809597 : enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5837 : :
5838 : 3809597 : if (cond_code == NE && COMPARISON_P (cond))
5839 : 584940 : return x;
5840 : :
5841 : : /* Simplify the alternative arms; this may collapse the true and
5842 : : false arms to store-flag values. Be careful to use copy_rtx
5843 : : here since true_rtx or false_rtx might share RTL with x as a
5844 : : result of the if_then_else_cond call above. */
5845 : 3224657 : true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5846 : : false, false, false);
5847 : 3224657 : false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5848 : : false, false, false);
5849 : :
5850 : : /* If true_rtx and false_rtx are not general_operands, an if_then_else
5851 : : is unlikely to be simpler. */
5852 : 3224657 : if (general_operand (true_rtx, VOIDmode)
5853 : 3224657 : && general_operand (false_rtx, VOIDmode))
5854 : : {
5855 : 1197906 : enum rtx_code reversed;
5856 : :
5857 : : /* Restarting if we generate a store-flag expression will cause
5858 : : us to loop. Just drop through in this case. */
5859 : :
5860 : : /* If the result values are STORE_FLAG_VALUE and zero, we can
5861 : : just make the comparison operation. */
5862 : 1197906 : if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5863 : 423764 : x = simplify_gen_relational (cond_code, mode, VOIDmode,
5864 : : cond, cop1);
5865 : 538275 : else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5866 : 774142 : && ((reversed = reversed_comparison_code_parts
5867 : 448262 : (cond_code, cond, cop1, NULL))
5868 : : != UNKNOWN))
5869 : 448262 : x = simplify_gen_relational (reversed, mode, VOIDmode,
5870 : : cond, cop1);
5871 : :
5872 : : /* Likewise, we can make the negate of a comparison operation
5873 : : if the result values are - STORE_FLAG_VALUE and zero. */
5874 : 325880 : else if (CONST_INT_P (true_rtx)
5875 : 235281 : && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5876 : 41090 : && false_rtx == const0_rtx)
5877 : 39365 : x = simplify_gen_unary (NEG, mode,
5878 : : simplify_gen_relational (cond_code,
5879 : : mode, VOIDmode,
5880 : : cond, cop1),
5881 : : mode);
5882 : 286515 : else if (CONST_INT_P (false_rtx)
5883 : 212798 : && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5884 : 24572 : && true_rtx == const0_rtx
5885 : 286515 : && ((reversed = reversed_comparison_code_parts
5886 : 21458 : (cond_code, cond, cop1, NULL))
5887 : : != UNKNOWN))
5888 : 21455 : x = simplify_gen_unary (NEG, mode,
5889 : : simplify_gen_relational (reversed,
5890 : : mode, VOIDmode,
5891 : : cond, cop1),
5892 : : mode);
5893 : :
5894 : 1197906 : code = GET_CODE (x);
5895 : 1197906 : op0_mode = VOIDmode;
5896 : : }
5897 : : }
5898 : : }
5899 : :
5900 : : /* First see if we can apply the inverse distributive law. */
5901 : 214549646 : if (code == PLUS || code == MINUS
5902 : 214549646 : || code == AND || code == IOR || code == XOR)
5903 : : {
5904 : 49341111 : x = apply_distributive_law (x);
5905 : 49341111 : code = GET_CODE (x);
5906 : 49341111 : op0_mode = VOIDmode;
5907 : : }
5908 : :
5909 : : /* If CODE is an associative operation not otherwise handled, see if we
5910 : : can associate some operands. This can win if they are constants or
5911 : : if they are logically related (i.e. (a & b) & a). */
5912 : 214549646 : if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5913 : : || code == AND || code == IOR || code == XOR
5914 : : || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5915 : 53512830 : && ((INTEGRAL_MODE_P (mode) && code != DIV)
5916 : 4551009 : || (flag_associative_math && FLOAT_MODE_P (mode))))
5917 : : {
5918 : 49578341 : if (GET_CODE (XEXP (x, 0)) == code)
5919 : : {
5920 : 4085592 : rtx other = XEXP (XEXP (x, 0), 0);
5921 : 4085592 : rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5922 : 4085592 : rtx inner_op1 = XEXP (x, 1);
5923 : 4085592 : rtx inner;
5924 : :
5925 : : /* Make sure we pass the constant operand if any as the second
5926 : : one if this is a commutative operation. */
5927 : 4085592 : if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5928 : : std::swap (inner_op0, inner_op1);
5929 : 4085592 : inner = simplify_binary_operation (code == MINUS ? PLUS
5930 : 3990957 : : code == DIV ? MULT
5931 : : : code,
5932 : : mode, inner_op0, inner_op1);
5933 : :
5934 : : /* For commutative operations, try the other pair if that one
5935 : : didn't simplify. */
5936 : 4085592 : if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5937 : : {
5938 : 3959265 : other = XEXP (XEXP (x, 0), 1);
5939 : 3959265 : inner = simplify_binary_operation (code, mode,
5940 : : XEXP (XEXP (x, 0), 0),
5941 : : XEXP (x, 1));
5942 : : }
5943 : :
5944 : 4050793 : if (inner)
5945 : 249996 : return simplify_gen_binary (code, mode, other, inner);
5946 : : }
5947 : : }
5948 : :
5949 : : /* A little bit of algebraic simplification here. */
5950 : 214299650 : switch (code)
5951 : : {
5952 : 21371138 : case MEM:
5953 : : /* Ensure that our address has any ASHIFTs converted to MULT in case
5954 : : address-recognizing predicates are called later. */
5955 : 21371138 : temp = make_compound_operation (XEXP (x, 0), MEM);
5956 : 21371138 : SUBST (XEXP (x, 0), temp);
5957 : 21371138 : break;
5958 : :
5959 : 8186487 : case SUBREG:
5960 : 8186487 : if (op0_mode == VOIDmode)
5961 : 206215 : op0_mode = GET_MODE (SUBREG_REG (x));
5962 : :
5963 : : /* See if this can be moved to simplify_subreg. */
5964 : 8186487 : if (CONSTANT_P (SUBREG_REG (x))
5965 : 14248 : && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5966 : : /* Don't call gen_lowpart if the inner mode
5967 : : is VOIDmode and we cannot simplify it, as SUBREG without
5968 : : inner mode is invalid. */
5969 : 8200735 : && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5970 : 0 : || gen_lowpart_common (mode, SUBREG_REG (x))))
5971 : 14248 : return gen_lowpart (mode, SUBREG_REG (x));
5972 : :
5973 : 8172239 : if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5974 : : break;
5975 : 8172239 : {
5976 : 8172239 : rtx temp;
5977 : 16344478 : temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5978 : 8172239 : SUBREG_BYTE (x));
5979 : 8172239 : if (temp)
5980 : 215134586 : return temp;
5981 : :
5982 : : /* If op is known to have all lower bits zero, the result is zero. */
5983 : 7629965 : scalar_int_mode int_mode, int_op0_mode;
5984 : 7629965 : if (!in_dest
5985 : 4614998 : && is_a <scalar_int_mode> (mode, &int_mode)
5986 : 4538276 : && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5987 : 4538276 : && (GET_MODE_PRECISION (int_mode)
5988 : 4538276 : < GET_MODE_PRECISION (int_op0_mode))
5989 : 3951596 : && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5990 : : SUBREG_BYTE (x))
5991 : 3468837 : && HWI_COMPUTABLE_MODE_P (int_op0_mode)
5992 : 3168972 : && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
5993 : 3168972 : & GET_MODE_MASK (int_mode)) == 0)
5994 : 7630658 : && !side_effects_p (SUBREG_REG (x)))
5995 : 693 : return CONST0_RTX (int_mode);
5996 : : }
5997 : :
5998 : : /* Don't change the mode of the MEM if that would change the meaning
5999 : : of the address. */
6000 : 7629272 : if (MEM_P (SUBREG_REG (x))
6001 : 7629272 : && (MEM_VOLATILE_P (SUBREG_REG (x))
6002 : 87752 : || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
6003 : 87817 : MEM_ADDR_SPACE (SUBREG_REG (x)))))
6004 : 43896 : return gen_rtx_CLOBBER (mode, const0_rtx);
6005 : :
6006 : : /* Note that we cannot do any narrowing for non-constants since
6007 : : we might have been counting on using the fact that some bits were
6008 : : zero. We now do this in the SET. */
6009 : :
6010 : : break;
6011 : :
6012 : 366291 : case NEG:
6013 : 366291 : temp = expand_compound_operation (XEXP (x, 0));
6014 : :
6015 : : /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6016 : : replaced by (lshiftrt X C). This will convert
6017 : : (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6018 : :
6019 : 366291 : if (GET_CODE (temp) == ASHIFTRT
6020 : 12809 : && CONST_INT_P (XEXP (temp, 1))
6021 : 391847 : && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
6022 : 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
6023 : 0 : INTVAL (XEXP (temp, 1)));
6024 : :
6025 : : /* If X has only a single bit that might be nonzero, say, bit I, convert
6026 : : (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6027 : : MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6028 : : (sign_extract X 1 Y). But only do this if TEMP isn't a register
6029 : : or a SUBREG of one since we'd be making the expression more
6030 : : complex if it was just a register. */
6031 : :
6032 : 366291 : if (!REG_P (temp)
6033 : 182925 : && ! (GET_CODE (temp) == SUBREG
6034 : 23811 : && REG_P (SUBREG_REG (temp)))
6035 : 215275693 : && is_a <scalar_int_mode> (mode, &int_mode)
6036 : 507398 : && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6037 : : {
6038 : 61530 : rtx temp1 = simplify_shift_const
6039 : 61530 : (NULL_RTX, ASHIFTRT, int_mode,
6040 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6041 : 61530 : GET_MODE_PRECISION (int_mode) - 1 - i),
6042 : 61530 : GET_MODE_PRECISION (int_mode) - 1 - i);
6043 : :
6044 : : /* If all we did was surround TEMP with the two shifts, we
6045 : : haven't improved anything, so don't use it. Otherwise,
6046 : : we are better off with TEMP1. */
6047 : 61530 : if (GET_CODE (temp1) != ASHIFTRT
6048 : 61343 : || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6049 : 61305 : || XEXP (XEXP (temp1, 0), 0) != temp)
6050 : : return temp1;
6051 : : }
6052 : : break;
6053 : :
6054 : 9254 : case TRUNCATE:
6055 : : /* We can't handle truncation to a partial integer mode here
6056 : : because we don't know the real bitsize of the partial
6057 : : integer mode. */
6058 : 9254 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6059 : : break;
6060 : :
6061 : 9254 : if (HWI_COMPUTABLE_MODE_P (mode))
6062 : 0 : SUBST (XEXP (x, 0),
6063 : : force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6064 : : GET_MODE_MASK (mode), false));
6065 : :
6066 : : /* We can truncate a constant value and return it. */
6067 : 9254 : {
6068 : 9254 : poly_int64 c;
6069 : 9254 : if (poly_int_rtx_p (XEXP (x, 0), &c))
6070 : 0 : return gen_int_mode (c, mode);
6071 : : }
6072 : :
6073 : : /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6074 : : whose value is a comparison can be replaced with a subreg if
6075 : : STORE_FLAG_VALUE permits. */
6076 : 9254 : if (HWI_COMPUTABLE_MODE_P (mode)
6077 : 0 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6078 : 0 : && (temp = get_last_value (XEXP (x, 0)))
6079 : 0 : && COMPARISON_P (temp)
6080 : 9254 : && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6081 : 0 : return gen_lowpart (mode, XEXP (x, 0));
6082 : : break;
6083 : :
6084 : 8790 : case CONST:
6085 : : /* (const (const X)) can become (const X). Do it this way rather than
6086 : : returning the inner CONST since CONST can be shared with a
6087 : : REG_EQUAL note. */
6088 : 8790 : if (GET_CODE (XEXP (x, 0)) == CONST)
6089 : 0 : SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6090 : : break;
6091 : :
6092 : : case LO_SUM:
6093 : : /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6094 : : can add in an offset. find_split_point will split this address up
6095 : : again if it doesn't match. */
6096 : : if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6097 : : && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6098 : : return XEXP (x, 1);
6099 : : break;
6100 : :
6101 : 32654213 : case PLUS:
6102 : : /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6103 : : when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6104 : : bit-field and can be replaced by either a sign_extend or a
6105 : : sign_extract. The `and' may be a zero_extend and the two
6106 : : <c>, -<c> constants may be reversed. */
6107 : 32654213 : if (GET_CODE (XEXP (x, 0)) == XOR
6108 : 32654213 : && is_a <scalar_int_mode> (mode, &int_mode)
6109 : 14017 : && CONST_INT_P (XEXP (x, 1))
6110 : 5354 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6111 : 4824 : && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6112 : 77 : && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6113 : 2 : || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6114 : 39 : && HWI_COMPUTABLE_MODE_P (int_mode)
6115 : 32654252 : && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6116 : 0 : && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6117 : 0 : && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6118 : 0 : == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6119 : 39 : || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6120 : 0 : && known_eq ((GET_MODE_PRECISION
6121 : : (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6122 : : (unsigned int) i + 1))))
6123 : 0 : return simplify_shift_const
6124 : 0 : (NULL_RTX, ASHIFTRT, int_mode,
6125 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6126 : : XEXP (XEXP (XEXP (x, 0), 0), 0),
6127 : 0 : GET_MODE_PRECISION (int_mode) - (i + 1)),
6128 : 0 : GET_MODE_PRECISION (int_mode) - (i + 1));
6129 : :
6130 : : /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6131 : : can become (ashiftrt (ashift (xor x 1) C) C) where C is
6132 : : the bitsize of the mode - 1. This allows simplification of
6133 : : "a = (b & 8) == 0;" */
6134 : 32654213 : if (XEXP (x, 1) == constm1_rtx
6135 : 768537 : && !REG_P (XEXP (x, 0))
6136 : 343401 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6137 : 60573 : && REG_P (SUBREG_REG (XEXP (x, 0))))
6138 : 32926378 : && is_a <scalar_int_mode> (mode, &int_mode)
6139 : 32938557 : && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6140 : 12179 : return simplify_shift_const
6141 : 12179 : (NULL_RTX, ASHIFTRT, int_mode,
6142 : : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6143 : : gen_rtx_XOR (int_mode, XEXP (x, 0),
6144 : : const1_rtx),
6145 : 12179 : GET_MODE_PRECISION (int_mode) - 1),
6146 : 24358 : GET_MODE_PRECISION (int_mode) - 1);
6147 : :
6148 : : /* If we are adding two things that have no bits in common, convert
6149 : : the addition into an IOR. This will often be further simplified,
6150 : : for example in cases like ((a & 1) + (a & 2)), which can
6151 : : become a & 3. */
6152 : :
6153 : 32642034 : if (HWI_COMPUTABLE_MODE_P (mode)
6154 : 28786618 : && (nonzero_bits (XEXP (x, 0), mode)
6155 : 28786618 : & nonzero_bits (XEXP (x, 1), mode)) == 0)
6156 : : {
6157 : : /* Try to simplify the expression further. */
6158 : 294344 : rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6159 : 294344 : temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6160 : :
6161 : : /* If we could, great. If not, do not go ahead with the IOR
6162 : : replacement, since PLUS appears in many special purpose
6163 : : address arithmetic instructions. */
6164 : 294344 : if (GET_CODE (temp) != CLOBBER
6165 : 294344 : && (GET_CODE (temp) != IOR
6166 : 290183 : || ((XEXP (temp, 0) != XEXP (x, 0)
6167 : 286605 : || XEXP (temp, 1) != XEXP (x, 1))
6168 : 3578 : && (XEXP (temp, 0) != XEXP (x, 1)
6169 : 0 : || XEXP (temp, 1) != XEXP (x, 0)))))
6170 : : return temp;
6171 : : }
6172 : :
6173 : : /* Canonicalize x + x into x << 1. */
6174 : 32634295 : if (GET_MODE_CLASS (mode) == MODE_INT
6175 : 29119129 : && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6176 : 32637206 : && !side_effects_p (XEXP (x, 0)))
6177 : 2911 : return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6178 : :
6179 : : break;
6180 : :
6181 : 4168143 : case MINUS:
6182 : : /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6183 : : (and <foo> (const_int pow2-1)) */
6184 : 4168143 : if (is_a <scalar_int_mode> (mode, &int_mode)
6185 : 3606185 : && GET_CODE (XEXP (x, 1)) == AND
6186 : 173911 : && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6187 : 171189 : && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6188 : 91094 : && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6189 : 0 : return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6190 : 0 : -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6191 : : break;
6192 : :
6193 : 3303745 : case MULT:
6194 : : /* If we have (mult (plus A B) C), apply the distributive law and then
6195 : : the inverse distributive law to see if things simplify. This
6196 : : occurs mostly in addresses, often when unrolling loops. */
6197 : :
6198 : 3303745 : if (GET_CODE (XEXP (x, 0)) == PLUS)
6199 : : {
6200 : 310801 : rtx result = distribute_and_simplify_rtx (x, 0);
6201 : 310801 : if (result)
6202 : : return result;
6203 : : }
6204 : :
6205 : : /* Try simplify a*(b/c) as (a*b)/c. */
6206 : 3303237 : if (FLOAT_MODE_P (mode) && flag_associative_math
6207 : 196570 : && GET_CODE (XEXP (x, 0)) == DIV)
6208 : : {
6209 : 259 : rtx tem = simplify_binary_operation (MULT, mode,
6210 : : XEXP (XEXP (x, 0), 0),
6211 : : XEXP (x, 1));
6212 : 259 : if (tem)
6213 : 33 : return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6214 : : }
6215 : : break;
6216 : :
6217 : 119694 : case UDIV:
6218 : : /* If this is a divide by a power of two, treat it as a shift if
6219 : : its first operand is a shift. */
6220 : 119694 : if (is_a <scalar_int_mode> (mode, &int_mode)
6221 : 119694 : && CONST_INT_P (XEXP (x, 1))
6222 : 1778 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6223 : 0 : && (GET_CODE (XEXP (x, 0)) == ASHIFT
6224 : 0 : || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6225 : 0 : || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6226 : 0 : || GET_CODE (XEXP (x, 0)) == ROTATE
6227 : 0 : || GET_CODE (XEXP (x, 0)) == ROTATERT))
6228 : 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6229 : 0 : XEXP (x, 0), i);
6230 : : break;
6231 : :
6232 : 16305630 : case EQ: case NE:
6233 : 16305630 : case GT: case GTU: case GE: case GEU:
6234 : 16305630 : case LT: case LTU: case LE: case LEU:
6235 : 16305630 : case UNEQ: case LTGT:
6236 : 16305630 : case UNGT: case UNGE:
6237 : 16305630 : case UNLT: case UNLE:
6238 : 16305630 : case UNORDERED: case ORDERED:
6239 : : /* If the first operand is a condition code, we can't do anything
6240 : : with it. */
6241 : 16305630 : if (GET_CODE (XEXP (x, 0)) == COMPARE
6242 : 16305630 : || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6243 : : {
6244 : 12305095 : rtx op0 = XEXP (x, 0);
6245 : 12305095 : rtx op1 = XEXP (x, 1);
6246 : 12305095 : enum rtx_code new_code;
6247 : :
6248 : 12305095 : if (GET_CODE (op0) == COMPARE)
6249 : 0 : op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6250 : :
6251 : : /* Simplify our comparison, if possible. */
6252 : 12305095 : new_code = simplify_comparison (code, &op0, &op1);
6253 : :
6254 : : /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6255 : : if only the low-order bit is possibly nonzero in X (such as when
6256 : : X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6257 : : (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6258 : : known to be either 0 or -1, NE becomes a NEG and EQ becomes
6259 : : (plus X 1).
6260 : :
6261 : : Remove any ZERO_EXTRACT we made when thinking this was a
6262 : : comparison. It may now be simpler to use, e.g., an AND. If a
6263 : : ZERO_EXTRACT is indeed appropriate, it will be placed back by
6264 : : the call to make_compound_operation in the SET case.
6265 : :
6266 : : Don't apply these optimizations if the caller would
6267 : : prefer a comparison rather than a value.
6268 : : E.g., for the condition in an IF_THEN_ELSE most targets need
6269 : : an explicit comparison. */
6270 : :
6271 : 12305095 : if (in_cond)
6272 : : ;
6273 : :
6274 : 2065243 : else if (STORE_FLAG_VALUE == 1
6275 : : && new_code == NE
6276 : 2460306 : && is_int_mode (mode, &int_mode)
6277 : 395283 : && op1 == const0_rtx
6278 : 201539 : && int_mode == GET_MODE (op0)
6279 : 2148049 : && nonzero_bits (op0, int_mode) == 1)
6280 : 220 : return gen_lowpart (int_mode,
6281 : 400787 : expand_compound_operation (op0));
6282 : :
6283 : 2065023 : else if (STORE_FLAG_VALUE == 1
6284 : : && new_code == NE
6285 : 2459467 : && is_int_mode (mode, &int_mode)
6286 : 395063 : && op1 == const0_rtx
6287 : 201319 : && int_mode == GET_MODE (op0)
6288 : 2147609 : && (num_sign_bit_copies (op0, int_mode)
6289 : 82586 : == GET_MODE_PRECISION (int_mode)))
6290 : : {
6291 : 619 : op0 = expand_compound_operation (op0);
6292 : 619 : return simplify_gen_unary (NEG, int_mode,
6293 : 619 : gen_lowpart (int_mode, op0),
6294 : 619 : int_mode);
6295 : : }
6296 : :
6297 : 2064404 : else if (STORE_FLAG_VALUE == 1
6298 : : && new_code == EQ
6299 : 2412302 : && is_int_mode (mode, &int_mode)
6300 : 350843 : && op1 == const0_rtx
6301 : 171635 : && int_mode == GET_MODE (op0)
6302 : 2144436 : && nonzero_bits (op0, int_mode) == 1)
6303 : : {
6304 : 2945 : op0 = expand_compound_operation (op0);
6305 : 2945 : return simplify_gen_binary (XOR, int_mode,
6306 : 2945 : gen_lowpart (int_mode, op0),
6307 : 2945 : const1_rtx);
6308 : : }
6309 : :
6310 : 2061459 : else if (STORE_FLAG_VALUE == 1
6311 : : && new_code == EQ
6312 : 12648656 : && is_int_mode (mode, &int_mode)
6313 : 347898 : && op1 == const0_rtx
6314 : 168690 : && int_mode == GET_MODE (op0)
6315 : 2138546 : && (num_sign_bit_copies (op0, int_mode)
6316 : 77087 : == GET_MODE_PRECISION (int_mode)))
6317 : : {
6318 : 553 : op0 = expand_compound_operation (op0);
6319 : 553 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6320 : : }
6321 : :
6322 : : /* If STORE_FLAG_VALUE is -1, we have cases similar to
6323 : : those above. */
6324 : 12300758 : if (in_cond)
6325 : : ;
6326 : :
6327 : 12300758 : else if (STORE_FLAG_VALUE == -1
6328 : : && new_code == NE
6329 : : && is_int_mode (mode, &int_mode)
6330 : : && op1 == const0_rtx
6331 : : && int_mode == GET_MODE (op0)
6332 : : && (num_sign_bit_copies (op0, int_mode)
6333 : : == GET_MODE_PRECISION (int_mode)))
6334 : : return gen_lowpart (int_mode, expand_compound_operation (op0));
6335 : :
6336 : 12300758 : else if (STORE_FLAG_VALUE == -1
6337 : : && new_code == NE
6338 : : && is_int_mode (mode, &int_mode)
6339 : : && op1 == const0_rtx
6340 : : && int_mode == GET_MODE (op0)
6341 : : && nonzero_bits (op0, int_mode) == 1)
6342 : : {
6343 : : op0 = expand_compound_operation (op0);
6344 : : return simplify_gen_unary (NEG, int_mode,
6345 : : gen_lowpart (int_mode, op0),
6346 : : int_mode);
6347 : : }
6348 : :
6349 : 12300758 : else if (STORE_FLAG_VALUE == -1
6350 : : && new_code == EQ
6351 : : && is_int_mode (mode, &int_mode)
6352 : : && op1 == const0_rtx
6353 : : && int_mode == GET_MODE (op0)
6354 : : && (num_sign_bit_copies (op0, int_mode)
6355 : : == GET_MODE_PRECISION (int_mode)))
6356 : : {
6357 : : op0 = expand_compound_operation (op0);
6358 : : return simplify_gen_unary (NOT, int_mode,
6359 : : gen_lowpart (int_mode, op0),
6360 : : int_mode);
6361 : : }
6362 : :
6363 : : /* If X is 0/1, (eq X 0) is X-1. */
6364 : 12300758 : else if (STORE_FLAG_VALUE == -1
6365 : : && new_code == EQ
6366 : : && is_int_mode (mode, &int_mode)
6367 : : && op1 == const0_rtx
6368 : : && int_mode == GET_MODE (op0)
6369 : : && nonzero_bits (op0, int_mode) == 1)
6370 : : {
6371 : : op0 = expand_compound_operation (op0);
6372 : : return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6373 : : }
6374 : :
6375 : : /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6376 : : one bit that might be nonzero, we can convert (ne x 0) to
6377 : : (ashift x c) where C puts the bit in the sign bit. Remove any
6378 : : AND with STORE_FLAG_VALUE when we are done, since we are only
6379 : : going to test the sign bit. */
6380 : 12300758 : if (new_code == NE
6381 : 12691336 : && is_int_mode (mode, &int_mode)
6382 : 394527 : && HWI_COMPUTABLE_MODE_P (int_mode)
6383 : 390578 : && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6384 : 0 : && op1 == const0_rtx
6385 : 0 : && int_mode == GET_MODE (op0)
6386 : 12300758 : && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6387 : : {
6388 : 0 : x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6389 : : expand_compound_operation (op0),
6390 : 0 : GET_MODE_PRECISION (int_mode) - 1 - i);
6391 : 0 : if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6392 : 0 : return XEXP (x, 0);
6393 : : else
6394 : : return x;
6395 : : }
6396 : :
6397 : : /* If the code changed, return a whole new comparison.
6398 : : We also need to avoid using SUBST in cases where
6399 : : simplify_comparison has widened a comparison with a CONST_INT,
6400 : : since in that case the wider CONST_INT may fail the sanity
6401 : : checks in do_SUBST. */
6402 : 12300758 : if (new_code != code
6403 : 11913821 : || (CONST_INT_P (op1)
6404 : 6907751 : && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6405 : 10804 : && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6406 : 396450 : return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6407 : :
6408 : : /* Otherwise, keep this operation, but maybe change its operands.
6409 : : This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6410 : 11904308 : SUBST (XEXP (x, 0), op0);
6411 : 11904308 : SUBST (XEXP (x, 1), op1);
6412 : : }
6413 : : break;
6414 : :
6415 : 11789707 : case IF_THEN_ELSE:
6416 : 11789707 : return simplify_if_then_else (x);
6417 : :
6418 : 4924058 : case ZERO_EXTRACT:
6419 : 4924058 : case SIGN_EXTRACT:
6420 : 4924058 : case ZERO_EXTEND:
6421 : 4924058 : case SIGN_EXTEND:
6422 : : /* If we are processing SET_DEST, we are done. */
6423 : 4924058 : if (in_dest)
6424 : : return x;
6425 : :
6426 : 4921381 : return expand_compound_operation (x);
6427 : :
6428 : 45759429 : case SET:
6429 : 45759429 : return simplify_set (x);
6430 : :
6431 : 11727936 : case AND:
6432 : 11727936 : case IOR:
6433 : 11727936 : return simplify_logical (x);
6434 : :
6435 : 13897623 : case ASHIFT:
6436 : 13897623 : case LSHIFTRT:
6437 : 13897623 : case ASHIFTRT:
6438 : 13897623 : case ROTATE:
6439 : 13897623 : case ROTATERT:
6440 : : /* If this is a shift by a constant amount, simplify it. */
6441 : 13897623 : if (CONST_INT_P (XEXP (x, 1)))
6442 : 13434899 : return simplify_shift_const (x, code, mode, XEXP (x, 0),
6443 : 13434899 : INTVAL (XEXP (x, 1)));
6444 : :
6445 : : else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6446 : : SUBST (XEXP (x, 1),
6447 : : force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6448 : : (HOST_WIDE_INT_1U
6449 : : << exact_log2 (GET_MODE_UNIT_BITSIZE
6450 : : (GET_MODE (x)))) - 1, false));
6451 : : break;
6452 : 1715158 : case VEC_SELECT:
6453 : 1715158 : {
6454 : 1715158 : rtx trueop0 = XEXP (x, 0);
6455 : 1715158 : mode = GET_MODE (trueop0);
6456 : 1715158 : rtx trueop1 = XEXP (x, 1);
6457 : : /* If we select a low-part subreg, return that. */
6458 : 1715158 : if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6459 : : {
6460 : 807 : rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6461 : 807 : if (new_rtx != NULL_RTX)
6462 : : return new_rtx;
6463 : : }
6464 : : }
6465 : :
6466 : : default:
6467 : : break;
6468 : : }
6469 : :
6470 : : return x;
6471 : : }
6472 : :
6473 : : /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6474 : :
6475 : : static rtx
6476 : 11789707 : simplify_if_then_else (rtx x)
6477 : : {
6478 : 11789707 : machine_mode mode = GET_MODE (x);
6479 : 11789707 : rtx cond = XEXP (x, 0);
6480 : 11789707 : rtx true_rtx = XEXP (x, 1);
6481 : 11789707 : rtx false_rtx = XEXP (x, 2);
6482 : 11789707 : enum rtx_code true_code = GET_CODE (cond);
6483 : 11789707 : bool comparison_p = COMPARISON_P (cond);
6484 : 11789707 : rtx temp;
6485 : 11789707 : int i;
6486 : 11789707 : enum rtx_code false_code;
6487 : 11789707 : rtx reversed;
6488 : 11789707 : scalar_int_mode int_mode, inner_mode;
6489 : :
6490 : : /* Simplify storing of the truth value. */
6491 : 11789707 : if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6492 : 0 : return simplify_gen_relational (true_code, mode, VOIDmode,
6493 : 0 : XEXP (cond, 0), XEXP (cond, 1));
6494 : :
6495 : : /* Also when the truth value has to be reversed. */
6496 : 11789072 : if (comparison_p
6497 : 11789072 : && true_rtx == const0_rtx && false_rtx == const_true_rtx
6498 : 0 : && (reversed = reversed_comparison (cond, mode)))
6499 : : return reversed;
6500 : :
6501 : : /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6502 : : in it is being compared against certain values. Get the true and false
6503 : : comparisons and see if that says anything about the value of each arm. */
6504 : :
6505 : 11789707 : if (comparison_p
6506 : 11789072 : && ((false_code = reversed_comparison_code (cond, NULL))
6507 : : != UNKNOWN)
6508 : 23434505 : && REG_P (XEXP (cond, 0)))
6509 : : {
6510 : 7568107 : HOST_WIDE_INT nzb;
6511 : 7568107 : rtx from = XEXP (cond, 0);
6512 : 7568107 : rtx true_val = XEXP (cond, 1);
6513 : 7568107 : rtx false_val = true_val;
6514 : 7568107 : bool swapped = false;
6515 : :
6516 : : /* If FALSE_CODE is EQ, swap the codes and arms. */
6517 : :
6518 : 7568107 : if (false_code == EQ)
6519 : : {
6520 : 2857085 : swapped = true, true_code = EQ, false_code = NE;
6521 : 2857085 : std::swap (true_rtx, false_rtx);
6522 : : }
6523 : :
6524 : 7568107 : scalar_int_mode from_mode;
6525 : 7568107 : if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6526 : : {
6527 : : /* If we are comparing against zero and the expression being
6528 : : tested has only a single bit that might be nonzero, that is
6529 : : its value when it is not equal to zero. Similarly if it is
6530 : : known to be -1 or 0. */
6531 : 6384313 : if (true_code == EQ
6532 : 4746064 : && true_val == const0_rtx
6533 : 8337504 : && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6534 : : {
6535 : 202863 : false_code = EQ;
6536 : 202863 : false_val = gen_int_mode (nzb, from_mode);
6537 : : }
6538 : 6181450 : else if (true_code == EQ
6539 : 4543201 : && true_val == const0_rtx
6540 : 7931778 : && (num_sign_bit_copies (from, from_mode)
6541 : 1750328 : == GET_MODE_PRECISION (from_mode)))
6542 : : {
6543 : 850 : false_code = EQ;
6544 : 850 : false_val = constm1_rtx;
6545 : : }
6546 : : }
6547 : :
6548 : : /* Now simplify an arm if we know the value of the register in the
6549 : : branch and it is used in the arm. Be careful due to the potential
6550 : : of locally-shared RTL. */
6551 : :
6552 : 7568107 : if (reg_mentioned_p (from, true_rtx))
6553 : 276030 : true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6554 : : from, true_val),
6555 : : pc_rtx, pc_rtx, false, false, false);
6556 : 7568107 : if (reg_mentioned_p (from, false_rtx))
6557 : 90794 : false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6558 : : from, false_val),
6559 : : pc_rtx, pc_rtx, false, false, false);
6560 : :
6561 : 12279129 : SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6562 : 12279129 : SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6563 : :
6564 : 7568107 : true_rtx = XEXP (x, 1);
6565 : 7568107 : false_rtx = XEXP (x, 2);
6566 : 7568107 : true_code = GET_CODE (cond);
6567 : : }
6568 : :
6569 : : /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6570 : : reversed, do so to avoid needing two sets of patterns for
6571 : : subtract-and-branch insns. Similarly if we have a constant in the true
6572 : : arm, the false arm is the same as the first operand of the comparison, or
6573 : : the false arm is more complicated than the true arm. */
6574 : :
6575 : 11789707 : if (comparison_p
6576 : 11789072 : && reversed_comparison_code (cond, NULL) != UNKNOWN
6577 : 23434505 : && (true_rtx == pc_rtx
6578 : 11644798 : || (CONSTANT_P (true_rtx)
6579 : 9798786 : && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6580 : 11609297 : || true_rtx == const0_rtx
6581 : 11609111 : || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6582 : 11575618 : || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6583 : 9547 : && !OBJECT_P (false_rtx))
6584 : 11573938 : || reg_mentioned_p (true_rtx, false_rtx)
6585 : 11573851 : || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6586 : : {
6587 : 99069 : SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6588 : 99069 : SUBST (XEXP (x, 1), false_rtx);
6589 : 99069 : SUBST (XEXP (x, 2), true_rtx);
6590 : :
6591 : 99069 : std::swap (true_rtx, false_rtx);
6592 : 99069 : cond = XEXP (x, 0);
6593 : :
6594 : : /* It is possible that the conditional has been simplified out. */
6595 : 99069 : true_code = GET_CODE (cond);
6596 : 99069 : comparison_p = COMPARISON_P (cond);
6597 : : }
6598 : :
6599 : : /* If the two arms are identical, we don't need the comparison. */
6600 : :
6601 : 11789707 : if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6602 : : return true_rtx;
6603 : :
6604 : : /* Convert a == b ? b : a to "a". */
6605 : 3420424 : if (true_code == EQ && ! side_effects_p (cond)
6606 : 3410236 : && !HONOR_NANS (mode)
6607 : 3378757 : && rtx_equal_p (XEXP (cond, 0), false_rtx)
6608 : 11790045 : && rtx_equal_p (XEXP (cond, 1), true_rtx))
6609 : : return false_rtx;
6610 : 4399975 : else if (true_code == NE && ! side_effects_p (cond)
6611 : 4362130 : && !HONOR_NANS (mode)
6612 : 4357985 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6613 : 11833622 : && rtx_equal_p (XEXP (cond, 1), false_rtx))
6614 : : return true_rtx;
6615 : :
6616 : : /* Look for cases where we have (abs x) or (neg (abs X)). */
6617 : :
6618 : 11789695 : if (GET_MODE_CLASS (mode) == MODE_INT
6619 : 1784320 : && comparison_p
6620 : 1784301 : && XEXP (cond, 1) == const0_rtx
6621 : 1361741 : && GET_CODE (false_rtx) == NEG
6622 : 23 : && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6623 : 0 : && rtx_equal_p (true_rtx, XEXP (cond, 0))
6624 : 11789695 : && ! side_effects_p (true_rtx))
6625 : 0 : switch (true_code)
6626 : : {
6627 : 0 : case GT:
6628 : 0 : case GE:
6629 : 0 : return simplify_gen_unary (ABS, mode, true_rtx, mode);
6630 : 0 : case LT:
6631 : 0 : case LE:
6632 : 0 : return
6633 : 0 : simplify_gen_unary (NEG, mode,
6634 : : simplify_gen_unary (ABS, mode, true_rtx, mode),
6635 : 0 : mode);
6636 : : default:
6637 : : break;
6638 : : }
6639 : :
6640 : : /* Look for MIN or MAX. */
6641 : :
6642 : 11789695 : if ((! FLOAT_MODE_P (mode)
6643 : 41565 : || (flag_unsafe_math_optimizations
6644 : 479 : && !HONOR_NANS (mode)
6645 : 479 : && !HONOR_SIGNED_ZEROS (mode)))
6646 : 11748609 : && comparison_p
6647 : 11748113 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6648 : 84910 : && rtx_equal_p (XEXP (cond, 1), false_rtx)
6649 : 10609 : && ! side_effects_p (cond))
6650 : 10609 : switch (true_code)
6651 : : {
6652 : 3485 : case GE:
6653 : 3485 : case GT:
6654 : 3485 : return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6655 : 3502 : case LE:
6656 : 3502 : case LT:
6657 : 3502 : return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6658 : 2776 : case GEU:
6659 : 2776 : case GTU:
6660 : 2776 : return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6661 : 846 : case LEU:
6662 : 846 : case LTU:
6663 : 846 : return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6664 : : default:
6665 : : break;
6666 : : }
6667 : :
6668 : : /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6669 : : second operand is zero, this can be done as (OP Z (mult COND C2)) where
6670 : : C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6671 : : SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6672 : : We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6673 : : neither 1 or -1, but it isn't worth checking for. */
6674 : :
6675 : 11779086 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6676 : : && comparison_p
6677 : 13460491 : && is_int_mode (mode, &int_mode)
6678 : 13552798 : && ! side_effects_p (x))
6679 : : {
6680 : 1770754 : rtx t = make_compound_operation (true_rtx, SET);
6681 : 1770754 : rtx f = make_compound_operation (false_rtx, SET);
6682 : 1770754 : rtx cond_op0 = XEXP (cond, 0);
6683 : 1770754 : rtx cond_op1 = XEXP (cond, 1);
6684 : 1770754 : enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6685 : 1770754 : scalar_int_mode m = int_mode;
6686 : 1770754 : rtx z = 0, c1 = NULL_RTX;
6687 : :
6688 : 1770754 : if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6689 : : || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6690 : : || GET_CODE (t) == ASHIFT
6691 : : || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6692 : 197383 : && rtx_equal_p (XEXP (t, 0), f))
6693 : 84923 : c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6694 : :
6695 : : /* If an identity-zero op is commutative, check whether there
6696 : : would be a match if we swapped the operands. */
6697 : 1625612 : else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6698 : 1614482 : || GET_CODE (t) == XOR)
6699 : 1698263 : && rtx_equal_p (XEXP (t, 1), f))
6700 : 7384 : c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6701 : 1678447 : else if (GET_CODE (t) == SIGN_EXTEND
6702 : 1196 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6703 : 1196 : && (GET_CODE (XEXP (t, 0)) == PLUS
6704 : 1196 : || GET_CODE (XEXP (t, 0)) == MINUS
6705 : : || GET_CODE (XEXP (t, 0)) == IOR
6706 : : || GET_CODE (XEXP (t, 0)) == XOR
6707 : : || GET_CODE (XEXP (t, 0)) == ASHIFT
6708 : : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6709 : : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6710 : 46 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6711 : 38 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6712 : 38 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6713 : 1678447 : && (num_sign_bit_copies (f, GET_MODE (f))
6714 : 0 : > (unsigned int)
6715 : 0 : (GET_MODE_PRECISION (int_mode)
6716 : 0 : - GET_MODE_PRECISION (inner_mode))))
6717 : : {
6718 : 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6719 : 0 : extend_op = SIGN_EXTEND;
6720 : 0 : m = inner_mode;
6721 : : }
6722 : 1678447 : else if (GET_CODE (t) == SIGN_EXTEND
6723 : 1196 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6724 : 1196 : && (GET_CODE (XEXP (t, 0)) == PLUS
6725 : 1155 : || GET_CODE (XEXP (t, 0)) == IOR
6726 : 1152 : || GET_CODE (XEXP (t, 0)) == XOR)
6727 : 44 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6728 : 2 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6729 : 2 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6730 : 1678449 : && (num_sign_bit_copies (f, GET_MODE (f))
6731 : 2 : > (unsigned int)
6732 : 2 : (GET_MODE_PRECISION (int_mode)
6733 : 2 : - GET_MODE_PRECISION (inner_mode))))
6734 : : {
6735 : 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6736 : 0 : extend_op = SIGN_EXTEND;
6737 : 0 : m = inner_mode;
6738 : : }
6739 : 1678447 : else if (GET_CODE (t) == ZERO_EXTEND
6740 : 2876 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6741 : 2876 : && (GET_CODE (XEXP (t, 0)) == PLUS
6742 : 2876 : || GET_CODE (XEXP (t, 0)) == MINUS
6743 : : || GET_CODE (XEXP (t, 0)) == IOR
6744 : : || GET_CODE (XEXP (t, 0)) == XOR
6745 : : || GET_CODE (XEXP (t, 0)) == ASHIFT
6746 : : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6747 : : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6748 : 721 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6749 : 95 : && HWI_COMPUTABLE_MODE_P (int_mode)
6750 : 95 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6751 : 95 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6752 : 1678447 : && ((nonzero_bits (f, GET_MODE (f))
6753 : 0 : & ~GET_MODE_MASK (inner_mode))
6754 : : == 0))
6755 : : {
6756 : 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6757 : 0 : extend_op = ZERO_EXTEND;
6758 : 0 : m = inner_mode;
6759 : : }
6760 : 1678447 : else if (GET_CODE (t) == ZERO_EXTEND
6761 : 2876 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6762 : 2876 : && (GET_CODE (XEXP (t, 0)) == PLUS
6763 : 2563 : || GET_CODE (XEXP (t, 0)) == IOR
6764 : 2563 : || GET_CODE (XEXP (t, 0)) == XOR)
6765 : 313 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6766 : 12 : && HWI_COMPUTABLE_MODE_P (int_mode)
6767 : 12 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6768 : 12 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6769 : 1678447 : && ((nonzero_bits (f, GET_MODE (f))
6770 : 0 : & ~GET_MODE_MASK (inner_mode))
6771 : : == 0))
6772 : : {
6773 : 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6774 : 0 : extend_op = ZERO_EXTEND;
6775 : 0 : m = inner_mode;
6776 : : }
6777 : :
6778 : 92307 : if (z)
6779 : : {
6780 : 92307 : machine_mode cm = m;
6781 : 92307 : if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6782 : 394 : && GET_MODE (c1) != VOIDmode)
6783 : 75 : cm = GET_MODE (c1);
6784 : 92307 : temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6785 : : cond_op0, cond_op1),
6786 : : pc_rtx, pc_rtx, false, false, false);
6787 : 92307 : temp = simplify_gen_binary (MULT, cm, temp,
6788 : : simplify_gen_binary (MULT, cm, c1,
6789 : : const_true_rtx));
6790 : 92307 : temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6791 : 92307 : temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6792 : :
6793 : 92307 : if (extend_op != UNKNOWN)
6794 : 0 : temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6795 : :
6796 : 92307 : return temp;
6797 : : }
6798 : : }
6799 : :
6800 : : /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6801 : : 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6802 : : negation of a single bit, we can convert this operation to a shift. We
6803 : : can actually do this more generally, but it doesn't seem worth it. */
6804 : :
6805 : 11686779 : if (true_code == NE
6806 : 11686779 : && is_a <scalar_int_mode> (mode, &int_mode)
6807 : 382517 : && XEXP (cond, 1) == const0_rtx
6808 : 251512 : && false_rtx == const0_rtx
6809 : 24380 : && CONST_INT_P (true_rtx)
6810 : 11687154 : && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6811 : 0 : && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6812 : 375 : || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6813 : 375 : == GET_MODE_PRECISION (int_mode))
6814 : 0 : && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6815 : 0 : return
6816 : 0 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6817 : 0 : gen_lowpart (int_mode, XEXP (cond, 0)), i);
6818 : :
6819 : : /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6820 : : non-zero bit in A is C1. */
6821 : 4366973 : if (true_code == NE && XEXP (cond, 1) == const0_rtx
6822 : 1925541 : && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6823 : 11790082 : && is_a <scalar_int_mode> (mode, &int_mode)
6824 : 375 : && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6825 : 38 : && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6826 : 38 : == nonzero_bits (XEXP (cond, 0), inner_mode)
6827 : 11686779 : && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6828 : : {
6829 : 0 : rtx val = XEXP (cond, 0);
6830 : 0 : if (inner_mode == int_mode)
6831 : : return val;
6832 : 0 : else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6833 : 0 : return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6834 : : }
6835 : :
6836 : : return x;
6837 : : }
6838 : :
6839 : : /* Simplify X, a SET expression. Return the new expression. */
6840 : :
6841 : : static rtx
6842 : 45759429 : simplify_set (rtx x)
6843 : : {
6844 : 45759429 : rtx src = SET_SRC (x);
6845 : 45759429 : rtx dest = SET_DEST (x);
6846 : 101908267 : machine_mode mode
6847 : 45759429 : = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6848 : 45759429 : rtx_insn *other_insn;
6849 : 45759429 : rtx *cc_use;
6850 : 45759429 : scalar_int_mode int_mode;
6851 : :
6852 : : /* (set (pc) (return)) gets written as (return). */
6853 : 45759429 : if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6854 : : return src;
6855 : :
6856 : : /* Now that we know for sure which bits of SRC we are using, see if we can
6857 : : simplify the expression for the object knowing that we only need the
6858 : : low-order bits. */
6859 : :
6860 : 45759429 : if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6861 : : {
6862 : 21217105 : src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6863 : 21217105 : SUBST (SET_SRC (x), src);
6864 : : }
6865 : :
6866 : : /* If the source is a COMPARE, look for the use of the comparison result
6867 : : and try to simplify it unless we already have used undobuf.other_insn. */
6868 : 39416447 : if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6869 : 6342982 : && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6870 : 5818879 : && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6871 : 5818879 : && COMPARISON_P (*cc_use)
6872 : 51577810 : && rtx_equal_p (XEXP (*cc_use, 0), dest))
6873 : : {
6874 : 5816849 : enum rtx_code old_code = GET_CODE (*cc_use);
6875 : 5816849 : enum rtx_code new_code;
6876 : 5816849 : rtx op0, op1, tmp;
6877 : 5816849 : bool other_changed = false;
6878 : 5816849 : rtx inner_compare = NULL_RTX;
6879 : 5816849 : machine_mode compare_mode = GET_MODE (dest);
6880 : :
6881 : 5816849 : if (GET_CODE (src) == COMPARE)
6882 : : {
6883 : 5466377 : op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6884 : 5466377 : if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6885 : : {
6886 : 0 : inner_compare = op0;
6887 : 0 : op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6888 : : }
6889 : : }
6890 : : else
6891 : 350472 : op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6892 : :
6893 : 5816849 : tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6894 : : op0, op1);
6895 : 5816849 : if (!tmp)
6896 : : new_code = old_code;
6897 : 451632 : else if (!CONSTANT_P (tmp))
6898 : : {
6899 : 445950 : new_code = GET_CODE (tmp);
6900 : 445950 : op0 = XEXP (tmp, 0);
6901 : 445950 : op1 = XEXP (tmp, 1);
6902 : : }
6903 : : else
6904 : : {
6905 : 5682 : rtx pat = PATTERN (other_insn);
6906 : 5682 : undobuf.other_insn = other_insn;
6907 : 5682 : SUBST (*cc_use, tmp);
6908 : :
6909 : : /* Attempt to simplify CC user. */
6910 : 5682 : if (GET_CODE (pat) == SET)
6911 : : {
6912 : 5173 : rtx new_rtx = simplify_rtx (SET_SRC (pat));
6913 : 5173 : if (new_rtx != NULL_RTX)
6914 : 4377 : SUBST (SET_SRC (pat), new_rtx);
6915 : : }
6916 : :
6917 : : /* Convert X into a no-op move. */
6918 : 5682 : SUBST (SET_DEST (x), pc_rtx);
6919 : 5682 : SUBST (SET_SRC (x), pc_rtx);
6920 : 5682 : return x;
6921 : : }
6922 : :
6923 : : /* Simplify our comparison, if possible. */
6924 : 5811167 : new_code = simplify_comparison (new_code, &op0, &op1);
6925 : :
6926 : : #ifdef SELECT_CC_MODE
6927 : : /* If this machine has CC modes other than CCmode, check to see if we
6928 : : need to use a different CC mode here. */
6929 : 5811167 : if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6930 : 547144 : compare_mode = GET_MODE (op0);
6931 : 5264023 : else if (inner_compare
6932 : 0 : && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6933 : 0 : && new_code == old_code
6934 : 0 : && op0 == XEXP (inner_compare, 0)
6935 : 0 : && op1 == XEXP (inner_compare, 1))
6936 : 0 : compare_mode = GET_MODE (inner_compare);
6937 : : else
6938 : 5264023 : compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6939 : :
6940 : : /* If the mode changed, we have to change SET_DEST, the mode in the
6941 : : compare, and the mode in the place SET_DEST is used. If SET_DEST is
6942 : : a hard register, just build new versions with the proper mode. If it
6943 : : is a pseudo, we lose unless it is only time we set the pseudo, in
6944 : : which case we can safely change its mode. */
6945 : 5811167 : if (compare_mode != GET_MODE (dest))
6946 : : {
6947 : 230549 : if (can_change_dest_mode (dest, 0, compare_mode))
6948 : : {
6949 : 230549 : unsigned int regno = REGNO (dest);
6950 : 230549 : rtx new_dest;
6951 : :
6952 : 230549 : if (regno < FIRST_PSEUDO_REGISTER)
6953 : 230549 : new_dest = gen_rtx_REG (compare_mode, regno);
6954 : : else
6955 : : {
6956 : 0 : subst_mode (regno, compare_mode);
6957 : 0 : new_dest = regno_reg_rtx[regno];
6958 : : }
6959 : :
6960 : 230549 : SUBST (SET_DEST (x), new_dest);
6961 : 230549 : SUBST (XEXP (*cc_use, 0), new_dest);
6962 : 230549 : other_changed = true;
6963 : :
6964 : 230549 : dest = new_dest;
6965 : : }
6966 : : }
6967 : : #endif /* SELECT_CC_MODE */
6968 : :
6969 : : /* If the code changed, we have to build a new comparison in
6970 : : undobuf.other_insn. */
6971 : 5811167 : if (new_code != old_code)
6972 : : {
6973 : 620903 : bool other_changed_previously = other_changed;
6974 : 620903 : unsigned HOST_WIDE_INT mask;
6975 : 620903 : rtx old_cc_use = *cc_use;
6976 : :
6977 : 620903 : SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6978 : : dest, const0_rtx));
6979 : 620903 : other_changed = true;
6980 : :
6981 : : /* If the only change we made was to change an EQ into an NE or
6982 : : vice versa, OP0 has only one bit that might be nonzero, and OP1
6983 : : is zero, check if changing the user of the condition code will
6984 : : produce a valid insn. If it won't, we can keep the original code
6985 : : in that insn by surrounding our operation with an XOR. */
6986 : :
6987 : 620903 : if (((old_code == NE && new_code == EQ)
6988 : 589219 : || (old_code == EQ && new_code == NE))
6989 : 67666 : && ! other_changed_previously && op1 == const0_rtx
6990 : 65150 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6991 : 629300 : && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
6992 : : {
6993 : 8385 : rtx pat = PATTERN (other_insn), note = 0;
6994 : :
6995 : 8385 : if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6996 : 8385 : && ! check_asm_operands (pat)))
6997 : : {
6998 : 4 : *cc_use = old_cc_use;
6999 : 4 : other_changed = false;
7000 : :
7001 : 4 : op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
7002 : 4 : gen_int_mode (mask,
7003 : 4 : GET_MODE (op0)));
7004 : : }
7005 : : }
7006 : : }
7007 : :
7008 : 5198649 : if (other_changed)
7009 : 642927 : undobuf.other_insn = other_insn;
7010 : :
7011 : : /* Don't generate a compare of a CC with 0, just use that CC. */
7012 : 5811167 : if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
7013 : : {
7014 : 547144 : SUBST (SET_SRC (x), op0);
7015 : 547144 : src = SET_SRC (x);
7016 : : }
7017 : : /* Otherwise, if we didn't previously have the same COMPARE we
7018 : : want, create it from scratch. */
7019 : 5264023 : else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
7020 : 5128598 : || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
7021 : : {
7022 : 1406825 : SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
7023 : 1406825 : src = SET_SRC (x);
7024 : : }
7025 : : }
7026 : : else
7027 : : {
7028 : : /* Get SET_SRC in a form where we have placed back any
7029 : : compound expressions. Then do the checks below. */
7030 : 39942580 : src = make_compound_operation (src, SET);
7031 : 39942580 : SUBST (SET_SRC (x), src);
7032 : : }
7033 : :
7034 : : /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7035 : : and X being a REG or (subreg (reg)), we may be able to convert this to
7036 : : (set (subreg:m2 x) (op)).
7037 : :
7038 : : We can always do this if M1 is narrower than M2 because that means that
7039 : : we only care about the low bits of the result.
7040 : :
7041 : : However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7042 : : perform a narrower operation than requested since the high-order bits will
7043 : : be undefined. On machine where it is defined, this transformation is safe
7044 : : as long as M1 and M2 have the same number of words. */
7045 : :
7046 : 432650 : if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7047 : 413052 : && !OBJECT_P (SUBREG_REG (src))
7048 : : && (known_equal_after_align_up
7049 : 262361 : (GET_MODE_SIZE (GET_MODE (src)),
7050 : 524722 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7051 : 262361 : UNITS_PER_WORD))
7052 : 238292 : && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7053 : 233363 : && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7054 : 137 : && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7055 : : GET_MODE (SUBREG_REG (src)),
7056 : : GET_MODE (src)))
7057 : 45986973 : && (REG_P (dest)
7058 : 103400 : || (GET_CODE (dest) == SUBREG
7059 : 260 : && REG_P (SUBREG_REG (dest)))))
7060 : : {
7061 : 130086 : SUBST (SET_DEST (x),
7062 : : gen_lowpart (GET_MODE (SUBREG_REG (src)),
7063 : : dest));
7064 : 130086 : SUBST (SET_SRC (x), SUBREG_REG (src));
7065 : :
7066 : 130086 : src = SET_SRC (x), dest = SET_DEST (x);
7067 : : }
7068 : :
7069 : : /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7070 : : would require a paradoxical subreg. Replace the subreg with a
7071 : : zero_extend to avoid the reload that would otherwise be required.
7072 : : Don't do this unless we have a scalar integer mode, otherwise the
7073 : : transformation is incorrect. */
7074 : :
7075 : 45753747 : enum rtx_code extend_op;
7076 : 45753747 : if (paradoxical_subreg_p (src)
7077 : : && MEM_P (SUBREG_REG (src))
7078 : : && SCALAR_INT_MODE_P (GET_MODE (src))
7079 : : && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7080 : : {
7081 : : SUBST (SET_SRC (x),
7082 : : gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7083 : :
7084 : : src = SET_SRC (x);
7085 : : }
7086 : :
7087 : : /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7088 : : are comparing an item known to be 0 or -1 against 0, use a logical
7089 : : operation instead. Check for one of the arms being an IOR of the other
7090 : : arm with some value. We compute three terms to be IOR'ed together. In
7091 : : practice, at most two will be nonzero. Then we do the IOR's. */
7092 : :
7093 : 45753747 : if (GET_CODE (dest) != PC
7094 : 35874773 : && GET_CODE (src) == IF_THEN_ELSE
7095 : 1059206 : && is_int_mode (GET_MODE (src), &int_mode)
7096 : 984411 : && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7097 : 456487 : && XEXP (XEXP (src, 0), 1) == const0_rtx
7098 : 291679 : && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7099 : 81145 : && (!HAVE_conditional_move
7100 : 81145 : || ! can_conditionally_move_p (int_mode))
7101 : 0 : && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7102 : 0 : == GET_MODE_PRECISION (int_mode))
7103 : 45753747 : && ! side_effects_p (src))
7104 : : {
7105 : 0 : rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7106 : 0 : ? XEXP (src, 1) : XEXP (src, 2));
7107 : 0 : rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7108 : 0 : ? XEXP (src, 2) : XEXP (src, 1));
7109 : 0 : rtx term1 = const0_rtx, term2, term3;
7110 : :
7111 : 0 : if (GET_CODE (true_rtx) == IOR
7112 : 0 : && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7113 : 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7114 : 0 : else if (GET_CODE (true_rtx) == IOR
7115 : 0 : && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7116 : 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7117 : 0 : else if (GET_CODE (false_rtx) == IOR
7118 : 0 : && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7119 : 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7120 : 0 : else if (GET_CODE (false_rtx) == IOR
7121 : 0 : && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7122 : 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7123 : :
7124 : 0 : term2 = simplify_gen_binary (AND, int_mode,
7125 : 0 : XEXP (XEXP (src, 0), 0), true_rtx);
7126 : 0 : term3 = simplify_gen_binary (AND, int_mode,
7127 : : simplify_gen_unary (NOT, int_mode,
7128 : 0 : XEXP (XEXP (src, 0), 0),
7129 : : int_mode),
7130 : : false_rtx);
7131 : :
7132 : 0 : SUBST (SET_SRC (x),
7133 : : simplify_gen_binary (IOR, int_mode,
7134 : : simplify_gen_binary (IOR, int_mode,
7135 : : term1, term2),
7136 : : term3));
7137 : :
7138 : 0 : src = SET_SRC (x);
7139 : : }
7140 : :
7141 : : /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7142 : : whole thing fail. */
7143 : 45753747 : if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7144 : : return src;
7145 : 45753723 : else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7146 : : return dest;
7147 : : else
7148 : : /* Convert this into a field assignment operation, if possible. */
7149 : 45753723 : return make_field_assignment (x);
7150 : : }
7151 : :
7152 : : /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7153 : : result. */
7154 : :
7155 : : static rtx
7156 : 11727936 : simplify_logical (rtx x)
7157 : : {
7158 : 11727936 : rtx op0 = XEXP (x, 0);
7159 : 11727936 : rtx op1 = XEXP (x, 1);
7160 : 11727936 : scalar_int_mode mode;
7161 : :
7162 : 11727936 : switch (GET_CODE (x))
7163 : : {
7164 : 7146170 : case AND:
7165 : : /* We can call simplify_and_const_int only if we don't lose
7166 : : any (sign) bits when converting INTVAL (op1) to
7167 : : "unsigned HOST_WIDE_INT". */
7168 : 7146170 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7169 : 6721387 : && CONST_INT_P (op1)
7170 : 5419788 : && (HWI_COMPUTABLE_MODE_P (mode)
7171 : 9508 : || INTVAL (op1) > 0))
7172 : : {
7173 : 5418704 : x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7174 : 5418704 : if (GET_CODE (x) != AND)
7175 : : return x;
7176 : :
7177 : 5382815 : op0 = XEXP (x, 0);
7178 : 5382815 : op1 = XEXP (x, 1);
7179 : : }
7180 : :
7181 : : /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7182 : : apply the distributive law and then the inverse distributive
7183 : : law to see if things simplify. */
7184 : 7110281 : if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7185 : : {
7186 : 114681 : rtx result = distribute_and_simplify_rtx (x, 0);
7187 : 114681 : if (result)
7188 : : return result;
7189 : : }
7190 : 7095772 : if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7191 : : {
7192 : 1731 : rtx result = distribute_and_simplify_rtx (x, 1);
7193 : 1731 : if (result)
7194 : : return result;
7195 : : }
7196 : : break;
7197 : :
7198 : 4581766 : case IOR:
7199 : : /* If we have (ior (and A B) C), apply the distributive law and then
7200 : : the inverse distributive law to see if things simplify. */
7201 : :
7202 : 4581766 : if (GET_CODE (op0) == AND)
7203 : : {
7204 : 1253981 : rtx result = distribute_and_simplify_rtx (x, 0);
7205 : 1253981 : if (result)
7206 : : return result;
7207 : : }
7208 : :
7209 : 4581686 : if (GET_CODE (op1) == AND)
7210 : : {
7211 : 70194 : rtx result = distribute_and_simplify_rtx (x, 1);
7212 : 70194 : if (result)
7213 : : return result;
7214 : : }
7215 : : break;
7216 : :
7217 : 0 : default:
7218 : 0 : gcc_unreachable ();
7219 : : }
7220 : :
7221 : : return x;
7222 : : }
7223 : :
7224 : : /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7225 : : operations" because they can be replaced with two more basic operations.
7226 : : ZERO_EXTEND is also considered "compound" because it can be replaced with
7227 : : an AND operation, which is simpler, though only one operation.
7228 : :
7229 : : The function expand_compound_operation is called with an rtx expression
7230 : : and will convert it to the appropriate shifts and AND operations,
7231 : : simplifying at each stage.
7232 : :
7233 : : The function make_compound_operation is called to convert an expression
7234 : : consisting of shifts and ANDs into the equivalent compound expression.
7235 : : It is the inverse of this function, loosely speaking. */
7236 : :
7237 : : static rtx
7238 : 16884401 : expand_compound_operation (rtx x)
7239 : : {
7240 : 16884401 : unsigned HOST_WIDE_INT pos = 0, len;
7241 : 16884401 : bool unsignedp = false;
7242 : 16884401 : unsigned int modewidth;
7243 : 16884401 : rtx tem;
7244 : 16884401 : scalar_int_mode inner_mode;
7245 : :
7246 : 16884401 : switch (GET_CODE (x))
7247 : : {
7248 : 4875125 : case ZERO_EXTEND:
7249 : 4875125 : unsignedp = true;
7250 : : /* FALLTHRU */
7251 : 6195933 : case SIGN_EXTEND:
7252 : : /* We can't necessarily use a const_int for a multiword mode;
7253 : : it depends on implicitly extending the value.
7254 : : Since we don't know the right way to extend it,
7255 : : we can't tell whether the implicit way is right.
7256 : :
7257 : : Even for a mode that is no wider than a const_int,
7258 : : we can't win, because we need to sign extend one of its bits through
7259 : : the rest of it, and we don't know which bit. */
7260 : 6195933 : if (CONST_INT_P (XEXP (x, 0)))
7261 : : return x;
7262 : :
7263 : : /* Reject modes that aren't scalar integers because turning vector
7264 : : or complex modes into shifts causes problems. */
7265 : 6195933 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7266 : : return x;
7267 : :
7268 : : /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7269 : : (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7270 : : because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7271 : : reloaded. If not for that, MEM's would very rarely be safe.
7272 : :
7273 : : Reject modes bigger than a word, because we might not be able
7274 : : to reference a two-register group starting with an arbitrary register
7275 : : (and currently gen_lowpart might crash for a SUBREG). */
7276 : :
7277 : 12514694 : if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7278 : : return x;
7279 : :
7280 : 5869298 : len = GET_MODE_PRECISION (inner_mode);
7281 : : /* If the inner object has VOIDmode (the only way this can happen
7282 : : is if it is an ASM_OPERANDS), we can't do anything since we don't
7283 : : know how much masking to do. */
7284 : 5869298 : if (len == 0)
7285 : : return x;
7286 : :
7287 : : break;
7288 : :
7289 : 896652 : case ZERO_EXTRACT:
7290 : 896652 : unsignedp = true;
7291 : :
7292 : : /* fall through */
7293 : :
7294 : 918761 : case SIGN_EXTRACT:
7295 : : /* If the operand is a CLOBBER, just return it. */
7296 : 918761 : if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7297 : : return XEXP (x, 0);
7298 : :
7299 : 918761 : if (!CONST_INT_P (XEXP (x, 1))
7300 : 918630 : || !CONST_INT_P (XEXP (x, 2)))
7301 : : return x;
7302 : :
7303 : : /* Reject modes that aren't scalar integers because turning vector
7304 : : or complex modes into shifts causes problems. */
7305 : 14246263 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7306 : : return x;
7307 : :
7308 : 827838 : len = INTVAL (XEXP (x, 1));
7309 : 827838 : pos = INTVAL (XEXP (x, 2));
7310 : :
7311 : : /* This should stay within the object being extracted, fail otherwise. */
7312 : 827838 : if (len + pos > GET_MODE_PRECISION (inner_mode))
7313 : : return x;
7314 : :
7315 : : if (BITS_BIG_ENDIAN)
7316 : : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7317 : :
7318 : : break;
7319 : :
7320 : : default:
7321 : : return x;
7322 : : }
7323 : :
7324 : : /* We've rejected non-scalar operations by now. */
7325 : 6697110 : scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7326 : :
7327 : : /* Convert sign extension to zero extension, if we know that the high
7328 : : bit is not set, as this is easier to optimize. It will be converted
7329 : : back to cheaper alternative in make_extraction. */
7330 : 6697110 : if (GET_CODE (x) == SIGN_EXTEND
7331 : 1177168 : && HWI_COMPUTABLE_MODE_P (mode)
7332 : 7760184 : && ((nonzero_bits (XEXP (x, 0), inner_mode)
7333 : 1063074 : & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7334 : : == 0))
7335 : : {
7336 : 546 : rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7337 : 546 : rtx temp2 = expand_compound_operation (temp);
7338 : :
7339 : : /* Make sure this is a profitable operation. */
7340 : 546 : if (set_src_cost (x, mode, optimize_this_for_speed_p)
7341 : 546 : > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7342 : : return temp2;
7343 : 532 : else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7344 : 532 : > set_src_cost (temp, mode, optimize_this_for_speed_p))
7345 : : return temp;
7346 : : else
7347 : : return x;
7348 : : }
7349 : :
7350 : : /* We can optimize some special cases of ZERO_EXTEND. */
7351 : 6696564 : if (GET_CODE (x) == ZERO_EXTEND)
7352 : : {
7353 : : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7354 : : know that the last value didn't have any inappropriate bits
7355 : : set. */
7356 : 4692130 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7357 : 183 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7358 : 183 : && HWI_COMPUTABLE_MODE_P (mode)
7359 : 4692313 : && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7360 : 183 : & ~GET_MODE_MASK (inner_mode)) == 0)
7361 : 31 : return XEXP (XEXP (x, 0), 0);
7362 : :
7363 : : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7364 : 4692099 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7365 : 616084 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7366 : 574575 : && subreg_lowpart_p (XEXP (x, 0))
7367 : 222000 : && HWI_COMPUTABLE_MODE_P (mode)
7368 : 4889426 : && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7369 : 197327 : & ~GET_MODE_MASK (inner_mode)) == 0)
7370 : 81 : return SUBREG_REG (XEXP (x, 0));
7371 : :
7372 : : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7373 : : is a comparison and STORE_FLAG_VALUE permits. This is like
7374 : : the first case, but it works even when MODE is larger
7375 : : than HOST_WIDE_INT. */
7376 : 4692018 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7377 : 152 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7378 : 152 : && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7379 : 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7380 : 4692018 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7381 : : return XEXP (XEXP (x, 0), 0);
7382 : :
7383 : : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7384 : 4692018 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7385 : 616003 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7386 : 574494 : && subreg_lowpart_p (XEXP (x, 0))
7387 : 221919 : && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7388 : 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7389 : 4692018 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7390 : : return SUBREG_REG (XEXP (x, 0));
7391 : :
7392 : : }
7393 : :
7394 : : /* If we reach here, we want to return a pair of shifts. The inner
7395 : : shift is a left shift of BITSIZE - POS - LEN bits. The outer
7396 : : shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7397 : : logical depending on the value of UNSIGNEDP.
7398 : :
7399 : : If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7400 : : converted into an AND of a shift.
7401 : :
7402 : : We must check for the case where the left shift would have a negative
7403 : : count. This can happen in a case like (x >> 31) & 255 on machines
7404 : : that can't shift by a constant. On those machines, we would first
7405 : : combine the shift with the AND to produce a variable-position
7406 : : extraction. Then the constant of 31 would be substituted in
7407 : : to produce such a position. */
7408 : :
7409 : 6696452 : modewidth = GET_MODE_PRECISION (mode);
7410 : 6696452 : if (modewidth >= pos + len)
7411 : : {
7412 : 6696451 : tem = gen_lowpart (mode, XEXP (x, 0));
7413 : 6696451 : if (!tem || GET_CODE (tem) == CLOBBER)
7414 : : return x;
7415 : 6930738 : tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7416 : 3465369 : tem, modewidth - pos - len);
7417 : 3465369 : tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7418 : 3465369 : mode, tem, modewidth - len);
7419 : : }
7420 : 1 : else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7421 : : {
7422 : 0 : tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7423 : : XEXP (x, 0), pos);
7424 : 0 : tem = gen_lowpart (mode, tem);
7425 : 0 : if (!tem || GET_CODE (tem) == CLOBBER)
7426 : : return x;
7427 : 0 : tem = simplify_and_const_int (NULL_RTX, mode, tem,
7428 : 0 : (HOST_WIDE_INT_1U << len) - 1);
7429 : : }
7430 : : else
7431 : : /* Any other cases we can't handle. */
7432 : : return x;
7433 : :
7434 : : /* If we couldn't do this for some reason, return the original
7435 : : expression. */
7436 : 3465369 : if (GET_CODE (tem) == CLOBBER)
7437 : : return x;
7438 : :
7439 : : return tem;
7440 : : }
7441 : :
7442 : : /* X is a SET which contains an assignment of one object into
7443 : : a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7444 : : or certain SUBREGS). If possible, convert it into a series of
7445 : : logical operations.
7446 : :
7447 : : We half-heartedly support variable positions, but do not at all
7448 : : support variable lengths. */
7449 : :
7450 : : static const_rtx
7451 : 82778841 : expand_field_assignment (const_rtx x)
7452 : : {
7453 : 82778841 : rtx inner;
7454 : 82778841 : rtx pos; /* Always counts from low bit. */
7455 : 82778841 : int len, inner_len;
7456 : 82778841 : rtx mask, cleared, masked;
7457 : 82778841 : scalar_int_mode compute_mode;
7458 : :
7459 : : /* Loop until we find something we can't simplify. */
7460 : 83076542 : while (1)
7461 : : {
7462 : 83076542 : if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7463 : 13471 : && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7464 : : {
7465 : 13471 : rtx x0 = XEXP (SET_DEST (x), 0);
7466 : 13471 : if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7467 : : break;
7468 : 13471 : inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7469 : 13471 : pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7470 : : MAX_MODE_INT);
7471 : 13471 : }
7472 : 83063071 : else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7473 : 4221 : && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7474 : : {
7475 : 4221 : inner = XEXP (SET_DEST (x), 0);
7476 : 4221 : if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7477 : : break;
7478 : :
7479 : 4221 : len = INTVAL (XEXP (SET_DEST (x), 1));
7480 : 4221 : pos = XEXP (SET_DEST (x), 2);
7481 : :
7482 : : /* A constant position should stay within the width of INNER. */
7483 : 4221 : if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7484 : : break;
7485 : :
7486 : : if (BITS_BIG_ENDIAN)
7487 : : {
7488 : : if (CONST_INT_P (pos))
7489 : : pos = GEN_INT (inner_len - len - INTVAL (pos));
7490 : : else if (GET_CODE (pos) == MINUS
7491 : : && CONST_INT_P (XEXP (pos, 1))
7492 : : && INTVAL (XEXP (pos, 1)) == inner_len - len)
7493 : : /* If position is ADJUST - X, new position is X. */
7494 : : pos = XEXP (pos, 0);
7495 : : else
7496 : : pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7497 : : gen_int_mode (inner_len - len,
7498 : : GET_MODE (pos)),
7499 : : pos);
7500 : : }
7501 : : }
7502 : :
7503 : : /* If the destination is a subreg that overwrites the whole of the inner
7504 : : register, we can move the subreg to the source. */
7505 : 83345356 : else if (GET_CODE (SET_DEST (x)) == SUBREG
7506 : : /* We need SUBREGs to compute nonzero_bits properly. */
7507 : 896248 : && nonzero_sign_valid
7508 : 83870486 : && !read_modify_subreg_p (SET_DEST (x)))
7509 : : {
7510 : 286506 : x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7511 : : gen_lowpart
7512 : : (GET_MODE (SUBREG_REG (SET_DEST (x))),
7513 : : SET_SRC (x)));
7514 : 286506 : continue;
7515 : : }
7516 : : else
7517 : : break;
7518 : :
7519 : 19499 : while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7520 : 1807 : inner = SUBREG_REG (inner);
7521 : :
7522 : : /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7523 : 17692 : if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7524 : : {
7525 : : /* Don't do anything for vector or complex integral types. */
7526 : 3996 : if (! FLOAT_MODE_P (GET_MODE (inner)))
7527 : : break;
7528 : :
7529 : : /* Try to find an integral mode to pun with. */
7530 : 38 : if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7531 : 0 : .exists (&compute_mode))
7532 : : break;
7533 : :
7534 : 19 : inner = gen_lowpart (compute_mode, inner);
7535 : : }
7536 : :
7537 : : /* Compute a mask of LEN bits, if we can do this on the host machine. */
7538 : 13715 : if (len >= HOST_BITS_PER_WIDE_INT)
7539 : : break;
7540 : :
7541 : : /* Don't try to compute in too wide unsupported modes. */
7542 : 13715 : if (!targetm.scalar_mode_supported_p (compute_mode))
7543 : : break;
7544 : :
7545 : : /* gen_lowpart_for_combine returns CLOBBER on failure. */
7546 : 13715 : rtx lowpart = gen_lowpart (compute_mode, SET_SRC (x));
7547 : 13715 : if (GET_CODE (lowpart) == CLOBBER)
7548 : : break;
7549 : :
7550 : : /* Now compute the equivalent expression. Make a copy of INNER
7551 : : for the SET_DEST in case it is a MEM into which we will substitute;
7552 : : we don't want shared RTL in that case. */
7553 : 11195 : mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7554 : : compute_mode);
7555 : 11195 : cleared = simplify_gen_binary (AND, compute_mode,
7556 : : simplify_gen_unary (NOT, compute_mode,
7557 : : simplify_gen_binary (ASHIFT,
7558 : : compute_mode,
7559 : : mask, pos),
7560 : : compute_mode),
7561 : : inner);
7562 : 11195 : masked = simplify_gen_binary (ASHIFT, compute_mode,
7563 : : simplify_gen_binary (
7564 : : AND, compute_mode, lowpart, mask),
7565 : : pos);
7566 : :
7567 : 11195 : x = gen_rtx_SET (copy_rtx (inner),
7568 : : simplify_gen_binary (IOR, compute_mode,
7569 : : cleared, masked));
7570 : : }
7571 : :
7572 : 82778841 : return x;
7573 : : }
7574 : :
7575 : : /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7576 : : it is an RTX that represents the (variable) starting position; otherwise,
7577 : : POS is the (constant) starting bit position. Both are counted from the LSB.
7578 : :
7579 : : UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7580 : :
7581 : : IN_DEST is true if this is a reference in the destination of a SET.
7582 : : This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7583 : : a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7584 : : be used.
7585 : :
7586 : : IN_COMPARE is true if we are in a COMPARE. This means that a
7587 : : ZERO_EXTRACT should be built even for bits starting at bit 0.
7588 : :
7589 : : MODE is the desired mode of the result (if IN_DEST == 0).
7590 : :
7591 : : The result is an RTX for the extraction or NULL_RTX if the target
7592 : : can't handle it. */
7593 : :
7594 : : static rtx
7595 : 5117684 : make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7596 : : rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7597 : : bool in_dest, bool in_compare)
7598 : : {
7599 : : /* This mode describes the size of the storage area
7600 : : to fetch the overall value from. Within that, we
7601 : : ignore the POS lowest bits, etc. */
7602 : 5117684 : machine_mode is_mode = GET_MODE (inner);
7603 : 5117684 : machine_mode inner_mode;
7604 : 5117684 : scalar_int_mode wanted_inner_mode;
7605 : 5117684 : scalar_int_mode wanted_inner_reg_mode = word_mode;
7606 : 5117684 : scalar_int_mode pos_mode = word_mode;
7607 : 5117684 : machine_mode extraction_mode = word_mode;
7608 : 5117684 : rtx new_rtx = 0;
7609 : 5117684 : rtx orig_pos_rtx = pos_rtx;
7610 : 5117684 : HOST_WIDE_INT orig_pos;
7611 : :
7612 : 5117684 : if (pos_rtx && CONST_INT_P (pos_rtx))
7613 : 934202 : pos = INTVAL (pos_rtx), pos_rtx = 0;
7614 : :
7615 : 5117684 : if (GET_CODE (inner) == SUBREG
7616 : 2662406 : && subreg_lowpart_p (inner)
7617 : 7776479 : && (paradoxical_subreg_p (inner)
7618 : : /* If trying or potentionally trying to extract
7619 : : bits outside of is_mode, don't look through
7620 : : non-paradoxical SUBREGs. See PR82192. */
7621 : 145282 : || (pos_rtx == NULL_RTX
7622 : 145227 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7623 : : {
7624 : : /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7625 : : consider just the QI as the memory to extract from.
7626 : : The subreg adds or removes high bits; its mode is
7627 : : irrelevant to the meaning of this extraction,
7628 : : since POS and LEN count from the lsb. */
7629 : 2658740 : if (MEM_P (SUBREG_REG (inner)))
7630 : 536652 : is_mode = GET_MODE (SUBREG_REG (inner));
7631 : : inner = SUBREG_REG (inner);
7632 : : }
7633 : 2458944 : else if (GET_CODE (inner) == ASHIFT
7634 : 130200 : && CONST_INT_P (XEXP (inner, 1))
7635 : 128952 : && pos_rtx == 0 && pos == 0
7636 : 128920 : && len > UINTVAL (XEXP (inner, 1)))
7637 : : {
7638 : : /* We're extracting the least significant bits of an rtx
7639 : : (ashift X (const_int C)), where LEN > C. Extract the
7640 : : least significant (LEN - C) bits of X, giving an rtx
7641 : : whose mode is MODE, then shift it left C times. */
7642 : 128920 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7643 : : 0, 0, len - INTVAL (XEXP (inner, 1)),
7644 : : unsignedp, in_dest, in_compare);
7645 : 128920 : if (new_rtx != 0)
7646 : 127274 : return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7647 : : }
7648 : 2330024 : else if (GET_CODE (inner) == MULT
7649 : 180100 : && CONST_INT_P (XEXP (inner, 1))
7650 : 145521 : && pos_rtx == 0 && pos == 0)
7651 : : {
7652 : : /* We're extracting the least significant bits of an rtx
7653 : : (mult X (const_int 2^C)), where LEN > C. Extract the
7654 : : least significant (LEN - C) bits of X, giving an rtx
7655 : : whose mode is MODE, then multiply it by 2^C. */
7656 : 93510 : const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7657 : 93510 : if (len > 1 && IN_RANGE (shift_amt, 1, len - 1))
7658 : : {
7659 : 89819 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7660 : : 0, 0, len - shift_amt,
7661 : : unsignedp, in_dest, in_compare);
7662 : 89819 : if (new_rtx)
7663 : 89819 : return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7664 : : }
7665 : : }
7666 : 2236514 : else if (GET_CODE (inner) == TRUNCATE
7667 : : /* If trying or potentionally trying to extract
7668 : : bits outside of is_mode, don't look through
7669 : : TRUNCATE. See PR82192. */
7670 : 0 : && pos_rtx == NULL_RTX
7671 : 2236514 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7672 : 0 : inner = XEXP (inner, 0);
7673 : :
7674 : 4900591 : inner_mode = GET_MODE (inner);
7675 : :
7676 : : /* See if this can be done without an extraction. We never can if the
7677 : : width of the field is not the same as that of some integer mode. For
7678 : : registers, we can only avoid the extraction if the position is at the
7679 : : low-order bit and this is either not in the destination or we have the
7680 : : appropriate STRICT_LOW_PART operation available.
7681 : :
7682 : : For MEM, we can avoid an extract if the field starts on an appropriate
7683 : : boundary and we can change the mode of the memory reference. */
7684 : :
7685 : 4900591 : scalar_int_mode tmode;
7686 : 4900591 : if (int_mode_for_size (len, 1).exists (&tmode)
7687 : 2459271 : && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7688 : 2164167 : && !MEM_P (inner)
7689 : 1788218 : && (pos == 0 || REG_P (inner))
7690 : 1788218 : && (inner_mode == tmode
7691 : 220120 : || !REG_P (inner)
7692 : 196206 : || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7693 : 0 : || reg_truncated_to_mode (tmode, inner))
7694 : 1788218 : && (! in_dest
7695 : 33 : || (REG_P (inner)
7696 : 33 : && have_insn_for (STRICT_LOW_PART, tmode))))
7697 : 554899 : || (MEM_P (inner) && pos_rtx == 0
7698 : 376978 : && (pos
7699 : : % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7700 : : : BITS_PER_UNIT)) == 0
7701 : : /* We can't do this if we are widening INNER_MODE (it
7702 : : may not be aligned, for one thing). */
7703 : 376314 : && !paradoxical_subreg_p (tmode, inner_mode)
7704 : 376314 : && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7705 : 376314 : && (inner_mode == tmode
7706 : 1222 : || (! mode_dependent_address_p (XEXP (inner, 0),
7707 : 1222 : MEM_ADDR_SPACE (inner))
7708 : 1222 : && ! MEM_VOLATILE_P (inner))))))
7709 : : {
7710 : : /* If INNER is a MEM, make a new MEM that encompasses just the desired
7711 : : field. If the original and current mode are the same, we need not
7712 : : adjust the offset. Otherwise, we do if bytes big endian.
7713 : :
7714 : : If INNER is not a MEM, get a piece consisting of just the field
7715 : : of interest (in this case POS % BITS_PER_WORD must be 0). */
7716 : :
7717 : 2164499 : if (MEM_P (inner))
7718 : : {
7719 : 376301 : poly_int64 offset;
7720 : :
7721 : : /* POS counts from lsb, but make OFFSET count in memory order. */
7722 : 376301 : if (BYTES_BIG_ENDIAN)
7723 : : offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7724 : : - len - pos);
7725 : : else
7726 : 376301 : offset = pos / BITS_PER_UNIT;
7727 : :
7728 : 376301 : new_rtx = adjust_address_nv (inner, tmode, offset);
7729 : : }
7730 : 1788198 : else if (REG_P (inner))
7731 : : {
7732 : 1129063 : if (tmode != inner_mode)
7733 : : {
7734 : : /* We can't call gen_lowpart in a DEST since we
7735 : : always want a SUBREG (see below) and it would sometimes
7736 : : return a new hard register. */
7737 : 196186 : if (pos || in_dest)
7738 : : {
7739 : 16 : poly_uint64 offset
7740 : 16 : = subreg_offset_from_lsb (tmode, inner_mode, pos);
7741 : :
7742 : : /* Avoid creating invalid subregs, for example when
7743 : : simplifying (x>>32)&255. */
7744 : 16 : if (!validate_subreg (tmode, inner_mode, inner, offset))
7745 : 0 : return NULL_RTX;
7746 : :
7747 : 16 : new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7748 : 16 : }
7749 : : else
7750 : 196170 : new_rtx = gen_lowpart (tmode, inner);
7751 : : }
7752 : : else
7753 : : new_rtx = inner;
7754 : : }
7755 : : else
7756 : 1318270 : new_rtx = force_to_mode (inner, tmode,
7757 : : len >= HOST_BITS_PER_WIDE_INT
7758 : : ? HOST_WIDE_INT_M1U
7759 : 659135 : : (HOST_WIDE_INT_1U << len) - 1, false);
7760 : :
7761 : : /* If this extraction is going into the destination of a SET,
7762 : : make a STRICT_LOW_PART unless we made a MEM. */
7763 : :
7764 : 2164499 : if (in_dest)
7765 : 49 : return (MEM_P (new_rtx) ? new_rtx
7766 : : : (GET_CODE (new_rtx) != SUBREG
7767 : 13 : ? gen_rtx_CLOBBER (tmode, const0_rtx)
7768 : 13 : : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7769 : :
7770 : 2164450 : if (mode == tmode)
7771 : : return new_rtx;
7772 : :
7773 : 2164415 : if (CONST_SCALAR_INT_P (new_rtx))
7774 : 5 : return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7775 : 5 : mode, new_rtx, tmode);
7776 : :
7777 : : /* If we know that no extraneous bits are set, and that the high
7778 : : bit is not set, convert the extraction to the cheaper of
7779 : : sign and zero extension, that are equivalent in these cases. */
7780 : 2164410 : if (flag_expensive_optimizations
7781 : 2164410 : && (HWI_COMPUTABLE_MODE_P (tmode)
7782 : 2022342 : && ((nonzero_bits (new_rtx, tmode)
7783 : 2022342 : & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7784 : : == 0)))
7785 : : {
7786 : 10865 : rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7787 : 10865 : rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7788 : :
7789 : : /* Prefer ZERO_EXTENSION, since it gives more information to
7790 : : backends. */
7791 : 10865 : if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7792 : 10865 : <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7793 : : return temp;
7794 : 0 : return temp1;
7795 : : }
7796 : :
7797 : : /* Otherwise, sign- or zero-extend unless we already are in the
7798 : : proper mode. */
7799 : :
7800 : 2153545 : return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7801 : 2153545 : mode, new_rtx));
7802 : : }
7803 : :
7804 : : /* Unless this is a COMPARE or we have a funny memory reference,
7805 : : don't do anything with zero-extending field extracts starting at
7806 : : the low-order bit since they are simple AND operations. */
7807 : 2736092 : if (pos_rtx == 0 && pos == 0 && ! in_dest
7808 : 1671475 : && ! in_compare && unsignedp)
7809 : : return 0;
7810 : :
7811 : : /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7812 : : if the position is not a constant and the length is not 1. In all
7813 : : other cases, we would only be going outside our object in cases when
7814 : : an original shift would have been undefined. */
7815 : 1473738 : if (MEM_P (inner)
7816 : 1473738 : && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7817 : 1440 : || (pos_rtx != 0 && len != 1)))
7818 : : return 0;
7819 : :
7820 : 1579913 : enum extraction_pattern pattern = (in_dest ? EP_insv
7821 : 1466462 : : unsignedp ? EP_extzv : EP_extv);
7822 : :
7823 : : /* If INNER is not from memory, we want it to have the mode of a register
7824 : : extraction pattern's structure operand, or word_mode if there is no
7825 : : such pattern. The same applies to extraction_mode and pos_mode
7826 : : and their respective operands.
7827 : :
7828 : : For memory, assume that the desired extraction_mode and pos_mode
7829 : : are the same as for a register operation, since at present we don't
7830 : : have named patterns for aligned memory structures. */
7831 : 1473700 : class extraction_insn insn;
7832 : 1473700 : unsigned int inner_size;
7833 : 2947400 : if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7834 : 1473700 : && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7835 : : {
7836 : 1369001 : wanted_inner_reg_mode = insn.struct_mode.require ();
7837 : 1369001 : pos_mode = insn.pos_mode;
7838 : 1369001 : extraction_mode = insn.field_mode;
7839 : : }
7840 : :
7841 : : /* Never narrow an object, since that might not be safe. */
7842 : :
7843 : 1473700 : if (mode != VOIDmode
7844 : 1473700 : && partial_subreg_p (extraction_mode, mode))
7845 : : extraction_mode = mode;
7846 : :
7847 : : /* Punt if len is too large for extraction_mode. */
7848 : 1473700 : if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7849 : : return NULL_RTX;
7850 : :
7851 : 1473688 : if (!MEM_P (inner))
7852 : 1282566 : wanted_inner_mode = wanted_inner_reg_mode;
7853 : : else
7854 : : {
7855 : : /* Be careful not to go beyond the extracted object and maintain the
7856 : : natural alignment of the memory. */
7857 : 191122 : wanted_inner_mode = smallest_int_mode_for_size (len).require ();
7858 : 385094 : while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7859 : 387944 : > GET_MODE_BITSIZE (wanted_inner_mode))
7860 : 2850 : wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7861 : : }
7862 : :
7863 : 1473688 : orig_pos = pos;
7864 : :
7865 : 1473688 : if (BITS_BIG_ENDIAN)
7866 : : {
7867 : : /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7868 : : BITS_BIG_ENDIAN style. If position is constant, compute new
7869 : : position. Otherwise, build subtraction.
7870 : : Note that POS is relative to the mode of the original argument.
7871 : : If it's a MEM we need to recompute POS relative to that.
7872 : : However, if we're extracting from (or inserting into) a register,
7873 : : we want to recompute POS relative to wanted_inner_mode. */
7874 : : int width;
7875 : : if (!MEM_P (inner))
7876 : : width = GET_MODE_BITSIZE (wanted_inner_mode);
7877 : : else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7878 : : return NULL_RTX;
7879 : :
7880 : : if (pos_rtx == 0)
7881 : : pos = width - len - pos;
7882 : : else
7883 : : pos_rtx
7884 : : = gen_rtx_MINUS (GET_MODE (pos_rtx),
7885 : : gen_int_mode (width - len, GET_MODE (pos_rtx)),
7886 : : pos_rtx);
7887 : : /* POS may be less than 0 now, but we check for that below.
7888 : : Note that it can only be less than 0 if !MEM_P (inner). */
7889 : : }
7890 : :
7891 : : /* If INNER has a wider mode, and this is a constant extraction, try to
7892 : : make it smaller and adjust the byte to point to the byte containing
7893 : : the value. */
7894 : 1473688 : if (wanted_inner_mode != VOIDmode
7895 : 1473688 : && inner_mode != wanted_inner_mode
7896 : 219868 : && ! pos_rtx
7897 : 206256 : && partial_subreg_p (wanted_inner_mode, is_mode)
7898 : 112682 : && MEM_P (inner)
7899 : 29671 : && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7900 : 1503359 : && ! MEM_VOLATILE_P (inner))
7901 : : {
7902 : 28091 : poly_int64 offset = 0;
7903 : :
7904 : : /* The computations below will be correct if the machine is big
7905 : : endian in both bits and bytes or little endian in bits and bytes.
7906 : : If it is mixed, we must adjust. */
7907 : :
7908 : : /* If bytes are big endian and we had a paradoxical SUBREG, we must
7909 : : adjust OFFSET to compensate. */
7910 : 28091 : if (BYTES_BIG_ENDIAN
7911 : : && paradoxical_subreg_p (is_mode, inner_mode))
7912 : : offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7913 : :
7914 : : /* We can now move to the desired byte. */
7915 : 56182 : offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7916 : 28091 : * GET_MODE_SIZE (wanted_inner_mode);
7917 : 28091 : pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7918 : :
7919 : 28091 : if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7920 : : && is_mode != wanted_inner_mode)
7921 : : offset = (GET_MODE_SIZE (is_mode)
7922 : : - GET_MODE_SIZE (wanted_inner_mode) - offset);
7923 : :
7924 : 28091 : inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7925 : : }
7926 : :
7927 : : /* If INNER is not memory, get it into the proper mode. If we are changing
7928 : : its mode, POS must be a constant and smaller than the size of the new
7929 : : mode. */
7930 : 1445597 : else if (!MEM_P (inner))
7931 : : {
7932 : : /* On the LHS, don't create paradoxical subregs implicitely truncating
7933 : : the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7934 : 1282566 : if (in_dest
7935 : 1282566 : && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7936 : : wanted_inner_mode))
7937 : 0 : return NULL_RTX;
7938 : :
7939 : 1282566 : if (GET_MODE (inner) != wanted_inner_mode
7940 : 1282566 : && (pos_rtx != 0
7941 : 353170 : || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7942 : : return NULL_RTX;
7943 : :
7944 : 1209097 : if (orig_pos < 0)
7945 : : return NULL_RTX;
7946 : :
7947 : 2396521 : inner = force_to_mode (inner, wanted_inner_mode,
7948 : : pos_rtx
7949 : 1187424 : || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7950 : : ? HOST_WIDE_INT_M1U
7951 : 949187 : : (((HOST_WIDE_INT_1U << len) - 1)
7952 : 949187 : << orig_pos), false);
7953 : : }
7954 : :
7955 : : /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7956 : : have to zero extend. Otherwise, we can just use a SUBREG.
7957 : :
7958 : : We dealt with constant rtxes earlier, so pos_rtx cannot
7959 : : have VOIDmode at this point. */
7960 : 1400219 : if (pos_rtx != 0
7961 : 1400219 : && (GET_MODE_SIZE (pos_mode)
7962 : 1423294 : > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7963 : : {
7964 : 62 : rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7965 : : GET_MODE (pos_rtx));
7966 : :
7967 : : /* If we know that no extraneous bits are set, and that the high
7968 : : bit is not set, convert extraction to cheaper one - either
7969 : : SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7970 : : cases. */
7971 : 62 : if (flag_expensive_optimizations
7972 : 62 : && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7973 : 62 : && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7974 : 62 : & ~(((unsigned HOST_WIDE_INT)
7975 : 62 : GET_MODE_MASK (GET_MODE (pos_rtx)))
7976 : 62 : >> 1))
7977 : : == 0)))
7978 : : {
7979 : 46 : rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7980 : : GET_MODE (pos_rtx));
7981 : :
7982 : : /* Prefer ZERO_EXTENSION, since it gives more information to
7983 : : backends. */
7984 : 46 : if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7985 : 46 : < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7986 : 1400219 : temp = temp1;
7987 : : }
7988 : : pos_rtx = temp;
7989 : : }
7990 : :
7991 : : /* Make POS_RTX unless we already have it and it is correct. If we don't
7992 : : have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7993 : : be a CONST_INT. */
7994 : 1400219 : if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7995 : : pos_rtx = orig_pos_rtx;
7996 : :
7997 : 491159 : else if (pos_rtx == 0)
7998 : 468084 : pos_rtx = GEN_INT (pos);
7999 : :
8000 : : /* Make the required operation. See if we can use existing rtx. */
8001 : 1400219 : new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
8002 : : extraction_mode, inner, GEN_INT (len), pos_rtx);
8003 : 1400219 : if (! in_dest)
8004 : 1393023 : new_rtx = gen_lowpart (mode, new_rtx);
8005 : :
8006 : : return new_rtx;
8007 : : }
8008 : :
8009 : : /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8010 : : can be commuted with any other operations in X. Return X without
8011 : : that shift if so. */
8012 : :
8013 : : static rtx
8014 : 1771041 : extract_left_shift (scalar_int_mode mode, rtx x, int count)
8015 : : {
8016 : 1771041 : enum rtx_code code = GET_CODE (x);
8017 : 1771041 : rtx tem;
8018 : :
8019 : 1771041 : switch (code)
8020 : : {
8021 : 234678 : case ASHIFT:
8022 : : /* This is the shift itself. If it is wide enough, we will return
8023 : : either the value being shifted if the shift count is equal to
8024 : : COUNT or a shift for the difference. */
8025 : 234678 : if (CONST_INT_P (XEXP (x, 1))
8026 : 229530 : && INTVAL (XEXP (x, 1)) >= count)
8027 : 227765 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8028 : 227765 : INTVAL (XEXP (x, 1)) - count);
8029 : : break;
8030 : :
8031 : 5068 : case NEG: case NOT:
8032 : 5068 : if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8033 : 2497 : return simplify_gen_unary (code, mode, tem, mode);
8034 : :
8035 : : break;
8036 : :
8037 : 578536 : case PLUS: case IOR: case XOR: case AND:
8038 : : /* If we can safely shift this constant and we find the inner shift,
8039 : : make a new operation. */
8040 : 578536 : if (CONST_INT_P (XEXP (x, 1))
8041 : 282661 : && (UINTVAL (XEXP (x, 1))
8042 : 282661 : & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8043 : 701765 : && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8044 : : {
8045 : 6767 : HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8046 : 6767 : return simplify_gen_binary (code, mode, tem,
8047 : 6767 : gen_int_mode (val, mode));
8048 : : }
8049 : : break;
8050 : :
8051 : : default:
8052 : : break;
8053 : : }
8054 : :
8055 : : return 0;
8056 : : }
8057 : :
8058 : : /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8059 : : level of the expression and MODE is its mode. IN_CODE is as for
8060 : : make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8061 : : that should be used when recursing on operands of *X_PTR.
8062 : :
8063 : : There are two possible actions:
8064 : :
8065 : : - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8066 : : equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8067 : :
8068 : : - Return a new rtx, which the caller returns directly. */
8069 : :
8070 : : static rtx
8071 : 266089813 : make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8072 : : enum rtx_code in_code,
8073 : : enum rtx_code *next_code_ptr)
8074 : : {
8075 : 266089813 : rtx x = *x_ptr;
8076 : 266089813 : enum rtx_code next_code = *next_code_ptr;
8077 : 266089813 : enum rtx_code code = GET_CODE (x);
8078 : 266089813 : int mode_width = GET_MODE_PRECISION (mode);
8079 : 266089813 : rtx rhs, lhs;
8080 : 266089813 : rtx new_rtx = 0;
8081 : 266089813 : int i;
8082 : 266089813 : rtx tem;
8083 : 266089813 : scalar_int_mode inner_mode;
8084 : 266089813 : bool equality_comparison = false;
8085 : :
8086 : 266089813 : if (in_code == EQ)
8087 : : {
8088 : 8438846 : equality_comparison = true;
8089 : 8438846 : in_code = COMPARE;
8090 : : }
8091 : :
8092 : : /* Process depending on the code of this operation. If NEW is set
8093 : : nonzero, it will be returned. */
8094 : :
8095 : 266089813 : switch (code)
8096 : : {
8097 : 6520186 : case ASHIFT:
8098 : : /* Convert shifts by constants into multiplications if inside
8099 : : an address. */
8100 : 6520186 : if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8101 : 1950106 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8102 : 1950106 : && INTVAL (XEXP (x, 1)) >= 0)
8103 : : {
8104 : 1950106 : HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8105 : 1950106 : HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8106 : :
8107 : 1950106 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8108 : 1950106 : if (GET_CODE (new_rtx) == NEG)
8109 : : {
8110 : 9 : new_rtx = XEXP (new_rtx, 0);
8111 : 9 : multval = -multval;
8112 : : }
8113 : 1950106 : multval = trunc_int_for_mode (multval, mode);
8114 : 1950106 : new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8115 : : }
8116 : : break;
8117 : :
8118 : 47993676 : case PLUS:
8119 : 47993676 : lhs = XEXP (x, 0);
8120 : 47993676 : rhs = XEXP (x, 1);
8121 : 47993676 : lhs = make_compound_operation (lhs, next_code);
8122 : 47993676 : rhs = make_compound_operation (rhs, next_code);
8123 : 47993676 : if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG)
8124 : : {
8125 : 0 : tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
8126 : : XEXP (lhs, 1));
8127 : 0 : new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8128 : : }
8129 : 47993676 : else if (GET_CODE (lhs) == MULT
8130 : 4587045 : && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
8131 : : {
8132 : 46501 : tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
8133 : : simplify_gen_unary (NEG, mode,
8134 : : XEXP (lhs, 1),
8135 : : mode));
8136 : 46501 : new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8137 : : }
8138 : : else
8139 : : {
8140 : 47947175 : SUBST (XEXP (x, 0), lhs);
8141 : 47947175 : SUBST (XEXP (x, 1), rhs);
8142 : : }
8143 : 47993676 : maybe_swap_commutative_operands (x);
8144 : 47993676 : return x;
8145 : :
8146 : 4219239 : case MINUS:
8147 : 4219239 : lhs = XEXP (x, 0);
8148 : 4219239 : rhs = XEXP (x, 1);
8149 : 4219239 : lhs = make_compound_operation (lhs, next_code);
8150 : 4219239 : rhs = make_compound_operation (rhs, next_code);
8151 : 4219239 : if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG)
8152 : : {
8153 : 0 : tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
8154 : : XEXP (rhs, 1));
8155 : 0 : return simplify_gen_binary (PLUS, mode, tem, lhs);
8156 : : }
8157 : 4219239 : else if (GET_CODE (rhs) == MULT
8158 : 148797 : && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
8159 : : {
8160 : 255 : tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
8161 : : simplify_gen_unary (NEG, mode,
8162 : : XEXP (rhs, 1),
8163 : : mode));
8164 : 255 : return simplify_gen_binary (PLUS, mode, tem, lhs);
8165 : : }
8166 : : else
8167 : : {
8168 : 4218984 : SUBST (XEXP (x, 0), lhs);
8169 : 4218984 : SUBST (XEXP (x, 1), rhs);
8170 : 4218984 : return x;
8171 : : }
8172 : :
8173 : 7539857 : case AND:
8174 : : /* If the second operand is not a constant, we can't do anything
8175 : : with it. */
8176 : 7539857 : if (!CONST_INT_P (XEXP (x, 1)))
8177 : : break;
8178 : :
8179 : : /* If the constant is a power of two minus one and the first operand
8180 : : is a logical right shift, make an extraction. */
8181 : 6138989 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8182 : 6138989 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8183 : : {
8184 : 571299 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8185 : 571299 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8186 : : i, true, false, in_code == COMPARE);
8187 : : }
8188 : :
8189 : : /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8190 : 5567690 : else if (GET_CODE (XEXP (x, 0)) == SUBREG
8191 : 1506453 : && subreg_lowpart_p (XEXP (x, 0))
8192 : 7032239 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8193 : : &inner_mode)
8194 : 1503210 : && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8195 : 5607705 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8196 : : {
8197 : 38661 : rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8198 : 38661 : new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8199 : 38661 : new_rtx = make_extraction (inner_mode, new_rtx, 0,
8200 : : XEXP (inner_x0, 1),
8201 : : i, true, false, in_code == COMPARE);
8202 : :
8203 : : /* If we narrowed the mode when dropping the subreg, then we lose. */
8204 : 115983 : if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8205 : 38661 : new_rtx = NULL;
8206 : :
8207 : : /* If that didn't give anything, see if the AND simplifies on
8208 : : its own. */
8209 : 38661 : if (!new_rtx && i >= 0)
8210 : : {
8211 : 3502 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8212 : 3502 : new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i,
8213 : : true, false, in_code == COMPARE);
8214 : : }
8215 : : }
8216 : : /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8217 : 5529029 : else if ((GET_CODE (XEXP (x, 0)) == XOR
8218 : 5529029 : || GET_CODE (XEXP (x, 0)) == IOR)
8219 : 22754 : && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8220 : 1872 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8221 : 5529039 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8222 : : {
8223 : : /* Apply the distributive law, and then try to make extractions. */
8224 : 10 : new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8225 : : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8226 : : XEXP (x, 1)),
8227 : : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8228 : : XEXP (x, 1)));
8229 : 10 : new_rtx = make_compound_operation (new_rtx, in_code);
8230 : : }
8231 : :
8232 : : /* If we are have (and (rotate X C) M) and C is larger than the number
8233 : : of bits in M, this is an extraction. */
8234 : :
8235 : 5529019 : else if (GET_CODE (XEXP (x, 0)) == ROTATE
8236 : 1582 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8237 : 1582 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8238 : 5529053 : && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8239 : : {
8240 : 2 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8241 : 2 : new_rtx = make_extraction (mode, new_rtx,
8242 : 2 : (GET_MODE_PRECISION (mode)
8243 : 2 : - INTVAL (XEXP (XEXP (x, 0), 1))),
8244 : : NULL_RTX, i, true, false,
8245 : : in_code == COMPARE);
8246 : : }
8247 : :
8248 : : /* On machines without logical shifts, if the operand of the AND is
8249 : : a logical shift and our mask turns off all the propagated sign
8250 : : bits, we can replace the logical shift with an arithmetic shift. */
8251 : 5529017 : else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8252 : 88115 : && !have_insn_for (LSHIFTRT, mode)
8253 : 0 : && have_insn_for (ASHIFTRT, mode)
8254 : 0 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8255 : 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8256 : 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8257 : 5529017 : && mode_width <= HOST_BITS_PER_WIDE_INT)
8258 : : {
8259 : 0 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8260 : :
8261 : 0 : mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8262 : 0 : if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8263 : 0 : SUBST (XEXP (x, 0),
8264 : : gen_rtx_ASHIFTRT (mode,
8265 : : make_compound_operation (XEXP (XEXP (x,
8266 : : 0),
8267 : : 0),
8268 : : next_code),
8269 : : XEXP (XEXP (x, 0), 1)));
8270 : : }
8271 : :
8272 : : /* If the constant is one less than a power of two, this might be
8273 : : representable by an extraction even if no shift is present.
8274 : : If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8275 : : we are in a COMPARE. */
8276 : 5529017 : else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8277 : 2688714 : new_rtx = make_extraction (mode,
8278 : : make_compound_operation (XEXP (x, 0),
8279 : : next_code),
8280 : : 0, NULL_RTX, i,
8281 : : true, false, in_code == COMPARE);
8282 : :
8283 : : /* If we are in a comparison and this is an AND with a power of two,
8284 : : convert this into the appropriate bit extract. */
8285 : 2840303 : else if (in_code == COMPARE
8286 : 495712 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8287 : 2919256 : && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8288 : 78953 : new_rtx = make_extraction (mode,
8289 : : make_compound_operation (XEXP (x, 0),
8290 : : next_code),
8291 : : i, NULL_RTX, 1, true, false, true);
8292 : :
8293 : : /* If the one operand is a paradoxical subreg of a register or memory and
8294 : : the constant (limited to the smaller mode) has only zero bits where
8295 : : the sub expression has known zero bits, this can be expressed as
8296 : : a zero_extend. */
8297 : 2761350 : else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8298 : : {
8299 : 73987 : rtx sub;
8300 : :
8301 : 73987 : sub = XEXP (XEXP (x, 0), 0);
8302 : 73987 : machine_mode sub_mode = GET_MODE (sub);
8303 : 73987 : int sub_width;
8304 : 30305 : if ((REG_P (sub) || MEM_P (sub))
8305 : 44086 : && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8306 : 44086 : && sub_width < mode_width
8307 : 73987 : && (!WORD_REGISTER_OPERATIONS
8308 : : || sub_width >= BITS_PER_WORD
8309 : : /* On WORD_REGISTER_OPERATIONS targets the bits
8310 : : beyond sub_mode aren't considered undefined,
8311 : : so optimize only if it is a MEM load when MEM loads
8312 : : zero extend, because then the upper bits are all zero. */
8313 : : || (MEM_P (sub)
8314 : : && load_extend_op (sub_mode) == ZERO_EXTEND)))
8315 : : {
8316 : 32249 : unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8317 : 32249 : unsigned HOST_WIDE_INT mask;
8318 : :
8319 : : /* Original AND constant with all the known zero bits set. */
8320 : 32249 : mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8321 : 32249 : if ((mask & mode_mask) == mode_mask)
8322 : : {
8323 : 27665 : new_rtx = make_compound_operation (sub, next_code);
8324 : 27665 : new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8325 : : true, false, in_code == COMPARE);
8326 : : }
8327 : : }
8328 : : }
8329 : :
8330 : : break;
8331 : :
8332 : 2107083 : case LSHIFTRT:
8333 : : /* If the sign bit is known to be zero, replace this with an
8334 : : arithmetic shift. */
8335 : 2107083 : if (have_insn_for (ASHIFTRT, mode)
8336 : 2107083 : && ! have_insn_for (LSHIFTRT, mode)
8337 : 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
8338 : 2107083 : && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8339 : : {
8340 : 0 : new_rtx = gen_rtx_ASHIFTRT (mode,
8341 : : make_compound_operation (XEXP (x, 0),
8342 : : next_code),
8343 : : XEXP (x, 1));
8344 : 0 : break;
8345 : : }
8346 : :
8347 : : /* fall through */
8348 : :
8349 : 4629720 : case ASHIFTRT:
8350 : 4629720 : lhs = XEXP (x, 0);
8351 : 4629720 : rhs = XEXP (x, 1);
8352 : :
8353 : : /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8354 : : this is a SIGN_EXTRACT. */
8355 : 4629720 : if (CONST_INT_P (rhs)
8356 : 4475660 : && GET_CODE (lhs) == ASHIFT
8357 : 1119704 : && CONST_INT_P (XEXP (lhs, 1))
8358 : 1114556 : && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8359 : 895792 : && INTVAL (XEXP (lhs, 1)) >= 0
8360 : 895788 : && INTVAL (rhs) < mode_width)
8361 : : {
8362 : 895788 : new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8363 : 895788 : new_rtx = make_extraction (mode, new_rtx,
8364 : 895788 : INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8365 : 895788 : NULL_RTX, mode_width - INTVAL (rhs),
8366 : : code == LSHIFTRT, false,
8367 : : in_code == COMPARE);
8368 : 895788 : break;
8369 : : }
8370 : :
8371 : : /* See if we have operations between an ASHIFTRT and an ASHIFT.
8372 : : If so, try to merge the shifts into a SIGN_EXTEND. We could
8373 : : also do this for some cases of SIGN_EXTRACT, but it doesn't
8374 : : seem worth the effort; the case checked for occurs on Alpha. */
8375 : :
8376 : 3733932 : if (!OBJECT_P (lhs)
8377 : 1730487 : && ! (GET_CODE (lhs) == SUBREG
8378 : 78584 : && (OBJECT_P (SUBREG_REG (lhs))))
8379 : 1666464 : && CONST_INT_P (rhs)
8380 : 1647402 : && INTVAL (rhs) >= 0
8381 : 1647402 : && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8382 : 1642744 : && INTVAL (rhs) < mode_width
8383 : 5376676 : && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8384 : 227765 : new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8385 : : next_code),
8386 : 227765 : 0, NULL_RTX, mode_width - INTVAL (rhs),
8387 : : code == LSHIFTRT, false, in_code == COMPARE);
8388 : :
8389 : : break;
8390 : :
8391 : 9212959 : case SUBREG:
8392 : : /* Call ourselves recursively on the inner expression. If we are
8393 : : narrowing the object and it has a different RTL code from
8394 : : what it originally did, do this SUBREG as a force_to_mode. */
8395 : 9212959 : {
8396 : 9212959 : rtx inner = SUBREG_REG (x), simplified;
8397 : 9212959 : enum rtx_code subreg_code = in_code;
8398 : :
8399 : : /* If the SUBREG is masking of a logical right shift,
8400 : : make an extraction. */
8401 : 9212959 : if (GET_CODE (inner) == LSHIFTRT
8402 : 9228981 : && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8403 : 750662 : && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8404 : 364878 : && CONST_INT_P (XEXP (inner, 1))
8405 : 360402 : && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8406 : 9573361 : && subreg_lowpart_p (x))
8407 : : {
8408 : 359309 : new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8409 : 359309 : int width = GET_MODE_PRECISION (inner_mode)
8410 : 359309 : - INTVAL (XEXP (inner, 1));
8411 : 359309 : if (width > mode_width)
8412 : : width = mode_width;
8413 : 359309 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8414 : : width, true, false, in_code == COMPARE);
8415 : 359309 : break;
8416 : : }
8417 : :
8418 : : /* If in_code is COMPARE, it isn't always safe to pass it through
8419 : : to the recursive make_compound_operation call. */
8420 : 8853650 : if (subreg_code == COMPARE
8421 : 8853650 : && (!subreg_lowpart_p (x)
8422 : 135655 : || GET_CODE (inner) == SUBREG
8423 : : /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8424 : : is (const_int 0), rather than
8425 : : (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8426 : : Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8427 : : for non-equality comparisons against 0 is not equivalent
8428 : : to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8429 : 135655 : || (GET_CODE (inner) == AND
8430 : 1131 : && CONST_INT_P (XEXP (inner, 1))
8431 : 257 : && partial_subreg_p (x)
8432 : 514 : && exact_log2 (UINTVAL (XEXP (inner, 1)))
8433 : 257 : >= GET_MODE_BITSIZE (mode) - 1)))
8434 : : subreg_code = SET;
8435 : :
8436 : 8853650 : tem = make_compound_operation (inner, subreg_code);
8437 : :
8438 : 8853650 : simplified
8439 : 8853650 : = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8440 : 8853650 : if (simplified)
8441 : 20058 : tem = simplified;
8442 : :
8443 : 8853650 : if (GET_CODE (tem) != GET_CODE (inner)
8444 : 27299 : && partial_subreg_p (x)
8445 : 8879082 : && subreg_lowpart_p (x))
8446 : : {
8447 : 25410 : rtx newer
8448 : 25410 : = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8449 : :
8450 : : /* If we have something other than a SUBREG, we might have
8451 : : done an expansion, so rerun ourselves. */
8452 : 25410 : if (GET_CODE (newer) != SUBREG)
8453 : 18588 : newer = make_compound_operation (newer, in_code);
8454 : :
8455 : : /* force_to_mode can expand compounds. If it just re-expanded
8456 : : the compound, use gen_lowpart to convert to the desired
8457 : : mode. */
8458 : 25410 : if (rtx_equal_p (newer, x)
8459 : : /* Likewise if it re-expanded the compound only partially.
8460 : : This happens for SUBREG of ZERO_EXTRACT if they extract
8461 : : the same number of bits. */
8462 : 25410 : || (GET_CODE (newer) == SUBREG
8463 : 6558 : && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8464 : 6558 : || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8465 : 3729 : && GET_CODE (inner) == AND
8466 : 3607 : && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8467 : 5237 : return gen_lowpart (GET_MODE (x), tem);
8468 : :
8469 : 20173 : return newer;
8470 : : }
8471 : :
8472 : 8828240 : if (simplified)
8473 : : return tem;
8474 : : }
8475 : : break;
8476 : :
8477 : : default:
8478 : : break;
8479 : : }
8480 : :
8481 : 10390761 : if (new_rtx)
8482 : 5507323 : *x_ptr = gen_lowpart (mode, new_rtx);
8483 : 213850731 : *next_code_ptr = next_code;
8484 : 213850731 : return NULL_RTX;
8485 : : }
8486 : :
8487 : : /* Look at the expression rooted at X. Look for expressions
8488 : : equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8489 : : Form these expressions.
8490 : :
8491 : : Return the new rtx, usually just X.
8492 : :
8493 : : Also, for machines like the VAX that don't have logical shift insns,
8494 : : try to convert logical to arithmetic shift operations in cases where
8495 : : they are equivalent. This undoes the canonicalizations to logical
8496 : : shifts done elsewhere.
8497 : :
8498 : : We try, as much as possible, to re-use rtl expressions to save memory.
8499 : :
8500 : : IN_CODE says what kind of expression we are processing. Normally, it is
8501 : : SET. In a memory address it is MEM. When processing the arguments of
8502 : : a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8503 : : precisely it is an equality comparison against zero. */
8504 : :
8505 : : rtx
8506 : 447407480 : make_compound_operation (rtx x, enum rtx_code in_code)
8507 : : {
8508 : 447407480 : enum rtx_code code = GET_CODE (x);
8509 : 447407480 : const char *fmt;
8510 : 447407480 : int i, j;
8511 : 447407480 : enum rtx_code next_code;
8512 : 447407480 : rtx new_rtx, tem;
8513 : :
8514 : : /* Select the code to be used in recursive calls. Once we are inside an
8515 : : address, we stay there. If we have a comparison, set to COMPARE,
8516 : : but once inside, go back to our default of SET. */
8517 : :
8518 : 447407480 : next_code = (code == MEM ? MEM
8519 : 422250988 : : ((code == COMPARE || COMPARISON_P (x))
8520 : 440732444 : && XEXP (x, 1) == const0_rtx) ? COMPARE
8521 : 414934639 : : in_code == COMPARE || in_code == EQ ? SET : in_code);
8522 : :
8523 : 447407480 : scalar_int_mode mode;
8524 : 447407480 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8525 : : {
8526 : 266089813 : rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8527 : : &next_code);
8528 : 266089813 : if (new_rtx)
8529 : : return new_rtx;
8530 : 213850731 : code = GET_CODE (x);
8531 : : }
8532 : :
8533 : : /* Now recursively process each operand of this operation. We need to
8534 : : handle ZERO_EXTEND specially so that we don't lose track of the
8535 : : inner mode. */
8536 : 395168398 : if (code == ZERO_EXTEND)
8537 : : {
8538 : 3524661 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8539 : 7049322 : tem = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8540 : 3524661 : new_rtx, GET_MODE (XEXP (x, 0)));
8541 : 3524661 : if (tem)
8542 : : return tem;
8543 : 3511556 : SUBST (XEXP (x, 0), new_rtx);
8544 : 3511556 : return x;
8545 : : }
8546 : :
8547 : 391643737 : fmt = GET_RTX_FORMAT (code);
8548 : 908958072 : for (i = 0; i < GET_RTX_LENGTH (code); i++)
8549 : 517314335 : if (fmt[i] == 'e')
8550 : : {
8551 : 198571306 : new_rtx = make_compound_operation (XEXP (x, i), next_code);
8552 : 198571306 : SUBST (XEXP (x, i), new_rtx);
8553 : : }
8554 : 318743029 : else if (fmt[i] == 'E')
8555 : 22426410 : for (j = 0; j < XVECLEN (x, i); j++)
8556 : : {
8557 : 16274545 : new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8558 : 16274545 : SUBST (XVECEXP (x, i, j), new_rtx);
8559 : : }
8560 : :
8561 : 391643737 : maybe_swap_commutative_operands (x);
8562 : 391643737 : return x;
8563 : : }
8564 : :
8565 : : /* Given M see if it is a value that would select a field of bits
8566 : : within an item, but not the entire word. Return -1 if not.
8567 : : Otherwise, return the starting position of the field, where 0 is the
8568 : : low-order bit.
8569 : :
8570 : : *PLEN is set to the length of the field. */
8571 : :
8572 : : static int
8573 : 11035 : get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8574 : : {
8575 : : /* Get the bit number of the first 1 bit from the right, -1 if none. */
8576 : 11035 : int pos = m ? ctz_hwi (m) : -1;
8577 : 11035 : int len = 0;
8578 : :
8579 : 11035 : if (pos >= 0)
8580 : : /* Now shift off the low-order zero bits and see if we have a
8581 : : power of two minus 1. */
8582 : 11035 : len = exact_log2 ((m >> pos) + 1);
8583 : :
8584 : 6742 : if (len <= 0)
8585 : : pos = -1;
8586 : :
8587 : 11035 : *plen = len;
8588 : 11035 : return pos;
8589 : : }
8590 : :
8591 : : /* If X refers to a register that equals REG in value, replace these
8592 : : references with REG. */
8593 : : static rtx
8594 : 9622 : canon_reg_for_combine (rtx x, rtx reg)
8595 : : {
8596 : 9622 : rtx op0, op1, op2;
8597 : 9622 : const char *fmt;
8598 : 9622 : int i;
8599 : 9622 : bool copied;
8600 : :
8601 : 9622 : enum rtx_code code = GET_CODE (x);
8602 : 9622 : switch (GET_RTX_CLASS (code))
8603 : : {
8604 : 0 : case RTX_UNARY:
8605 : 0 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8606 : 0 : if (op0 != XEXP (x, 0))
8607 : 0 : return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8608 : 0 : GET_MODE (reg));
8609 : : break;
8610 : :
8611 : 1457 : case RTX_BIN_ARITH:
8612 : 1457 : case RTX_COMM_ARITH:
8613 : 1457 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8614 : 1457 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8615 : 1457 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8616 : 0 : return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8617 : : break;
8618 : :
8619 : 13 : case RTX_COMPARE:
8620 : 13 : case RTX_COMM_COMPARE:
8621 : 13 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8622 : 13 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8623 : 13 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8624 : 0 : return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8625 : 0 : GET_MODE (op0), op0, op1);
8626 : : break;
8627 : :
8628 : 0 : case RTX_TERNARY:
8629 : 0 : case RTX_BITFIELD_OPS:
8630 : 0 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8631 : 0 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8632 : 0 : op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8633 : 0 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8634 : 0 : return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8635 : 0 : GET_MODE (op0), op0, op1, op2);
8636 : : /* FALLTHRU */
8637 : :
8638 : 6089 : case RTX_OBJ:
8639 : 6089 : if (REG_P (x))
8640 : : {
8641 : 6083 : if (rtx_equal_p (get_last_value (reg), x)
8642 : 6083 : || rtx_equal_p (reg, get_last_value (x)))
8643 : 0 : return reg;
8644 : : else
8645 : : break;
8646 : : }
8647 : :
8648 : : /* fall through */
8649 : :
8650 : 2069 : default:
8651 : 2069 : fmt = GET_RTX_FORMAT (code);
8652 : 2069 : copied = false;
8653 : 4201 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8654 : 2132 : if (fmt[i] == 'e')
8655 : : {
8656 : 63 : rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8657 : 63 : if (op != XEXP (x, i))
8658 : : {
8659 : 0 : if (!copied)
8660 : : {
8661 : 0 : copied = true;
8662 : 0 : x = copy_rtx (x);
8663 : : }
8664 : 0 : XEXP (x, i) = op;
8665 : : }
8666 : : }
8667 : 2069 : else if (fmt[i] == 'E')
8668 : : {
8669 : : int j;
8670 : 0 : for (j = 0; j < XVECLEN (x, i); j++)
8671 : : {
8672 : 0 : rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8673 : 0 : if (op != XVECEXP (x, i, j))
8674 : : {
8675 : 0 : if (!copied)
8676 : : {
8677 : 0 : copied = true;
8678 : 0 : x = copy_rtx (x);
8679 : : }
8680 : 0 : XVECEXP (x, i, j) = op;
8681 : : }
8682 : : }
8683 : : }
8684 : :
8685 : : break;
8686 : : }
8687 : :
8688 : : return x;
8689 : : }
8690 : :
8691 : : /* Return X converted to MODE. If the value is already truncated to
8692 : : MODE we can just return a subreg even though in the general case we
8693 : : would need an explicit truncation. */
8694 : :
8695 : : static rtx
8696 : 121675749 : gen_lowpart_or_truncate (machine_mode mode, rtx x)
8697 : : {
8698 : 121675749 : if (!CONST_INT_P (x)
8699 : 115347680 : && partial_subreg_p (mode, GET_MODE (x))
8700 : 121675749 : && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8701 : 121675749 : && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8702 : : {
8703 : : /* Bit-cast X into an integer mode. */
8704 : 0 : if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8705 : 0 : x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8706 : 0 : x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8707 : 0 : x, GET_MODE (x));
8708 : : }
8709 : :
8710 : 121675749 : return gen_lowpart (mode, x);
8711 : : }
8712 : :
8713 : : /* See if X can be simplified knowing that we will only refer to it in
8714 : : MODE and will only refer to those bits that are nonzero in MASK.
8715 : : If other bits are being computed or if masking operations are done
8716 : : that select a superset of the bits in MASK, they can sometimes be
8717 : : ignored.
8718 : :
8719 : : Return a possibly simplified expression, but always convert X to
8720 : : MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8721 : :
8722 : : If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8723 : : are all off in X. This is used when X will be complemented, by either
8724 : : NOT, NEG, or XOR. */
8725 : :
8726 : : static rtx
8727 : 91893250 : force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8728 : : bool just_select)
8729 : : {
8730 : 91893250 : enum rtx_code code = GET_CODE (x);
8731 : 91893250 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8732 : 91893250 : machine_mode op_mode;
8733 : 91893250 : unsigned HOST_WIDE_INT nonzero;
8734 : :
8735 : : /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8736 : : code below will do the wrong thing since the mode of such an
8737 : : expression is VOIDmode.
8738 : :
8739 : : Also do nothing if X is a CLOBBER; this can happen if X was
8740 : : the return value from a call to gen_lowpart. */
8741 : 91893250 : if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8742 : : return x;
8743 : :
8744 : : /* We want to perform the operation in its present mode unless we know
8745 : : that the operation is valid in MODE, in which case we do the operation
8746 : : in MODE. */
8747 : 149578300 : op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8748 : 84992128 : && have_insn_for (code, mode))
8749 : 142764007 : ? mode : GET_MODE (x));
8750 : :
8751 : : /* It is not valid to do a right-shift in a narrower mode
8752 : : than the one it came in with. */
8753 : 91806421 : if ((code == LSHIFTRT || code == ASHIFTRT)
8754 : 91806421 : && partial_subreg_p (mode, GET_MODE (x)))
8755 : 502920 : op_mode = GET_MODE (x);
8756 : :
8757 : : /* Truncate MASK to fit OP_MODE. */
8758 : 91806421 : if (op_mode)
8759 : 85021072 : mask &= GET_MODE_MASK (op_mode);
8760 : :
8761 : : /* Determine what bits of X are guaranteed to be (non)zero. */
8762 : 91806421 : nonzero = nonzero_bits (x, mode);
8763 : :
8764 : : /* If none of the bits in X are needed, return a zero. */
8765 : 91806421 : if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8766 : 551969 : x = const0_rtx;
8767 : :
8768 : : /* If X is a CONST_INT, return a new one. Do this here since the
8769 : : test below will fail. */
8770 : 91806421 : if (CONST_INT_P (x))
8771 : : {
8772 : 6860421 : if (SCALAR_INT_MODE_P (mode))
8773 : 6860421 : return gen_int_mode (INTVAL (x) & mask, mode);
8774 : : else
8775 : : {
8776 : 0 : x = GEN_INT (INTVAL (x) & mask);
8777 : 0 : return gen_lowpart_common (mode, x);
8778 : : }
8779 : : }
8780 : :
8781 : : /* If X is narrower than MODE and we want all the bits in X's mode, just
8782 : : get X in the proper mode. */
8783 : 84946000 : if (paradoxical_subreg_p (mode, GET_MODE (x))
8784 : 84946000 : && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8785 : 3548515 : return gen_lowpart (mode, x);
8786 : :
8787 : : /* We can ignore the effect of a SUBREG if it narrows the mode or
8788 : : if the constant masks to zero all the bits the mode doesn't have. */
8789 : 81397485 : if (GET_CODE (x) == SUBREG
8790 : 7776727 : && subreg_lowpart_p (x)
8791 : 89012911 : && (partial_subreg_p (x)
8792 : 5607300 : || (mask
8793 : 5607300 : & GET_MODE_MASK (GET_MODE (x))
8794 : 5607300 : & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8795 : 7588388 : return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8796 : :
8797 : 73809097 : scalar_int_mode int_mode, xmode;
8798 : 73809097 : if (is_a <scalar_int_mode> (mode, &int_mode)
8799 : 73809097 : && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8800 : : /* OP_MODE is either MODE or XMODE, so it must be a scalar
8801 : : integer too. */
8802 : 73780550 : return force_int_to_mode (x, int_mode, xmode,
8803 : : as_a <scalar_int_mode> (op_mode),
8804 : 73780550 : mask, just_select);
8805 : :
8806 : 28547 : return gen_lowpart_or_truncate (mode, x);
8807 : : }
8808 : :
8809 : : /* Subroutine of force_to_mode that handles cases in which both X and
8810 : : the result are scalar integers. MODE is the mode of the result,
8811 : : XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8812 : : is preferred for simplified versions of X. The other arguments
8813 : : are as for force_to_mode. */
8814 : :
8815 : : static rtx
8816 : 73780550 : force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8817 : : scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8818 : : bool just_select)
8819 : : {
8820 : 73780550 : enum rtx_code code = GET_CODE (x);
8821 : 73780550 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8822 : 73780550 : unsigned HOST_WIDE_INT fuller_mask;
8823 : 73780550 : rtx op0, op1, temp;
8824 : 73780550 : poly_int64 const_op0;
8825 : :
8826 : : /* When we have an arithmetic operation, or a shift whose count we
8827 : : do not know, we need to assume that all bits up to the highest-order
8828 : : bit in MASK will be needed. This is how we form such a mask. */
8829 : 73780550 : if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8830 : : fuller_mask = HOST_WIDE_INT_M1U;
8831 : : else
8832 : 81784483 : fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) - 1);
8833 : :
8834 : 73780550 : switch (code)
8835 : : {
8836 : : case CLOBBER:
8837 : : /* If X is a (clobber (const_int)), return it since we know we are
8838 : : generating something that won't match. */
8839 : : return x;
8840 : :
8841 : 354812 : case SIGN_EXTEND:
8842 : 354812 : case ZERO_EXTEND:
8843 : 354812 : case ZERO_EXTRACT:
8844 : 354812 : case SIGN_EXTRACT:
8845 : 354812 : x = expand_compound_operation (x);
8846 : 354812 : if (GET_CODE (x) != code)
8847 : 220786 : return force_to_mode (x, mode, mask, next_select);
8848 : : break;
8849 : :
8850 : 141 : case TRUNCATE:
8851 : : /* Similarly for a truncate. */
8852 : 141 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8853 : :
8854 : 3937210 : case AND:
8855 : : /* If this is an AND with a constant, convert it into an AND
8856 : : whose constant is the AND of that constant with MASK. If it
8857 : : remains an AND of MASK, delete it since it is redundant. */
8858 : :
8859 : 3937210 : if (CONST_INT_P (XEXP (x, 1)))
8860 : : {
8861 : 6435966 : x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8862 : 3217983 : mask & INTVAL (XEXP (x, 1)));
8863 : 3217983 : xmode = op_mode;
8864 : :
8865 : : /* If X is still an AND, see if it is an AND with a mask that
8866 : : is just some low-order bits. If so, and it is MASK, we don't
8867 : : need it. */
8868 : :
8869 : 3168871 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8870 : 6386854 : && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8871 : 21155 : x = XEXP (x, 0);
8872 : :
8873 : : /* If it remains an AND, try making another AND with the bits
8874 : : in the mode mask that aren't in MASK turned on. If the
8875 : : constant in the AND is wide enough, this might make a
8876 : : cheaper constant. */
8877 : :
8878 : 3147718 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8879 : 3147716 : && GET_MODE_MASK (xmode) != mask
8880 : 3300214 : && HWI_COMPUTABLE_MODE_P (xmode))
8881 : : {
8882 : 82231 : unsigned HOST_WIDE_INT cval
8883 : 82231 : = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8884 : 82231 : rtx y;
8885 : :
8886 : 82231 : y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8887 : 82231 : gen_int_mode (cval, xmode));
8888 : 82231 : if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8889 : 82231 : < set_src_cost (x, xmode, optimize_this_for_speed_p))
8890 : 73455103 : x = y;
8891 : : }
8892 : :
8893 : : break;
8894 : : }
8895 : :
8896 : 719227 : goto binop;
8897 : :
8898 : 10027266 : case PLUS:
8899 : : /* In (and (plus FOO C1) M), if M is a mask that just turns off
8900 : : low-order bits (as in an alignment operation) and FOO is already
8901 : : aligned to that boundary, mask C1 to that boundary as well.
8902 : : This may eliminate that PLUS and, later, the AND. */
8903 : :
8904 : 10027266 : {
8905 : 10027266 : unsigned int width = GET_MODE_PRECISION (mode);
8906 : 10027266 : unsigned HOST_WIDE_INT smask = mask;
8907 : :
8908 : : /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8909 : : number, sign extend it. */
8910 : :
8911 : 10027266 : if (width < HOST_BITS_PER_WIDE_INT
8912 : 3304540 : && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8913 : 2980282 : smask |= HOST_WIDE_INT_M1U << width;
8914 : :
8915 : 10027266 : if (CONST_INT_P (XEXP (x, 1))
8916 : 3820961 : && pow2p_hwi (- smask)
8917 : 3276048 : && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8918 : 12833730 : && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8919 : 12433 : return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8920 : 12433 : (INTVAL (XEXP (x, 1)) & smask)),
8921 : : mode, smask, next_select);
8922 : : }
8923 : :
8924 : : /* fall through */
8925 : :
8926 : 12140472 : case MULT:
8927 : : /* Substituting into the operands of a widening MULT is not likely to
8928 : : create RTL matching a machine insn. */
8929 : 12140472 : if (code == MULT
8930 : 2125639 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8931 : 2125639 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8932 : 97898 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8933 : 97898 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8934 : 39350 : && REG_P (XEXP (XEXP (x, 0), 0))
8935 : 29755 : && REG_P (XEXP (XEXP (x, 1), 0)))
8936 : 22171 : return gen_lowpart_or_truncate (mode, x);
8937 : :
8938 : : /* For PLUS, MINUS and MULT, we need any bits less significant than the
8939 : : most significant bit in MASK since carries from those bits will
8940 : : affect the bits we are interested in. */
8941 : 12118301 : mask = fuller_mask;
8942 : 12118301 : goto binop;
8943 : :
8944 : 2725498 : case MINUS:
8945 : : /* If X is (minus C Y) where C's least set bit is larger than any bit
8946 : : in the mask, then we may replace with (neg Y). */
8947 : 2725498 : if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8948 : 206169 : && known_alignment (poly_uint64 (const_op0)) > mask)
8949 : : {
8950 : 28 : x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8951 : 28 : return force_to_mode (x, mode, mask, next_select);
8952 : : }
8953 : :
8954 : : /* Similarly, if C contains every bit in the fuller_mask, then we may
8955 : : replace with (not Y). */
8956 : 2725470 : if (CONST_INT_P (XEXP (x, 0))
8957 : 206141 : && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8958 : : {
8959 : 505 : x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8960 : 505 : return force_to_mode (x, mode, mask, next_select);
8961 : : }
8962 : :
8963 : 2724965 : mask = fuller_mask;
8964 : 2724965 : goto binop;
8965 : :
8966 : 2845987 : case IOR:
8967 : 2845987 : case XOR:
8968 : : /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8969 : : LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8970 : : operation which may be a bitfield extraction. Ensure that the
8971 : : constant we form is not wider than the mode of X. */
8972 : :
8973 : 2845987 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8974 : 72549 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8975 : 62403 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8976 : 62403 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8977 : 62403 : && CONST_INT_P (XEXP (x, 1))
8978 : 8717 : && ((INTVAL (XEXP (XEXP (x, 0), 1))
8979 : 17434 : + floor_log2 (INTVAL (XEXP (x, 1))))
8980 : 8717 : < GET_MODE_PRECISION (xmode))
8981 : 2845987 : && (UINTVAL (XEXP (x, 1))
8982 : 5401 : & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8983 : : {
8984 : 10080 : temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8985 : 5040 : << INTVAL (XEXP (XEXP (x, 0), 1)),
8986 : : xmode);
8987 : 10080 : temp = simplify_gen_binary (GET_CODE (x), xmode,
8988 : 5040 : XEXP (XEXP (x, 0), 0), temp);
8989 : 10080 : x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8990 : 5040 : XEXP (XEXP (x, 0), 1));
8991 : 5040 : return force_to_mode (x, mode, mask, next_select);
8992 : : }
8993 : :
8994 : 18403440 : binop:
8995 : : /* For most binary operations, just propagate into the operation and
8996 : : change the mode if we have an operation of that mode. */
8997 : :
8998 : 18403440 : op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8999 : 18403440 : op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
9000 : :
9001 : : /* If we ended up truncating both operands, truncate the result of the
9002 : : operation instead. */
9003 : 18403440 : if (GET_CODE (op0) == TRUNCATE
9004 : 0 : && GET_CODE (op1) == TRUNCATE)
9005 : : {
9006 : 0 : op0 = XEXP (op0, 0);
9007 : 0 : op1 = XEXP (op1, 0);
9008 : : }
9009 : :
9010 : 18403440 : op0 = gen_lowpart_or_truncate (op_mode, op0);
9011 : 18403440 : op1 = gen_lowpart_or_truncate (op_mode, op1);
9012 : :
9013 : 18403440 : if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
9014 : : {
9015 : 2680953 : x = simplify_gen_binary (code, op_mode, op0, op1);
9016 : 2680953 : xmode = op_mode;
9017 : : }
9018 : : break;
9019 : :
9020 : 4645047 : case ASHIFT:
9021 : : /* For left shifts, do the same, but just for the first operand.
9022 : : However, we cannot do anything with shifts where we cannot
9023 : : guarantee that the counts are smaller than the size of the mode
9024 : : because such a count will have a different meaning in a
9025 : : wider mode. */
9026 : :
9027 : 4413038 : if (! (CONST_INT_P (XEXP (x, 1))
9028 : 4413063 : && INTVAL (XEXP (x, 1)) >= 0
9029 : 4413038 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
9030 : 4711502 : && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
9031 : 231984 : && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
9032 : 231984 : < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
9033 : : break;
9034 : :
9035 : : /* If the shift count is a constant and we can do arithmetic in
9036 : : the mode of the shift, refine which bits we need. Otherwise, use the
9037 : : conservative form of the mask. */
9038 : 4409084 : if (CONST_INT_P (XEXP (x, 1))
9039 : 4346608 : && INTVAL (XEXP (x, 1)) >= 0
9040 : 4346608 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9041 : 8755692 : && HWI_COMPUTABLE_MODE_P (op_mode))
9042 : 4343540 : mask >>= INTVAL (XEXP (x, 1));
9043 : : else
9044 : : mask = fuller_mask;
9045 : :
9046 : 4409084 : op0 = gen_lowpart_or_truncate (op_mode,
9047 : : force_to_mode (XEXP (x, 0), mode,
9048 : : mask, next_select));
9049 : :
9050 : 4409084 : if (op_mode != xmode || op0 != XEXP (x, 0))
9051 : : {
9052 : 1175244 : x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9053 : 1175244 : xmode = op_mode;
9054 : : }
9055 : : break;
9056 : :
9057 : 3412628 : case LSHIFTRT:
9058 : : /* Here we can only do something if the shift count is a constant,
9059 : : this shift constant is valid for the host, and we can do arithmetic
9060 : : in OP_MODE. */
9061 : :
9062 : 3412628 : if (CONST_INT_P (XEXP (x, 1))
9063 : 3299850 : && INTVAL (XEXP (x, 1)) >= 0
9064 : 3299849 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9065 : 6712463 : && HWI_COMPUTABLE_MODE_P (op_mode))
9066 : : {
9067 : 3295263 : rtx inner = XEXP (x, 0);
9068 : 3295263 : unsigned HOST_WIDE_INT inner_mask;
9069 : :
9070 : : /* Select the mask of the bits we need for the shift operand. */
9071 : 3295263 : inner_mask = mask << INTVAL (XEXP (x, 1));
9072 : :
9073 : : /* We can only change the mode of the shift if we can do arithmetic
9074 : : in the mode of the shift and INNER_MASK is no wider than the
9075 : : width of X's mode. */
9076 : 3295263 : if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9077 : 365260 : op_mode = xmode;
9078 : :
9079 : 3295263 : inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9080 : :
9081 : 3295263 : if (xmode != op_mode || inner != XEXP (x, 0))
9082 : : {
9083 : 765981 : x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9084 : 765981 : xmode = op_mode;
9085 : : }
9086 : : }
9087 : :
9088 : : /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9089 : : shift and AND produces only copies of the sign bit (C2 is one less
9090 : : than a power of two), we can do this with just a shift. */
9091 : :
9092 : 3412628 : if (GET_CODE (x) == LSHIFTRT
9093 : 3412577 : && CONST_INT_P (XEXP (x, 1))
9094 : : /* The shift puts one of the sign bit copies in the least significant
9095 : : bit. */
9096 : 6599598 : && ((INTVAL (XEXP (x, 1))
9097 : 3299799 : + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9098 : 3299799 : >= GET_MODE_PRECISION (xmode))
9099 : 258901 : && pow2p_hwi (mask + 1)
9100 : : /* Number of bits left after the shift must be more than the mask
9101 : : needs. */
9102 : 77541 : && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9103 : 77541 : <= GET_MODE_PRECISION (xmode))
9104 : : /* Must be more sign bit copies than the mask needs. */
9105 : 3445610 : && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9106 : 32982 : >= exact_log2 (mask + 1)))
9107 : : {
9108 : 32982 : int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9109 : 32982 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9110 : 32982 : gen_int_shift_amount (xmode, nbits));
9111 : : }
9112 : 3412628 : goto shiftrt;
9113 : :
9114 : 2018722 : case ASHIFTRT:
9115 : : /* If we are just looking for the sign bit, we don't need this shift at
9116 : : all, even if it has a variable count. */
9117 : 2018722 : if (val_signbit_p (xmode, mask))
9118 : 2351 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9119 : :
9120 : : /* If this is a shift by a constant, get a mask that contains those bits
9121 : : that are not copies of the sign bit. We then have two cases: If
9122 : : MASK only includes those bits, this can be a logical shift, which may
9123 : : allow simplifications. If MASK is a single-bit field not within
9124 : : those bits, we are requesting a copy of the sign bit and hence can
9125 : : shift the sign bit to the appropriate location. */
9126 : :
9127 : 2016371 : if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9128 : 1978522 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9129 : : {
9130 : 1978435 : unsigned HOST_WIDE_INT nonzero;
9131 : 1978435 : int i;
9132 : :
9133 : : /* If the considered data is wider than HOST_WIDE_INT, we can't
9134 : : represent a mask for all its bits in a single scalar.
9135 : : But we only care about the lower bits, so calculate these. */
9136 : :
9137 : 1978435 : if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9138 : : {
9139 : 396 : nonzero = HOST_WIDE_INT_M1U;
9140 : :
9141 : : /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9142 : : is the number of bits a full-width mask would have set.
9143 : : We need only shift if these are fewer than nonzero can
9144 : : hold. If not, we must keep all bits set in nonzero. */
9145 : :
9146 : 396 : if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9147 : : < HOST_BITS_PER_WIDE_INT)
9148 : 0 : nonzero >>= INTVAL (XEXP (x, 1))
9149 : 0 : + HOST_BITS_PER_WIDE_INT
9150 : 0 : - GET_MODE_PRECISION (xmode);
9151 : : }
9152 : : else
9153 : : {
9154 : 1978039 : nonzero = GET_MODE_MASK (xmode);
9155 : 1978039 : nonzero >>= INTVAL (XEXP (x, 1));
9156 : : }
9157 : :
9158 : 1978435 : if ((mask & ~nonzero) == 0)
9159 : : {
9160 : 48686 : x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9161 : : XEXP (x, 0), INTVAL (XEXP (x, 1)));
9162 : 48686 : if (GET_CODE (x) != ASHIFTRT)
9163 : 48686 : return force_to_mode (x, mode, mask, next_select);
9164 : : }
9165 : :
9166 : 1929749 : else if ((i = exact_log2 (mask)) >= 0)
9167 : : {
9168 : 72 : x = simplify_shift_const
9169 : 144 : (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9170 : 72 : GET_MODE_PRECISION (xmode) - 1 - i);
9171 : :
9172 : 72 : if (GET_CODE (x) != ASHIFTRT)
9173 : 72 : return force_to_mode (x, mode, mask, next_select);
9174 : : }
9175 : : }
9176 : :
9177 : : /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9178 : : even if the shift count isn't a constant. */
9179 : 1967613 : if (mask == 1)
9180 : 3224 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9181 : :
9182 : 1964389 : shiftrt:
9183 : :
9184 : : /* If this is a zero- or sign-extension operation that just affects bits
9185 : : we don't care about, remove it. Be sure the call above returned
9186 : : something that is still a shift. */
9187 : :
9188 : 5380241 : if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9189 : 5380190 : && CONST_INT_P (XEXP (x, 1))
9190 : 5229563 : && INTVAL (XEXP (x, 1)) >= 0
9191 : 5229562 : && (INTVAL (XEXP (x, 1))
9192 : 10459124 : <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9193 : 1745450 : && GET_CODE (XEXP (x, 0)) == ASHIFT
9194 : 5381174 : && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9195 : 765 : return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, next_select);
9196 : :
9197 : : break;
9198 : :
9199 : 36693 : case ROTATE:
9200 : 36693 : case ROTATERT:
9201 : : /* If the shift count is constant and we can do computations
9202 : : in the mode of X, compute where the bits we care about are.
9203 : : Otherwise, we can't do anything. Don't change the mode of
9204 : : the shift or propagate MODE into the shift, though. */
9205 : 36693 : if (CONST_INT_P (XEXP (x, 1))
9206 : 28012 : && INTVAL (XEXP (x, 1)) >= 0)
9207 : : {
9208 : 28010 : temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9209 : 28010 : xmode, gen_int_mode (mask, xmode),
9210 : : XEXP (x, 1));
9211 : 28010 : if (temp && CONST_INT_P (temp))
9212 : 28010 : x = simplify_gen_binary (code, xmode,
9213 : : force_to_mode (XEXP (x, 0), xmode,
9214 : 28010 : INTVAL (temp), next_select),
9215 : : XEXP (x, 1));
9216 : : }
9217 : : break;
9218 : :
9219 : 144223 : case NEG:
9220 : : /* If we just want the low-order bit, the NEG isn't needed since it
9221 : : won't change the low-order bit. */
9222 : 144223 : if (mask == 1)
9223 : 291 : return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9224 : :
9225 : : /* We need any bits less significant than the most significant bit in
9226 : : MASK since carries from those bits will affect the bits we are
9227 : : interested in. */
9228 : 143932 : mask = fuller_mask;
9229 : 143932 : goto unop;
9230 : :
9231 : 430141 : case NOT:
9232 : : /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9233 : : same as the XOR case above. Ensure that the constant we form is not
9234 : : wider than the mode of X. */
9235 : :
9236 : 430141 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9237 : 20053 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9238 : 19524 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9239 : 39048 : && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9240 : 19524 : < GET_MODE_PRECISION (xmode))
9241 : 442319 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9242 : : {
9243 : 12178 : temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9244 : 12178 : temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9245 : 24356 : x = simplify_gen_binary (LSHIFTRT, xmode,
9246 : 12178 : temp, XEXP (XEXP (x, 0), 1));
9247 : :
9248 : 12178 : return force_to_mode (x, mode, mask, next_select);
9249 : : }
9250 : :
9251 : : /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9252 : : use the full mask inside the NOT. */
9253 : : mask = fuller_mask;
9254 : :
9255 : 561895 : unop:
9256 : 561895 : op0 = gen_lowpart_or_truncate (op_mode,
9257 : : force_to_mode (XEXP (x, 0), mode, mask,
9258 : : next_select));
9259 : 561895 : if (op_mode != xmode || op0 != XEXP (x, 0))
9260 : : {
9261 : 75885 : x = simplify_gen_unary (code, op_mode, op0, op_mode);
9262 : 75885 : xmode = op_mode;
9263 : : }
9264 : : break;
9265 : :
9266 : 485208 : case NE:
9267 : : /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9268 : : in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9269 : : which is equal to STORE_FLAG_VALUE. */
9270 : 485208 : if ((mask & ~STORE_FLAG_VALUE) == 0
9271 : 3460 : && XEXP (x, 1) == const0_rtx
9272 : 3441 : && GET_MODE (XEXP (x, 0)) == mode
9273 : 2 : && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9274 : 485208 : && (nonzero_bits (XEXP (x, 0), mode)
9275 : : == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9276 : 0 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9277 : :
9278 : : break;
9279 : :
9280 : 1228054 : case IF_THEN_ELSE:
9281 : : /* We have no way of knowing if the IF_THEN_ELSE can itself be
9282 : : written in a narrower mode. We play it safe and do not do so. */
9283 : :
9284 : 1228054 : op0 = gen_lowpart_or_truncate (xmode,
9285 : : force_to_mode (XEXP (x, 1), mode,
9286 : : mask, next_select));
9287 : 1228054 : op1 = gen_lowpart_or_truncate (xmode,
9288 : : force_to_mode (XEXP (x, 2), mode,
9289 : : mask, next_select));
9290 : 1228054 : if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9291 : 175173 : x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9292 : 175173 : GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9293 : : op0, op1);
9294 : : break;
9295 : :
9296 : : default:
9297 : : break;
9298 : : }
9299 : :
9300 : : /* Ensure we return a value of the proper mode. */
9301 : 73455103 : return gen_lowpart_or_truncate (mode, x);
9302 : : }
9303 : :
9304 : : /* Return nonzero if X is an expression that has one of two values depending on
9305 : : whether some other value is zero or nonzero. In that case, we return the
9306 : : value that is being tested, *PTRUE is set to the value if the rtx being
9307 : : returned has a nonzero value, and *PFALSE is set to the other alternative.
9308 : :
9309 : : If we return zero, we set *PTRUE and *PFALSE to X. */
9310 : :
9311 : : static rtx
9312 : 236719249 : if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9313 : : {
9314 : 236719249 : machine_mode mode = GET_MODE (x);
9315 : 236719249 : enum rtx_code code = GET_CODE (x);
9316 : 236719249 : rtx cond0, cond1, true0, true1, false0, false1;
9317 : 236719249 : unsigned HOST_WIDE_INT nz;
9318 : 236719249 : scalar_int_mode int_mode;
9319 : :
9320 : : /* If we are comparing a value against zero, we are done. */
9321 : 236719249 : if ((code == NE || code == EQ)
9322 : 2335996 : && XEXP (x, 1) == const0_rtx)
9323 : : {
9324 : 1460977 : *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9325 : 1460977 : *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9326 : 1460977 : return XEXP (x, 0);
9327 : : }
9328 : :
9329 : : /* If this is a unary operation whose operand has one of two values, apply
9330 : : our opcode to compute those values. */
9331 : 235258272 : else if (UNARY_P (x)
9332 : 235258272 : && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9333 : : {
9334 : 414462 : *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9335 : 828924 : *pfalse = simplify_gen_unary (code, mode, false0,
9336 : 414462 : GET_MODE (XEXP (x, 0)));
9337 : 414462 : return cond0;
9338 : : }
9339 : :
9340 : : /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9341 : : make can't possibly match and would suppress other optimizations. */
9342 : 234843810 : else if (code == COMPARE)
9343 : : ;
9344 : :
9345 : : /* If this is a binary operation, see if either side has only one of two
9346 : : values. If either one does or if both do and they are conditional on
9347 : : the same value, compute the new true and false values. */
9348 : 230659709 : else if (BINARY_P (x))
9349 : : {
9350 : 85847074 : rtx op0 = XEXP (x, 0);
9351 : 85847074 : rtx op1 = XEXP (x, 1);
9352 : 85847074 : cond0 = if_then_else_cond (op0, &true0, &false0);
9353 : 85847074 : cond1 = if_then_else_cond (op1, &true1, &false1);
9354 : :
9355 : 518551 : if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9356 : 86338180 : && (REG_P (op0) || REG_P (op1)))
9357 : : {
9358 : : /* Try to enable a simplification by undoing work done by
9359 : : if_then_else_cond if it converted a REG into something more
9360 : : complex. */
9361 : 396028 : if (REG_P (op0))
9362 : : {
9363 : 92490 : cond0 = 0;
9364 : 92490 : true0 = false0 = op0;
9365 : : }
9366 : : else
9367 : : {
9368 : 303538 : cond1 = 0;
9369 : 303538 : true1 = false1 = op1;
9370 : : }
9371 : : }
9372 : :
9373 : 85847074 : if ((cond0 != 0 || cond1 != 0)
9374 : 85847074 : && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9375 : : {
9376 : : /* If if_then_else_cond returned zero, then true/false are the
9377 : : same rtl. We must copy one of them to prevent invalid rtl
9378 : : sharing. */
9379 : 4373500 : if (cond0 == 0)
9380 : 1421787 : true0 = copy_rtx (true0);
9381 : 2951713 : else if (cond1 == 0)
9382 : 2924268 : true1 = copy_rtx (true1);
9383 : :
9384 : 4373500 : if (COMPARISON_P (x))
9385 : : {
9386 : 250132 : *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9387 : : true0, true1);
9388 : 250132 : *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9389 : : false0, false1);
9390 : : }
9391 : : else
9392 : : {
9393 : 4123368 : *ptrue = simplify_gen_binary (code, mode, true0, true1);
9394 : 4123368 : *pfalse = simplify_gen_binary (code, mode, false0, false1);
9395 : : }
9396 : :
9397 : 5795287 : return cond0 ? cond0 : cond1;
9398 : : }
9399 : :
9400 : : /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9401 : : operands is zero when the other is nonzero, and vice-versa,
9402 : : and STORE_FLAG_VALUE is 1 or -1. */
9403 : :
9404 : 81473574 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9405 : 81473574 : && (code == PLUS || code == IOR || code == XOR || code == MINUS
9406 : : || code == UMAX)
9407 : 34428511 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9408 : : {
9409 : 35578 : rtx op0 = XEXP (XEXP (x, 0), 1);
9410 : 35578 : rtx op1 = XEXP (XEXP (x, 1), 1);
9411 : :
9412 : 35578 : cond0 = XEXP (XEXP (x, 0), 0);
9413 : 35578 : cond1 = XEXP (XEXP (x, 1), 0);
9414 : :
9415 : 35578 : if (COMPARISON_P (cond0)
9416 : 409 : && COMPARISON_P (cond1)
9417 : 0 : && SCALAR_INT_MODE_P (mode)
9418 : 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9419 : 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9420 : 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9421 : 0 : || ((swap_condition (GET_CODE (cond0))
9422 : 0 : == reversed_comparison_code (cond1, NULL))
9423 : 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9424 : 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9425 : 35578 : && ! side_effects_p (x))
9426 : : {
9427 : 0 : *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9428 : 0 : *pfalse = simplify_gen_binary (MULT, mode,
9429 : : (code == MINUS
9430 : 0 : ? simplify_gen_unary (NEG, mode,
9431 : : op1, mode)
9432 : : : op1),
9433 : : const_true_rtx);
9434 : 0 : return cond0;
9435 : : }
9436 : : }
9437 : :
9438 : : /* Similarly for MULT, AND and UMIN, except that for these the result
9439 : : is always zero. */
9440 : 81473574 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9441 : 81473574 : && (code == MULT || code == AND || code == UMIN)
9442 : 12064530 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9443 : : {
9444 : 886 : cond0 = XEXP (XEXP (x, 0), 0);
9445 : 886 : cond1 = XEXP (XEXP (x, 1), 0);
9446 : :
9447 : 886 : if (COMPARISON_P (cond0)
9448 : 0 : && COMPARISON_P (cond1)
9449 : 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9450 : 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9451 : 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9452 : 0 : || ((swap_condition (GET_CODE (cond0))
9453 : 0 : == reversed_comparison_code (cond1, NULL))
9454 : 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9455 : 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9456 : 886 : && ! side_effects_p (x))
9457 : : {
9458 : 0 : *ptrue = *pfalse = const0_rtx;
9459 : 0 : return cond0;
9460 : : }
9461 : : }
9462 : : }
9463 : :
9464 : 144812635 : else if (code == IF_THEN_ELSE)
9465 : : {
9466 : : /* If we have IF_THEN_ELSE already, extract the condition and
9467 : : canonicalize it if it is NE or EQ. */
9468 : 423427 : cond0 = XEXP (x, 0);
9469 : 423427 : *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9470 : 423427 : if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9471 : 126410 : return XEXP (cond0, 0);
9472 : 297017 : else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9473 : : {
9474 : 20638 : *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9475 : 20638 : return XEXP (cond0, 0);
9476 : : }
9477 : : else
9478 : : return cond0;
9479 : : }
9480 : :
9481 : : /* If X is a SUBREG, we can narrow both the true and false values
9482 : : if the inner expression, if there is a condition. */
9483 : 144389208 : else if (code == SUBREG
9484 : 144389208 : && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9485 : : &false0)) != 0)
9486 : : {
9487 : 770740 : true0 = simplify_gen_subreg (mode, true0,
9488 : 385370 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9489 : 770740 : false0 = simplify_gen_subreg (mode, false0,
9490 : 385370 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9491 : 385370 : if (true0 && false0)
9492 : : {
9493 : 385370 : *ptrue = true0;
9494 : 385370 : *pfalse = false0;
9495 : 385370 : return cond0;
9496 : : }
9497 : : }
9498 : :
9499 : : /* If X is a constant, this isn't special and will cause confusions
9500 : : if we treat it as such. Likewise if it is equivalent to a constant. */
9501 : 144003838 : else if (CONSTANT_P (x)
9502 : 144003838 : || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9503 : : ;
9504 : :
9505 : : /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9506 : : will be least confusing to the rest of the compiler. */
9507 : 95233333 : else if (mode == BImode)
9508 : : {
9509 : 0 : *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9510 : 0 : return x;
9511 : : }
9512 : :
9513 : : /* If X is known to be either 0 or -1, those are the true and
9514 : : false values when testing X. */
9515 : 95233333 : else if (x == constm1_rtx || x == const0_rtx
9516 : 95233333 : || (is_a <scalar_int_mode> (mode, &int_mode)
9517 : 69539007 : && (num_sign_bit_copies (x, int_mode)
9518 : 69539007 : == GET_MODE_PRECISION (int_mode))))
9519 : : {
9520 : 762859 : *ptrue = constm1_rtx, *pfalse = const0_rtx;
9521 : 762859 : return x;
9522 : : }
9523 : :
9524 : : /* Likewise for 0 or a single bit. */
9525 : 94470474 : else if (HWI_COMPUTABLE_MODE_P (mode)
9526 : 65107234 : && pow2p_hwi (nz = nonzero_bits (x, mode)))
9527 : : {
9528 : 1925561 : *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9529 : 1925561 : return x;
9530 : : }
9531 : :
9532 : : /* Otherwise fail; show no condition with true and false values the same. */
9533 : 226973093 : *ptrue = *pfalse = x;
9534 : 226973093 : return 0;
9535 : : }
9536 : :
9537 : : /* Return the value of expression X given the fact that condition COND
9538 : : is known to be true when applied to REG as its first operand and VAL
9539 : : as its second. X is known to not be shared and so can be modified in
9540 : : place.
9541 : :
9542 : : We only handle the simplest cases, and specifically those cases that
9543 : : arise with IF_THEN_ELSE expressions. */
9544 : :
9545 : : static rtx
9546 : 537439 : known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9547 : : {
9548 : 537439 : enum rtx_code code = GET_CODE (x);
9549 : 537439 : const char *fmt;
9550 : 537439 : int i, j;
9551 : :
9552 : 537439 : if (side_effects_p (x))
9553 : : return x;
9554 : :
9555 : : /* If either operand of the condition is a floating point value,
9556 : : then we have to avoid collapsing an EQ comparison. */
9557 : 537439 : if (cond == EQ
9558 : 102477 : && rtx_equal_p (x, reg)
9559 : 68201 : && ! FLOAT_MODE_P (GET_MODE (x))
9560 : 605640 : && ! FLOAT_MODE_P (GET_MODE (val)))
9561 : : return val;
9562 : :
9563 : 469238 : if (cond == UNEQ && rtx_equal_p (x, reg))
9564 : : return val;
9565 : :
9566 : : /* If X is (abs REG) and we know something about REG's relationship
9567 : : with zero, we may be able to simplify this. */
9568 : :
9569 : 469238 : if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9570 : 1 : switch (cond)
9571 : : {
9572 : 0 : case GE: case GT: case EQ:
9573 : 0 : return XEXP (x, 0);
9574 : 1 : case LT: case LE:
9575 : 2 : return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9576 : : XEXP (x, 0),
9577 : 1 : GET_MODE (XEXP (x, 0)));
9578 : : default:
9579 : : break;
9580 : : }
9581 : :
9582 : : /* The only other cases we handle are MIN, MAX, and comparisons if the
9583 : : operands are the same as REG and VAL. */
9584 : :
9585 : 469237 : else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9586 : : {
9587 : 231822 : if (rtx_equal_p (XEXP (x, 0), val))
9588 : : {
9589 : 3 : std::swap (val, reg);
9590 : 3 : cond = swap_condition (cond);
9591 : : }
9592 : :
9593 : 231822 : if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9594 : : {
9595 : 208998 : if (COMPARISON_P (x))
9596 : : {
9597 : 208795 : if (comparison_dominates_p (cond, code))
9598 : 288 : return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9599 : :
9600 : 208507 : code = reversed_comparison_code (x, NULL);
9601 : 208507 : if (code != UNKNOWN
9602 : 208507 : && comparison_dominates_p (cond, code))
9603 : 40 : return CONST0_RTX (GET_MODE (x));
9604 : : else
9605 : 208467 : return x;
9606 : : }
9607 : 203 : else if (code == SMAX || code == SMIN
9608 : 203 : || code == UMIN || code == UMAX)
9609 : : {
9610 : 37 : int unsignedp = (code == UMIN || code == UMAX);
9611 : :
9612 : : /* Do not reverse the condition when it is NE or EQ.
9613 : : This is because we cannot conclude anything about
9614 : : the value of 'SMAX (x, y)' when x is not equal to y,
9615 : : but we can when x equals y. */
9616 : 37 : if ((code == SMAX || code == UMAX)
9617 : 34 : && ! (cond == EQ || cond == NE))
9618 : 1 : cond = reverse_condition (cond);
9619 : :
9620 : 4 : switch (cond)
9621 : : {
9622 : 0 : case GE: case GT:
9623 : 0 : return unsignedp ? x : XEXP (x, 1);
9624 : 4 : case LE: case LT:
9625 : 4 : return unsignedp ? x : XEXP (x, 0);
9626 : 0 : case GEU: case GTU:
9627 : 0 : return unsignedp ? XEXP (x, 1) : x;
9628 : 0 : case LEU: case LTU:
9629 : 0 : return unsignedp ? XEXP (x, 0) : x;
9630 : : default:
9631 : : break;
9632 : : }
9633 : : }
9634 : : }
9635 : : }
9636 : 237415 : else if (code == SUBREG)
9637 : : {
9638 : 7078 : machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9639 : 7078 : rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9640 : :
9641 : 7078 : if (SUBREG_REG (x) != r)
9642 : : {
9643 : : /* We must simplify subreg here, before we lose track of the
9644 : : original inner_mode. */
9645 : 16 : new_rtx = simplify_subreg (GET_MODE (x), r,
9646 : 8 : inner_mode, SUBREG_BYTE (x));
9647 : 8 : if (new_rtx)
9648 : : return new_rtx;
9649 : : else
9650 : 8 : SUBST (SUBREG_REG (x), r);
9651 : : }
9652 : :
9653 : 7078 : return x;
9654 : : }
9655 : : /* We don't have to handle SIGN_EXTEND here, because even in the
9656 : : case of replacing something with a modeless CONST_INT, a
9657 : : CONST_INT is already (supposed to be) a valid sign extension for
9658 : : its narrower mode, which implies it's already properly
9659 : : sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9660 : : story is different. */
9661 : 230337 : else if (code == ZERO_EXTEND)
9662 : : {
9663 : 1116 : machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9664 : 1116 : rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9665 : :
9666 : 1116 : if (XEXP (x, 0) != r)
9667 : : {
9668 : : /* We must simplify the zero_extend here, before we lose
9669 : : track of the original inner_mode. */
9670 : 0 : new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9671 : : r, inner_mode);
9672 : 0 : if (new_rtx)
9673 : : return new_rtx;
9674 : : else
9675 : 0 : SUBST (XEXP (x, 0), r);
9676 : : }
9677 : :
9678 : 1116 : return x;
9679 : : }
9680 : :
9681 : 252244 : fmt = GET_RTX_FORMAT (code);
9682 : 581057 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9683 : : {
9684 : 328813 : if (fmt[i] == 'e')
9685 : 155349 : SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9686 : 173464 : else if (fmt[i] == 'E')
9687 : 8780 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9688 : 7072 : SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9689 : : cond, reg, val));
9690 : : }
9691 : :
9692 : : return x;
9693 : : }
9694 : :
9695 : : /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9696 : : assignment as a field assignment. */
9697 : :
9698 : : static bool
9699 : 617392 : rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9700 : : {
9701 : 617392 : if (widen_x && GET_MODE (x) != GET_MODE (y))
9702 : : {
9703 : 55056 : if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9704 : : return false;
9705 : 55056 : if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9706 : : return false;
9707 : 55056 : x = adjust_address_nv (x, GET_MODE (y),
9708 : : byte_lowpart_offset (GET_MODE (y),
9709 : : GET_MODE (x)));
9710 : : }
9711 : :
9712 : 617392 : if (x == y || rtx_equal_p (x, y))
9713 : 11640 : return true;
9714 : :
9715 : 605752 : if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9716 : : return false;
9717 : :
9718 : : /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9719 : : Note that all SUBREGs of MEM are paradoxical; otherwise they
9720 : : would have been rewritten. */
9721 : 98465 : if (MEM_P (x) && GET_CODE (y) == SUBREG
9722 : 6109 : && MEM_P (SUBREG_REG (y))
9723 : 605752 : && rtx_equal_p (SUBREG_REG (y),
9724 : 0 : gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9725 : : return true;
9726 : :
9727 : 74748 : if (MEM_P (y) && GET_CODE (x) == SUBREG
9728 : 7568 : && MEM_P (SUBREG_REG (x))
9729 : 605890 : && rtx_equal_p (SUBREG_REG (x),
9730 : 138 : gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9731 : : return true;
9732 : :
9733 : : /* We used to see if get_last_value of X and Y were the same but that's
9734 : : not correct. In one direction, we'll cause the assignment to have
9735 : : the wrong destination and in the case, we'll import a register into this
9736 : : insn that might have already have been dead. So fail if none of the
9737 : : above cases are true. */
9738 : : return false;
9739 : : }
9740 : :
9741 : : /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9742 : : Return that assignment if so.
9743 : :
9744 : : We only handle the most common cases. */
9745 : :
9746 : : static rtx
9747 : 45753723 : make_field_assignment (rtx x)
9748 : : {
9749 : 45753723 : rtx dest = SET_DEST (x);
9750 : 45753723 : rtx src = SET_SRC (x);
9751 : 45753723 : rtx assign;
9752 : 45753723 : rtx rhs, lhs;
9753 : 45753723 : HOST_WIDE_INT c1;
9754 : 45753723 : HOST_WIDE_INT pos;
9755 : 45753723 : unsigned HOST_WIDE_INT len;
9756 : 45753723 : rtx other;
9757 : :
9758 : : /* All the rules in this function are specific to scalar integers. */
9759 : 45753723 : scalar_int_mode mode;
9760 : 67625053 : if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9761 : : return x;
9762 : :
9763 : : /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9764 : : a clear of a one-bit field. We will have changed it to
9765 : : (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9766 : : for a SUBREG. */
9767 : :
9768 : 1345189 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9769 : 2398 : && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9770 : 569 : && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9771 : 21879168 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9772 : : {
9773 : 155 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9774 : : 1, true, true, false);
9775 : 155 : if (assign != 0)
9776 : 152 : return gen_rtx_SET (assign, const0_rtx);
9777 : : return x;
9778 : : }
9779 : :
9780 : 1345034 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9781 : 89417 : && subreg_lowpart_p (XEXP (src, 0))
9782 : 89384 : && partial_subreg_p (XEXP (src, 0))
9783 : 19450 : && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9784 : 115 : && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9785 : 55 : && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9786 : 21878499 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9787 : : {
9788 : 14 : assign = make_extraction (VOIDmode, dest, 0,
9789 : 7 : XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9790 : : 1, true, true, false);
9791 : 7 : if (assign != 0)
9792 : 7 : return gen_rtx_SET (assign, const0_rtx);
9793 : : return x;
9794 : : }
9795 : :
9796 : : /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9797 : : one-bit field. */
9798 : 1987234 : if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9799 : 446312 : && XEXP (XEXP (src, 0), 0) == const1_rtx
9800 : 21880284 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9801 : : {
9802 : 494 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9803 : : 1, true, true, false);
9804 : 494 : if (assign != 0)
9805 : 467 : return gen_rtx_SET (assign, const1_rtx);
9806 : : return x;
9807 : : }
9808 : :
9809 : : /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9810 : : SRC is an AND with all bits of that field set, then we can discard
9811 : : the AND. */
9812 : 21877943 : if (GET_CODE (dest) == ZERO_EXTRACT
9813 : 2676 : && CONST_INT_P (XEXP (dest, 1))
9814 : 2676 : && GET_CODE (src) == AND
9815 : 24 : && CONST_INT_P (XEXP (src, 1)))
9816 : : {
9817 : 24 : HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9818 : 24 : unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9819 : 24 : unsigned HOST_WIDE_INT ze_mask;
9820 : :
9821 : 24 : if (width >= HOST_BITS_PER_WIDE_INT)
9822 : : ze_mask = -1;
9823 : : else
9824 : 24 : ze_mask = (HOST_WIDE_INT_1U << width) - 1;
9825 : :
9826 : : /* Complete overlap. We can remove the source AND. */
9827 : 24 : if ((and_mask & ze_mask) == ze_mask)
9828 : 24 : return gen_rtx_SET (dest, XEXP (src, 0));
9829 : :
9830 : : /* Partial overlap. We can reduce the source AND. */
9831 : 0 : if ((and_mask & ze_mask) != and_mask)
9832 : : {
9833 : 0 : src = gen_rtx_AND (mode, XEXP (src, 0),
9834 : : gen_int_mode (and_mask & ze_mask, mode));
9835 : 0 : return gen_rtx_SET (dest, src);
9836 : : }
9837 : : }
9838 : :
9839 : : /* The other case we handle is assignments into a constant-position
9840 : : field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9841 : : a mask that has all one bits except for a group of zero bits and
9842 : : OTHER is known to have zeros where C1 has ones, this is such an
9843 : : assignment. Compute the position and length from C1. Shift OTHER
9844 : : to the appropriate position, force it to the required mode, and
9845 : : make the extraction. Check for the AND in both operands. */
9846 : :
9847 : : /* One or more SUBREGs might obscure the constant-position field
9848 : : assignment. The first one we are likely to encounter is an outer
9849 : : narrowing SUBREG, which we can just strip for the purposes of
9850 : : identifying the constant-field assignment. */
9851 : 21877919 : scalar_int_mode src_mode = mode;
9852 : 21877919 : if (GET_CODE (src) == SUBREG
9853 : 223708 : && subreg_lowpart_p (src)
9854 : 22082015 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9855 : : src = SUBREG_REG (src);
9856 : :
9857 : 21877919 : if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9858 : : return x;
9859 : :
9860 : 2168847 : rhs = expand_compound_operation (XEXP (src, 0));
9861 : 2168847 : lhs = expand_compound_operation (XEXP (src, 1));
9862 : :
9863 : 2168847 : if (GET_CODE (rhs) == AND
9864 : 842868 : && CONST_INT_P (XEXP (rhs, 1))
9865 : 2646340 : && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9866 : 11013 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9867 : : /* The second SUBREG that might get in the way is a paradoxical
9868 : : SUBREG around the first operand of the AND. We want to
9869 : : pretend the operand is as wide as the destination here. We
9870 : : do this by adjusting the MEM to wider mode for the sole
9871 : : purpose of the call to rtx_equal_for_field_assignment_p. Also
9872 : : note this trick only works for MEMs. */
9873 : 2157834 : else if (GET_CODE (rhs) == AND
9874 : 831855 : && paradoxical_subreg_p (XEXP (rhs, 0))
9875 : 77187 : && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9876 : 30286 : && CONST_INT_P (XEXP (rhs, 1))
9877 : 2188120 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9878 : : dest, true))
9879 : 0 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9880 : 2157834 : else if (GET_CODE (lhs) == AND
9881 : 92133 : && CONST_INT_P (XEXP (lhs, 1))
9882 : 2240206 : && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9883 : 22 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9884 : : /* The second SUBREG that might get in the way is a paradoxical
9885 : : SUBREG around the first operand of the AND. We want to
9886 : : pretend the operand is as wide as the destination here. We
9887 : : do this by adjusting the MEM to wider mode for the sole
9888 : : purpose of the call to rtx_equal_for_field_assignment_p. Also
9889 : : note this trick only works for MEMs. */
9890 : 2157812 : else if (GET_CODE (lhs) == AND
9891 : 92111 : && paradoxical_subreg_p (XEXP (lhs, 0))
9892 : 34528 : && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9893 : 24770 : && CONST_INT_P (XEXP (lhs, 1))
9894 : 2182582 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9895 : : dest, true))
9896 : 0 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9897 : : else
9898 : 2157812 : return x;
9899 : :
9900 : 11035 : pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9901 : 11035 : if (pos < 0
9902 : 6742 : || pos + len > GET_MODE_PRECISION (mode)
9903 : 6742 : || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9904 : 17773 : || (c1 & nonzero_bits (other, mode)) != 0)
9905 : 4404 : return x;
9906 : :
9907 : 6631 : assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len,
9908 : : true, true, false);
9909 : 6631 : if (assign == 0)
9910 : : return x;
9911 : :
9912 : : /* The mode to use for the source is the mode of the assignment, or of
9913 : : what is inside a possible STRICT_LOW_PART. */
9914 : 13238 : machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9915 : 6619 : ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9916 : :
9917 : : /* Shift OTHER right POS places and make it the source, restricting it
9918 : : to the proper length and mode. */
9919 : :
9920 : 6619 : src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9921 : : src_mode, other, pos),
9922 : : dest);
9923 : 13238 : src = force_to_mode (src, new_mode,
9924 : : len >= HOST_BITS_PER_WIDE_INT
9925 : : ? HOST_WIDE_INT_M1U
9926 : 6619 : : (HOST_WIDE_INT_1U << len) - 1, false);
9927 : :
9928 : : /* If SRC is masked by an AND that does not make a difference in
9929 : : the value being stored, strip it. */
9930 : 6619 : if (GET_CODE (assign) == ZERO_EXTRACT
9931 : 6570 : && CONST_INT_P (XEXP (assign, 1))
9932 : 6570 : && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9933 : 6570 : && GET_CODE (src) == AND
9934 : 0 : && CONST_INT_P (XEXP (src, 1))
9935 : 0 : && UINTVAL (XEXP (src, 1))
9936 : 0 : == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9937 : 0 : src = XEXP (src, 0);
9938 : :
9939 : 6619 : return gen_rtx_SET (assign, src);
9940 : : }
9941 : :
9942 : : /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9943 : : if so. */
9944 : :
9945 : : static rtx
9946 : 51127129 : apply_distributive_law (rtx x)
9947 : : {
9948 : 51127129 : enum rtx_code code = GET_CODE (x);
9949 : 51127129 : enum rtx_code inner_code;
9950 : 51127129 : rtx lhs, rhs, other;
9951 : 51127129 : rtx tem;
9952 : :
9953 : : /* Distributivity is not true for floating point as it can change the
9954 : : value. So we don't do it unless -funsafe-math-optimizations. */
9955 : 51127129 : if (FLOAT_MODE_P (GET_MODE (x))
9956 : 3534849 : && ! flag_unsafe_math_optimizations)
9957 : : return x;
9958 : :
9959 : : /* The outer operation can only be one of the following: */
9960 : 48008983 : if (code != IOR && code != AND && code != XOR
9961 : 48008983 : && code != PLUS && code != MINUS)
9962 : : return x;
9963 : :
9964 : 47994207 : lhs = XEXP (x, 0);
9965 : 47994207 : rhs = XEXP (x, 1);
9966 : :
9967 : : /* If either operand is a primitive we can't do anything, so get out
9968 : : fast. */
9969 : 47994207 : if (OBJECT_P (lhs) || OBJECT_P (rhs))
9970 : : return x;
9971 : :
9972 : 3022003 : lhs = expand_compound_operation (lhs);
9973 : 3022003 : rhs = expand_compound_operation (rhs);
9974 : 3022003 : inner_code = GET_CODE (lhs);
9975 : 3022003 : if (inner_code != GET_CODE (rhs))
9976 : : return x;
9977 : :
9978 : : /* See if the inner and outer operations distribute. */
9979 : 867424 : switch (inner_code)
9980 : : {
9981 : 325692 : case LSHIFTRT:
9982 : 325692 : case ASHIFTRT:
9983 : 325692 : case AND:
9984 : 325692 : case IOR:
9985 : : /* These all distribute except over PLUS. */
9986 : 325692 : if (code == PLUS || code == MINUS)
9987 : : return x;
9988 : : break;
9989 : :
9990 : 88746 : case MULT:
9991 : 88746 : if (code != PLUS && code != MINUS)
9992 : : return x;
9993 : : break;
9994 : :
9995 : : case ASHIFT:
9996 : : /* This is also a multiply, so it distributes over everything. */
9997 : : break;
9998 : :
9999 : : /* This used to handle SUBREG, but this turned out to be counter-
10000 : : productive, since (subreg (op ...)) usually is not handled by
10001 : : insn patterns, and this "optimization" therefore transformed
10002 : : recognizable patterns into unrecognizable ones. Therefore the
10003 : : SUBREG case was removed from here.
10004 : :
10005 : : It is possible that distributing SUBREG over arithmetic operations
10006 : : leads to an intermediate result than can then be optimized further,
10007 : : e.g. by moving the outer SUBREG to the other side of a SET as done
10008 : : in simplify_set. This seems to have been the original intent of
10009 : : handling SUBREGs here.
10010 : :
10011 : : However, with current GCC this does not appear to actually happen,
10012 : : at least on major platforms. If some case is found where removing
10013 : : the SUBREG case here prevents follow-on optimizations, distributing
10014 : : SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
10015 : :
10016 : : default:
10017 : : return x;
10018 : : }
10019 : :
10020 : : /* Set LHS and RHS to the inner operands (A and B in the example
10021 : : above) and set OTHER to the common operand (C in the example).
10022 : : There is only one way to do this unless the inner operation is
10023 : : commutative. */
10024 : 339404 : if (COMMUTATIVE_ARITH_P (lhs)
10025 : 339404 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
10026 : 2141 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
10027 : 337263 : else if (COMMUTATIVE_ARITH_P (lhs)
10028 : 337263 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
10029 : 15 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
10030 : 337248 : else if (COMMUTATIVE_ARITH_P (lhs)
10031 : 337248 : && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
10032 : 10848 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
10033 : 326400 : else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
10034 : 59876 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
10035 : : else
10036 : : return x;
10037 : :
10038 : : /* Form the new inner operation, seeing if it simplifies first. */
10039 : 72880 : tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10040 : :
10041 : : /* There is one exception to the general way of distributing:
10042 : : (a | c) ^ (b | c) -> (a ^ b) & ~c */
10043 : 72880 : if (code == XOR && inner_code == IOR)
10044 : : {
10045 : 80 : inner_code = AND;
10046 : 80 : other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10047 : : }
10048 : :
10049 : : /* We may be able to continuing distributing the result, so call
10050 : : ourselves recursively on the inner operation before forming the
10051 : : outer operation, which we return. */
10052 : 72880 : return simplify_gen_binary (inner_code, GET_MODE (x),
10053 : 72880 : apply_distributive_law (tem), other);
10054 : : }
10055 : :
10056 : : /* See if X is of the form (* (+ A B) C), and if so convert to
10057 : : (+ (* A C) (* B C)) and try to simplify.
10058 : :
10059 : : Most of the time, this results in no change. However, if some of
10060 : : the operands are the same or inverses of each other, simplifications
10061 : : will result.
10062 : :
10063 : : For example, (and (ior A B) (not B)) can occur as the result of
10064 : : expanding a bit field assignment. When we apply the distributive
10065 : : law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10066 : : which then simplifies to (and (A (not B))).
10067 : :
10068 : : Note that no checks happen on the validity of applying the inverse
10069 : : distributive law. This is pointless since we can do it in the
10070 : : few places where this routine is called.
10071 : :
10072 : : N is the index of the term that is decomposed (the arithmetic operation,
10073 : : i.e. (+ A B) in the first example above). !N is the index of the term that
10074 : : is distributed, i.e. of C in the first example above. */
10075 : : static rtx
10076 : 1751388 : distribute_and_simplify_rtx (rtx x, int n)
10077 : : {
10078 : 1751388 : machine_mode mode;
10079 : 1751388 : enum rtx_code outer_code, inner_code;
10080 : 1751388 : rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10081 : :
10082 : : /* Distributivity is not true for floating point as it can change the
10083 : : value. So we don't do it unless -funsafe-math-optimizations. */
10084 : 1751388 : if (FLOAT_MODE_P (GET_MODE (x))
10085 : 118774 : && ! flag_unsafe_math_optimizations)
10086 : : return NULL_RTX;
10087 : :
10088 : 1635974 : decomposed = XEXP (x, n);
10089 : 1635974 : if (!ARITHMETIC_P (decomposed))
10090 : : return NULL_RTX;
10091 : :
10092 : 1635974 : mode = GET_MODE (x);
10093 : 1635974 : outer_code = GET_CODE (x);
10094 : 1635974 : distributed = XEXP (x, !n);
10095 : :
10096 : 1635974 : inner_code = GET_CODE (decomposed);
10097 : 1635974 : inner_op0 = XEXP (decomposed, 0);
10098 : 1635974 : inner_op1 = XEXP (decomposed, 1);
10099 : :
10100 : : /* Special case (and (xor B C) (not A)), which is equivalent to
10101 : : (xor (ior A B) (ior A C)) */
10102 : 1635974 : if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10103 : : {
10104 : 70 : distributed = XEXP (distributed, 0);
10105 : 70 : outer_code = IOR;
10106 : : }
10107 : :
10108 : 1635974 : if (n == 0)
10109 : : {
10110 : : /* Distribute the second term. */
10111 : 1564868 : new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10112 : 1564868 : new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10113 : : }
10114 : : else
10115 : : {
10116 : : /* Distribute the first term. */
10117 : 71106 : new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10118 : 71106 : new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10119 : : }
10120 : :
10121 : 1635974 : tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10122 : : new_op0, new_op1));
10123 : 1635974 : if (GET_CODE (tmp) != outer_code
10124 : 1635974 : && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10125 : 292133 : < set_src_cost (x, mode, optimize_this_for_speed_p)))
10126 : : return tmp;
10127 : :
10128 : : return NULL_RTX;
10129 : : }
10130 : :
10131 : : /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10132 : : in MODE. Return an equivalent form, if different from (and VAROP
10133 : : (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10134 : :
10135 : : static rtx
10136 : 12872485 : simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10137 : : unsigned HOST_WIDE_INT constop)
10138 : : {
10139 : 12872485 : unsigned HOST_WIDE_INT nonzero;
10140 : 12872485 : unsigned HOST_WIDE_INT orig_constop;
10141 : 12872485 : rtx orig_varop;
10142 : 12872485 : int i;
10143 : :
10144 : 12872485 : orig_varop = varop;
10145 : 12872485 : orig_constop = constop;
10146 : 12872485 : if (GET_CODE (varop) == CLOBBER)
10147 : : return NULL_RTX;
10148 : :
10149 : : /* Simplify VAROP knowing that we will be only looking at some of the
10150 : : bits in it.
10151 : :
10152 : : Note by passing in CONSTOP, we guarantee that the bits not set in
10153 : : CONSTOP are not significant and will never be examined. We must
10154 : : ensure that is the case by explicitly masking out those bits
10155 : : before returning. */
10156 : 12872485 : varop = force_to_mode (varop, mode, constop, false);
10157 : :
10158 : : /* If VAROP is a CLOBBER, we will fail so return it. */
10159 : 12872485 : if (GET_CODE (varop) == CLOBBER)
10160 : : return varop;
10161 : :
10162 : : /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10163 : : to VAROP and return the new constant. */
10164 : 12872475 : if (CONST_INT_P (varop))
10165 : 311179 : return gen_int_mode (INTVAL (varop) & constop, mode);
10166 : :
10167 : : /* See what bits may be nonzero in VAROP. Unlike the general case of
10168 : : a call to nonzero_bits, here we don't care about bits outside
10169 : : MODE unless WORD_REGISTER_OPERATIONS is true. */
10170 : :
10171 : 12561296 : scalar_int_mode tmode = mode;
10172 : 12561296 : if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10173 : : tmode = word_mode;
10174 : 12561296 : nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10175 : :
10176 : : /* Turn off all bits in the constant that are known to already be zero.
10177 : : Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10178 : : which is tested below. */
10179 : :
10180 : 12561296 : constop &= nonzero;
10181 : :
10182 : : /* If we don't have any bits left, return zero. */
10183 : 12561296 : if (constop == 0 && !side_effects_p (varop))
10184 : 0 : return const0_rtx;
10185 : :
10186 : : /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10187 : : a power of two, we can replace this with an ASHIFT. */
10188 : 31873 : if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10189 : 12567525 : && (i = exact_log2 (constop)) >= 0)
10190 : 119 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10191 : :
10192 : : /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10193 : : or XOR, then try to apply the distributive law. This may eliminate
10194 : : operations if either branch can be simplified because of the AND.
10195 : : It may also make some cases more complex, but those cases probably
10196 : : won't match a pattern either with or without this. */
10197 : :
10198 : 12561177 : if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10199 : : {
10200 : 75911 : scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10201 : 75911 : return
10202 : 75911 : gen_lowpart
10203 : 75911 : (mode,
10204 : : apply_distributive_law
10205 : 75911 : (simplify_gen_binary (GET_CODE (varop), varop_mode,
10206 : : simplify_and_const_int (NULL_RTX, varop_mode,
10207 : : XEXP (varop, 0),
10208 : : constop),
10209 : : simplify_and_const_int (NULL_RTX, varop_mode,
10210 : : XEXP (varop, 1),
10211 : : constop))));
10212 : : }
10213 : :
10214 : : /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10215 : : the AND and see if one of the operands simplifies to zero. If so, we
10216 : : may eliminate it. */
10217 : :
10218 : 12485266 : if (GET_CODE (varop) == PLUS
10219 : 12485266 : && pow2p_hwi (constop + 1))
10220 : : {
10221 : 441616 : rtx o0, o1;
10222 : :
10223 : 441616 : o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10224 : 441616 : o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10225 : 441616 : if (o0 == const0_rtx)
10226 : : return o1;
10227 : 441616 : if (o1 == const0_rtx)
10228 : : return o0;
10229 : : }
10230 : :
10231 : : /* Make a SUBREG if necessary. If we can't make it, fail. */
10232 : 12485191 : varop = gen_lowpart (mode, varop);
10233 : 12485191 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10234 : : return NULL_RTX;
10235 : :
10236 : : /* If we are only masking insignificant bits, return VAROP. */
10237 : 12485191 : if (constop == nonzero)
10238 : : return varop;
10239 : :
10240 : 12035446 : if (varop == orig_varop && constop == orig_constop)
10241 : : return NULL_RTX;
10242 : :
10243 : : /* Otherwise, return an AND. */
10244 : 6714383 : return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10245 : : }
10246 : :
10247 : :
10248 : : /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10249 : : in MODE.
10250 : :
10251 : : Return an equivalent form, if different from X. Otherwise, return X. If
10252 : : X is zero, we are to always construct the equivalent form. */
10253 : :
10254 : : static rtx
10255 : 12872485 : simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10256 : : unsigned HOST_WIDE_INT constop)
10257 : : {
10258 : 12872485 : rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10259 : 12872485 : if (tem)
10260 : : return tem;
10261 : :
10262 : 5321063 : if (!x)
10263 : 1247364 : x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10264 : 1247364 : gen_int_mode (constop, mode));
10265 : 5321063 : if (GET_MODE (x) != mode)
10266 : 0 : x = gen_lowpart (mode, x);
10267 : : return x;
10268 : : }
10269 : :
10270 : : /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10271 : : We don't care about bits outside of those defined in MODE.
10272 : : We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10273 : :
10274 : : For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10275 : : a shift, AND, or zero_extract, we can do better. */
10276 : :
10277 : : static rtx
10278 : 448969160 : reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10279 : : scalar_int_mode mode,
10280 : : unsigned HOST_WIDE_INT *nonzero)
10281 : : {
10282 : 448969160 : rtx tem;
10283 : 448969160 : reg_stat_type *rsp;
10284 : :
10285 : : /* If X is a register whose nonzero bits value is current, use it.
10286 : : Otherwise, if X is a register whose value we can find, use that
10287 : : value. Otherwise, use the previously-computed global nonzero bits
10288 : : for this register. */
10289 : :
10290 : 448969160 : rsp = ®_stat[REGNO (x)];
10291 : 448969160 : if (rsp->last_set_value != 0
10292 : 418007657 : && (rsp->last_set_mode == mode
10293 : 1278 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10294 : 0 : && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10295 : 0 : && GET_MODE_CLASS (mode) == MODE_INT))
10296 : 866975539 : && ((rsp->last_set_label >= label_tick_ebb_start
10297 : 317688188 : && rsp->last_set_label < label_tick)
10298 : 397941547 : || (rsp->last_set_label == label_tick
10299 : 297623356 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10300 : 131214323 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10301 : 131155667 : && REGNO (x) < reg_n_sets_max
10302 : 131155551 : && REG_N_SETS (REGNO (x)) == 1
10303 : 144517200 : && !REGNO_REG_SET_P
10304 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10305 : : REGNO (x)))))
10306 : : {
10307 : : /* Note that, even if the precision of last_set_mode is lower than that
10308 : : of mode, record_value_for_reg invoked nonzero_bits on the register
10309 : : with nonzero_bits_mode (because last_set_mode is necessarily integral
10310 : : and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10311 : : are all valid, hence in mode too since nonzero_bits_mode is defined
10312 : : to the largest HWI_COMPUTABLE_MODE_P mode. */
10313 : 358966047 : *nonzero &= rsp->last_set_nonzero_bits;
10314 : 358966047 : return NULL;
10315 : : }
10316 : :
10317 : 90003113 : tem = get_last_value (x);
10318 : 90003113 : if (tem)
10319 : : {
10320 : : if (SHORT_IMMEDIATES_SIGN_EXTEND)
10321 : : tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10322 : :
10323 : : return tem;
10324 : : }
10325 : :
10326 : 90003107 : if (nonzero_sign_valid && rsp->nonzero_bits)
10327 : : {
10328 : 56354541 : unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10329 : :
10330 : 56354541 : if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10331 : : /* We don't know anything about the upper bits. */
10332 : 0 : mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10333 : :
10334 : 56354541 : *nonzero &= mask;
10335 : : }
10336 : :
10337 : : return NULL;
10338 : : }
10339 : :
10340 : : /* Given a reg X of mode XMODE, return the number of bits at the high-order
10341 : : end of X that are known to be equal to the sign bit. X will be used
10342 : : in mode MODE; the returned value will always be between 1 and the
10343 : : number of bits in MODE. */
10344 : :
10345 : : static rtx
10346 : 129493894 : reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10347 : : scalar_int_mode mode,
10348 : : unsigned int *result)
10349 : : {
10350 : 129493894 : rtx tem;
10351 : 129493894 : reg_stat_type *rsp;
10352 : :
10353 : 129493894 : rsp = ®_stat[REGNO (x)];
10354 : 129493894 : if (rsp->last_set_value != 0
10355 : 118372765 : && rsp->last_set_mode == mode
10356 : 247866490 : && ((rsp->last_set_label >= label_tick_ebb_start
10357 : 90427571 : && rsp->last_set_label < label_tick)
10358 : 113015154 : || (rsp->last_set_label == label_tick
10359 : 85070129 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10360 : 36429830 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10361 : 36418329 : && REGNO (x) < reg_n_sets_max
10362 : 36418257 : && REG_N_SETS (REGNO (x)) == 1
10363 : 40409726 : && !REGNO_REG_SET_P
10364 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10365 : : REGNO (x)))))
10366 : : {
10367 : 102125727 : *result = rsp->last_set_sign_bit_copies;
10368 : 102125727 : return NULL;
10369 : : }
10370 : :
10371 : 27368167 : tem = get_last_value (x);
10372 : 27368167 : if (tem != 0)
10373 : : return tem;
10374 : :
10375 : 17998272 : if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10376 : 41111072 : && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10377 : 13742910 : *result = rsp->sign_bit_copies;
10378 : :
10379 : : return NULL;
10380 : : }
10381 : :
10382 : : /* Return the number of "extended" bits there are in X, when interpreted
10383 : : as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10384 : : unsigned quantities, this is the number of high-order zero bits.
10385 : : For signed quantities, this is the number of copies of the sign bit
10386 : : minus 1. In both case, this function returns the number of "spare"
10387 : : bits. For example, if two quantities for which this function returns
10388 : : at least 1 are added, the addition is known not to overflow.
10389 : :
10390 : : This function will always return 0 unless called during combine, which
10391 : : implies that it must be called from a define_split. */
10392 : :
10393 : : unsigned int
10394 : 0 : extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10395 : : {
10396 : 0 : if (nonzero_sign_valid == 0)
10397 : : return 0;
10398 : :
10399 : 0 : scalar_int_mode int_mode;
10400 : 0 : return (unsignedp
10401 : 0 : ? (is_a <scalar_int_mode> (mode, &int_mode)
10402 : 0 : && HWI_COMPUTABLE_MODE_P (int_mode)
10403 : 0 : ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10404 : 0 : - floor_log2 (nonzero_bits (x, int_mode)))
10405 : : : 0)
10406 : 0 : : num_sign_bit_copies (x, mode) - 1);
10407 : : }
10408 : :
10409 : : /* This function is called from `simplify_shift_const' to merge two
10410 : : outer operations. Specifically, we have already found that we need
10411 : : to perform operation *POP0 with constant *PCONST0 at the outermost
10412 : : position. We would now like to also perform OP1 with constant CONST1
10413 : : (with *POP0 being done last).
10414 : :
10415 : : Return true if we can do the operation and update *POP0 and *PCONST0 with
10416 : : the resulting operation. *PCOMP_P is set to true if we would need to
10417 : : complement the innermost operand, otherwise it is unchanged.
10418 : :
10419 : : MODE is the mode in which the operation will be done. No bits outside
10420 : : the width of this mode matter. It is assumed that the width of this mode
10421 : : is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10422 : :
10423 : : If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10424 : : IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10425 : : result is simply *PCONST0.
10426 : :
10427 : : If the resulting operation cannot be expressed as one operation, we
10428 : : return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10429 : :
10430 : : static bool
10431 : 3771242 : merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10432 : : enum rtx_code op1, HOST_WIDE_INT const1,
10433 : : machine_mode mode, bool *pcomp_p)
10434 : : {
10435 : 3771242 : enum rtx_code op0 = *pop0;
10436 : 3771242 : HOST_WIDE_INT const0 = *pconst0;
10437 : :
10438 : 3771242 : const0 &= GET_MODE_MASK (mode);
10439 : 3771242 : const1 &= GET_MODE_MASK (mode);
10440 : :
10441 : : /* If OP0 is an AND, clear unimportant bits in CONST1. */
10442 : 3771242 : if (op0 == AND)
10443 : 15023 : const1 &= const0;
10444 : :
10445 : : /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10446 : : if OP0 is SET. */
10447 : :
10448 : 3771242 : if (op1 == UNKNOWN || op0 == SET)
10449 : : return true;
10450 : :
10451 : 3771242 : else if (op0 == UNKNOWN)
10452 : : op0 = op1, const0 = const1;
10453 : :
10454 : 69000 : else if (op0 == op1)
10455 : : {
10456 : 14845 : switch (op0)
10457 : : {
10458 : 14840 : case AND:
10459 : 14840 : const0 &= const1;
10460 : 14840 : break;
10461 : 5 : case IOR:
10462 : 5 : const0 |= const1;
10463 : 5 : break;
10464 : 0 : case XOR:
10465 : 0 : const0 ^= const1;
10466 : 0 : break;
10467 : 0 : case PLUS:
10468 : 0 : const0 += const1;
10469 : 0 : break;
10470 : : case NEG:
10471 : 3742120 : op0 = UNKNOWN;
10472 : : break;
10473 : : default:
10474 : : break;
10475 : : }
10476 : : }
10477 : :
10478 : : /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10479 : 54155 : else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10480 : : return false;
10481 : :
10482 : : /* If the two constants aren't the same, we can't do anything. The
10483 : : remaining six cases can all be done. */
10484 : 26436 : else if (const0 != const1)
10485 : : return false;
10486 : :
10487 : : else
10488 : 25033 : switch (op0)
10489 : : {
10490 : 8 : case IOR:
10491 : 8 : if (op1 == AND)
10492 : : /* (a & b) | b == b */
10493 : 0 : op0 = SET;
10494 : : else /* op1 == XOR */
10495 : : /* (a ^ b) | b == a | b */
10496 : : {;}
10497 : : break;
10498 : :
10499 : 24846 : case XOR:
10500 : 24846 : if (op1 == AND)
10501 : : /* (a & b) ^ b == (~a) & b */
10502 : 24846 : op0 = AND, *pcomp_p = true;
10503 : : else /* op1 == IOR */
10504 : : /* (a | b) ^ b == a & ~b */
10505 : 0 : op0 = AND, const0 = ~const0;
10506 : : break;
10507 : :
10508 : 179 : case AND:
10509 : 179 : if (op1 == IOR)
10510 : : /* (a | b) & b == b */
10511 : : op0 = SET;
10512 : : else /* op1 == XOR */
10513 : : /* (a ^ b) & b) == (~a) & b */
10514 : 179 : *pcomp_p = true;
10515 : : break;
10516 : : default:
10517 : : break;
10518 : : }
10519 : :
10520 : : /* Check for NO-OP cases. */
10521 : 3742120 : const0 &= GET_MODE_MASK (mode);
10522 : 3742120 : if (const0 == 0
10523 : 19976 : && (op0 == IOR || op0 == XOR || op0 == PLUS))
10524 : : op0 = UNKNOWN;
10525 : 3739957 : else if (const0 == 0 && op0 == AND)
10526 : : op0 = SET;
10527 : 3739957 : else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10528 : 17898 : && op0 == AND)
10529 : 3742120 : op0 = UNKNOWN;
10530 : :
10531 : 3742120 : *pop0 = op0;
10532 : :
10533 : : /* ??? Slightly redundant with the above mask, but not entirely.
10534 : : Moving this above means we'd have to sign-extend the mode mask
10535 : : for the final test. */
10536 : 3742120 : if (op0 != UNKNOWN && op0 != NEG)
10537 : 3711998 : *pconst0 = trunc_int_for_mode (const0, mode);
10538 : :
10539 : : return true;
10540 : : }
10541 : :
10542 : : /* A helper to simplify_shift_const_1 to determine the mode we can perform
10543 : : the shift in. The original shift operation CODE is performed on OP in
10544 : : ORIG_MODE. Return the wider mode MODE if we can perform the operation
10545 : : in that mode. Return ORIG_MODE otherwise. We can also assume that the
10546 : : result of the shift is subject to operation OUTER_CODE with operand
10547 : : OUTER_CONST. */
10548 : :
10549 : : static scalar_int_mode
10550 : 480342 : try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10551 : : scalar_int_mode orig_mode, scalar_int_mode mode,
10552 : : enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10553 : : {
10554 : 480342 : gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10555 : :
10556 : : /* In general we can't perform in wider mode for right shift and rotate. */
10557 : 480342 : switch (code)
10558 : : {
10559 : 37971 : case ASHIFTRT:
10560 : : /* We can still widen if the bits brought in from the left are identical
10561 : : to the sign bit of ORIG_MODE. */
10562 : 37971 : if (num_sign_bit_copies (op, mode)
10563 : 37971 : > (unsigned) (GET_MODE_PRECISION (mode)
10564 : 37971 : - GET_MODE_PRECISION (orig_mode)))
10565 : 347 : return mode;
10566 : 37624 : return orig_mode;
10567 : :
10568 : 34170 : case LSHIFTRT:
10569 : : /* Similarly here but with zero bits. */
10570 : 34170 : if (HWI_COMPUTABLE_MODE_P (mode)
10571 : 34170 : && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10572 : 6289 : return mode;
10573 : :
10574 : : /* We can also widen if the bits brought in will be masked off. This
10575 : : operation is performed in ORIG_MODE. */
10576 : 27881 : if (outer_code == AND)
10577 : : {
10578 : 8482 : int care_bits = low_bitmask_len (orig_mode, outer_const);
10579 : :
10580 : 8482 : if (care_bits >= 0
10581 : 8482 : && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10582 : 8436 : return mode;
10583 : : }
10584 : : /* fall through */
10585 : :
10586 : 20109 : case ROTATE:
10587 : 20109 : return orig_mode;
10588 : :
10589 : 0 : case ROTATERT:
10590 : 0 : gcc_unreachable ();
10591 : :
10592 : 407537 : default:
10593 : 407537 : return mode;
10594 : : }
10595 : : }
10596 : :
10597 : : /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10598 : : of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10599 : : if we cannot simplify it. Otherwise, return a simplified value.
10600 : :
10601 : : The shift is normally computed in the widest mode we find in VAROP, as
10602 : : long as it isn't a different number of words than RESULT_MODE. Exceptions
10603 : : are ASHIFTRT and ROTATE, which are always done in their original mode. */
10604 : :
10605 : : static rtx
10606 : 24514543 : simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10607 : : rtx varop, int orig_count)
10608 : : {
10609 : 24514543 : enum rtx_code orig_code = code;
10610 : 24514543 : rtx orig_varop = varop;
10611 : 24514543 : int count, log2;
10612 : 24514543 : machine_mode mode = result_mode;
10613 : 24514543 : machine_mode shift_mode;
10614 : 24514543 : scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10615 : : /* We form (outer_op (code varop count) (outer_const)). */
10616 : 24514543 : enum rtx_code outer_op = UNKNOWN;
10617 : 24514543 : HOST_WIDE_INT outer_const = 0;
10618 : 24514543 : bool complement_p = false;
10619 : 24514543 : rtx new_rtx, x;
10620 : :
10621 : : /* Make sure and truncate the "natural" shift on the way in. We don't
10622 : : want to do this inside the loop as it makes it more difficult to
10623 : : combine shifts. */
10624 : 24514543 : if (SHIFT_COUNT_TRUNCATED)
10625 : : orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10626 : :
10627 : : /* If we were given an invalid count, don't do anything except exactly
10628 : : what was requested. */
10629 : :
10630 : 49028986 : if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10631 : : return NULL_RTX;
10632 : :
10633 : : count = orig_count;
10634 : :
10635 : : /* Unless one of the branches of the `if' in this loop does a `continue',
10636 : : we will `break' the loop after the `if'. */
10637 : :
10638 : 28649763 : while (count != 0)
10639 : : {
10640 : : /* If we have an operand of (clobber (const_int 0)), fail. */
10641 : 24626816 : if (GET_CODE (varop) == CLOBBER)
10642 : 24514543 : return NULL_RTX;
10643 : :
10644 : : /* Convert ROTATERT to ROTATE. */
10645 : 24626816 : if (code == ROTATERT)
10646 : : {
10647 : 10565 : unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10648 : 10565 : code = ROTATE;
10649 : 10565 : count = bitsize - count;
10650 : : }
10651 : :
10652 : 24626816 : shift_mode = result_mode;
10653 : 24626816 : if (shift_mode != mode)
10654 : : {
10655 : : /* We only change the modes of scalar shifts. */
10656 : 242424 : int_mode = as_a <scalar_int_mode> (mode);
10657 : 242424 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10658 : 242424 : shift_mode = try_widen_shift_mode (code, varop, count,
10659 : : int_result_mode, int_mode,
10660 : : outer_op, outer_const);
10661 : : }
10662 : :
10663 : 24626816 : scalar_int_mode shift_unit_mode;
10664 : 69847964 : if (!is_a <scalar_int_mode> (GET_MODE_INNER (shift_mode),
10665 : : &shift_unit_mode))
10666 : : return NULL_RTX;
10667 : :
10668 : : /* Handle cases where the count is greater than the size of the mode
10669 : : minus 1. For ASHIFT, use the size minus one as the count (this can
10670 : : occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10671 : : take the count modulo the size. For other shifts, the result is
10672 : : zero.
10673 : :
10674 : : Since these shifts are being produced by the compiler by combining
10675 : : multiple operations, each of which are defined, we know what the
10676 : : result is supposed to be. */
10677 : :
10678 : 24626816 : if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10679 : : {
10680 : 9605 : if (code == ASHIFTRT)
10681 : 9599 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10682 : 6 : else if (code == ROTATE || code == ROTATERT)
10683 : 6 : count %= GET_MODE_PRECISION (shift_unit_mode);
10684 : : else
10685 : : {
10686 : : /* We can't simply return zero because there may be an
10687 : : outer op. */
10688 : 0 : varop = const0_rtx;
10689 : 0 : count = 0;
10690 : 0 : break;
10691 : : }
10692 : : }
10693 : :
10694 : : /* If we discovered we had to complement VAROP, leave. Making a NOT
10695 : : here would cause an infinite loop. */
10696 : 24626816 : if (complement_p)
10697 : : break;
10698 : :
10699 : 24610483 : if (shift_mode == shift_unit_mode)
10700 : : {
10701 : : /* An arithmetic right shift of a quantity known to be -1 or 0
10702 : : is a no-op. */
10703 : 24047695 : if (code == ASHIFTRT
10704 : 24047695 : && (num_sign_bit_copies (varop, shift_unit_mode)
10705 : 4385372 : == GET_MODE_PRECISION (shift_unit_mode)))
10706 : : {
10707 : : count = 0;
10708 : : break;
10709 : : }
10710 : :
10711 : : /* If we are doing an arithmetic right shift and discarding all but
10712 : : the sign bit copies, this is equivalent to doing a shift by the
10713 : : bitsize minus one. Convert it into that shift because it will
10714 : : often allow other simplifications. */
10715 : :
10716 : 24047627 : if (code == ASHIFTRT
10717 : 24047627 : && (count + num_sign_bit_copies (varop, shift_unit_mode)
10718 : 4385304 : >= GET_MODE_PRECISION (shift_unit_mode)))
10719 : 316979 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10720 : :
10721 : : /* We simplify the tests below and elsewhere by converting
10722 : : ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10723 : : `make_compound_operation' will convert it to an ASHIFTRT for
10724 : : those machines (such as VAX) that don't have an LSHIFTRT. */
10725 : 24047627 : if (code == ASHIFTRT
10726 : 4385304 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10727 : 28408100 : && val_signbit_known_clear_p (shift_unit_mode,
10728 : : nonzero_bits (varop,
10729 : : shift_unit_mode)))
10730 : : code = LSHIFTRT;
10731 : :
10732 : 24022760 : if (((code == LSHIFTRT
10733 : 6039147 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10734 : 6017223 : && !(nonzero_bits (varop, shift_unit_mode) >> count))
10735 : 24046099 : || (code == ASHIFT
10736 : 13618904 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10737 : 13100324 : && !((nonzero_bits (varop, shift_unit_mode) << count)
10738 : 13100324 : & GET_MODE_MASK (shift_unit_mode))))
10739 : 24025753 : && !side_effects_p (varop))
10740 : 2993 : varop = const0_rtx;
10741 : : }
10742 : :
10743 : 24610415 : switch (GET_CODE (varop))
10744 : : {
10745 : 542535 : case SIGN_EXTEND:
10746 : 542535 : case ZERO_EXTEND:
10747 : 542535 : case SIGN_EXTRACT:
10748 : 542535 : case ZERO_EXTRACT:
10749 : 542535 : new_rtx = expand_compound_operation (varop);
10750 : 542535 : if (new_rtx != varop)
10751 : : {
10752 : 56742 : varop = new_rtx;
10753 : 28706505 : continue;
10754 : : }
10755 : : break;
10756 : :
10757 : 261604 : case MEM:
10758 : : /* The following rules apply only to scalars. */
10759 : 261604 : if (shift_mode != shift_unit_mode)
10760 : : break;
10761 : 247906 : int_mode = as_a <scalar_int_mode> (mode);
10762 : :
10763 : : /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10764 : : minus the width of a smaller mode, we can do this with a
10765 : : SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10766 : 252678 : if ((code == ASHIFTRT || code == LSHIFTRT)
10767 : 85316 : && ! mode_dependent_address_p (XEXP (varop, 0),
10768 : 85316 : MEM_ADDR_SPACE (varop))
10769 : 85316 : && ! MEM_VOLATILE_P (varop)
10770 : 331416 : && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10771 : 243134 : .exists (&tmode)))
10772 : : {
10773 : 4772 : new_rtx = adjust_address_nv (varop, tmode,
10774 : : BYTES_BIG_ENDIAN ? 0
10775 : : : count / BITS_PER_UNIT);
10776 : :
10777 : 4772 : varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10778 : : : ZERO_EXTEND, int_mode, new_rtx);
10779 : 4772 : count = 0;
10780 : 4772 : continue;
10781 : : }
10782 : : break;
10783 : :
10784 : 4816029 : case SUBREG:
10785 : : /* The following rules apply only to scalars. */
10786 : 4816029 : if (shift_mode != shift_unit_mode)
10787 : : break;
10788 : 4428858 : int_mode = as_a <scalar_int_mode> (mode);
10789 : 4428858 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10790 : :
10791 : : /* If VAROP is a SUBREG, strip it as long as the inner operand has
10792 : : the same number of words as what we've seen so far. Then store
10793 : : the widest mode in MODE. */
10794 : 4428858 : if (subreg_lowpart_p (varop)
10795 : 28928667 : && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10796 : 8809552 : && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10797 : 262191 : && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10798 : 247887 : == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10799 : 4666789 : && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10800 : : {
10801 : 237931 : varop = SUBREG_REG (varop);
10802 : 713793 : if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10803 : 237931 : mode = inner_mode;
10804 : 237931 : continue;
10805 : : }
10806 : : break;
10807 : :
10808 : 553495 : case MULT:
10809 : : /* Some machines use MULT instead of ASHIFT because MULT
10810 : : is cheaper. But it is still better on those machines to
10811 : : merge two shifts into one. */
10812 : 553495 : if (CONST_INT_P (XEXP (varop, 1))
10813 : 553495 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10814 : : {
10815 : 2 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10816 : 2 : varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10817 : : XEXP (varop, 0), log2_rtx);
10818 : 2 : continue;
10819 : 2 : }
10820 : : break;
10821 : :
10822 : 6609 : case UDIV:
10823 : : /* Similar, for when divides are cheaper. */
10824 : 6609 : if (CONST_INT_P (XEXP (varop, 1))
10825 : 6609 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10826 : : {
10827 : 9 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10828 : 9 : varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10829 : : XEXP (varop, 0), log2_rtx);
10830 : 9 : continue;
10831 : 9 : }
10832 : : break;
10833 : :
10834 : 335223 : case ASHIFTRT:
10835 : : /* If we are extracting just the sign bit of an arithmetic
10836 : : right shift, that shift is not needed. However, the sign
10837 : : bit of a wider mode may be different from what would be
10838 : : interpreted as the sign bit in a narrower mode, so, if
10839 : : the result is narrower, don't discard the shift. */
10840 : 337593 : if (code == LSHIFTRT
10841 : 14751 : && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10842 : 335223 : && (GET_MODE_UNIT_BITSIZE (result_mode)
10843 : 4766 : >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10844 : : {
10845 : 2370 : varop = XEXP (varop, 0);
10846 : 2370 : continue;
10847 : : }
10848 : :
10849 : : /* fall through */
10850 : :
10851 : 5761456 : case LSHIFTRT:
10852 : 5761456 : case ASHIFT:
10853 : 5761456 : case ROTATE:
10854 : : /* The following rules apply only to scalars. */
10855 : 5761456 : if (shift_mode != shift_unit_mode)
10856 : : break;
10857 : 5754190 : int_mode = as_a <scalar_int_mode> (mode);
10858 : 5754190 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10859 : 5754190 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10860 : :
10861 : : /* Here we have two nested shifts. The result is usually the
10862 : : AND of a new shift with a mask. We compute the result below. */
10863 : 5754190 : if (CONST_INT_P (XEXP (varop, 1))
10864 : 5733822 : && INTVAL (XEXP (varop, 1)) >= 0
10865 : 5733819 : && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10866 : 5733819 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
10867 : 11454983 : && HWI_COMPUTABLE_MODE_P (int_mode))
10868 : : {
10869 : 5700793 : enum rtx_code first_code = GET_CODE (varop);
10870 : 5700793 : unsigned int first_count = INTVAL (XEXP (varop, 1));
10871 : 5700793 : unsigned HOST_WIDE_INT mask;
10872 : 5700793 : rtx mask_rtx;
10873 : :
10874 : : /* We have one common special case. We can't do any merging if
10875 : : the inner code is an ASHIFTRT of a smaller mode. However, if
10876 : : we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10877 : : with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10878 : : we can convert it to
10879 : : (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10880 : : This simplifies certain SIGN_EXTEND operations. */
10881 : 5700793 : if (code == ASHIFT && first_code == ASHIFTRT
10882 : 5700793 : && count == (GET_MODE_PRECISION (int_result_mode)
10883 : 300998 : - GET_MODE_PRECISION (int_varop_mode)))
10884 : : {
10885 : : /* C3 has the low-order C1 bits zero. */
10886 : :
10887 : 0 : mask = GET_MODE_MASK (int_mode)
10888 : 0 : & ~((HOST_WIDE_INT_1U << first_count) - 1);
10889 : :
10890 : 0 : varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10891 : : XEXP (varop, 0), mask);
10892 : 0 : varop = simplify_shift_const (NULL_RTX, ASHIFT,
10893 : : int_result_mode, varop, count);
10894 : 0 : count = first_count;
10895 : 0 : code = ASHIFTRT;
10896 : 0 : continue;
10897 : : }
10898 : :
10899 : : /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10900 : : than C1 high-order bits equal to the sign bit, we can convert
10901 : : this to either an ASHIFT or an ASHIFTRT depending on the
10902 : : two counts.
10903 : :
10904 : : We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10905 : :
10906 : 5702251 : if (code == ASHIFTRT && first_code == ASHIFT
10907 : 2783500 : && int_varop_mode == shift_unit_mode
10908 : 8477830 : && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10909 : : > first_count))
10910 : : {
10911 : 1458 : varop = XEXP (varop, 0);
10912 : 1458 : count -= first_count;
10913 : 1458 : if (count < 0)
10914 : : {
10915 : 0 : count = -count;
10916 : 0 : code = ASHIFT;
10917 : : }
10918 : :
10919 : 1458 : continue;
10920 : : }
10921 : :
10922 : : /* There are some cases we can't do. If CODE is ASHIFTRT,
10923 : : we can only do this if FIRST_CODE is also ASHIFTRT.
10924 : :
10925 : : We can't do the case when CODE is ROTATE and FIRST_CODE is
10926 : : ASHIFTRT.
10927 : :
10928 : : If the mode of this shift is not the mode of the outer shift,
10929 : : we can't do this if either shift is a right shift or ROTATE.
10930 : :
10931 : : Finally, we can't do any of these if the mode is too wide
10932 : : unless the codes are the same.
10933 : :
10934 : : Handle the case where the shift codes are the same
10935 : : first. */
10936 : :
10937 : 5699335 : if (code == first_code)
10938 : : {
10939 : 27520 : if (int_varop_mode != int_result_mode
10940 : 27520 : && (code == ASHIFTRT || code == LSHIFTRT
10941 : 143 : || code == ROTATE))
10942 : : break;
10943 : :
10944 : 27468 : count += first_count;
10945 : 27468 : varop = XEXP (varop, 0);
10946 : 27468 : continue;
10947 : : }
10948 : :
10949 : 5671815 : if (code == ASHIFTRT
10950 : 2889728 : || (code == ROTATE && first_code == ASHIFTRT)
10951 : 2889698 : || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10952 : 8561513 : || (int_varop_mode != int_result_mode
10953 : 59662 : && (first_code == ASHIFTRT || first_code == LSHIFTRT
10954 : 59662 : || first_code == ROTATE
10955 : 10800 : || code == ROTATE)))
10956 : : break;
10957 : :
10958 : : /* To compute the mask to apply after the shift, shift the
10959 : : nonzero bits of the inner shift the same way the
10960 : : outer shift will. */
10961 : :
10962 : 2840836 : mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10963 : : int_result_mode);
10964 : 2840836 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10965 : 2840836 : mask_rtx
10966 : 2840836 : = simplify_const_binary_operation (code, int_result_mode,
10967 : : mask_rtx, count_rtx);
10968 : :
10969 : : /* Give up if we can't compute an outer operation to use. */
10970 : 2840836 : if (mask_rtx == 0
10971 : 2840836 : || !CONST_INT_P (mask_rtx)
10972 : 5681672 : || ! merge_outer_ops (&outer_op, &outer_const, AND,
10973 : : INTVAL (mask_rtx),
10974 : : int_result_mode, &complement_p))
10975 : : break;
10976 : :
10977 : : /* If the shifts are in the same direction, we add the
10978 : : counts. Otherwise, we subtract them. */
10979 : 2813143 : if ((code == ASHIFTRT || code == LSHIFTRT)
10980 : 2813143 : == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10981 : 10755 : count += first_count;
10982 : : else
10983 : 2802388 : count -= first_count;
10984 : :
10985 : : /* If COUNT is positive, the new shift is usually CODE,
10986 : : except for the two exceptions below, in which case it is
10987 : : FIRST_CODE. If the count is negative, FIRST_CODE should
10988 : : always be used */
10989 : 2813143 : if (count > 0
10990 : 584140 : && ((first_code == ROTATE && code == ASHIFT)
10991 : 583395 : || (first_code == ASHIFTRT && code == LSHIFTRT)))
10992 : : code = first_code;
10993 : 2802394 : else if (count < 0)
10994 : 280811 : code = first_code, count = -count;
10995 : :
10996 : 2813143 : varop = XEXP (varop, 0);
10997 : 2813143 : continue;
10998 : 2813143 : }
10999 : :
11000 : : /* If we have (A << B << C) for any shift, we can convert this to
11001 : : (A << C << B). This wins if A is a constant. Only try this if
11002 : : B is not a constant. */
11003 : :
11004 : 53397 : else if (GET_CODE (varop) == code
11005 : 4892 : && CONST_INT_P (XEXP (varop, 0))
11006 : 1006 : && !CONST_INT_P (XEXP (varop, 1)))
11007 : : {
11008 : : /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
11009 : : sure the result will be masked. See PR70222. */
11010 : 1006 : if (code == LSHIFTRT
11011 : 7 : && int_mode != int_result_mode
11012 : 1013 : && !merge_outer_ops (&outer_op, &outer_const, AND,
11013 : 7 : GET_MODE_MASK (int_result_mode)
11014 : 7 : >> orig_count, int_result_mode,
11015 : : &complement_p))
11016 : : break;
11017 : : /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
11018 : : up outer sign extension (often left and right shift) is
11019 : : hardly more efficient than the original. See PR70429.
11020 : : Similarly punt for rotates with different modes.
11021 : : See PR97386. */
11022 : 1006 : if ((code == ASHIFTRT || code == ROTATE)
11023 : 1006 : && int_mode != int_result_mode)
11024 : : break;
11025 : :
11026 : 992 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
11027 : 992 : rtx new_rtx = simplify_const_binary_operation (code, int_mode,
11028 : : XEXP (varop, 0),
11029 : : count_rtx);
11030 : 992 : varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
11031 : 992 : count = 0;
11032 : 992 : continue;
11033 : 992 : }
11034 : : break;
11035 : :
11036 : 56642 : case NOT:
11037 : : /* The following rules apply only to scalars. */
11038 : 56642 : if (shift_mode != shift_unit_mode)
11039 : : break;
11040 : :
11041 : : /* Make this fit the case below. */
11042 : 56640 : varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11043 : 56640 : continue;
11044 : :
11045 : 791327 : case IOR:
11046 : 791327 : case AND:
11047 : 791327 : case XOR:
11048 : : /* The following rules apply only to scalars. */
11049 : 791327 : if (shift_mode != shift_unit_mode)
11050 : : break;
11051 : 789862 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11052 : 789862 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11053 : :
11054 : : /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11055 : : with C the size of VAROP - 1 and the shift is logical if
11056 : : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11057 : : we have an (le X 0) operation. If we have an arithmetic shift
11058 : : and STORE_FLAG_VALUE is 1 or we have a logical shift with
11059 : : STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11060 : :
11061 : 238089 : if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11062 : 1974 : && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11063 : : && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11064 : 221 : && (code == LSHIFTRT || code == ASHIFTRT)
11065 : 221 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11066 : 790083 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11067 : : {
11068 : 53 : count = 0;
11069 : 53 : varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11070 : : const0_rtx);
11071 : :
11072 : 53 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11073 : 53 : varop = gen_rtx_NEG (int_varop_mode, varop);
11074 : :
11075 : 53 : continue;
11076 : : }
11077 : :
11078 : : /* If we have (shift (logical)), move the logical to the outside
11079 : : to allow it to possibly combine with another logical and the
11080 : : shift to combine with another shift. This also canonicalizes to
11081 : : what a ZERO_EXTRACT looks like. Also, some machines have
11082 : : (and (shift)) insns. */
11083 : :
11084 : 1260576 : if (CONST_INT_P (XEXP (varop, 1))
11085 : : /* We can't do this if we have (ashiftrt (xor)) and the
11086 : : constant has its sign bit set in shift_unit_mode with
11087 : : shift_unit_mode wider than result_mode. */
11088 : 472020 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11089 : 7876 : && int_result_mode != shift_unit_mode
11090 : 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11091 : : shift_unit_mode) < 0)
11092 : 472020 : && (new_rtx = simplify_const_binary_operation
11093 : 472020 : (code, int_result_mode,
11094 : 472020 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11095 : 472020 : gen_int_shift_amount (int_result_mode, count))) != 0
11096 : 472020 : && CONST_INT_P (new_rtx)
11097 : 1261829 : && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11098 : : INTVAL (new_rtx), int_result_mode,
11099 : : &complement_p))
11100 : : {
11101 : 470767 : varop = XEXP (varop, 0);
11102 : 470767 : continue;
11103 : : }
11104 : :
11105 : : /* If we can't do that, try to simplify the shift in each arm of the
11106 : : logical expression, make a new logical expression, and apply
11107 : : the inverse distributive law. This also can't be done for
11108 : : (ashiftrt (xor)) where we've widened the shift and the constant
11109 : : changes the sign bit. */
11110 : 319042 : if (CONST_INT_P (XEXP (varop, 1))
11111 : 319042 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11112 : 0 : && int_result_mode != shift_unit_mode
11113 : 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11114 : : shift_unit_mode) < 0))
11115 : : {
11116 : 1253 : rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11117 : : XEXP (varop, 0), count);
11118 : 1253 : rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11119 : : XEXP (varop, 1), count);
11120 : :
11121 : 1253 : varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11122 : : lhs, rhs);
11123 : 1253 : varop = apply_distributive_law (varop);
11124 : :
11125 : 1253 : count = 0;
11126 : 1253 : continue;
11127 : 1253 : }
11128 : : break;
11129 : :
11130 : 32624 : case EQ:
11131 : : /* The following rules apply only to scalars. */
11132 : 32624 : if (shift_mode != shift_unit_mode)
11133 : : break;
11134 : 32624 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11135 : :
11136 : : /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11137 : : says that the sign bit can be tested, FOO has mode MODE, C is
11138 : : GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11139 : : that may be nonzero. */
11140 : 32624 : if (code == LSHIFTRT
11141 : : && XEXP (varop, 1) == const0_rtx
11142 : : && GET_MODE (XEXP (varop, 0)) == int_result_mode
11143 : : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11144 : : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11145 : : && STORE_FLAG_VALUE == -1
11146 : : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11147 : : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11148 : : int_result_mode, &complement_p))
11149 : : {
11150 : : varop = XEXP (varop, 0);
11151 : : count = 0;
11152 : : continue;
11153 : : }
11154 : : break;
11155 : :
11156 : 26763 : case NEG:
11157 : : /* The following rules apply only to scalars. */
11158 : 26763 : if (shift_mode != shift_unit_mode)
11159 : : break;
11160 : 26629 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11161 : :
11162 : : /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11163 : : than the number of bits in the mode is equivalent to A. */
11164 : 26634 : if (code == LSHIFTRT
11165 : 5506 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11166 : 29245 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11167 : : {
11168 : 5 : varop = XEXP (varop, 0);
11169 : 5 : count = 0;
11170 : 5 : continue;
11171 : : }
11172 : :
11173 : : /* NEG commutes with ASHIFT since it is multiplication. Move the
11174 : : NEG outside to allow shifts to combine. */
11175 : 44437 : if (code == ASHIFT
11176 : 26624 : && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11177 : : int_result_mode, &complement_p))
11178 : : {
11179 : 17813 : varop = XEXP (varop, 0);
11180 : 17813 : continue;
11181 : : }
11182 : : break;
11183 : :
11184 : 1974002 : case PLUS:
11185 : : /* The following rules apply only to scalars. */
11186 : 1974002 : if (shift_mode != shift_unit_mode)
11187 : : break;
11188 : 1931424 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11189 : :
11190 : : /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11191 : : is one less than the number of bits in the mode is
11192 : : equivalent to (xor A 1). */
11193 : 1931424 : if (code == LSHIFTRT
11194 : 406765 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11195 : 32461 : && XEXP (varop, 1) == constm1_rtx
11196 : 14232 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11197 : 1931424 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11198 : : int_result_mode, &complement_p))
11199 : : {
11200 : 0 : count = 0;
11201 : 0 : varop = XEXP (varop, 0);
11202 : 0 : continue;
11203 : : }
11204 : :
11205 : : /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11206 : : that might be nonzero in BAR are those being shifted out and those
11207 : : bits are known zero in FOO, we can replace the PLUS with FOO.
11208 : : Similarly in the other operand order. This code occurs when
11209 : : we are computing the size of a variable-size array. */
11210 : :
11211 : 1934526 : if ((code == ASHIFTRT || code == LSHIFTRT)
11212 : 571571 : && count < HOST_BITS_PER_WIDE_INT
11213 : 571487 : && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11214 : 2075105 : && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11215 : 143681 : & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11216 : : {
11217 : 3102 : varop = XEXP (varop, 0);
11218 : 3102 : continue;
11219 : : }
11220 : 1928353 : else if ((code == ASHIFTRT || code == LSHIFTRT)
11221 : 568469 : && count < HOST_BITS_PER_WIDE_INT
11222 : 568385 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11223 : 567214 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11224 : 567214 : >> count) == 0
11225 : 1992366 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11226 : 64044 : & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11227 : : {
11228 : 31 : varop = XEXP (varop, 1);
11229 : 31 : continue;
11230 : : }
11231 : :
11232 : : /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11233 : 2359033 : if (code == ASHIFT
11234 : 1351264 : && CONST_INT_P (XEXP (varop, 1))
11235 : 430914 : && (new_rtx = simplify_const_binary_operation
11236 : 430914 : (ASHIFT, int_result_mode,
11237 : 430914 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11238 : 430914 : gen_int_shift_amount (int_result_mode, count))) != 0
11239 : 430914 : && CONST_INT_P (new_rtx)
11240 : 2359205 : && merge_outer_ops (&outer_op, &outer_const, PLUS,
11241 : : INTVAL (new_rtx), int_result_mode,
11242 : : &complement_p))
11243 : : {
11244 : 430742 : varop = XEXP (varop, 0);
11245 : 430742 : continue;
11246 : : }
11247 : :
11248 : : /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11249 : : signbit', and attempt to change the PLUS to an XOR and move it to
11250 : : the outer operation as is done above in the AND/IOR/XOR case
11251 : : leg for shift(logical). See details in logical handling above
11252 : : for reasoning in doing so. */
11253 : 1507197 : if (code == LSHIFTRT
11254 : 403712 : && CONST_INT_P (XEXP (varop, 1))
11255 : 278999 : && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11256 : 9648 : && (new_rtx = simplify_const_binary_operation
11257 : 1497549 : (code, int_result_mode,
11258 : 9648 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11259 : 9648 : gen_int_shift_amount (int_result_mode, count))) != 0
11260 : 9648 : && CONST_INT_P (new_rtx)
11261 : 1507197 : && merge_outer_ops (&outer_op, &outer_const, XOR,
11262 : : INTVAL (new_rtx), int_result_mode,
11263 : : &complement_p))
11264 : : {
11265 : 9648 : varop = XEXP (varop, 0);
11266 : 9648 : continue;
11267 : : }
11268 : :
11269 : : break;
11270 : :
11271 : 689777 : case MINUS:
11272 : : /* The following rules apply only to scalars. */
11273 : 689777 : if (shift_mode != shift_unit_mode)
11274 : : break;
11275 : 679576 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11276 : :
11277 : : /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11278 : : with C the size of VAROP - 1 and the shift is logical if
11279 : : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11280 : : we have a (gt X 0) operation. If the shift is arithmetic with
11281 : : STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11282 : : we have a (neg (gt X 0)) operation. */
11283 : :
11284 : 679576 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11285 : 679576 : && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11286 : 14682 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11287 : 44 : && (code == LSHIFTRT || code == ASHIFTRT)
11288 : 13 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11289 : 13 : && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11290 : 679576 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11291 : : {
11292 : 0 : count = 0;
11293 : 0 : varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11294 : : const0_rtx);
11295 : :
11296 : 0 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11297 : 0 : varop = gen_rtx_NEG (int_varop_mode, varop);
11298 : :
11299 : 0 : continue;
11300 : : }
11301 : : break;
11302 : :
11303 : 667 : case TRUNCATE:
11304 : : /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11305 : : if the truncate does not affect the value. */
11306 : 667 : if (code == LSHIFTRT
11307 : 509 : && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11308 : 509 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11309 : 667 : && (INTVAL (XEXP (XEXP (varop, 0), 1))
11310 : 509 : >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11311 : 1018 : - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11312 : : {
11313 : 509 : rtx varop_inner = XEXP (varop, 0);
11314 : 509 : int new_count = count + INTVAL (XEXP (varop_inner, 1));
11315 : 509 : rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11316 : 509 : new_count);
11317 : 509 : varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11318 : : XEXP (varop_inner, 0),
11319 : : new_count_rtx);
11320 : 509 : varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11321 : 509 : count = 0;
11322 : 509 : continue;
11323 : 509 : }
11324 : : break;
11325 : :
11326 : : default:
11327 : : break;
11328 : 56640 : }
11329 : :
11330 : : break;
11331 : : }
11332 : :
11333 : 24514313 : shift_mode = result_mode;
11334 : 24514313 : if (shift_mode != mode)
11335 : : {
11336 : : /* We only change the modes of scalar shifts. */
11337 : 237918 : int_mode = as_a <scalar_int_mode> (mode);
11338 : 237918 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11339 : 237918 : shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11340 : : int_mode, outer_op, outer_const);
11341 : : }
11342 : :
11343 : : /* We have now finished analyzing the shift. The result should be
11344 : : a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11345 : : OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11346 : : to the result of the shift. OUTER_CONST is the relevant constant,
11347 : : but we must turn off all bits turned off in the shift. */
11348 : :
11349 : 24514313 : if (outer_op == UNKNOWN
11350 : 20824380 : && orig_code == code && orig_count == count
11351 : 20780459 : && varop == orig_varop
11352 : 20596582 : && shift_mode == GET_MODE (varop))
11353 : : return NULL_RTX;
11354 : :
11355 : : /* Make a SUBREG if necessary. If we can't make it, fail. */
11356 : 3920211 : varop = gen_lowpart (shift_mode, varop);
11357 : 3920211 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11358 : : return NULL_RTX;
11359 : :
11360 : : /* If we have an outer operation and we just made a shift, it is
11361 : : possible that we could have simplified the shift were it not
11362 : : for the outer operation. So try to do the simplification
11363 : : recursively. */
11364 : :
11365 : 3920211 : if (outer_op != UNKNOWN)
11366 : 3689933 : x = simplify_shift_const_1 (code, shift_mode, varop, count);
11367 : : else
11368 : : x = NULL_RTX;
11369 : :
11370 : 3689933 : if (x == NULL_RTX)
11371 : 3881105 : x = simplify_gen_binary (code, shift_mode, varop,
11372 : 3881105 : gen_int_shift_amount (shift_mode, count));
11373 : :
11374 : : /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11375 : : turn off all the bits that the shift would have turned off. */
11376 : 3920211 : if (orig_code == LSHIFTRT && result_mode != shift_mode)
11377 : : /* We only change the modes of scalar shifts. */
11378 : 11689 : x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11379 : 11689 : x, GET_MODE_MASK (result_mode) >> orig_count);
11380 : :
11381 : : /* Do the remainder of the processing in RESULT_MODE. */
11382 : 3920211 : x = gen_lowpart_or_truncate (result_mode, x);
11383 : :
11384 : : /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11385 : : operation. */
11386 : 3920211 : if (complement_p)
11387 : 25025 : x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11388 : :
11389 : 3920211 : if (outer_op != UNKNOWN)
11390 : : {
11391 : 3689933 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11392 : :
11393 : 3689933 : if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11394 : 3689933 : && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11395 : 1308531 : outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11396 : :
11397 : 3689933 : if (outer_op == AND)
11398 : 3169467 : x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11399 : 520466 : else if (outer_op == SET)
11400 : : {
11401 : : /* This means that we have determined that the result is
11402 : : equivalent to a constant. This should be rare. */
11403 : 0 : if (!side_effects_p (x))
11404 : 0 : x = GEN_INT (outer_const);
11405 : : }
11406 : 520466 : else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11407 : 17813 : x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11408 : : else
11409 : 502653 : x = simplify_gen_binary (outer_op, int_result_mode, x,
11410 : : GEN_INT (outer_const));
11411 : : }
11412 : :
11413 : : return x;
11414 : : }
11415 : :
11416 : : /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11417 : : The result of the shift is RESULT_MODE. If we cannot simplify it,
11418 : : return X or, if it is NULL, synthesize the expression with
11419 : : simplify_gen_binary. Otherwise, return a simplified value.
11420 : :
11421 : : The shift is normally computed in the widest mode we find in VAROP, as
11422 : : long as it isn't a different number of words than RESULT_MODE. Exceptions
11423 : : are ASHIFTRT and ROTATE, which are always done in their original mode. */
11424 : :
11425 : : static rtx
11426 : 20824610 : simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11427 : : rtx varop, int count)
11428 : : {
11429 : 20824610 : rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11430 : 20824610 : if (tem)
11431 : : return tem;
11432 : :
11433 : 16943505 : if (!x)
11434 : 4943021 : x = simplify_gen_binary (code, GET_MODE (varop), varop,
11435 : 4943021 : gen_int_shift_amount (GET_MODE (varop), count));
11436 : 16943505 : if (GET_MODE (x) != result_mode)
11437 : 0 : x = gen_lowpart (result_mode, x);
11438 : : return x;
11439 : : }
11440 : :
11441 : :
11442 : : /* A subroutine of recog_for_combine. See there for arguments and
11443 : : return value. */
11444 : :
11445 : : static int
11446 : 48113495 : recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11447 : : unsigned old_nregs, unsigned new_nregs)
11448 : : {
11449 : 48113495 : rtx pat = *pnewpat;
11450 : 48113495 : rtx pat_without_clobbers;
11451 : 48113495 : int insn_code_number;
11452 : 48113495 : int num_clobbers_to_add = 0;
11453 : 48113495 : int i;
11454 : 48113495 : rtx notes = NULL_RTX;
11455 : 48113495 : rtx old_notes, old_pat;
11456 : 48113495 : int old_icode;
11457 : :
11458 : : /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11459 : : we use to indicate that something didn't match. If we find such a
11460 : : thing, force rejection. */
11461 : 48113495 : if (GET_CODE (pat) == PARALLEL)
11462 : 52219533 : for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11463 : 36010303 : if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11464 : 7613726 : && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11465 : : return -1;
11466 : :
11467 : 48111513 : old_pat = PATTERN (insn);
11468 : 48111513 : old_notes = REG_NOTES (insn);
11469 : 48111513 : PATTERN (insn) = pat;
11470 : 48111513 : REG_NOTES (insn) = NULL_RTX;
11471 : :
11472 : 48111513 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11473 : 48111513 : if (dump_file && (dump_flags & TDF_DETAILS))
11474 : : {
11475 : 277 : if (insn_code_number < 0)
11476 : 177 : fputs ("Failed to match this instruction:\n", dump_file);
11477 : : else
11478 : 100 : fputs ("Successfully matched this instruction:\n", dump_file);
11479 : 277 : print_rtl_single (dump_file, pat);
11480 : : }
11481 : :
11482 : : /* If it isn't, there is the possibility that we previously had an insn
11483 : : that clobbered some register as a side effect, but the combined
11484 : : insn doesn't need to do that. So try once more without the clobbers
11485 : : unless this represents an ASM insn. */
11486 : :
11487 : 38431455 : if (insn_code_number < 0 && ! check_asm_operands (pat)
11488 : 86541496 : && GET_CODE (pat) == PARALLEL)
11489 : : {
11490 : : int pos;
11491 : :
11492 : 50808225 : for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11493 : 35052599 : if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11494 : : {
11495 : 27826844 : if (i != pos)
11496 : 2335533 : SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11497 : 27826844 : pos++;
11498 : : }
11499 : :
11500 : 15755626 : SUBST_INT (XVECLEN (pat, 0), pos);
11501 : :
11502 : 15755626 : if (pos == 1)
11503 : 4916344 : pat = XVECEXP (pat, 0, 0);
11504 : :
11505 : 15755626 : PATTERN (insn) = pat;
11506 : 15755626 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11507 : 15755626 : if (dump_file && (dump_flags & TDF_DETAILS))
11508 : : {
11509 : 82 : if (insn_code_number < 0)
11510 : 81 : fputs ("Failed to match this instruction:\n", dump_file);
11511 : : else
11512 : 1 : fputs ("Successfully matched this instruction:\n", dump_file);
11513 : 82 : print_rtl_single (dump_file, pat);
11514 : : }
11515 : : }
11516 : :
11517 : 48111513 : pat_without_clobbers = pat;
11518 : :
11519 : 48111513 : PATTERN (insn) = old_pat;
11520 : 48111513 : REG_NOTES (insn) = old_notes;
11521 : :
11522 : : /* Recognize all noop sets, these will be killed by followup pass. */
11523 : 48111513 : if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11524 : 202846 : insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11525 : :
11526 : : /* If we had any clobbers to add, make a new pattern than contains
11527 : : them. Then check to make sure that all of them are dead. */
11528 : 48111513 : if (num_clobbers_to_add)
11529 : : {
11530 : 1701731 : rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11531 : : rtvec_alloc (GET_CODE (pat) == PARALLEL
11532 : : ? (XVECLEN (pat, 0)
11533 : : + num_clobbers_to_add)
11534 : : : num_clobbers_to_add + 1));
11535 : :
11536 : 1701731 : if (GET_CODE (pat) == PARALLEL)
11537 : 1395 : for (i = 0; i < XVECLEN (pat, 0); i++)
11538 : 930 : XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11539 : : else
11540 : 1701266 : XVECEXP (newpat, 0, 0) = pat;
11541 : :
11542 : 1701731 : add_clobbers (newpat, insn_code_number);
11543 : :
11544 : 3297860 : for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11545 : 3297860 : i < XVECLEN (newpat, 0); i++)
11546 : : {
11547 : 1731306 : if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11548 : 1731306 : && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11549 : : return -1;
11550 : 1596129 : if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11551 : : {
11552 : 1542593 : gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11553 : 1542593 : notes = alloc_reg_note (REG_UNUSED,
11554 : : XEXP (XVECEXP (newpat, 0, i), 0), notes);
11555 : : }
11556 : : }
11557 : : pat = newpat;
11558 : : }
11559 : :
11560 : 47976336 : if (insn_code_number >= 0
11561 : 47976336 : && insn_code_number != NOOP_MOVE_INSN_CODE)
11562 : : {
11563 : : /* Create the reg dead notes if needed for the regs that were created via split. */
11564 : 9879491 : for (; old_nregs < new_nregs; old_nregs++)
11565 : 4683 : notes = alloc_reg_note (REG_DEAD, regno_reg_rtx[old_nregs], notes);
11566 : 9874808 : old_pat = PATTERN (insn);
11567 : 9874808 : old_notes = REG_NOTES (insn);
11568 : 9874808 : old_icode = INSN_CODE (insn);
11569 : 9874808 : PATTERN (insn) = pat;
11570 : 9874808 : REG_NOTES (insn) = notes;
11571 : 9874808 : INSN_CODE (insn) = insn_code_number;
11572 : :
11573 : : /* Allow targets to reject combined insn. */
11574 : 9874808 : if (!targetm.legitimate_combined_insn (insn))
11575 : : {
11576 : 3485 : if (dump_file && (dump_flags & TDF_DETAILS))
11577 : 0 : fputs ("Instruction not appropriate for target.",
11578 : : dump_file);
11579 : :
11580 : : /* Callers expect recog_for_combine to strip
11581 : : clobbers from the pattern on failure. */
11582 : : pat = pat_without_clobbers;
11583 : : notes = NULL_RTX;
11584 : :
11585 : : insn_code_number = -1;
11586 : : }
11587 : :
11588 : 9874808 : PATTERN (insn) = old_pat;
11589 : 9874808 : REG_NOTES (insn) = old_notes;
11590 : 9874808 : INSN_CODE (insn) = old_icode;
11591 : : }
11592 : :
11593 : 47976336 : *pnewpat = pat;
11594 : 47976336 : *pnotes = notes;
11595 : :
11596 : 47976336 : return insn_code_number;
11597 : : }
11598 : :
11599 : : /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11600 : : expressed as an AND and maybe an LSHIFTRT, to that formulation.
11601 : : Return whether anything was so changed. */
11602 : :
11603 : : static bool
11604 : 48068754 : change_zero_ext (rtx pat)
11605 : : {
11606 : 48068754 : bool changed = false;
11607 : 48068754 : rtx *src = &SET_SRC (pat);
11608 : :
11609 : 48068754 : subrtx_ptr_iterator::array_type array;
11610 : 329892853 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11611 : : {
11612 : 281824099 : rtx x = **iter;
11613 : 281824099 : scalar_int_mode mode, inner_mode;
11614 : 281824099 : if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11615 : 411967386 : continue;
11616 : 151680812 : int size;
11617 : :
11618 : 151680812 : if (GET_CODE (x) == ZERO_EXTRACT
11619 : 834153 : && CONST_INT_P (XEXP (x, 1))
11620 : 834133 : && CONST_INT_P (XEXP (x, 2))
11621 : 786636 : && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11622 : 152467448 : && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11623 : : {
11624 : 786628 : size = INTVAL (XEXP (x, 1));
11625 : :
11626 : 786628 : int start = INTVAL (XEXP (x, 2));
11627 : 786628 : if (BITS_BIG_ENDIAN)
11628 : : start = GET_MODE_PRECISION (inner_mode) - size - start;
11629 : :
11630 : 786628 : if (start != 0)
11631 : 680250 : x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11632 : : gen_int_shift_amount (inner_mode, start));
11633 : : else
11634 : : x = XEXP (x, 0);
11635 : :
11636 : 786628 : if (mode != inner_mode)
11637 : : {
11638 : 143 : if (REG_P (x) && HARD_REGISTER_P (x)
11639 : 194075 : && !can_change_dest_mode (x, 0, mode))
11640 : 0 : continue;
11641 : :
11642 : 194075 : x = gen_lowpart_SUBREG (mode, x);
11643 : : }
11644 : : }
11645 : 150894184 : else if (GET_CODE (x) == ZERO_EXTEND
11646 : 2332213 : && GET_CODE (XEXP (x, 0)) == SUBREG
11647 : 346280 : && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11648 : 345179 : && !paradoxical_subreg_p (XEXP (x, 0))
11649 : 151239363 : && subreg_lowpart_p (XEXP (x, 0)))
11650 : : {
11651 : 227330 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11652 : 227330 : size = GET_MODE_PRECISION (inner_mode);
11653 : 227330 : x = SUBREG_REG (XEXP (x, 0));
11654 : 227330 : if (GET_MODE (x) != mode)
11655 : : {
11656 : 16082 : if (REG_P (x) && HARD_REGISTER_P (x)
11657 : 16432 : && !can_change_dest_mode (x, 0, mode))
11658 : 0 : continue;
11659 : :
11660 : 16432 : x = gen_lowpart_SUBREG (mode, x);
11661 : : }
11662 : : }
11663 : 301333628 : else if (GET_CODE (x) == ZERO_EXTEND
11664 : 2104883 : && REG_P (XEXP (x, 0))
11665 : 1109898 : && HARD_REGISTER_P (XEXP (x, 0))
11666 : 150666934 : && can_change_dest_mode (XEXP (x, 0), 0, mode))
11667 : : {
11668 : 80 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11669 : 80 : size = GET_MODE_PRECISION (inner_mode);
11670 : 80 : x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11671 : : }
11672 : : else
11673 : 150666774 : continue;
11674 : :
11675 : 1527396 : if (!(GET_CODE (x) == LSHIFTRT
11676 : 513358 : && CONST_INT_P (XEXP (x, 1))
11677 : 513358 : && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11678 : : {
11679 : 763962 : wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11680 : 763962 : x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11681 : 763962 : }
11682 : :
11683 : 1014038 : SUBST (**iter, x);
11684 : 1014038 : changed = true;
11685 : : }
11686 : :
11687 : 48068754 : if (changed)
11688 : 9167618 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11689 : 8171442 : maybe_swap_commutative_operands (**iter);
11690 : :
11691 : 48068754 : rtx *dst = &SET_DEST (pat);
11692 : 48068754 : scalar_int_mode mode;
11693 : 48068754 : if (GET_CODE (*dst) == ZERO_EXTRACT
11694 : 9854 : && REG_P (XEXP (*dst, 0))
11695 : 426 : && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11696 : 426 : && CONST_INT_P (XEXP (*dst, 1))
11697 : 48069180 : && CONST_INT_P (XEXP (*dst, 2)))
11698 : : {
11699 : 261 : rtx reg = XEXP (*dst, 0);
11700 : 261 : int width = INTVAL (XEXP (*dst, 1));
11701 : 261 : int offset = INTVAL (XEXP (*dst, 2));
11702 : 261 : int reg_width = GET_MODE_PRECISION (mode);
11703 : 261 : if (BITS_BIG_ENDIAN)
11704 : : offset = reg_width - width - offset;
11705 : :
11706 : 261 : rtx x, y, z, w;
11707 : 261 : wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11708 : 261 : wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11709 : 261 : x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11710 : 261 : if (offset)
11711 : 207 : y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11712 : : else
11713 : 54 : y = SET_SRC (pat);
11714 : 261 : z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11715 : 261 : w = gen_rtx_IOR (mode, x, z);
11716 : 261 : SUBST (SET_DEST (pat), reg);
11717 : 261 : SUBST (SET_SRC (pat), w);
11718 : :
11719 : 261 : changed = true;
11720 : 261 : }
11721 : :
11722 : 48068754 : return changed;
11723 : 48068754 : }
11724 : :
11725 : : /* Like recog, but we receive the address of a pointer to a new pattern.
11726 : : We try to match the rtx that the pointer points to.
11727 : : If that fails, we may try to modify or replace the pattern,
11728 : : storing the replacement into the same pointer object.
11729 : :
11730 : : Modifications include deletion or addition of CLOBBERs. If the
11731 : : instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11732 : : to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11733 : : (and undo if that fails).
11734 : :
11735 : : PNOTES is a pointer to a location where any REG_UNUSED notes added for
11736 : : the CLOBBERs are placed.
11737 : : If OLD_NREGS != NEW_NREGS, then PNOTES also includes REG_DEAD notes added.
11738 : :
11739 : : The value is the final insn code from the pattern ultimately matched,
11740 : : or -1. */
11741 : :
11742 : : static int
11743 : 46849248 : recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11744 : : unsigned int old_nregs, unsigned int new_nregs)
11745 : : {
11746 : 46849248 : rtx pat = *pnewpat;
11747 : 46849248 : int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11748 : : old_nregs, new_nregs);
11749 : 46849248 : if (insn_code_number >= 0 || check_asm_operands (pat))
11750 : 9910395 : return insn_code_number;
11751 : :
11752 : 36938853 : void *marker = get_undo_marker ();
11753 : 36938853 : bool changed = false;
11754 : :
11755 : 36938853 : if (GET_CODE (pat) == SET)
11756 : : {
11757 : : /* For an unrecognized single set of a constant, try placing it in
11758 : : the constant pool, if this function already uses one. */
11759 : 21712949 : rtx src = SET_SRC (pat);
11760 : 21712949 : if (CONSTANT_P (src)
11761 : 453813 : && !CONST_INT_P (src)
11762 : 406639 : && crtl->uses_const_pool)
11763 : : {
11764 : 357778 : machine_mode mode = GET_MODE (src);
11765 : 357778 : if (mode == VOIDmode)
11766 : 1195 : mode = GET_MODE (SET_DEST (pat));
11767 : 357778 : src = force_const_mem (mode, src);
11768 : 357778 : if (src)
11769 : : {
11770 : 357776 : SUBST (SET_SRC (pat), src);
11771 : 357776 : changed = true;
11772 : : }
11773 : : }
11774 : : else
11775 : 21355171 : changed = change_zero_ext (pat);
11776 : : }
11777 : 15225904 : else if (GET_CODE (pat) == PARALLEL)
11778 : : {
11779 : : int i;
11780 : 42220067 : for (i = 0; i < XVECLEN (pat, 0); i++)
11781 : : {
11782 : 27020847 : rtx set = XVECEXP (pat, 0, i);
11783 : 27020847 : if (GET_CODE (set) == SET)
11784 : 26713583 : changed |= change_zero_ext (set);
11785 : : }
11786 : : }
11787 : :
11788 : 36912167 : if (changed)
11789 : : {
11790 : 1264247 : insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11791 : : old_nregs, new_nregs);
11792 : :
11793 : 1264247 : if (insn_code_number < 0)
11794 : 1099001 : undo_to_marker (marker);
11795 : : }
11796 : :
11797 : : return insn_code_number;
11798 : : }
11799 : :
11800 : : /* Like gen_lowpart_general but for use by combine. In combine it
11801 : : is not possible to create any new pseudoregs. However, it is
11802 : : safe to create invalid memory addresses, because combine will
11803 : : try to recognize them and all they will do is make the combine
11804 : : attempt fail.
11805 : :
11806 : : If for some reason this cannot do its job, an rtx
11807 : : (clobber (const_int 0)) is returned.
11808 : : An insn containing that will not be recognized. */
11809 : :
11810 : : static rtx
11811 : 161224627 : gen_lowpart_for_combine (machine_mode omode, rtx x)
11812 : : {
11813 : 161224627 : machine_mode imode = GET_MODE (x);
11814 : 161224627 : rtx result;
11815 : :
11816 : 161224627 : if (omode == imode)
11817 : : return x;
11818 : :
11819 : : /* We can only support MODE being wider than a word if X is a
11820 : : constant integer or has a mode the same size. */
11821 : 56239407 : if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11822 : 26845118 : && ! (CONST_SCALAR_INT_P (x)
11823 : 10182938 : || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11824 : 3218407 : goto fail;
11825 : :
11826 : : /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11827 : : won't know what to do. So we will strip off the SUBREG here and
11828 : : process normally. */
11829 : 23626711 : if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11830 : : {
11831 : 14124 : x = SUBREG_REG (x);
11832 : :
11833 : : /* For use in case we fall down into the address adjustments
11834 : : further below, we need to adjust the known mode and size of
11835 : : x; imode and isize, since we just adjusted x. */
11836 : 14124 : imode = GET_MODE (x);
11837 : :
11838 : 14124 : if (imode == omode)
11839 : : return x;
11840 : : }
11841 : :
11842 : 23619040 : result = gen_lowpart_common (omode, x);
11843 : :
11844 : 23619040 : if (result)
11845 : : return result;
11846 : :
11847 : 9223262 : if (MEM_P (x))
11848 : : {
11849 : : /* Refuse to work on a volatile memory ref or one with a mode-dependent
11850 : : address. */
11851 : 2002411 : if (MEM_VOLATILE_P (x)
11852 : 3966202 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11853 : 38650 : goto fail;
11854 : :
11855 : : /* If we want to refer to something bigger than the original memref,
11856 : : generate a paradoxical subreg instead. That will force a reload
11857 : : of the original memref X. */
11858 : 1963761 : if (paradoxical_subreg_p (omode, imode))
11859 : 1759807 : return gen_rtx_SUBREG (omode, x, 0);
11860 : :
11861 : 203954 : poly_int64 offset = byte_lowpart_offset (omode, imode);
11862 : 203954 : return adjust_address_nv (x, omode, offset);
11863 : : }
11864 : :
11865 : : /* If X is a comparison operator, rewrite it in a new mode. This
11866 : : probably won't match, but may allow further simplifications. */
11867 : 7220851 : else if (COMPARISON_P (x)
11868 : 136677 : && SCALAR_INT_MODE_P (imode)
11869 : 56285 : && SCALAR_INT_MODE_P (omode))
11870 : 56274 : return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11871 : :
11872 : : /* If we couldn't simplify X any other way, just enclose it in a
11873 : : SUBREG. Normally, this SUBREG won't match, but some patterns may
11874 : : include an explicit SUBREG or we may simplify it further in combine. */
11875 : : else
11876 : : {
11877 : 7164577 : rtx res;
11878 : :
11879 : 7164577 : if (imode == VOIDmode)
11880 : : {
11881 : 4 : imode = int_mode_for_mode (omode).require ();
11882 : 4 : x = gen_lowpart_common (imode, x);
11883 : 4 : if (x == NULL)
11884 : 0 : goto fail;
11885 : : }
11886 : 7164577 : res = lowpart_subreg (omode, x, imode);
11887 : 7164577 : if (res)
11888 : : return res;
11889 : : }
11890 : :
11891 : 17710 : fail:
11892 : 3274767 : return gen_rtx_CLOBBER (omode, const0_rtx);
11893 : : }
11894 : :
11895 : : /* Like gen_lowpart_for_combine but returns NULL_RTX
11896 : : for an error instead of CLOBBER.
11897 : : Note no_emit is not called directly from combine but rather from
11898 : : simplify_rtx and is expecting a NULL on failure rather than
11899 : : a CLOBBER. */
11900 : :
11901 : : static rtx
11902 : 1191010 : gen_lowpart_for_combine_no_emit (machine_mode omode, rtx x)
11903 : : {
11904 : 1191010 : rtx tem = gen_lowpart_for_combine (omode, x);
11905 : 1191010 : if (!tem || GET_CODE (tem) == CLOBBER)
11906 : 14419 : return NULL_RTX;
11907 : : return tem;
11908 : : }
11909 : :
11910 : :
11911 : : /* Try to simplify a comparison between OP0 and a constant OP1,
11912 : : where CODE is the comparison code that will be tested, into a
11913 : : (CODE OP0 const0_rtx) form.
11914 : :
11915 : : The result is a possibly different comparison code to use.
11916 : : *POP0 and *POP1 may be updated. */
11917 : :
11918 : : static enum rtx_code
11919 : 14879674 : simplify_compare_const (enum rtx_code code, machine_mode mode,
11920 : : rtx *pop0, rtx *pop1)
11921 : : {
11922 : 14879674 : scalar_int_mode int_mode;
11923 : 14879674 : rtx op0 = *pop0;
11924 : 14879674 : HOST_WIDE_INT const_op = INTVAL (*pop1);
11925 : :
11926 : : /* Get the constant we are comparing against and turn off all bits
11927 : : not on in our mode. */
11928 : 14879674 : if (mode != VOIDmode)
11929 : 14638854 : const_op = trunc_int_for_mode (const_op, mode);
11930 : :
11931 : : /* If we are comparing against a constant power of two and the value
11932 : : being compared can only have that single bit nonzero (e.g., it was
11933 : : `and'ed with that bit), we can replace this with a comparison
11934 : : with zero. */
11935 : 14879674 : if (const_op
11936 : 4021380 : && (code == EQ || code == NE || code == GEU || code == LTU
11937 : : /* This optimization is incorrect for signed >= INT_MIN or
11938 : : < INT_MIN, those are always true or always false. */
11939 : 23056 : || ((code == GE || code == LT) && const_op > 0))
11940 : 2754678 : && is_a <scalar_int_mode> (mode, &int_mode)
11941 : 2754678 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11942 : 2734565 : && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11943 : 15806520 : && (nonzero_bits (op0, int_mode)
11944 : 926846 : == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11945 : : {
11946 : 4851 : code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11947 : : const_op = 0;
11948 : : }
11949 : :
11950 : : /* Similarly, if we are comparing a value known to be either -1 or
11951 : : 0 with -1, change it to the opposite comparison against zero. */
11952 : 14874823 : if (const_op == -1
11953 : 242612 : && (code == EQ || code == NE || code == GT || code == LE
11954 : : || code == GEU || code == LTU)
11955 : 15107204 : && is_a <scalar_int_mode> (mode, &int_mode)
11956 : 15115000 : && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11957 : : {
11958 : 13850 : code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11959 : : const_op = 0;
11960 : : }
11961 : :
11962 : : /* Do some canonicalizations based on the comparison code. We prefer
11963 : : comparisons against zero and then prefer equality comparisons.
11964 : : If we can reduce the size of a constant, we will do that too. */
11965 : 14867027 : switch (code)
11966 : : {
11967 : 263189 : case LT:
11968 : : /* < C is equivalent to <= (C - 1) */
11969 : 263189 : if (const_op > 0)
11970 : : {
11971 : 4438 : const_op -= 1;
11972 : 4438 : code = LE;
11973 : : /* ... fall through to LE case below. */
11974 : 335831 : gcc_fallthrough ();
11975 : : }
11976 : : else
11977 : : break;
11978 : :
11979 : 335831 : case LE:
11980 : : /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11981 : 335831 : if (const_op < 0)
11982 : : {
11983 : 42 : const_op += 1;
11984 : 42 : code = LT;
11985 : : }
11986 : :
11987 : : /* If we are doing a <= 0 comparison on a value known to have
11988 : : a zero sign bit, we can replace this with == 0. */
11989 : 335789 : else if (const_op == 0
11990 : 207186 : && is_a <scalar_int_mode> (mode, &int_mode)
11991 : 207186 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11992 : 542975 : && (nonzero_bits (op0, int_mode)
11993 : 207186 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11994 : 207186 : == 0)
11995 : : code = EQ;
11996 : : break;
11997 : :
11998 : 241163 : case GE:
11999 : : /* >= C is equivalent to > (C - 1). */
12000 : 241163 : if (const_op > 0)
12001 : : {
12002 : 2011 : const_op -= 1;
12003 : 2011 : code = GT;
12004 : : /* ... fall through to GT below. */
12005 : 270873 : gcc_fallthrough ();
12006 : : }
12007 : : else
12008 : : break;
12009 : :
12010 : 270873 : case GT:
12011 : : /* > C is equivalent to >= (C + 1); we do this for C < 0. */
12012 : 270873 : if (const_op < 0)
12013 : : {
12014 : 133 : const_op += 1;
12015 : 133 : code = GE;
12016 : : }
12017 : :
12018 : : /* If we are doing a > 0 comparison on a value known to have
12019 : : a zero sign bit, we can replace this with != 0. */
12020 : 270740 : else if (const_op == 0
12021 : 142177 : && is_a <scalar_int_mode> (mode, &int_mode)
12022 : 142177 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12023 : 412917 : && (nonzero_bits (op0, int_mode)
12024 : 142177 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12025 : 142177 : == 0)
12026 : : code = NE;
12027 : : break;
12028 : :
12029 : 77455 : case LTU:
12030 : : /* < C is equivalent to <= (C - 1). */
12031 : 77455 : if (const_op > 0)
12032 : : {
12033 : 67768 : const_op -= 1;
12034 : 67768 : code = LEU;
12035 : : /* ... fall through ... */
12036 : 67768 : gcc_fallthrough ();
12037 : : }
12038 : : /* (unsigned) < 0x80000000 is equivalent to >= 0. */
12039 : 9687 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12040 : 9687 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12041 : 8917 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12042 : 8917 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12043 : : {
12044 : : const_op = 0;
12045 : : code = GE;
12046 : : break;
12047 : : }
12048 : : else
12049 : : break;
12050 : :
12051 : 606265 : case LEU:
12052 : : /* unsigned <= 0 is equivalent to == 0 */
12053 : 606265 : if (const_op == 0)
12054 : : code = EQ;
12055 : : /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12056 : 605963 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12057 : 605963 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12058 : 604022 : && ((unsigned HOST_WIDE_INT) const_op
12059 : : == ((HOST_WIDE_INT_1U
12060 : 604022 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12061 : : {
12062 : : const_op = 0;
12063 : : code = GE;
12064 : : }
12065 : : break;
12066 : :
12067 : 23175 : case GEU:
12068 : : /* >= C is equivalent to > (C - 1). */
12069 : 23175 : if (const_op > 1)
12070 : : {
12071 : 14379 : const_op -= 1;
12072 : 14379 : code = GTU;
12073 : : /* ... fall through ... */
12074 : 14379 : gcc_fallthrough ();
12075 : : }
12076 : :
12077 : : /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12078 : 8796 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12079 : 8796 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12080 : 7605 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12081 : 7605 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12082 : : {
12083 : : const_op = 0;
12084 : : code = LT;
12085 : : break;
12086 : : }
12087 : : else
12088 : : break;
12089 : :
12090 : 475085 : case GTU:
12091 : : /* unsigned > 0 is equivalent to != 0 */
12092 : 475085 : if (const_op == 0)
12093 : : code = NE;
12094 : : /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12095 : 475085 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12096 : 475085 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12097 : 474072 : && ((unsigned HOST_WIDE_INT) const_op
12098 : : == (HOST_WIDE_INT_1U
12099 : 474072 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12100 : : {
12101 : : const_op = 0;
12102 : : code = LT;
12103 : : }
12104 : : break;
12105 : :
12106 : : default:
12107 : : break;
12108 : : }
12109 : :
12110 : : /* Narrow non-symmetric comparison of memory and constant as e.g.
12111 : : x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12112 : : significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
12113 : : x0 >= 0x40. */
12114 : 14256167 : if ((code == LEU || code == LTU || code == GEU || code == GTU)
12115 : 1096218 : && is_a <scalar_int_mode> (GET_MODE (op0), &int_mode)
12116 : 1096198 : && HWI_COMPUTABLE_MODE_P (int_mode)
12117 : 1091283 : && MEM_P (op0)
12118 : 79554 : && !MEM_VOLATILE_P (op0)
12119 : : /* The optimization makes only sense for constants which are big enough
12120 : : so that we have a chance to chop off something at all. */
12121 : 78879 : && ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12122 : : /* Ensure that we do not overflow during normalization. */
12123 : 26491 : && (code != GTU
12124 : 2373 : || ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12125 : : < HOST_WIDE_INT_M1U)
12126 : 14906165 : && trunc_int_for_mode (const_op, int_mode) == const_op)
12127 : : {
12128 : 26491 : unsigned HOST_WIDE_INT n
12129 : 26491 : = (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12130 : 26491 : enum rtx_code adjusted_code;
12131 : :
12132 : : /* Normalize code to either LEU or GEU. */
12133 : 26491 : if (code == LTU)
12134 : : {
12135 : 335 : --n;
12136 : 335 : adjusted_code = LEU;
12137 : : }
12138 : 26156 : else if (code == GTU)
12139 : : {
12140 : 2373 : ++n;
12141 : 2373 : adjusted_code = GEU;
12142 : : }
12143 : : else
12144 : : adjusted_code = code;
12145 : :
12146 : 26491 : scalar_int_mode narrow_mode_iter;
12147 : 81898 : FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12148 : : {
12149 : 56011 : unsigned nbits = GET_MODE_PRECISION (int_mode)
12150 : 56011 : - GET_MODE_PRECISION (narrow_mode_iter);
12151 : 56011 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12152 : 56011 : unsigned HOST_WIDE_INT lower_bits = n & mask;
12153 : 56011 : if ((adjusted_code == LEU && lower_bits == mask)
12154 : 55777 : || (adjusted_code == GEU && lower_bits == 0))
12155 : : {
12156 : 604 : n >>= nbits;
12157 : 604 : break;
12158 : : }
12159 : : }
12160 : :
12161 : 26491 : if (narrow_mode_iter < int_mode)
12162 : : {
12163 : 604 : if (dump_file && (dump_flags & TDF_DETAILS))
12164 : : {
12165 : 12 : fprintf (
12166 : : dump_file, "narrow comparison from mode %s to %s: (MEM %s "
12167 : : HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12168 : 12 : HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12169 : 12 : GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12170 : 12 : (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12171 : 12 : GET_RTX_NAME (adjusted_code), n);
12172 : : }
12173 : 604 : poly_int64 offset = (BYTES_BIG_ENDIAN
12174 : 604 : ? 0
12175 : 604 : : (GET_MODE_SIZE (int_mode)
12176 : 604 : - GET_MODE_SIZE (narrow_mode_iter)));
12177 : 604 : *pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12178 : 604 : *pop1 = gen_int_mode (n, narrow_mode_iter);
12179 : 604 : return adjusted_code;
12180 : : }
12181 : : }
12182 : :
12183 : 14879070 : *pop1 = GEN_INT (const_op);
12184 : 14879070 : return code;
12185 : : }
12186 : :
12187 : : /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12188 : : comparison code that will be tested.
12189 : :
12190 : : The result is a possibly different comparison code to use. *POP0 and
12191 : : *POP1 may be updated.
12192 : :
12193 : : It is possible that we might detect that a comparison is either always
12194 : : true or always false. However, we do not perform general constant
12195 : : folding in combine, so this knowledge isn't useful. Such tautologies
12196 : : should have been detected earlier. Hence we ignore all such cases. */
12197 : :
12198 : : static enum rtx_code
12199 : 21925859 : simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12200 : : {
12201 : 21925859 : rtx op0 = *pop0;
12202 : 21925859 : rtx op1 = *pop1;
12203 : 21925859 : rtx tem, tem1;
12204 : 21925859 : int i;
12205 : 21925859 : scalar_int_mode mode, inner_mode, tmode;
12206 : 21925859 : opt_scalar_int_mode tmode_iter;
12207 : :
12208 : : /* Try a few ways of applying the same transformation to both operands. */
12209 : 21926138 : while (1)
12210 : : {
12211 : : /* The test below this one won't handle SIGN_EXTENDs on these machines,
12212 : : so check specially. */
12213 : 21926138 : if (!WORD_REGISTER_OPERATIONS
12214 : 21926138 : && code != GTU && code != GEU && code != LTU && code != LEU
12215 : 19005866 : && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12216 : 1838 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12217 : 1374 : && GET_CODE (XEXP (op1, 0)) == ASHIFT
12218 : 723 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12219 : 723 : && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12220 : 723 : && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12221 : : && (is_a <scalar_int_mode>
12222 : 723 : (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12223 : 723 : && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12224 : 723 : && CONST_INT_P (XEXP (op0, 1))
12225 : 723 : && XEXP (op0, 1) == XEXP (op1, 1)
12226 : 90 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12227 : 90 : && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12228 : 90 : && (INTVAL (XEXP (op0, 1))
12229 : 90 : == (GET_MODE_PRECISION (mode)
12230 : 90 : - GET_MODE_PRECISION (inner_mode))))
12231 : : {
12232 : 90 : op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12233 : 90 : op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12234 : : }
12235 : :
12236 : : /* If both operands are the same constant shift, see if we can ignore the
12237 : : shift. We can if the shift is a rotate or if the bits shifted out of
12238 : : this shift are known to be zero for both inputs and if the type of
12239 : : comparison is compatible with the shift. */
12240 : 21926138 : if (GET_CODE (op0) == GET_CODE (op1)
12241 : 3191434 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12242 : 2975556 : && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12243 : 2975556 : || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12244 : 963 : && (code != GT && code != LT && code != GE && code != LE))
12245 : 2974643 : || (GET_CODE (op0) == ASHIFTRT
12246 : 1760 : && (code != GTU && code != LTU
12247 : 1752 : && code != GEU && code != LEU)))
12248 : 2661 : && CONST_INT_P (XEXP (op0, 1))
12249 : 2629 : && INTVAL (XEXP (op0, 1)) >= 0
12250 : 2629 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12251 : 21928767 : && XEXP (op0, 1) == XEXP (op1, 1))
12252 : : {
12253 : 1162 : machine_mode mode = GET_MODE (op0);
12254 : 1162 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12255 : 1162 : int shift_count = INTVAL (XEXP (op0, 1));
12256 : :
12257 : 1162 : if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12258 : 748 : mask &= (mask >> shift_count) << shift_count;
12259 : 414 : else if (GET_CODE (op0) == ASHIFT)
12260 : 414 : mask = (mask & (mask << shift_count)) >> shift_count;
12261 : :
12262 : 1162 : if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12263 : 1162 : && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12264 : 124 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12265 : : else
12266 : : break;
12267 : : }
12268 : :
12269 : : /* If both operands are AND's of a paradoxical SUBREG by constant, the
12270 : : SUBREGs are of the same mode, and, in both cases, the AND would
12271 : : be redundant if the comparison was done in the narrower mode,
12272 : : do the comparison in the narrower mode (e.g., we are AND'ing with 1
12273 : : and the operand's possibly nonzero bits are 0xffffff01; in that case
12274 : : if we only care about QImode, we don't need the AND). This case
12275 : : occurs if the output mode of an scc insn is not SImode and
12276 : : STORE_FLAG_VALUE == 1 (e.g., the 386).
12277 : :
12278 : : Similarly, check for a case where the AND's are ZERO_EXTEND
12279 : : operations from some narrower mode even though a SUBREG is not
12280 : : present. */
12281 : :
12282 : 21924976 : else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12283 : 2606 : && CONST_INT_P (XEXP (op0, 1))
12284 : 2511 : && CONST_INT_P (XEXP (op1, 1)))
12285 : : {
12286 : 2496 : rtx inner_op0 = XEXP (op0, 0);
12287 : 2496 : rtx inner_op1 = XEXP (op1, 0);
12288 : 2496 : HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12289 : 2496 : HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12290 : 2496 : bool changed = false;
12291 : :
12292 : 2496 : if (paradoxical_subreg_p (inner_op0)
12293 : 1019 : && GET_CODE (inner_op1) == SUBREG
12294 : 522 : && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12295 : 522 : && (GET_MODE (SUBREG_REG (inner_op0))
12296 : 522 : == GET_MODE (SUBREG_REG (inner_op1)))
12297 : 131 : && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12298 : : GET_MODE (SUBREG_REG (inner_op0)))) == 0
12299 : 1719 : && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12300 : 119 : GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12301 : : {
12302 : 113 : op0 = SUBREG_REG (inner_op0);
12303 : 113 : op1 = SUBREG_REG (inner_op1);
12304 : :
12305 : : /* The resulting comparison is always unsigned since we masked
12306 : : off the original sign bit. */
12307 : 113 : code = unsigned_condition (code);
12308 : :
12309 : 113 : changed = true;
12310 : : }
12311 : :
12312 : 2383 : else if (c0 == c1)
12313 : 4848 : FOR_EACH_MODE_UNTIL (tmode,
12314 : : as_a <scalar_int_mode> (GET_MODE (op0)))
12315 : 2933 : if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12316 : : {
12317 : 30 : op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12318 : 30 : op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12319 : 30 : code = unsigned_condition (code);
12320 : 30 : changed = true;
12321 : 30 : break;
12322 : : }
12323 : :
12324 : 2058 : if (! changed)
12325 : : break;
12326 : : }
12327 : :
12328 : : /* If both operands are NOT, we can strip off the outer operation
12329 : : and adjust the comparison code for swapped operands; similarly for
12330 : : NEG, except that this must be an equality comparison. */
12331 : 21922480 : else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12332 : 21922479 : || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12333 : 11 : && (code == EQ || code == NE)))
12334 : 12 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12335 : :
12336 : : else
12337 : : break;
12338 : : }
12339 : :
12340 : : /* If the first operand is a constant, swap the operands and adjust the
12341 : : comparison code appropriately, but don't do this if the second operand
12342 : : is already a constant integer. */
12343 : 21925859 : if (swap_commutative_operands_p (op0, op1))
12344 : : {
12345 : 1392640 : std::swap (op0, op1);
12346 : 1392640 : code = swap_condition (code);
12347 : : }
12348 : :
12349 : : /* We now enter a loop during which we will try to simplify the comparison.
12350 : : For the most part, we only are concerned with comparisons with zero,
12351 : : but some things may really be comparisons with zero but not start
12352 : : out looking that way. */
12353 : :
12354 : 23005796 : while (CONST_INT_P (op1))
12355 : : {
12356 : 15123011 : machine_mode raw_mode = GET_MODE (op0);
12357 : 15123011 : scalar_int_mode int_mode;
12358 : 15123011 : int equality_comparison_p;
12359 : 15123011 : int sign_bit_comparison_p;
12360 : 15123011 : int unsigned_comparison_p;
12361 : 15123011 : HOST_WIDE_INT const_op;
12362 : :
12363 : : /* We only want to handle integral modes. This catches VOIDmode,
12364 : : CCmode, and the floating-point modes. An exception is that we
12365 : : can handle VOIDmode if OP0 is a COMPARE or a comparison
12366 : : operation. */
12367 : :
12368 : 15123011 : if (GET_MODE_CLASS (raw_mode) != MODE_INT
12369 : 1283356 : && ! (raw_mode == VOIDmode
12370 : 240868 : && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12371 : : break;
12372 : :
12373 : : /* Try to simplify the compare to constant, possibly changing the
12374 : : comparison op, and/or changing op1 to zero. */
12375 : 14080475 : code = simplify_compare_const (code, raw_mode, &op0, &op1);
12376 : 14080475 : const_op = INTVAL (op1);
12377 : :
12378 : : /* Compute some predicates to simplify code below. */
12379 : :
12380 : 14080475 : equality_comparison_p = (code == EQ || code == NE);
12381 : 14080475 : sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12382 : 14080475 : unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12383 : 14080475 : || code == GEU);
12384 : :
12385 : : /* If this is a sign bit comparison and we can do arithmetic in
12386 : : MODE, say that we will only be needing the sign bit of OP0. */
12387 : 14080475 : if (sign_bit_comparison_p
12388 : 454887 : && is_a <scalar_int_mode> (raw_mode, &int_mode)
12389 : 14535362 : && HWI_COMPUTABLE_MODE_P (int_mode))
12390 : 454495 : op0 = force_to_mode (op0, int_mode,
12391 : : HOST_WIDE_INT_1U
12392 : 454495 : << (GET_MODE_PRECISION (int_mode) - 1), false);
12393 : :
12394 : 14080475 : if (COMPARISON_P (op0))
12395 : : {
12396 : : /* We can't do anything if OP0 is a condition code value, rather
12397 : : than an actual data value. */
12398 : 602248 : if (const_op != 0
12399 : 602248 : || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12400 : : break;
12401 : :
12402 : : /* Get the two operands being compared. */
12403 : 80442 : if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12404 : 0 : tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12405 : : else
12406 : 80442 : tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12407 : :
12408 : : /* Check for the cases where we simply want the result of the
12409 : : earlier test or the opposite of that result. */
12410 : 80442 : if (code == NE || code == EQ
12411 : 80442 : || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12412 : 0 : && (code == LT || code == GE)))
12413 : : {
12414 : 80442 : enum rtx_code new_code;
12415 : 80442 : if (code == LT || code == NE)
12416 : 80442 : new_code = GET_CODE (op0);
12417 : : else
12418 : 0 : new_code = reversed_comparison_code (op0, NULL);
12419 : :
12420 : 80442 : if (new_code != UNKNOWN)
12421 : : {
12422 : 80442 : code = new_code;
12423 : 80442 : op0 = tem;
12424 : 80442 : op1 = tem1;
12425 : 23086238 : continue;
12426 : : }
12427 : : }
12428 : : break;
12429 : : }
12430 : :
12431 : 13478227 : if (raw_mode == VOIDmode)
12432 : : break;
12433 : 13478227 : scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12434 : :
12435 : : /* Now try cases based on the opcode of OP0. If none of the cases
12436 : : does a "continue", we exit this loop immediately after the
12437 : : switch. */
12438 : :
12439 : 13478227 : unsigned int mode_width = GET_MODE_PRECISION (mode);
12440 : 13478227 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12441 : 13478227 : switch (GET_CODE (op0))
12442 : : {
12443 : 312795 : case ZERO_EXTRACT:
12444 : : /* If we are extracting a single bit from a variable position in
12445 : : a constant that has only a single bit set and are comparing it
12446 : : with zero, we can convert this into an equality comparison
12447 : : between the position and the location of the single bit. */
12448 : : /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12449 : : have already reduced the shift count modulo the word size. */
12450 : 312795 : if (!SHIFT_COUNT_TRUNCATED
12451 : 312795 : && CONST_INT_P (XEXP (op0, 0))
12452 : 12281 : && XEXP (op0, 1) == const1_rtx
12453 : 12261 : && equality_comparison_p && const_op == 0
12454 : 325056 : && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12455 : : {
12456 : 0 : if (BITS_BIG_ENDIAN)
12457 : : i = BITS_PER_WORD - 1 - i;
12458 : :
12459 : 0 : op0 = XEXP (op0, 2);
12460 : 0 : op1 = GEN_INT (i);
12461 : 0 : const_op = i;
12462 : :
12463 : : /* Result is nonzero iff shift count is equal to I. */
12464 : 0 : code = reverse_condition (code);
12465 : 0 : continue;
12466 : : }
12467 : :
12468 : : /* fall through */
12469 : :
12470 : 312799 : case SIGN_EXTRACT:
12471 : 312799 : tem = expand_compound_operation (op0);
12472 : 312799 : if (tem != op0)
12473 : : {
12474 : 271394 : op0 = tem;
12475 : 271394 : continue;
12476 : : }
12477 : : break;
12478 : :
12479 : 29901 : case NOT:
12480 : : /* If testing for equality, we can take the NOT of the constant. */
12481 : 42587 : if (equality_comparison_p
12482 : 29901 : && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12483 : : {
12484 : 12686 : op0 = XEXP (op0, 0);
12485 : 12686 : op1 = tem;
12486 : 12686 : continue;
12487 : : }
12488 : :
12489 : : /* If just looking at the sign bit, reverse the sense of the
12490 : : comparison. */
12491 : 17215 : if (sign_bit_comparison_p)
12492 : : {
12493 : 16867 : op0 = XEXP (op0, 0);
12494 : 16867 : code = (code == GE ? LT : GE);
12495 : 16867 : continue;
12496 : : }
12497 : : break;
12498 : :
12499 : 278187 : case NEG:
12500 : : /* If testing for equality, we can take the NEG of the constant. */
12501 : 552177 : if (equality_comparison_p
12502 : 278187 : && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12503 : : {
12504 : 273990 : op0 = XEXP (op0, 0);
12505 : 273990 : op1 = tem;
12506 : 273990 : continue;
12507 : : }
12508 : :
12509 : : /* The remaining cases only apply to comparisons with zero. */
12510 : 4197 : if (const_op != 0)
12511 : : break;
12512 : :
12513 : : /* When X is ABS or is known positive,
12514 : : (neg X) is < 0 if and only if X != 0. */
12515 : :
12516 : 3692 : if (sign_bit_comparison_p
12517 : 3654 : && (GET_CODE (XEXP (op0, 0)) == ABS
12518 : 3653 : || (mode_width <= HOST_BITS_PER_WIDE_INT
12519 : 3653 : && (nonzero_bits (XEXP (op0, 0), mode)
12520 : 3653 : & (HOST_WIDE_INT_1U << (mode_width - 1)))
12521 : 3653 : == 0)))
12522 : : {
12523 : 38 : op0 = XEXP (op0, 0);
12524 : 38 : code = (code == LT ? NE : EQ);
12525 : 38 : continue;
12526 : : }
12527 : :
12528 : : /* If we have NEG of something whose two high-order bits are the
12529 : : same, we know that "(-a) < 0" is equivalent to "a > 0". */
12530 : 3616 : if (num_sign_bit_copies (op0, mode) >= 2)
12531 : : {
12532 : 22 : op0 = XEXP (op0, 0);
12533 : 22 : code = swap_condition (code);
12534 : 22 : continue;
12535 : : }
12536 : : break;
12537 : :
12538 : 146 : case ROTATE:
12539 : : /* If we are testing equality and our count is a constant, we
12540 : : can perform the inverse operation on our RHS. */
12541 : 146 : if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12542 : 146 : && (tem = simplify_binary_operation (ROTATERT, mode,
12543 : : op1, XEXP (op0, 1))) != 0)
12544 : : {
12545 : 0 : op0 = XEXP (op0, 0);
12546 : 0 : op1 = tem;
12547 : 0 : continue;
12548 : : }
12549 : :
12550 : : /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12551 : : a particular bit. Convert it to an AND of a constant of that
12552 : : bit. This will be converted into a ZERO_EXTRACT. */
12553 : 146 : if (const_op == 0 && sign_bit_comparison_p
12554 : 0 : && CONST_INT_P (XEXP (op0, 1))
12555 : 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
12556 : 0 : && UINTVAL (XEXP (op0, 1)) < mode_width)
12557 : : {
12558 : 0 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12559 : : (HOST_WIDE_INT_1U
12560 : : << (mode_width - 1
12561 : 0 : - INTVAL (XEXP (op0, 1)))));
12562 : 0 : code = (code == LT ? NE : EQ);
12563 : 0 : continue;
12564 : : }
12565 : :
12566 : : /* Fall through. */
12567 : :
12568 : 3027 : case ABS:
12569 : : /* ABS is ignorable inside an equality comparison with zero. */
12570 : 3027 : if (const_op == 0 && equality_comparison_p)
12571 : : {
12572 : 1 : op0 = XEXP (op0, 0);
12573 : 1 : continue;
12574 : : }
12575 : : break;
12576 : :
12577 : 1048 : case SIGN_EXTEND:
12578 : : /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12579 : : (compare FOO CONST) if CONST fits in FOO's mode and we
12580 : : are either testing inequality or have an unsigned
12581 : : comparison with ZERO_EXTEND or a signed comparison with
12582 : : SIGN_EXTEND. But don't do it if we don't have a compare
12583 : : insn of the given mode, since we'd have to revert it
12584 : : later on, and then we wouldn't know whether to sign- or
12585 : : zero-extend. */
12586 : 1048 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12587 : 1048 : && ! unsigned_comparison_p
12588 : 901 : && HWI_COMPUTABLE_MODE_P (mode)
12589 : 901 : && trunc_int_for_mode (const_op, mode) == const_op
12590 : 901 : && have_insn_for (COMPARE, mode))
12591 : : {
12592 : 901 : op0 = XEXP (op0, 0);
12593 : 901 : continue;
12594 : : }
12595 : : break;
12596 : :
12597 : 412292 : case SUBREG:
12598 : : /* Check for the case where we are comparing A - C1 with C2, that is
12599 : :
12600 : : (subreg:MODE (plus (A) (-C1))) op (C2)
12601 : :
12602 : : with C1 a constant, and try to lift the SUBREG, i.e. to do the
12603 : : comparison in the wider mode. One of the following two conditions
12604 : : must be true in order for this to be valid:
12605 : :
12606 : : 1. The mode extension results in the same bit pattern being added
12607 : : on both sides and the comparison is equality or unsigned. As
12608 : : C2 has been truncated to fit in MODE, the pattern can only be
12609 : : all 0s or all 1s.
12610 : :
12611 : : 2. The mode extension results in the sign bit being copied on
12612 : : each side.
12613 : :
12614 : : The difficulty here is that we have predicates for A but not for
12615 : : (A - C1) so we need to check that C1 is within proper bounds so
12616 : : as to perturbate A as little as possible. */
12617 : :
12618 : 412292 : if (mode_width <= HOST_BITS_PER_WIDE_INT
12619 : 412190 : && subreg_lowpart_p (op0)
12620 : 383102 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12621 : : &inner_mode)
12622 : 381693 : && GET_MODE_PRECISION (inner_mode) > mode_width
12623 : 381693 : && GET_CODE (SUBREG_REG (op0)) == PLUS
12624 : 412292 : && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12625 : : {
12626 : 0 : rtx a = XEXP (SUBREG_REG (op0), 0);
12627 : 0 : HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12628 : :
12629 : 0 : if ((c1 > 0
12630 : 0 : && (unsigned HOST_WIDE_INT) c1
12631 : 0 : < HOST_WIDE_INT_1U << (mode_width - 1)
12632 : 0 : && (equality_comparison_p || unsigned_comparison_p)
12633 : : /* (A - C1) zero-extends if it is positive and sign-extends
12634 : : if it is negative, C2 both zero- and sign-extends. */
12635 : 0 : && (((nonzero_bits (a, inner_mode)
12636 : 0 : & ~GET_MODE_MASK (mode)) == 0
12637 : 0 : && const_op >= 0)
12638 : : /* (A - C1) sign-extends if it is positive and 1-extends
12639 : : if it is negative, C2 both sign- and 1-extends. */
12640 : 0 : || (num_sign_bit_copies (a, inner_mode)
12641 : 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12642 : 0 : - mode_width)
12643 : 0 : && const_op < 0)))
12644 : 0 : || ((unsigned HOST_WIDE_INT) c1
12645 : 0 : < HOST_WIDE_INT_1U << (mode_width - 2)
12646 : : /* (A - C1) always sign-extends, like C2. */
12647 : 0 : && num_sign_bit_copies (a, inner_mode)
12648 : 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12649 : 0 : - (mode_width - 1))))
12650 : : {
12651 : 0 : op0 = SUBREG_REG (op0);
12652 : 0 : continue;
12653 : : }
12654 : : }
12655 : :
12656 : : /* If the inner mode is narrower and we are extracting the low part,
12657 : : we can treat the SUBREG as if it were a ZERO_EXTEND ... */
12658 : 412292 : if (paradoxical_subreg_p (op0))
12659 : : {
12660 : : if (WORD_REGISTER_OPERATIONS
12661 : : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12662 : : &inner_mode)
12663 : : && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD
12664 : : /* On WORD_REGISTER_OPERATIONS targets the bits
12665 : : beyond sub_mode aren't considered undefined,
12666 : : so optimize only if it is a MEM load when MEM loads
12667 : : zero extend, because then the upper bits are all zero. */
12668 : : && !(MEM_P (SUBREG_REG (op0))
12669 : : && load_extend_op (inner_mode) == ZERO_EXTEND))
12670 : : break;
12671 : : /* FALLTHROUGH to case ZERO_EXTEND */
12672 : : }
12673 : 412292 : else if (subreg_lowpart_p (op0)
12674 : 383204 : && GET_MODE_CLASS (mode) == MODE_INT
12675 : 383204 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12676 : 381693 : && (code == NE || code == EQ)
12677 : 275594 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12678 : 269800 : && !paradoxical_subreg_p (op0)
12679 : 682092 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12680 : 269800 : & ~GET_MODE_MASK (mode)) == 0)
12681 : : {
12682 : : /* Remove outer subregs that don't do anything. */
12683 : 112519 : tem = gen_lowpart (inner_mode, op1);
12684 : :
12685 : 112519 : if ((nonzero_bits (tem, inner_mode)
12686 : 112519 : & ~GET_MODE_MASK (mode)) == 0)
12687 : : {
12688 : 111756 : op0 = SUBREG_REG (op0);
12689 : 111756 : op1 = tem;
12690 : 111756 : continue;
12691 : : }
12692 : : break;
12693 : : }
12694 : : else
12695 : : break;
12696 : :
12697 : : /* FALLTHROUGH */
12698 : :
12699 : 39261 : case ZERO_EXTEND:
12700 : 39261 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12701 : 39261 : && (unsigned_comparison_p || equality_comparison_p)
12702 : 39222 : && HWI_COMPUTABLE_MODE_P (mode)
12703 : 39222 : && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12704 : 39222 : && const_op >= 0
12705 : 39213 : && have_insn_for (COMPARE, mode))
12706 : : {
12707 : 39213 : op0 = XEXP (op0, 0);
12708 : 39213 : continue;
12709 : : }
12710 : : break;
12711 : :
12712 : 412150 : case PLUS:
12713 : : /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12714 : : this for equality comparisons due to pathological cases involving
12715 : : overflows. */
12716 : 462654 : if (equality_comparison_p
12717 : 412150 : && (tem = simplify_binary_operation (MINUS, mode,
12718 : : op1, XEXP (op0, 1))) != 0)
12719 : : {
12720 : 50504 : op0 = XEXP (op0, 0);
12721 : 50504 : op1 = tem;
12722 : 50504 : continue;
12723 : : }
12724 : :
12725 : : /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12726 : 361646 : if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12727 : 12837 : && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12728 : : {
12729 : 0 : op0 = XEXP (XEXP (op0, 0), 0);
12730 : 0 : code = (code == LT ? EQ : NE);
12731 : 0 : continue;
12732 : : }
12733 : : break;
12734 : :
12735 : 151296 : case MINUS:
12736 : : /* We used to optimize signed comparisons against zero, but that
12737 : : was incorrect. Unsigned comparisons against zero (GTU, LEU)
12738 : : arrive here as equality comparisons, or (GEU, LTU) are
12739 : : optimized away. No need to special-case them. */
12740 : :
12741 : : /* (eq (minus A B) C) -> (eq A (plus B C)) or
12742 : : (eq B (minus A C)), whichever simplifies. We can only do
12743 : : this for equality comparisons due to pathological cases involving
12744 : : overflows. */
12745 : 185088 : if (equality_comparison_p
12746 : 151296 : && (tem = simplify_binary_operation (PLUS, mode,
12747 : : XEXP (op0, 1), op1)) != 0)
12748 : : {
12749 : 33792 : op0 = XEXP (op0, 0);
12750 : 33792 : op1 = tem;
12751 : 33792 : continue;
12752 : : }
12753 : :
12754 : 144077 : if (equality_comparison_p
12755 : 117504 : && (tem = simplify_binary_operation (MINUS, mode,
12756 : : XEXP (op0, 0), op1)) != 0)
12757 : : {
12758 : 26573 : op0 = XEXP (op0, 1);
12759 : 26573 : op1 = tem;
12760 : 26573 : continue;
12761 : : }
12762 : :
12763 : : /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12764 : : of bits in X minus 1, is one iff X > 0. */
12765 : 17329 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12766 : 493 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12767 : 493 : && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12768 : 90949 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12769 : : {
12770 : 0 : op0 = XEXP (op0, 1);
12771 : 0 : code = (code == GE ? LE : GT);
12772 : 0 : continue;
12773 : : }
12774 : : break;
12775 : :
12776 : 5921 : case XOR:
12777 : : /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12778 : : if C is zero or B is a constant. */
12779 : 6067 : if (equality_comparison_p
12780 : 5921 : && (tem = simplify_binary_operation (XOR, mode,
12781 : : XEXP (op0, 1), op1)) != 0)
12782 : : {
12783 : 146 : op0 = XEXP (op0, 0);
12784 : 146 : op1 = tem;
12785 : 146 : continue;
12786 : : }
12787 : : break;
12788 : :
12789 : :
12790 : 353281 : case IOR:
12791 : : /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12792 : : iff X <= 0. */
12793 : 6146 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12794 : 1270 : && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12795 : 353329 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12796 : : {
12797 : 48 : op0 = XEXP (op0, 1);
12798 : 48 : code = (code == GE ? GT : LE);
12799 : 48 : continue;
12800 : : }
12801 : : break;
12802 : :
12803 : 1617475 : case AND:
12804 : : /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12805 : : will be converted to a ZERO_EXTRACT later. */
12806 : 1617475 : if (const_op == 0 && equality_comparison_p
12807 : 1458189 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12808 : 52039 : && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12809 : : {
12810 : 9131 : op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12811 : : XEXP (XEXP (op0, 0), 1));
12812 : 9131 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12813 : 9131 : continue;
12814 : : }
12815 : :
12816 : : /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12817 : : zero and X is a comparison and C1 and C2 describe only bits set
12818 : : in STORE_FLAG_VALUE, we can compare with X. */
12819 : 1608344 : if (const_op == 0 && equality_comparison_p
12820 : 1449058 : && mode_width <= HOST_BITS_PER_WIDE_INT
12821 : 1445269 : && CONST_INT_P (XEXP (op0, 1))
12822 : 1143595 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12823 : 407814 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12824 : 389682 : && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12825 : 389682 : && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12826 : : {
12827 : 389682 : mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12828 : 389682 : << INTVAL (XEXP (XEXP (op0, 0), 1)));
12829 : 389682 : if ((~STORE_FLAG_VALUE & mask) == 0
12830 : 389682 : && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12831 : 0 : || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12832 : 0 : && COMPARISON_P (tem))))
12833 : : {
12834 : 0 : op0 = XEXP (XEXP (op0, 0), 0);
12835 : 0 : continue;
12836 : : }
12837 : : }
12838 : :
12839 : : /* If we are doing an equality comparison of an AND of a bit equal
12840 : : to the sign bit, replace this with a LT or GE comparison of
12841 : : the underlying value. */
12842 : 1608934 : if (equality_comparison_p
12843 : : && const_op == 0
12844 : 1449058 : && CONST_INT_P (XEXP (op0, 1))
12845 : 1143898 : && mode_width <= HOST_BITS_PER_WIDE_INT
12846 : 1608344 : && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12847 : 1143595 : == HOST_WIDE_INT_1U << (mode_width - 1)))
12848 : : {
12849 : 590 : op0 = XEXP (op0, 0);
12850 : 590 : code = (code == EQ ? GE : LT);
12851 : 590 : continue;
12852 : : }
12853 : :
12854 : : /* If this AND operation is really a ZERO_EXTEND from a narrower
12855 : : mode, the constant fits within that mode, and this is either an
12856 : : equality or unsigned comparison, try to do this comparison in
12857 : : the narrower mode.
12858 : :
12859 : : Note that in:
12860 : :
12861 : : (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12862 : : -> (ne:DI (reg:SI 4) (const_int 0))
12863 : :
12864 : : unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12865 : : known to hold a value of the required mode the
12866 : : transformation is invalid. */
12867 : 1623444 : if ((equality_comparison_p || unsigned_comparison_p)
12868 : 1593900 : && CONST_INT_P (XEXP (op0, 1))
12869 : 3710731 : && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12870 : 1284818 : & GET_MODE_MASK (mode))
12871 : : + 1)) >= 0
12872 : 833849 : && const_op >> i == 0
12873 : 4019813 : && int_mode_for_size (i, 1).exists (&tmode))
12874 : : {
12875 : 15690 : op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12876 : 15690 : continue;
12877 : : }
12878 : :
12879 : : /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12880 : : fits in both M1 and M2 and the SUBREG is either paradoxical
12881 : : or represents the low part, permute the SUBREG and the AND
12882 : : and try again. */
12883 : 1592064 : if (GET_CODE (XEXP (op0, 0)) == SUBREG
12884 : 97467 : && CONST_INT_P (XEXP (op0, 1)))
12885 : : {
12886 : 92337 : unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12887 : : /* Require an integral mode, to avoid creating something like
12888 : : (AND:SF ...). */
12889 : 120202 : if ((is_a <scalar_int_mode>
12890 : 92337 : (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode))
12891 : : /* It is unsafe to commute the AND into the SUBREG if the
12892 : : SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12893 : : not defined. As originally written the upper bits
12894 : : have a defined value due to the AND operation.
12895 : : However, if we commute the AND inside the SUBREG then
12896 : : they no longer have defined values and the meaning of
12897 : : the code has been changed.
12898 : : Also C1 should not change value in the smaller mode,
12899 : : see PR67028 (a positive C1 can become negative in the
12900 : : smaller mode, so that the AND does no longer mask the
12901 : : upper bits). */
12902 : 92310 : && ((WORD_REGISTER_OPERATIONS
12903 : : && mode_width > GET_MODE_PRECISION (tmode)
12904 : : && mode_width <= BITS_PER_WORD
12905 : : && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12906 : 92310 : || (mode_width <= GET_MODE_PRECISION (tmode)
12907 : 29549 : && subreg_lowpart_p (XEXP (op0, 0))))
12908 : 29525 : && mode_width <= HOST_BITS_PER_WIDE_INT
12909 : 29525 : && HWI_COMPUTABLE_MODE_P (tmode)
12910 : 29408 : && (c1 & ~mask) == 0
12911 : 27865 : && (c1 & ~GET_MODE_MASK (tmode)) == 0
12912 : 27865 : && c1 != mask
12913 : 27865 : && c1 != GET_MODE_MASK (tmode))
12914 : : {
12915 : 27865 : op0 = simplify_gen_binary (AND, tmode,
12916 : 27865 : SUBREG_REG (XEXP (op0, 0)),
12917 : 27865 : gen_int_mode (c1, tmode));
12918 : 27865 : op0 = gen_lowpart (mode, op0);
12919 : 27865 : continue;
12920 : : }
12921 : : }
12922 : :
12923 : : /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12924 : 1564199 : if (const_op == 0 && equality_comparison_p
12925 : 1412811 : && XEXP (op0, 1) == const1_rtx
12926 : 547772 : && GET_CODE (XEXP (op0, 0)) == NOT)
12927 : : {
12928 : 4618 : op0 = simplify_and_const_int (NULL_RTX, mode,
12929 : : XEXP (XEXP (op0, 0), 0), 1);
12930 : 4618 : code = (code == NE ? EQ : NE);
12931 : 4618 : continue;
12932 : : }
12933 : :
12934 : : /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12935 : : (eq (and (lshiftrt X) 1) 0).
12936 : : Also handle the case where (not X) is expressed using xor. */
12937 : 1559581 : if (const_op == 0 && equality_comparison_p
12938 : 1408193 : && XEXP (op0, 1) == const1_rtx
12939 : 543154 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12940 : : {
12941 : 392345 : rtx shift_op = XEXP (XEXP (op0, 0), 0);
12942 : 392345 : rtx shift_count = XEXP (XEXP (op0, 0), 1);
12943 : :
12944 : 395099 : if (GET_CODE (shift_op) == NOT
12945 : 392345 : || (GET_CODE (shift_op) == XOR
12946 : 4480 : && CONST_INT_P (XEXP (shift_op, 1))
12947 : 2754 : && CONST_INT_P (shift_count)
12948 : 2754 : && HWI_COMPUTABLE_MODE_P (mode)
12949 : 2754 : && (UINTVAL (XEXP (shift_op, 1))
12950 : : == HOST_WIDE_INT_1U
12951 : 2754 : << INTVAL (shift_count))))
12952 : : {
12953 : 2754 : op0
12954 : 2754 : = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12955 : 2754 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12956 : 2754 : code = (code == NE ? EQ : NE);
12957 : 2754 : continue;
12958 : : }
12959 : : }
12960 : : break;
12961 : :
12962 : 45522 : case ASHIFT:
12963 : : /* If we have (compare (ashift FOO N) (const_int C)) and
12964 : : the high order N bits of FOO (N+1 if an inequality comparison)
12965 : : are known to be zero, we can do this by comparing FOO with C
12966 : : shifted right N bits so long as the low-order N bits of C are
12967 : : zero. */
12968 : 45522 : if (CONST_INT_P (XEXP (op0, 1))
12969 : 42089 : && INTVAL (XEXP (op0, 1)) >= 0
12970 : 42089 : && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12971 : : < HOST_BITS_PER_WIDE_INT)
12972 : 42087 : && (((unsigned HOST_WIDE_INT) const_op
12973 : 42087 : & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12974 : : - 1)) == 0)
12975 : 31732 : && mode_width <= HOST_BITS_PER_WIDE_INT
12976 : 77224 : && (nonzero_bits (XEXP (op0, 0), mode)
12977 : 31702 : & ~(mask >> (INTVAL (XEXP (op0, 1))
12978 : 31702 : + ! equality_comparison_p))) == 0)
12979 : : {
12980 : : /* We must perform a logical shift, not an arithmetic one,
12981 : : as we want the top N bits of C to be zero. */
12982 : 341 : unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12983 : :
12984 : 341 : temp >>= INTVAL (XEXP (op0, 1));
12985 : 341 : op1 = gen_int_mode (temp, mode);
12986 : 341 : op0 = XEXP (op0, 0);
12987 : 341 : continue;
12988 : 341 : }
12989 : :
12990 : : /* If we are doing a sign bit comparison, it means we are testing
12991 : : a particular bit. Convert it to the appropriate AND. */
12992 : 45181 : if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12993 : 2983 : && mode_width <= HOST_BITS_PER_WIDE_INT)
12994 : : {
12995 : 5966 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12996 : : (HOST_WIDE_INT_1U
12997 : : << (mode_width - 1
12998 : 2983 : - INTVAL (XEXP (op0, 1)))));
12999 : 2983 : code = (code == LT ? NE : EQ);
13000 : 2983 : continue;
13001 : : }
13002 : :
13003 : : /* If this an equality comparison with zero and we are shifting
13004 : : the low bit to the sign bit, we can convert this to an AND of the
13005 : : low-order bit. */
13006 : 42198 : if (const_op == 0 && equality_comparison_p
13007 : 9756 : && CONST_INT_P (XEXP (op0, 1))
13008 : 7447 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13009 : : {
13010 : 102 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
13011 : 102 : continue;
13012 : : }
13013 : : break;
13014 : :
13015 : 41401 : case ASHIFTRT:
13016 : : /* If this is an equality comparison with zero, we can do this
13017 : : as a logical shift, which might be much simpler. */
13018 : 41401 : if (equality_comparison_p && const_op == 0
13019 : 26238 : && CONST_INT_P (XEXP (op0, 1)))
13020 : : {
13021 : 51576 : op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
13022 : : XEXP (op0, 0),
13023 : 25788 : INTVAL (XEXP (op0, 1)));
13024 : 25788 : continue;
13025 : : }
13026 : :
13027 : : /* If OP0 is a sign extension and CODE is not an unsigned comparison,
13028 : : do the comparison in a narrower mode. */
13029 : 19883 : if (! unsigned_comparison_p
13030 : 12912 : && CONST_INT_P (XEXP (op0, 1))
13031 : 12434 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
13032 : 4976 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
13033 : 4758 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13034 : 15613 : .exists (&tmode))
13035 : 15613 : && (((unsigned HOST_WIDE_INT) const_op
13036 : 4270 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13037 : 4270 : <= GET_MODE_MASK (tmode)))
13038 : : {
13039 : 4270 : op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
13040 : 4270 : continue;
13041 : : }
13042 : :
13043 : : /* Likewise if OP0 is a PLUS of a sign extension with a
13044 : : constant, which is usually represented with the PLUS
13045 : : between the shifts. */
13046 : 11343 : if (! unsigned_comparison_p
13047 : 8642 : && CONST_INT_P (XEXP (op0, 1))
13048 : 8164 : && GET_CODE (XEXP (op0, 0)) == PLUS
13049 : 54 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
13050 : 22 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
13051 : 2 : && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
13052 : 0 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13053 : 11343 : .exists (&tmode))
13054 : 11343 : && (((unsigned HOST_WIDE_INT) const_op
13055 : 0 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13056 : 0 : <= GET_MODE_MASK (tmode)))
13057 : : {
13058 : 0 : rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
13059 : 0 : rtx add_const = XEXP (XEXP (op0, 0), 1);
13060 : 0 : rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
13061 : : add_const, XEXP (op0, 1));
13062 : :
13063 : 0 : op0 = simplify_gen_binary (PLUS, tmode,
13064 : 0 : gen_lowpart (tmode, inner),
13065 : : new_const);
13066 : 0 : continue;
13067 : 0 : }
13068 : :
13069 : : /* FALLTHROUGH */
13070 : 126448 : case LSHIFTRT:
13071 : : /* If we have (compare (xshiftrt FOO N) (const_int C)) and
13072 : : the low order N bits of FOO are known to be zero, we can do this
13073 : : by comparing FOO with C shifted left N bits so long as no
13074 : : overflow occurs. Even if the low order N bits of FOO aren't known
13075 : : to be zero, if the comparison is >= or < we can use the same
13076 : : optimization and for > or <= by setting all the low
13077 : : order N bits in the comparison constant. */
13078 : 126448 : if (CONST_INT_P (XEXP (op0, 1))
13079 : 122073 : && INTVAL (XEXP (op0, 1)) > 0
13080 : 122073 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
13081 : 121713 : && mode_width <= HOST_BITS_PER_WIDE_INT
13082 : 126448 : && (((unsigned HOST_WIDE_INT) const_op
13083 : 241904 : + (GET_CODE (op0) != LSHIFTRT
13084 : 120952 : ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
13085 : : + 1)
13086 : : : 0))
13087 : 120952 : <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
13088 : : {
13089 : 120825 : unsigned HOST_WIDE_INT low_bits
13090 : 120825 : = (nonzero_bits (XEXP (op0, 0), mode)
13091 : 120825 : & ((HOST_WIDE_INT_1U
13092 : 120825 : << INTVAL (XEXP (op0, 1))) - 1));
13093 : 120825 : if (low_bits == 0 || !equality_comparison_p)
13094 : : {
13095 : : /* If the shift was logical, then we must make the condition
13096 : : unsigned. */
13097 : 20567 : if (GET_CODE (op0) == LSHIFTRT)
13098 : 16314 : code = unsigned_condition (code);
13099 : :
13100 : 20567 : const_op = (unsigned HOST_WIDE_INT) const_op
13101 : 20567 : << INTVAL (XEXP (op0, 1));
13102 : 20567 : if (low_bits != 0
13103 : 4476 : && (code == GT || code == GTU
13104 : 917 : || code == LE || code == LEU))
13105 : 4408 : const_op
13106 : 4408 : |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
13107 : 20567 : op1 = GEN_INT (const_op);
13108 : 20567 : op0 = XEXP (op0, 0);
13109 : 20567 : continue;
13110 : : }
13111 : : }
13112 : :
13113 : : /* If we are using this shift to extract just the sign bit, we
13114 : : can replace this with an LT or GE comparison. */
13115 : 105881 : if (const_op == 0
13116 : 94825 : && (equality_comparison_p || sign_bit_comparison_p)
13117 : 94797 : && CONST_INT_P (XEXP (op0, 1))
13118 : 90682 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13119 : : {
13120 : 46865 : op0 = XEXP (op0, 0);
13121 : 46865 : code = (code == NE || code == GT ? LT : GE);
13122 : 46865 : continue;
13123 : : }
13124 : : break;
13125 : :
13126 : : default:
13127 : : break;
13128 : : }
13129 : :
13130 : : break;
13131 : : }
13132 : :
13133 : : /* Now make any compound operations involved in this comparison. Then,
13134 : : check for an outmost SUBREG on OP0 that is not doing anything or is
13135 : : paradoxical. The latter transformation must only be performed when
13136 : : it is known that the "extra" bits will be the same in op0 and op1 or
13137 : : that they don't matter. There are three cases to consider:
13138 : :
13139 : : 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13140 : : care bits and we can assume they have any convenient value. So
13141 : : making the transformation is safe.
13142 : :
13143 : : 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13144 : : In this case the upper bits of op0 are undefined. We should not make
13145 : : the simplification in that case as we do not know the contents of
13146 : : those bits.
13147 : :
13148 : : 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13149 : : In that case we know those bits are zeros or ones. We must also be
13150 : : sure that they are the same as the upper bits of op1.
13151 : :
13152 : : We can never remove a SUBREG for a non-equality comparison because
13153 : : the sign bit is in a different place in the underlying object. */
13154 : :
13155 : 21925859 : rtx_code op0_mco_code = SET;
13156 : 21925859 : if (op1 == const0_rtx)
13157 : 10397447 : op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13158 : :
13159 : 21925859 : op0 = make_compound_operation (op0, op0_mco_code);
13160 : 21925859 : op1 = make_compound_operation (op1, SET);
13161 : :
13162 : 443266 : if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13163 : 412949 : && is_int_mode (GET_MODE (op0), &mode)
13164 : 390270 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13165 : 22313408 : && (code == NE || code == EQ))
13166 : : {
13167 : 217672 : if (paradoxical_subreg_p (op0))
13168 : : {
13169 : : /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13170 : : implemented. */
13171 : 0 : if (REG_P (SUBREG_REG (op0)))
13172 : : {
13173 : 0 : op0 = SUBREG_REG (op0);
13174 : 0 : op1 = gen_lowpart (inner_mode, op1);
13175 : : }
13176 : : }
13177 : 217672 : else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13178 : 217672 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13179 : 210836 : & ~GET_MODE_MASK (mode)) == 0)
13180 : : {
13181 : 39977 : tem = gen_lowpart (inner_mode, op1);
13182 : :
13183 : 39977 : if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13184 : 32175 : op0 = SUBREG_REG (op0), op1 = tem;
13185 : : }
13186 : : }
13187 : :
13188 : : /* We now do the opposite procedure: Some machines don't have compare
13189 : : insns in all modes. If OP0's mode is an integer mode smaller than a
13190 : : word and we can't do a compare in that mode, see if there is a larger
13191 : : mode for which we can do the compare. There are a number of cases in
13192 : : which we can use the wider mode. */
13193 : :
13194 : 21925859 : if (is_int_mode (GET_MODE (op0), &mode)
13195 : 22802147 : && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13196 : 8345958 : && ! have_insn_for (COMPARE, mode))
13197 : 0 : FOR_EACH_WIDER_MODE (tmode_iter, mode)
13198 : : {
13199 : 0 : tmode = tmode_iter.require ();
13200 : 0 : if (!HWI_COMPUTABLE_MODE_P (tmode))
13201 : : break;
13202 : 0 : if (have_insn_for (COMPARE, tmode))
13203 : : {
13204 : 0 : int zero_extended;
13205 : :
13206 : : /* If this is a test for negative, we can make an explicit
13207 : : test of the sign bit. Test this first so we can use
13208 : : a paradoxical subreg to extend OP0. */
13209 : :
13210 : 0 : if (op1 == const0_rtx && (code == LT || code == GE)
13211 : 0 : && HWI_COMPUTABLE_MODE_P (mode))
13212 : : {
13213 : 0 : unsigned HOST_WIDE_INT sign
13214 : 0 : = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13215 : 0 : op0 = simplify_gen_binary (AND, tmode,
13216 : 0 : gen_lowpart (tmode, op0),
13217 : 0 : gen_int_mode (sign, tmode));
13218 : 0 : code = (code == LT) ? NE : EQ;
13219 : : break;
13220 : : }
13221 : :
13222 : : /* If the only nonzero bits in OP0 and OP1 are those in the
13223 : : narrower mode and this is an equality or unsigned comparison,
13224 : : we can use the wider mode. Similarly for sign-extended
13225 : : values, in which case it is true for all comparisons. */
13226 : 0 : zero_extended = ((code == EQ || code == NE
13227 : 0 : || code == GEU || code == GTU
13228 : 0 : || code == LEU || code == LTU)
13229 : 0 : && (nonzero_bits (op0, tmode)
13230 : 0 : & ~GET_MODE_MASK (mode)) == 0
13231 : 0 : && ((CONST_INT_P (op1)
13232 : 0 : || (nonzero_bits (op1, tmode)
13233 : 0 : & ~GET_MODE_MASK (mode)) == 0)));
13234 : :
13235 : 0 : if (zero_extended
13236 : 0 : || ((num_sign_bit_copies (op0, tmode)
13237 : 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13238 : 0 : - GET_MODE_PRECISION (mode)))
13239 : 0 : && (num_sign_bit_copies (op1, tmode)
13240 : 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13241 : 0 : - GET_MODE_PRECISION (mode)))))
13242 : : {
13243 : : /* If OP0 is an AND and we don't have an AND in MODE either,
13244 : : make a new AND in the proper mode. */
13245 : 0 : if (GET_CODE (op0) == AND
13246 : 0 : && !have_insn_for (AND, mode))
13247 : 0 : op0 = simplify_gen_binary (AND, tmode,
13248 : 0 : gen_lowpart (tmode,
13249 : : XEXP (op0, 0)),
13250 : 0 : gen_lowpart (tmode,
13251 : : XEXP (op0, 1)));
13252 : : else
13253 : : {
13254 : 0 : if (zero_extended)
13255 : : {
13256 : 0 : op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13257 : : op0, mode);
13258 : 0 : op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13259 : : op1, mode);
13260 : : }
13261 : : else
13262 : : {
13263 : 0 : op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13264 : : op0, mode);
13265 : 0 : op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13266 : : op1, mode);
13267 : : }
13268 : : break;
13269 : : }
13270 : : }
13271 : : }
13272 : : }
13273 : :
13274 : : /* We may have changed the comparison operands. Re-canonicalize. */
13275 : 21925859 : if (swap_commutative_operands_p (op0, op1))
13276 : : {
13277 : 82512 : std::swap (op0, op1);
13278 : 82512 : code = swap_condition (code);
13279 : : }
13280 : :
13281 : : /* If this machine only supports a subset of valid comparisons, see if we
13282 : : can convert an unsupported one into a supported one. */
13283 : 21925859 : target_canonicalize_comparison (&code, &op0, &op1, 0);
13284 : :
13285 : 21925859 : *pop0 = op0;
13286 : 21925859 : *pop1 = op1;
13287 : :
13288 : 21925859 : return code;
13289 : : }
13290 : :
13291 : : /* Utility function for record_value_for_reg. Count number of
13292 : : rtxs in X. */
13293 : : static int
13294 : 1695 : count_rtxs (rtx x)
13295 : : {
13296 : 1695 : enum rtx_code code = GET_CODE (x);
13297 : 1695 : const char *fmt;
13298 : 1695 : int i, j, ret = 1;
13299 : :
13300 : 1695 : if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13301 : 1695 : || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13302 : : {
13303 : 78 : rtx x0 = XEXP (x, 0);
13304 : 78 : rtx x1 = XEXP (x, 1);
13305 : :
13306 : 78 : if (x0 == x1)
13307 : 0 : return 1 + 2 * count_rtxs (x0);
13308 : :
13309 : 78 : if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13310 : 78 : || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13311 : 4 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13312 : 0 : return 2 + 2 * count_rtxs (x0)
13313 : 0 : + count_rtxs (x == XEXP (x1, 0)
13314 : 0 : ? XEXP (x1, 1) : XEXP (x1, 0));
13315 : :
13316 : 78 : if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13317 : 78 : || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13318 : 8 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13319 : 0 : return 2 + 2 * count_rtxs (x1)
13320 : 0 : + count_rtxs (x == XEXP (x0, 0)
13321 : 0 : ? XEXP (x0, 1) : XEXP (x0, 0));
13322 : : }
13323 : :
13324 : 1695 : fmt = GET_RTX_FORMAT (code);
13325 : 4129 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13326 : 2434 : if (fmt[i] == 'e')
13327 : 964 : ret += count_rtxs (XEXP (x, i));
13328 : 1470 : else if (fmt[i] == 'E')
13329 : 280 : for (j = 0; j < XVECLEN (x, i); j++)
13330 : 220 : ret += count_rtxs (XVECEXP (x, i, j));
13331 : :
13332 : : return ret;
13333 : : }
13334 : :
13335 : : /* Utility function for following routine. Called when X is part of a value
13336 : : being stored into last_set_value. Sets last_set_table_tick
13337 : : for each register mentioned. Similar to mention_regs in cse.cc */
13338 : :
13339 : : static void
13340 : 240063329 : update_table_tick (rtx x)
13341 : : {
13342 : 240692217 : enum rtx_code code = GET_CODE (x);
13343 : 240692217 : const char *fmt = GET_RTX_FORMAT (code);
13344 : 240692217 : int i, j;
13345 : :
13346 : 240692217 : if (code == REG)
13347 : : {
13348 : 81247667 : unsigned int regno = REGNO (x);
13349 : 81247667 : unsigned int endregno = END_REGNO (x);
13350 : 81247667 : unsigned int r;
13351 : :
13352 : 162612164 : for (r = regno; r < endregno; r++)
13353 : : {
13354 : 81364497 : reg_stat_type *rsp = ®_stat[r];
13355 : 81364497 : rsp->last_set_table_tick = label_tick;
13356 : : }
13357 : :
13358 : : return;
13359 : : }
13360 : :
13361 : 410647397 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13362 : 251949320 : if (fmt[i] == 'e')
13363 : : {
13364 : : /* Check for identical subexpressions. If x contains
13365 : : identical subexpression we only have to traverse one of
13366 : : them. */
13367 : 148529996 : if (i == 0 && ARITHMETIC_P (x))
13368 : : {
13369 : : /* Note that at this point x1 has already been
13370 : : processed. */
13371 : 58184524 : rtx x0 = XEXP (x, 0);
13372 : 58184524 : rtx x1 = XEXP (x, 1);
13373 : :
13374 : : /* If x0 and x1 are identical then there is no need to
13375 : : process x0. */
13376 : 58184524 : if (x0 == x1)
13377 : : break;
13378 : :
13379 : : /* If x0 is identical to a subexpression of x1 then while
13380 : : processing x1, x0 has already been processed. Thus we
13381 : : are done with x. */
13382 : 58067065 : if (ARITHMETIC_P (x1)
13383 : 437851 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13384 : : break;
13385 : :
13386 : : /* If x1 is identical to a subexpression of x0 then we
13387 : : still have to process the rest of x0. */
13388 : 58066939 : if (ARITHMETIC_P (x0)
13389 : 15969394 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13390 : : {
13391 : 628888 : update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13392 : 628888 : break;
13393 : : }
13394 : : }
13395 : :
13396 : 147783523 : update_table_tick (XEXP (x, i));
13397 : : }
13398 : 103419324 : else if (fmt[i] == 'E')
13399 : 8909130 : for (j = 0; j < XVECLEN (x, i); j++)
13400 : 6489097 : update_table_tick (XVECEXP (x, i, j));
13401 : : }
13402 : :
13403 : : /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13404 : : are saying that the register is clobbered and we no longer know its
13405 : : value. If INSN is zero, don't update reg_stat[].last_set; this is
13406 : : only permitted with VALUE also zero and is used to invalidate the
13407 : : register. */
13408 : :
13409 : : static void
13410 : 113087918 : record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13411 : : {
13412 : 113087918 : unsigned int regno = REGNO (reg);
13413 : 113087918 : unsigned int endregno = END_REGNO (reg);
13414 : 113087918 : unsigned int i;
13415 : 113087918 : reg_stat_type *rsp;
13416 : :
13417 : : /* If VALUE contains REG and we have a previous value for REG, substitute
13418 : : the previous value. */
13419 : 113087918 : if (value && insn && reg_overlap_mentioned_p (reg, value))
13420 : : {
13421 : 6115271 : rtx tem;
13422 : :
13423 : : /* Set things up so get_last_value is allowed to see anything set up to
13424 : : our insn. */
13425 : 6115271 : subst_low_luid = DF_INSN_LUID (insn);
13426 : 6115271 : tem = get_last_value (reg);
13427 : :
13428 : : /* If TEM is simply a binary operation with two CLOBBERs as operands,
13429 : : it isn't going to be useful and will take a lot of time to process,
13430 : : so just use the CLOBBER. */
13431 : :
13432 : 6115271 : if (tem)
13433 : : {
13434 : 2490068 : if (ARITHMETIC_P (tem)
13435 : 2266517 : && GET_CODE (XEXP (tem, 0)) == CLOBBER
13436 : 1060104 : && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13437 : : tem = XEXP (tem, 0);
13438 : 2488776 : else if (count_occurrences (value, reg, 1) >= 2)
13439 : : {
13440 : : /* If there are two or more occurrences of REG in VALUE,
13441 : : prevent the value from growing too much. */
13442 : 511 : if (count_rtxs (tem) > param_max_last_value_rtl)
13443 : 0 : tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13444 : : }
13445 : :
13446 : 2490068 : value = replace_rtx (copy_rtx (value), reg, tem);
13447 : : }
13448 : : }
13449 : :
13450 : : /* For each register modified, show we don't know its value, that
13451 : : we don't know about its bitwise content, that its value has been
13452 : : updated, and that we don't know the location of the death of the
13453 : : register. */
13454 : 226532172 : for (i = regno; i < endregno; i++)
13455 : : {
13456 : 113444254 : rsp = ®_stat[i];
13457 : :
13458 : 113444254 : if (insn)
13459 : 103494008 : rsp->last_set = insn;
13460 : :
13461 : 113444254 : rsp->last_set_value = 0;
13462 : 113444254 : rsp->last_set_mode = VOIDmode;
13463 : 113444254 : rsp->last_set_nonzero_bits = 0;
13464 : 113444254 : rsp->last_set_sign_bit_copies = 0;
13465 : 113444254 : rsp->last_death = 0;
13466 : 113444254 : rsp->truncated_to_mode = VOIDmode;
13467 : : }
13468 : :
13469 : : /* Mark registers that are being referenced in this value. */
13470 : 113087918 : if (value)
13471 : 85790709 : update_table_tick (value);
13472 : :
13473 : : /* Now update the status of each register being set.
13474 : : If someone is using this register in this block, set this register
13475 : : to invalid since we will get confused between the two lives in this
13476 : : basic block. This makes using this register always invalid. In cse, we
13477 : : scan the table to invalidate all entries using this register, but this
13478 : : is too much work for us. */
13479 : :
13480 : 226532172 : for (i = regno; i < endregno; i++)
13481 : : {
13482 : 113444254 : rsp = ®_stat[i];
13483 : 113444254 : rsp->last_set_label = label_tick;
13484 : 113444254 : if (!insn
13485 : 103494008 : || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13486 : 20242066 : rsp->last_set_invalid = true;
13487 : : else
13488 : 93202188 : rsp->last_set_invalid = false;
13489 : : }
13490 : :
13491 : : /* The value being assigned might refer to X (like in "x++;"). In that
13492 : : case, we must replace it with (clobber (const_int 0)) to prevent
13493 : : infinite loops. */
13494 : 113087918 : rsp = ®_stat[regno];
13495 : 113087918 : if (value && !get_last_value_validate (&value, insn, label_tick, false))
13496 : : {
13497 : 11156609 : value = copy_rtx (value);
13498 : 11156609 : if (!get_last_value_validate (&value, insn, label_tick, true))
13499 : 0 : value = 0;
13500 : : }
13501 : :
13502 : : /* For the main register being modified, update the value, the mode, the
13503 : : nonzero bits, and the number of sign bit copies. */
13504 : :
13505 : 113087918 : rsp->last_set_value = value;
13506 : :
13507 : 113087918 : if (value)
13508 : : {
13509 : 85790709 : machine_mode mode = GET_MODE (reg);
13510 : 85790709 : subst_low_luid = DF_INSN_LUID (insn);
13511 : 85790709 : rsp->last_set_mode = mode;
13512 : 85790709 : if (GET_MODE_CLASS (mode) == MODE_INT
13513 : 85790709 : && HWI_COMPUTABLE_MODE_P (mode))
13514 : 65061726 : mode = nonzero_bits_mode;
13515 : 85790709 : rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13516 : 85790709 : rsp->last_set_sign_bit_copies
13517 : 85790709 : = num_sign_bit_copies (value, GET_MODE (reg));
13518 : : }
13519 : 113087918 : }
13520 : :
13521 : : /* Called via note_stores from record_dead_and_set_regs to handle one
13522 : : SET or CLOBBER in an insn. DATA is the instruction in which the
13523 : : set is occurring. */
13524 : :
13525 : : static void
13526 : 134807323 : record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13527 : : {
13528 : 134807323 : rtx_insn *record_dead_insn = (rtx_insn *) data;
13529 : :
13530 : 134807323 : if (GET_CODE (dest) == SUBREG)
13531 : 5 : dest = SUBREG_REG (dest);
13532 : :
13533 : 134807323 : if (!record_dead_insn)
13534 : : {
13535 : 5046740 : if (REG_P (dest))
13536 : 5046740 : record_value_for_reg (dest, NULL, NULL_RTX);
13537 : 5046740 : return;
13538 : : }
13539 : :
13540 : 129760583 : if (REG_P (dest))
13541 : : {
13542 : : /* If we are setting the whole register, we know its value. */
13543 : 103320692 : if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13544 : 85635202 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13545 : : /* We can handle a SUBREG if it's the low part, but we must be
13546 : : careful with paradoxical SUBREGs on RISC architectures because
13547 : : we cannot strip e.g. an extension around a load and record the
13548 : : naked load since the RTL middle-end considers that the upper bits
13549 : : are defined according to LOAD_EXTEND_OP. */
13550 : 17685490 : else if (GET_CODE (setter) == SET
13551 : 586972 : && GET_CODE (SET_DEST (setter)) == SUBREG
13552 : 575205 : && SUBREG_REG (SET_DEST (setter)) == dest
13553 : 931270 : && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13554 : : BITS_PER_WORD)
13555 : 17791280 : && subreg_lowpart_p (SET_DEST (setter)))
13556 : : {
13557 : 105790 : if (WORD_REGISTER_OPERATIONS
13558 : : && word_register_operation_p (SET_SRC (setter))
13559 : : && paradoxical_subreg_p (SET_DEST (setter)))
13560 : : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13561 : 105790 : else if (!partial_subreg_p (SET_DEST (setter)))
13562 : 93866 : record_value_for_reg (dest, record_dead_insn,
13563 : 93866 : gen_lowpart (GET_MODE (dest),
13564 : 93866 : SET_SRC (setter)));
13565 : : else
13566 : : {
13567 : 11924 : record_value_for_reg (dest, record_dead_insn,
13568 : 11924 : gen_lowpart (GET_MODE (dest),
13569 : 11924 : SET_SRC (setter)));
13570 : :
13571 : 11924 : unsigned HOST_WIDE_INT mask;
13572 : 11924 : reg_stat_type *rsp = ®_stat[REGNO (dest)];
13573 : 11924 : mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13574 : 11924 : rsp->last_set_nonzero_bits |= ~mask;
13575 : 11924 : rsp->last_set_sign_bit_copies = 1;
13576 : : }
13577 : : }
13578 : : /* Otherwise show that we don't know the value. */
13579 : : else
13580 : 17579700 : record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13581 : : }
13582 : 26439891 : else if (MEM_P (dest)
13583 : : /* Ignore pushes, they clobber nothing. */
13584 : 26439891 : && ! push_operand (dest, GET_MODE (dest)))
13585 : 13475476 : mem_last_set = DF_INSN_LUID (record_dead_insn);
13586 : : }
13587 : :
13588 : : /* Update the records of when each REG was most recently set or killed
13589 : : for the things done by INSN. This is the last thing done in processing
13590 : : INSN in the combiner loop.
13591 : :
13592 : : We update reg_stat[], in particular fields last_set, last_set_value,
13593 : : last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13594 : : last_death, and also the similar information mem_last_set (which insn
13595 : : most recently modified memory) and last_call_luid (which insn was the
13596 : : most recent subroutine call). */
13597 : :
13598 : : static void
13599 : 170351184 : record_dead_and_set_regs (rtx_insn *insn)
13600 : : {
13601 : 170351184 : rtx link;
13602 : 170351184 : unsigned int i;
13603 : :
13604 : 305869899 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13605 : : {
13606 : 135518715 : if (REG_NOTE_KIND (link) == REG_DEAD
13607 : 77494897 : && REG_P (XEXP (link, 0)))
13608 : : {
13609 : 77494897 : unsigned int regno = REGNO (XEXP (link, 0));
13610 : 77494897 : unsigned int endregno = END_REGNO (XEXP (link, 0));
13611 : :
13612 : 155189258 : for (i = regno; i < endregno; i++)
13613 : : {
13614 : 77694361 : reg_stat_type *rsp;
13615 : :
13616 : 77694361 : rsp = ®_stat[i];
13617 : 77694361 : rsp->last_death = insn;
13618 : : }
13619 : : }
13620 : 58023818 : else if (REG_NOTE_KIND (link) == REG_INC)
13621 : 0 : record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13622 : : }
13623 : :
13624 : 170351184 : if (CALL_P (insn))
13625 : : {
13626 : 9303727 : HARD_REG_SET callee_clobbers
13627 : 9303727 : = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13628 : 9303727 : hard_reg_set_iterator hrsi;
13629 : 768289964 : EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13630 : : {
13631 : 758986237 : reg_stat_type *rsp;
13632 : :
13633 : : /* ??? We could try to preserve some information from the last
13634 : : set of register I if the call doesn't actually clobber
13635 : : (reg:last_set_mode I), which might be true for ABIs with
13636 : : partial clobbers. However, it would be difficult to
13637 : : update last_set_nonzero_bits and last_sign_bit_copies
13638 : : to account for the part of I that actually was clobbered.
13639 : : It wouldn't help much anyway, since we rarely see this
13640 : : situation before RA. */
13641 : 758986237 : rsp = ®_stat[i];
13642 : 758986237 : rsp->last_set_invalid = true;
13643 : 758986237 : rsp->last_set = insn;
13644 : 758986237 : rsp->last_set_value = 0;
13645 : 758986237 : rsp->last_set_mode = VOIDmode;
13646 : 758986237 : rsp->last_set_nonzero_bits = 0;
13647 : 758986237 : rsp->last_set_sign_bit_copies = 0;
13648 : 758986237 : rsp->last_death = 0;
13649 : 758986237 : rsp->truncated_to_mode = VOIDmode;
13650 : : }
13651 : :
13652 : 9303727 : last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13653 : :
13654 : : /* We can't combine into a call pattern. Remember, though, that
13655 : : the return value register is set at this LUID. We could
13656 : : still replace a register with the return value from the
13657 : : wrong subroutine call! */
13658 : 9303727 : note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13659 : : }
13660 : : else
13661 : 161047457 : note_stores (insn, record_dead_and_set_regs_1, insn);
13662 : 170351184 : }
13663 : :
13664 : : /* If a SUBREG has the promoted bit set, it is in fact a property of the
13665 : : register present in the SUBREG, so for each such SUBREG go back and
13666 : : adjust nonzero and sign bit information of the registers that are
13667 : : known to have some zero/sign bits set.
13668 : :
13669 : : This is needed because when combine blows the SUBREGs away, the
13670 : : information on zero/sign bits is lost and further combines can be
13671 : : missed because of that. */
13672 : :
13673 : : static void
13674 : 5667 : record_promoted_value (rtx_insn *insn, rtx subreg)
13675 : : {
13676 : 5667 : struct insn_link *links;
13677 : 5667 : rtx set;
13678 : 5667 : unsigned int regno = REGNO (SUBREG_REG (subreg));
13679 : 5667 : machine_mode mode = GET_MODE (subreg);
13680 : :
13681 : 5667 : if (!HWI_COMPUTABLE_MODE_P (mode))
13682 : : return;
13683 : :
13684 : 6188 : for (links = LOG_LINKS (insn); links;)
13685 : : {
13686 : 5564 : reg_stat_type *rsp;
13687 : :
13688 : 5564 : insn = links->insn;
13689 : 5564 : set = single_set (insn);
13690 : :
13691 : 5564 : if (! set || !REG_P (SET_DEST (set))
13692 : 5564 : || REGNO (SET_DEST (set)) != regno
13693 : 10735 : || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13694 : : {
13695 : 393 : links = links->next;
13696 : 393 : continue;
13697 : : }
13698 : :
13699 : 5171 : rsp = ®_stat[regno];
13700 : 5171 : if (rsp->last_set == insn)
13701 : : {
13702 : 5171 : if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13703 : 5171 : rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13704 : : }
13705 : :
13706 : 5171 : if (REG_P (SET_SRC (set)))
13707 : : {
13708 : 128 : regno = REGNO (SET_SRC (set));
13709 : 128 : links = LOG_LINKS (insn);
13710 : : }
13711 : : else
13712 : : break;
13713 : : }
13714 : : }
13715 : :
13716 : : /* Check if X, a register, is known to contain a value already
13717 : : truncated to MODE. In this case we can use a subreg to refer to
13718 : : the truncated value even though in the generic case we would need
13719 : : an explicit truncation. */
13720 : :
13721 : : static bool
13722 : 0 : reg_truncated_to_mode (machine_mode mode, const_rtx x)
13723 : : {
13724 : 0 : reg_stat_type *rsp = ®_stat[REGNO (x)];
13725 : 0 : machine_mode truncated = rsp->truncated_to_mode;
13726 : :
13727 : 0 : if (truncated == 0
13728 : 0 : || rsp->truncation_label < label_tick_ebb_start)
13729 : : return false;
13730 : 0 : if (!partial_subreg_p (mode, truncated))
13731 : : return true;
13732 : 0 : if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13733 : : return true;
13734 : : return false;
13735 : : }
13736 : :
13737 : : /* If X is a hard reg or a subreg record the mode that the register is
13738 : : accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13739 : : able to turn a truncate into a subreg using this information. Return true
13740 : : if traversing X is complete. */
13741 : :
13742 : : static bool
13743 : 194974164 : record_truncated_value (rtx x)
13744 : : {
13745 : 194974164 : machine_mode truncated_mode;
13746 : 194974164 : reg_stat_type *rsp;
13747 : :
13748 : 194974164 : if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13749 : : {
13750 : 1726148 : machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13751 : 1726148 : truncated_mode = GET_MODE (x);
13752 : :
13753 : 1726148 : if (!partial_subreg_p (truncated_mode, original_mode))
13754 : : return true;
13755 : :
13756 : 1085240 : truncated_mode = GET_MODE (x);
13757 : 1085240 : if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13758 : : return true;
13759 : :
13760 : 0 : x = SUBREG_REG (x);
13761 : 0 : }
13762 : : /* ??? For hard-regs we now record everything. We might be able to
13763 : : optimize this using last_set_mode. */
13764 : 193248016 : else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13765 : 20753844 : truncated_mode = GET_MODE (x);
13766 : : else
13767 : : return false;
13768 : :
13769 : 20753844 : rsp = ®_stat[REGNO (x)];
13770 : 20753844 : if (rsp->truncated_to_mode == 0
13771 : 9689512 : || rsp->truncation_label < label_tick_ebb_start
13772 : 29164319 : || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13773 : : {
13774 : 12343962 : rsp->truncated_to_mode = truncated_mode;
13775 : 12343962 : rsp->truncation_label = label_tick;
13776 : : }
13777 : :
13778 : : return true;
13779 : : }
13780 : :
13781 : : /* Callback for note_uses. Find hardregs and subregs of pseudos and
13782 : : the modes they are used in. This can help truning TRUNCATEs into
13783 : : SUBREGs. */
13784 : :
13785 : : static void
13786 : 74889131 : record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13787 : : {
13788 : 74889131 : subrtx_var_iterator::array_type array;
13789 : 269863295 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13790 : 194974164 : if (record_truncated_value (*iter))
13791 : 22479992 : iter.skip_subrtxes ();
13792 : 74889131 : }
13793 : :
13794 : : /* Scan X for promoted SUBREGs. For each one found,
13795 : : note what it implies to the registers used in it. */
13796 : :
13797 : : static void
13798 : 355759168 : check_promoted_subreg (rtx_insn *insn, rtx x)
13799 : : {
13800 : 355759168 : if (GET_CODE (x) == SUBREG
13801 : 2094498 : && SUBREG_PROMOTED_VAR_P (x)
13802 : 355764835 : && REG_P (SUBREG_REG (x)))
13803 : 5667 : record_promoted_value (insn, x);
13804 : : else
13805 : : {
13806 : 355753501 : const char *format = GET_RTX_FORMAT (GET_CODE (x));
13807 : 355753501 : int i, j;
13808 : :
13809 : 855567905 : for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13810 : 499814404 : switch (format[i])
13811 : : {
13812 : 266051671 : case 'e':
13813 : 266051671 : check_promoted_subreg (insn, XEXP (x, i));
13814 : 266051671 : break;
13815 : 11611476 : case 'V':
13816 : 11611476 : case 'E':
13817 : 11611476 : if (XVEC (x, i) != 0)
13818 : 35838845 : for (j = 0; j < XVECLEN (x, i); j++)
13819 : 24227369 : check_promoted_subreg (insn, XVECEXP (x, i, j));
13820 : : break;
13821 : : }
13822 : : }
13823 : 355759168 : }
13824 : :
13825 : : /* Verify that all the registers and memory references mentioned in *LOC are
13826 : : still valid. *LOC was part of a value set in INSN when label_tick was
13827 : : equal to TICK. Return false if some are not. If REPLACE is true, replace
13828 : : the invalid references with (clobber (const_int 0)) and return true. This
13829 : : replacement is useful because we often can get useful information about
13830 : : the form of a value (e.g., if it was produced by a shift that always
13831 : : produces -1 or 0) even though we don't know exactly what registers it
13832 : : was produced from. */
13833 : :
13834 : : static bool
13835 : 488855274 : get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13836 : : {
13837 : 488855274 : rtx x = *loc;
13838 : 488855274 : const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13839 : 488855274 : int len = GET_RTX_LENGTH (GET_CODE (x));
13840 : 488855274 : int i, j;
13841 : :
13842 : 488855274 : if (REG_P (x))
13843 : : {
13844 : 156496319 : unsigned int regno = REGNO (x);
13845 : 156496319 : unsigned int endregno = END_REGNO (x);
13846 : 156496319 : unsigned int j;
13847 : :
13848 : 288923384 : for (j = regno; j < endregno; j++)
13849 : : {
13850 : 156522455 : reg_stat_type *rsp = ®_stat[j];
13851 : 156522455 : if (rsp->last_set_invalid
13852 : : /* If this is a pseudo-register that was only set once and not
13853 : : live at the beginning of the function, it is always valid. */
13854 : 258718016 : || (! (regno >= FIRST_PSEUDO_REGISTER
13855 : 117705154 : && regno < reg_n_sets_max
13856 : 117657708 : && REG_N_SETS (regno) == 1
13857 : 204391122 : && (!REGNO_REG_SET_P
13858 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13859 : : regno)))
13860 : 30469664 : && rsp->last_set_label > tick))
13861 : : {
13862 : 24095390 : if (replace)
13863 : 12446761 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13864 : 24095390 : return replace;
13865 : : }
13866 : : }
13867 : :
13868 : : return true;
13869 : : }
13870 : : /* If this is a memory reference, make sure that there were no stores after
13871 : : it that might have clobbered the value. We don't have alias info, so we
13872 : : assume any store invalidates it. Moreover, we only have local UIDs, so
13873 : : we also assume that there were stores in the intervening basic blocks. */
13874 : 33224509 : else if (MEM_P (x) && !MEM_READONLY_P (x)
13875 : 363485060 : && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13876 : : {
13877 : 7164476 : if (replace)
13878 : 3585024 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13879 : 7164476 : return replace;
13880 : : }
13881 : :
13882 : 811569029 : for (i = 0; i < len; i++)
13883 : : {
13884 : 498088207 : if (fmt[i] == 'e')
13885 : : {
13886 : : /* Check for identical subexpressions. If x contains
13887 : : identical subexpression we only have to traverse one of
13888 : : them. */
13889 : 310283814 : if (i == 1 && ARITHMETIC_P (x))
13890 : : {
13891 : : /* Note that at this point x0 has already been checked
13892 : : and found valid. */
13893 : 115715314 : rtx x0 = XEXP (x, 0);
13894 : 115715314 : rtx x1 = XEXP (x, 1);
13895 : :
13896 : : /* If x0 and x1 are identical then x is also valid. */
13897 : 115715314 : if (x0 == x1)
13898 : : return true;
13899 : :
13900 : : /* If x1 is identical to a subexpression of x0 then
13901 : : while checking x0, x1 has already been checked. Thus
13902 : : it is valid and so as x. */
13903 : 115348604 : if (ARITHMETIC_P (x0)
13904 : 32690353 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13905 : : return true;
13906 : :
13907 : : /* If x0 is identical to a subexpression of x1 then x is
13908 : : valid iff the rest of x1 is valid. */
13909 : 113430720 : if (ARITHMETIC_P (x1)
13910 : 1299594 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13911 : 397 : return
13912 : 434 : get_last_value_validate (&XEXP (x1,
13913 : : x0 == XEXP (x1, 0) ? 1 : 0),
13914 : 397 : insn, tick, replace);
13915 : : }
13916 : :
13917 : 307998823 : if (!get_last_value_validate (&XEXP (x, i), insn, tick, replace))
13918 : : return false;
13919 : : }
13920 : 187804393 : else if (fmt[i] == 'E')
13921 : 27422830 : for (j = 0; j < XVECLEN (x, i); j++)
13922 : 21742392 : if (!get_last_value_validate (&XVECEXP (x, i, j),
13923 : : insn, tick, replace))
13924 : : return false;
13925 : : }
13926 : :
13927 : : /* If we haven't found a reason for it to be invalid, it is valid. */
13928 : : return true;
13929 : : }
13930 : :
13931 : : /* Get the last value assigned to X, if known. Some registers
13932 : : in the value may be replaced with (clobber (const_int 0)) if their value
13933 : : is known longer known reliably. */
13934 : :
13935 : : static rtx
13936 : 228547582 : get_last_value (const_rtx x)
13937 : : {
13938 : 228547582 : unsigned int regno;
13939 : 228547582 : rtx value;
13940 : 228547582 : reg_stat_type *rsp;
13941 : :
13942 : : /* If this is a non-paradoxical SUBREG, get the value of its operand and
13943 : : then convert it to the desired mode. If this is a paradoxical SUBREG,
13944 : : we cannot predict what values the "extra" bits might have. */
13945 : 228547582 : if (GET_CODE (x) == SUBREG
13946 : 13102907 : && subreg_lowpart_p (x)
13947 : 12599483 : && !paradoxical_subreg_p (x)
13948 : 236054246 : && (value = get_last_value (SUBREG_REG (x))) != 0)
13949 : 3677454 : return gen_lowpart (GET_MODE (x), value);
13950 : :
13951 : 224870128 : if (!REG_P (x))
13952 : : return 0;
13953 : :
13954 : 196110661 : regno = REGNO (x);
13955 : 196110661 : rsp = ®_stat[regno];
13956 : 196110661 : value = rsp->last_set_value;
13957 : :
13958 : : /* If we don't have a value, or if it isn't for this basic block and
13959 : : it's either a hard register, set more than once, or it's a live
13960 : : at the beginning of the function, return 0.
13961 : :
13962 : : Because if it's not live at the beginning of the function then the reg
13963 : : is always set before being used (is never used without being set).
13964 : : And, if it's set only once, and it's always set before use, then all
13965 : : uses must have the same last value, even if it's not from this basic
13966 : : block. */
13967 : :
13968 : 196110661 : if (value == 0
13969 : 196110661 : || (rsp->last_set_label < label_tick_ebb_start
13970 : 77133828 : && (regno < FIRST_PSEUDO_REGISTER
13971 : 76266803 : || regno >= reg_n_sets_max
13972 : 76266803 : || REG_N_SETS (regno) != 1
13973 : 15732704 : || REGNO_REG_SET_P
13974 : : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13975 : 114329180 : return 0;
13976 : :
13977 : : /* If the value was set in a later insn than the ones we are processing,
13978 : : we can't use it even if the register was only set once. */
13979 : 81781481 : if (rsp->last_set_label == label_tick
13980 : 81781481 : && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13981 : : return 0;
13982 : :
13983 : : /* If fewer bits were set than what we are asked for now, we cannot use
13984 : : the value. */
13985 : 58096294 : if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13986 : 58096294 : GET_MODE_PRECISION (GET_MODE (x))))
13987 : : return 0;
13988 : :
13989 : : /* If the value has all its registers valid, return it. */
13990 : 58094872 : if (get_last_value_validate (&value, rsp->last_set,
13991 : : rsp->last_set_label, false))
13992 : 54023400 : return value;
13993 : :
13994 : : /* Otherwise, make a copy and replace any invalid register with
13995 : : (clobber (const_int 0)). If that fails for some reason, return 0. */
13996 : :
13997 : 4071472 : value = copy_rtx (value);
13998 : 4071472 : if (get_last_value_validate (&value, rsp->last_set,
13999 : : rsp->last_set_label, true))
14000 : 4071472 : return value;
14001 : :
14002 : : return 0;
14003 : : }
14004 : :
14005 : : /* Define three variables used for communication between the following
14006 : : routines. */
14007 : :
14008 : : static unsigned int reg_dead_regno, reg_dead_endregno;
14009 : : static int reg_dead_flag;
14010 : : rtx reg_dead_reg;
14011 : :
14012 : : /* Function called via note_stores from reg_dead_at_p.
14013 : :
14014 : : If DEST is within [reg_dead_regno, reg_dead_endregno), set
14015 : : reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
14016 : :
14017 : : static void
14018 : 611659 : reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
14019 : : {
14020 : 611659 : unsigned int regno, endregno;
14021 : :
14022 : 611659 : if (!REG_P (dest))
14023 : : return;
14024 : :
14025 : 566603 : regno = REGNO (dest);
14026 : 566603 : endregno = END_REGNO (dest);
14027 : 566603 : if (reg_dead_endregno > regno && reg_dead_regno < endregno)
14028 : 270354 : reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
14029 : : }
14030 : :
14031 : : /* Return true if REG is known to be dead at INSN.
14032 : :
14033 : : We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
14034 : : referencing REG, it is dead. If we hit a SET referencing REG, it is
14035 : : live. Otherwise, see if it is live or dead at the start of the basic
14036 : : block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
14037 : : must be assumed to be always live. */
14038 : :
14039 : : static bool
14040 : 1677770 : reg_dead_at_p (rtx reg, rtx_insn *insn)
14041 : : {
14042 : 1677770 : basic_block block;
14043 : 1677770 : unsigned int i;
14044 : :
14045 : : /* Set variables for reg_dead_at_p_1. */
14046 : 1677770 : reg_dead_regno = REGNO (reg);
14047 : 1677770 : reg_dead_endregno = END_REGNO (reg);
14048 : 1677770 : reg_dead_reg = reg;
14049 : :
14050 : 1677770 : reg_dead_flag = 0;
14051 : :
14052 : : /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
14053 : : we allow the machine description to decide whether use-and-clobber
14054 : : patterns are OK. */
14055 : 1677770 : if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
14056 : : {
14057 : 3355540 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14058 : 1677770 : if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
14059 : : return false;
14060 : : }
14061 : :
14062 : : /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
14063 : : beginning of basic block. */
14064 : 1677770 : block = BLOCK_FOR_INSN (insn);
14065 : 821381 : for (;;)
14066 : : {
14067 : 2499151 : if (INSN_P (insn))
14068 : : {
14069 : 2347735 : if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
14070 : : return true;
14071 : :
14072 : 864983 : note_stores (insn, reg_dead_at_p_1, NULL);
14073 : 864983 : if (reg_dead_flag)
14074 : 135177 : return reg_dead_flag == 1 ? 1 : 0;
14075 : :
14076 : 729806 : if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
14077 : : return true;
14078 : : }
14079 : :
14080 : 852698 : if (insn == BB_HEAD (block))
14081 : : break;
14082 : :
14083 : 821381 : insn = PREV_INSN (insn);
14084 : : }
14085 : :
14086 : : /* Look at live-in sets for the basic block that we were in. */
14087 : 62634 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14088 : 31317 : if (REGNO_REG_SET_P (df_get_live_in (block), i))
14089 : : return false;
14090 : :
14091 : : return true;
14092 : : }
14093 : :
14094 : : /* Note hard registers in X that are used. */
14095 : :
14096 : : static void
14097 : 279910280 : mark_used_regs_combine (rtx x)
14098 : : {
14099 : 323743769 : RTX_CODE code = GET_CODE (x);
14100 : 323743769 : unsigned int regno;
14101 : 323743769 : int i;
14102 : :
14103 : 323743769 : switch (code)
14104 : : {
14105 : : case LABEL_REF:
14106 : : case SYMBOL_REF:
14107 : : case CONST:
14108 : : CASE_CONST_ANY:
14109 : : case PC:
14110 : : case ADDR_VEC:
14111 : : case ADDR_DIFF_VEC:
14112 : : case ASM_INPUT:
14113 : : return;
14114 : :
14115 : 7606982 : case CLOBBER:
14116 : : /* If we are clobbering a MEM, mark any hard registers inside the
14117 : : address as used. */
14118 : 7606982 : if (MEM_P (XEXP (x, 0)))
14119 : 5514 : mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
14120 : : return;
14121 : :
14122 : 74009472 : case REG:
14123 : 74009472 : regno = REGNO (x);
14124 : : /* A hard reg in a wide mode may really be multiple registers.
14125 : : If so, mark all of them just like the first. */
14126 : 74009472 : if (regno < FIRST_PSEUDO_REGISTER)
14127 : : {
14128 : : /* None of this applies to the stack, frame or arg pointers. */
14129 : 9083112 : if (regno == STACK_POINTER_REGNUM
14130 : 9083112 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14131 : : && regno == HARD_FRAME_POINTER_REGNUM)
14132 : 8170094 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14133 : 1073561 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14134 : 7096533 : || regno == FRAME_POINTER_REGNUM)
14135 : : return;
14136 : :
14137 : 1619433 : add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
14138 : : }
14139 : : return;
14140 : :
14141 : 43827975 : case SET:
14142 : 43827975 : {
14143 : : /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14144 : : the address. */
14145 : 43827975 : rtx testreg = SET_DEST (x);
14146 : :
14147 : 43827975 : while (GET_CODE (testreg) == SUBREG
14148 : 43843452 : || GET_CODE (testreg) == ZERO_EXTRACT
14149 : 88016886 : || GET_CODE (testreg) == STRICT_LOW_PART)
14150 : 353869 : testreg = XEXP (testreg, 0);
14151 : :
14152 : 43827975 : if (MEM_P (testreg))
14153 : 4803198 : mark_used_regs_combine (XEXP (testreg, 0));
14154 : :
14155 : 43827975 : mark_used_regs_combine (SET_SRC (x));
14156 : : }
14157 : 43827975 : return;
14158 : :
14159 : 128736895 : default:
14160 : 128736895 : break;
14161 : : }
14162 : :
14163 : : /* Recursively scan the operands of this expression. */
14164 : :
14165 : 128736895 : {
14166 : 128736895 : const char *fmt = GET_RTX_FORMAT (code);
14167 : :
14168 : 372553670 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14169 : : {
14170 : 243816775 : if (fmt[i] == 'e')
14171 : 198569680 : mark_used_regs_combine (XEXP (x, i));
14172 : 45247095 : else if (fmt[i] == 'E')
14173 : : {
14174 : : int j;
14175 : :
14176 : 63777637 : for (j = 0; j < XVECLEN (x, i); j++)
14177 : 44249808 : mark_used_regs_combine (XVECEXP (x, i, j));
14178 : : }
14179 : : }
14180 : : }
14181 : : }
14182 : :
14183 : : /* Remove register number REGNO from the dead registers list of INSN.
14184 : :
14185 : : Return the note used to record the death, if there was one. */
14186 : :
14187 : : rtx
14188 : 3060509 : remove_death (unsigned int regno, rtx_insn *insn)
14189 : : {
14190 : 3060509 : rtx note = find_regno_note (insn, REG_DEAD, regno);
14191 : :
14192 : 3060509 : if (note)
14193 : 458776 : remove_note (insn, note);
14194 : :
14195 : 3060509 : return note;
14196 : : }
14197 : :
14198 : : /* For each register (hardware or pseudo) used within expression X, if its
14199 : : death is in an instruction with luid between FROM_LUID (inclusive) and
14200 : : TO_INSN (exclusive), put a REG_DEAD note for that register in the
14201 : : list headed by PNOTES.
14202 : :
14203 : : That said, don't move registers killed by maybe_kill_insn.
14204 : :
14205 : : This is done when X is being merged by combination into TO_INSN. These
14206 : : notes will then be distributed as needed. */
14207 : :
14208 : : static void
14209 : 23349273 : move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14210 : : rtx *pnotes)
14211 : : {
14212 : 23834169 : const char *fmt;
14213 : 23834169 : int len, i;
14214 : 23834169 : enum rtx_code code = GET_CODE (x);
14215 : :
14216 : 23834169 : if (code == REG)
14217 : : {
14218 : 5930785 : unsigned int regno = REGNO (x);
14219 : 5930785 : rtx_insn *where_dead = reg_stat[regno].last_death;
14220 : :
14221 : : /* If we do not know where the register died, it may still die between
14222 : : FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14223 : 5930785 : if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14224 : : {
14225 : 3141410 : rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14226 : 3141410 : while (insn
14227 : 4685857 : && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14228 : 8700374 : && DF_INSN_LUID (insn) >= from_luid)
14229 : : {
14230 : 2133935 : if (dead_or_set_regno_p (insn, regno))
14231 : : {
14232 : 559636 : if (find_regno_note (insn, REG_DEAD, regno))
14233 : 5930785 : where_dead = insn;
14234 : : break;
14235 : : }
14236 : :
14237 : 1574299 : insn = prev_real_nondebug_insn (insn);
14238 : : }
14239 : : }
14240 : :
14241 : : /* Don't move the register if it gets killed in between from and to. */
14242 : 148777 : if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14243 : 5977127 : && ! reg_referenced_p (x, maybe_kill_insn))
14244 : : return;
14245 : :
14246 : 5884443 : if (where_dead
14247 : 3134993 : && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14248 : 2962029 : && DF_INSN_LUID (where_dead) >= from_luid
14249 : 8846287 : && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14250 : : {
14251 : 2679718 : rtx note = remove_death (regno, where_dead);
14252 : :
14253 : : /* It is possible for the call above to return 0. This can occur
14254 : : when last_death points to I2 or I1 that we combined with.
14255 : : In that case make a new note.
14256 : :
14257 : : We must also check for the case where X is a hard register
14258 : : and NOTE is a death note for a range of hard registers
14259 : : including X. In that case, we must put REG_DEAD notes for
14260 : : the remaining registers in place of NOTE. */
14261 : :
14262 : 2679718 : if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14263 : 2679718 : && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14264 : : {
14265 : 0 : unsigned int deadregno = REGNO (XEXP (note, 0));
14266 : 0 : unsigned int deadend = END_REGNO (XEXP (note, 0));
14267 : 0 : unsigned int ourend = END_REGNO (x);
14268 : 0 : unsigned int i;
14269 : :
14270 : 0 : for (i = deadregno; i < deadend; i++)
14271 : 0 : if (i < regno || i >= ourend)
14272 : 0 : add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14273 : : }
14274 : :
14275 : : /* If we didn't find any note, or if we found a REG_DEAD note that
14276 : : covers only part of the given reg, and we have a multi-reg hard
14277 : : register, then to be safe we must check for REG_DEAD notes
14278 : : for each register other than the first. They could have
14279 : : their own REG_DEAD notes lying around. */
14280 : 2679718 : else if ((note == 0
14281 : : || (note != 0
14282 : 78024 : && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14283 : 78024 : GET_MODE (x))))
14284 : 2601694 : && regno < FIRST_PSEUDO_REGISTER
14285 : 2971689 : && REG_NREGS (x) > 1)
14286 : : {
14287 : 0 : unsigned int ourend = END_REGNO (x);
14288 : 0 : unsigned int i, offset;
14289 : 0 : rtx oldnotes = 0;
14290 : :
14291 : 0 : if (note)
14292 : 0 : offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14293 : : else
14294 : : offset = 1;
14295 : :
14296 : 0 : for (i = regno + offset; i < ourend; i++)
14297 : 0 : move_deaths (regno_reg_rtx[i],
14298 : : maybe_kill_insn, from_luid, to_insn, &oldnotes);
14299 : : }
14300 : :
14301 : 2679718 : if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14302 : : {
14303 : 78000 : XEXP (note, 1) = *pnotes;
14304 : 78000 : *pnotes = note;
14305 : : }
14306 : : else
14307 : 2601718 : *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14308 : : }
14309 : :
14310 : 5884443 : return;
14311 : : }
14312 : :
14313 : 17903384 : else if (GET_CODE (x) == SET)
14314 : : {
14315 : 4015223 : rtx dest = SET_DEST (x);
14316 : :
14317 : 4015223 : move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14318 : :
14319 : : /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14320 : : that accesses one word of a multi-word item, some
14321 : : piece of everything register in the expression is used by
14322 : : this insn, so remove any old death. */
14323 : : /* ??? So why do we test for equality of the sizes? */
14324 : :
14325 : 4015223 : if (GET_CODE (dest) == ZERO_EXTRACT
14326 : 4014827 : || GET_CODE (dest) == STRICT_LOW_PART
14327 : 8028534 : || (GET_CODE (dest) == SUBREG
14328 : 79912 : && !read_modify_subreg_p (dest)))
14329 : : {
14330 : 66773 : move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14331 : 66773 : return;
14332 : : }
14333 : :
14334 : : /* If this is some other SUBREG, we know it replaces the entire
14335 : : value, so use that as the destination. */
14336 : 3948450 : if (GET_CODE (dest) == SUBREG)
14337 : 15051 : dest = SUBREG_REG (dest);
14338 : :
14339 : : /* If this is a MEM, adjust deaths of anything used in the address.
14340 : : For a REG (the only other possibility), the entire value is
14341 : : being replaced so the old value is not used in this insn. */
14342 : :
14343 : 3948450 : if (MEM_P (dest))
14344 : 418123 : move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14345 : : to_insn, pnotes);
14346 : : return;
14347 : : }
14348 : :
14349 : 13888161 : else if (GET_CODE (x) == CLOBBER)
14350 : : return;
14351 : :
14352 : 13293563 : len = GET_RTX_LENGTH (code);
14353 : 13293563 : fmt = GET_RTX_FORMAT (code);
14354 : :
14355 : 34426443 : for (i = 0; i < len; i++)
14356 : : {
14357 : 21132880 : if (fmt[i] == 'E')
14358 : : {
14359 : 937920 : int j;
14360 : 3338703 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14361 : 2400783 : move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14362 : : to_insn, pnotes);
14363 : : }
14364 : 20194960 : else if (fmt[i] == 'e')
14365 : 12965552 : move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14366 : : }
14367 : : }
14368 : :
14369 : : /* Return true if X is the target of a bit-field assignment in BODY, the
14370 : : pattern of an insn. X must be a REG. */
14371 : :
14372 : : static bool
14373 : 4705671 : reg_bitfield_target_p (rtx x, rtx body)
14374 : : {
14375 : 4705671 : int i;
14376 : :
14377 : 4705671 : if (GET_CODE (body) == SET)
14378 : : {
14379 : 3381738 : rtx dest = SET_DEST (body);
14380 : 3381738 : rtx target;
14381 : 3381738 : unsigned int regno, tregno, endregno, endtregno;
14382 : :
14383 : 3381738 : if (GET_CODE (dest) == ZERO_EXTRACT)
14384 : 376 : target = XEXP (dest, 0);
14385 : 3381362 : else if (GET_CODE (dest) == STRICT_LOW_PART)
14386 : 1772 : target = SUBREG_REG (XEXP (dest, 0));
14387 : : else
14388 : : return false;
14389 : :
14390 : 2148 : if (GET_CODE (target) == SUBREG)
14391 : 227 : target = SUBREG_REG (target);
14392 : :
14393 : 2148 : if (!REG_P (target))
14394 : : return false;
14395 : :
14396 : 2121 : tregno = REGNO (target), regno = REGNO (x);
14397 : 2121 : if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14398 : 2111 : return target == x;
14399 : :
14400 : 10 : endtregno = end_hard_regno (GET_MODE (target), tregno);
14401 : 10 : endregno = end_hard_regno (GET_MODE (x), regno);
14402 : :
14403 : 10 : return endregno > tregno && regno < endtregno;
14404 : : }
14405 : :
14406 : 1323933 : else if (GET_CODE (body) == PARALLEL)
14407 : 1937881 : for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14408 : 1301181 : if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14409 : : return true;
14410 : :
14411 : : return false;
14412 : : }
14413 : :
14414 : : /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14415 : : as appropriate. I3 and I2 are the insns resulting from the combination
14416 : : insns including FROM (I2 may be zero).
14417 : :
14418 : : ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14419 : : not need REG_DEAD notes because they are being substituted for. This
14420 : : saves searching in the most common cases.
14421 : :
14422 : : Each note in the list is either ignored or placed on some insns, depending
14423 : : on the type of note. */
14424 : :
14425 : : static void
14426 : 9682910 : distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14427 : : rtx elim_i2, rtx elim_i1, rtx elim_i0)
14428 : : {
14429 : 9682910 : rtx note, next_note;
14430 : 9682910 : rtx tem_note;
14431 : 9682910 : rtx_insn *tem_insn;
14432 : :
14433 : 22431626 : for (note = notes; note; note = next_note)
14434 : : {
14435 : 12748716 : rtx_insn *place = 0, *place2 = 0;
14436 : :
14437 : 12748716 : next_note = XEXP (note, 1);
14438 : 12748716 : switch (REG_NOTE_KIND (note))
14439 : : {
14440 : : case REG_BR_PROB:
14441 : : case REG_BR_PRED:
14442 : : /* Doesn't matter much where we put this, as long as it's somewhere.
14443 : : It is preferable to keep these notes on branches, which is most
14444 : : likely to be i3. */
14445 : : place = i3;
14446 : : break;
14447 : :
14448 : 0 : case REG_NON_LOCAL_GOTO:
14449 : 0 : if (JUMP_P (i3))
14450 : : place = i3;
14451 : : else
14452 : : {
14453 : 0 : gcc_assert (i2 && JUMP_P (i2));
14454 : : place = i2;
14455 : : }
14456 : : break;
14457 : :
14458 : 28078 : case REG_EH_REGION:
14459 : 28078 : {
14460 : : /* The landing pad handling needs to be kept in sync with the
14461 : : prerequisite checking in try_combine. */
14462 : 28078 : int lp_nr = INTVAL (XEXP (note, 0));
14463 : : /* A REG_EH_REGION note transfering control can only ever come
14464 : : from i3. */
14465 : 28078 : if (lp_nr > 0)
14466 : 17167 : gcc_assert (from_insn == i3);
14467 : : /* We are making sure there is a single effective REG_EH_REGION
14468 : : note and it's valid to put it on i3. */
14469 : 28078 : if (!insn_could_throw_p (from_insn)
14470 : 28078 : && !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14471 : : /* Throw away stray notes on insns that can never throw or
14472 : : make a nonlocal goto. */
14473 : : ;
14474 : : else
14475 : : {
14476 : 27948 : if (CALL_P (i3))
14477 : : place = i3;
14478 : : else
14479 : : {
14480 : 2212 : gcc_assert (cfun->can_throw_non_call_exceptions);
14481 : : /* If i3 can still trap preserve the note, otherwise we've
14482 : : combined things such that we can now prove that the
14483 : : instructions can't trap. Drop the note in this case. */
14484 : 2212 : if (may_trap_p (i3))
14485 : : place = i3;
14486 : : }
14487 : : }
14488 : : break;
14489 : : }
14490 : :
14491 : 123986 : case REG_ARGS_SIZE:
14492 : : /* ??? How to distribute between i3-i1. Assume i3 contains the
14493 : : entire adjustment. Assert i3 contains at least some adjust. */
14494 : 123986 : if (!noop_move_p (i3))
14495 : : {
14496 : 123985 : poly_int64 old_size, args_size = get_args_size (note);
14497 : : /* fixup_args_size_notes looks at REG_NORETURN note,
14498 : : so ensure the note is placed there first. */
14499 : 123985 : if (CALL_P (i3))
14500 : : {
14501 : : rtx *np;
14502 : 1742 : for (np = &next_note; *np; np = &XEXP (*np, 1))
14503 : 21 : if (REG_NOTE_KIND (*np) == REG_NORETURN)
14504 : : {
14505 : 5 : rtx n = *np;
14506 : 5 : *np = XEXP (n, 1);
14507 : 5 : XEXP (n, 1) = REG_NOTES (i3);
14508 : 5 : REG_NOTES (i3) = n;
14509 : 5 : break;
14510 : : }
14511 : : }
14512 : 123985 : old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14513 : : /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14514 : : REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14515 : 123985 : gcc_assert (maybe_ne (old_size, args_size)
14516 : : || (CALL_P (i3)
14517 : : && !ACCUMULATE_OUTGOING_ARGS
14518 : : && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14519 : : }
14520 : : break;
14521 : :
14522 : 87104 : case REG_NORETURN:
14523 : 87104 : case REG_SETJMP:
14524 : 87104 : case REG_TM:
14525 : 87104 : case REG_CALL_DECL:
14526 : 87104 : case REG_UNTYPED_CALL:
14527 : 87104 : case REG_CALL_NOCF_CHECK:
14528 : : /* These notes must remain with the call. It should not be
14529 : : possible for both I2 and I3 to be a call. */
14530 : 87104 : if (CALL_P (i3))
14531 : : place = i3;
14532 : : else
14533 : : {
14534 : 0 : gcc_assert (i2 && CALL_P (i2));
14535 : : place = i2;
14536 : : }
14537 : : break;
14538 : :
14539 : 1962820 : case REG_UNUSED:
14540 : : /* Any clobbers for i3 may still exist, and so we must process
14541 : : REG_UNUSED notes from that insn.
14542 : :
14543 : : Any clobbers from i2 or i1 can only exist if they were added by
14544 : : recog_for_combine. In that case, recog_for_combine created the
14545 : : necessary REG_UNUSED notes. Trying to keep any original
14546 : : REG_UNUSED notes from these insns can cause incorrect output
14547 : : if it is for the same register as the original i3 dest.
14548 : : In that case, we will notice that the register is set in i3,
14549 : : and then add a REG_UNUSED note for the destination of i3, which
14550 : : is wrong. However, it is possible to have REG_UNUSED notes from
14551 : : i2 or i1 for register which were both used and clobbered, so
14552 : : we keep notes from i2 or i1 if they will turn into REG_DEAD
14553 : : notes. */
14554 : :
14555 : : /* If this register is set or clobbered between FROM_INSN and I3,
14556 : : we should not create a note for it. */
14557 : 1962820 : if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14558 : : break;
14559 : :
14560 : : /* If this register is set or clobbered in I3, put the note there
14561 : : unless there is one already. */
14562 : 1878709 : if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14563 : : {
14564 : 1127918 : if (from_insn != i3)
14565 : : break;
14566 : :
14567 : 626356 : if (! (REG_P (XEXP (note, 0))
14568 : 626356 : ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14569 : 0 : : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14570 : : place = i3;
14571 : : }
14572 : : /* Otherwise, if this register is used by I3, then this register
14573 : : now dies here, so we must put a REG_DEAD note here unless there
14574 : : is one already. */
14575 : 750791 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14576 : : {
14577 : 7044 : if (! (REG_P (XEXP (note, 0))
14578 : 7044 : ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
14579 : 0 : : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14580 : : {
14581 : 6806 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14582 : 6806 : place = i3;
14583 : : }
14584 : : }
14585 : :
14586 : : /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14587 : : but we can't tell which at this point. We must reset any
14588 : : expectations we had about the value that was previously
14589 : : stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14590 : : and, if appropriate, restore its previous value, but we
14591 : : don't have enough information for that at this point. */
14592 : : else
14593 : : {
14594 : 743747 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14595 : :
14596 : : /* Otherwise, if this register is now referenced in i2
14597 : : then the register used to be modified in one of the
14598 : : original insns. If it was i3 (say, in an unused
14599 : : parallel), it's now completely gone, so the note can
14600 : : be discarded. But if it was modified in i2, i1 or i0
14601 : : and we still reference it in i2, then we're
14602 : : referencing the previous value, and since the
14603 : : register was modified and REG_UNUSED, we know that
14604 : : the previous value is now dead. So, if we only
14605 : : reference the register in i2, we change the note to
14606 : : REG_DEAD, to reflect the previous value. However, if
14607 : : we're also setting or clobbering the register as
14608 : : scratch, we know (because the register was not
14609 : : referenced in i3) that it's unused, just as it was
14610 : : unused before, and we place the note in i2. */
14611 : 19904 : if (from_insn != i3 && i2 && INSN_P (i2)
14612 : 763651 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14613 : : {
14614 : 132 : if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14615 : 132 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14616 : 132 : if (! (REG_P (XEXP (note, 0))
14617 : 132 : ? find_regno_note (i2, REG_NOTE_KIND (note),
14618 : 132 : REGNO (XEXP (note, 0)))
14619 : 0 : : find_reg_note (i2, REG_NOTE_KIND (note),
14620 : : XEXP (note, 0))))
14621 : : place = i2;
14622 : : }
14623 : : }
14624 : :
14625 : : break;
14626 : :
14627 : 395802 : case REG_EQUAL:
14628 : 395802 : case REG_EQUIV:
14629 : 395802 : case REG_NOALIAS:
14630 : : /* These notes say something about results of an insn. We can
14631 : : only support them if they used to be on I3 in which case they
14632 : : remain on I3. Otherwise they are ignored.
14633 : :
14634 : : If the note refers to an expression that is not a constant, we
14635 : : must also ignore the note since we cannot tell whether the
14636 : : equivalence is still true. It might be possible to do
14637 : : slightly better than this (we only have a problem if I2DEST
14638 : : or I1DEST is present in the expression), but it doesn't
14639 : : seem worth the trouble. */
14640 : :
14641 : 395802 : if (from_insn == i3
14642 : 185027 : && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14643 : : place = i3;
14644 : : break;
14645 : :
14646 : 0 : case REG_INC:
14647 : : /* These notes say something about how a register is used. They must
14648 : : be present on any use of the register in I2 or I3. */
14649 : 0 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14650 : 0 : place = i3;
14651 : :
14652 : 0 : if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14653 : : {
14654 : 0 : if (place)
14655 : : place2 = i2;
14656 : : else
14657 : : place = i2;
14658 : : }
14659 : : break;
14660 : :
14661 : 9634 : case REG_LABEL_TARGET:
14662 : 9634 : case REG_LABEL_OPERAND:
14663 : : /* This can show up in several ways -- either directly in the
14664 : : pattern, or hidden off in the constant pool with (or without?)
14665 : : a REG_EQUAL note. */
14666 : : /* ??? Ignore the without-reg_equal-note problem for now. */
14667 : 9634 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14668 : 9634 : || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14669 : 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14670 : 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14671 : : place = i3;
14672 : :
14673 : 9634 : if (i2
14674 : 9634 : && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14675 : 0 : || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14676 : 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14677 : 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14678 : : {
14679 : 0 : if (place)
14680 : : place2 = i2;
14681 : : else
14682 : : place = i2;
14683 : : }
14684 : :
14685 : : /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14686 : : as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14687 : : there. */
14688 : 9634 : if (place && JUMP_P (place)
14689 : 8615 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14690 : 0 : && (JUMP_LABEL (place) == NULL
14691 : 0 : || JUMP_LABEL (place) == XEXP (note, 0)))
14692 : : {
14693 : 0 : rtx label = JUMP_LABEL (place);
14694 : :
14695 : 0 : if (!label)
14696 : 0 : JUMP_LABEL (place) = XEXP (note, 0);
14697 : 0 : else if (LABEL_P (label))
14698 : 0 : LABEL_NUSES (label)--;
14699 : : }
14700 : :
14701 : 9634 : if (place2 && JUMP_P (place2)
14702 : 0 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14703 : 0 : && (JUMP_LABEL (place2) == NULL
14704 : 0 : || JUMP_LABEL (place2) == XEXP (note, 0)))
14705 : : {
14706 : 0 : rtx label = JUMP_LABEL (place2);
14707 : :
14708 : 0 : if (!label)
14709 : 0 : JUMP_LABEL (place2) = XEXP (note, 0);
14710 : 0 : else if (LABEL_P (label))
14711 : 0 : LABEL_NUSES (label)--;
14712 : : place2 = 0;
14713 : : }
14714 : : break;
14715 : :
14716 : : case REG_NONNEG:
14717 : : /* This note says something about the value of a register prior
14718 : : to the execution of an insn. It is too much trouble to see
14719 : : if the note is still correct in all situations. It is better
14720 : : to simply delete it. */
14721 : : break;
14722 : :
14723 : 10100495 : case REG_DEAD:
14724 : : /* If we replaced the right hand side of FROM_INSN with a
14725 : : REG_EQUAL note, the original use of the dying register
14726 : : will not have been combined into I3 and I2. In such cases,
14727 : : FROM_INSN is guaranteed to be the first of the combined
14728 : : instructions, so we simply need to search back before
14729 : : FROM_INSN for the previous use or set of this register,
14730 : : then alter the notes there appropriately.
14731 : :
14732 : : If the register is used as an input in I3, it dies there.
14733 : : Similarly for I2, if it is nonzero and adjacent to I3.
14734 : :
14735 : : If the register is not used as an input in either I3 or I2
14736 : : and it is not one of the registers we were supposed to eliminate,
14737 : : there are two possibilities. We might have a non-adjacent I2
14738 : : or we might have somehow eliminated an additional register
14739 : : from a computation. For example, we might have had A & B where
14740 : : we discover that B will always be zero. In this case we will
14741 : : eliminate the reference to A.
14742 : :
14743 : : In both cases, we must search to see if we can find a previous
14744 : : use of A and put the death note there. */
14745 : :
14746 : 10100495 : if (from_insn
14747 : 7048477 : && from_insn == i2mod
14748 : 10102395 : && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14749 : : tem_insn = from_insn;
14750 : : else
14751 : : {
14752 : 10098911 : if (from_insn
14753 : 7046893 : && CALL_P (from_insn)
14754 : 10334883 : && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14755 : : place = from_insn;
14756 : 9950036 : else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14757 : : {
14758 : : /* If the new I2 sets the same register that is marked
14759 : : dead in the note, we do not in general know where to
14760 : : put the note. One important case we _can_ handle is
14761 : : when the note comes from I3. */
14762 : 40464 : if (from_insn == i3)
14763 : : place = i3;
14764 : : else
14765 : : break;
14766 : : }
14767 : 9909572 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14768 : : place = i3;
14769 : 120156 : else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14770 : 3931655 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14771 : : place = i2;
14772 : 3762205 : else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14773 : 3642789 : && !(i2mod
14774 : 28521 : && reg_overlap_mentioned_p (XEXP (note, 0),
14775 : : i2mod_old_rhs)))
14776 : 147947 : || rtx_equal_p (XEXP (note, 0), elim_i1)
14777 : 3820501 : || rtx_equal_p (XEXP (note, 0), elim_i0))
14778 : : break;
14779 : 241470 : tem_insn = i3;
14780 : : }
14781 : :
14782 : 241470 : if (place == 0)
14783 : : {
14784 : 53458 : basic_block bb = this_basic_block;
14785 : :
14786 : 2437260 : for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14787 : : {
14788 : 2437260 : if (!NONDEBUG_INSN_P (tem_insn))
14789 : : {
14790 : 1809047 : if (tem_insn == BB_HEAD (bb))
14791 : : break;
14792 : 1770898 : continue;
14793 : : }
14794 : :
14795 : : /* If the register is being set at TEM_INSN, see if that is all
14796 : : TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14797 : : into a REG_UNUSED note instead. Don't delete sets to
14798 : : global register vars. */
14799 : 628213 : if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14800 : 1335 : || !global_regs[REGNO (XEXP (note, 0))])
14801 : 629548 : && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14802 : : {
14803 : 14081 : rtx set = single_set (tem_insn);
14804 : 14081 : rtx inner_dest = 0;
14805 : :
14806 : 14081 : if (set != 0)
14807 : 11630 : for (inner_dest = SET_DEST (set);
14808 : 11639 : (GET_CODE (inner_dest) == STRICT_LOW_PART
14809 : 11639 : || GET_CODE (inner_dest) == SUBREG
14810 : 11639 : || GET_CODE (inner_dest) == ZERO_EXTRACT);
14811 : 9 : inner_dest = XEXP (inner_dest, 0))
14812 : : ;
14813 : :
14814 : : /* Verify that it was the set, and not a clobber that
14815 : : modified the register.
14816 : :
14817 : : If we cannot delete the setter due to side
14818 : : effects, mark the user with an UNUSED note instead
14819 : : of deleting it. */
14820 : :
14821 : 11630 : if (set != 0 && ! side_effects_p (SET_SRC (set))
14822 : 11390 : && rtx_equal_p (XEXP (note, 0), inner_dest))
14823 : : {
14824 : : /* Move the notes and links of TEM_INSN elsewhere.
14825 : : This might delete other dead insns recursively.
14826 : : First set the pattern to something that won't use
14827 : : any register. */
14828 : 11280 : rtx old_notes = REG_NOTES (tem_insn);
14829 : :
14830 : 11280 : PATTERN (tem_insn) = pc_rtx;
14831 : 11280 : REG_NOTES (tem_insn) = NULL;
14832 : :
14833 : 11280 : distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14834 : : NULL_RTX, NULL_RTX, NULL_RTX);
14835 : 11280 : distribute_links (LOG_LINKS (tem_insn));
14836 : :
14837 : 11280 : unsigned int regno = REGNO (XEXP (note, 0));
14838 : 11280 : reg_stat_type *rsp = ®_stat[regno];
14839 : 11280 : if (rsp->last_set == tem_insn)
14840 : 10131 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14841 : :
14842 : 11280 : SET_INSN_DELETED (tem_insn);
14843 : 11280 : if (tem_insn == i2)
14844 : 612904 : i2 = NULL;
14845 : : }
14846 : : else
14847 : : {
14848 : 2801 : PUT_REG_NOTE_KIND (note, REG_UNUSED);
14849 : :
14850 : : /* If there isn't already a REG_UNUSED note, put one
14851 : : here. Do not place a REG_DEAD note, even if
14852 : : the register is also used here; that would not
14853 : : match the algorithm used in lifetime analysis
14854 : : and can cause the consistency check in the
14855 : : scheduler to fail. */
14856 : 2801 : if (! find_regno_note (tem_insn, REG_UNUSED,
14857 : 2801 : REGNO (XEXP (note, 0))))
14858 : 1487 : place = tem_insn;
14859 : : break;
14860 : : }
14861 : : }
14862 : 614132 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14863 : 614132 : || (CALL_P (tem_insn)
14864 : 15662 : && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14865 : : {
14866 : 12508 : place = tem_insn;
14867 : :
14868 : : /* If we are doing a 3->2 combination, and we have a
14869 : : register which formerly died in i3 and was not used
14870 : : by i2, which now no longer dies in i3 and is used in
14871 : : i2 but does not die in i2, and place is between i2
14872 : : and i3, then we may need to move a link from place to
14873 : : i2. */
14874 : 3812 : if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14875 : 77 : && from_insn
14876 : 77 : && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14877 : 12585 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14878 : : {
14879 : 77 : struct insn_link *links = LOG_LINKS (place);
14880 : 77 : LOG_LINKS (place) = NULL;
14881 : 77 : distribute_links (links);
14882 : : }
14883 : : break;
14884 : : }
14885 : :
14886 : 612904 : if (tem_insn == BB_HEAD (bb))
14887 : : break;
14888 : : }
14889 : :
14890 : : }
14891 : :
14892 : : /* If the register is set or already dead at PLACE, we needn't do
14893 : : anything with this note if it is still a REG_DEAD note.
14894 : : We check here if it is set at all, not if is it totally replaced,
14895 : : which is what `dead_or_set_p' checks, so also check for it being
14896 : : set partially. */
14897 : :
14898 : 6386856 : if (place && REG_NOTE_KIND (note) == REG_DEAD)
14899 : : {
14900 : 6345906 : unsigned int regno = REGNO (XEXP (note, 0));
14901 : 6345906 : reg_stat_type *rsp = ®_stat[regno];
14902 : :
14903 : 6345906 : if (dead_or_set_p (place, XEXP (note, 0))
14904 : 6345906 : || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14905 : : {
14906 : : /* Unless the register previously died in PLACE, clear
14907 : : last_death. [I no longer understand why this is
14908 : : being done.] */
14909 : 2941442 : if (rsp->last_death != place)
14910 : 519755 : rsp->last_death = 0;
14911 : : place = 0;
14912 : : }
14913 : : else
14914 : 3404464 : rsp->last_death = place;
14915 : :
14916 : : /* If this is a death note for a hard reg that is occupying
14917 : : multiple registers, ensure that we are still using all
14918 : : parts of the object. If we find a piece of the object
14919 : : that is unused, we must arrange for an appropriate REG_DEAD
14920 : : note to be added for it. However, we can't just emit a USE
14921 : : and tag the note to it, since the register might actually
14922 : : be dead; so we recourse, and the recursive call then finds
14923 : : the previous insn that used this register. */
14924 : :
14925 : 3404464 : if (place && REG_NREGS (XEXP (note, 0)) > 1)
14926 : : {
14927 : 775 : unsigned int endregno = END_REGNO (XEXP (note, 0));
14928 : 775 : bool all_used = true;
14929 : 775 : unsigned int i;
14930 : :
14931 : 2325 : for (i = regno; i < endregno; i++)
14932 : 1550 : if ((! refers_to_regno_p (i, PATTERN (place))
14933 : 1550 : && ! find_regno_fusage (place, USE, i))
14934 : 3100 : || dead_or_set_regno_p (place, i))
14935 : : {
14936 : : all_used = false;
14937 : : break;
14938 : : }
14939 : :
14940 : 775 : if (! all_used)
14941 : : {
14942 : : /* Put only REG_DEAD notes for pieces that are
14943 : : not already dead or set. */
14944 : :
14945 : 0 : for (i = regno; i < endregno;
14946 : 0 : i += hard_regno_nregs (i, reg_raw_mode[i]))
14947 : : {
14948 : 0 : rtx piece = regno_reg_rtx[i];
14949 : 0 : basic_block bb = this_basic_block;
14950 : :
14951 : 0 : if (! dead_or_set_p (place, piece)
14952 : 0 : && ! reg_bitfield_target_p (piece,
14953 : 0 : PATTERN (place)))
14954 : : {
14955 : 0 : rtx new_note = alloc_reg_note (REG_DEAD, piece,
14956 : : NULL_RTX);
14957 : :
14958 : 0 : distribute_notes (new_note, place, place,
14959 : : NULL, NULL_RTX, NULL_RTX,
14960 : : NULL_RTX);
14961 : : }
14962 : 0 : else if (! refers_to_regno_p (i, PATTERN (place))
14963 : 0 : && ! find_regno_fusage (place, USE, i))
14964 : 0 : for (tem_insn = PREV_INSN (place); ;
14965 : 0 : tem_insn = PREV_INSN (tem_insn))
14966 : : {
14967 : 0 : if (!NONDEBUG_INSN_P (tem_insn))
14968 : : {
14969 : 0 : if (tem_insn == BB_HEAD (bb))
14970 : : break;
14971 : 0 : continue;
14972 : : }
14973 : 0 : if (dead_or_set_p (tem_insn, piece)
14974 : 0 : || reg_bitfield_target_p (piece,
14975 : 0 : PATTERN (tem_insn)))
14976 : : {
14977 : 0 : add_reg_note (tem_insn, REG_UNUSED, piece);
14978 : 0 : break;
14979 : : }
14980 : : }
14981 : : }
14982 : :
14983 : : place = 0;
14984 : : }
14985 : : }
14986 : : }
14987 : : break;
14988 : :
14989 : 0 : default:
14990 : : /* Any other notes should not be present at this point in the
14991 : : compilation. */
14992 : 0 : gcc_unreachable ();
14993 : : }
14994 : :
14995 : 4188778 : if (place)
14996 : : {
14997 : 4177503 : XEXP (note, 1) = REG_NOTES (place);
14998 : 4177503 : REG_NOTES (place) = note;
14999 : :
15000 : : /* Set added_notes_insn to the earliest insn we added a note to. */
15001 : 4177503 : if (added_notes_insn == 0
15002 : 4177503 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
15003 : 2752011 : added_notes_insn = place;
15004 : : }
15005 : :
15006 : 12748716 : if (place2)
15007 : : {
15008 : 0 : add_shallow_copy_of_reg_note (place2, note);
15009 : :
15010 : : /* Set added_notes_insn to the earliest insn we added a note to. */
15011 : 0 : if (added_notes_insn == 0
15012 : 0 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
15013 : 0 : added_notes_insn = place2;
15014 : : }
15015 : : }
15016 : 9682910 : }
15017 : :
15018 : : /* Similarly to above, distribute the LOG_LINKS that used to be present on
15019 : : I3, I2, and I1 to new locations. This is also called to add a link
15020 : : pointing at I3 when I3's destination is changed.
15021 : :
15022 : : If START is nonnull and an insn, we know that the next location for each
15023 : : link is no earlier than START. LIMIT is the maximum number of nondebug
15024 : : instructions that can be scanned when looking for the next use of a
15025 : : definition. */
15026 : :
15027 : : static void
15028 : 15380879 : distribute_links (struct insn_link *links, rtx_insn *start, int limit)
15029 : : {
15030 : 15380879 : struct insn_link *link, *next_link;
15031 : :
15032 : 22731366 : for (link = links; link; link = next_link)
15033 : : {
15034 : 7350487 : rtx_insn *place = 0;
15035 : 7350487 : rtx_insn *insn;
15036 : 7350487 : rtx set, reg;
15037 : :
15038 : 7350487 : next_link = link->next;
15039 : :
15040 : : /* If the insn that this link points to is a NOTE, ignore it. */
15041 : 7350487 : if (NOTE_P (link->insn))
15042 : 3868620 : continue;
15043 : :
15044 : 3481867 : set = 0;
15045 : 3481867 : rtx pat = PATTERN (link->insn);
15046 : 3481867 : if (GET_CODE (pat) == SET)
15047 : : set = pat;
15048 : 640850 : else if (GET_CODE (pat) == PARALLEL)
15049 : : {
15050 : : int i;
15051 : 756759 : for (i = 0; i < XVECLEN (pat, 0); i++)
15052 : : {
15053 : 751272 : set = XVECEXP (pat, 0, i);
15054 : 751272 : if (GET_CODE (set) != SET)
15055 : 5488 : continue;
15056 : :
15057 : 745784 : reg = SET_DEST (set);
15058 : 745784 : while (GET_CODE (reg) == ZERO_EXTRACT
15059 : 754538 : || GET_CODE (reg) == STRICT_LOW_PART
15060 : 1508978 : || GET_CODE (reg) == SUBREG)
15061 : 8761 : reg = XEXP (reg, 0);
15062 : :
15063 : 745784 : if (!REG_P (reg))
15064 : 43868 : continue;
15065 : :
15066 : 701916 : if (REGNO (reg) == link->regno)
15067 : : break;
15068 : : }
15069 : 639267 : if (i == XVECLEN (pat, 0))
15070 : 5487 : continue;
15071 : : }
15072 : : else
15073 : 1583 : continue;
15074 : :
15075 : 3474797 : reg = SET_DEST (set);
15076 : :
15077 : 3474797 : while (GET_CODE (reg) == ZERO_EXTRACT
15078 : 3497067 : || GET_CODE (reg) == STRICT_LOW_PART
15079 : 6994257 : || GET_CODE (reg) == SUBREG)
15080 : 22823 : reg = XEXP (reg, 0);
15081 : :
15082 : 3474797 : if (reg == pc_rtx)
15083 : 735 : continue;
15084 : :
15085 : : /* A LOG_LINK is defined as being placed on the first insn that uses
15086 : : a register and points to the insn that sets the register. Start
15087 : : searching at the next insn after the target of the link and stop
15088 : : when we reach a set of the register or the end of the basic block.
15089 : :
15090 : : Note that this correctly handles the link that used to point from
15091 : : I3 to I2. Also note that not much searching is typically done here
15092 : : since most links don't point very far away. */
15093 : :
15094 : 3474062 : int count = 0;
15095 : 3474062 : insn = start;
15096 : 3474062 : if (!insn || NOTE_P (insn))
15097 : 3425544 : insn = NEXT_INSN (link->insn);
15098 : : else
15099 : 48518 : count = link->insn_count;
15100 : 11411309 : for (;
15101 : 14885371 : (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
15102 : 10531331 : || BB_HEAD (this_basic_block->next_bb) != insn));
15103 : 11411309 : insn = NEXT_INSN (insn))
15104 : 14845885 : if (DEBUG_INSN_P (insn))
15105 : 3162658 : continue;
15106 : 11683227 : else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
15107 : : {
15108 : 3282407 : if (reg_referenced_p (reg, PATTERN (insn)))
15109 : 3282407 : place = insn;
15110 : : break;
15111 : : }
15112 : 8400820 : else if (CALL_P (insn)
15113 : 8400820 : && find_reg_fusage (insn, USE, reg))
15114 : : {
15115 : : place = insn;
15116 : : break;
15117 : : }
15118 : 8248757 : else if (INSN_P (insn) && reg_set_p (reg, insn))
15119 : : break;
15120 : 8248651 : else if (count >= limit)
15121 : : break;
15122 : : else
15123 : 8248651 : count += 1;
15124 : 3474062 : link->insn_count = count;
15125 : :
15126 : : /* If we found a place to put the link, place it there unless there
15127 : : is already a link to the same insn as LINK at that point. */
15128 : :
15129 : 3474062 : if (place)
15130 : : {
15131 : 3434470 : struct insn_link *link2;
15132 : :
15133 : 4424769 : FOR_EACH_LOG_LINK (link2, place)
15134 : 1008654 : if (link2->insn == link->insn && link2->regno == link->regno)
15135 : : break;
15136 : :
15137 : 3434470 : if (link2 == NULL)
15138 : : {
15139 : 3416115 : link->next = LOG_LINKS (place);
15140 : 3416115 : LOG_LINKS (place) = link;
15141 : :
15142 : : /* Set added_links_insn to the earliest insn we added a
15143 : : link to. */
15144 : 3416115 : if (added_links_insn == 0
15145 : 3416115 : || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15146 : 2699304 : added_links_insn = place;
15147 : : }
15148 : : }
15149 : : }
15150 : 15380879 : }
15151 : :
15152 : : /* Check for any register or memory mentioned in EQUIV that is not
15153 : : mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15154 : : of EXPR where some registers may have been replaced by constants. */
15155 : :
15156 : : static bool
15157 : 2593631 : unmentioned_reg_p (rtx equiv, rtx expr)
15158 : : {
15159 : 2593631 : subrtx_iterator::array_type array;
15160 : 6826984 : FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15161 : : {
15162 : 5605683 : const_rtx x = *iter;
15163 : 3824304 : if ((REG_P (x) || MEM_P (x))
15164 : 5994145 : && !reg_mentioned_p (x, expr))
15165 : 1372330 : return true;
15166 : : }
15167 : 1221301 : return false;
15168 : 2593631 : }
15169 : :
15170 : : /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15171 : : the reg-to-reg copy can usefully combine with later instructions, but we
15172 : : do not want to combine the hard reg into later instructions, for that
15173 : : restricts register allocation. */
15174 : : static void
15175 : 1023804 : make_more_copies (void)
15176 : : {
15177 : 1023804 : basic_block bb;
15178 : :
15179 : 11305067 : FOR_EACH_BB_FN (bb, cfun)
15180 : : {
15181 : 10281263 : rtx_insn *insn;
15182 : :
15183 : 132857945 : FOR_BB_INSNS (bb, insn)
15184 : : {
15185 : 122576682 : if (!NONDEBUG_INSN_P (insn))
15186 : 64055891 : continue;
15187 : :
15188 : 58520791 : rtx set = single_set (insn);
15189 : 58520791 : if (!set)
15190 : 3944426 : continue;
15191 : :
15192 : 54576365 : rtx dest = SET_DEST (set);
15193 : 54576365 : if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15194 : 31131599 : continue;
15195 : :
15196 : 23444766 : rtx src = SET_SRC (set);
15197 : 23444766 : if (!(REG_P (src) && HARD_REGISTER_P (src)))
15198 : 20429880 : continue;
15199 : 3014886 : if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15200 : 9943 : continue;
15201 : :
15202 : 3004943 : rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15203 : :
15204 : : /* The "original" pseudo copies have important attributes
15205 : : attached, like pointerness. We want that for these copies
15206 : : too, for use by insn recognition and later passes. */
15207 : 3004943 : set_reg_attrs_from_value (new_reg, dest);
15208 : :
15209 : 3004943 : rtx_insn *new_insn = gen_move_insn (new_reg, src);
15210 : 3004943 : SET_SRC (set) = new_reg;
15211 : 3004943 : emit_insn_before (new_insn, insn);
15212 : 3004943 : df_insn_rescan (insn);
15213 : : }
15214 : : }
15215 : 1023804 : }
15216 : :
15217 : : /* Try combining insns through substitution. */
15218 : : static void
15219 : 1023804 : rest_of_handle_combine (void)
15220 : : {
15221 : 1023804 : make_more_copies ();
15222 : :
15223 : 1023804 : df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15224 : 1023804 : df_note_add_problem ();
15225 : 1023804 : df_analyze ();
15226 : :
15227 : 1023804 : regstat_init_n_sets_and_refs ();
15228 : 1023804 : reg_n_sets_max = max_reg_num ();
15229 : :
15230 : 1023804 : bool rebuild_jump_labels_after_combine
15231 : 1023804 : = combine_instructions (get_insns (), max_reg_num ());
15232 : :
15233 : : /* Combining insns may have turned an indirect jump into a
15234 : : direct jump. Rebuild the JUMP_LABEL fields of jumping
15235 : : instructions. */
15236 : 1023804 : if (rebuild_jump_labels_after_combine)
15237 : : {
15238 : 2612 : if (dom_info_available_p (CDI_DOMINATORS))
15239 : 0 : free_dominance_info (CDI_DOMINATORS);
15240 : 2612 : timevar_push (TV_JUMP);
15241 : 2612 : rebuild_jump_labels (get_insns ());
15242 : 2612 : cleanup_cfg (0);
15243 : 2612 : timevar_pop (TV_JUMP);
15244 : : }
15245 : :
15246 : 1023804 : regstat_free_n_sets_and_refs ();
15247 : 1023804 : }
15248 : :
15249 : : namespace {
15250 : :
15251 : : const pass_data pass_data_combine =
15252 : : {
15253 : : RTL_PASS, /* type */
15254 : : "combine", /* name */
15255 : : OPTGROUP_NONE, /* optinfo_flags */
15256 : : TV_COMBINE, /* tv_id */
15257 : : PROP_cfglayout, /* properties_required */
15258 : : 0, /* properties_provided */
15259 : : 0, /* properties_destroyed */
15260 : : 0, /* todo_flags_start */
15261 : : TODO_df_finish, /* todo_flags_finish */
15262 : : };
15263 : :
15264 : : class pass_combine : public rtl_opt_pass
15265 : : {
15266 : : public:
15267 : 285081 : pass_combine (gcc::context *ctxt)
15268 : 570162 : : rtl_opt_pass (pass_data_combine, ctxt)
15269 : : {}
15270 : :
15271 : : /* opt_pass methods: */
15272 : 1449863 : bool gate (function *) final override { return (optimize > 0); }
15273 : 1023804 : unsigned int execute (function *) final override
15274 : : {
15275 : 1023804 : rest_of_handle_combine ();
15276 : 1023804 : return 0;
15277 : : }
15278 : :
15279 : : }; // class pass_combine
15280 : :
15281 : : } // anon namespace
15282 : :
15283 : : rtl_opt_pass *
15284 : 285081 : make_pass_combine (gcc::context *ctxt)
15285 : : {
15286 : 285081 : return new pass_combine (ctxt);
15287 : : }
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