Line data Source code
1 : /* Optimize by combining instructions for GNU compiler.
2 : Copyright (C) 1987-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it under
7 : the terms of the GNU General Public License as published by the Free
8 : Software Foundation; either version 3, or (at your option) any later
9 : version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : /* This module is essentially the "combiner" phase of the U. of Arizona
21 : Portable Optimizer, but redone to work on our list-structured
22 : representation for RTL instead of their string representation.
23 :
24 : The LOG_LINKS of each insn identify the most recent assignment
25 : to each REG used in the insn. It is a list of previous insns,
26 : each of which contains a SET for a REG that is used in this insn
27 : and not used or set in between. LOG_LINKs never cross basic blocks.
28 : They were set up by the preceding pass (lifetime analysis).
29 :
30 : We try to combine each pair of insns joined by a logical link.
31 : We also try to combine triplets of insns A, B and C when C has
32 : a link back to B and B has a link back to A. Likewise for a
33 : small number of quadruplets of insns A, B, C and D for which
34 : there's high likelihood of success.
35 :
36 : We check (with modified_between_p) to avoid combining in such a way
37 : as to move a computation to a place where its value would be different.
38 :
39 : Combination is done by mathematically substituting the previous
40 : insn(s) values for the regs they set into the expressions in
41 : the later insns that refer to these regs. If the result is a valid insn
42 : for our target machine, according to the machine description,
43 : we install it, delete the earlier insns, and update the data flow
44 : information (LOG_LINKS and REG_NOTES) for what we did.
45 :
46 : There are a few exceptions where the dataflow information isn't
47 : completely updated (however this is only a local issue since it is
48 : regenerated before the next pass that uses it):
49 :
50 : - reg_live_length is not updated
51 : - reg_n_refs is not adjusted in the rare case when a register is
52 : no longer required in a computation
53 : - there are extremely rare cases (see distribute_notes) when a
54 : REG_DEAD note is lost
55 : - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 : removed because there is no way to know which register it was
57 : linking
58 :
59 : To simplify substitution, we combine only when the earlier insn(s)
60 : consist of only a single assignment. To simplify updating afterward,
61 : we never combine when a subroutine call appears in the middle. */
62 :
63 : #include "config.h"
64 : #include "system.h"
65 : #include "coretypes.h"
66 : #include "backend.h"
67 : #include "target.h"
68 : #include "rtl.h"
69 : #include "tree.h"
70 : #include "cfghooks.h"
71 : #include "predict.h"
72 : #include "df.h"
73 : #include "memmodel.h"
74 : #include "tm_p.h"
75 : #include "optabs.h"
76 : #include "regs.h"
77 : #include "emit-rtl.h"
78 : #include "recog.h"
79 : #include "cgraph.h"
80 : #include "stor-layout.h"
81 : #include "cfgrtl.h"
82 : #include "cfgcleanup.h"
83 : /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84 : #include "explow.h"
85 : #include "insn-attr.h"
86 : #include "rtlhooks-def.h"
87 : #include "expr.h"
88 : #include "tree-pass.h"
89 : #include "valtrack.h"
90 : #include "rtl-iter.h"
91 : #include "print-rtl.h"
92 : #include "function-abi.h"
93 : #include "rtlanal.h"
94 :
95 : /* Number of attempts to combine instructions in this function. */
96 :
97 : static int combine_attempts;
98 :
99 : /* Number of attempts that got as far as substitution in this function. */
100 :
101 : static int combine_merges;
102 :
103 : /* Number of instructions combined with added SETs in this function. */
104 :
105 : static int combine_extras;
106 :
107 : /* Number of instructions combined in this function. */
108 :
109 : static int combine_successes;
110 :
111 : /* combine_instructions may try to replace the right hand side of the
112 : second instruction with the value of an associated REG_EQUAL note
113 : before throwing it at try_combine. That is problematic when there
114 : is a REG_DEAD note for a register used in the old right hand side
115 : and can cause distribute_notes to do wrong things. This is the
116 : second instruction if it has been so modified, null otherwise. */
117 :
118 : static rtx_insn *i2mod;
119 :
120 : /* When I2MOD is nonnull, this is a copy of the old right hand side. */
121 :
122 : static rtx i2mod_old_rhs;
123 :
124 : /* When I2MOD is nonnull, this is a copy of the new right hand side. */
125 :
126 : static rtx i2mod_new_rhs;
127 :
128 : struct reg_stat_type {
129 : /* Record last point of death of (hard or pseudo) register n. */
130 : rtx_insn *last_death;
131 :
132 : /* Record last point of modification of (hard or pseudo) register n. */
133 : rtx_insn *last_set;
134 :
135 : /* The next group of fields allows the recording of the last value assigned
136 : to (hard or pseudo) register n. We use this information to see if an
137 : operation being processed is redundant given a prior operation performed
138 : on the register. For example, an `and' with a constant is redundant if
139 : all the zero bits are already known to be turned off.
140 :
141 : We use an approach similar to that used by cse, but change it in the
142 : following ways:
143 :
144 : (1) We do not want to reinitialize at each label.
145 : (2) It is useful, but not critical, to know the actual value assigned
146 : to a register. Often just its form is helpful.
147 :
148 : Therefore, we maintain the following fields:
149 :
150 : last_set_value the last value assigned
151 : last_set_label records the value of label_tick when the
152 : register was assigned
153 : last_set_table_tick records the value of label_tick when a
154 : value using the register is assigned
155 : last_set_invalid set to true when it is not valid
156 : to use the value of this register in some
157 : register's value
158 :
159 : To understand the usage of these tables, it is important to understand
160 : the distinction between the value in last_set_value being valid and
161 : the register being validly contained in some other expression in the
162 : table.
163 :
164 : (The next two parameters are out of date).
165 :
166 : reg_stat[i].last_set_value is valid if it is nonzero, and either
167 : reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168 :
169 : Register I may validly appear in any expression returned for the value
170 : of another register if reg_n_sets[i] is 1. It may also appear in the
171 : value for register J if reg_stat[j].last_set_invalid is zero, or
172 : reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173 :
174 : If an expression is found in the table containing a register which may
175 : not validly appear in an expression, the register is replaced by
176 : something that won't match, (clobber (const_int 0)). */
177 :
178 : /* Record last value assigned to (hard or pseudo) register n. */
179 :
180 : rtx last_set_value;
181 :
182 : /* Record the value of label_tick when an expression involving register n
183 : is placed in last_set_value. */
184 :
185 : int last_set_table_tick;
186 :
187 : /* Record the value of label_tick when the value for register n is placed in
188 : last_set_value. */
189 :
190 : int last_set_label;
191 :
192 : /* These fields are maintained in parallel with last_set_value and are
193 : used to store the mode in which the register was last set, the bits
194 : that were known to be zero when it was last set, and the number of
195 : sign bits copies it was known to have when it was last set. */
196 :
197 : unsigned HOST_WIDE_INT last_set_nonzero_bits;
198 : unsigned short last_set_sign_bit_copies;
199 : machine_mode last_set_mode : MACHINE_MODE_BITSIZE;
200 :
201 : /* Set to true if references to register n in expressions should not be
202 : used. last_set_invalid is set nonzero when this register is being
203 : assigned to and last_set_table_tick == label_tick. */
204 :
205 : bool last_set_invalid;
206 :
207 : /* Some registers that are set more than once and used in more than one
208 : basic block are nevertheless always set in similar ways. For example,
209 : a QImode register may be loaded from memory in two places on a machine
210 : where byte loads zero extend.
211 :
212 : We record in the following fields if a register has some leading bits
213 : that are always equal to the sign bit, and what we know about the
214 : nonzero bits of a register, specifically which bits are known to be
215 : zero.
216 :
217 : If an entry is zero, it means that we don't know anything special. */
218 :
219 : unsigned short sign_bit_copies;
220 :
221 : unsigned HOST_WIDE_INT nonzero_bits;
222 :
223 : /* Record the value of the label_tick when the last truncation
224 : happened. The field truncated_to_mode is only valid if
225 : truncation_label == label_tick. */
226 :
227 : int truncation_label;
228 :
229 : /* Record the last truncation seen for this register. If truncation
230 : is not a nop to this mode we might be able to save an explicit
231 : truncation if we know that value already contains a truncated
232 : value. */
233 :
234 : machine_mode truncated_to_mode : MACHINE_MODE_BITSIZE;
235 : };
236 :
237 :
238 : static vec<reg_stat_type> reg_stat;
239 :
240 : /* One plus the highest pseudo for which we track REG_N_SETS.
241 : regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 : but during combine_split_insns new pseudos can be created. As we don't have
243 : updated DF information in that case, it is hard to initialize the array
244 : after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 : so instead of growing the arrays, just assume all newly created pseudos
246 : during combine might be set multiple times. */
247 :
248 : static unsigned int reg_n_sets_max;
249 :
250 : /* Record the luid of the last insn that invalidated memory
251 : (anything that writes memory, and subroutine calls, but not pushes). */
252 :
253 : static int mem_last_set;
254 :
255 : /* Record the luid of the last CALL_INSN
256 : so we can tell whether a potential combination crosses any calls. */
257 :
258 : static int last_call_luid;
259 :
260 : /* When `subst' is called, this is the insn that is being modified
261 : (by combining in a previous insn). The PATTERN of this insn
262 : is still the old pattern partially modified and it should not be
263 : looked at, but this may be used to examine the successors of the insn
264 : to judge whether a simplification is valid. */
265 :
266 : static rtx_insn *subst_insn;
267 :
268 : /* This is the lowest LUID that `subst' is currently dealing with.
269 : get_last_value will not return a value if the register was set at or
270 : after this LUID. If not for this mechanism, we could get confused if
271 : I2 or I1 in try_combine were an insn that used the old value of a register
272 : to obtain a new value. In that case, we might erroneously get the
273 : new value of the register when we wanted the old one. */
274 :
275 : static int subst_low_luid;
276 :
277 : /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 : must consider all these registers to be always live. */
279 :
280 : static HARD_REG_SET newpat_used_regs;
281 :
282 : /* This is an insn to which a LOG_LINKS entry has been added. If this
283 : insn is the earlier than I2 or I3, combine should rescan starting at
284 : that location. */
285 :
286 : static rtx_insn *added_links_insn;
287 :
288 : /* And similarly, for notes. */
289 :
290 : static rtx_insn *added_notes_insn;
291 :
292 : /* Basic block in which we are performing combines. */
293 : static basic_block this_basic_block;
294 : static bool optimize_this_for_speed_p;
295 :
296 :
297 : /* Length of the currently allocated uid_insn_cost array. */
298 :
299 : static int max_uid_known;
300 :
301 : /* The following array records the insn_cost for every insn
302 : in the instruction stream. */
303 :
304 : static int *uid_insn_cost;
305 :
306 : /* The following array records the LOG_LINKS for every insn in the
307 : instruction stream as struct insn_link pointers. */
308 :
309 : struct insn_link {
310 : rtx_insn *insn;
311 : unsigned int regno;
312 : int insn_count;
313 : struct insn_link *next;
314 : };
315 :
316 : static struct insn_link **uid_log_links;
317 :
318 : static inline int
319 775682471 : insn_uid_check (const_rtx insn)
320 : {
321 775682471 : int uid = INSN_UID (insn);
322 775682471 : gcc_checking_assert (uid <= max_uid_known);
323 775682471 : return uid;
324 : }
325 :
326 : #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
327 : #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 :
329 : #define FOR_EACH_LOG_LINK(L, INSN) \
330 : for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 :
332 : /* Links for LOG_LINKS are allocated from this obstack. */
333 :
334 : static struct obstack insn_link_obstack;
335 :
336 : /* Allocate a link. */
337 :
338 : static inline struct insn_link *
339 38897515 : alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
340 : {
341 38897515 : struct insn_link *l
342 38897515 : = (struct insn_link *) obstack_alloc (&insn_link_obstack,
343 : sizeof (struct insn_link));
344 38897515 : l->insn = insn;
345 38897515 : l->regno = regno;
346 38897515 : l->insn_count = 0;
347 38897515 : l->next = next;
348 38897515 : return l;
349 : }
350 :
351 : /* Incremented for each basic block. */
352 :
353 : static int label_tick;
354 :
355 : /* Reset to label_tick for each extended basic block in scanning order. */
356 :
357 : static int label_tick_ebb_start;
358 :
359 : /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
360 : largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
361 :
362 : static scalar_int_mode nonzero_bits_mode;
363 :
364 : /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
365 : be safely used. It is zero while computing them and after combine has
366 : completed. This former test prevents propagating values based on
367 : previously set values, which can be incorrect if a variable is modified
368 : in a loop. */
369 :
370 : static int nonzero_sign_valid;
371 :
372 :
373 : /* Record one modification to rtl structure
374 : to be undone by storing old_contents into *where. */
375 :
376 : enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
377 :
378 : struct undo
379 : {
380 : struct undo *next;
381 : enum undo_kind kind;
382 : union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
383 : union { rtx *r; int *i; int regno; struct insn_link **l; } where;
384 : };
385 :
386 : /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
387 : num_undo says how many are currently recorded.
388 :
389 : other_insn is nonzero if we have modified some other insn in the process
390 : of working on subst_insn. It must be verified too. */
391 :
392 : struct undobuf
393 : {
394 : struct undo *undos;
395 : struct undo *frees;
396 : rtx_insn *other_insn;
397 : };
398 :
399 : static struct undobuf undobuf;
400 :
401 : /* Number of times the pseudo being substituted for
402 : was found and replaced. */
403 :
404 : static int n_occurrences;
405 :
406 : static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
407 : scalar_int_mode,
408 : unsigned HOST_WIDE_INT *);
409 : static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
410 : scalar_int_mode,
411 : unsigned int *);
412 : static void do_SUBST (rtx *, rtx);
413 : static void do_SUBST_INT (int *, int);
414 : static void init_reg_last (void);
415 : static void setup_incoming_promotions (rtx_insn *);
416 : static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
417 : static bool cant_combine_insn_p (rtx_insn *);
418 : static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
419 : rtx_insn *, rtx_insn *, rtx *, rtx *);
420 : static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
421 : bool, bool, rtx *);
422 : static bool contains_muldiv (rtx);
423 : static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
424 : bool *, rtx_insn *);
425 : static void undo_all (void);
426 : static void undo_commit (void);
427 : static rtx *find_split_point (rtx *, rtx_insn *, bool);
428 : static rtx subst (rtx, rtx, rtx, bool, bool, bool);
429 : static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
430 : static rtx simplify_if_then_else (rtx);
431 : static rtx simplify_set (rtx);
432 : static rtx simplify_logical (rtx);
433 : static rtx expand_compound_operation (rtx);
434 : static const_rtx expand_field_assignment (const_rtx);
435 : static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
436 : unsigned HOST_WIDE_INT, bool, bool, bool);
437 : static int get_pos_from_mask (unsigned HOST_WIDE_INT,
438 : unsigned HOST_WIDE_INT *);
439 : static rtx canon_reg_for_combine (rtx, rtx);
440 : static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
441 : scalar_int_mode, unsigned HOST_WIDE_INT, bool);
442 : static rtx force_to_mode (rtx, machine_mode,
443 : unsigned HOST_WIDE_INT, bool);
444 : static rtx if_then_else_cond (rtx, rtx *, rtx *);
445 : static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
446 : static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
447 : static rtx make_field_assignment (rtx);
448 : static rtx apply_distributive_law (rtx);
449 : static rtx distribute_and_simplify_rtx (rtx, int);
450 : static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
451 : unsigned HOST_WIDE_INT);
452 : static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
453 : unsigned HOST_WIDE_INT);
454 : static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
455 : HOST_WIDE_INT, machine_mode, bool *);
456 : static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
457 : static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
458 : int);
459 : static int recog_for_combine (rtx *, rtx_insn *, rtx *, unsigned = 0, unsigned = 0);
460 : static rtx gen_lowpart_for_combine (machine_mode, rtx);
461 : static rtx gen_lowpart_for_combine_no_emit (machine_mode, rtx);
462 : static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
463 : rtx *, rtx *);
464 : static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
465 : static void update_table_tick (rtx);
466 : static void record_value_for_reg (rtx, rtx_insn *, rtx);
467 : static void check_promoted_subreg (rtx_insn *, rtx);
468 : static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
469 : static void record_dead_and_set_regs (rtx_insn *);
470 : static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
471 : static rtx get_last_value (const_rtx);
472 : static void reg_dead_at_p_1 (rtx, const_rtx, void *);
473 : static bool reg_dead_at_p (rtx, rtx_insn *);
474 : static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
475 : static bool reg_bitfield_target_p (rtx, rtx);
476 : static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
477 : rtx, rtx, rtx);
478 : static void distribute_links (struct insn_link *, rtx_insn * = nullptr,
479 : int limit = INT_MAX);
480 : static void mark_used_regs_combine (rtx);
481 : static void record_promoted_value (rtx_insn *, rtx);
482 : static bool unmentioned_reg_p (rtx, rtx);
483 : static void record_truncated_values (rtx *, void *);
484 : static bool reg_truncated_to_mode (machine_mode, const_rtx);
485 : static rtx gen_lowpart_or_truncate (machine_mode, rtx);
486 :
487 :
488 : /* It is not safe to use ordinary gen_lowpart in combine.
489 : See comments in gen_lowpart_for_combine. */
490 : #undef RTL_HOOKS_GEN_LOWPART
491 : #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 :
493 : /* Our implementation of gen_lowpart never emits a new pseudo. */
494 : #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 : #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine_no_emit
496 :
497 : #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 : #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 :
500 : #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 : #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 :
503 : #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 : #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
505 :
506 : static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
507 :
508 :
509 : /* Convenience wrapper for the canonicalize_comparison target hook.
510 : Target hooks cannot use enum rtx_code. */
511 : static inline void
512 25322998 : target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
513 : bool op0_preserve_value)
514 : {
515 25322998 : int code_int = (int)*code;
516 25322998 : targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
517 25322998 : *code = (enum rtx_code)code_int;
518 : }
519 :
520 : /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 : PATTERN cannot be split. Otherwise, it returns an insn sequence.
522 : Updates OLD_NREGS with the max number of regs before the split
523 : and NEW_NREGS after the split.
524 : This is a wrapper around split_insns which ensures that the
525 : reg_stat vector is made larger if the splitter creates a new
526 : register. */
527 :
528 : static rtx_insn *
529 12140497 : combine_split_insns (rtx pattern, rtx_insn *insn,
530 : unsigned int *old_nregs,
531 : unsigned int *new_regs)
532 : {
533 12140497 : rtx_insn *ret;
534 12140497 : unsigned int nregs;
535 12140497 : *old_nregs = max_reg_num ();
536 12140497 : ret = split_insns (pattern, insn);
537 12140497 : *new_regs = nregs = max_reg_num ();
538 24280994 : if (nregs > reg_stat.length ())
539 2243 : reg_stat.safe_grow_cleared (nregs, true);
540 12140497 : return ret;
541 : }
542 :
543 : /* This is used by find_single_use to locate an rtx in LOC that
544 : contains exactly one use of DEST, which is typically a REG.
545 : It returns a pointer to the innermost rtx expression
546 : containing DEST. Appearances of DEST that are being used to
547 : totally replace it are not counted. */
548 :
549 : static rtx *
550 33386478 : find_single_use_1 (rtx dest, rtx *loc)
551 : {
552 40414172 : rtx x = *loc;
553 40414172 : enum rtx_code code = GET_CODE (x);
554 40414172 : rtx *result = NULL;
555 40414172 : rtx *this_result;
556 40414172 : int i;
557 40414172 : const char *fmt;
558 :
559 40414172 : switch (code)
560 : {
561 : case CONST:
562 : case LABEL_REF:
563 : case SYMBOL_REF:
564 : CASE_CONST_ANY:
565 : case CLOBBER:
566 : return 0;
567 :
568 6982650 : case SET:
569 : /* If the destination is anything other than PC, a REG or a SUBREG
570 : of a REG that occupies all of the REG, the insn uses DEST if
571 : it is mentioned in the destination or the source. Otherwise, we
572 : need just check the source. */
573 6982650 : if (GET_CODE (SET_DEST (x)) != PC
574 6982650 : && !REG_P (SET_DEST (x))
575 6985218 : && ! (GET_CODE (SET_DEST (x)) == SUBREG
576 2568 : && REG_P (SUBREG_REG (SET_DEST (x)))
577 2568 : && !read_modify_subreg_p (SET_DEST (x))))
578 : break;
579 :
580 6981239 : return find_single_use_1 (dest, &SET_SRC (x));
581 :
582 46455 : case MEM:
583 46455 : case SUBREG:
584 46455 : return find_single_use_1 (dest, &XEXP (x, 0));
585 :
586 : default:
587 : break;
588 : }
589 :
590 : /* If it wasn't one of the common cases above, check each expression and
591 : vector of this code. Look for a unique usage of DEST. */
592 :
593 20112378 : fmt = GET_RTX_FORMAT (code);
594 53776031 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
595 : {
596 33671121 : if (fmt[i] == 'e')
597 : {
598 33287237 : if (dest == XEXP (x, i)
599 33287237 : || (REG_P (dest) && REG_P (XEXP (x, i))
600 872407 : && REGNO (dest) == REGNO (XEXP (x, i))))
601 : this_result = loc;
602 : else
603 26301793 : this_result = find_single_use_1 (dest, &XEXP (x, i));
604 :
605 33287237 : if (result == NULL)
606 : result = this_result;
607 40807 : else if (this_result)
608 : /* Duplicate usage. */
609 : return NULL;
610 : }
611 383884 : else if (fmt[i] == 'E')
612 : {
613 51493 : int j;
614 :
615 156767 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
616 : {
617 109371 : if (XVECEXP (x, i, j) == dest
618 109371 : || (REG_P (dest)
619 109371 : && REG_P (XVECEXP (x, i, j))
620 4599 : && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
621 : this_result = loc;
622 : else
623 109371 : this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
624 :
625 109371 : if (result == NULL)
626 : result = this_result;
627 17092 : else if (this_result)
628 : return NULL;
629 : }
630 : }
631 : }
632 :
633 : return result;
634 : }
635 :
636 :
637 : /* See if DEST, produced in INSN, is used only a single time in the
638 : sequel. If so, return a pointer to the innermost rtx expression in which
639 : it is used.
640 :
641 : If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 :
643 : Otherwise, we find the single use by finding an insn that has a
644 : LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
645 : only referenced once in that insn, we know that it must be the first
646 : and last insn referencing DEST. */
647 :
648 : static rtx *
649 7597554 : find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
650 : {
651 7597554 : basic_block bb;
652 7597554 : rtx_insn *next;
653 7597554 : rtx *result;
654 7597554 : struct insn_link *link;
655 :
656 7597554 : if (!REG_P (dest))
657 : return 0;
658 :
659 7597554 : bb = BLOCK_FOR_INSN (insn);
660 10527522 : for (next = NEXT_INSN (insn);
661 10527522 : next && BLOCK_FOR_INSN (next) == bb;
662 2929968 : next = NEXT_INSN (next))
663 9905282 : if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
664 : {
665 9325374 : FOR_EACH_LOG_LINK (link, next)
666 8279248 : if (link->insn == insn && link->regno == REGNO (dest))
667 : break;
668 :
669 8021440 : if (link)
670 : {
671 6975314 : result = find_single_use_1 (dest, &PATTERN (next));
672 6975314 : if (ploc)
673 6975313 : *ploc = next;
674 : return result;
675 : }
676 : }
677 :
678 : return 0;
679 : }
680 :
681 : /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 : insn. The substitution can be undone by undo_all. If INTO is already
683 : set to NEWVAL, do not record this change. Because computing NEWVAL might
684 : also call SUBST, we have to compute it before we put anything into
685 : the undo table. */
686 :
687 : static void
688 764985393 : do_SUBST (rtx *into, rtx newval)
689 : {
690 764985393 : struct undo *buf;
691 764985393 : rtx oldval = *into;
692 :
693 764985393 : if (oldval == newval)
694 : return;
695 :
696 : /* We'd like to catch as many invalid transformations here as
697 : possible. Unfortunately, there are way too many mode changes
698 : that are perfectly valid, so we'd waste too much effort for
699 : little gain doing the checks here. Focus on catching invalid
700 : transformations involving integer constants. */
701 96670100 : if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 58593731 : && CONST_INT_P (newval))
703 : {
704 : /* Sanity check that we're replacing oldval with a CONST_INT
705 : that is a valid sign-extension for the original mode. */
706 1825363 : gcc_assert (INTVAL (newval)
707 : == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 :
709 : /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 : CONST_INT is not valid, because after the replacement, the
711 : original mode would be gone. Unfortunately, we can't tell
712 : when do_SUBST is called to replace the operand thereof, so we
713 : perform this test on oldval instead, checking whether an
714 : invalid replacement took place before we got here. */
715 1825363 : gcc_assert (!(GET_CODE (oldval) == SUBREG
716 : && CONST_INT_P (SUBREG_REG (oldval))));
717 1825363 : gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 : && CONST_INT_P (XEXP (oldval, 0))));
719 : }
720 :
721 96670100 : if (undobuf.frees)
722 92497180 : buf = undobuf.frees, undobuf.frees = buf->next;
723 : else
724 4172920 : buf = XNEW (struct undo);
725 :
726 96670100 : buf->kind = UNDO_RTX;
727 96670100 : buf->where.r = into;
728 96670100 : buf->old_contents.r = oldval;
729 96670100 : *into = newval;
730 :
731 96670100 : buf->next = undobuf.undos, undobuf.undos = buf;
732 : }
733 :
734 : #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
735 :
736 : /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 : for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 : not safe. */
739 :
740 : static void
741 16208127 : do_SUBST_INT (int *into, int newval)
742 : {
743 16208127 : struct undo *buf;
744 16208127 : int oldval = *into;
745 :
746 16208127 : if (oldval == newval)
747 : return;
748 :
749 6973494 : if (undobuf.frees)
750 6448784 : buf = undobuf.frees, undobuf.frees = buf->next;
751 : else
752 524710 : buf = XNEW (struct undo);
753 :
754 6973494 : buf->kind = UNDO_INT;
755 6973494 : buf->where.i = into;
756 6973494 : buf->old_contents.i = oldval;
757 6973494 : *into = newval;
758 :
759 6973494 : buf->next = undobuf.undos, undobuf.undos = buf;
760 : }
761 :
762 : #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
763 :
764 : /* Similar to SUBST, but just substitute the mode. This is used when
765 : changing the mode of a pseudo-register, so that any other
766 : references to the entry in the regno_reg_rtx array will change as
767 : well. */
768 :
769 : static void
770 1459192 : subst_mode (int regno, machine_mode newval)
771 : {
772 1459192 : struct undo *buf;
773 1459192 : rtx reg = regno_reg_rtx[regno];
774 1459192 : machine_mode oldval = GET_MODE (reg);
775 :
776 1459192 : if (oldval == newval)
777 : return;
778 :
779 1459192 : if (undobuf.frees)
780 1379513 : buf = undobuf.frees, undobuf.frees = buf->next;
781 : else
782 79679 : buf = XNEW (struct undo);
783 :
784 1459192 : buf->kind = UNDO_MODE;
785 1459192 : buf->where.regno = regno;
786 1459192 : buf->old_contents.m = oldval;
787 1459192 : adjust_reg_mode (reg, newval);
788 :
789 1459192 : buf->next = undobuf.undos, undobuf.undos = buf;
790 : }
791 :
792 : /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
793 :
794 : static void
795 71004 : do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
796 : {
797 71004 : struct undo *buf;
798 71004 : struct insn_link * oldval = *into;
799 :
800 71004 : if (oldval == newval)
801 : return;
802 :
803 71004 : if (undobuf.frees)
804 67892 : buf = undobuf.frees, undobuf.frees = buf->next;
805 : else
806 3112 : buf = XNEW (struct undo);
807 :
808 71004 : buf->kind = UNDO_LINKS;
809 71004 : buf->where.l = into;
810 71004 : buf->old_contents.l = oldval;
811 71004 : *into = newval;
812 :
813 71004 : buf->next = undobuf.undos, undobuf.undos = buf;
814 : }
815 :
816 : #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
817 :
818 : /* Subroutine of try_combine. Determine whether the replacement patterns
819 : NEWPAT, NEWI2PAT and NEWOTHERPAT are more expensive according to insn_cost
820 : than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
821 : that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
822 : undobuf.other_insn may also both be NULL_RTX. Return false if the cost
823 : of all the instructions can be estimated and the replacements are more
824 : expensive than the original sequence. */
825 :
826 : static bool
827 4280689 : combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
828 : rtx newpat, rtx newi2pat, rtx newotherpat,
829 : int insn_code, int i2_code, int other_code)
830 : {
831 4280689 : int i0_cost, i1_cost, i2_cost, i3_cost;
832 4280689 : int new_i2_cost, new_i3_cost;
833 4280689 : int old_cost, new_cost;
834 :
835 : /* Lookup the original insn_costs. */
836 4280689 : i2_cost = INSN_COST (i2);
837 4280689 : i3_cost = INSN_COST (i3);
838 :
839 4280689 : if (i1)
840 : {
841 120748 : i1_cost = INSN_COST (i1);
842 120748 : if (i0)
843 : {
844 4871 : i0_cost = INSN_COST (i0);
845 4738 : old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
846 9597 : ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
847 : }
848 : else
849 : {
850 111297 : old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
851 227172 : ? i1_cost + i2_cost + i3_cost : 0);
852 : i0_cost = 0;
853 : }
854 : }
855 : else
856 : {
857 4159941 : old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
858 : i1_cost = i0_cost = 0;
859 : }
860 :
861 : /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
862 : correct that. */
863 4280689 : if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
864 2231 : old_cost -= i1_cost;
865 :
866 :
867 : /* Calculate the replacement insn_costs. */
868 4280689 : rtx tmp = PATTERN (i3);
869 4280689 : PATTERN (i3) = newpat;
870 4280689 : int tmpi = INSN_CODE (i3);
871 4280689 : INSN_CODE (i3) = insn_code;
872 4280689 : new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
873 4280689 : PATTERN (i3) = tmp;
874 4280689 : INSN_CODE (i3) = tmpi;
875 4280689 : if (newi2pat)
876 : {
877 213996 : tmp = PATTERN (i2);
878 213996 : PATTERN (i2) = newi2pat;
879 213996 : tmpi = INSN_CODE (i2);
880 213996 : INSN_CODE (i2) = i2_code;
881 213996 : new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
882 213996 : PATTERN (i2) = tmp;
883 213996 : INSN_CODE (i2) = tmpi;
884 213996 : new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
885 213996 : ? new_i2_cost + new_i3_cost : 0;
886 : }
887 : else
888 : {
889 : new_cost = new_i3_cost;
890 : new_i2_cost = 0;
891 : }
892 :
893 4280689 : if (undobuf.other_insn)
894 : {
895 223973 : int old_other_cost, new_other_cost;
896 :
897 223973 : old_other_cost = INSN_COST (undobuf.other_insn);
898 223973 : tmp = PATTERN (undobuf.other_insn);
899 223973 : PATTERN (undobuf.other_insn) = newotherpat;
900 223973 : tmpi = INSN_CODE (undobuf.other_insn);
901 223973 : INSN_CODE (undobuf.other_insn) = other_code;
902 223973 : new_other_cost = insn_cost (undobuf.other_insn,
903 : optimize_this_for_speed_p);
904 223973 : PATTERN (undobuf.other_insn) = tmp;
905 223973 : INSN_CODE (undobuf.other_insn) = tmpi;
906 223973 : if (old_other_cost > 0 && new_other_cost > 0)
907 : {
908 223973 : old_cost += old_other_cost;
909 223973 : new_cost += new_other_cost;
910 : }
911 : else
912 : old_cost = 0;
913 : }
914 :
915 : /* Disallow this combination if both new_cost and old_cost are greater than
916 : zero, and new_cost is greater than old cost. */
917 4280689 : bool reject = old_cost > 0 && new_cost > old_cost;
918 :
919 4280689 : if (dump_file)
920 : {
921 484 : fprintf (dump_file, "%s combination of insns ",
922 : reject ? "rejecting" : "allowing");
923 244 : if (i0)
924 0 : fprintf (dump_file, "%d, ", INSN_UID (i0));
925 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
926 1 : fprintf (dump_file, "%d, ", INSN_UID (i1));
927 244 : fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
928 :
929 244 : fprintf (dump_file, "original costs ");
930 244 : if (i0)
931 0 : fprintf (dump_file, "%d + ", i0_cost);
932 244 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
933 1 : fprintf (dump_file, "%d + ", i1_cost);
934 244 : fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
935 :
936 244 : if (newi2pat)
937 19 : fprintf (dump_file, "replacement costs %d + %d = %d\n",
938 : new_i2_cost, new_i3_cost, new_cost);
939 : else
940 225 : fprintf (dump_file, "replacement cost %d\n", new_cost);
941 : }
942 :
943 4280689 : if (reject)
944 : return false;
945 :
946 : /* Update the uid_insn_cost array with the replacement costs. */
947 4067319 : INSN_COST (i2) = new_i2_cost;
948 4067319 : INSN_COST (i3) = new_i3_cost;
949 4067319 : if (i1)
950 : {
951 101859 : INSN_COST (i1) = 0;
952 101859 : if (i0)
953 4511 : INSN_COST (i0) = 0;
954 : }
955 :
956 : return true;
957 : }
958 :
959 :
960 : /* Delete any insns that copy a register to itself.
961 : Return true if the CFG was changed. */
962 :
963 : static bool
964 1019761 : delete_noop_moves (void)
965 : {
966 1019761 : rtx_insn *insn, *next;
967 1019761 : basic_block bb;
968 :
969 1019761 : bool edges_deleted = false;
970 :
971 11550062 : FOR_EACH_BB_FN (bb, cfun)
972 : {
973 143315735 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
974 : {
975 132785434 : next = NEXT_INSN (insn);
976 132785434 : if (INSN_P (insn) && noop_move_p (insn))
977 : {
978 6508 : if (dump_file)
979 0 : fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
980 :
981 6508 : edges_deleted |= delete_insn_and_edges (insn);
982 : }
983 : }
984 : }
985 :
986 1019761 : return edges_deleted;
987 : }
988 :
989 :
990 : /* Return false if we do not want to (or cannot) combine DEF. */
991 : static bool
992 42766787 : can_combine_def_p (df_ref def)
993 : {
994 : /* Do not consider if it is pre/post modification in MEM. */
995 42766787 : if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
996 : return false;
997 :
998 41090324 : unsigned int regno = DF_REF_REGNO (def);
999 :
1000 : /* Do not combine frame pointer adjustments. */
1001 41090324 : if ((regno == FRAME_POINTER_REGNUM
1002 0 : && (!reload_completed || frame_pointer_needed))
1003 2062 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 41090324 : && regno == HARD_FRAME_POINTER_REGNUM
1005 : && (!reload_completed || frame_pointer_needed))
1006 41088262 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1007 0 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1008 2062 : return false;
1009 :
1010 : return true;
1011 : }
1012 :
1013 : /* Return false if we do not want to (or cannot) combine USE. */
1014 : static bool
1015 79246309 : can_combine_use_p (df_ref use)
1016 : {
1017 : /* Do not consider the usage of the stack pointer by function call. */
1018 0 : if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1019 0 : return false;
1020 :
1021 : return true;
1022 : }
1023 :
1024 : /* Fill in log links field for all insns. */
1025 :
1026 : static void
1027 1019761 : create_log_links (void)
1028 : {
1029 1019761 : basic_block bb;
1030 1019761 : rtx_insn **next_use;
1031 1019761 : rtx_insn *insn;
1032 1019761 : df_ref def, use;
1033 :
1034 1019761 : next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1035 :
1036 : /* Pass through each block from the end, recording the uses of each
1037 : register and establishing log links when def is encountered.
1038 : Note that we do not clear next_use array in order to save time,
1039 : so we have to test whether the use is in the same basic block as def.
1040 :
1041 : There are a few cases below when we do not consider the definition or
1042 : usage -- these are taken from original flow.c did. Don't ask me why it is
1043 : done this way; I don't know and if it works, I don't want to know. */
1044 :
1045 11550062 : FOR_EACH_BB_FN (bb, cfun)
1046 : {
1047 143299206 : FOR_BB_INSNS_REVERSE (bb, insn)
1048 : {
1049 132768905 : if (!NONDEBUG_INSN_P (insn))
1050 69787353 : continue;
1051 :
1052 : /* Log links are created only once. */
1053 62981552 : gcc_assert (!LOG_LINKS (insn));
1054 :
1055 516826931 : FOR_EACH_INSN_DEF (def, insn)
1056 : {
1057 453845379 : unsigned int regno = DF_REF_REGNO (def);
1058 453845379 : rtx_insn *use_insn;
1059 :
1060 453845379 : if (!next_use[regno])
1061 411078592 : continue;
1062 :
1063 42766787 : if (!can_combine_def_p (def))
1064 1678525 : continue;
1065 :
1066 41088262 : use_insn = next_use[regno];
1067 41088262 : next_use[regno] = NULL;
1068 :
1069 41088262 : if (BLOCK_FOR_INSN (use_insn) != bb)
1070 2278295 : continue;
1071 :
1072 : /* flow.c claimed:
1073 :
1074 : We don't build a LOG_LINK for hard registers contained
1075 : in ASM_OPERANDs. If these registers get replaced,
1076 : we might wind up changing the semantics of the insn,
1077 : even if reload can make what appear to be valid
1078 : assignments later. */
1079 38810819 : if (regno < FIRST_PSEUDO_REGISTER
1080 38809967 : && asm_noperands (PATTERN (use_insn)) >= 0)
1081 852 : continue;
1082 :
1083 : /* Don't add duplicate links between instructions. */
1084 38809115 : struct insn_link *links;
1085 52046028 : FOR_EACH_LOG_LINK (links, use_insn)
1086 13236913 : if (insn == links->insn && regno == links->regno)
1087 : break;
1088 :
1089 38809115 : if (!links)
1090 38809115 : LOG_LINKS (use_insn)
1091 77618230 : = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1092 : }
1093 :
1094 142227861 : FOR_EACH_INSN_USE (use, insn)
1095 153719883 : if (can_combine_use_p (use))
1096 74473574 : next_use[DF_REF_REGNO (use)] = insn;
1097 : }
1098 : }
1099 :
1100 1019761 : free (next_use);
1101 1019761 : }
1102 :
1103 : /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 : true if we found a LOG_LINK that proves that A feeds B. This only works
1105 : if there are no instructions between A and B which could have a link
1106 : depending on A, since in that case we would not record a link for B. */
1107 :
1108 : static bool
1109 13282696 : insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1110 : {
1111 13282696 : struct insn_link *links;
1112 16729652 : FOR_EACH_LOG_LINK (links, b)
1113 14094826 : if (links->insn == a)
1114 : return true;
1115 : return false;
1116 : }
1117 :
1118 : /* Main entry point for combiner. F is the first insn of the function.
1119 : NREGS is the first unused pseudo-reg number.
1120 :
1121 : Return nonzero if the CFG was changed (e.g. if the combiner has
1122 : turned an indirect jump instruction into a direct jump). */
1123 : static bool
1124 1064387 : combine_instructions (rtx_insn *f, unsigned int nregs)
1125 : {
1126 1064387 : rtx_insn *insn, *next;
1127 1064387 : struct insn_link *links, *nextlinks;
1128 1064387 : rtx_insn *first;
1129 1064387 : basic_block last_bb;
1130 :
1131 1064387 : bool new_direct_jump_p = false;
1132 :
1133 3187835 : for (first = f; first && !NONDEBUG_INSN_P (first); )
1134 2123448 : first = NEXT_INSN (first);
1135 1064387 : if (!first)
1136 : return false;
1137 :
1138 1019761 : combine_attempts = 0;
1139 1019761 : combine_merges = 0;
1140 1019761 : combine_extras = 0;
1141 1019761 : combine_successes = 0;
1142 :
1143 1019761 : rtl_hooks = combine_rtl_hooks;
1144 :
1145 1019761 : reg_stat.safe_grow_cleared (nregs, true);
1146 :
1147 1019761 : init_recog_no_volatile ();
1148 :
1149 : /* Allocate array for insn info. */
1150 1019761 : max_uid_known = get_max_uid ();
1151 1019761 : uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1152 1019761 : uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1153 1019761 : gcc_obstack_init (&insn_link_obstack);
1154 :
1155 1019761 : nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1156 :
1157 : /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1158 : problems when, for example, we have j <<= 1 in a loop. */
1159 :
1160 1019761 : nonzero_sign_valid = 0;
1161 1019761 : label_tick = label_tick_ebb_start = 1;
1162 :
1163 : /* Scan all SETs and see if we can deduce anything about what
1164 : bits are known to be zero for some registers and how many copies
1165 : of the sign bit are known to exist for those registers.
1166 :
1167 : Also set any known values so that we can use it while searching
1168 : for what bits are known to be set. */
1169 :
1170 1019761 : setup_incoming_promotions (first);
1171 : /* Allow the entry block and the first block to fall into the same EBB.
1172 : Conceptually the incoming promotions are assigned to the entry block. */
1173 1019761 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1174 :
1175 1019761 : create_log_links ();
1176 11550062 : FOR_EACH_BB_FN (this_basic_block, cfun)
1177 : {
1178 10530301 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1179 10530301 : last_call_luid = 0;
1180 10530301 : mem_last_set = -1;
1181 :
1182 10530301 : label_tick++;
1183 10530301 : if (!single_pred_p (this_basic_block)
1184 10530301 : || single_pred (this_basic_block) != last_bb)
1185 5049571 : label_tick_ebb_start = label_tick;
1186 10530301 : last_bb = this_basic_block;
1187 :
1188 143299206 : FOR_BB_INSNS (this_basic_block, insn)
1189 132768905 : if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1190 : {
1191 116068591 : rtx links;
1192 :
1193 116068591 : subst_low_luid = DF_INSN_LUID (insn);
1194 116068591 : subst_insn = insn;
1195 :
1196 116068591 : note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1197 116068591 : record_dead_and_set_regs (insn);
1198 :
1199 116068591 : if (AUTO_INC_DEC)
1200 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1201 : if (REG_NOTE_KIND (links) == REG_INC)
1202 : set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1203 : insn);
1204 :
1205 : /* Record the current insn_cost of this instruction. */
1206 116068591 : INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1207 116068591 : if (dump_file)
1208 : {
1209 1695 : fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1210 1695 : dump_insn_slim (dump_file, insn);
1211 : }
1212 : }
1213 : }
1214 :
1215 1019761 : nonzero_sign_valid = 1;
1216 :
1217 : /* Now scan all the insns in forward order. */
1218 1019761 : label_tick = label_tick_ebb_start = 1;
1219 1019761 : init_reg_last ();
1220 1019761 : setup_incoming_promotions (first);
1221 1019761 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1222 1019761 : int max_combine = param_max_combine_insns;
1223 :
1224 11550062 : FOR_EACH_BB_FN (this_basic_block, cfun)
1225 : {
1226 10530301 : rtx_insn *last_combined_insn = NULL;
1227 :
1228 : /* Ignore instruction combination in basic blocks that are going to
1229 : be removed as unreachable anyway. See PR82386. */
1230 10530301 : if (EDGE_COUNT (this_basic_block->preds) == 0)
1231 1647 : continue;
1232 :
1233 10528654 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1234 10528654 : last_call_luid = 0;
1235 10528654 : mem_last_set = -1;
1236 :
1237 10528654 : label_tick++;
1238 10528654 : if (!single_pred_p (this_basic_block)
1239 10528654 : || single_pred (this_basic_block) != last_bb)
1240 5049218 : label_tick_ebb_start = label_tick;
1241 10528654 : last_bb = this_basic_block;
1242 :
1243 10528654 : rtl_profile_for_bb (this_basic_block);
1244 10528654 : for (insn = BB_HEAD (this_basic_block);
1245 147861725 : insn != NEXT_INSN (BB_END (this_basic_block));
1246 133265752 : insn = next ? next : NEXT_INSN (insn))
1247 : {
1248 137333071 : next = 0;
1249 137333071 : if (!NONDEBUG_INSN_P (insn))
1250 69993119 : continue;
1251 :
1252 : while (last_combined_insn
1253 67341738 : && (!NONDEBUG_INSN_P (last_combined_insn)
1254 57000967 : || last_combined_insn->deleted ()))
1255 1786 : last_combined_insn = PREV_INSN (last_combined_insn);
1256 67339952 : if (last_combined_insn == NULL_RTX
1257 57000381 : || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1258 124340127 : || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1259 : last_combined_insn = insn;
1260 :
1261 : /* See if we know about function return values before this
1262 : insn based upon SUBREG flags. */
1263 67339952 : check_promoted_subreg (insn, PATTERN (insn));
1264 :
1265 : /* See if we can find hardregs and subreg of pseudos in
1266 : narrower modes. This could help turning TRUNCATEs
1267 : into SUBREGs. */
1268 67339952 : note_uses (&PATTERN (insn), record_truncated_values, NULL);
1269 :
1270 : /* Try this insn with each insn it links back to. */
1271 :
1272 105223972 : FOR_EACH_LOG_LINK (links, insn)
1273 41824953 : if ((next = try_combine (insn, links->insn, NULL,
1274 : NULL, &new_direct_jump_p,
1275 : last_combined_insn)) != 0)
1276 : {
1277 3940933 : statistics_counter_event (cfun, "two-insn combine", 1);
1278 3940933 : goto retry;
1279 : }
1280 :
1281 : /* Try each sequence of three linked insns ending with this one. */
1282 :
1283 63399019 : if (max_combine >= 3)
1284 100680236 : FOR_EACH_LOG_LINK (links, insn)
1285 : {
1286 37462817 : rtx_insn *link = links->insn;
1287 :
1288 : /* If the linked insn has been replaced by a note, then there
1289 : is no point in pursuing this chain any further. */
1290 37462817 : if (NOTE_P (link))
1291 227 : continue;
1292 :
1293 55798715 : FOR_EACH_LOG_LINK (nextlinks, link)
1294 18415776 : if ((next = try_combine (insn, link, nextlinks->insn,
1295 : NULL, &new_direct_jump_p,
1296 : last_combined_insn)) != 0)
1297 : {
1298 79651 : statistics_counter_event (cfun, "three-insn combine", 1);
1299 79651 : goto retry;
1300 : }
1301 : }
1302 :
1303 : /* Try combining an insn with two different insns whose results it
1304 : uses. */
1305 63217419 : if (max_combine >= 3)
1306 100563518 : FOR_EACH_LOG_LINK (links, insn)
1307 50278644 : for (nextlinks = links->next; nextlinks;
1308 12917291 : nextlinks = nextlinks->next)
1309 12932545 : if ((next = try_combine (insn, links->insn,
1310 : nextlinks->insn, NULL,
1311 : &new_direct_jump_p,
1312 : last_combined_insn)) != 0)
1313 :
1314 : {
1315 15254 : statistics_counter_event (cfun, "three-insn combine", 1);
1316 15254 : goto retry;
1317 : }
1318 :
1319 : /* Try four-instruction combinations. */
1320 63202165 : if (max_combine >= 4)
1321 100540616 : FOR_EACH_LOG_LINK (links, insn)
1322 : {
1323 37342905 : struct insn_link *next1;
1324 37342905 : rtx_insn *link = links->insn;
1325 :
1326 : /* If the linked insn has been replaced by a note, then there
1327 : is no point in pursuing this chain any further. */
1328 37342905 : if (NOTE_P (link))
1329 226 : continue;
1330 :
1331 55655738 : FOR_EACH_LOG_LINK (next1, link)
1332 : {
1333 18314423 : rtx_insn *link1 = next1->insn;
1334 18314423 : if (NOTE_P (link1))
1335 76 : continue;
1336 : /* I0 -> I1 -> I2 -> I3. */
1337 29951055 : FOR_EACH_LOG_LINK (nextlinks, link1)
1338 11637958 : if ((next = try_combine (insn, link, link1,
1339 : nextlinks->insn,
1340 : &new_direct_jump_p,
1341 : last_combined_insn)) != 0)
1342 : {
1343 1250 : statistics_counter_event (cfun, "four-insn combine", 1);
1344 1250 : goto retry;
1345 : }
1346 : /* I0, I1 -> I2, I2 -> I3. */
1347 22292651 : for (nextlinks = next1->next; nextlinks;
1348 3979554 : nextlinks = nextlinks->next)
1349 3979668 : if ((next = try_combine (insn, link, link1,
1350 : nextlinks->insn,
1351 : &new_direct_jump_p,
1352 : last_combined_insn)) != 0)
1353 : {
1354 114 : statistics_counter_event (cfun, "four-insn combine", 1);
1355 114 : goto retry;
1356 : }
1357 : }
1358 :
1359 50255259 : for (next1 = links->next; next1; next1 = next1->next)
1360 : {
1361 12916955 : rtx_insn *link1 = next1->insn;
1362 12916955 : if (NOTE_P (link1))
1363 8 : continue;
1364 : /* I0 -> I2; I1, I2 -> I3. */
1365 16376164 : FOR_EACH_LOG_LINK (nextlinks, link)
1366 3462044 : if ((next = try_combine (insn, link, link1,
1367 : nextlinks->insn,
1368 : &new_direct_jump_p,
1369 : last_combined_insn)) != 0)
1370 : {
1371 2827 : statistics_counter_event (cfun, "four-insn combine", 1);
1372 2827 : goto retry;
1373 : }
1374 : /* I0 -> I1; I1, I2 -> I3. */
1375 16617083 : FOR_EACH_LOG_LINK (nextlinks, link1)
1376 3703147 : if ((next = try_combine (insn, link, link1,
1377 : nextlinks->insn,
1378 : &new_direct_jump_p,
1379 : last_combined_insn)) != 0)
1380 : {
1381 184 : statistics_counter_event (cfun, "four-insn combine", 1);
1382 184 : goto retry;
1383 : }
1384 : }
1385 : }
1386 :
1387 : /* Try this insn with each REG_EQUAL note it links back to. */
1388 100662992 : FOR_EACH_LOG_LINK (links, insn)
1389 : {
1390 37390359 : rtx set, note;
1391 37390359 : rtx_insn *temp = links->insn;
1392 37390359 : if ((set = single_set (temp)) != 0
1393 36997789 : && (note = find_reg_equal_equiv_note (temp)) != 0
1394 2757588 : && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1395 2757588 : && ! side_effects_p (SET_SRC (set))
1396 : /* Avoid using a register that may already been marked
1397 : dead by an earlier instruction. */
1398 2757588 : && ! unmentioned_reg_p (note, SET_SRC (set))
1399 38753173 : && (GET_MODE (note) == VOIDmode
1400 26918 : ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1401 1335896 : : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1402 1335863 : && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1403 0 : || (GET_MODE (XEXP (SET_DEST (set), 0))
1404 : == GET_MODE (note))))))
1405 : {
1406 : /* Temporarily replace the set's source with the
1407 : contents of the REG_EQUAL note. The insn will
1408 : be deleted or recognized by try_combine. */
1409 1362764 : rtx orig_src = SET_SRC (set);
1410 1362764 : rtx orig_dest = SET_DEST (set);
1411 1362764 : if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1412 0 : SET_DEST (set) = XEXP (SET_DEST (set), 0);
1413 1362764 : SET_SRC (set) = note;
1414 1362764 : i2mod = temp;
1415 1362764 : i2mod_old_rhs = copy_rtx (orig_src);
1416 1362764 : i2mod_new_rhs = copy_rtx (note);
1417 1362764 : next = try_combine (insn, i2mod, NULL, NULL,
1418 : &new_direct_jump_p,
1419 : last_combined_insn);
1420 1362764 : i2mod = NULL;
1421 1362764 : if (next)
1422 : {
1423 27106 : statistics_counter_event (cfun, "insn-with-note combine", 1);
1424 27106 : goto retry;
1425 : }
1426 1335658 : INSN_CODE (temp) = -1;
1427 1335658 : SET_SRC (set) = orig_src;
1428 1335658 : SET_DEST (set) = orig_dest;
1429 : }
1430 : }
1431 :
1432 63272633 : if (!NOTE_P (insn))
1433 63272633 : record_dead_and_set_regs (insn);
1434 :
1435 137333071 : retry:
1436 137333071 : ;
1437 : }
1438 : }
1439 :
1440 1019761 : default_rtl_profile ();
1441 1019761 : clear_bb_flags ();
1442 :
1443 1019761 : if (purge_all_dead_edges ())
1444 1280 : new_direct_jump_p = true;
1445 1019761 : if (delete_noop_moves ())
1446 0 : new_direct_jump_p = true;
1447 :
1448 : /* Clean up. */
1449 1019761 : obstack_free (&insn_link_obstack, NULL);
1450 1019761 : free (uid_log_links);
1451 1019761 : free (uid_insn_cost);
1452 1019761 : reg_stat.release ();
1453 :
1454 1019761 : {
1455 1019761 : struct undo *undo, *next;
1456 5800182 : for (undo = undobuf.frees; undo; undo = next)
1457 : {
1458 4780421 : next = undo->next;
1459 4780421 : free (undo);
1460 : }
1461 1019761 : undobuf.frees = 0;
1462 : }
1463 :
1464 1019761 : statistics_counter_event (cfun, "attempts", combine_attempts);
1465 1019761 : statistics_counter_event (cfun, "merges", combine_merges);
1466 1019761 : statistics_counter_event (cfun, "extras", combine_extras);
1467 1019761 : statistics_counter_event (cfun, "successes", combine_successes);
1468 :
1469 1019761 : nonzero_sign_valid = 0;
1470 1019761 : rtl_hooks = general_rtl_hooks;
1471 :
1472 : /* Make recognizer allow volatile MEMs again. */
1473 1019761 : init_recog ();
1474 :
1475 1019761 : return new_direct_jump_p;
1476 : }
1477 :
1478 : /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1479 :
1480 : static void
1481 1019761 : init_reg_last (void)
1482 : {
1483 1019761 : unsigned int i;
1484 1019761 : reg_stat_type *p;
1485 :
1486 147496030 : FOR_EACH_VEC_ELT (reg_stat, i, p)
1487 146476269 : memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1488 1019761 : }
1489 :
1490 : /* Set up any promoted values for incoming argument registers. */
1491 :
1492 : static void
1493 2039522 : setup_incoming_promotions (rtx_insn *first)
1494 : {
1495 2039522 : tree arg;
1496 2039522 : bool strictly_local = false;
1497 :
1498 5521380 : for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 3481858 : arg = DECL_CHAIN (arg))
1500 : {
1501 3481858 : rtx x, reg = DECL_INCOMING_RTL (arg);
1502 3481858 : int uns1, uns3;
1503 3481858 : machine_mode mode1, mode2, mode3, mode4;
1504 :
1505 : /* Only continue if the incoming argument is in a register. */
1506 3481858 : if (!REG_P (reg))
1507 3481758 : continue;
1508 :
1509 : /* Determine, if possible, whether all call sites of the current
1510 : function lie within the current compilation unit. (This does
1511 : take into account the exporting of a function via taking its
1512 : address, and so forth.) */
1513 2739676 : strictly_local
1514 2739676 : = cgraph_node::local_info_node (current_function_decl)->local;
1515 :
1516 : /* The mode and signedness of the argument before any promotions happen
1517 : (equal to the mode of the pseudo holding it at that stage). */
1518 2739676 : mode1 = TYPE_MODE (TREE_TYPE (arg));
1519 2739676 : uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1520 :
1521 : /* The mode and signedness of the argument after any source language and
1522 : TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1523 2739676 : mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1524 2739676 : uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1525 :
1526 : /* The mode and signedness of the argument as it is actually passed,
1527 : see assign_parm_setup_reg in function.cc. */
1528 2739676 : mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1529 2739676 : TREE_TYPE (cfun->decl), 0);
1530 :
1531 : /* The mode of the register in which the argument is being passed. */
1532 2739676 : mode4 = GET_MODE (reg);
1533 :
1534 : /* Eliminate sign extensions in the callee when:
1535 : (a) A mode promotion has occurred; */
1536 2739676 : if (mode1 == mode3)
1537 2739576 : continue;
1538 : /* (b) The mode of the register is the same as the mode of
1539 : the argument as it is passed; */
1540 100 : if (mode3 != mode4)
1541 0 : continue;
1542 : /* (c) There's no language level extension; */
1543 100 : if (mode1 == mode2)
1544 : ;
1545 : /* (c.1) All callers are from the current compilation unit. If that's
1546 : the case we don't have to rely on an ABI, we only have to know
1547 : what we're generating right now, and we know that we will do the
1548 : mode1 to mode2 promotion with the given sign. */
1549 0 : else if (!strictly_local)
1550 0 : continue;
1551 : /* (c.2) The combination of the two promotions is useful. This is
1552 : true when the signs match, or if the first promotion is unsigned.
1553 : In the later case, (sign_extend (zero_extend x)) is the same as
1554 : (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1555 0 : else if (uns1)
1556 0 : uns3 = true;
1557 0 : else if (uns3)
1558 0 : continue;
1559 :
1560 : /* Record that the value was promoted from mode1 to mode3,
1561 : so that any sign extension at the head of the current
1562 : function may be eliminated. */
1563 100 : x = gen_rtx_CLOBBER (mode1, const0_rtx);
1564 100 : x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1565 100 : record_value_for_reg (reg, first, x);
1566 : }
1567 2039522 : }
1568 :
1569 : /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1570 : that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1571 : because some machines (maybe most) will actually do the sign-extension and
1572 : this is the conservative approach.
1573 :
1574 : ??? For 2.5, try to tighten up the MD files in this regard instead of this
1575 : kludge. */
1576 :
1577 : static rtx
1578 0 : sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1579 : {
1580 0 : scalar_int_mode int_mode;
1581 0 : if (CONST_INT_P (src)
1582 0 : && is_a <scalar_int_mode> (mode, &int_mode)
1583 0 : && GET_MODE_PRECISION (int_mode) < prec
1584 0 : && INTVAL (src) > 0
1585 0 : && val_signbit_known_set_p (int_mode, INTVAL (src)))
1586 0 : src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1587 :
1588 0 : return src;
1589 : }
1590 :
1591 : /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1592 : and SET. */
1593 :
1594 : static void
1595 23815831 : update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1596 : rtx x)
1597 : {
1598 23815831 : rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1599 23815831 : unsigned HOST_WIDE_INT bits = 0;
1600 23815831 : rtx reg_equal = NULL, src = SET_SRC (set);
1601 23815831 : unsigned int num = 0;
1602 :
1603 23815831 : if (reg_equal_note)
1604 1001978 : reg_equal = XEXP (reg_equal_note, 0);
1605 :
1606 23815831 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
1607 : {
1608 : src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1609 : if (reg_equal)
1610 : reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1611 : }
1612 :
1613 : /* Don't call nonzero_bits if it cannot change anything. */
1614 23815831 : if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1615 : {
1616 20605570 : machine_mode mode = GET_MODE (x);
1617 20605570 : if (GET_MODE_CLASS (mode) == MODE_INT
1618 20605570 : && HWI_COMPUTABLE_MODE_P (mode))
1619 20605438 : mode = nonzero_bits_mode;
1620 20605570 : bits = nonzero_bits (src, mode);
1621 20605570 : if (reg_equal && bits)
1622 949632 : bits &= nonzero_bits (reg_equal, mode);
1623 20605570 : rsp->nonzero_bits |= bits;
1624 : }
1625 :
1626 : /* Don't call num_sign_bit_copies if it cannot change anything. */
1627 23815831 : if (rsp->sign_bit_copies != 1)
1628 : {
1629 20455029 : num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1630 20455029 : if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1631 : {
1632 946983 : unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1633 946983 : if (num == 0 || numeq > num)
1634 20455029 : num = numeq;
1635 : }
1636 20455029 : if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1637 19753882 : rsp->sign_bit_copies = num;
1638 : }
1639 23815831 : }
1640 :
1641 : /* Called via note_stores. If X is a pseudo that is narrower than
1642 : HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1643 :
1644 : If we are setting only a portion of X and we can't figure out what
1645 : portion, assume all bits will be used since we don't know what will
1646 : be happening.
1647 :
1648 : Similarly, set how many bits of X are known to be copies of the sign bit
1649 : at all locations in the function. This is the smallest number implied
1650 : by any set of X. */
1651 :
1652 : static void
1653 73353236 : set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1654 : {
1655 73353236 : rtx_insn *insn = (rtx_insn *) data;
1656 73353236 : scalar_int_mode mode;
1657 :
1658 73353236 : if (REG_P (x)
1659 59094409 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1660 : /* If this register is undefined at the start of the file, we can't
1661 : say what its contents were. */
1662 59107248 : && ! REGNO_REG_SET_P
1663 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1664 29453107 : && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1665 98097196 : && HWI_COMPUTABLE_MODE_P (mode))
1666 : {
1667 24023923 : reg_stat_type *rsp = ®_stat[REGNO (x)];
1668 :
1669 24023923 : if (set == 0 || GET_CODE (set) == CLOBBER)
1670 : {
1671 22638 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1672 22638 : rsp->sign_bit_copies = 1;
1673 22638 : return;
1674 : }
1675 :
1676 : /* If this register is being initialized using itself, and the
1677 : register is uninitialized in this basic block, and there are
1678 : no LOG_LINKS which set the register, then part of the
1679 : register is uninitialized. In that case we can't assume
1680 : anything about the number of nonzero bits.
1681 :
1682 : ??? We could do better if we checked this in
1683 : reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1684 : could avoid making assumptions about the insn which initially
1685 : sets the register, while still using the information in other
1686 : insns. We would have to be careful to check every insn
1687 : involved in the combination. */
1688 :
1689 24001285 : if (insn
1690 22593861 : && reg_referenced_p (x, PATTERN (insn))
1691 26630603 : && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1692 : REGNO (x)))
1693 : {
1694 266655 : struct insn_link *link;
1695 :
1696 396885 : FOR_EACH_LOG_LINK (link, insn)
1697 309591 : if (dead_or_set_p (link->insn, x))
1698 : break;
1699 266655 : if (!link)
1700 : {
1701 87294 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1702 87294 : rsp->sign_bit_copies = 1;
1703 87294 : return;
1704 : }
1705 : }
1706 :
1707 : /* If this is a complex assignment, see if we can convert it into a
1708 : simple assignment. */
1709 23913991 : set = expand_field_assignment (set);
1710 :
1711 : /* If this is a simple assignment, or we have a paradoxical SUBREG,
1712 : set what we know about X. */
1713 :
1714 23913991 : if (SET_DEST (set) == x
1715 23913991 : || (paradoxical_subreg_p (SET_DEST (set))
1716 4732 : && SUBREG_REG (SET_DEST (set)) == x))
1717 23815831 : update_rsp_from_reg_equal (rsp, insn, set, x);
1718 : else
1719 : {
1720 98160 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1721 98160 : rsp->sign_bit_copies = 1;
1722 : }
1723 : }
1724 : }
1725 :
1726 : /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1727 : optionally insns that were previously combined into I3 or that will be
1728 : combined into the merger of INSN and I3. The order is PRED, PRED2,
1729 : INSN, SUCC, SUCC2, I3.
1730 :
1731 : Return false if the combination is not allowed for any reason.
1732 :
1733 : If the combination is allowed, *PDEST will be set to the single
1734 : destination of INSN and *PSRC to the single source, and this function
1735 : will return true. */
1736 :
1737 : static bool
1738 62208482 : can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1739 : rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1740 : rtx *pdest, rtx *psrc)
1741 : {
1742 62208482 : int i;
1743 62208482 : const_rtx set = 0;
1744 62208482 : rtx src, dest;
1745 62208482 : rtx_insn *p;
1746 62208482 : rtx link;
1747 62208482 : bool all_adjacent = true;
1748 62208482 : bool (*is_volatile_p) (const_rtx);
1749 :
1750 62208482 : if (succ)
1751 : {
1752 14698424 : if (succ2)
1753 : {
1754 2201589 : if (next_active_insn (succ2) != i3)
1755 198302 : all_adjacent = false;
1756 2201589 : if (next_active_insn (succ) != succ2)
1757 2082024 : all_adjacent = false;
1758 : }
1759 12496835 : else if (next_active_insn (succ) != i3)
1760 2082024 : all_adjacent = false;
1761 14698424 : if (next_active_insn (insn) != succ)
1762 17382859 : all_adjacent = false;
1763 : }
1764 47510058 : else if (next_active_insn (insn) != i3)
1765 17382859 : all_adjacent = false;
1766 :
1767 : /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1768 : or a PARALLEL consisting of such a SET and CLOBBERs.
1769 :
1770 : If INSN has CLOBBER parallel parts, ignore them for our processing.
1771 : By definition, these happen during the execution of the insn. When it
1772 : is merged with another insn, all bets are off. If they are, in fact,
1773 : needed and aren't also supplied in I3, they may be added by
1774 : recog_for_combine. Otherwise, it won't match.
1775 :
1776 : We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1777 : note.
1778 :
1779 : Get the source and destination of INSN. If more than one, can't
1780 : combine. */
1781 :
1782 62208482 : if (GET_CODE (PATTERN (insn)) == SET)
1783 : set = PATTERN (insn);
1784 16336496 : else if (GET_CODE (PATTERN (insn)) == PARALLEL
1785 16336496 : && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1786 : {
1787 48960984 : for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1788 : {
1789 33143407 : rtx elt = XVECEXP (PATTERN (insn), 0, i);
1790 :
1791 33143407 : switch (GET_CODE (elt))
1792 : {
1793 : /* This is important to combine floating point insns
1794 : for the SH4 port. */
1795 137484 : case USE:
1796 : /* Combining an isolated USE doesn't make sense.
1797 : We depend here on combinable_i3pat to reject them. */
1798 : /* The code below this loop only verifies that the inputs of
1799 : the SET in INSN do not change. We call reg_set_between_p
1800 : to verify that the REG in the USE does not change between
1801 : I3 and INSN.
1802 : If the USE in INSN was for a pseudo register, the matching
1803 : insn pattern will likely match any register; combining this
1804 : with any other USE would only be safe if we knew that the
1805 : used registers have identical values, or if there was
1806 : something to tell them apart, e.g. different modes. For
1807 : now, we forgo such complicated tests and simply disallow
1808 : combining of USES of pseudo registers with any other USE. */
1809 137484 : if (REG_P (XEXP (elt, 0))
1810 137484 : && GET_CODE (PATTERN (i3)) == PARALLEL)
1811 : {
1812 247 : rtx i3pat = PATTERN (i3);
1813 247 : int i = XVECLEN (i3pat, 0) - 1;
1814 247 : unsigned int regno = REGNO (XEXP (elt, 0));
1815 :
1816 505 : do
1817 : {
1818 505 : rtx i3elt = XVECEXP (i3pat, 0, i);
1819 :
1820 505 : if (GET_CODE (i3elt) == USE
1821 225 : && REG_P (XEXP (i3elt, 0))
1822 757 : && (REGNO (XEXP (i3elt, 0)) == regno
1823 198 : ? reg_set_between_p (XEXP (elt, 0),
1824 27 : PREV_INSN (insn), i3)
1825 : : regno >= FIRST_PSEUDO_REGISTER))
1826 : return false;
1827 : }
1828 307 : while (--i >= 0);
1829 : }
1830 : break;
1831 :
1832 : /* We can ignore CLOBBERs. */
1833 : case CLOBBER:
1834 : break;
1835 :
1836 16926603 : case SET:
1837 : /* Ignore SETs whose result isn't used but not those that
1838 : have side-effects. */
1839 16926603 : if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1840 194014 : && insn_nothrow_p (insn)
1841 17107526 : && !side_effects_p (elt))
1842 : break;
1843 :
1844 : /* If we have already found a SET, this is a second one and
1845 : so we cannot combine with this insn. */
1846 16829789 : if (set)
1847 : return false;
1848 :
1849 : set = elt;
1850 : break;
1851 :
1852 : default:
1853 : /* Anything else means we can't combine. */
1854 : return false;
1855 : }
1856 : }
1857 :
1858 15817577 : if (set == 0
1859 : /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1860 : so don't do anything with it. */
1861 15817577 : || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1862 : return false;
1863 : }
1864 : else
1865 : return false;
1866 :
1867 : if (set == 0)
1868 : return false;
1869 :
1870 : /* The simplification in expand_field_assignment may call back to
1871 : get_last_value, so set safe guard here. */
1872 61669689 : subst_low_luid = DF_INSN_LUID (insn);
1873 :
1874 61669689 : set = expand_field_assignment (set);
1875 61669689 : src = SET_SRC (set), dest = SET_DEST (set);
1876 :
1877 : /* Do not eliminate user-specified register if it is in an
1878 : asm input because we may break the register asm usage defined
1879 : in GCC manual if allow to do so.
1880 : Be aware that this may cover more cases than we expect but this
1881 : should be harmless. */
1882 61109734 : if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1883 61669692 : && extract_asm_operands (PATTERN (i3)))
1884 : return false;
1885 :
1886 : /* Don't eliminate a store in the stack pointer. */
1887 61669689 : if (dest == stack_pointer_rtx
1888 : /* Don't combine with an insn that sets a register to itself if it has
1889 : a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1890 59767907 : || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1891 : /* Can't merge an ASM_OPERANDS. */
1892 59767907 : || GET_CODE (src) == ASM_OPERANDS
1893 : /* Can't merge a function call. */
1894 59764291 : || GET_CODE (src) == CALL
1895 : /* Don't eliminate a function call argument. */
1896 59764291 : || (CALL_P (i3)
1897 8908969 : && (find_reg_fusage (i3, USE, dest)
1898 168089 : || (REG_P (dest)
1899 168089 : && REGNO (dest) < FIRST_PSEUDO_REGISTER
1900 283 : && global_regs[REGNO (dest)])))
1901 : /* Don't substitute into an incremented register. */
1902 : || FIND_REG_INC_NOTE (i3, dest)
1903 : || (succ && FIND_REG_INC_NOTE (succ, dest))
1904 59764291 : || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1905 : /* Don't substitute into a non-local goto, this confuses CFG. */
1906 51023408 : || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1907 : /* Make sure that DEST is not used after INSN but before SUCC, or
1908 : after SUCC and before SUCC2, or after SUCC2 but before I3. */
1909 51022687 : || (!all_adjacent
1910 12600497 : && ((succ2
1911 970946 : && (reg_used_between_p (dest, succ2, i3)
1912 948850 : || reg_used_between_p (dest, succ, succ2)))
1913 12532165 : || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1914 12251950 : || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1915 12251950 : || (succ
1916 : /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1917 : that case SUCC is not in the insn stream, so use SUCC2
1918 : instead for this test. */
1919 10114836 : && reg_used_between_p (dest, insn,
1920 : succ2
1921 902614 : && INSN_UID (succ) == INSN_UID (succ2)
1922 : ? succ2 : succ))))
1923 : /* Make sure that the value that is to be substituted for the register
1924 : does not use any registers whose values alter in between. However,
1925 : If the insns are adjacent, a use can't cross a set even though we
1926 : think it might (this can happen for a sequence of insns each setting
1927 : the same destination; last_set of that register might point to
1928 : a NOTE). If INSN has a REG_EQUIV note, the register is always
1929 : equivalent to the memory so the substitution is valid even if there
1930 : are intervening stores. Also, don't move a volatile asm or
1931 : UNSPEC_VOLATILE across any other insns. */
1932 : || (! all_adjacent
1933 12251950 : && (((!MEM_P (src)
1934 3445175 : || ! find_reg_note (insn, REG_EQUIV, src))
1935 12136421 : && modified_between_p (src, insn, i3))
1936 11082990 : || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1937 11082990 : || GET_CODE (src) == UNSPEC_VOLATILE))
1938 : /* Don't combine across a CALL_INSN, because that would possibly
1939 : change whether the life span of some REGs crosses calls or not,
1940 : and it is a pain to update that information.
1941 : Exception: if source is a constant, moving it later can't hurt.
1942 : Accept that as a special case. */
1943 111164405 : || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1944 : return false;
1945 :
1946 : /* DEST must be a REG. */
1947 49193751 : if (REG_P (dest))
1948 : {
1949 : /* If register alignment is being enforced for multi-word items in all
1950 : cases except for parameters, it is possible to have a register copy
1951 : insn referencing a hard register that is not allowed to contain the
1952 : mode being copied and which would not be valid as an operand of most
1953 : insns. Eliminate this problem by not combining with such an insn.
1954 :
1955 : Also, on some machines we don't want to extend the life of a hard
1956 : register. */
1957 :
1958 48638754 : if (REG_P (src)
1959 48638754 : && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1960 29518 : && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1961 : /* Don't extend the life of a hard register unless it is
1962 : user variable (if we have few registers) or it can't
1963 : fit into the desired register (meaning something special
1964 : is going on).
1965 : Also avoid substituting a return register into I3, because
1966 : reload can't handle a conflict with constraints of other
1967 : inputs. */
1968 2572762 : || (REGNO (src) < FIRST_PSEUDO_REGISTER
1969 37478 : && !targetm.hard_regno_mode_ok (REGNO (src),
1970 37478 : GET_MODE (src)))))
1971 : return false;
1972 : }
1973 : else
1974 : return false;
1975 :
1976 :
1977 48638754 : if (GET_CODE (PATTERN (i3)) == PARALLEL)
1978 36559685 : for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1979 24651452 : if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1980 : {
1981 11578640 : rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1982 :
1983 : /* If the clobber represents an earlyclobber operand, we must not
1984 : substitute an expression containing the clobbered register.
1985 : As we do not analyze the constraint strings here, we have to
1986 : make the conservative assumption. However, if the register is
1987 : a fixed hard reg, the clobber cannot represent any operand;
1988 : we leave it up to the machine description to either accept or
1989 : reject use-and-clobber patterns. */
1990 11578640 : if (!REG_P (reg)
1991 11211937 : || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1992 22741675 : || !fixed_regs[REGNO (reg)])
1993 453345 : if (reg_overlap_mentioned_p (reg, src))
1994 : return false;
1995 : }
1996 :
1997 : /* If INSN contains anything volatile, or is an `asm' (whether volatile
1998 : or not), reject, unless nothing volatile comes between it and I3 */
1999 :
2000 48638099 : if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2001 : {
2002 : /* Make sure neither succ nor succ2 contains a volatile reference. */
2003 698964 : if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2004 : return false;
2005 698871 : if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2006 : return false;
2007 : /* We'll check insns between INSN and I3 below. */
2008 : }
2009 :
2010 : /* If INSN is an asm, and DEST is a hard register, reject, since it has
2011 : to be an explicit register variable, and was chosen for a reason. */
2012 :
2013 48601950 : if (GET_CODE (src) == ASM_OPERANDS
2014 48601950 : && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2015 : return false;
2016 :
2017 : /* If INSN contains volatile references (specifically volatile MEMs),
2018 : we cannot combine across any other volatile references.
2019 : Even if INSN doesn't contain volatile references, any intervening
2020 : volatile insn might affect machine state. */
2021 :
2022 96540217 : is_volatile_p = volatile_refs_p (PATTERN (insn))
2023 48601950 : ? volatile_refs_p
2024 : : volatile_insn_p;
2025 :
2026 221519484 : for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2027 124520933 : if (NONDEBUG_INSN_P (p)
2028 60823607 : && p != succ
2029 60823607 : && p != succ2
2030 170485548 : && is_volatile_p (PATTERN (p)))
2031 : return false;
2032 :
2033 : /* If INSN contains an autoincrement or autodecrement, make sure that
2034 : register is not used between there and I3, and not already used in
2035 : I3 either. Neither must it be used in PRED or SUCC, if they exist.
2036 : Also insist that I3 not be a jump if using LRA; if it were one
2037 : and the incremented register were spilled, we would lose.
2038 : Reload handles this correctly. */
2039 :
2040 48396601 : if (AUTO_INC_DEC)
2041 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2042 : if (REG_NOTE_KIND (link) == REG_INC
2043 : && ((JUMP_P (i3) && targetm.lra_p ())
2044 : || reg_used_between_p (XEXP (link, 0), insn, i3)
2045 : || (pred != NULL_RTX
2046 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2047 : || (pred2 != NULL_RTX
2048 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2049 : || (succ != NULL_RTX
2050 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2051 : || (succ2 != NULL_RTX
2052 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2053 : || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2054 : return false;
2055 :
2056 : /* If we get here, we have passed all the tests and the combination is
2057 : to be allowed. */
2058 :
2059 48396601 : *pdest = dest;
2060 48396601 : *psrc = src;
2061 :
2062 48396601 : return true;
2063 : }
2064 :
2065 : /* LOC is the location within I3 that contains its pattern or the component
2066 : of a PARALLEL of the pattern. We validate that it is valid for combining.
2067 :
2068 : One problem is if I3 modifies its output, as opposed to replacing it
2069 : entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2070 : doing so would produce an insn that is not equivalent to the original insns.
2071 :
2072 : Consider:
2073 :
2074 : (set (reg:DI 101) (reg:DI 100))
2075 : (set (subreg:SI (reg:DI 101) 0) <foo>)
2076 :
2077 : This is NOT equivalent to:
2078 :
2079 : (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2080 : (set (reg:DI 101) (reg:DI 100))])
2081 :
2082 : Not only does this modify 100 (in which case it might still be valid
2083 : if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2084 :
2085 : We can also run into a problem if I2 sets a register that I1
2086 : uses and I1 gets directly substituted into I3 (not via I2). In that
2087 : case, we would be getting the wrong value of I2DEST into I3, so we
2088 : must reject the combination. This case occurs when I2 and I1 both
2089 : feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2090 : If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2091 : of a SET must prevent combination from occurring. The same situation
2092 : can occur for I0, in which case I0_NOT_IN_SRC is set.
2093 :
2094 : Before doing the above check, we first try to expand a field assignment
2095 : into a set of logical operations.
2096 :
2097 : If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2098 : we place a register that is both set and used within I3. If more than one
2099 : such register is detected, we fail.
2100 :
2101 : Return true if the combination is valid, false otherwise. */
2102 :
2103 : static bool
2104 69444032 : combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2105 : bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2106 : {
2107 69444032 : rtx x = *loc;
2108 :
2109 69444032 : if (GET_CODE (x) == SET)
2110 : {
2111 46877497 : rtx set = x ;
2112 46877497 : rtx dest = SET_DEST (set);
2113 46877497 : rtx src = SET_SRC (set);
2114 46877497 : rtx inner_dest = dest;
2115 46877497 : rtx subdest;
2116 :
2117 46877497 : while (GET_CODE (inner_dest) == STRICT_LOW_PART
2118 47391604 : || GET_CODE (inner_dest) == SUBREG
2119 47391604 : || GET_CODE (inner_dest) == ZERO_EXTRACT)
2120 514107 : inner_dest = XEXP (inner_dest, 0);
2121 :
2122 : /* Check for the case where I3 modifies its output, as discussed
2123 : above. We don't want to prevent pseudos from being combined
2124 : into the address of a MEM, so only prevent the combination if
2125 : i1 or i2 set the same MEM. */
2126 493479 : if ((inner_dest != dest &&
2127 : (!MEM_P (inner_dest)
2128 783 : || rtx_equal_p (i2dest, inner_dest)
2129 783 : || (i1dest && rtx_equal_p (i1dest, inner_dest))
2130 783 : || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2131 492696 : && (reg_overlap_mentioned_p (i2dest, inner_dest)
2132 363306 : || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2133 362011 : || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2134 :
2135 : /* This is the same test done in can_combine_p except we can't test
2136 : all_adjacent; we don't have to, since this instruction will stay
2137 : in place, thus we are not considering increasing the lifetime of
2138 : INNER_DEST.
2139 :
2140 : Also, if this insn sets a function argument, combining it with
2141 : something that might need a spill could clobber a previous
2142 : function argument; the all_adjacent test in can_combine_p also
2143 : checks this; here, we do a more specific test for this case. */
2144 :
2145 46746720 : || (REG_P (inner_dest)
2146 30119089 : && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2147 7458561 : && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2148 7458561 : GET_MODE (inner_dest)))
2149 46746466 : || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2150 93617089 : || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2151 : return false;
2152 :
2153 : /* If DEST is used in I3, it is being killed in this insn, so
2154 : record that for later. We have to consider paradoxical
2155 : subregs here, since they kill the whole register, but we
2156 : ignore partial subregs, STRICT_LOW_PART, etc.
2157 : Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2158 : STACK_POINTER_REGNUM, since these are always considered to be
2159 : live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2160 46708872 : subdest = dest;
2161 46708872 : if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2162 252394 : subdest = SUBREG_REG (subdest);
2163 46708872 : if (pi3dest_killed
2164 33910111 : && REG_P (subdest)
2165 21562120 : && reg_referenced_p (subdest, PATTERN (i3))
2166 1245029 : && REGNO (subdest) != FRAME_POINTER_REGNUM
2167 1245029 : && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2168 1245029 : || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2169 1245029 : && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2170 1245029 : || (REGNO (subdest) != ARG_POINTER_REGNUM
2171 0 : || ! fixed_regs [REGNO (subdest)]))
2172 47953901 : && REGNO (subdest) != STACK_POINTER_REGNUM)
2173 : {
2174 1207441 : if (*pi3dest_killed)
2175 : return false;
2176 :
2177 1184091 : *pi3dest_killed = subdest;
2178 : }
2179 : }
2180 :
2181 22566535 : else if (GET_CODE (x) == PARALLEL)
2182 : {
2183 : int i;
2184 :
2185 34349755 : for (i = 0; i < XVECLEN (x, 0); i++)
2186 23164019 : if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2187 : i1_not_in_src, i0_not_in_src, pi3dest_killed))
2188 : return false;
2189 : }
2190 :
2191 : return true;
2192 : }
2193 :
2194 : /* Return true if X is an arithmetic expression that contains a multiplication
2195 : and division. We don't count multiplications by powers of two here. */
2196 :
2197 : static bool
2198 17311151 : contains_muldiv (rtx x)
2199 : {
2200 17977488 : switch (GET_CODE (x))
2201 : {
2202 : case MOD: case DIV: case UMOD: case UDIV:
2203 : return true;
2204 :
2205 530987 : case MULT:
2206 530987 : return ! (CONST_INT_P (XEXP (x, 1))
2207 124970 : && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2208 17288217 : default:
2209 17288217 : if (BINARY_P (x))
2210 5919564 : return contains_muldiv (XEXP (x, 0))
2211 5919564 : || contains_muldiv (XEXP (x, 1));
2212 :
2213 11368653 : if (UNARY_P (x))
2214 666337 : return contains_muldiv (XEXP (x, 0));
2215 :
2216 : return false;
2217 : }
2218 : }
2219 :
2220 : /* Determine whether INSN can be used in a combination. Return true if
2221 : not. This is used in try_combine to detect early some cases where we
2222 : can't perform combinations. */
2223 :
2224 : static bool
2225 169066959 : cant_combine_insn_p (rtx_insn *insn)
2226 : {
2227 169066959 : rtx set;
2228 169066959 : rtx src, dest;
2229 :
2230 : /* If this isn't really an insn, we can't do anything.
2231 : This can occur when flow deletes an insn that it has merged into an
2232 : auto-increment address. */
2233 169066959 : if (!NONDEBUG_INSN_P (insn))
2234 : return true;
2235 :
2236 : /* Never combine loads and stores involving hard regs that are likely
2237 : to be spilled. The register allocator can usually handle such
2238 : reg-reg moves by tying. If we allow the combiner to make
2239 : substitutions of likely-spilled regs, reload might die.
2240 : As an exception, we allow combinations involving fixed regs; these are
2241 : not available to the register allocator so there's no risk involved. */
2242 :
2243 169066564 : set = single_set (insn);
2244 169066564 : if (! set)
2245 : return false;
2246 155578102 : src = SET_SRC (set);
2247 155578102 : dest = SET_DEST (set);
2248 155578102 : if (GET_CODE (src) == SUBREG)
2249 1150224 : src = SUBREG_REG (src);
2250 155578102 : if (GET_CODE (dest) == SUBREG)
2251 1727512 : dest = SUBREG_REG (dest);
2252 42201024 : if (REG_P (src) && REG_P (dest)
2253 190965679 : && ((HARD_REGISTER_P (src)
2254 6826219 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2255 : #ifdef LEAF_REGISTERS
2256 : && ! LEAF_REGISTERS [REGNO (src)])
2257 : #else
2258 : )
2259 : #endif
2260 28899500 : || (HARD_REGISTER_P (dest)
2261 20613087 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2262 20311495 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2263 25224773 : return true;
2264 :
2265 : return false;
2266 : }
2267 :
2268 : struct likely_spilled_retval_info
2269 : {
2270 : unsigned regno, nregs;
2271 : unsigned mask;
2272 : };
2273 :
2274 : /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2275 : hard registers that are known to be written to / clobbered in full. */
2276 : static void
2277 168492 : likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2278 : {
2279 168492 : struct likely_spilled_retval_info *const info =
2280 : (struct likely_spilled_retval_info *) data;
2281 168492 : unsigned regno, nregs;
2282 168492 : unsigned new_mask;
2283 :
2284 168492 : if (!REG_P (XEXP (set, 0)))
2285 : return;
2286 168492 : regno = REGNO (x);
2287 168492 : if (regno >= info->regno + info->nregs)
2288 : return;
2289 168492 : nregs = REG_NREGS (x);
2290 168492 : if (regno + nregs <= info->regno)
2291 : return;
2292 168492 : new_mask = (2U << (nregs - 1)) - 1;
2293 168492 : if (regno < info->regno)
2294 0 : new_mask >>= info->regno - regno;
2295 : else
2296 168492 : new_mask <<= regno - info->regno;
2297 168492 : info->mask &= ~new_mask;
2298 : }
2299 :
2300 : /* Return true iff part of the return value is live during INSN, and
2301 : it is likely spilled. This can happen when more than one insn is needed
2302 : to copy the return value, e.g. when we consider to combine into the
2303 : second copy insn for a complex value. */
2304 :
2305 : static bool
2306 47862575 : likely_spilled_retval_p (rtx_insn *insn)
2307 : {
2308 47862575 : rtx_insn *use = BB_END (this_basic_block);
2309 47862575 : rtx reg;
2310 47862575 : rtx_insn *p;
2311 47862575 : unsigned regno, nregs;
2312 : /* We assume here that no machine mode needs more than
2313 : 32 hard registers when the value overlaps with a register
2314 : for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2315 47862575 : unsigned mask;
2316 47862575 : struct likely_spilled_retval_info info;
2317 :
2318 47862575 : if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2319 : return false;
2320 3212089 : reg = XEXP (PATTERN (use), 0);
2321 3212089 : if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2322 : return false;
2323 3212089 : regno = REGNO (reg);
2324 3212089 : nregs = REG_NREGS (reg);
2325 3212089 : if (nregs == 1)
2326 : return false;
2327 165874 : mask = (2U << (nregs - 1)) - 1;
2328 :
2329 : /* Disregard parts of the return value that are set later. */
2330 165874 : info.regno = regno;
2331 165874 : info.nregs = nregs;
2332 165874 : info.mask = mask;
2333 563860 : for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2334 232112 : if (INSN_P (p))
2335 232112 : note_stores (p, likely_spilled_retval_1, &info);
2336 331712 : mask = info.mask;
2337 :
2338 : /* Check if any of the (probably) live return value registers is
2339 : likely spilled. */
2340 : nregs --;
2341 331712 : do
2342 : {
2343 331712 : if ((mask & 1 << nregs)
2344 331712 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2345 : return true;
2346 331666 : } while (nregs--);
2347 : return false;
2348 : }
2349 :
2350 : /* Adjust INSN after we made a change to its destination.
2351 :
2352 : Changing the destination can invalidate notes that say something about
2353 : the results of the insn and a LOG_LINK pointing to the insn. */
2354 :
2355 : static void
2356 17396 : adjust_for_new_dest (rtx_insn *insn)
2357 : {
2358 : /* For notes, be conservative and simply remove them. */
2359 17396 : remove_reg_equal_equiv_notes (insn, true);
2360 :
2361 : /* The new insn will have a destination that was previously the destination
2362 : of an insn just above it. Call distribute_links to make a LOG_LINK from
2363 : the next use of that destination. */
2364 :
2365 17396 : rtx set = single_set (insn);
2366 17396 : gcc_assert (set);
2367 :
2368 17396 : rtx reg = SET_DEST (set);
2369 :
2370 17396 : while (GET_CODE (reg) == ZERO_EXTRACT
2371 17396 : || GET_CODE (reg) == STRICT_LOW_PART
2372 34792 : || GET_CODE (reg) == SUBREG)
2373 0 : reg = XEXP (reg, 0);
2374 17396 : gcc_assert (REG_P (reg));
2375 :
2376 17396 : distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2377 :
2378 17396 : df_insn_rescan (insn);
2379 17396 : }
2380 :
2381 : /* Return TRUE if combine can reuse reg X in mode MODE.
2382 : ADDED_SETS is trueif the original set is still required. */
2383 : static bool
2384 2739529 : can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2385 : {
2386 2739529 : unsigned int regno;
2387 :
2388 2739529 : if (!REG_P (x))
2389 : return false;
2390 :
2391 : /* Don't change between modes with different underlying register sizes,
2392 : since this could lead to invalid subregs. */
2393 2739529 : if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2394 2739529 : REGMODE_NATURAL_SIZE (GET_MODE (x))))
2395 : return false;
2396 :
2397 2739529 : regno = REGNO (x);
2398 : /* Allow hard registers if the new mode is legal, and occupies no more
2399 : registers than the old mode. */
2400 2739529 : if (regno < FIRST_PSEUDO_REGISTER)
2401 1220561 : return (targetm.hard_regno_mode_ok (regno, mode)
2402 1220561 : && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2403 :
2404 : /* Or a pseudo that is only used once. */
2405 1518968 : return (regno < reg_n_sets_max
2406 1518936 : && REG_N_SETS (regno) == 1
2407 1470712 : && !added_sets
2408 2989680 : && !REG_USERVAR_P (x));
2409 : }
2410 :
2411 :
2412 : /* Check whether X, the destination of a set, refers to part of
2413 : the register specified by REG. */
2414 :
2415 : static bool
2416 17673 : reg_subword_p (rtx x, rtx reg)
2417 : {
2418 : /* Check that reg is an integer mode register. */
2419 17673 : if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2420 : return false;
2421 :
2422 17103 : if (GET_CODE (x) == STRICT_LOW_PART
2423 16674 : || GET_CODE (x) == ZERO_EXTRACT)
2424 453 : x = XEXP (x, 0);
2425 :
2426 17103 : return GET_CODE (x) == SUBREG
2427 16908 : && !paradoxical_subreg_p (x)
2428 16908 : && SUBREG_REG (x) == reg
2429 34011 : && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2430 : }
2431 :
2432 : /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2433 : by an arbitrary number of CLOBBERs. */
2434 : static bool
2435 102330676 : is_parallel_of_n_reg_sets (rtx pat, int n)
2436 : {
2437 102330676 : if (GET_CODE (pat) != PARALLEL)
2438 : return false;
2439 :
2440 27304911 : int len = XVECLEN (pat, 0);
2441 27304911 : if (len < n)
2442 : return false;
2443 :
2444 : int i;
2445 54352737 : for (i = 0; i < n; i++)
2446 51509156 : if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2447 30452957 : || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2448 : return false;
2449 3230386 : for ( ; i < len; i++)
2450 1017531 : switch (GET_CODE (XVECEXP (pat, 0, i)))
2451 : {
2452 386806 : case CLOBBER:
2453 386806 : if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2454 : return false;
2455 386805 : break;
2456 : default:
2457 : return false;
2458 : }
2459 : return true;
2460 : }
2461 :
2462 : /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2463 : CLOBBERs), can be split into individual SETs in that order, without
2464 : changing semantics. */
2465 : static bool
2466 363133 : can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2467 : {
2468 363133 : if (!insn_nothrow_p (insn))
2469 : return false;
2470 :
2471 361612 : rtx pat = PATTERN (insn);
2472 :
2473 361612 : int i, j;
2474 979590 : for (i = 0; i < n; i++)
2475 : {
2476 670601 : if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2477 : return false;
2478 :
2479 667489 : rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2480 :
2481 976478 : for (j = i + 1; j < n; j++)
2482 358500 : if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2483 : return false;
2484 : }
2485 :
2486 : return true;
2487 : }
2488 :
2489 : /* Return whether X is just a single_set, with the source
2490 : a general_operand. */
2491 : static bool
2492 67396010 : is_just_move (rtx_insn *x)
2493 : {
2494 67396010 : rtx set = single_set (x);
2495 67396010 : if (!set)
2496 : return false;
2497 :
2498 66985366 : return general_operand (SET_SRC (set), VOIDmode);
2499 : }
2500 :
2501 : /* Callback function to count autoincs. */
2502 :
2503 : static int
2504 1042760 : count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2505 : {
2506 1042760 : (*((int *) arg))++;
2507 :
2508 1042760 : return 0;
2509 : }
2510 :
2511 : /* Try to combine the insns I0, I1 and I2 into I3.
2512 : Here I0, I1 and I2 appear earlier than I3.
2513 : I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2514 : I3.
2515 :
2516 : If we are combining more than two insns and the resulting insn is not
2517 : recognized, try splitting it into two insns. If that happens, I2 and I3
2518 : are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2519 : Otherwise, I0, I1 and I2 are pseudo-deleted.
2520 :
2521 : Return 0 if the combination does not work. Then nothing is changed.
2522 : If we did the combination, return the insn at which combine should
2523 : resume scanning.
2524 :
2525 : Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2526 : new direct jump instruction.
2527 :
2528 : LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2529 : been I3 passed to an earlier try_combine within the same basic
2530 : block. */
2531 :
2532 : static rtx_insn *
2533 97318855 : try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2534 : bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2535 : {
2536 : /* New patterns for I3 and I2, respectively. */
2537 97318855 : rtx newpat, newi2pat = 0;
2538 97318855 : rtvec newpat_vec_with_clobbers = 0;
2539 97318855 : bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2540 : /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2541 : dead. */
2542 97318855 : bool added_sets_0, added_sets_1, added_sets_2;
2543 : /* Total number of SETs to put into I3. */
2544 97318855 : int total_sets;
2545 : /* Nonzero if I2's or I1's body now appears in I3. */
2546 97318855 : int i2_is_used = 0, i1_is_used = 0;
2547 : /* INSN_CODEs for new I3, new I2, and user of condition code. */
2548 97318855 : int insn_code_number, i2_code_number = 0, other_code_number = 0;
2549 : /* Contains I3 if the destination of I3 is used in its source, which means
2550 : that the old life of I3 is being killed. If that usage is placed into
2551 : I2 and not in I3, a REG_DEAD note must be made. */
2552 97318855 : rtx i3dest_killed = 0;
2553 : /* SET_DEST and SET_SRC of I2, I1 and I0. */
2554 97318855 : rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2555 : /* Copy of SET_SRC of I1 and I0, if needed. */
2556 97318855 : rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2557 : /* Set if I2DEST was reused as a scratch register. */
2558 97318855 : bool i2scratch = false;
2559 : /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2560 97318855 : rtx i0pat = 0, i1pat = 0, i2pat = 0;
2561 : /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2562 97318855 : bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2563 97318855 : bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2564 97318855 : bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2565 97318855 : bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2566 97318855 : bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2567 : /* Notes that must be added to REG_NOTES in I3 and I2. */
2568 97318855 : rtx new_i3_notes, new_i2_notes;
2569 : /* Notes that we substituted I3 into I2 instead of the normal case. */
2570 97318855 : bool i3_subst_into_i2 = false;
2571 : /* Notes that I1, I2 or I3 is a MULT operation. */
2572 97318855 : bool have_mult = false;
2573 97318855 : bool swap_i2i3 = false;
2574 97318855 : bool split_i2i3 = false;
2575 97318855 : bool changed_i3_dest = false;
2576 97318855 : bool i2_was_move = false, i3_was_move = false;
2577 97318855 : int n_auto_inc = 0;
2578 :
2579 97318855 : int maxreg;
2580 97318855 : rtx_insn *temp_insn;
2581 97318855 : rtx temp_expr;
2582 97318855 : struct insn_link *link;
2583 97318855 : rtx other_pat = 0;
2584 97318855 : rtx new_other_notes;
2585 97318855 : int i;
2586 97318855 : scalar_int_mode dest_mode, temp_mode;
2587 97318855 : bool has_non_call_exception = false;
2588 :
2589 : /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2590 : never be). */
2591 97318855 : if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2592 : return 0;
2593 :
2594 : /* Only try four-insn combinations when there's high likelihood of
2595 : success. Look for simple insns, such as loads of constants or
2596 : binary operations involving a constant. */
2597 22383443 : if (i0)
2598 : {
2599 22383443 : int i;
2600 22383443 : int ngood = 0;
2601 22383443 : int nshift = 0;
2602 22383443 : rtx set0, set3;
2603 :
2604 22383443 : if (!flag_expensive_optimizations)
2605 : return 0;
2606 :
2607 88279654 : for (i = 0; i < 4; i++)
2608 : {
2609 72222741 : rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2610 72222741 : rtx set = single_set (insn);
2611 72222741 : rtx src;
2612 72222741 : if (!set)
2613 2293671 : continue;
2614 69929070 : src = SET_SRC (set);
2615 69929070 : if (CONSTANT_P (src))
2616 : {
2617 4848385 : ngood += 2;
2618 4848385 : break;
2619 : }
2620 65080685 : else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2621 8452417 : ngood++;
2622 56628268 : else if (GET_CODE (src) == IF_THEN_ELSE)
2623 2158844 : ngood++;
2624 54469424 : else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2625 54372293 : || GET_CODE (src) == LSHIFTRT)
2626 128454 : nshift++;
2627 : }
2628 :
2629 : /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2630 : are likely manipulating its value. Ideally we'll be able to combine
2631 : all four insns into a bitfield insertion of some kind.
2632 :
2633 : Note the source in I0 might be inside a sign/zero extension and the
2634 : memory modes in I0 and I3 might be different. So extract the address
2635 : from the destination of I3 and search for it in the source of I0.
2636 :
2637 : In the event that there's a match but the source/dest do not actually
2638 : refer to the same memory, the worst that happens is we try some
2639 : combinations that we wouldn't have otherwise. */
2640 20905298 : if ((set0 = single_set (i0))
2641 : /* Ensure the source of SET0 is a MEM, possibly buried inside
2642 : an extension. */
2643 20777452 : && (GET_CODE (SET_SRC (set0)) == MEM
2644 17523504 : || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2645 17523504 : || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2646 548461 : && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2647 3365921 : && (set3 = single_set (i3))
2648 : /* Ensure the destination of SET3 is a MEM. */
2649 2919526 : && GET_CODE (SET_DEST (set3)) == MEM
2650 : /* Would it be better to extract the base address for the MEM
2651 : in SET3 and look for that? I don't have cases where it matters
2652 : but I could envision such cases. */
2653 21204054 : && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2654 21803 : ngood += 2;
2655 :
2656 20905298 : if (ngood < 2 && nshift < 2)
2657 : return 0;
2658 : }
2659 :
2660 : /* Exit early if one of the insns involved can't be used for
2661 : combinations. */
2662 82097919 : if (CALL_P (i2)
2663 77005783 : || (i1 && CALL_P (i1))
2664 73556903 : || (i0 && CALL_P (i0))
2665 73087743 : || cant_combine_insn_p (i3)
2666 69639363 : || cant_combine_insn_p (i2)
2667 53250232 : || (i1 && cant_combine_insn_p (i1))
2668 48099383 : || (i0 && cant_combine_insn_p (i0))
2669 129960494 : || likely_spilled_retval_p (i3))
2670 : return 0;
2671 :
2672 47862529 : combine_attempts++;
2673 47862529 : undobuf.other_insn = 0;
2674 :
2675 : /* Reset the hard register usage information. */
2676 47862529 : CLEAR_HARD_REG_SET (newpat_used_regs);
2677 :
2678 47862529 : if (dump_file && (dump_flags & TDF_DETAILS))
2679 : {
2680 174 : if (i0)
2681 20 : fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2682 20 : INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2683 154 : else if (i1)
2684 26 : fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2685 26 : INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2686 : else
2687 128 : fprintf (dump_file, "\nTrying %d -> %d:\n",
2688 128 : INSN_UID (i2), INSN_UID (i3));
2689 :
2690 174 : if (i0)
2691 20 : dump_insn_slim (dump_file, i0);
2692 174 : if (i1)
2693 46 : dump_insn_slim (dump_file, i1);
2694 174 : dump_insn_slim (dump_file, i2);
2695 174 : dump_insn_slim (dump_file, i3);
2696 : }
2697 :
2698 : /* If multiple insns feed into one of I2 or I3, they can be in any
2699 : order. To simplify the code below, reorder them in sequence. */
2700 47862529 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2701 : std::swap (i0, i2);
2702 47862529 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2703 : std::swap (i0, i1);
2704 47862529 : if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2705 : std::swap (i1, i2);
2706 :
2707 47862529 : added_links_insn = 0;
2708 47862529 : added_notes_insn = 0;
2709 :
2710 : /* First check for one important special case that the code below will
2711 : not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2712 : and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2713 : we may be able to replace that destination with the destination of I3.
2714 : This occurs in the common code where we compute both a quotient and
2715 : remainder into a structure, in which case we want to do the computation
2716 : directly into the structure to avoid register-register copies.
2717 :
2718 : Note that this case handles both multiple sets in I2 and also cases
2719 : where I2 has a number of CLOBBERs inside the PARALLEL.
2720 :
2721 : We make very conservative checks below and only try to handle the
2722 : most common cases of this. For example, we only handle the case
2723 : where I2 and I3 are adjacent to avoid making difficult register
2724 : usage tests. */
2725 :
2726 29884794 : if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2727 15576938 : && REG_P (SET_SRC (PATTERN (i3)))
2728 5257684 : && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2729 5015796 : && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2730 4106366 : && GET_CODE (PATTERN (i2)) == PARALLEL
2731 1100347 : && ! side_effects_p (SET_DEST (PATTERN (i3)))
2732 : /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2733 : below would need to check what is inside (and reg_overlap_mentioned_p
2734 : doesn't support those codes anyway). Don't allow those destinations;
2735 : the resulting insn isn't likely to be recognized anyway. */
2736 608044 : && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2737 608024 : && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2738 606811 : && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2739 606811 : SET_DEST (PATTERN (i3)))
2740 48469205 : && next_active_insn (i2) == i3)
2741 : {
2742 396991 : rtx p2 = PATTERN (i2);
2743 :
2744 : /* Make sure that the destination of I3,
2745 : which we are going to substitute into one output of I2,
2746 : is not used within another output of I2. We must avoid making this:
2747 : (parallel [(set (mem (reg 69)) ...)
2748 : (set (reg 69) ...)])
2749 : which is not well-defined as to order of actions.
2750 : (Besides, reload can't handle output reloads for this.)
2751 :
2752 : The problem can also happen if the dest of I3 is a memory ref,
2753 : if another dest in I2 is an indirect memory ref.
2754 :
2755 : Neither can this PARALLEL be an asm. We do not allow combining
2756 : that usually (see can_combine_p), so do not here either. */
2757 396991 : bool ok = true;
2758 1203590 : for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2759 : {
2760 806599 : if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2761 396646 : || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2762 1611780 : && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2763 805181 : SET_DEST (XVECEXP (p2, 0, i))))
2764 : ok = false;
2765 805814 : else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2766 409170 : && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2767 806599 : ok = false;
2768 : }
2769 :
2770 396991 : if (ok)
2771 517449 : for (i = 0; i < XVECLEN (p2, 0); i++)
2772 457951 : if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2773 457951 : && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2774 : {
2775 335566 : combine_merges++;
2776 :
2777 335566 : subst_insn = i3;
2778 335566 : subst_low_luid = DF_INSN_LUID (i2);
2779 :
2780 335566 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2781 335566 : i2src = SET_SRC (XVECEXP (p2, 0, i));
2782 335566 : i2dest = SET_DEST (XVECEXP (p2, 0, i));
2783 335566 : i2dest_killed = dead_or_set_p (i2, i2dest);
2784 :
2785 : /* Replace the dest in I2 with our dest and make the resulting
2786 : insn the new pattern for I3. Then skip to where we validate
2787 : the pattern. Everything was set up above. */
2788 335566 : SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2789 335566 : newpat = p2;
2790 335566 : i3_subst_into_i2 = true;
2791 335566 : goto validate_replacement;
2792 : }
2793 : }
2794 :
2795 : /* If I2 is setting a pseudo to a constant and I3 is setting some
2796 : sub-part of it to another constant, merge them by making a new
2797 : constant. */
2798 47526963 : if (i1 == 0
2799 29549228 : && (temp_expr = single_set (i2)) != 0
2800 29272729 : && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2801 19277640 : && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2802 2871978 : && GET_CODE (PATTERN (i3)) == SET
2803 1425582 : && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2804 47544636 : && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2805 : {
2806 16908 : rtx dest = SET_DEST (PATTERN (i3));
2807 16908 : rtx temp_dest = SET_DEST (temp_expr);
2808 16908 : int offset = -1;
2809 16908 : int width = 0;
2810 :
2811 16908 : if (GET_CODE (dest) == ZERO_EXTRACT)
2812 : {
2813 1 : if (CONST_INT_P (XEXP (dest, 1))
2814 1 : && CONST_INT_P (XEXP (dest, 2))
2815 2 : && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2816 : &dest_mode))
2817 : {
2818 1 : width = INTVAL (XEXP (dest, 1));
2819 1 : offset = INTVAL (XEXP (dest, 2));
2820 1 : dest = XEXP (dest, 0);
2821 1 : if (BITS_BIG_ENDIAN)
2822 : offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2823 : }
2824 : }
2825 : else
2826 : {
2827 16907 : if (GET_CODE (dest) == STRICT_LOW_PART)
2828 429 : dest = XEXP (dest, 0);
2829 16907 : if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2830 : {
2831 16907 : width = GET_MODE_PRECISION (dest_mode);
2832 16907 : offset = 0;
2833 : }
2834 : }
2835 :
2836 16908 : if (offset >= 0)
2837 : {
2838 : /* If this is the low part, we're done. */
2839 16908 : if (subreg_lowpart_p (dest))
2840 : ;
2841 : /* Handle the case where inner is twice the size of outer. */
2842 5014 : else if (GET_MODE_PRECISION (temp_mode)
2843 5014 : == 2 * GET_MODE_PRECISION (dest_mode))
2844 5011 : offset += GET_MODE_PRECISION (dest_mode);
2845 : /* Otherwise give up for now. */
2846 : else
2847 : offset = -1;
2848 : }
2849 :
2850 16905 : if (offset >= 0)
2851 : {
2852 16905 : rtx inner = SET_SRC (PATTERN (i3));
2853 16905 : rtx outer = SET_SRC (temp_expr);
2854 :
2855 33810 : wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2856 16905 : rtx_mode_t (inner, dest_mode),
2857 33810 : offset, width);
2858 :
2859 16905 : combine_merges++;
2860 16905 : subst_insn = i3;
2861 16905 : subst_low_luid = DF_INSN_LUID (i2);
2862 16905 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2863 16905 : i2dest = temp_dest;
2864 16905 : i2dest_killed = dead_or_set_p (i2, i2dest);
2865 :
2866 : /* Replace the source in I2 with the new constant and make the
2867 : resulting insn the new pattern for I3. Then skip to where we
2868 : validate the pattern. Everything was set up above. */
2869 16905 : SUBST (SET_SRC (temp_expr),
2870 : immed_wide_int_const (o, temp_mode));
2871 :
2872 16905 : newpat = PATTERN (i2);
2873 :
2874 : /* The dest of I3 has been replaced with the dest of I2. */
2875 16905 : changed_i3_dest = true;
2876 16905 : goto validate_replacement;
2877 16905 : }
2878 : }
2879 :
2880 : /* If we have no I1 and I2 looks like:
2881 : (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2882 : (set Y OP)])
2883 : make up a dummy I1 that is
2884 : (set Y OP)
2885 : and change I2 to be
2886 : (set (reg:CC X) (compare:CC Y (const_int 0)))
2887 :
2888 : (We can ignore any trailing CLOBBERs.)
2889 :
2890 : This undoes a previous combination and allows us to match a branch-and-
2891 : decrement insn. */
2892 :
2893 47510058 : if (i1 == 0
2894 29532323 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2895 233279 : && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2896 : == MODE_CC)
2897 141088 : && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2898 114538 : && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2899 76481 : && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2900 76481 : SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2901 71222 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2902 47581280 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2903 : {
2904 : /* We make I1 with the same INSN_UID as I2. This gives it
2905 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2906 : never appear in the insn stream so giving it the same INSN_UID
2907 : as I2 will not cause a problem. */
2908 :
2909 142008 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2910 71004 : XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2911 : -1, NULL_RTX);
2912 71004 : INSN_UID (i1) = INSN_UID (i2);
2913 :
2914 71004 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2915 71004 : SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2916 : SET_DEST (PATTERN (i1)));
2917 71004 : unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2918 71004 : SUBST_LINK (LOG_LINKS (i2),
2919 : alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2920 : }
2921 :
2922 : /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2923 : make those two SETs separate I1 and I2 insns, and make an I0 that is
2924 : the original I1. */
2925 47510058 : if (i0 == 0
2926 44772427 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2927 363133 : && can_split_parallel_of_n_reg_sets (i2, 2)
2928 308989 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2929 278598 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2930 262106 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2931 47772155 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2932 : {
2933 : /* If there is no I1, there is no I0 either. */
2934 262097 : i0 = i1;
2935 :
2936 : /* We make I1 with the same INSN_UID as I2. This gives it
2937 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2938 : never appear in the insn stream so giving it the same INSN_UID
2939 : as I2 will not cause a problem. */
2940 :
2941 524194 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2942 262097 : XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2943 : -1, NULL_RTX);
2944 262097 : INSN_UID (i1) = INSN_UID (i2);
2945 :
2946 262097 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2947 : }
2948 :
2949 : /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2950 47510058 : if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2951 : {
2952 12147594 : if (dump_file && (dump_flags & TDF_DETAILS))
2953 8 : fprintf (dump_file, "Can't combine i2 into i3\n");
2954 12147594 : undo_all ();
2955 12147594 : return 0;
2956 : }
2957 35362464 : if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2958 : {
2959 1415539 : if (dump_file && (dump_flags & TDF_DETAILS))
2960 0 : fprintf (dump_file, "Can't combine i1 into i3\n");
2961 1415539 : undo_all ();
2962 1415539 : return 0;
2963 : }
2964 33946925 : if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2965 : {
2966 248748 : if (dump_file && (dump_flags & TDF_DETAILS))
2967 0 : fprintf (dump_file, "Can't combine i0 into i3\n");
2968 248748 : undo_all ();
2969 248748 : return 0;
2970 : }
2971 :
2972 : /* With non-call exceptions we can end up trying to combine multiple
2973 : insns with possible EH side effects. Make sure we can combine
2974 : that to a single insn which means there must be at most one insn
2975 : in the combination with an EH side effect. */
2976 33698177 : if (cfun->can_throw_non_call_exceptions)
2977 : {
2978 6104592 : if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2979 6080936 : || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2980 6080854 : || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2981 12185445 : || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2982 : {
2983 23739 : has_non_call_exception = true;
2984 23739 : if (insn_could_throw_p (i3)
2985 23739 : + insn_could_throw_p (i2)
2986 23739 : + (i1 ? insn_could_throw_p (i1) : 0)
2987 23739 : + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2988 : {
2989 172 : if (dump_file && (dump_flags & TDF_DETAILS))
2990 0 : fprintf (dump_file, "Can't combine multiple insns with EH "
2991 : "side-effects\n");
2992 172 : undo_all ();
2993 172 : return 0;
2994 : }
2995 : }
2996 : }
2997 :
2998 : /* Record whether i2 and i3 are trivial moves. */
2999 33698005 : i2_was_move = is_just_move (i2);
3000 33698005 : i3_was_move = is_just_move (i3);
3001 :
3002 : /* Record whether I2DEST is used in I2SRC and similarly for the other
3003 : cases. Knowing this will help in register status updating below. */
3004 33698005 : i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
3005 33698005 : i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3006 10832499 : i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3007 33698005 : i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3008 1952841 : i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3009 1952841 : i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3010 33698005 : i2dest_killed = dead_or_set_p (i2, i2dest);
3011 33698005 : i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3012 33698005 : i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3013 :
3014 : /* For the earlier insns, determine which of the subsequent ones they
3015 : feed. */
3016 33698005 : i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3017 33698005 : i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3018 3408326 : i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3019 1455485 : : (!reg_overlap_mentioned_p (i1dest, i0dest)
3020 1423466 : && reg_overlap_mentioned_p (i0dest, i2src))));
3021 :
3022 : /* Ensure that I3's pattern can be the destination of combines. */
3023 44530504 : if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3024 10832499 : i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3025 1952841 : i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3026 1923998 : || (i1dest_in_i0src && !i0_feeds_i1_n)),
3027 : &i3dest_killed))
3028 : {
3029 191959 : undo_all ();
3030 191959 : return 0;
3031 : }
3032 :
3033 : /* See if any of the insns is a MULT operation. Unless one is, we will
3034 : reject a combination that is, since it must be slower. Be conservative
3035 : here. */
3036 33506046 : if (GET_CODE (i2src) == MULT
3037 32652071 : || (i1 != 0 && GET_CODE (i1src) == MULT)
3038 32308867 : || (i0 != 0 && GET_CODE (i0src) == MULT)
3039 65767797 : || (GET_CODE (PATTERN (i3)) == SET
3040 25279222 : && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3041 : have_mult = true;
3042 :
3043 : /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3044 : We used to do this EXCEPT in one case: I3 has a post-inc in an
3045 : output operand. However, that exception can give rise to insns like
3046 : mov r3,(r3)+
3047 : which is a famous insn on the PDP-11 where the value of r3 used as the
3048 : source was model-dependent. Avoid this sort of thing. */
3049 :
3050 : #if 0
3051 : if (!(GET_CODE (PATTERN (i3)) == SET
3052 : && REG_P (SET_SRC (PATTERN (i3)))
3053 : && MEM_P (SET_DEST (PATTERN (i3)))
3054 : && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3055 : || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3056 : /* It's not the exception. */
3057 : #endif
3058 33506046 : if (AUTO_INC_DEC)
3059 : {
3060 : rtx link;
3061 : for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3062 : if (REG_NOTE_KIND (link) == REG_INC
3063 : && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3064 : || (i1 != 0
3065 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3066 : {
3067 : undo_all ();
3068 : return 0;
3069 : }
3070 : }
3071 :
3072 : /* See if the SETs in I1 or I2 need to be kept around in the merged
3073 : instruction: whenever the value set there is still needed past I3.
3074 : For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3075 :
3076 : For the SET in I1, we have two cases: if I1 and I2 independently feed
3077 : into I3, the set in I1 needs to be kept around unless I1DEST dies
3078 : or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3079 : in I1 needs to be kept around unless I1DEST dies or is set in either
3080 : I2 or I3. The same considerations apply to I0. */
3081 :
3082 33506046 : added_sets_2 = !dead_or_set_p (i3, i2dest);
3083 :
3084 33506046 : if (i1)
3085 10765692 : added_sets_1 = !(dead_or_set_p (i3, i1dest)
3086 8234613 : || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3087 : else
3088 : added_sets_1 = false;
3089 :
3090 33506046 : if (i0)
3091 2826942 : added_sets_0 = !(dead_or_set_p (i3, i0dest)
3092 1742300 : || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3093 355300 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3094 844405 : && dead_or_set_p (i2, i0dest)));
3095 : else
3096 : added_sets_0 = false;
3097 :
3098 : /* We are about to copy insns for the case where they need to be kept
3099 : around. Check that they can be copied in the merged instruction. */
3100 :
3101 33506046 : if (targetm.cannot_copy_insn_p
3102 33506046 : && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3103 0 : || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3104 0 : || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3105 : {
3106 0 : undo_all ();
3107 0 : return 0;
3108 : }
3109 :
3110 : /* We cannot safely duplicate volatile references in any case. */
3111 :
3112 7503965 : if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3113 33469748 : || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3114 66947499 : || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3115 : {
3116 66850 : undo_all ();
3117 66850 : return 0;
3118 : }
3119 :
3120 : /* Count how many auto_inc expressions there were in the original insns;
3121 : we need to have the same number in the resulting patterns. */
3122 :
3123 33439196 : if (i0)
3124 1911826 : for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3125 33439196 : if (i1)
3126 10733654 : for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3127 33439196 : for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3128 33439196 : for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3129 :
3130 : /* If the set in I2 needs to be kept around, we must make a copy of
3131 : PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3132 : PATTERN (I2), we are only substituting for the original I1DEST, not into
3133 : an already-substituted copy. This also prevents making self-referential
3134 : rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3135 : I2DEST. */
3136 :
3137 33439196 : if (added_sets_2)
3138 : {
3139 7464736 : if (GET_CODE (PATTERN (i2)) == PARALLEL)
3140 2314251 : i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3141 : else
3142 5150485 : i2pat = copy_rtx (PATTERN (i2));
3143 : }
3144 :
3145 33439196 : if (added_sets_1)
3146 : {
3147 4033900 : if (GET_CODE (PATTERN (i1)) == PARALLEL)
3148 1287025 : i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3149 : else
3150 2746875 : i1pat = copy_rtx (PATTERN (i1));
3151 : }
3152 :
3153 33439196 : if (added_sets_0)
3154 : {
3155 532433 : if (GET_CODE (PATTERN (i0)) == PARALLEL)
3156 204864 : i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3157 : else
3158 327569 : i0pat = copy_rtx (PATTERN (i0));
3159 : }
3160 :
3161 33439196 : combine_merges++;
3162 :
3163 : /* Substitute in the latest insn for the regs set by the earlier ones. */
3164 :
3165 33439196 : maxreg = max_reg_num ();
3166 :
3167 33439196 : subst_insn = i3;
3168 :
3169 : /* Many machines have insns that can both perform an
3170 : arithmetic operation and set the condition code. These operations will
3171 : be represented as a PARALLEL with the first element of the vector
3172 : being a COMPARE of an arithmetic operation with the constant zero.
3173 : The second element of the vector will set some pseudo to the result
3174 : of the same arithmetic operation. If we simplify the COMPARE, we won't
3175 : match such a pattern and so will generate an extra insn. Here we test
3176 : for this case, where both the comparison and the operation result are
3177 : needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3178 : I2SRC. Later we will make the PARALLEL that contains I2. */
3179 :
3180 22705542 : if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3181 4313628 : && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3182 1824819 : && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3183 34328982 : && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3184 : {
3185 819720 : rtx newpat_dest;
3186 819720 : rtx *cc_use_loc = NULL;
3187 819720 : rtx_insn *cc_use_insn = NULL;
3188 819720 : rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3189 819720 : machine_mode compare_mode, orig_compare_mode;
3190 819720 : enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3191 819720 : scalar_int_mode mode;
3192 :
3193 819720 : newpat = PATTERN (i3);
3194 819720 : newpat_dest = SET_DEST (newpat);
3195 819720 : compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3196 :
3197 819720 : if (undobuf.other_insn == 0
3198 819720 : && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3199 : &cc_use_insn)))
3200 : {
3201 813153 : compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3202 813153 : if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3203 813153 : compare_code = simplify_compare_const (compare_code, mode,
3204 : &op0, &op1);
3205 813153 : target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3206 : }
3207 :
3208 : /* Do the rest only if op1 is const0_rtx, which may be the
3209 : result of simplification. */
3210 819720 : if (op1 == const0_rtx)
3211 : {
3212 : /* If a single use of the CC is found, prepare to modify it
3213 : when SELECT_CC_MODE returns a new CC-class mode, or when
3214 : the above simplify_compare_const() returned a new comparison
3215 : operator. undobuf.other_insn is assigned the CC use insn
3216 : when modifying it. */
3217 514121 : if (cc_use_loc)
3218 : {
3219 : #ifdef SELECT_CC_MODE
3220 511283 : machine_mode new_mode
3221 511283 : = SELECT_CC_MODE (compare_code, op0, op1);
3222 511283 : if (new_mode != orig_compare_mode
3223 511283 : && can_change_dest_mode (SET_DEST (newpat),
3224 : added_sets_2, new_mode))
3225 : {
3226 527 : unsigned int regno = REGNO (newpat_dest);
3227 527 : compare_mode = new_mode;
3228 527 : if (regno < FIRST_PSEUDO_REGISTER)
3229 527 : newpat_dest = gen_rtx_REG (compare_mode, regno);
3230 : else
3231 : {
3232 0 : subst_mode (regno, compare_mode);
3233 0 : newpat_dest = regno_reg_rtx[regno];
3234 : }
3235 : }
3236 : #endif
3237 : /* Cases for modifying the CC-using comparison. */
3238 511283 : if (compare_code != orig_compare_code
3239 549 : && COMPARISON_P (*cc_use_loc))
3240 : {
3241 : /* Replace cc_use_loc with entire new RTX. */
3242 549 : SUBST (*cc_use_loc,
3243 : gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3244 : newpat_dest, const0_rtx));
3245 549 : undobuf.other_insn = cc_use_insn;
3246 : }
3247 510734 : else if (compare_mode != orig_compare_mode)
3248 : {
3249 1 : subrtx_ptr_iterator::array_type array;
3250 :
3251 : /* Just replace the CC reg with a new mode. */
3252 4 : FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3253 : {
3254 3 : rtx *loc = *iter;
3255 3 : if (REG_P (*loc)
3256 3 : && REGNO (*loc) == REGNO (newpat_dest))
3257 : {
3258 1 : SUBST (*loc, newpat_dest);
3259 1 : iter.skip_subrtxes ();
3260 : }
3261 : }
3262 1 : undobuf.other_insn = cc_use_insn;
3263 1 : }
3264 : }
3265 :
3266 : /* Now we modify the current newpat:
3267 : First, SET_DEST(newpat) is updated if the CC mode has been
3268 : altered. For targets without SELECT_CC_MODE, this should be
3269 : optimized away. */
3270 514121 : if (compare_mode != orig_compare_mode)
3271 527 : SUBST (SET_DEST (newpat), newpat_dest);
3272 : /* This is always done to propagate i2src into newpat. */
3273 514121 : SUBST (SET_SRC (newpat),
3274 : gen_rtx_COMPARE (compare_mode, op0, op1));
3275 : /* Create new version of i2pat if needed; the below PARALLEL
3276 : creation needs this to work correctly. */
3277 514121 : if (! rtx_equal_p (i2src, op0))
3278 27 : i2pat = gen_rtx_SET (i2dest, op0);
3279 : i2_is_used = 1;
3280 : }
3281 : }
3282 :
3283 819720 : if (i2_is_used == 0)
3284 : {
3285 : /* It is possible that the source of I2 or I1 may be performing
3286 : an unneeded operation, such as a ZERO_EXTEND of something
3287 : that is known to have the high part zero. Handle that case
3288 : by letting subst look at the inner insns.
3289 :
3290 : Another way to do this would be to have a function that tries
3291 : to simplify a single insn instead of merging two or more
3292 : insns. We don't do this because of the potential of infinite
3293 : loops and because of the potential extra memory required.
3294 : However, doing it the way we are is a bit of a kludge and
3295 : doesn't catch all cases.
3296 :
3297 : But only do this if -fexpensive-optimizations since it slows
3298 : things down and doesn't usually win.
3299 :
3300 : This is not done in the COMPARE case above because the
3301 : unmodified I2PAT is used in the PARALLEL and so a pattern
3302 : with a modified I2SRC would not match. */
3303 :
3304 32925075 : if (flag_expensive_optimizations)
3305 : {
3306 : /* Pass pc_rtx so no substitutions are done, just
3307 : simplifications. */
3308 30675409 : if (i1)
3309 : {
3310 10066055 : subst_low_luid = DF_INSN_LUID (i1);
3311 10066055 : i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3312 : }
3313 :
3314 30675409 : subst_low_luid = DF_INSN_LUID (i2);
3315 30675409 : i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3316 : }
3317 :
3318 32925075 : n_occurrences = 0; /* `subst' counts here */
3319 32925075 : subst_low_luid = DF_INSN_LUID (i2);
3320 :
3321 : /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3322 : copy of I2SRC each time we substitute it, in order to avoid creating
3323 : self-referential RTL when we will be substituting I1SRC for I1DEST
3324 : later. Likewise if I0 feeds into I2, either directly or indirectly
3325 : through I1, and I0DEST is in I0SRC. */
3326 65233400 : newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3327 32925075 : (i1_feeds_i2_n && i1dest_in_i1src)
3328 31707813 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3329 : && i0dest_in_i0src));
3330 32925075 : substed_i2 = true;
3331 :
3332 : /* Record whether I2's body now appears within I3's body. */
3333 32925075 : i2_is_used = n_occurrences;
3334 : }
3335 :
3336 : /* If we already got a failure, don't try to do more. Otherwise, try to
3337 : substitute I1 if we have it. */
3338 :
3339 33439196 : if (i1 && GET_CODE (newpat) != CLOBBER)
3340 : {
3341 : /* Before we can do this substitution, we must redo the test done
3342 : above (see detailed comments there) that ensures I1DEST isn't
3343 : mentioned in any SETs in NEWPAT that are field assignments. */
3344 10689308 : if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3345 : false, false, 0))
3346 : {
3347 16 : undo_all ();
3348 16 : return 0;
3349 : }
3350 :
3351 10689292 : n_occurrences = 0;
3352 10689292 : subst_low_luid = DF_INSN_LUID (i1);
3353 :
3354 : /* If the following substitution will modify I1SRC, make a copy of it
3355 : for the case where it is substituted for I1DEST in I2PAT later. */
3356 10689292 : if (added_sets_2 && i1_feeds_i2_n)
3357 1509006 : i1src_copy = copy_rtx (i1src);
3358 :
3359 : /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3360 : copy of I1SRC each time we substitute it, in order to avoid creating
3361 : self-referential RTL when we will be substituting I0SRC for I0DEST
3362 : later. */
3363 10689292 : newpat = subst (newpat, i1dest, i1src, false, false,
3364 : i0_feeds_i1_n && i0dest_in_i0src);
3365 10689292 : substed_i1 = true;
3366 :
3367 : /* Record whether I1's body now appears within I3's body. */
3368 10689292 : i1_is_used = n_occurrences;
3369 : }
3370 :
3371 : /* Likewise for I0 if we have it. */
3372 :
3373 33439180 : if (i0 && GET_CODE (newpat) != CLOBBER)
3374 : {
3375 1892700 : if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3376 : false, false, 0))
3377 : {
3378 0 : undo_all ();
3379 0 : return 0;
3380 : }
3381 :
3382 : /* If the following substitution will modify I0SRC, make a copy of it
3383 : for the case where it is substituted for I0DEST in I1PAT later. */
3384 1892700 : if (added_sets_1 && i0_feeds_i1_n)
3385 368959 : i0src_copy = copy_rtx (i0src);
3386 : /* And a copy for I0DEST in I2PAT substitution. */
3387 1892700 : if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3388 209864 : || (i0_feeds_i2_n)))
3389 343940 : i0src_copy2 = copy_rtx (i0src);
3390 :
3391 1892700 : n_occurrences = 0;
3392 1892700 : subst_low_luid = DF_INSN_LUID (i0);
3393 1892700 : newpat = subst (newpat, i0dest, i0src, false, false, false);
3394 1892700 : substed_i0 = true;
3395 : }
3396 :
3397 33439180 : if (n_auto_inc)
3398 : {
3399 521920 : int new_n_auto_inc = 0;
3400 521920 : for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3401 :
3402 521920 : if (n_auto_inc != new_n_auto_inc)
3403 : {
3404 1082 : if (dump_file && (dump_flags & TDF_DETAILS))
3405 0 : fprintf (dump_file, "Number of auto_inc expressions changed\n");
3406 1082 : undo_all ();
3407 1082 : return 0;
3408 : }
3409 : }
3410 :
3411 : /* Fail if an autoincrement side-effect has been duplicated. Be careful
3412 : to count all the ways that I2SRC and I1SRC can be used. */
3413 33438098 : if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3414 : && i2_is_used + added_sets_2 > 1)
3415 : || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3416 : && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3417 : || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3418 : && (n_occurrences + added_sets_0
3419 : + (added_sets_1 && i0_feeds_i1_n)
3420 : + (added_sets_2 && i0_feeds_i2_n) > 1))
3421 : /* Fail if we tried to make a new register. */
3422 33438098 : || max_reg_num () != maxreg
3423 : /* Fail if we couldn't do something and have a CLOBBER. */
3424 33438098 : || GET_CODE (newpat) == CLOBBER
3425 : /* Fail if this new pattern is a MULT and we didn't have one before
3426 : at the outer level. */
3427 66518000 : || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3428 310537 : && ! have_mult))
3429 : {
3430 389743 : undo_all ();
3431 389743 : return 0;
3432 : }
3433 :
3434 : /* If the actions of the earlier insns must be kept
3435 : in addition to substituting them into the latest one,
3436 : we must make a new PARALLEL for the latest insn
3437 : to hold additional the SETs. */
3438 :
3439 33048355 : if (added_sets_0 || added_sets_1 || added_sets_2)
3440 : {
3441 10956871 : int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3442 10956871 : combine_extras++;
3443 :
3444 10956871 : if (GET_CODE (newpat) == PARALLEL)
3445 : {
3446 2181021 : rtvec old = XVEC (newpat, 0);
3447 2181021 : total_sets = XVECLEN (newpat, 0) + extra_sets;
3448 2181021 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3449 2181021 : memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3450 2181021 : sizeof (old->elem[0]) * old->num_elem);
3451 : }
3452 : else
3453 : {
3454 8775850 : rtx old = newpat;
3455 8775850 : total_sets = 1 + extra_sets;
3456 8775850 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3457 8775850 : XVECEXP (newpat, 0, 0) = old;
3458 : }
3459 :
3460 10956871 : if (added_sets_0)
3461 513082 : XVECEXP (newpat, 0, --total_sets) = i0pat;
3462 :
3463 10956871 : if (added_sets_1)
3464 : {
3465 3981721 : rtx t = i1pat;
3466 3981721 : if (i0_feeds_i1_n)
3467 365313 : t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3468 : false, false, false);
3469 :
3470 3981721 : XVECEXP (newpat, 0, --total_sets) = t;
3471 : }
3472 10956871 : if (added_sets_2)
3473 : {
3474 7386207 : rtx t = i2pat;
3475 7386207 : if (i1_feeds_i2_n)
3476 1490141 : t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3477 : i0_feeds_i1_n && i0dest_in_i0src);
3478 7386207 : if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3479 339448 : t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3480 : false, false, false);
3481 :
3482 7386207 : XVECEXP (newpat, 0, --total_sets) = t;
3483 : }
3484 : }
3485 :
3486 25662148 : validate_replacement:
3487 :
3488 : /* Note which hard regs this insn has as inputs. */
3489 33400826 : mark_used_regs_combine (newpat);
3490 :
3491 : /* If recog_for_combine fails, it strips existing clobbers. If we'll
3492 : consider splitting this pattern, we might need these clobbers. */
3493 33400826 : if (i1 && GET_CODE (newpat) == PARALLEL
3494 7385684 : && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3495 : {
3496 1737562 : int len = XVECLEN (newpat, 0);
3497 :
3498 1737562 : newpat_vec_with_clobbers = rtvec_alloc (len);
3499 7001041 : for (i = 0; i < len; i++)
3500 3525917 : RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3501 : }
3502 :
3503 : /* We have recognized nothing yet. */
3504 33400826 : insn_code_number = -1;
3505 :
3506 : /* See if this is a PARALLEL of two SETs where one SET's destination is
3507 : a register that is unused and this isn't marked as an instruction that
3508 : might trap in an EH region. In that case, we just need the other SET.
3509 : We prefer this over the PARALLEL.
3510 :
3511 : This can occur when simplifying a divmod insn. We *must* test for this
3512 : case here because the code below that splits two independent SETs doesn't
3513 : handle this case correctly when it updates the register status.
3514 :
3515 : It's pointless doing this if we originally had two sets, one from
3516 : i3, and one from i2. Combining then splitting the parallel results
3517 : in the original i2 again plus an invalid insn (which we delete).
3518 : The net effect is only to move instructions around, which makes
3519 : debug info less accurate.
3520 :
3521 : If the remaining SET came from I2 its destination should not be used
3522 : between I2 and I3. See PR82024. */
3523 :
3524 7386207 : if (!(added_sets_2 && i1 == 0)
3525 28025926 : && is_parallel_of_n_reg_sets (newpat, 2)
3526 35017269 : && asm_noperands (newpat) < 0)
3527 : {
3528 1615549 : rtx set0 = XVECEXP (newpat, 0, 0);
3529 1615549 : rtx set1 = XVECEXP (newpat, 0, 1);
3530 1615549 : rtx oldpat = newpat;
3531 :
3532 1615549 : if (((REG_P (SET_DEST (set1))
3533 1615549 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3534 1574151 : || (GET_CODE (SET_DEST (set1)) == SUBREG
3535 0 : && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3536 41398 : && insn_nothrow_p (i3)
3537 1655718 : && !side_effects_p (SET_SRC (set1)))
3538 : {
3539 39902 : newpat = set0;
3540 39902 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3541 : }
3542 :
3543 1575647 : else if (((REG_P (SET_DEST (set0))
3544 1575647 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3545 1550447 : || (GET_CODE (SET_DEST (set0)) == SUBREG
3546 0 : && find_reg_note (i3, REG_UNUSED,
3547 0 : SUBREG_REG (SET_DEST (set0)))))
3548 25200 : && insn_nothrow_p (i3)
3549 1600243 : && !side_effects_p (SET_SRC (set0)))
3550 : {
3551 24553 : rtx dest = SET_DEST (set1);
3552 24553 : if (GET_CODE (dest) == SUBREG)
3553 0 : dest = SUBREG_REG (dest);
3554 24553 : if (!reg_used_between_p (dest, i2, i3))
3555 : {
3556 24552 : newpat = set1;
3557 24552 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3558 :
3559 24552 : if (insn_code_number >= 0)
3560 : changed_i3_dest = true;
3561 : }
3562 : }
3563 :
3564 39902 : if (insn_code_number < 0)
3565 1609954 : newpat = oldpat;
3566 : }
3567 :
3568 : /* Is the result of combination a valid instruction? */
3569 1609954 : if (insn_code_number < 0)
3570 33395231 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3571 :
3572 : /* If we were combining three insns and the result is a simple SET
3573 : with no ASM_OPERANDS that wasn't recognized, try to split it into two
3574 : insns. There are two ways to do this. It can be split using a
3575 : machine-specific method (like when you have an addition of a large
3576 : constant) or by combine in the function find_split_point. */
3577 :
3578 10528692 : if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3579 38193476 : && asm_noperands (newpat) < 0)
3580 : {
3581 4792125 : rtx parallel, *split;
3582 4792125 : rtx_insn *m_split_insn;
3583 4792125 : unsigned int old_nregs, new_nregs;
3584 :
3585 : /* See if the MD file can split NEWPAT. If it can't, see if letting it
3586 : use I2DEST as a scratch register will help. In the latter case,
3587 : convert I2DEST to the mode of the source of NEWPAT if we can. */
3588 :
3589 4792125 : m_split_insn = combine_split_insns (newpat, i3, &old_nregs, &new_nregs);
3590 :
3591 : /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3592 : inputs of NEWPAT. */
3593 :
3594 : /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3595 : possible to try that as a scratch reg. This would require adding
3596 : more code to make it work though. */
3597 :
3598 4792125 : if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3599 : {
3600 4651805 : machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3601 :
3602 : /* ??? Reusing i2dest without resetting the reg_stat entry for it
3603 : (temporarily, until we are committed to this instruction
3604 : combination) does not work: for example, any call to nonzero_bits
3605 : on the register (from a splitter in the MD file, for example)
3606 : will get the old information, which is invalid.
3607 :
3608 : Since nowadays we can create registers during combine just fine,
3609 : we should just create a new one here, not reuse i2dest. */
3610 :
3611 : /* First try to split using the original register as a
3612 : scratch register. */
3613 4651805 : parallel = gen_rtx_PARALLEL (VOIDmode,
3614 : gen_rtvec (2, newpat,
3615 : gen_rtx_CLOBBER (VOIDmode,
3616 : i2dest)));
3617 4651805 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3618 :
3619 : /* If that didn't work, try changing the mode of I2DEST if
3620 : we can. */
3621 4651805 : if (m_split_insn == 0
3622 4651805 : && new_mode != GET_MODE (i2dest)
3623 1797653 : && new_mode != VOIDmode
3624 5863649 : && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3625 : {
3626 897687 : machine_mode old_mode = GET_MODE (i2dest);
3627 897687 : rtx ni2dest;
3628 :
3629 897687 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3630 8700 : ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3631 : else
3632 : {
3633 888987 : subst_mode (REGNO (i2dest), new_mode);
3634 888987 : ni2dest = regno_reg_rtx[REGNO (i2dest)];
3635 : }
3636 :
3637 897687 : parallel = (gen_rtx_PARALLEL
3638 : (VOIDmode,
3639 : gen_rtvec (2, newpat,
3640 : gen_rtx_CLOBBER (VOIDmode,
3641 : ni2dest))));
3642 897687 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3643 :
3644 897687 : if (m_split_insn == 0
3645 897687 : && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3646 : {
3647 888987 : struct undo *buf;
3648 :
3649 888987 : adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3650 888987 : buf = undobuf.undos;
3651 888987 : undobuf.undos = buf->next;
3652 888987 : buf->next = undobuf.frees;
3653 888987 : undobuf.frees = buf;
3654 : }
3655 : }
3656 :
3657 4651805 : i2scratch = m_split_insn != 0;
3658 : }
3659 :
3660 : /* If recog_for_combine has discarded clobbers, try to use them
3661 : again for the split. */
3662 4792125 : if (m_split_insn == 0 && newpat_vec_with_clobbers)
3663 : {
3664 1685967 : parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3665 1685967 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3666 : }
3667 :
3668 4803821 : if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3669 : {
3670 1632 : rtx m_split_pat = PATTERN (m_split_insn);
3671 1632 : insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes,
3672 : old_nregs, new_nregs);
3673 1632 : if (insn_code_number >= 0)
3674 245 : newpat = m_split_pat;
3675 : }
3676 10064 : else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3677 4800557 : && (next_nonnote_nondebug_insn (i2) == i3
3678 6 : || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3679 : {
3680 10064 : rtx i2set, i3set;
3681 10064 : rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3682 10064 : newi2pat = PATTERN (m_split_insn);
3683 :
3684 10064 : i3set = single_set (NEXT_INSN (m_split_insn));
3685 10064 : i2set = single_set (m_split_insn);
3686 :
3687 10064 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3688 :
3689 : /* If I2 or I3 has multiple SETs, we won't know how to track
3690 : register status, so don't use these insns. If I2's destination
3691 : is used between I2 and I3, we also can't use these insns. */
3692 :
3693 10064 : if (i2_code_number >= 0 && i2set && i3set
3694 20128 : && (next_nonnote_nondebug_insn (i2) == i3
3695 6 : || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3696 10064 : insn_code_number = recog_for_combine (&newi3pat, i3,
3697 : &new_i3_notes,
3698 : old_nregs, new_nregs);
3699 10064 : if (insn_code_number >= 0)
3700 10064 : newpat = newi3pat;
3701 :
3702 : /* It is possible that both insns now set the destination of I3.
3703 : If so, we must show an extra use of it. */
3704 :
3705 10064 : if (insn_code_number >= 0)
3706 : {
3707 10064 : rtx new_i3_dest = SET_DEST (i3set);
3708 10064 : rtx new_i2_dest = SET_DEST (i2set);
3709 :
3710 10064 : while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3711 10104 : || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3712 20190 : || GET_CODE (new_i3_dest) == SUBREG)
3713 40 : new_i3_dest = XEXP (new_i3_dest, 0);
3714 :
3715 10064 : while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3716 10064 : || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3717 20128 : || GET_CODE (new_i2_dest) == SUBREG)
3718 0 : new_i2_dest = XEXP (new_i2_dest, 0);
3719 :
3720 10064 : if (REG_P (new_i3_dest)
3721 5755 : && REG_P (new_i2_dest)
3722 5755 : && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3723 10064 : && REGNO (new_i2_dest) < reg_n_sets_max)
3724 0 : INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3725 : }
3726 : }
3727 :
3728 : /* If we can split it and use I2DEST, go ahead and see if that
3729 : helps things be recognized. Verify that none of the registers
3730 : are set between I2 and I3. */
3731 1387 : if (insn_code_number < 0
3732 4781816 : && (split = find_split_point (&newpat, i3, false)) != 0
3733 : /* We need I2DEST in the proper mode. If it is a hard register
3734 : or the only use of a pseudo, we can change its mode.
3735 : Make sure we don't change a hard register to have a mode that
3736 : isn't valid for it, or change the number of registers. */
3737 4513771 : && (GET_MODE (*split) == GET_MODE (i2dest)
3738 1690853 : || GET_MODE (*split) == VOIDmode
3739 1314919 : || can_change_dest_mode (i2dest, added_sets_2,
3740 : GET_MODE (*split)))
3741 3772549 : && (next_nonnote_nondebug_insn (i2) == i3
3742 598215 : || !modified_between_p (*split, i2, i3))
3743 : /* We can't overwrite I2DEST if its value is still used by
3744 : NEWPAT. */
3745 3742714 : && ! reg_referenced_p (i2dest, newpat)
3746 : /* We should not split a possibly trapping part when we
3747 : care about non-call EH and have REG_EH_REGION notes
3748 : to distribute. */
3749 8458505 : && ! (cfun->can_throw_non_call_exceptions
3750 392274 : && has_non_call_exception
3751 121 : && may_trap_p (*split)))
3752 : {
3753 3667646 : rtx newdest = i2dest;
3754 3667646 : enum rtx_code split_code = GET_CODE (*split);
3755 3667646 : machine_mode split_mode = GET_MODE (*split);
3756 3667646 : bool subst_done = false;
3757 3667646 : newi2pat = NULL_RTX;
3758 :
3759 3667646 : i2scratch = true;
3760 :
3761 : /* *SPLIT may be part of I2SRC, so make sure we have the
3762 : original expression around for later debug processing.
3763 : We should not need I2SRC any more in other cases. */
3764 3667646 : if (MAY_HAVE_DEBUG_BIND_INSNS)
3765 1803386 : i2src = copy_rtx (i2src);
3766 : else
3767 : i2src = NULL;
3768 :
3769 : /* Get NEWDEST as a register in the proper mode. We have already
3770 : validated that we can do this. */
3771 3667646 : if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3772 : {
3773 570205 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3774 0 : newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3775 : else
3776 : {
3777 570205 : subst_mode (REGNO (i2dest), split_mode);
3778 570205 : newdest = regno_reg_rtx[REGNO (i2dest)];
3779 : }
3780 : }
3781 :
3782 : /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3783 : an ASHIFT. This can occur if it was inside a PLUS and hence
3784 : appeared to be a memory address. This is a kludge. */
3785 3667646 : if (split_code == MULT
3786 201317 : && CONST_INT_P (XEXP (*split, 1))
3787 99999 : && INTVAL (XEXP (*split, 1)) > 0
3788 3763330 : && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3789 : {
3790 66420 : rtx i_rtx = gen_int_shift_amount (split_mode, i);
3791 66420 : SUBST (*split, gen_rtx_ASHIFT (split_mode,
3792 : XEXP (*split, 0), i_rtx));
3793 : /* Update split_code because we may not have a multiply
3794 : anymore. */
3795 66420 : split_code = GET_CODE (*split);
3796 : }
3797 :
3798 : /* Similarly for (plus (mult FOO (const_int pow2))). */
3799 3667646 : if (split_code == PLUS
3800 680847 : && GET_CODE (XEXP (*split, 0)) == MULT
3801 112309 : && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3802 39663 : && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3803 3703699 : && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3804 : {
3805 6786 : rtx nsplit = XEXP (*split, 0);
3806 6786 : rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3807 6786 : SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3808 : XEXP (nsplit, 0),
3809 : i_rtx));
3810 : /* Update split_code because we may not have a multiply
3811 : anymore. */
3812 6786 : split_code = GET_CODE (*split);
3813 : }
3814 :
3815 : #ifdef INSN_SCHEDULING
3816 : /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3817 : be written as a ZERO_EXTEND. */
3818 3667646 : if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3819 : {
3820 : /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3821 : what it really is. */
3822 10296 : if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3823 : == SIGN_EXTEND)
3824 : SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3825 : SUBREG_REG (*split)));
3826 : else
3827 10296 : SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3828 : SUBREG_REG (*split)));
3829 : }
3830 : #endif
3831 :
3832 : /* Attempt to split binary operators using arithmetic identities. */
3833 3667646 : if (BINARY_P (SET_SRC (newpat))
3834 3074776 : && split_mode == GET_MODE (SET_SRC (newpat))
3835 5774151 : && ! side_effects_p (SET_SRC (newpat)))
3836 : {
3837 2091949 : rtx setsrc = SET_SRC (newpat);
3838 2091949 : machine_mode mode = GET_MODE (setsrc);
3839 2091949 : enum rtx_code code = GET_CODE (setsrc);
3840 2091949 : rtx src_op0 = XEXP (setsrc, 0);
3841 2091949 : rtx src_op1 = XEXP (setsrc, 1);
3842 :
3843 : /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3844 2091949 : if (rtx_equal_p (src_op0, src_op1))
3845 : {
3846 1564 : newi2pat = gen_rtx_SET (newdest, src_op0);
3847 1564 : SUBST (XEXP (setsrc, 0), newdest);
3848 1564 : SUBST (XEXP (setsrc, 1), newdest);
3849 1564 : subst_done = true;
3850 : }
3851 : /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3852 2090385 : else if ((code == PLUS || code == MULT)
3853 1043070 : && GET_CODE (src_op0) == code
3854 409969 : && GET_CODE (XEXP (src_op0, 0)) == code
3855 172007 : && (INTEGRAL_MODE_P (mode)
3856 : || (FLOAT_MODE_P (mode)
3857 98726 : && flag_unsafe_math_optimizations)))
3858 : {
3859 77082 : rtx p = XEXP (XEXP (src_op0, 0), 0);
3860 77082 : rtx q = XEXP (XEXP (src_op0, 0), 1);
3861 77082 : rtx r = XEXP (src_op0, 1);
3862 77082 : rtx s = src_op1;
3863 :
3864 : /* Split both "((X op Y) op X) op Y" and
3865 : "((X op Y) op Y) op X" as "T op T" where T is
3866 : "X op Y". */
3867 77333 : if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3868 77250 : || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3869 : {
3870 83 : newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3871 83 : SUBST (XEXP (setsrc, 0), newdest);
3872 83 : SUBST (XEXP (setsrc, 1), newdest);
3873 83 : subst_done = true;
3874 : }
3875 : /* Split "((X op X) op Y) op Y)" as "T op T" where
3876 : T is "X op Y". */
3877 76999 : else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3878 : {
3879 41 : rtx tmp = simplify_gen_binary (code, mode, p, r);
3880 41 : newi2pat = gen_rtx_SET (newdest, tmp);
3881 41 : SUBST (XEXP (setsrc, 0), newdest);
3882 41 : SUBST (XEXP (setsrc, 1), newdest);
3883 41 : subst_done = true;
3884 : }
3885 : }
3886 : }
3887 :
3888 1688 : if (!subst_done)
3889 : {
3890 3665958 : newi2pat = gen_rtx_SET (newdest, *split);
3891 3665958 : SUBST (*split, newdest);
3892 : }
3893 :
3894 3667646 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3895 :
3896 : /* recog_for_combine might have added CLOBBERs to newi2pat.
3897 : Make sure NEWPAT does not depend on the clobbered regs. */
3898 3667646 : if (GET_CODE (newi2pat) == PARALLEL)
3899 2544880 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3900 1709273 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3901 : {
3902 873666 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3903 873666 : if (reg_overlap_mentioned_p (reg, newpat))
3904 : {
3905 23658 : undo_all ();
3906 23658 : return 0;
3907 : }
3908 : }
3909 :
3910 : /* If the split point was a MULT and we didn't have one before,
3911 : don't use one now. */
3912 3643988 : if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3913 2188154 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3914 : }
3915 : }
3916 :
3917 : /* Check for a case where we loaded from memory in a narrow mode and
3918 : then sign extended it, but we need both registers. In that case,
3919 : we have a PARALLEL with both loads from the same memory location.
3920 : We can split this into a load from memory followed by a register-register
3921 : copy. This saves at least one insn, more if register allocation can
3922 : eliminate the copy.
3923 :
3924 : We cannot do this if the involved modes have more than one elements,
3925 : like for vector or complex modes.
3926 :
3927 : We cannot do this if the destination of the first assignment is a
3928 : condition code register. We eliminate this case by making sure
3929 : the SET_DEST and SET_SRC have the same mode.
3930 :
3931 : We cannot do this if the destination of the second assignment is
3932 : a register that we have already assumed is zero-extended. Similarly
3933 : for a SUBREG of such a register. */
3934 :
3935 5736567 : else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3936 5677924 : && GET_CODE (newpat) == PARALLEL
3937 5676080 : && XVECLEN (newpat, 0) == 2
3938 4702990 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3939 4702733 : && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3940 23321 : && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3941 23321 : == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3942 23321 : && ! VECTOR_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3943 : && ! COMPLEX_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3944 21887 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3945 21887 : && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3946 21887 : XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3947 6464 : && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3948 6464 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3949 6464 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3950 6464 : && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3951 : (REG_P (temp_expr)
3952 6464 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3953 6563 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3954 : BITS_PER_WORD)
3955 6339 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3956 : HOST_BITS_PER_INT)
3957 1131 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3958 1131 : != GET_MODE_MASK (word_mode))))
3959 6446 : && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3960 0 : && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3961 0 : (REG_P (temp_expr)
3962 0 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3963 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3964 : BITS_PER_WORD)
3965 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3966 : HOST_BITS_PER_INT)
3967 0 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3968 0 : != GET_MODE_MASK (word_mode)))))
3969 6446 : && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3970 6446 : SET_SRC (XVECEXP (newpat, 0, 1)))
3971 28615091 : && ! find_reg_note (i3, REG_UNUSED,
3972 6390 : SET_DEST (XVECEXP (newpat, 0, 0))))
3973 : {
3974 6390 : rtx ni2dest;
3975 :
3976 6390 : newi2pat = XVECEXP (newpat, 0, 0);
3977 6390 : ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3978 6390 : newpat = XVECEXP (newpat, 0, 1);
3979 6390 : SUBST (SET_SRC (newpat),
3980 : gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3981 6390 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3982 :
3983 6390 : if (i2_code_number >= 0)
3984 0 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3985 :
3986 6390 : if (insn_code_number >= 0)
3987 : swap_i2i3 = 1;
3988 : }
3989 :
3990 : /* Similarly, check for a case where we have a PARALLEL of two independent
3991 : SETs but we started with three insns. In this case, we can do the sets
3992 : as two separate insns. This case occurs when some SET allows two
3993 : other insns to combine, but the destination of that SET is still live.
3994 :
3995 : Also do this if we started with two insns and (at least) one of the
3996 : resulting sets is a noop; this noop will be deleted later.
3997 :
3998 : Also do this if we started with two insns neither of which was a simple
3999 : move. */
4000 :
4001 24532849 : else if (insn_code_number < 0 && asm_noperands (newpat) < 0
4002 24514424 : && GET_CODE (newpat) == PARALLEL
4003 11162323 : && XVECLEN (newpat, 0) == 2
4004 10086327 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4005 9978531 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4006 9914910 : && (i1
4007 5241279 : || set_noop_p (XVECEXP (newpat, 0, 0))
4008 5240807 : || set_noop_p (XVECEXP (newpat, 0, 1))
4009 5240798 : || (!i2_was_move && !i3_was_move))
4010 6566628 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4011 6566001 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4012 6565859 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4013 6565293 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4014 6565279 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4015 : XVECEXP (newpat, 0, 0))
4016 5479389 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4017 5479389 : XVECEXP (newpat, 0, 1))
4018 34389092 : && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4019 438807 : && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4020 : {
4021 5097510 : rtx set0 = XVECEXP (newpat, 0, 0);
4022 5097510 : rtx set1 = XVECEXP (newpat, 0, 1);
4023 :
4024 : /* Normally, it doesn't matter which of the two is done first, but
4025 : one which uses any regs/memory set or used in between i2 and i3
4026 : can't be first. The PARALLEL might also have been pre-existing
4027 : in i3, so we need to make sure that we won't wrongly hoist a SET
4028 : to i2 that would conflict with a death note present in there, or
4029 : would have its dest modified or used between i2 and i3. */
4030 5097510 : if ((set_noop_p (set1)
4031 5097510 : || (!modified_between_p (SET_SRC (set1), i2, i3)
4032 10157206 : && !(REG_P (SET_DEST (set1))
4033 5066508 : && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4034 5114590 : && !(GET_CODE (SET_DEST (set1)) == SUBREG
4035 24190 : && find_reg_note (i2, REG_DEAD,
4036 24190 : SUBREG_REG (SET_DEST (set1))))
4037 5090400 : && !modified_between_p (SET_DEST (set1), i2, i3)
4038 5090400 : && !reg_used_between_p (SET_DEST (set1), i2, i3)))
4039 : /* If I3 is a jump, ensure that set0 is a jump so that
4040 : we do not create invalid RTL. */
4041 10187904 : && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx))
4042 : {
4043 5090394 : newi2pat = set1;
4044 5090394 : newpat = set0;
4045 : }
4046 7116 : else if ((set_noop_p (set0)
4047 7110 : || (!modified_between_p (SET_SRC (set0), i2, i3)
4048 600 : && !(REG_P (SET_DEST (set0))
4049 300 : && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4050 300 : && !(GET_CODE (SET_DEST (set0)) == SUBREG
4051 0 : && find_reg_note (i2, REG_DEAD,
4052 0 : SUBREG_REG (SET_DEST (set0))))
4053 300 : && !modified_between_p (SET_DEST (set0), i2, i3)
4054 299 : && !reg_used_between_p (SET_DEST (set0), i2, i3)))
4055 : /* If I3 is a jump, ensure that set1 is a jump so that
4056 : we do not create invalid RTL. */
4057 7415 : && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx))
4058 : {
4059 305 : newi2pat = set0;
4060 305 : newpat = set1;
4061 : }
4062 : else
4063 : {
4064 6811 : undo_all ();
4065 6811 : return 0;
4066 : }
4067 :
4068 5090699 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4069 :
4070 5090699 : if (i2_code_number >= 0)
4071 : {
4072 : /* recog_for_combine might have added CLOBBERs to newi2pat.
4073 : Make sure NEWPAT does not depend on the clobbered regs. */
4074 3741005 : if (GET_CODE (newi2pat) == PARALLEL)
4075 : {
4076 1385471 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4077 928227 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4078 : {
4079 470983 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4080 470983 : if (reg_overlap_mentioned_p (reg, newpat))
4081 : {
4082 5114 : undo_all ();
4083 5114 : return 0;
4084 : }
4085 : }
4086 : }
4087 :
4088 3735891 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4089 :
4090 : /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4091 : Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4092 : mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4093 3735891 : if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4094 : {
4095 71717 : for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4096 47822 : if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4097 : {
4098 23927 : rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4099 23927 : if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4100 23927 : || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4101 : {
4102 0 : undo_all ();
4103 0 : return 0;
4104 : }
4105 : }
4106 : }
4107 :
4108 : if (insn_code_number >= 0)
4109 : split_i2i3 = true;
4110 : }
4111 : }
4112 :
4113 : /* If it still isn't recognized, fail and change things back the way they
4114 : were. */
4115 29622962 : if ((insn_code_number < 0
4116 : /* Is the result a reasonable ASM_OPERANDS? */
4117 33202756 : && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4118 : {
4119 29077972 : undo_all ();
4120 29077972 : return 0;
4121 : }
4122 :
4123 : /* If we had to change another insn, make sure it is valid also. */
4124 4287271 : if (undobuf.other_insn)
4125 : {
4126 230555 : CLEAR_HARD_REG_SET (newpat_used_regs);
4127 :
4128 230555 : other_pat = PATTERN (undobuf.other_insn);
4129 230555 : other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4130 : &new_other_notes);
4131 :
4132 230555 : if (other_code_number < 0 && ! check_asm_operands (other_pat))
4133 : {
4134 6582 : undo_all ();
4135 6582 : return 0;
4136 : }
4137 : }
4138 :
4139 : /* Reject this combination if insn_cost reports that the replacement
4140 : instructions are more expensive than the originals. */
4141 4280689 : if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat,
4142 : insn_code_number, i2_code_number,
4143 : other_code_number))
4144 : {
4145 213370 : undo_all ();
4146 213370 : return 0;
4147 : }
4148 :
4149 4067319 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4150 : {
4151 2192496 : struct undo *undo;
4152 :
4153 6559031 : for (undo = undobuf.undos; undo; undo = undo->next)
4154 4366535 : if (undo->kind == UNDO_MODE)
4155 : {
4156 2876 : rtx reg = regno_reg_rtx[undo->where.regno];
4157 2876 : machine_mode new_mode = GET_MODE (reg);
4158 2876 : machine_mode old_mode = undo->old_contents.m;
4159 :
4160 : /* Temporarily revert mode back. */
4161 2876 : adjust_reg_mode (reg, old_mode);
4162 :
4163 2876 : if (reg == i2dest && i2scratch)
4164 : {
4165 : /* If we used i2dest as a scratch register with a
4166 : different mode, substitute it for the original
4167 : i2src while its original mode is temporarily
4168 : restored, and then clear i2scratch so that we don't
4169 : do it again later. */
4170 2876 : propagate_for_debug (i2, last_combined_insn, reg, i2src,
4171 : this_basic_block);
4172 2876 : i2scratch = false;
4173 : /* Put back the new mode. */
4174 2876 : adjust_reg_mode (reg, new_mode);
4175 : }
4176 : else
4177 : {
4178 0 : rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4179 0 : rtx_insn *first, *last;
4180 :
4181 0 : if (reg == i2dest)
4182 : {
4183 : first = i2;
4184 : last = last_combined_insn;
4185 : }
4186 : else
4187 : {
4188 0 : first = i3;
4189 0 : last = undobuf.other_insn;
4190 0 : gcc_assert (last);
4191 0 : if (DF_INSN_LUID (last)
4192 0 : < DF_INSN_LUID (last_combined_insn))
4193 0 : last = last_combined_insn;
4194 : }
4195 :
4196 : /* We're dealing with a reg that changed mode but not
4197 : meaning, so we want to turn it into a subreg for
4198 : the new mode. However, because of REG sharing and
4199 : because its mode had already changed, we have to do
4200 : it in two steps. First, replace any debug uses of
4201 : reg, with its original mode temporarily restored,
4202 : with this copy we have created; then, replace the
4203 : copy with the SUBREG of the original shared reg,
4204 : once again changed to the new mode. */
4205 0 : propagate_for_debug (first, last, reg, tempreg,
4206 : this_basic_block);
4207 0 : adjust_reg_mode (reg, new_mode);
4208 0 : propagate_for_debug (first, last, tempreg,
4209 : lowpart_subreg (old_mode, reg, new_mode),
4210 : this_basic_block);
4211 : }
4212 : }
4213 : }
4214 :
4215 : /* If we will be able to accept this, we have made a
4216 : change to the destination of I3. This requires us to
4217 : do a few adjustments. */
4218 :
4219 4067319 : if (changed_i3_dest)
4220 : {
4221 17396 : PATTERN (i3) = newpat;
4222 17396 : adjust_for_new_dest (i3);
4223 : }
4224 :
4225 4067319 : bool only_i3_changed = !i0 && !i1 && rtx_equal_p (newi2pat, PATTERN (i2));
4226 :
4227 : /* If only i3 has changed, any split of the combined instruction just
4228 : restored i2 to its original state. No destinations moved from i3
4229 : to i2. */
4230 : if (only_i3_changed)
4231 : split_i2i3 = false;
4232 :
4233 : /* We now know that we can do this combination. Merge the insns and
4234 : update the status of registers and LOG_LINKS. */
4235 :
4236 4067319 : if (undobuf.other_insn)
4237 : {
4238 223813 : rtx note, next;
4239 :
4240 223813 : PATTERN (undobuf.other_insn) = other_pat;
4241 :
4242 : /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4243 : ensure that they are still valid. Then add any non-duplicate
4244 : notes added by recog_for_combine. */
4245 668600 : for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4246 : {
4247 444787 : next = XEXP (note, 1);
4248 :
4249 444787 : if ((REG_NOTE_KIND (note) == REG_DEAD
4250 226986 : && !reg_referenced_p (XEXP (note, 0),
4251 226986 : PATTERN (undobuf.other_insn)))
4252 440508 : ||(REG_NOTE_KIND (note) == REG_UNUSED
4253 5 : && !reg_set_p (XEXP (note, 0),
4254 5 : PATTERN (undobuf.other_insn)))
4255 : /* Simply drop equal note since it may be no longer valid
4256 : for other_insn. It may be possible to record that CC
4257 : register is changed and only discard those notes, but
4258 : in practice it's unnecessary complication and doesn't
4259 : give any meaningful improvement.
4260 :
4261 : See PR78559. */
4262 440508 : || REG_NOTE_KIND (note) == REG_EQUAL
4263 885159 : || REG_NOTE_KIND (note) == REG_EQUIV)
4264 4415 : remove_note (undobuf.other_insn, note);
4265 : }
4266 :
4267 223813 : distribute_notes (new_other_notes, undobuf.other_insn,
4268 : undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4269 : NULL_RTX);
4270 : }
4271 :
4272 4067319 : if (swap_i2i3)
4273 : {
4274 : /* I3 now uses what used to be its destination and which is now
4275 : I2's destination. This requires us to do a few adjustments. */
4276 0 : PATTERN (i3) = newpat;
4277 0 : adjust_for_new_dest (i3);
4278 : }
4279 :
4280 4067319 : if (swap_i2i3 || split_i2i3)
4281 : {
4282 : /* We might need a LOG_LINK from I3 to I2. But then we used to
4283 : have one, so we still will.
4284 :
4285 : However, some later insn might be using I2's dest and have
4286 : a LOG_LINK pointing at I3. We should change it to point at
4287 : I2 instead. */
4288 :
4289 : /* newi2pat is usually a SET here; however, recog_for_combine might
4290 : have added some clobbers. */
4291 27360 : rtx x = newi2pat;
4292 27360 : if (GET_CODE (x) == PARALLEL)
4293 550 : x = XVECEXP (newi2pat, 0, 0);
4294 :
4295 27360 : if (REG_P (SET_DEST (x))
4296 8 : || (GET_CODE (SET_DEST (x)) == SUBREG
4297 2 : && REG_P (SUBREG_REG (SET_DEST (x)))))
4298 : {
4299 27354 : unsigned int regno = reg_or_subregno (SET_DEST (x));
4300 :
4301 27354 : bool done = false;
4302 373178 : for (rtx_insn *insn = NEXT_INSN (i3);
4303 373178 : !done
4304 373178 : && insn
4305 371876 : && INSN_P (insn)
4306 719002 : && BLOCK_FOR_INSN (insn) == this_basic_block;
4307 345824 : insn = NEXT_INSN (insn))
4308 : {
4309 345824 : if (DEBUG_INSN_P (insn))
4310 68114 : continue;
4311 277710 : struct insn_link *link;
4312 522187 : FOR_EACH_LOG_LINK (link, insn)
4313 244487 : if (link->insn == i3 && link->regno == regno)
4314 : {
4315 10 : link->insn = i2;
4316 10 : done = true;
4317 10 : break;
4318 : }
4319 : }
4320 : }
4321 : }
4322 :
4323 4067319 : {
4324 4067319 : rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4325 4067319 : struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4326 4067319 : rtx midnotes = 0;
4327 4067319 : int from_luid;
4328 : /* Compute which registers we expect to eliminate. newi2pat may be setting
4329 : either i3dest or i2dest, so we must check it. */
4330 102615 : rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4331 3975998 : || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4332 3890276 : || !i2dest_killed
4333 7956516 : ? 0 : i2dest);
4334 : /* For i1, we need to compute both local elimination and global
4335 : elimination information with respect to newi2pat because i1dest
4336 : may be the same as i3dest, in which case newi2pat may be setting
4337 : i1dest. Global information is used when distributing REG_DEAD
4338 : note for i2 and i3, in which case it does matter if newi2pat sets
4339 : i1dest or not.
4340 :
4341 : Local information is used when distributing REG_DEAD note for i1,
4342 : in which case it doesn't matter if newi2pat sets i1dest or not.
4343 : See PR62151, if we have four insns combination:
4344 : i0: r0 <- i0src
4345 : i1: r1 <- i1src (using r0)
4346 : REG_DEAD (r0)
4347 : i2: r0 <- i2src (using r1)
4348 : i3: r3 <- i3src (using r0)
4349 : ix: using r0
4350 : From i1's point of view, r0 is eliminated, no matter if it is set
4351 : by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4352 : should be discarded.
4353 :
4354 : Note local information only affects cases in forms like "I1->I2->I3",
4355 : "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4356 : "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4357 : i0dest anyway. */
4358 101859 : rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4359 101793 : || !i1dest_killed
4360 4067319 : ? 0 : i1dest);
4361 101792 : rtx elim_i1 = (local_elim_i1 == 0
4362 101792 : || (newi2pat && reg_set_p (i1dest, newi2pat))
4363 101792 : ? 0 : i1dest);
4364 : /* Same case as i1. */
4365 4511 : rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4366 4067319 : ? 0 : i0dest);
4367 4499 : rtx elim_i0 = (local_elim_i0 == 0
4368 4499 : || (newi2pat && reg_set_p (i0dest, newi2pat))
4369 4499 : ? 0 : i0dest);
4370 :
4371 : /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4372 : clear them. */
4373 4067319 : i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4374 4067319 : i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4375 4067319 : if (i1)
4376 101859 : i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4377 4067319 : if (i0)
4378 4511 : i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4379 :
4380 : /* Ensure that we do not have something that should not be shared but
4381 : occurs multiple times in the new insns. Check this by first
4382 : resetting all the `used' flags and then copying anything is shared. */
4383 :
4384 4067319 : reset_used_flags (i3notes);
4385 4067319 : reset_used_flags (i2notes);
4386 4067319 : reset_used_flags (i1notes);
4387 4067319 : reset_used_flags (i0notes);
4388 4067319 : reset_used_flags (newpat);
4389 4067319 : reset_used_flags (newi2pat);
4390 4067319 : if (undobuf.other_insn)
4391 223813 : reset_used_flags (PATTERN (undobuf.other_insn));
4392 :
4393 4067319 : i3notes = copy_rtx_if_shared (i3notes);
4394 4067319 : i2notes = copy_rtx_if_shared (i2notes);
4395 4067319 : i1notes = copy_rtx_if_shared (i1notes);
4396 4067319 : i0notes = copy_rtx_if_shared (i0notes);
4397 4067319 : newpat = copy_rtx_if_shared (newpat);
4398 4067319 : newi2pat = copy_rtx_if_shared (newi2pat);
4399 4067319 : if (undobuf.other_insn)
4400 223813 : reset_used_flags (PATTERN (undobuf.other_insn));
4401 :
4402 4067319 : INSN_CODE (i3) = insn_code_number;
4403 4067319 : PATTERN (i3) = newpat;
4404 :
4405 4067319 : if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4406 : {
4407 241926 : for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4408 163729 : link = XEXP (link, 1))
4409 : {
4410 163729 : if (substed_i2)
4411 : {
4412 : /* I2SRC must still be meaningful at this point. Some
4413 : splitting operations can invalidate I2SRC, but those
4414 : operations do not apply to calls. */
4415 163729 : gcc_assert (i2src);
4416 163729 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4417 : i2dest, i2src);
4418 : }
4419 163729 : if (substed_i1)
4420 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4421 : i1dest, i1src);
4422 163729 : if (substed_i0)
4423 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4424 : i0dest, i0src);
4425 : }
4426 : }
4427 :
4428 4067319 : if (undobuf.other_insn)
4429 223813 : INSN_CODE (undobuf.other_insn) = other_code_number;
4430 :
4431 : /* We had one special case above where I2 had more than one set and
4432 : we replaced a destination of one of those sets with the destination
4433 : of I3. In that case, we have to update LOG_LINKS of insns later
4434 : in this basic block. Note that this (expensive) case is rare.
4435 :
4436 : Also, in this case, we must pretend that all REG_NOTEs for I2
4437 : actually came from I3, so that REG_UNUSED notes from I2 will be
4438 : properly handled. */
4439 :
4440 4067319 : if (i3_subst_into_i2)
4441 : {
4442 203790 : for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4443 140067 : if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4444 65034 : || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4445 139234 : && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4446 124368 : && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4447 264435 : && ! find_reg_note (i2, REG_UNUSED,
4448 124368 : SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4449 31809303 : for (temp_insn = NEXT_INSN (i2);
4450 : temp_insn
4451 31809303 : && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4452 31559535 : || BB_HEAD (this_basic_block) != temp_insn);
4453 31753324 : temp_insn = NEXT_INSN (temp_insn))
4454 31753324 : if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4455 20300097 : FOR_EACH_LOG_LINK (link, temp_insn)
4456 7495634 : if (link->insn == i2)
4457 440 : link->insn = i3;
4458 :
4459 63723 : if (i3notes)
4460 : {
4461 : rtx link = i3notes;
4462 71254 : while (XEXP (link, 1))
4463 : link = XEXP (link, 1);
4464 63723 : XEXP (link, 1) = i2notes;
4465 : }
4466 : else
4467 : i3notes = i2notes;
4468 : i2notes = 0;
4469 : }
4470 :
4471 4067319 : LOG_LINKS (i3) = NULL;
4472 4067319 : REG_NOTES (i3) = 0;
4473 4067319 : LOG_LINKS (i2) = NULL;
4474 4067319 : REG_NOTES (i2) = 0;
4475 :
4476 4067319 : if (newi2pat)
4477 : {
4478 102615 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4479 10077 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4480 : this_basic_block);
4481 102615 : INSN_CODE (i2) = i2_code_number;
4482 102615 : PATTERN (i2) = newi2pat;
4483 : }
4484 : else
4485 : {
4486 3964704 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4487 2127078 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4488 : this_basic_block);
4489 3964704 : SET_INSN_DELETED (i2);
4490 : }
4491 :
4492 4067319 : if (i1)
4493 : {
4494 101859 : LOG_LINKS (i1) = NULL;
4495 101859 : REG_NOTES (i1) = 0;
4496 101859 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4497 52972 : propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4498 : this_basic_block);
4499 101859 : SET_INSN_DELETED (i1);
4500 : }
4501 :
4502 4067319 : if (i0)
4503 : {
4504 4511 : LOG_LINKS (i0) = NULL;
4505 4511 : REG_NOTES (i0) = 0;
4506 4511 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4507 2820 : propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4508 : this_basic_block);
4509 4511 : SET_INSN_DELETED (i0);
4510 : }
4511 :
4512 : /* Get death notes for everything that is now used in either I3 or
4513 : I2 and used to die in a previous insn. If we built two new
4514 : patterns, move from I1 to I2 then I2 to I3 so that we get the
4515 : proper movement on registers that I2 modifies. */
4516 :
4517 4511 : if (i0)
4518 4511 : from_luid = DF_INSN_LUID (i0);
4519 4062808 : else if (i1)
4520 97348 : from_luid = DF_INSN_LUID (i1);
4521 : else
4522 3965460 : from_luid = DF_INSN_LUID (i2);
4523 4067319 : if (newi2pat)
4524 102615 : move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4525 4067319 : move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4526 :
4527 : /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4528 4067319 : if (i3notes)
4529 7361475 : distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4530 : elim_i2, elim_i1, elim_i0);
4531 4067319 : if (i2notes)
4532 5669018 : distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4533 : elim_i2, elim_i1, elim_i0);
4534 4067319 : if (i1notes)
4535 59385 : distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4536 : elim_i2, local_elim_i1, local_elim_i0);
4537 4067319 : if (i0notes)
4538 3794 : distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4539 : elim_i2, elim_i1, local_elim_i0);
4540 4067319 : if (midnotes)
4541 4861182 : distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4542 : elim_i2, elim_i1, elim_i0);
4543 :
4544 : /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4545 : know these are REG_UNUSED and want them to go to the desired insn,
4546 : so we always pass it as i3. */
4547 :
4548 4067319 : if (newi2pat && new_i2_notes)
4549 40861 : distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4550 : NULL_RTX);
4551 :
4552 4067319 : if (new_i3_notes)
4553 153752 : distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4554 : NULL_RTX);
4555 :
4556 : /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4557 : put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4558 : I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4559 : in that case, it might delete I2. Similarly for I2 and I1.
4560 : Show an additional death due to the REG_DEAD note we make here. If
4561 : we discard it in distribute_notes, we will decrement it again. */
4562 :
4563 4067319 : if (i3dest_killed)
4564 : {
4565 339291 : rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4566 339291 : if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4567 667 : distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4568 : elim_i1, elim_i0);
4569 : else
4570 675350 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4571 : elim_i2, elim_i1, elim_i0);
4572 : }
4573 :
4574 4067319 : if (i2dest_in_i2src)
4575 : {
4576 84686 : rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4577 84686 : if (newi2pat && reg_set_p (i2dest, newi2pat))
4578 849 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4579 : NULL_RTX, NULL_RTX);
4580 : else
4581 167636 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4582 : NULL_RTX, NULL_RTX, NULL_RTX);
4583 : }
4584 :
4585 4067319 : if (i1dest_in_i1src)
4586 : {
4587 64 : rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4588 64 : if (newi2pat && reg_set_p (i1dest, newi2pat))
4589 5 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4590 : NULL_RTX, NULL_RTX);
4591 : else
4592 101 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4593 : NULL_RTX, NULL_RTX, NULL_RTX);
4594 : }
4595 :
4596 4067319 : if (i0dest_in_i0src)
4597 : {
4598 12 : rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4599 12 : if (newi2pat && reg_set_p (i0dest, newi2pat))
4600 0 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4601 : NULL_RTX, NULL_RTX);
4602 : else
4603 24 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4604 : NULL_RTX, NULL_RTX, NULL_RTX);
4605 : }
4606 :
4607 4067319 : if (only_i3_changed)
4608 33610 : distribute_links (i3links, i3, param_max_combine_search_insns);
4609 : else
4610 : {
4611 4033709 : distribute_links (i3links);
4612 4033709 : distribute_links (i2links, i2);
4613 4033709 : distribute_links (i1links);
4614 4033709 : distribute_links (i0links);
4615 : }
4616 :
4617 4067319 : if (REG_P (i2dest))
4618 : {
4619 4067319 : struct insn_link *link;
4620 4067319 : rtx_insn *i2_insn = 0;
4621 4067319 : rtx i2_val = 0, set;
4622 :
4623 : /* The insn that used to set this register doesn't exist, and
4624 : this life of the register may not exist either. See if one of
4625 : I3's links points to an insn that sets I2DEST. If it does,
4626 : that is now the last known value for I2DEST. If we don't update
4627 : this and I2 set the register to a value that depended on its old
4628 : contents, we will get confused. If this insn is used, thing
4629 : will be set correctly in combine_instructions. */
4630 7494722 : FOR_EACH_LOG_LINK (link, i3)
4631 3427403 : if ((set = single_set (link->insn)) != 0
4632 3427403 : && rtx_equal_p (i2dest, SET_DEST (set)))
4633 47337 : i2_insn = link->insn, i2_val = SET_SRC (set);
4634 :
4635 4067319 : record_value_for_reg (i2dest, i2_insn, i2_val);
4636 :
4637 : /* If the reg formerly set in I2 died only once and that was in I3,
4638 : zero its use count so it won't make `reload' do any work. */
4639 4067319 : if (! added_sets_2
4640 3939733 : && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4641 3901741 : && ! i2dest_in_i2src
4642 7905078 : && REGNO (i2dest) < reg_n_sets_max)
4643 3837757 : INC_REG_N_SETS (REGNO (i2dest), -1);
4644 : }
4645 :
4646 4067319 : if (i1 && REG_P (i1dest))
4647 : {
4648 101859 : struct insn_link *link;
4649 101859 : rtx_insn *i1_insn = 0;
4650 101859 : rtx i1_val = 0, set;
4651 :
4652 177342 : FOR_EACH_LOG_LINK (link, i3)
4653 75483 : if ((set = single_set (link->insn)) != 0
4654 75483 : && rtx_equal_p (i1dest, SET_DEST (set)))
4655 494 : i1_insn = link->insn, i1_val = SET_SRC (set);
4656 :
4657 101859 : record_value_for_reg (i1dest, i1_insn, i1_val);
4658 :
4659 101859 : if (! added_sets_1
4660 : && ! i1dest_in_i1src
4661 101859 : && REGNO (i1dest) < reg_n_sets_max)
4662 95808 : INC_REG_N_SETS (REGNO (i1dest), -1);
4663 : }
4664 :
4665 4067319 : if (i0 && REG_P (i0dest))
4666 : {
4667 4511 : struct insn_link *link;
4668 4511 : rtx_insn *i0_insn = 0;
4669 4511 : rtx i0_val = 0, set;
4670 :
4671 6882 : FOR_EACH_LOG_LINK (link, i3)
4672 2371 : if ((set = single_set (link->insn)) != 0
4673 2371 : && rtx_equal_p (i0dest, SET_DEST (set)))
4674 0 : i0_insn = link->insn, i0_val = SET_SRC (set);
4675 :
4676 4511 : record_value_for_reg (i0dest, i0_insn, i0_val);
4677 :
4678 4511 : if (! added_sets_0
4679 : && ! i0dest_in_i0src
4680 4511 : && REGNO (i0dest) < reg_n_sets_max)
4681 4451 : INC_REG_N_SETS (REGNO (i0dest), -1);
4682 : }
4683 :
4684 : /* Update reg_stat[].nonzero_bits et al for any changes that may have
4685 : been made to this insn. The order is important, because newi2pat
4686 : can affect nonzero_bits of newpat. */
4687 4067319 : if (newi2pat)
4688 102615 : note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4689 4067319 : note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4690 : }
4691 :
4692 4067319 : if (undobuf.other_insn != NULL_RTX)
4693 : {
4694 223813 : if (dump_file)
4695 : {
4696 12 : fprintf (dump_file, "modifying other_insn ");
4697 12 : dump_insn_slim (dump_file, undobuf.other_insn);
4698 : }
4699 223813 : df_insn_rescan (undobuf.other_insn);
4700 : }
4701 :
4702 4067319 : if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4703 : {
4704 0 : if (dump_file)
4705 : {
4706 0 : fprintf (dump_file, "modifying insn i0 ");
4707 0 : dump_insn_slim (dump_file, i0);
4708 : }
4709 0 : df_insn_rescan (i0);
4710 : }
4711 :
4712 4067319 : if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4713 : {
4714 0 : if (dump_file)
4715 : {
4716 0 : fprintf (dump_file, "modifying insn i1 ");
4717 0 : dump_insn_slim (dump_file, i1);
4718 : }
4719 0 : df_insn_rescan (i1);
4720 : }
4721 :
4722 4067319 : if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4723 : {
4724 102615 : if (dump_file)
4725 : {
4726 15 : fprintf (dump_file, "modifying insn i2 ");
4727 15 : dump_insn_slim (dump_file, i2);
4728 : }
4729 102615 : df_insn_rescan (i2);
4730 : }
4731 :
4732 4067319 : if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4733 : {
4734 4067319 : if (dump_file)
4735 : {
4736 240 : fprintf (dump_file, "modifying insn i3 ");
4737 240 : dump_insn_slim (dump_file, i3);
4738 : }
4739 4067319 : df_insn_rescan (i3);
4740 : }
4741 :
4742 : /* Set new_direct_jump_p if a new return or simple jump instruction
4743 : has been created. Adjust the CFG accordingly. */
4744 4067319 : if (returnjump_p (i3) || any_uncondjump_p (i3))
4745 : {
4746 196 : *new_direct_jump_p = 1;
4747 196 : mark_jump_label (PATTERN (i3), i3, 0);
4748 196 : update_cfg_for_uncondjump (i3);
4749 : }
4750 :
4751 4067319 : if (undobuf.other_insn != NULL_RTX
4752 4067319 : && (returnjump_p (undobuf.other_insn)
4753 223813 : || any_uncondjump_p (undobuf.other_insn)))
4754 : {
4755 1954 : *new_direct_jump_p = 1;
4756 1954 : update_cfg_for_uncondjump (undobuf.other_insn);
4757 : }
4758 :
4759 4067319 : if (GET_CODE (PATTERN (i3)) == TRAP_IF
4760 4067319 : && XEXP (PATTERN (i3), 0) == const1_rtx)
4761 : {
4762 0 : basic_block bb = BLOCK_FOR_INSN (i3);
4763 0 : gcc_assert (bb);
4764 0 : remove_edge (split_block (bb, i3));
4765 0 : emit_barrier_after_bb (bb);
4766 0 : *new_direct_jump_p = 1;
4767 : }
4768 :
4769 4067319 : if (undobuf.other_insn
4770 223813 : && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4771 4067319 : && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4772 : {
4773 0 : basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4774 0 : gcc_assert (bb);
4775 0 : remove_edge (split_block (bb, undobuf.other_insn));
4776 0 : emit_barrier_after_bb (bb);
4777 0 : *new_direct_jump_p = 1;
4778 : }
4779 :
4780 : /* A noop might also need cleaning up of CFG, if it comes from the
4781 : simplification of a jump. */
4782 4067319 : if (JUMP_P (i3)
4783 46023 : && GET_CODE (newpat) == SET
4784 34766 : && SET_SRC (newpat) == pc_rtx
4785 390 : && SET_DEST (newpat) == pc_rtx)
4786 : {
4787 390 : *new_direct_jump_p = 1;
4788 390 : update_cfg_for_uncondjump (i3);
4789 : }
4790 :
4791 4067319 : if (undobuf.other_insn != NULL_RTX
4792 223813 : && JUMP_P (undobuf.other_insn)
4793 217731 : && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4794 217731 : && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4795 4069054 : && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4796 : {
4797 1735 : *new_direct_jump_p = 1;
4798 1735 : update_cfg_for_uncondjump (undobuf.other_insn);
4799 : }
4800 :
4801 4067319 : combine_successes++;
4802 4067319 : undo_commit ();
4803 :
4804 4067319 : if (only_i3_changed)
4805 : return i3;
4806 :
4807 4033709 : rtx_insn *ret = newi2pat ? i2 : i3;
4808 4033709 : if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4809 : ret = added_links_insn;
4810 4033709 : if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4811 : ret = added_notes_insn;
4812 :
4813 : return ret;
4814 : }
4815 :
4816 : /* Get a marker for undoing to the current state. */
4817 :
4818 : static void *
4819 38081305 : get_undo_marker (void)
4820 : {
4821 38081305 : return undobuf.undos;
4822 : }
4823 :
4824 : /* Undo the modifications up to the marker. */
4825 :
4826 : static void
4827 44922642 : undo_to_marker (void *marker)
4828 : {
4829 44922642 : struct undo *undo, *next;
4830 :
4831 141314072 : for (undo = undobuf.undos; undo != marker; undo = next)
4832 : {
4833 96391430 : gcc_assert (undo);
4834 :
4835 96391430 : next = undo->next;
4836 96391430 : switch (undo->kind)
4837 : {
4838 89145816 : case UNDO_RTX:
4839 89145816 : *undo->where.r = undo->old_contents.r;
4840 89145816 : break;
4841 6609802 : case UNDO_INT:
4842 6609802 : *undo->where.i = undo->old_contents.i;
4843 6609802 : break;
4844 565127 : case UNDO_MODE:
4845 565127 : adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4846 : undo->old_contents.m);
4847 565127 : break;
4848 70685 : case UNDO_LINKS:
4849 70685 : *undo->where.l = undo->old_contents.l;
4850 70685 : break;
4851 0 : default:
4852 0 : gcc_unreachable ();
4853 : }
4854 :
4855 96391430 : undo->next = undobuf.frees;
4856 96391430 : undobuf.frees = undo;
4857 : }
4858 :
4859 44922642 : undobuf.undos = (struct undo *) marker;
4860 44922642 : }
4861 :
4862 : /* Undo all the modifications recorded in undobuf. */
4863 :
4864 : static void
4865 43795210 : undo_all (void)
4866 : {
4867 43795210 : undo_to_marker (0);
4868 0 : }
4869 :
4870 : /* We've committed to accepting the changes we made. Move all
4871 : of the undos to the free list. */
4872 :
4873 : static void
4874 4067319 : undo_commit (void)
4875 : {
4876 4067319 : struct undo *undo, *next;
4877 :
4878 11960692 : for (undo = undobuf.undos; undo; undo = next)
4879 : {
4880 7893373 : next = undo->next;
4881 7893373 : undo->next = undobuf.frees;
4882 7893373 : undobuf.frees = undo;
4883 : }
4884 4067319 : undobuf.undos = 0;
4885 4067319 : }
4886 :
4887 : /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4888 : where we have an arithmetic expression and return that point. LOC will
4889 : be inside INSN.
4890 :
4891 : try_combine will call this function to see if an insn can be split into
4892 : two insns. */
4893 :
4894 : static rtx *
4895 31707869 : find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4896 : {
4897 32762191 : rtx x = *loc;
4898 32762191 : enum rtx_code code = GET_CODE (x);
4899 32762191 : rtx *split;
4900 32762191 : unsigned HOST_WIDE_INT len = 0;
4901 32762191 : HOST_WIDE_INT pos = 0;
4902 32762191 : bool unsignedp = false;
4903 32762191 : rtx inner = NULL_RTX;
4904 32762191 : scalar_int_mode mode, inner_mode;
4905 :
4906 : /* First special-case some codes. */
4907 32762191 : switch (code)
4908 : {
4909 1059494 : case SUBREG:
4910 : #ifdef INSN_SCHEDULING
4911 : /* If we are making a paradoxical SUBREG invalid, it becomes a split
4912 : point. */
4913 1059494 : if (MEM_P (SUBREG_REG (x)))
4914 : return loc;
4915 : #endif
4916 1047600 : return find_split_point (&SUBREG_REG (x), insn, false);
4917 :
4918 1528449 : case MEM:
4919 : /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4920 : using LO_SUM and HIGH. */
4921 1528449 : if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4922 : || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4923 : {
4924 : machine_mode address_mode = get_address_mode (x);
4925 :
4926 : SUBST (XEXP (x, 0),
4927 : gen_rtx_LO_SUM (address_mode,
4928 : gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4929 : XEXP (x, 0)));
4930 : return &XEXP (XEXP (x, 0), 0);
4931 : }
4932 :
4933 : /* If we have a PLUS whose second operand is a constant and the
4934 : address is not valid, perhaps we can split it up using
4935 : the machine-specific way to split large constants. We use
4936 : the first pseudo-reg (one of the virtual regs) as a placeholder;
4937 : it will not remain in the result. */
4938 1528449 : if (GET_CODE (XEXP (x, 0)) == PLUS
4939 1012098 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4940 3276503 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4941 735956 : MEM_ADDR_SPACE (x)))
4942 : {
4943 112913 : rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4944 112913 : unsigned int old_nregs, new_nregs;
4945 112913 : rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4946 : subst_insn, &old_nregs, &new_nregs);
4947 :
4948 : /* This should have produced two insns, each of which sets our
4949 : placeholder. If the source of the second is a valid address,
4950 : we can put both sources together and make a split point
4951 : in the middle. */
4952 :
4953 112913 : if (seq
4954 56 : && NEXT_INSN (seq) != NULL_RTX
4955 0 : && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4956 0 : && NONJUMP_INSN_P (seq)
4957 0 : && GET_CODE (PATTERN (seq)) == SET
4958 0 : && SET_DEST (PATTERN (seq)) == reg
4959 0 : && ! reg_mentioned_p (reg,
4960 0 : SET_SRC (PATTERN (seq)))
4961 0 : && NONJUMP_INSN_P (NEXT_INSN (seq))
4962 0 : && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4963 0 : && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4964 112913 : && memory_address_addr_space_p
4965 112913 : (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4966 0 : MEM_ADDR_SPACE (x)))
4967 : {
4968 0 : rtx src1 = SET_SRC (PATTERN (seq));
4969 0 : rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4970 :
4971 : /* Replace the placeholder in SRC2 with SRC1. If we can
4972 : find where in SRC2 it was placed, that can become our
4973 : split point and we can replace this address with SRC2.
4974 : Just try two obvious places. */
4975 :
4976 0 : src2 = replace_rtx (src2, reg, src1);
4977 0 : split = 0;
4978 0 : if (XEXP (src2, 0) == src1)
4979 0 : split = &XEXP (src2, 0);
4980 0 : else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4981 0 : && XEXP (XEXP (src2, 0), 0) == src1)
4982 0 : split = &XEXP (XEXP (src2, 0), 0);
4983 :
4984 0 : if (split)
4985 : {
4986 0 : SUBST (XEXP (x, 0), src2);
4987 88146 : return split;
4988 : }
4989 : }
4990 :
4991 : /* If that didn't work and we have a nested plus, like:
4992 : ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4993 : is valid address, try to split (REG1 * CONST1). */
4994 112913 : if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4995 74867 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4996 58521 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4997 58510 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4998 10 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4999 : 0), 0)))))
5000 : {
5001 58510 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
5002 58510 : XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
5003 117020 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5004 58510 : MEM_ADDR_SPACE (x)))
5005 : {
5006 47233 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5007 47233 : return &XEXP (XEXP (XEXP (x, 0), 0), 0);
5008 : }
5009 11277 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5010 11277 : }
5011 54403 : else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5012 16357 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5013 16346 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5014 286 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
5015 286 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5016 : 0), 1)))))
5017 : {
5018 0 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
5019 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
5020 0 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5021 0 : MEM_ADDR_SPACE (x)))
5022 : {
5023 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5024 0 : return &XEXP (XEXP (XEXP (x, 0), 0), 1);
5025 : }
5026 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5027 : }
5028 :
5029 : /* If that didn't work, perhaps the first operand is complex and
5030 : needs to be computed separately, so make a split point there.
5031 : This will occur on machines that just support REG + CONST
5032 : and have a constant moved through some previous computation. */
5033 65680 : if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5034 40913 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5035 0 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5036 40913 : return &XEXP (XEXP (x, 0), 0);
5037 : }
5038 :
5039 : /* If we have a PLUS whose first operand is complex, try computing it
5040 : separately by making a split there. */
5041 1440303 : if (GET_CODE (XEXP (x, 0)) == PLUS
5042 2529222 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5043 923952 : MEM_ADDR_SPACE (x))
5044 164967 : && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5045 1550448 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5046 590 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5047 110141 : return &XEXP (XEXP (x, 0), 0);
5048 : break;
5049 :
5050 4781816 : case SET:
5051 : /* See if we can split SET_SRC as it stands. */
5052 4781816 : split = find_split_point (&SET_SRC (x), insn, true);
5053 4781816 : if (split && split != &SET_SRC (x))
5054 : return split;
5055 :
5056 : /* See if we can split SET_DEST as it stands. */
5057 509044 : split = find_split_point (&SET_DEST (x), insn, false);
5058 509044 : if (split && split != &SET_DEST (x))
5059 : return split;
5060 :
5061 : /* See if this is a bitfield assignment with everything constant. If
5062 : so, this is an IOR of an AND, so split it into that. */
5063 479081 : if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5064 3767 : && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5065 : &inner_mode)
5066 3767 : && HWI_COMPUTABLE_MODE_P (inner_mode)
5067 3767 : && CONST_INT_P (XEXP (SET_DEST (x), 1))
5068 3767 : && CONST_INT_P (XEXP (SET_DEST (x), 2))
5069 3605 : && CONST_INT_P (SET_SRC (x))
5070 303 : && ((INTVAL (XEXP (SET_DEST (x), 1))
5071 303 : + INTVAL (XEXP (SET_DEST (x), 2)))
5072 303 : <= GET_MODE_PRECISION (inner_mode))
5073 479384 : && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5074 : {
5075 290 : HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5076 290 : unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5077 290 : rtx dest = XEXP (SET_DEST (x), 0);
5078 290 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5079 290 : unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5080 290 : rtx or_mask;
5081 :
5082 290 : if (BITS_BIG_ENDIAN)
5083 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5084 :
5085 290 : or_mask = gen_int_mode (src << pos, inner_mode);
5086 290 : if (src == mask)
5087 0 : SUBST (SET_SRC (x),
5088 : simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5089 : else
5090 : {
5091 290 : rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5092 290 : SUBST (SET_SRC (x),
5093 : simplify_gen_binary (IOR, inner_mode,
5094 : simplify_gen_binary (AND, inner_mode,
5095 : dest, negmask),
5096 : or_mask));
5097 : }
5098 :
5099 290 : SUBST (SET_DEST (x), dest);
5100 :
5101 290 : split = find_split_point (&SET_SRC (x), insn, true);
5102 290 : if (split && split != &SET_SRC (x))
5103 : return split;
5104 : }
5105 :
5106 : /* Otherwise, see if this is an operation that we can split into two.
5107 : If so, try to split that. */
5108 478791 : code = GET_CODE (SET_SRC (x));
5109 :
5110 478791 : switch (code)
5111 : {
5112 16483 : case AND:
5113 : /* If we are AND'ing with a large constant that is only a single
5114 : bit and the result is only being used in a context where we
5115 : need to know if it is zero or nonzero, replace it with a bit
5116 : extraction. This will avoid the large constant, which might
5117 : have taken more than one insn to make. If the constant were
5118 : not a valid argument to the AND but took only one insn to make,
5119 : this is no worse, but if it took more than one insn, it will
5120 : be better. */
5121 :
5122 16483 : if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5123 11018 : && REG_P (XEXP (SET_SRC (x), 0))
5124 450 : && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5125 2 : && REG_P (SET_DEST (x))
5126 1 : && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5127 1 : && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5128 0 : && XEXP (*split, 0) == SET_DEST (x)
5129 16483 : && XEXP (*split, 1) == const0_rtx)
5130 : {
5131 0 : rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5132 0 : XEXP (SET_SRC (x), 0),
5133 : pos, NULL_RTX, 1,
5134 : true, false, false);
5135 0 : if (extraction != 0)
5136 : {
5137 0 : SUBST (SET_SRC (x), extraction);
5138 0 : return find_split_point (loc, insn, false);
5139 : }
5140 : }
5141 : break;
5142 :
5143 : case NE:
5144 : /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5145 : is known to be on, this can be converted into a NEG of a shift. */
5146 : if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5147 : && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5148 : && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5149 : GET_MODE (XEXP (SET_SRC (x),
5150 : 0))))) >= 1))
5151 : {
5152 : machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5153 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5154 : SUBST (SET_SRC (x),
5155 : gen_rtx_NEG (mode,
5156 : gen_rtx_LSHIFTRT (mode,
5157 : XEXP (SET_SRC (x), 0),
5158 : pos_rtx)));
5159 :
5160 : split = find_split_point (&SET_SRC (x), insn, true);
5161 : if (split && split != &SET_SRC (x))
5162 : return split;
5163 : }
5164 : break;
5165 :
5166 517 : case SIGN_EXTEND:
5167 517 : inner = XEXP (SET_SRC (x), 0);
5168 :
5169 : /* We can't optimize if either mode is a partial integer
5170 : mode as we don't know how many bits are significant
5171 : in those modes. */
5172 517 : if (!is_int_mode (GET_MODE (inner), &inner_mode)
5173 511 : || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5174 : break;
5175 :
5176 511 : pos = 0;
5177 511 : len = GET_MODE_PRECISION (inner_mode);
5178 511 : unsignedp = false;
5179 511 : break;
5180 :
5181 12340 : case SIGN_EXTRACT:
5182 12340 : case ZERO_EXTRACT:
5183 12340 : if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5184 : &inner_mode)
5185 12044 : && CONST_INT_P (XEXP (SET_SRC (x), 1))
5186 12044 : && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5187 : {
5188 11616 : inner = XEXP (SET_SRC (x), 0);
5189 11616 : len = INTVAL (XEXP (SET_SRC (x), 1));
5190 11616 : pos = INTVAL (XEXP (SET_SRC (x), 2));
5191 :
5192 11616 : if (BITS_BIG_ENDIAN)
5193 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5194 11616 : unsignedp = (code == ZERO_EXTRACT);
5195 : }
5196 : break;
5197 :
5198 : default:
5199 : break;
5200 : }
5201 :
5202 478791 : if (len
5203 12127 : && known_subrange_p (pos, len,
5204 12127 : 0, GET_MODE_PRECISION (GET_MODE (inner)))
5205 490918 : && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5206 : {
5207 : /* For unsigned, we have a choice of a shift followed by an
5208 : AND or two shifts. Use two shifts for field sizes where the
5209 : constant might be too large. We assume here that we can
5210 : always at least get 8-bit constants in an AND insn, which is
5211 : true for every current RISC. */
5212 :
5213 12127 : if (unsignedp && len <= 8)
5214 : {
5215 4956 : unsigned HOST_WIDE_INT mask
5216 4956 : = (HOST_WIDE_INT_1U << len) - 1;
5217 4956 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5218 4956 : SUBST (SET_SRC (x),
5219 : gen_rtx_AND (mode,
5220 : gen_rtx_LSHIFTRT
5221 : (mode, gen_lowpart (mode, inner), pos_rtx),
5222 : gen_int_mode (mask, mode)));
5223 :
5224 4956 : split = find_split_point (&SET_SRC (x), insn, true);
5225 4956 : if (split && split != &SET_SRC (x))
5226 31707869 : return split;
5227 : }
5228 : else
5229 : {
5230 7171 : int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5231 7171 : int right_bits = GET_MODE_PRECISION (mode) - len;
5232 14342 : SUBST (SET_SRC (x),
5233 : gen_rtx_fmt_ee
5234 : (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5235 : gen_rtx_ASHIFT (mode,
5236 : gen_lowpart (mode, inner),
5237 : gen_int_shift_amount (mode, left_bits)),
5238 : gen_int_shift_amount (mode, right_bits)));
5239 :
5240 7171 : split = find_split_point (&SET_SRC (x), insn, true);
5241 7171 : if (split && split != &SET_SRC (x))
5242 31707869 : return split;
5243 : }
5244 : }
5245 :
5246 : /* See if this is a simple operation with a constant as the second
5247 : operand. It might be that this constant is out of range and hence
5248 : could be used as a split point. */
5249 466664 : if (BINARY_P (SET_SRC (x))
5250 204448 : && CONSTANT_P (XEXP (SET_SRC (x), 1))
5251 113794 : && (OBJECT_P (XEXP (SET_SRC (x), 0))
5252 37595 : || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5253 11243 : && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5254 78018 : return &XEXP (SET_SRC (x), 1);
5255 :
5256 : /* Finally, see if this is a simple operation with its first operand
5257 : not in a register. The operation might require this operand in a
5258 : register, so return it as a split point. We can always do this
5259 : because if the first operand were another operation, we would have
5260 : already found it as a split point. */
5261 388646 : if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5262 388646 : && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5263 120601 : return &XEXP (SET_SRC (x), 0);
5264 :
5265 : return 0;
5266 :
5267 1140429 : case AND:
5268 1140429 : case IOR:
5269 : /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5270 : it is better to write this as (not (ior A B)) so we can split it.
5271 : Similarly for IOR. */
5272 1140429 : if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5273 : {
5274 1870 : SUBST (*loc,
5275 : gen_rtx_NOT (GET_MODE (x),
5276 : gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5277 : GET_MODE (x),
5278 : XEXP (XEXP (x, 0), 0),
5279 : XEXP (XEXP (x, 1), 0))));
5280 935 : return find_split_point (loc, insn, set_src);
5281 : }
5282 :
5283 : /* Many RISC machines have a large set of logical insns. If the
5284 : second operand is a NOT, put it first so we will try to split the
5285 : other operand first. */
5286 1139494 : if (GET_CODE (XEXP (x, 1)) == NOT)
5287 : {
5288 5334 : rtx tem = XEXP (x, 0);
5289 5334 : SUBST (XEXP (x, 0), XEXP (x, 1));
5290 5334 : SUBST (XEXP (x, 1), tem);
5291 : }
5292 : /* Many targets have a `(and (not X) Y)` and/or `(ior (not X) Y)` instructions.
5293 : Split at that insns. However if this is
5294 : the SET_SRC, we likely do not have such an instruction and it's
5295 : worthless to try this split. */
5296 1139494 : if (!set_src && GET_CODE (XEXP (x, 0)) == NOT)
5297 : return loc;
5298 : break;
5299 :
5300 3286414 : case PLUS:
5301 3286414 : case MINUS:
5302 : /* Canonicalization can produce (minus A (mult B C)), where C is a
5303 : constant. It may be better to try splitting (plus (mult B -C) A)
5304 : instead if this isn't a multiply by a power of two. */
5305 198140 : if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5306 21515 : && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5307 3292201 : && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5308 : {
5309 5787 : machine_mode mode = GET_MODE (x);
5310 5787 : unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5311 5787 : HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5312 5787 : SUBST (*loc, gen_rtx_PLUS (mode,
5313 : gen_rtx_MULT (mode,
5314 : XEXP (XEXP (x, 1), 0),
5315 : gen_int_mode (other_int,
5316 : mode)),
5317 : XEXP (x, 0)));
5318 5787 : return find_split_point (loc, insn, set_src);
5319 : }
5320 :
5321 : /* Split at a multiply-accumulate instruction. However if this is
5322 : the SET_SRC, we likely do not have such an instruction and it's
5323 : worthless to try this split. */
5324 3280627 : if (!set_src
5325 1967140 : && (GET_CODE (XEXP (x, 0)) == MULT
5326 1853770 : || (GET_CODE (XEXP (x, 0)) == ASHIFT
5327 112001 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5328 : return loc;
5329 :
5330 : default:
5331 : break;
5332 : }
5333 :
5334 : /* Otherwise, select our actions depending on our rtx class. */
5335 26485173 : switch (GET_RTX_CLASS (code))
5336 : {
5337 1509335 : case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5338 1509335 : case RTX_TERNARY:
5339 1509335 : split = find_split_point (&XEXP (x, 2), insn, false);
5340 1509335 : if (split)
5341 : return split;
5342 : /* fall through */
5343 10434864 : case RTX_BIN_ARITH:
5344 10434864 : case RTX_COMM_ARITH:
5345 10434864 : case RTX_COMPARE:
5346 10434864 : case RTX_COMM_COMPARE:
5347 10434864 : split = find_split_point (&XEXP (x, 1), insn, false);
5348 10434864 : if (split)
5349 : return split;
5350 : /* fall through */
5351 10043164 : case RTX_UNARY:
5352 : /* Some machines have (and (shift ...) ...) insns. If X is not
5353 : an AND, but XEXP (X, 0) is, use it as our split point. */
5354 10043164 : if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5355 364587 : return &XEXP (x, 0);
5356 :
5357 9678577 : split = find_split_point (&XEXP (x, 0), insn, false);
5358 9678577 : if (split)
5359 5931342 : return split;
5360 : return loc;
5361 :
5362 : default:
5363 : /* Otherwise, we don't have a split point. */
5364 : return 0;
5365 : }
5366 : }
5367 :
5368 : /* Throughout X, replace FROM with TO, and return the result.
5369 : The result is TO if X is FROM;
5370 : otherwise the result is X, but its contents may have been modified.
5371 : If they were modified, a record was made in undobuf so that
5372 : undo_all will (among other things) return X to its original state.
5373 :
5374 : If the number of changes necessary is too much to record to undo,
5375 : the excess changes are not made, so the result is invalid.
5376 : The changes already made can still be undone.
5377 : undobuf.num_undo is incremented for such changes, so by testing that
5378 : the caller can tell whether the result is valid.
5379 :
5380 : `n_occurrences' is incremented each time FROM is replaced.
5381 :
5382 : IN_DEST is true if we are processing the SET_DEST of a SET.
5383 :
5384 : IN_COND is true if we are at the top level of a condition.
5385 :
5386 : UNIQUE_COPY is true if each substitution must be unique. We do this
5387 : by copying if `n_occurrences' is nonzero. */
5388 :
5389 : static rtx
5390 422924281 : subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5391 : {
5392 422924281 : enum rtx_code code = GET_CODE (x);
5393 422924281 : machine_mode op0_mode = VOIDmode;
5394 422924281 : const char *fmt;
5395 422924281 : int len, i;
5396 422924281 : rtx new_rtx;
5397 :
5398 : /* Two expressions are equal if they are identical copies of a shared
5399 : RTX or if they are both registers with the same register number
5400 : and mode. */
5401 :
5402 : #define COMBINE_RTX_EQUAL_P(X,Y) \
5403 : ((X) == (Y) \
5404 : || (REG_P (X) && REG_P (Y) \
5405 : && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5406 :
5407 : /* Do not substitute into clobbers of regs -- this will never result in
5408 : valid RTL. */
5409 422924281 : if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5410 : return x;
5411 :
5412 412350846 : if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5413 : {
5414 0 : n_occurrences++;
5415 0 : return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5416 : }
5417 :
5418 : /* If X and FROM are the same register but different modes, they
5419 : will not have been seen as equal above. However, the log links code
5420 : will make a LOG_LINKS entry for that case. If we do nothing, we
5421 : will try to rerecognize our original insn and, when it succeeds,
5422 : we will delete the feeding insn, which is incorrect.
5423 :
5424 : So force this insn not to match in this (rare) case. */
5425 91613985 : if (! in_dest && code == REG && REG_P (from)
5426 445164237 : && reg_overlap_mentioned_p (x, from))
5427 4706 : return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5428 :
5429 : /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5430 : of which may contain things that can be combined. */
5431 412346140 : if (code != MEM && code != LO_SUM && OBJECT_P (x))
5432 : return x;
5433 :
5434 : /* It is possible to have a subexpression appear twice in the insn.
5435 : Suppose that FROM is a register that appears within TO.
5436 : Then, after that subexpression has been scanned once by `subst',
5437 : the second time it is scanned, TO may be found. If we were
5438 : to scan TO here, we would find FROM within it and create a
5439 : self-referent rtl structure which is completely wrong. */
5440 220824257 : if (COMBINE_RTX_EQUAL_P (x, to))
5441 : return to;
5442 :
5443 : /* Parallel asm_operands need special attention because all of the
5444 : inputs are shared across the arms. Furthermore, unsharing the
5445 : rtl results in recognition failures. Failure to handle this case
5446 : specially can result in circular rtl.
5447 :
5448 : Solve this by doing a normal pass across the first entry of the
5449 : parallel, and only processing the SET_DESTs of the subsequent
5450 : entries. Ug. */
5451 :
5452 220681091 : if (code == PARALLEL
5453 13277592 : && GET_CODE (XVECEXP (x, 0, 0)) == SET
5454 11165851 : && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5455 : {
5456 21403 : new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5457 :
5458 : /* If this substitution failed, this whole thing fails. */
5459 21403 : if (GET_CODE (new_rtx) == CLOBBER
5460 0 : && XEXP (new_rtx, 0) == const0_rtx)
5461 : return new_rtx;
5462 :
5463 21403 : SUBST (XVECEXP (x, 0, 0), new_rtx);
5464 :
5465 104096 : for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5466 : {
5467 82693 : rtx dest = SET_DEST (XVECEXP (x, 0, i));
5468 :
5469 82693 : if (!REG_P (dest) && GET_CODE (dest) != PC)
5470 : {
5471 2945 : new_rtx = subst (dest, from, to, false, false, unique_copy);
5472 :
5473 : /* If this substitution failed, this whole thing fails. */
5474 2945 : if (GET_CODE (new_rtx) == CLOBBER
5475 0 : && XEXP (new_rtx, 0) == const0_rtx)
5476 : return new_rtx;
5477 :
5478 2945 : SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5479 : }
5480 : }
5481 : }
5482 : else
5483 : {
5484 220659688 : len = GET_RTX_LENGTH (code);
5485 220659688 : fmt = GET_RTX_FORMAT (code);
5486 :
5487 : /* We don't need to process a SET_DEST that is a register or PC, so
5488 : set up to skip this common case. All other cases where we want
5489 : to suppress replacing something inside a SET_SRC are handled via
5490 : the IN_DEST operand. */
5491 220659688 : if (code == SET
5492 48213959 : && (REG_P (SET_DEST (x))
5493 48213959 : || GET_CODE (SET_DEST (x)) == PC))
5494 220659688 : fmt = "ie";
5495 :
5496 : /* Trying to simplify the operands of a widening MULT is not likely
5497 : to create RTL matching a machine insn. */
5498 220659688 : if (code == MULT
5499 4898656 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5500 4898656 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5501 302631 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5502 302631 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5503 226199 : && REG_P (XEXP (XEXP (x, 0), 0))
5504 108227 : && REG_P (XEXP (XEXP (x, 1), 0))
5505 95590 : && from == to)
5506 : return x;
5507 :
5508 :
5509 : /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5510 : constant. */
5511 220600992 : if (fmt[0] == 'e')
5512 162554717 : op0_mode = GET_MODE (XEXP (x, 0));
5513 :
5514 653416076 : for (i = 0; i < len; i++)
5515 : {
5516 433798700 : if (fmt[i] == 'E')
5517 : {
5518 15741122 : int j;
5519 49902825 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5520 : {
5521 34293986 : if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5522 : {
5523 1612 : new_rtx = (unique_copy && n_occurrences
5524 302566 : ? copy_rtx (to) : to);
5525 302545 : n_occurrences++;
5526 : }
5527 : else
5528 : {
5529 33991441 : new_rtx = subst (XVECEXP (x, i, j), from, to,
5530 : false, false, unique_copy);
5531 :
5532 : /* If this substitution failed, this whole thing
5533 : fails. */
5534 33991441 : if (GET_CODE (new_rtx) == CLOBBER
5535 11029823 : && XEXP (new_rtx, 0) == const0_rtx)
5536 : return new_rtx;
5537 : }
5538 :
5539 34161703 : SUBST (XVECEXP (x, i, j), new_rtx);
5540 : }
5541 : }
5542 418057578 : else if (fmt[i] == 'e')
5543 : {
5544 : /* If this is a register being set, ignore it. */
5545 340967254 : new_rtx = XEXP (x, i);
5546 340967254 : if (in_dest
5547 340967254 : && i == 0
5548 5943096 : && (((code == SUBREG || code == ZERO_EXTRACT)
5549 365946 : && REG_P (new_rtx))
5550 5579586 : || code == STRICT_LOW_PART))
5551 : ;
5552 :
5553 340593095 : else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5554 : {
5555 : /* In general, don't install a subreg involving two
5556 : modes not tieable. It can worsen register
5557 : allocation, and can even make invalid reload
5558 : insns, since the reg inside may need to be copied
5559 : from in the outside mode, and that may be invalid
5560 : if it is an fp reg copied in integer mode.
5561 :
5562 : We allow an exception to this: It is valid if
5563 : it is inside another SUBREG and the mode of that
5564 : SUBREG and the mode of the inside of TO is
5565 : tieable. */
5566 :
5567 48414498 : if (GET_CODE (to) == SUBREG
5568 606647 : && !targetm.modes_tieable_p (GET_MODE (to),
5569 606647 : GET_MODE (SUBREG_REG (to)))
5570 48748235 : && ! (code == SUBREG
5571 28861 : && (targetm.modes_tieable_p
5572 28861 : (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5573 302575 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5574 :
5575 48111923 : if (code == SUBREG
5576 2606979 : && REG_P (to)
5577 97450 : && REGNO (to) < FIRST_PSEUDO_REGISTER
5578 48111928 : && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5579 5 : SUBREG_BYTE (x),
5580 5 : GET_MODE (x)) < 0)
5581 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5582 :
5583 48111923 : new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5584 48111923 : n_occurrences++;
5585 : }
5586 : else
5587 : /* If we are in a SET_DEST, suppress most cases unless we
5588 : have gone inside a MEM, in which case we want to
5589 : simplify the address. We assume here that things that
5590 : are actually part of the destination have their inner
5591 : parts in the first expression. This is true for SUBREG,
5592 : STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5593 : things aside from REG and MEM that should appear in a
5594 : SET_DEST. */
5595 335954510 : new_rtx = subst (XEXP (x, i), from, to,
5596 : (((in_dest
5597 5289757 : && (code == SUBREG || code == STRICT_LOW_PART
5598 5289757 : || code == ZERO_EXTRACT))
5599 292170824 : || code == SET)
5600 : && i == 0),
5601 292178597 : code == IF_THEN_ELSE && i == 0,
5602 : unique_copy);
5603 :
5604 : /* If we found that we will have to reject this combination,
5605 : indicate that by returning the CLOBBER ourselves, rather than
5606 : an expression containing it. This will speed things up as
5607 : well as prevent accidents where two CLOBBERs are considered
5608 : to be equal, thus producing an incorrect simplification. */
5609 :
5610 340664679 : if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5611 : return new_rtx;
5612 :
5613 340116173 : if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5614 : {
5615 31696 : machine_mode mode = GET_MODE (x);
5616 :
5617 63392 : x = simplify_subreg (GET_MODE (x), new_rtx,
5618 31696 : GET_MODE (SUBREG_REG (x)),
5619 31696 : SUBREG_BYTE (x));
5620 31696 : if (! x)
5621 2 : x = gen_rtx_CLOBBER (mode, const0_rtx);
5622 : }
5623 340084477 : else if (CONST_SCALAR_INT_P (new_rtx)
5624 : && (GET_CODE (x) == ZERO_EXTEND
5625 61534448 : || GET_CODE (x) == SIGN_EXTEND
5626 : || GET_CODE (x) == FLOAT
5627 : || GET_CODE (x) == UNSIGNED_FLOAT))
5628 : {
5629 136944 : x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5630 : new_rtx,
5631 68472 : GET_MODE (XEXP (x, 0)));
5632 68472 : if (!x)
5633 252 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5634 : }
5635 : /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5636 : etc. arguments, otherwise we can ICE before trying to recog
5637 : it. See PR104446. */
5638 340016005 : else if (CONST_SCALAR_INT_P (new_rtx)
5639 61465976 : && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5640 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5641 : else
5642 340016005 : SUBST (XEXP (x, i), new_rtx);
5643 : }
5644 : }
5645 : }
5646 :
5647 : /* Check if we are loading something from the constant pool via float
5648 : extension; in this case we would undo compress_float_constant
5649 : optimization and degenerate constant load to an immediate value. */
5650 219638779 : if (GET_CODE (x) == FLOAT_EXTEND
5651 309339 : && MEM_P (XEXP (x, 0))
5652 219702746 : && MEM_READONLY_P (XEXP (x, 0)))
5653 : {
5654 36611 : rtx tmp = avoid_constant_pool_reference (x);
5655 36611 : if (x != tmp)
5656 : return x;
5657 : }
5658 :
5659 : /* Try to simplify X. If the simplification changed the code, it is likely
5660 : that further simplification will help, so loop, but limit the number
5661 : of repetitions that will be performed. */
5662 :
5663 227738621 : for (i = 0; i < 4; i++)
5664 : {
5665 : /* If X is sufficiently simple, don't bother trying to do anything
5666 : with it. */
5667 227685043 : if (code != CONST_INT && code != REG && code != CLOBBER)
5668 227003980 : x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5669 :
5670 227685043 : if (GET_CODE (x) == code)
5671 : break;
5672 :
5673 8136323 : code = GET_CODE (x);
5674 :
5675 : /* We no longer know the original mode of operand 0 since we
5676 : have changed the form of X) */
5677 8136323 : op0_mode = VOIDmode;
5678 : }
5679 :
5680 : return x;
5681 : }
5682 :
5683 : /* If X is a commutative operation whose operands are not in the canonical
5684 : order, use substitutions to swap them. */
5685 :
5686 : static void
5687 663940537 : maybe_swap_commutative_operands (rtx x)
5688 : {
5689 663940537 : if (COMMUTATIVE_ARITH_P (x)
5690 663940537 : && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5691 : {
5692 3556822 : rtx temp = XEXP (x, 0);
5693 3556822 : SUBST (XEXP (x, 0), XEXP (x, 1));
5694 3556822 : SUBST (XEXP (x, 1), temp);
5695 : }
5696 :
5697 : /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5698 : (vec_merge (fma op1 op2 op3) op1 mask). */
5699 663940537 : if (GET_CODE (x) == VEC_MERGE
5700 1098027 : && GET_CODE (XEXP (x, 0)) == FMA)
5701 : {
5702 25271 : rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5703 25271 : rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5704 25271 : rtx masked_op = XEXP (x, 1);
5705 25271 : if (rtx_equal_p (masked_op, fma_op2))
5706 : {
5707 218 : if (GET_CODE (fma_op1) == NEG)
5708 : {
5709 : /* Keep the negate canonicalized to the first operand. */
5710 150 : fma_op1 = XEXP (fma_op1, 0);
5711 150 : SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5712 150 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5713 : }
5714 : else
5715 : {
5716 68 : SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5717 68 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5718 : }
5719 : }
5720 : }
5721 :
5722 663940537 : unsigned n_elts = 0;
5723 663940537 : if (GET_CODE (x) == VEC_MERGE
5724 1098027 : && CONST_INT_P (XEXP (x, 2))
5725 1430900 : && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5726 664655987 : && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5727 : /* Two operands have same precedence, then
5728 : first bit of mask select first operand. */
5729 681568 : || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5730 157313 : && !(UINTVAL (XEXP (x, 2)) & 1))))
5731 : {
5732 64988 : rtx temp = XEXP (x, 0);
5733 64988 : unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5734 64988 : unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5735 64988 : if (n_elts == HOST_BITS_PER_WIDE_INT)
5736 : mask = -1;
5737 : else
5738 64847 : mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5739 64988 : SUBST (XEXP (x, 0), XEXP (x, 1));
5740 64988 : SUBST (XEXP (x, 1), temp);
5741 64988 : SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5742 : }
5743 663940537 : }
5744 :
5745 : /* Simplify X, a piece of RTL. We just operate on the expression at the
5746 : outer level; call `subst' to simplify recursively. Return the new
5747 : expression.
5748 :
5749 : OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5750 : if we are inside a SET_DEST. IN_COND is true if we are at the top level
5751 : of a condition. */
5752 :
5753 : static rtx
5754 227650150 : combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5755 : {
5756 227650150 : enum rtx_code code = GET_CODE (x);
5757 227650150 : machine_mode mode = GET_MODE (x);
5758 227650150 : scalar_int_mode int_mode;
5759 227650150 : rtx temp;
5760 227650150 : int i;
5761 :
5762 : /* If this is a commutative operation, put a constant last and a complex
5763 : expression first. We don't need to do this for comparisons here. */
5764 227650150 : maybe_swap_commutative_operands (x);
5765 :
5766 : /* Try to fold this expression in case we have constants that weren't
5767 : present before. */
5768 227650150 : temp = 0;
5769 227650150 : switch (GET_RTX_CLASS (code))
5770 : {
5771 7504236 : case RTX_UNARY:
5772 7504236 : if (op0_mode == VOIDmode)
5773 164416 : op0_mode = GET_MODE (XEXP (x, 0));
5774 7504236 : temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5775 7504236 : break;
5776 18567866 : case RTX_COMPARE:
5777 18567866 : case RTX_COMM_COMPARE:
5778 18567866 : {
5779 18567866 : machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5780 18567866 : if (cmp_mode == VOIDmode)
5781 : {
5782 49080 : cmp_mode = GET_MODE (XEXP (x, 1));
5783 49080 : if (cmp_mode == VOIDmode)
5784 8154 : cmp_mode = op0_mode;
5785 : }
5786 18567866 : temp = simplify_relational_operation (code, mode, cmp_mode,
5787 : XEXP (x, 0), XEXP (x, 1));
5788 : }
5789 18567866 : break;
5790 89541384 : case RTX_COMM_ARITH:
5791 89541384 : case RTX_BIN_ARITH:
5792 89541384 : temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5793 89541384 : break;
5794 14763599 : case RTX_BITFIELD_OPS:
5795 14763599 : case RTX_TERNARY:
5796 14763599 : temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5797 : XEXP (x, 1), XEXP (x, 2));
5798 14763599 : break;
5799 : default:
5800 : break;
5801 : }
5802 :
5803 130377085 : if (temp)
5804 : {
5805 16826138 : x = temp;
5806 16826138 : code = GET_CODE (temp);
5807 16826138 : op0_mode = VOIDmode;
5808 16826138 : mode = GET_MODE (temp);
5809 : }
5810 :
5811 : /* If this is a simple operation applied to an IF_THEN_ELSE, try
5812 : applying it to the arms of the IF_THEN_ELSE. This often simplifies
5813 : things. Check for cases where both arms are testing the same
5814 : condition.
5815 :
5816 : Don't do anything if all operands are very simple. */
5817 :
5818 227650150 : if ((BINARY_P (x)
5819 107849214 : && ((!OBJECT_P (XEXP (x, 0))
5820 42369474 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5821 5304795 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5822 68453642 : || (!OBJECT_P (XEXP (x, 1))
5823 4995374 : && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5824 1961762 : && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5825 184942151 : || (UNARY_P (x)
5826 7382997 : && (!OBJECT_P (XEXP (x, 0))
5827 3338556 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5828 892940 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5829 : {
5830 45245431 : rtx cond, true_rtx, false_rtx;
5831 :
5832 45245431 : cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5833 45245431 : if (cond != 0
5834 : /* If everything is a comparison, what we have is highly unlikely
5835 : to be simpler, so don't use it. */
5836 4675105 : && ! (COMPARISON_P (x)
5837 1271512 : && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5838 : /* Similarly, if we end up with one of the expressions the same
5839 : as the original, it is certainly not simpler. */
5840 4499429 : && ! rtx_equal_p (x, true_rtx)
5841 49744860 : && ! rtx_equal_p (x, false_rtx))
5842 : {
5843 4499429 : rtx cop1 = const0_rtx;
5844 4499429 : enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5845 :
5846 4499429 : if (cond_code == NE && COMPARISON_P (cond))
5847 673004 : return x;
5848 :
5849 : /* Simplify the alternative arms; this may collapse the true and
5850 : false arms to store-flag values. Be careful to use copy_rtx
5851 : here since true_rtx or false_rtx might share RTL with x as a
5852 : result of the if_then_else_cond call above. */
5853 3826425 : true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5854 : false, false, false);
5855 3826425 : false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5856 : false, false, false);
5857 :
5858 : /* If true_rtx and false_rtx are not general_operands, an if_then_else
5859 : is unlikely to be simpler. */
5860 3826425 : if (general_operand (true_rtx, VOIDmode)
5861 3826425 : && general_operand (false_rtx, VOIDmode))
5862 : {
5863 1417981 : enum rtx_code reversed;
5864 :
5865 : /* Restarting if we generate a store-flag expression will cause
5866 : us to loop. Just drop through in this case. */
5867 :
5868 : /* If the result values are STORE_FLAG_VALUE and zero, we can
5869 : just make the comparison operation. */
5870 1417981 : if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5871 628786 : x = simplify_gen_relational (cond_code, mode, VOIDmode,
5872 : cond, cop1);
5873 515567 : else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5874 789195 : && ((reversed = reversed_comparison_code_parts
5875 457754 : (cond_code, cond, cop1, NULL))
5876 : != UNKNOWN))
5877 457754 : x = simplify_gen_relational (reversed, mode, VOIDmode,
5878 : cond, cop1);
5879 :
5880 : /* Likewise, we can make the negate of a comparison operation
5881 : if the result values are - STORE_FLAG_VALUE and zero. */
5882 331441 : else if (CONST_INT_P (true_rtx)
5883 232273 : && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5884 46666 : && false_rtx == const0_rtx)
5885 44775 : x = simplify_gen_unary (NEG, mode,
5886 : simplify_gen_relational (cond_code,
5887 : mode, VOIDmode,
5888 : cond, cop1),
5889 : mode);
5890 286666 : else if (CONST_INT_P (false_rtx)
5891 223861 : && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5892 23886 : && true_rtx == const0_rtx
5893 286666 : && ((reversed = reversed_comparison_code_parts
5894 21420 : (cond_code, cond, cop1, NULL))
5895 : != UNKNOWN))
5896 21417 : x = simplify_gen_unary (NEG, mode,
5897 : simplify_gen_relational (reversed,
5898 : mode, VOIDmode,
5899 : cond, cop1),
5900 : mode);
5901 :
5902 1417981 : code = GET_CODE (x);
5903 1417981 : op0_mode = VOIDmode;
5904 : }
5905 : }
5906 : }
5907 :
5908 : /* First see if we can apply the inverse distributive law. */
5909 226977146 : if (code == PLUS || code == MINUS
5910 226977146 : || code == AND || code == IOR || code == XOR)
5911 : {
5912 50626278 : x = apply_distributive_law (x);
5913 50626278 : code = GET_CODE (x);
5914 50626278 : op0_mode = VOIDmode;
5915 : }
5916 :
5917 : /* If CODE is an associative operation not otherwise handled, see if we
5918 : can associate some operands. This can win if they are constants or
5919 : if they are logically related (i.e. (a & b) & a). */
5920 226977146 : if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5921 : || code == AND || code == IOR || code == XOR
5922 : || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5923 55123813 : && ((INTEGRAL_MODE_P (mode) && code != DIV)
5924 4747629 : || (flag_associative_math && FLOAT_MODE_P (mode))))
5925 : {
5926 51016964 : if (GET_CODE (XEXP (x, 0)) == code)
5927 : {
5928 3993299 : rtx other = XEXP (XEXP (x, 0), 0);
5929 3993299 : rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5930 3993299 : rtx inner_op1 = XEXP (x, 1);
5931 3993299 : rtx inner;
5932 :
5933 : /* Make sure we pass the constant operand if any as the second
5934 : one if this is a commutative operation. */
5935 3993299 : if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5936 : std::swap (inner_op0, inner_op1);
5937 3993299 : inner = simplify_binary_operation (code == MINUS ? PLUS
5938 3889450 : : code == DIV ? MULT
5939 : : code,
5940 : mode, inner_op0, inner_op1);
5941 :
5942 : /* For commutative operations, try the other pair if that one
5943 : didn't simplify. */
5944 3993299 : if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5945 : {
5946 3859779 : other = XEXP (XEXP (x, 0), 1);
5947 3859779 : inner = simplify_binary_operation (code, mode,
5948 : XEXP (XEXP (x, 0), 0),
5949 : XEXP (x, 1));
5950 : }
5951 :
5952 3960510 : if (inner)
5953 237298 : return simplify_gen_binary (code, mode, other, inner);
5954 : }
5955 : }
5956 :
5957 : /* A little bit of algebraic simplification here. */
5958 226739848 : switch (code)
5959 : {
5960 22742601 : case PREFETCH:
5961 : /* A prefetch reaches memory through an address, and targets recognize
5962 : that address with the same predicates they use for a MEM, so it
5963 : needs the same treatment. */
5964 22742601 : case MEM:
5965 : /* Ensure that our address has any ASHIFTs converted to MULT in case
5966 : address-recognizing predicates are called later. */
5967 22742601 : temp = make_compound_operation (XEXP (x, 0), MEM);
5968 22742601 : SUBST (XEXP (x, 0), temp);
5969 22742601 : break;
5970 :
5971 9719297 : case SUBREG:
5972 9719297 : if (op0_mode == VOIDmode)
5973 159526 : op0_mode = GET_MODE (SUBREG_REG (x));
5974 :
5975 : /* See if this can be moved to simplify_subreg. */
5976 9719297 : if (CONSTANT_P (SUBREG_REG (x))
5977 45608 : && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5978 : /* Don't call gen_lowpart if the inner mode
5979 : is VOIDmode and we cannot simplify it, as SUBREG without
5980 : inner mode is invalid. */
5981 9742101 : && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5982 0 : || gen_lowpart_common (mode, SUBREG_REG (x))))
5983 22804 : return gen_lowpart (mode, SUBREG_REG (x));
5984 :
5985 9696493 : if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5986 : break;
5987 9696493 : {
5988 9696493 : rtx temp;
5989 19392986 : temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5990 9696493 : SUBREG_BYTE (x));
5991 9696493 : if (temp)
5992 227650150 : return temp;
5993 :
5994 : /* If op is known to have all lower bits zero, the result is zero. */
5995 9050211 : scalar_int_mode int_mode, int_op0_mode;
5996 9050211 : if (!in_dest
5997 5452283 : && is_a <scalar_int_mode> (mode, &int_mode)
5998 5325835 : && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5999 5325835 : && (GET_MODE_PRECISION (int_mode)
6000 5325835 : < GET_MODE_PRECISION (int_op0_mode))
6001 4776385 : && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
6002 : SUBREG_BYTE (x))
6003 4282272 : && HWI_COMPUTABLE_MODE_P (int_op0_mode)
6004 4085959 : && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
6005 4085959 : & GET_MODE_MASK (int_mode)) == 0)
6006 9051201 : && !side_effects_p (SUBREG_REG (x)))
6007 990 : return CONST0_RTX (int_mode);
6008 : }
6009 :
6010 : /* Don't change the mode of the MEM if that would change the meaning
6011 : of the address. */
6012 9049221 : if (MEM_P (SUBREG_REG (x))
6013 9049221 : && (MEM_VOLATILE_P (SUBREG_REG (x))
6014 69029 : || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
6015 69063 : MEM_ADDR_SPACE (SUBREG_REG (x)))))
6016 45324 : return gen_rtx_CLOBBER (mode, const0_rtx);
6017 :
6018 : /* Note that we cannot do any narrowing for non-constants since
6019 : we might have been counting on using the fact that some bits were
6020 : zero. We now do this in the SET. */
6021 :
6022 : break;
6023 :
6024 385242 : case NEG:
6025 385242 : temp = expand_compound_operation (XEXP (x, 0));
6026 :
6027 : /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6028 : replaced by (lshiftrt X C). This will convert
6029 : (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6030 :
6031 385242 : if (GET_CODE (temp) == ASHIFTRT
6032 15002 : && CONST_INT_P (XEXP (temp, 1))
6033 415172 : && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
6034 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
6035 0 : INTVAL (XEXP (temp, 1)));
6036 :
6037 : /* If X has only a single bit that might be nonzero, say, bit I, convert
6038 : (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6039 : MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6040 : (sign_extract X 1 Y). But only do this if TEMP isn't a register
6041 : or a SUBREG of one since we'd be making the expression more
6042 : complex if it was just a register. */
6043 :
6044 385242 : if (!REG_P (temp)
6045 186156 : && ! (GET_CODE (temp) == SUBREG
6046 19705 : && REG_P (SUBREG_REG (temp)))
6047 227792124 : && is_a <scalar_int_mode> (mode, &int_mode)
6048 527216 : && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6049 : {
6050 67097 : rtx temp1 = simplify_shift_const
6051 67097 : (NULL_RTX, ASHIFTRT, int_mode,
6052 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6053 67097 : GET_MODE_PRECISION (int_mode) - 1 - i),
6054 67097 : GET_MODE_PRECISION (int_mode) - 1 - i);
6055 :
6056 : /* If all we did was surround TEMP with the two shifts, we
6057 : haven't improved anything, so don't use it. Otherwise,
6058 : we are better off with TEMP1. */
6059 67097 : if (GET_CODE (temp1) != ASHIFTRT
6060 66659 : || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6061 66621 : || XEXP (XEXP (temp1, 0), 0) != temp)
6062 6525 : return temp1;
6063 : }
6064 : break;
6065 :
6066 9780 : case TRUNCATE:
6067 : /* We can't handle truncation to a partial integer mode here
6068 : because we don't know the real bitsize of the partial
6069 : integer mode. */
6070 9780 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6071 : break;
6072 :
6073 9780 : if (HWI_COMPUTABLE_MODE_P (mode))
6074 0 : SUBST (XEXP (x, 0),
6075 : force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6076 : GET_MODE_MASK (mode), false));
6077 :
6078 : /* We can truncate a constant value and return it. */
6079 9780 : {
6080 9780 : poly_int64 c;
6081 9780 : if (poly_int_rtx_p (XEXP (x, 0), &c))
6082 0 : return gen_int_mode (c, mode);
6083 : }
6084 :
6085 : /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6086 : whose value is a comparison can be replaced with a subreg if
6087 : STORE_FLAG_VALUE permits. */
6088 9780 : if (HWI_COMPUTABLE_MODE_P (mode)
6089 0 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6090 0 : && (temp = get_last_value (XEXP (x, 0)))
6091 0 : && COMPARISON_P (temp)
6092 9780 : && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6093 0 : return gen_lowpart (mode, XEXP (x, 0));
6094 : break;
6095 :
6096 5350 : case CONST:
6097 : /* (const (const X)) can become (const X). Do it this way rather than
6098 : returning the inner CONST since CONST can be shared with a
6099 : REG_EQUAL note. */
6100 5350 : if (GET_CODE (XEXP (x, 0)) == CONST)
6101 0 : SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6102 : break;
6103 :
6104 : case LO_SUM:
6105 : /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6106 : can add in an offset. find_split_point will split this address up
6107 : again if it doesn't match. */
6108 : if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6109 : && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6110 : return XEXP (x, 1);
6111 : break;
6112 :
6113 34223873 : case PLUS:
6114 : /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6115 : when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6116 : bit-field and can be replaced by either a sign_extend or a
6117 : sign_extract. The `and' may be a zero_extend and the two
6118 : <c>, -<c> constants may be reversed. */
6119 34223873 : if (GET_CODE (XEXP (x, 0)) == XOR
6120 34223873 : && is_a <scalar_int_mode> (mode, &int_mode)
6121 13597 : && CONST_INT_P (XEXP (x, 1))
6122 3465 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6123 3009 : && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6124 77 : && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6125 2 : || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6126 39 : && HWI_COMPUTABLE_MODE_P (int_mode)
6127 34223912 : && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6128 0 : && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6129 0 : && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6130 0 : == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6131 39 : || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6132 0 : && known_eq ((GET_MODE_PRECISION
6133 : (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6134 : (unsigned int) i + 1))))
6135 0 : return simplify_shift_const
6136 0 : (NULL_RTX, ASHIFTRT, int_mode,
6137 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6138 : XEXP (XEXP (XEXP (x, 0), 0), 0),
6139 0 : GET_MODE_PRECISION (int_mode) - (i + 1)),
6140 0 : GET_MODE_PRECISION (int_mode) - (i + 1));
6141 :
6142 : /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6143 : can become (ashiftrt (ashift (xor x 1) C) C) where C is
6144 : the bitsize of the mode - 1. This allows simplification of
6145 : "a = (b & 8) == 0;" */
6146 34223873 : if (XEXP (x, 1) == constm1_rtx
6147 738638 : && !REG_P (XEXP (x, 0))
6148 326079 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6149 33683 : && REG_P (SUBREG_REG (XEXP (x, 0))))
6150 34512737 : && is_a <scalar_int_mode> (mode, &int_mode)
6151 34522463 : && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6152 9726 : return simplify_shift_const
6153 9726 : (NULL_RTX, ASHIFTRT, int_mode,
6154 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6155 : gen_rtx_XOR (int_mode, XEXP (x, 0),
6156 : const1_rtx),
6157 9726 : GET_MODE_PRECISION (int_mode) - 1),
6158 19452 : GET_MODE_PRECISION (int_mode) - 1);
6159 :
6160 : /* If we are adding two things that have no bits in common, convert
6161 : the addition into an IOR. This will often be further simplified,
6162 : for example in cases like ((a & 1) + (a & 2)), which can
6163 : become a & 3. */
6164 :
6165 34214147 : if (HWI_COMPUTABLE_MODE_P (mode)
6166 30325503 : && (nonzero_bits (XEXP (x, 0), mode)
6167 30325503 : & nonzero_bits (XEXP (x, 1), mode)) == 0)
6168 : {
6169 : /* Try to simplify the expression further. */
6170 646170 : rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6171 646170 : temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6172 :
6173 : /* If we could, great. If not, do not go ahead with the IOR
6174 : replacement, since PLUS appears in many special purpose
6175 : address arithmetic instructions. */
6176 646170 : if (GET_CODE (temp) != CLOBBER
6177 646170 : && (GET_CODE (temp) != IOR
6178 640931 : || ((XEXP (temp, 0) != XEXP (x, 0)
6179 637677 : || XEXP (temp, 1) != XEXP (x, 1))
6180 3254 : && (XEXP (temp, 0) != XEXP (x, 1)
6181 0 : || XEXP (temp, 1) != XEXP (x, 0)))))
6182 : return temp;
6183 : }
6184 :
6185 : /* Canonicalize x + x into x << 1. */
6186 34205654 : if (GET_MODE_CLASS (mode) == MODE_INT
6187 30639906 : && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6188 34208823 : && !side_effects_p (XEXP (x, 0)))
6189 3157 : return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6190 :
6191 : break;
6192 :
6193 4126836 : case MINUS:
6194 : /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6195 : (and <foo> (const_int pow2-1)) */
6196 4126836 : if (is_a <scalar_int_mode> (mode, &int_mode)
6197 3487536 : && GET_CODE (XEXP (x, 1)) == AND
6198 99239 : && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6199 96527 : && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6200 48120 : && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6201 0 : return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6202 0 : -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6203 : break;
6204 :
6205 3227412 : case MULT:
6206 : /* If we have (mult (plus A B) C), apply the distributive law and then
6207 : the inverse distributive law to see if things simplify. This
6208 : occurs mostly in addresses, often when unrolling loops. */
6209 :
6210 3227412 : if (GET_CODE (XEXP (x, 0)) == PLUS)
6211 : {
6212 279218 : rtx result = distribute_and_simplify_rtx (x, 0);
6213 279218 : if (result)
6214 : return result;
6215 : }
6216 :
6217 : /* Try simplify a*(b/c) as (a*b)/c. */
6218 3226600 : if (FLOAT_MODE_P (mode) && flag_associative_math
6219 203407 : && GET_CODE (XEXP (x, 0)) == DIV)
6220 : {
6221 244 : rtx tem = simplify_binary_operation (MULT, mode,
6222 : XEXP (XEXP (x, 0), 0),
6223 : XEXP (x, 1));
6224 244 : if (tem)
6225 32 : return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6226 : }
6227 : break;
6228 :
6229 119977 : case UDIV:
6230 : /* If this is a divide by a power of two, treat it as a shift if
6231 : its first operand is a shift. */
6232 119977 : if (is_a <scalar_int_mode> (mode, &int_mode)
6233 119977 : && CONST_INT_P (XEXP (x, 1))
6234 1999 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6235 0 : && (GET_CODE (XEXP (x, 0)) == ASHIFT
6236 0 : || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6237 0 : || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6238 0 : || GET_CODE (XEXP (x, 0)) == ROTATE
6239 0 : || GET_CODE (XEXP (x, 0)) == ROTATERT))
6240 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6241 0 : XEXP (x, 0), i);
6242 : break;
6243 :
6244 18499882 : case EQ: case NE:
6245 18499882 : case GT: case GTU: case GE: case GEU:
6246 18499882 : case LT: case LTU: case LE: case LEU:
6247 18499882 : case UNEQ: case LTGT:
6248 18499882 : case UNGT: case UNGE:
6249 18499882 : case UNLT: case UNLE:
6250 18499882 : case UNORDERED: case ORDERED:
6251 : /* If the first operand is a condition code, we can't do anything
6252 : with it. */
6253 18499882 : if (GET_CODE (XEXP (x, 0)) == COMPARE
6254 18499882 : || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6255 : {
6256 13860253 : rtx op0 = XEXP (x, 0);
6257 13860253 : rtx op1 = XEXP (x, 1);
6258 13860253 : enum rtx_code new_code;
6259 :
6260 13860253 : if (GET_CODE (op0) == COMPARE)
6261 0 : op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6262 :
6263 : /* Simplify our comparison, if possible. */
6264 13860253 : new_code = simplify_comparison (code, &op0, &op1);
6265 :
6266 : /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6267 : if only the low-order bit is possibly nonzero in X (such as when
6268 : X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6269 : (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6270 : known to be either 0 or -1, NE becomes a NEG and EQ becomes
6271 : (plus X 1).
6272 :
6273 : Remove any ZERO_EXTRACT we made when thinking this was a
6274 : comparison. It may now be simpler to use, e.g., an AND. If a
6275 : ZERO_EXTRACT is indeed appropriate, it will be placed back by
6276 : the call to make_compound_operation in the SET case.
6277 :
6278 : Don't apply these optimizations if the caller would
6279 : prefer a comparison rather than a value.
6280 : E.g., for the condition in an IF_THEN_ELSE most targets need
6281 : an explicit comparison. */
6282 :
6283 13860253 : if (in_cond)
6284 : ;
6285 :
6286 2191366 : else if (STORE_FLAG_VALUE == 1
6287 : && new_code == NE
6288 2633118 : && is_int_mode (mode, &int_mode)
6289 441967 : && op1 == const0_rtx
6290 229508 : && int_mode == GET_MODE (op0)
6291 2285668 : && nonzero_bits (op0, int_mode) == 1)
6292 215 : return gen_lowpart (int_mode,
6293 473984 : expand_compound_operation (op0));
6294 :
6295 2191151 : else if (STORE_FLAG_VALUE == 1
6296 : && new_code == NE
6297 2631874 : && is_int_mode (mode, &int_mode)
6298 441752 : && op1 == const0_rtx
6299 229293 : && int_mode == GET_MODE (op0)
6300 2285238 : && (num_sign_bit_copies (op0, int_mode)
6301 94087 : == GET_MODE_PRECISION (int_mode)))
6302 : {
6303 1029 : op0 = expand_compound_operation (op0);
6304 1029 : return simplify_gen_unary (NEG, int_mode,
6305 1029 : gen_lowpart (int_mode, op0),
6306 1029 : int_mode);
6307 : }
6308 :
6309 2190122 : else if (STORE_FLAG_VALUE == 1
6310 : && new_code == EQ
6311 2525558 : && is_int_mode (mode, &int_mode)
6312 337775 : && op1 == const0_rtx
6313 136503 : && int_mode == GET_MODE (op0)
6314 2234613 : && nonzero_bits (op0, int_mode) == 1)
6315 : {
6316 2339 : op0 = expand_compound_operation (op0);
6317 2339 : return simplify_gen_binary (XOR, int_mode,
6318 2339 : gen_lowpart (int_mode, op0),
6319 2339 : const1_rtx);
6320 : }
6321 :
6322 2187783 : else if (STORE_FLAG_VALUE == 1
6323 : && new_code == EQ
6324 14191533 : && is_int_mode (mode, &int_mode)
6325 335436 : && op1 == const0_rtx
6326 134164 : && int_mode == GET_MODE (op0)
6327 2229935 : && (num_sign_bit_copies (op0, int_mode)
6328 42152 : == GET_MODE_PRECISION (int_mode)))
6329 : {
6330 573 : op0 = expand_compound_operation (op0);
6331 573 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6332 : }
6333 :
6334 : /* If STORE_FLAG_VALUE is -1, we have cases similar to
6335 : those above. */
6336 13856097 : if (in_cond)
6337 : ;
6338 :
6339 13856097 : else if (STORE_FLAG_VALUE == -1
6340 : && new_code == NE
6341 : && is_int_mode (mode, &int_mode)
6342 : && op1 == const0_rtx
6343 : && int_mode == GET_MODE (op0)
6344 : && (num_sign_bit_copies (op0, int_mode)
6345 : == GET_MODE_PRECISION (int_mode)))
6346 : return gen_lowpart (int_mode, expand_compound_operation (op0));
6347 :
6348 13856097 : else if (STORE_FLAG_VALUE == -1
6349 : && new_code == NE
6350 : && is_int_mode (mode, &int_mode)
6351 : && op1 == const0_rtx
6352 : && int_mode == GET_MODE (op0)
6353 : && nonzero_bits (op0, int_mode) == 1)
6354 : {
6355 : op0 = expand_compound_operation (op0);
6356 : return simplify_gen_unary (NEG, int_mode,
6357 : gen_lowpart (int_mode, op0),
6358 : int_mode);
6359 : }
6360 :
6361 13856097 : else if (STORE_FLAG_VALUE == -1
6362 : && new_code == EQ
6363 : && is_int_mode (mode, &int_mode)
6364 : && op1 == const0_rtx
6365 : && int_mode == GET_MODE (op0)
6366 : && (num_sign_bit_copies (op0, int_mode)
6367 : == GET_MODE_PRECISION (int_mode)))
6368 : {
6369 : op0 = expand_compound_operation (op0);
6370 : return simplify_gen_unary (NOT, int_mode,
6371 : gen_lowpart (int_mode, op0),
6372 : int_mode);
6373 : }
6374 :
6375 : /* If X is 0/1, (eq X 0) is X-1. */
6376 13856097 : else if (STORE_FLAG_VALUE == -1
6377 : && new_code == EQ
6378 : && is_int_mode (mode, &int_mode)
6379 : && op1 == const0_rtx
6380 : && int_mode == GET_MODE (op0)
6381 : && nonzero_bits (op0, int_mode) == 1)
6382 : {
6383 : op0 = expand_compound_operation (op0);
6384 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6385 : }
6386 :
6387 : /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6388 : one bit that might be nonzero, we can convert (ne x 0) to
6389 : (ashift x c) where C puts the bit in the sign bit. Remove any
6390 : AND with STORE_FLAG_VALUE when we are done, since we are only
6391 : going to test the sign bit. */
6392 13856097 : if (new_code == NE
6393 14292501 : && is_int_mode (mode, &int_mode)
6394 440793 : && HWI_COMPUTABLE_MODE_P (int_mode)
6395 436404 : && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6396 0 : && op1 == const0_rtx
6397 0 : && int_mode == GET_MODE (op0)
6398 13856097 : && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6399 : {
6400 0 : x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6401 : expand_compound_operation (op0),
6402 0 : GET_MODE_PRECISION (int_mode) - 1 - i);
6403 0 : if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6404 0 : return XEXP (x, 0);
6405 : else
6406 : return x;
6407 : }
6408 :
6409 : /* If the code changed, return a whole new comparison.
6410 : We also need to avoid using SUBST in cases where
6411 : simplify_comparison has widened a comparison with a CONST_INT,
6412 : since in that case the wider CONST_INT may fail the sanity
6413 : checks in do_SUBST. */
6414 13856097 : if (new_code != code
6415 13393930 : || (CONST_INT_P (op1)
6416 7584285 : && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6417 8936 : && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6418 469828 : return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6419 :
6420 : /* Otherwise, keep this operation, but maybe change its operands.
6421 : This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6422 13386269 : SUBST (XEXP (x, 0), op0);
6423 13386269 : SUBST (XEXP (x, 1), op1);
6424 : }
6425 : break;
6426 :
6427 13509595 : case IF_THEN_ELSE:
6428 13509595 : return simplify_if_then_else (x);
6429 :
6430 4837162 : case ZERO_EXTRACT:
6431 4837162 : case SIGN_EXTRACT:
6432 4837162 : case ZERO_EXTEND:
6433 4837162 : case SIGN_EXTEND:
6434 : /* If we are processing SET_DEST, we are done. */
6435 4837162 : if (in_dest)
6436 : return x;
6437 :
6438 4834420 : return expand_compound_operation (x);
6439 :
6440 47854523 : case SET:
6441 47854523 : return simplify_set (x);
6442 :
6443 11435263 : case AND:
6444 11435263 : case IOR:
6445 11435263 : return simplify_logical (x);
6446 :
6447 13502870 : case ASHIFT:
6448 13502870 : case LSHIFTRT:
6449 13502870 : case ASHIFTRT:
6450 13502870 : case ROTATE:
6451 13502870 : case ROTATERT:
6452 : /* If this is a shift by a constant amount, simplify it. */
6453 13502870 : if (CONST_INT_P (XEXP (x, 1)))
6454 13005419 : return simplify_shift_const (x, code, mode, XEXP (x, 0),
6455 13005419 : INTVAL (XEXP (x, 1)));
6456 :
6457 : else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6458 : SUBST (XEXP (x, 1),
6459 : force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6460 : (HOST_WIDE_INT_1U
6461 : << exact_log2 (GET_MODE_UNIT_BITSIZE
6462 : (GET_MODE (x)))) - 1, false));
6463 : break;
6464 2133455 : case VEC_SELECT:
6465 2133455 : {
6466 2133455 : rtx trueop0 = XEXP (x, 0);
6467 2133455 : mode = GET_MODE (trueop0);
6468 2133455 : rtx trueop1 = XEXP (x, 1);
6469 : /* If we select a low-part subreg, return that. */
6470 2133455 : if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6471 : {
6472 1194 : rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6473 1194 : if (new_rtx != NULL_RTX)
6474 1194 : return new_rtx;
6475 : }
6476 : }
6477 :
6478 : default:
6479 : break;
6480 : }
6481 :
6482 : return x;
6483 : }
6484 :
6485 : /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6486 :
6487 : static rtx
6488 13509595 : simplify_if_then_else (rtx x)
6489 : {
6490 13509595 : machine_mode mode = GET_MODE (x);
6491 13509595 : rtx cond = XEXP (x, 0);
6492 13509595 : rtx true_rtx = XEXP (x, 1);
6493 13509595 : rtx false_rtx = XEXP (x, 2);
6494 13509595 : enum rtx_code true_code = GET_CODE (cond);
6495 13509595 : bool comparison_p = COMPARISON_P (cond);
6496 13509595 : rtx temp;
6497 13509595 : int i;
6498 13509595 : enum rtx_code false_code;
6499 13509595 : rtx reversed;
6500 13509595 : scalar_int_mode int_mode, inner_mode;
6501 :
6502 : /* Simplify storing of the truth value. */
6503 13509595 : if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6504 0 : return simplify_gen_relational (true_code, mode, VOIDmode,
6505 0 : XEXP (cond, 0), XEXP (cond, 1));
6506 :
6507 : /* Also when the truth value has to be reversed. */
6508 13509050 : if (comparison_p
6509 13509050 : && true_rtx == const0_rtx && false_rtx == const_true_rtx
6510 0 : && (reversed = reversed_comparison (cond, mode)))
6511 : return reversed;
6512 :
6513 : /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6514 : in it is being compared against certain values. Get the true and false
6515 : comparisons and see if that says anything about the value of each arm. */
6516 :
6517 13509595 : if (comparison_p
6518 13509050 : && ((false_code = reversed_comparison_code (cond, NULL))
6519 : != UNKNOWN)
6520 26861770 : && REG_P (XEXP (cond, 0)))
6521 : {
6522 8351622 : HOST_WIDE_INT nzb;
6523 8351622 : rtx from = XEXP (cond, 0);
6524 8351622 : rtx true_val = XEXP (cond, 1);
6525 8351622 : rtx false_val = true_val;
6526 8351622 : bool swapped = false;
6527 :
6528 : /* If FALSE_CODE is EQ, swap the codes and arms. */
6529 :
6530 8351622 : if (false_code == EQ)
6531 : {
6532 3027503 : swapped = true, true_code = EQ, false_code = NE;
6533 3027503 : std::swap (true_rtx, false_rtx);
6534 : }
6535 :
6536 8351622 : scalar_int_mode from_mode;
6537 8351622 : if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6538 : {
6539 : /* If we are comparing against zero and the expression being
6540 : tested has only a single bit that might be nonzero, that is
6541 : its value when it is not equal to zero. Similarly if it is
6542 : known to be -1 or 0. */
6543 6920266 : if (true_code == EQ
6544 5024868 : && true_val == const0_rtx
6545 9012453 : && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6546 : {
6547 239439 : false_code = EQ;
6548 239439 : false_val = gen_int_mode (nzb, from_mode);
6549 : }
6550 6680827 : else if (true_code == EQ
6551 4785429 : && true_val == const0_rtx
6552 8533575 : && (num_sign_bit_copies (from, from_mode)
6553 1852748 : == GET_MODE_PRECISION (from_mode)))
6554 : {
6555 720 : false_code = EQ;
6556 720 : false_val = constm1_rtx;
6557 : }
6558 : }
6559 :
6560 : /* Now simplify an arm if we know the value of the register in the
6561 : branch and it is used in the arm. Be careful due to the potential
6562 : of locally-shared RTL. */
6563 :
6564 8351622 : if (reg_mentioned_p (from, true_rtx))
6565 320214 : true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6566 : from, true_val),
6567 : pc_rtx, pc_rtx, false, false, false);
6568 8351622 : if (reg_mentioned_p (from, false_rtx))
6569 138738 : false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6570 : from, false_val),
6571 : pc_rtx, pc_rtx, false, false, false);
6572 :
6573 13675741 : SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6574 13675741 : SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6575 :
6576 8351622 : true_rtx = XEXP (x, 1);
6577 8351622 : false_rtx = XEXP (x, 2);
6578 8351622 : true_code = GET_CODE (cond);
6579 : }
6580 :
6581 : /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6582 : reversed, do so to avoid needing two sets of patterns for
6583 : subtract-and-branch insns. Similarly if we have a constant in the true
6584 : arm, the false arm is the same as the first operand of the comparison, or
6585 : the false arm is more complicated than the true arm. */
6586 :
6587 13509595 : if (comparison_p
6588 13509050 : && reversed_comparison_code (cond, NULL) != UNKNOWN
6589 26861770 : && (true_rtx == pc_rtx
6590 13352175 : || (CONSTANT_P (true_rtx)
6591 10942909 : && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6592 13311794 : || true_rtx == const0_rtx
6593 13308772 : || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6594 13240233 : || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6595 15023 : && !OBJECT_P (false_rtx))
6596 13237756 : || reg_mentioned_p (true_rtx, false_rtx)
6597 13237661 : || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6598 : {
6599 171562 : SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6600 171562 : SUBST (XEXP (x, 1), false_rtx);
6601 171562 : SUBST (XEXP (x, 2), true_rtx);
6602 :
6603 171562 : std::swap (true_rtx, false_rtx);
6604 171562 : cond = XEXP (x, 0);
6605 :
6606 : /* It is possible that the conditional has been simplified out. */
6607 171562 : true_code = GET_CODE (cond);
6608 171562 : comparison_p = COMPARISON_P (cond);
6609 : }
6610 :
6611 : /* If the two arms are identical, we don't need the comparison. */
6612 :
6613 13509595 : if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6614 : return true_rtx;
6615 :
6616 : /* Convert a == b ? b : a to "a". */
6617 3973283 : if (true_code == EQ && ! side_effects_p (cond)
6618 3954318 : && !HONOR_NANS (mode)
6619 3951240 : && rtx_equal_p (XEXP (cond, 0), false_rtx)
6620 13510048 : && rtx_equal_p (XEXP (cond, 1), true_rtx))
6621 : return false_rtx;
6622 4899593 : else if (true_code == NE && ! side_effects_p (cond)
6623 4850870 : && !HONOR_NANS (mode)
6624 4697103 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6625 13577622 : && rtx_equal_p (XEXP (cond, 1), false_rtx))
6626 : return true_rtx;
6627 :
6628 : /* Look for cases where we have (abs x) or (neg (abs X)). */
6629 :
6630 13509577 : if (GET_MODE_CLASS (mode) == MODE_INT
6631 2217103 : && comparison_p
6632 2217083 : && XEXP (cond, 1) == const0_rtx
6633 1693308 : && GET_CODE (false_rtx) == NEG
6634 161 : && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6635 24 : && rtx_equal_p (true_rtx, XEXP (cond, 0))
6636 13509601 : && ! side_effects_p (true_rtx))
6637 24 : switch (true_code)
6638 : {
6639 24 : case GT:
6640 24 : case GE:
6641 24 : return simplify_gen_unary (ABS, mode, true_rtx, mode);
6642 0 : case LT:
6643 0 : case LE:
6644 0 : return
6645 0 : simplify_gen_unary (NEG, mode,
6646 : simplify_gen_unary (ABS, mode, true_rtx, mode),
6647 0 : mode);
6648 : default:
6649 : break;
6650 : }
6651 :
6652 : /* Look for MIN or MAX. */
6653 :
6654 13509553 : if ((! FLOAT_MODE_P (mode)
6655 170662 : || (flag_unsafe_math_optimizations
6656 438 : && !HONOR_NANS (mode)
6657 438 : && !HONOR_SIGNED_ZEROS (mode)))
6658 13339329 : && comparison_p
6659 13338952 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6660 141714 : && rtx_equal_p (XEXP (cond, 1), false_rtx)
6661 13746 : && ! side_effects_p (cond))
6662 13742 : switch (true_code)
6663 : {
6664 5209 : case GE:
6665 5209 : case GT:
6666 5209 : return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6667 4769 : case LE:
6668 4769 : case LT:
6669 4769 : return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6670 2857 : case GEU:
6671 2857 : case GTU:
6672 2857 : return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6673 907 : case LEU:
6674 907 : case LTU:
6675 907 : return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6676 : default:
6677 : break;
6678 : }
6679 :
6680 : /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6681 : second operand is zero, this can be done as (OP Z (mult COND C2)) where
6682 : C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6683 : SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6684 : We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6685 : neither 1 or -1, but it isn't worth checking for. */
6686 :
6687 13495811 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6688 : && comparison_p
6689 15611820 : && is_int_mode (mode, &int_mode)
6690 15699150 : && ! side_effects_p (x))
6691 : {
6692 2199240 : rtx t = make_compound_operation (true_rtx, SET);
6693 2199240 : rtx f = make_compound_operation (false_rtx, SET);
6694 2199240 : rtx cond_op0 = XEXP (cond, 0);
6695 2199240 : rtx cond_op1 = XEXP (cond, 1);
6696 2199240 : enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6697 2199240 : scalar_int_mode m = int_mode;
6698 2199240 : rtx z = 0, c1 = NULL_RTX;
6699 :
6700 2199240 : if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6701 : || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6702 : || GET_CODE (t) == ASHIFT
6703 : || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6704 235840 : && rtx_equal_p (XEXP (t, 0), f))
6705 76527 : c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6706 :
6707 : /* If an identity-zero op is commutative, check whether there
6708 : would be a match if we swapped the operands. */
6709 2036325 : else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6710 2024730 : || GET_CODE (t) == XOR)
6711 2135438 : && rtx_equal_p (XEXP (t, 1), f))
6712 10803 : c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6713 2111910 : else if (GET_CODE (t) == SIGN_EXTEND
6714 4619 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6715 4619 : && (GET_CODE (XEXP (t, 0)) == PLUS
6716 4619 : || GET_CODE (XEXP (t, 0)) == MINUS
6717 : || GET_CODE (XEXP (t, 0)) == IOR
6718 : || GET_CODE (XEXP (t, 0)) == XOR
6719 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6720 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6721 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6722 144 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6723 86 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6724 86 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6725 2111910 : && (num_sign_bit_copies (f, GET_MODE (f))
6726 0 : > (unsigned int)
6727 0 : (GET_MODE_PRECISION (int_mode)
6728 0 : - GET_MODE_PRECISION (inner_mode))))
6729 : {
6730 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6731 0 : extend_op = SIGN_EXTEND;
6732 0 : m = inner_mode;
6733 : }
6734 2111910 : else if (GET_CODE (t) == SIGN_EXTEND
6735 4619 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6736 4619 : && (GET_CODE (XEXP (t, 0)) == PLUS
6737 4502 : || GET_CODE (XEXP (t, 0)) == IOR
6738 4498 : || GET_CODE (XEXP (t, 0)) == XOR)
6739 121 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6740 4 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6741 4 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6742 2111914 : && (num_sign_bit_copies (f, GET_MODE (f))
6743 4 : > (unsigned int)
6744 4 : (GET_MODE_PRECISION (int_mode)
6745 4 : - GET_MODE_PRECISION (inner_mode))))
6746 : {
6747 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6748 0 : extend_op = SIGN_EXTEND;
6749 0 : m = inner_mode;
6750 : }
6751 2111910 : else if (GET_CODE (t) == ZERO_EXTEND
6752 5023 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6753 5023 : && (GET_CODE (XEXP (t, 0)) == PLUS
6754 5023 : || GET_CODE (XEXP (t, 0)) == MINUS
6755 : || GET_CODE (XEXP (t, 0)) == IOR
6756 : || GET_CODE (XEXP (t, 0)) == XOR
6757 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6758 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6759 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6760 1473 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6761 104 : && HWI_COMPUTABLE_MODE_P (int_mode)
6762 104 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6763 104 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6764 2111910 : && ((nonzero_bits (f, GET_MODE (f))
6765 0 : & ~GET_MODE_MASK (inner_mode))
6766 : == 0))
6767 : {
6768 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6769 0 : extend_op = ZERO_EXTEND;
6770 0 : m = inner_mode;
6771 : }
6772 2111910 : else if (GET_CODE (t) == ZERO_EXTEND
6773 5023 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6774 5023 : && (GET_CODE (XEXP (t, 0)) == PLUS
6775 4161 : || GET_CODE (XEXP (t, 0)) == IOR
6776 4161 : || GET_CODE (XEXP (t, 0)) == XOR)
6777 862 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6778 18 : && HWI_COMPUTABLE_MODE_P (int_mode)
6779 18 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6780 18 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6781 2111910 : && ((nonzero_bits (f, GET_MODE (f))
6782 0 : & ~GET_MODE_MASK (inner_mode))
6783 : == 0))
6784 : {
6785 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6786 0 : extend_op = ZERO_EXTEND;
6787 0 : m = inner_mode;
6788 : }
6789 :
6790 87330 : if (z)
6791 : {
6792 87330 : machine_mode cm = m;
6793 87330 : if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6794 2390 : && GET_MODE (c1) != VOIDmode)
6795 1754 : cm = GET_MODE (c1);
6796 87330 : temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6797 : cond_op0, cond_op1),
6798 : pc_rtx, pc_rtx, false, false, false);
6799 87330 : temp = simplify_gen_binary (MULT, cm, temp,
6800 : simplify_gen_binary (MULT, cm, c1,
6801 : const_true_rtx));
6802 87330 : temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6803 87330 : temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6804 :
6805 87330 : if (extend_op != UNKNOWN)
6806 0 : temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6807 :
6808 13509595 : return temp;
6809 : }
6810 : }
6811 :
6812 : /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6813 : 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6814 : negation of a single bit, we can convert this operation to a shift. We
6815 : can actually do this more generally, but it doesn't seem worth it. */
6816 :
6817 13408481 : if (true_code == NE
6818 13408481 : && is_a <scalar_int_mode> (mode, &int_mode)
6819 446050 : && XEXP (cond, 1) == const0_rtx
6820 332723 : && false_rtx == const0_rtx
6821 51685 : && CONST_INT_P (true_rtx)
6822 13410550 : && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6823 0 : && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6824 2069 : || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6825 2069 : == GET_MODE_PRECISION (int_mode))
6826 0 : && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6827 0 : return
6828 0 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6829 0 : gen_lowpart (int_mode, XEXP (cond, 0)), i);
6830 :
6831 : /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6832 : non-zero bit in A is C1. */
6833 4882064 : if (true_code == NE && XEXP (cond, 1) == const0_rtx
6834 2311873 : && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6835 13511664 : && is_a <scalar_int_mode> (mode, &int_mode)
6836 2069 : && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6837 35 : && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6838 35 : == nonzero_bits (XEXP (cond, 0), inner_mode)
6839 13408481 : && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6840 : {
6841 0 : rtx val = XEXP (cond, 0);
6842 0 : if (inner_mode == int_mode)
6843 : return val;
6844 0 : else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6845 0 : return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6846 : }
6847 :
6848 : return x;
6849 : }
6850 :
6851 : /* Simplify X, a SET expression. Return the new expression. */
6852 :
6853 : static rtx
6854 47854523 : simplify_set (rtx x)
6855 : {
6856 47854523 : rtx src = SET_SRC (x);
6857 47854523 : rtx dest = SET_DEST (x);
6858 107145162 : machine_mode mode
6859 47854523 : = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6860 47854523 : rtx_insn *other_insn;
6861 47854523 : rtx *cc_use;
6862 47854523 : scalar_int_mode int_mode;
6863 :
6864 : /* (set (pc) (return)) gets written as (return). */
6865 47854523 : if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6866 : return src;
6867 :
6868 : /* Now that we know for sure which bits of SRC we are using, see if we can
6869 : simplify the expression for the object knowing that we only need the
6870 : low-order bits. */
6871 :
6872 47854523 : if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6873 : {
6874 21319984 : src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6875 21319984 : SUBST (SET_SRC (x), src);
6876 : }
6877 :
6878 : /* If the source is a COMPARE, look for the use of the comparison result
6879 : and try to simplify it unless we already have used undobuf.other_insn. */
6880 41076690 : if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6881 6777833 : && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6882 6157354 : && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6883 6157354 : && COMPARISON_P (*cc_use)
6884 54011361 : && rtx_equal_p (XEXP (*cc_use, 0), dest))
6885 : {
6886 6154976 : enum rtx_code old_code = GET_CODE (*cc_use);
6887 6154976 : enum rtx_code new_code;
6888 6154976 : rtx op0, op1, tmp;
6889 6154976 : bool other_changed = false;
6890 6154976 : rtx inner_compare = NULL_RTX;
6891 6154976 : machine_mode compare_mode = GET_MODE (dest);
6892 :
6893 6154976 : if (GET_CODE (src) == COMPARE)
6894 : {
6895 5706873 : op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6896 5706873 : if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6897 : {
6898 0 : inner_compare = op0;
6899 0 : op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6900 : }
6901 : }
6902 : else
6903 448103 : op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6904 :
6905 6154976 : tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6906 : op0, op1);
6907 6154976 : if (!tmp)
6908 : new_code = old_code;
6909 485675 : else if (!CONSTANT_P (tmp))
6910 : {
6911 480862 : new_code = GET_CODE (tmp);
6912 480862 : op0 = XEXP (tmp, 0);
6913 480862 : op1 = XEXP (tmp, 1);
6914 : }
6915 : else
6916 : {
6917 4813 : rtx pat = PATTERN (other_insn);
6918 4813 : undobuf.other_insn = other_insn;
6919 4813 : SUBST (*cc_use, tmp);
6920 :
6921 : /* Attempt to simplify CC user. */
6922 4813 : if (GET_CODE (pat) == SET)
6923 : {
6924 4313 : rtx new_rtx = simplify_rtx (SET_SRC (pat));
6925 4313 : if (new_rtx != NULL_RTX)
6926 3780 : SUBST (SET_SRC (pat), new_rtx);
6927 : }
6928 :
6929 : /* Convert X into a no-op move. */
6930 4813 : SUBST (SET_DEST (x), pc_rtx);
6931 4813 : SUBST (SET_SRC (x), pc_rtx);
6932 4813 : return x;
6933 : }
6934 :
6935 : /* Simplify our comparison, if possible. */
6936 6150163 : new_code = simplify_comparison (new_code, &op0, &op1);
6937 :
6938 : #ifdef SELECT_CC_MODE
6939 : /* If this machine has CC modes other than CCmode, check to see if we
6940 : need to use a different CC mode here. */
6941 6150163 : if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6942 685086 : compare_mode = GET_MODE (op0);
6943 5465077 : else if (inner_compare
6944 0 : && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6945 0 : && new_code == old_code
6946 0 : && op0 == XEXP (inner_compare, 0)
6947 0 : && op1 == XEXP (inner_compare, 1))
6948 0 : compare_mode = GET_MODE (inner_compare);
6949 : else
6950 5465077 : compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6951 :
6952 : /* If the mode changed, we have to change SET_DEST, the mode in the
6953 : compare, and the mode in the place SET_DEST is used. If SET_DEST is
6954 : a hard register, just build new versions with the proper mode. If it
6955 : is a pseudo, we lose unless it is only time we set the pseudo, in
6956 : which case we can safely change its mode. */
6957 6150163 : if (compare_mode != GET_MODE (dest))
6958 : {
6959 212166 : if (can_change_dest_mode (dest, 0, compare_mode))
6960 : {
6961 212166 : unsigned int regno = REGNO (dest);
6962 212166 : rtx new_dest;
6963 :
6964 212166 : if (regno < FIRST_PSEUDO_REGISTER)
6965 212166 : new_dest = gen_rtx_REG (compare_mode, regno);
6966 : else
6967 : {
6968 0 : subst_mode (regno, compare_mode);
6969 0 : new_dest = regno_reg_rtx[regno];
6970 : }
6971 :
6972 212166 : SUBST (SET_DEST (x), new_dest);
6973 212166 : SUBST (XEXP (*cc_use, 0), new_dest);
6974 212166 : other_changed = true;
6975 :
6976 212166 : dest = new_dest;
6977 : }
6978 : }
6979 : #endif /* SELECT_CC_MODE */
6980 :
6981 : /* If the code changed, we have to build a new comparison in
6982 : undobuf.other_insn. */
6983 6150163 : if (new_code != old_code)
6984 : {
6985 618268 : bool other_changed_previously = other_changed;
6986 618268 : unsigned HOST_WIDE_INT mask;
6987 618268 : rtx old_cc_use = *cc_use;
6988 :
6989 618268 : SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6990 : dest, const0_rtx));
6991 618268 : other_changed = true;
6992 :
6993 : /* If the only change we made was to change an EQ into an NE or
6994 : vice versa, OP0 has only one bit that might be nonzero, and OP1
6995 : is zero, check if changing the user of the condition code will
6996 : produce a valid insn. If it won't, we can keep the original code
6997 : in that insn by surrounding our operation with an XOR. */
6998 :
6999 618268 : if (((old_code == NE && new_code == EQ)
7000 577950 : || (old_code == EQ && new_code == NE))
7001 89634 : && ! other_changed_previously && op1 == const0_rtx
7002 86901 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
7003 628067 : && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
7004 : {
7005 9788 : rtx pat = PATTERN (other_insn), note = 0;
7006 :
7007 9788 : if ((recog_for_combine (&pat, other_insn, ¬e) < 0
7008 9788 : && ! check_asm_operands (pat)))
7009 : {
7010 4 : *cc_use = old_cc_use;
7011 4 : other_changed = false;
7012 :
7013 4 : op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
7014 4 : gen_int_mode (mask,
7015 4 : GET_MODE (op0)));
7016 : }
7017 : }
7018 : }
7019 :
7020 5541683 : if (other_changed)
7021 635557 : undobuf.other_insn = other_insn;
7022 :
7023 : /* Don't generate a compare of a CC with 0, just use that CC. */
7024 6150163 : if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
7025 : {
7026 685086 : SUBST (SET_SRC (x), op0);
7027 685086 : src = SET_SRC (x);
7028 : }
7029 : /* Otherwise, if we didn't previously have the same COMPARE we
7030 : want, create it from scratch. */
7031 5465077 : else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
7032 5344294 : || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
7033 : {
7034 1376351 : SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
7035 1376351 : src = SET_SRC (x);
7036 : }
7037 : }
7038 : else
7039 : {
7040 : /* Get SET_SRC in a form where we have placed back any
7041 : compound expressions. Then do the checks below. */
7042 41699547 : src = make_compound_operation (src, SET);
7043 41699547 : SUBST (SET_SRC (x), src);
7044 : }
7045 :
7046 : /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7047 : and X being a REG or (subreg (reg)), we may be able to convert this to
7048 : (set (subreg:m2 x) (op)).
7049 :
7050 : We can always do this if M1 is narrower than M2 because that means that
7051 : we only care about the low bits of the result.
7052 :
7053 : However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7054 : perform a narrower operation than requested since the high-order bits will
7055 : be undefined. On machine where it is defined, this transformation is safe
7056 : as long as M1 and M2 have the same number of words. */
7057 :
7058 430038 : if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7059 414159 : && !OBJECT_P (SUBREG_REG (src))
7060 : && (known_equal_after_align_up
7061 265471 : (GET_MODE_SIZE (GET_MODE (src)),
7062 530942 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7063 265471 : UNITS_PER_WORD))
7064 236126 : && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7065 223622 : && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7066 229 : && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7067 : GET_MODE (SUBREG_REG (src)),
7068 : GET_MODE (src)))
7069 48073103 : && (REG_P (dest)
7070 122654 : || (GET_CODE (dest) == SUBREG
7071 350 : && REG_P (SUBREG_REG (dest)))))
7072 : {
7073 101089 : SUBST (SET_DEST (x),
7074 : gen_lowpart (GET_MODE (SUBREG_REG (src)),
7075 : dest));
7076 101089 : SUBST (SET_SRC (x), SUBREG_REG (src));
7077 :
7078 101089 : src = SET_SRC (x), dest = SET_DEST (x);
7079 : }
7080 :
7081 : /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7082 : would require a paradoxical subreg. Replace the subreg with a
7083 : zero_extend to avoid the reload that would otherwise be required.
7084 : Don't do this unless we have a scalar integer mode, otherwise the
7085 : transformation is incorrect. */
7086 :
7087 47849710 : enum rtx_code extend_op;
7088 47849710 : if (paradoxical_subreg_p (src)
7089 : && MEM_P (SUBREG_REG (src))
7090 : && SCALAR_INT_MODE_P (GET_MODE (src))
7091 : && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7092 : {
7093 : SUBST (SET_SRC (x),
7094 : gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7095 :
7096 : src = SET_SRC (x);
7097 : }
7098 :
7099 : /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7100 : are comparing an item known to be 0 or -1 against 0, use a logical
7101 : operation instead. Check for one of the arms being an IOR of the other
7102 : arm with some value. We compute three terms to be IOR'ed together. In
7103 : practice, at most two will be nonzero. Then we do the IOR's. */
7104 :
7105 47849710 : if (GET_CODE (dest) != PC
7106 36848662 : && GET_CODE (src) == IF_THEN_ELSE
7107 1341200 : && is_int_mode (GET_MODE (src), &int_mode)
7108 1210321 : && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7109 475091 : && XEXP (XEXP (src, 0), 1) == const0_rtx
7110 350933 : && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7111 116991 : && (!HAVE_conditional_move
7112 116991 : || ! can_conditionally_move_p (int_mode))
7113 0 : && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7114 0 : == GET_MODE_PRECISION (int_mode))
7115 47849710 : && ! side_effects_p (src))
7116 : {
7117 0 : rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7118 0 : ? XEXP (src, 1) : XEXP (src, 2));
7119 0 : rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7120 0 : ? XEXP (src, 2) : XEXP (src, 1));
7121 0 : rtx term1 = const0_rtx, term2, term3;
7122 :
7123 0 : if (GET_CODE (true_rtx) == IOR
7124 0 : && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7125 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7126 0 : else if (GET_CODE (true_rtx) == IOR
7127 0 : && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7128 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7129 0 : else if (GET_CODE (false_rtx) == IOR
7130 0 : && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7131 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7132 0 : else if (GET_CODE (false_rtx) == IOR
7133 0 : && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7134 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7135 :
7136 0 : term2 = simplify_gen_binary (AND, int_mode,
7137 0 : XEXP (XEXP (src, 0), 0), true_rtx);
7138 0 : term3 = simplify_gen_binary (AND, int_mode,
7139 : simplify_gen_unary (NOT, int_mode,
7140 0 : XEXP (XEXP (src, 0), 0),
7141 : int_mode),
7142 : false_rtx);
7143 :
7144 0 : SUBST (SET_SRC (x),
7145 : simplify_gen_binary (IOR, int_mode,
7146 : simplify_gen_binary (IOR, int_mode,
7147 : term1, term2),
7148 : term3));
7149 :
7150 0 : src = SET_SRC (x);
7151 : }
7152 :
7153 : /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7154 : whole thing fail. */
7155 47849710 : if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7156 : return src;
7157 47849690 : else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7158 : return dest;
7159 : else
7160 : /* Convert this into a field assignment operation, if possible. */
7161 47849648 : return make_field_assignment (x);
7162 : }
7163 :
7164 : /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7165 : result. */
7166 :
7167 : static rtx
7168 11435263 : simplify_logical (rtx x)
7169 : {
7170 11435263 : rtx op0 = XEXP (x, 0);
7171 11435263 : rtx op1 = XEXP (x, 1);
7172 11435263 : scalar_int_mode mode;
7173 :
7174 11435263 : switch (GET_CODE (x))
7175 : {
7176 7143886 : case AND:
7177 : /* We can call simplify_and_const_int only if we don't lose
7178 : any (sign) bits when converting INTVAL (op1) to
7179 : "unsigned HOST_WIDE_INT". */
7180 7143886 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7181 6611029 : && CONST_INT_P (op1)
7182 5212035 : && (HWI_COMPUTABLE_MODE_P (mode)
7183 6647 : || INTVAL (op1) > 0))
7184 : {
7185 5208695 : x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7186 5208695 : if (GET_CODE (x) != AND)
7187 : return x;
7188 :
7189 5183818 : op0 = XEXP (x, 0);
7190 5183818 : op1 = XEXP (x, 1);
7191 : }
7192 :
7193 : /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7194 : apply the distributive law and then the inverse distributive
7195 : law to see if things simplify. */
7196 7119009 : if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7197 : {
7198 118510 : rtx result = distribute_and_simplify_rtx (x, 0);
7199 118510 : if (result)
7200 : return result;
7201 : }
7202 7105417 : if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7203 : {
7204 1822 : rtx result = distribute_and_simplify_rtx (x, 1);
7205 1822 : if (result)
7206 0 : return result;
7207 : }
7208 : break;
7209 :
7210 4291377 : case IOR:
7211 : /* If we have (ior (and A B) C), apply the distributive law and then
7212 : the inverse distributive law to see if things simplify. */
7213 :
7214 4291377 : if (GET_CODE (op0) == AND)
7215 : {
7216 1196357 : rtx result = distribute_and_simplify_rtx (x, 0);
7217 1196357 : if (result)
7218 : return result;
7219 : }
7220 :
7221 4288623 : if (GET_CODE (op1) == AND)
7222 : {
7223 54192 : rtx result = distribute_and_simplify_rtx (x, 1);
7224 54192 : if (result)
7225 4 : return result;
7226 : }
7227 : break;
7228 :
7229 0 : default:
7230 0 : gcc_unreachable ();
7231 : }
7232 :
7233 : return x;
7234 : }
7235 :
7236 : /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7237 : operations" because they can be replaced with two more basic operations.
7238 : ZERO_EXTEND is also considered "compound" because it can be replaced with
7239 : an AND operation, which is simpler, though only one operation.
7240 :
7241 : The function expand_compound_operation is called with an rtx expression
7242 : and will convert it to the appropriate shifts and AND operations,
7243 : simplifying at each stage.
7244 :
7245 : The function make_compound_operation is called to convert an expression
7246 : consisting of shifts and ANDs into the equivalent compound expression.
7247 : It is the inverse of this function, loosely speaking. */
7248 :
7249 : static rtx
7250 17028283 : expand_compound_operation (rtx x)
7251 : {
7252 17028283 : unsigned HOST_WIDE_INT pos = 0, len;
7253 17028283 : bool unsignedp = false;
7254 17028283 : unsigned int modewidth;
7255 17028283 : rtx tem;
7256 17028283 : scalar_int_mode inner_mode;
7257 :
7258 17028283 : switch (GET_CODE (x))
7259 : {
7260 4699424 : case ZERO_EXTEND:
7261 4699424 : unsignedp = true;
7262 : /* FALLTHRU */
7263 6054338 : case SIGN_EXTEND:
7264 : /* We can't necessarily use a const_int for a multiword mode;
7265 : it depends on implicitly extending the value.
7266 : Since we don't know the right way to extend it,
7267 : we can't tell whether the implicit way is right.
7268 :
7269 : Even for a mode that is no wider than a const_int,
7270 : we can't win, because we need to sign extend one of its bits through
7271 : the rest of it, and we don't know which bit. */
7272 6054338 : if (CONST_INT_P (XEXP (x, 0)))
7273 : return x;
7274 :
7275 : /* Reject modes that aren't scalar integers because turning vector
7276 : or complex modes into shifts causes problems. */
7277 6054338 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7278 : return x;
7279 :
7280 : /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7281 : (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7282 : because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7283 : reloaded. If not for that, MEM's would very rarely be safe.
7284 :
7285 : Reject modes bigger than a word, because we might not be able
7286 : to reference a two-register group starting with an arbitrary register
7287 : (and currently gen_lowpart might crash for a SUBREG). */
7288 :
7289 12258700 : if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7290 : return x;
7291 :
7292 5697784 : len = GET_MODE_PRECISION (inner_mode);
7293 : /* If the inner object has VOIDmode (the only way this can happen
7294 : is if it is an ASM_OPERANDS), we can't do anything since we don't
7295 : know how much masking to do. */
7296 5697784 : if (len == 0)
7297 : return x;
7298 :
7299 : break;
7300 :
7301 916121 : case ZERO_EXTRACT:
7302 916121 : unsignedp = true;
7303 :
7304 : /* fall through */
7305 :
7306 945640 : case SIGN_EXTRACT:
7307 : /* If the operand is a CLOBBER, just return it. */
7308 945640 : if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7309 : return XEXP (x, 0);
7310 :
7311 945634 : if (!CONST_INT_P (XEXP (x, 1))
7312 945511 : || !CONST_INT_P (XEXP (x, 2)))
7313 : return x;
7314 :
7315 : /* Reject modes that aren't scalar integers because turning vector
7316 : or complex modes into shifts causes problems. */
7317 871131 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7318 : return x;
7319 :
7320 871129 : len = INTVAL (XEXP (x, 1));
7321 871129 : pos = INTVAL (XEXP (x, 2));
7322 :
7323 : /* This should stay within the object being extracted, fail otherwise. */
7324 871129 : if (len + pos > GET_MODE_PRECISION (inner_mode))
7325 : return x;
7326 :
7327 : if (BITS_BIG_ENDIAN)
7328 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7329 :
7330 : break;
7331 :
7332 : default:
7333 : return x;
7334 : }
7335 :
7336 : /* We've rejected non-scalar operations by now. */
7337 6568864 : scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7338 :
7339 : /* Convert sign extension to zero extension, if we know that the high
7340 : bit is not set, as this is easier to optimize. It will be converted
7341 : back to cheaper alternative in make_extraction. */
7342 6568864 : if (GET_CODE (x) == SIGN_EXTEND
7343 1198667 : && HWI_COMPUTABLE_MODE_P (mode)
7344 7652279 : && ((nonzero_bits (XEXP (x, 0), inner_mode)
7345 1083415 : & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7346 : == 0))
7347 : {
7348 611 : rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7349 611 : rtx temp2 = expand_compound_operation (temp);
7350 :
7351 : /* Make sure this is a profitable operation. */
7352 611 : if (set_src_cost (x, mode, optimize_this_for_speed_p)
7353 611 : > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7354 : return temp2;
7355 597 : else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7356 597 : > set_src_cost (temp, mode, optimize_this_for_speed_p))
7357 : return temp;
7358 : else
7359 43 : return x;
7360 : }
7361 :
7362 : /* We can optimize some special cases of ZERO_EXTEND. */
7363 6568253 : if (GET_CODE (x) == ZERO_EXTEND)
7364 : {
7365 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7366 : know that the last value didn't have any inappropriate bits
7367 : set. */
7368 4499117 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7369 204 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7370 204 : && HWI_COMPUTABLE_MODE_P (mode)
7371 4499321 : && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7372 204 : & ~GET_MODE_MASK (inner_mode)) == 0)
7373 37 : return XEXP (XEXP (x, 0), 0);
7374 :
7375 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7376 4499080 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7377 674952 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7378 612541 : && subreg_lowpart_p (XEXP (x, 0))
7379 248837 : && HWI_COMPUTABLE_MODE_P (mode)
7380 4725454 : && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7381 226374 : & ~GET_MODE_MASK (inner_mode)) == 0)
7382 65 : return SUBREG_REG (XEXP (x, 0));
7383 :
7384 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7385 : is a comparison and STORE_FLAG_VALUE permits. This is like
7386 : the first case, but it works even when MODE is larger
7387 : than HOST_WIDE_INT. */
7388 4499015 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7389 167 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7390 167 : && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7391 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7392 4499015 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7393 : return XEXP (XEXP (x, 0), 0);
7394 :
7395 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7396 4499015 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7397 674887 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7398 612476 : && subreg_lowpart_p (XEXP (x, 0))
7399 248772 : && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7400 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7401 4499015 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7402 : return SUBREG_REG (XEXP (x, 0));
7403 :
7404 : }
7405 :
7406 : /* If we reach here, we want to return a pair of shifts. The inner
7407 : shift is a left shift of BITSIZE - POS - LEN bits. The outer
7408 : shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7409 : logical depending on the value of UNSIGNEDP.
7410 :
7411 : If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7412 : converted into an AND of a shift.
7413 :
7414 : We must check for the case where the left shift would have a negative
7415 : count. This can happen in a case like (x >> 31) & 255 on machines
7416 : that can't shift by a constant. On those machines, we would first
7417 : combine the shift with the AND to produce a variable-position
7418 : extraction. Then the constant of 31 would be substituted in
7419 : to produce such a position. */
7420 :
7421 6568151 : modewidth = GET_MODE_PRECISION (mode);
7422 6568151 : if (modewidth >= pos + len)
7423 : {
7424 6568150 : tem = gen_lowpart (mode, XEXP (x, 0));
7425 6568150 : if (!tem || GET_CODE (tem) == CLOBBER)
7426 : return x;
7427 6953140 : tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7428 3476570 : tem, modewidth - pos - len);
7429 3476570 : tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7430 3476570 : mode, tem, modewidth - len);
7431 : }
7432 1 : else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7433 : {
7434 1 : tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7435 : XEXP (x, 0), pos);
7436 1 : tem = gen_lowpart (mode, tem);
7437 1 : if (!tem || GET_CODE (tem) == CLOBBER)
7438 : return x;
7439 1 : tem = simplify_and_const_int (NULL_RTX, mode, tem,
7440 1 : (HOST_WIDE_INT_1U << len) - 1);
7441 : }
7442 : else
7443 : /* Any other cases we can't handle. */
7444 : return x;
7445 :
7446 : /* If we couldn't do this for some reason, return the original
7447 : expression. */
7448 3476571 : if (GET_CODE (tem) == CLOBBER)
7449 15 : return x;
7450 :
7451 : return tem;
7452 : }
7453 :
7454 : /* X is a SET which contains an assignment of one object into
7455 : a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7456 : or certain SUBREGS). If possible, convert it into a series of
7457 : logical operations.
7458 :
7459 : We half-heartedly support variable positions, but do not at all
7460 : support variable lengths. */
7461 :
7462 : static const_rtx
7463 85583680 : expand_field_assignment (const_rtx x)
7464 : {
7465 85583680 : rtx inner;
7466 85583680 : rtx pos; /* Always counts from low bit. */
7467 85583680 : int len, inner_len;
7468 85583680 : rtx mask, cleared, masked;
7469 85583680 : scalar_int_mode compute_mode;
7470 :
7471 : /* Loop until we find something we can't simplify. */
7472 85851973 : while (1)
7473 : {
7474 85851973 : if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7475 14066 : && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7476 : {
7477 14066 : rtx x0 = XEXP (SET_DEST (x), 0);
7478 14066 : if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7479 : break;
7480 14066 : inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7481 14066 : pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7482 : MAX_MODE_INT);
7483 14066 : }
7484 85837907 : else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7485 4449 : && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7486 : {
7487 4449 : inner = XEXP (SET_DEST (x), 0);
7488 4449 : if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7489 : break;
7490 :
7491 4449 : len = INTVAL (XEXP (SET_DEST (x), 1));
7492 4449 : pos = XEXP (SET_DEST (x), 2);
7493 :
7494 : /* A constant position should stay within the width of INNER. */
7495 4449 : if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7496 : break;
7497 :
7498 : if (BITS_BIG_ENDIAN)
7499 : {
7500 : if (CONST_INT_P (pos))
7501 : pos = GEN_INT (inner_len - len - INTVAL (pos));
7502 : else if (GET_CODE (pos) == MINUS
7503 : && CONST_INT_P (XEXP (pos, 1))
7504 : && INTVAL (XEXP (pos, 1)) == inner_len - len)
7505 : /* If position is ADJUST - X, new position is X. */
7506 : pos = XEXP (pos, 0);
7507 : else
7508 : pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7509 : gen_int_mode (inner_len - len,
7510 : GET_MODE (pos)),
7511 : pos);
7512 : }
7513 : }
7514 :
7515 : /* If the destination is a subreg that overwrites the whole of the inner
7516 : register, we can move the subreg to the source. */
7517 86089846 : else if (GET_CODE (SET_DEST (x)) == SUBREG
7518 : /* We need SUBREGs to compute nonzero_bits properly. */
7519 912106 : && nonzero_sign_valid
7520 86657012 : && !read_modify_subreg_p (SET_DEST (x)))
7521 : {
7522 256388 : x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7523 : gen_lowpart
7524 : (GET_MODE (SUBREG_REG (SET_DEST (x))),
7525 : SET_SRC (x)));
7526 256388 : continue;
7527 : }
7528 : else
7529 : break;
7530 :
7531 20725 : while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7532 2210 : inner = SUBREG_REG (inner);
7533 :
7534 : /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7535 18515 : if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7536 : {
7537 : /* Don't do anything for vector or complex integral types. */
7538 : if (! FLOAT_MODE_P (GET_MODE (inner)))
7539 : break;
7540 :
7541 : /* Try to find an integral mode to pun with. */
7542 38 : if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7543 0 : .exists (&compute_mode))
7544 : break;
7545 :
7546 19 : inner = gen_lowpart (compute_mode, inner);
7547 : }
7548 :
7549 : /* Compute a mask of LEN bits, if we can do this on the host machine. */
7550 13857 : if (len >= HOST_BITS_PER_WIDE_INT)
7551 : break;
7552 :
7553 : /* Don't try to compute in too wide unsupported modes. */
7554 13857 : if (!targetm.scalar_mode_supported_p (compute_mode))
7555 : break;
7556 :
7557 : /* gen_lowpart_for_combine returns CLOBBER on failure. */
7558 13857 : rtx lowpart = gen_lowpart (compute_mode, SET_SRC (x));
7559 13857 : if (GET_CODE (lowpart) == CLOBBER)
7560 : break;
7561 :
7562 : /* Now compute the equivalent expression. Make a copy of INNER
7563 : for the SET_DEST in case it is a MEM into which we will substitute;
7564 : we don't want shared RTL in that case. */
7565 11905 : mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7566 : compute_mode);
7567 11905 : cleared = simplify_gen_binary (AND, compute_mode,
7568 : simplify_gen_unary (NOT, compute_mode,
7569 : simplify_gen_binary (ASHIFT,
7570 : compute_mode,
7571 : mask, pos),
7572 : compute_mode),
7573 : inner);
7574 11905 : masked = simplify_gen_binary (ASHIFT, compute_mode,
7575 : simplify_gen_binary (
7576 : AND, compute_mode, lowpart, mask),
7577 : pos);
7578 :
7579 11905 : x = gen_rtx_SET (copy_rtx (inner),
7580 : simplify_gen_binary (IOR, compute_mode,
7581 : cleared, masked));
7582 : }
7583 :
7584 85583680 : return x;
7585 : }
7586 :
7587 : /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7588 : it is an RTX that represents the (variable) starting position; otherwise,
7589 : POS is the (constant) starting bit position. Both are counted from the LSB.
7590 :
7591 : UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7592 :
7593 : IN_DEST is true if this is a reference in the destination of a SET.
7594 : This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7595 : a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7596 : be used.
7597 :
7598 : IN_COMPARE is true if we are in a COMPARE. This means that a
7599 : ZERO_EXTRACT should be built even for bits starting at bit 0.
7600 :
7601 : MODE is the desired mode of the result (if IN_DEST == 0).
7602 :
7603 : The result is an RTX for the extraction or NULL_RTX if the target
7604 : can't handle it. */
7605 :
7606 : static rtx
7607 5178678 : make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7608 : rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7609 : bool in_dest, bool in_compare)
7610 : {
7611 : /* This mode describes the size of the storage area
7612 : to fetch the overall value from. Within that, we
7613 : ignore the POS lowest bits, etc. */
7614 5178678 : machine_mode is_mode = GET_MODE (inner);
7615 5178678 : machine_mode inner_mode;
7616 5178678 : scalar_int_mode wanted_inner_mode;
7617 5178678 : scalar_int_mode wanted_inner_reg_mode = word_mode;
7618 5178678 : scalar_int_mode pos_mode = word_mode;
7619 5178678 : machine_mode extraction_mode = word_mode;
7620 5178678 : rtx new_rtx = 0;
7621 5178678 : rtx orig_pos_rtx = pos_rtx;
7622 5178678 : HOST_WIDE_INT orig_pos;
7623 :
7624 5178678 : if (pos_rtx && CONST_INT_P (pos_rtx))
7625 941212 : pos = INTVAL (pos_rtx), pos_rtx = 0;
7626 :
7627 5178678 : if (GET_CODE (inner) == SUBREG
7628 2664675 : && subreg_lowpart_p (inner)
7629 7839661 : && (paradoxical_subreg_p (inner)
7630 : /* If trying or potentially trying to extract
7631 : bits outside of is_mode, don't look through
7632 : non-paradoxical SUBREGs. See PR82192. */
7633 188336 : || (pos_rtx == NULL_RTX
7634 188285 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7635 : {
7636 : /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7637 : consider just the QI as the memory to extract from.
7638 : The subreg adds or removes high bits; its mode is
7639 : irrelevant to the meaning of this extraction,
7640 : since POS and LEN count from the lsb. */
7641 2660932 : if (MEM_P (SUBREG_REG (inner)))
7642 490133 : is_mode = GET_MODE (SUBREG_REG (inner));
7643 : inner = SUBREG_REG (inner);
7644 : }
7645 2517746 : else if (GET_CODE (inner) == ASHIFT
7646 142013 : && CONST_INT_P (XEXP (inner, 1))
7647 140844 : && pos_rtx == 0 && pos == 0
7648 140821 : && len > UINTVAL (XEXP (inner, 1)))
7649 : {
7650 : /* We're extracting the least significant bits of an rtx
7651 : (ashift X (const_int C)), where LEN > C. Extract the
7652 : least significant (LEN - C) bits of X, giving an rtx
7653 : whose mode is MODE, then shift it left C times. */
7654 140821 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7655 : 0, 0, len - INTVAL (XEXP (inner, 1)),
7656 : unsignedp, in_dest, in_compare);
7657 140821 : if (new_rtx != 0)
7658 139175 : return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7659 : }
7660 2376925 : else if (GET_CODE (inner) == MULT
7661 173558 : && CONST_INT_P (XEXP (inner, 1))
7662 133491 : && pos_rtx == 0 && pos == 0)
7663 : {
7664 : /* We're extracting the least significant bits of an rtx
7665 : (mult X (const_int 2^C)), where LEN > C. Extract the
7666 : least significant (LEN - C) bits of X, giving an rtx
7667 : whose mode is MODE, then multiply it by 2^C. */
7668 113500 : const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7669 113500 : if (len > 1 && IN_RANGE (shift_amt, 1, len - 1))
7670 : {
7671 109056 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7672 : 0, 0, len - shift_amt,
7673 : unsignedp, in_dest, in_compare);
7674 109056 : if (new_rtx)
7675 109056 : return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7676 : }
7677 : }
7678 2263425 : else if (GET_CODE (inner) == TRUNCATE
7679 : /* If trying or potentially trying to extract
7680 : bits outside of is_mode, don't look through
7681 : TRUNCATE. See PR82192. */
7682 0 : && pos_rtx == NULL_RTX
7683 2263425 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7684 0 : inner = XEXP (inner, 0);
7685 :
7686 4930447 : inner_mode = GET_MODE (inner);
7687 :
7688 : /* See if this can be done without an extraction. We never can if the
7689 : width of the field is not the same as that of some integer mode. For
7690 : registers, we can only avoid the extraction if the position is at the
7691 : low-order bit and this is either not in the destination or we have the
7692 : appropriate STRICT_LOW_PART operation available.
7693 :
7694 : For MEM, we can avoid an extract if the field starts on an appropriate
7695 : boundary and we can change the mode of the memory reference. */
7696 :
7697 4930447 : scalar_int_mode tmode;
7698 4930447 : if (int_mode_for_size (len, 1).exists (&tmode)
7699 2397956 : && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7700 2077200 : && !MEM_P (inner)
7701 1695978 : && (pos == 0 || REG_P (inner))
7702 1695978 : && (inner_mode == tmode
7703 261362 : || !REG_P (inner)
7704 2300803 : || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7705 0 : || reg_truncated_to_mode (tmode, inner))
7706 1695978 : && (! in_dest
7707 5 : || (REG_P (inner)
7708 5 : && have_insn_for (STRICT_LOW_PART, tmode))))
7709 561800 : || (MEM_P (inner) && pos_rtx == 0
7710 382571 : && (pos
7711 : % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7712 : : BITS_PER_UNIT)) == 0
7713 : /* We can't do this if we are widening INNER_MODE (it
7714 : may not be aligned, for one thing). */
7715 381554 : && !paradoxical_subreg_p (tmode, inner_mode)
7716 381554 : && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7717 381554 : && (inner_mode == tmode
7718 603 : || (! mode_dependent_address_p (XEXP (inner, 0),
7719 603 : MEM_ADDR_SPACE (inner))
7720 603 : && ! MEM_VOLATILE_P (inner))))))
7721 : {
7722 : /* If INNER is a MEM, make a new MEM that encompasses just the desired
7723 : field. If the original and current mode are the same, we need not
7724 : adjust the offset. Otherwise, we do if bytes big endian.
7725 :
7726 : If INNER is not a MEM, get a piece consisting of just the field
7727 : of interest (in this case POS % BITS_PER_WORD must be 0). */
7728 :
7729 2077519 : if (MEM_P (inner))
7730 : {
7731 381541 : poly_int64 offset;
7732 :
7733 : /* POS counts from lsb, but make OFFSET count in memory order. */
7734 381541 : if (BYTES_BIG_ENDIAN)
7735 : offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7736 : - len - pos);
7737 : else
7738 381541 : offset = pos / BITS_PER_UNIT;
7739 :
7740 381541 : new_rtx = adjust_address_nv (inner, tmode, offset);
7741 : }
7742 1695978 : else if (REG_P (inner))
7743 : {
7744 1060627 : if (tmode != inner_mode)
7745 : {
7746 : /* We can't call gen_lowpart in a DEST since we
7747 : always want a SUBREG (see below) and it would sometimes
7748 : return a new hard register. */
7749 223284 : if (pos || in_dest)
7750 : {
7751 8 : poly_uint64 offset
7752 8 : = subreg_offset_from_lsb (tmode, inner_mode, pos);
7753 :
7754 : /* Avoid creating invalid subregs, for example when
7755 : simplifying (x>>32)&255. */
7756 8 : if (!validate_subreg (tmode, inner_mode, inner, offset))
7757 0 : return NULL_RTX;
7758 :
7759 8 : new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7760 8 : }
7761 : else
7762 223276 : new_rtx = gen_lowpart (tmode, inner);
7763 : }
7764 : else
7765 : new_rtx = inner;
7766 : }
7767 : else
7768 1270702 : new_rtx = force_to_mode (inner, tmode,
7769 : len >= HOST_BITS_PER_WIDE_INT
7770 : ? HOST_WIDE_INT_M1U
7771 635351 : : (HOST_WIDE_INT_1U << len) - 1, false);
7772 :
7773 : /* If this extraction is going into the destination of a SET,
7774 : make a STRICT_LOW_PART unless we made a MEM. */
7775 :
7776 2077519 : if (in_dest)
7777 41 : return (MEM_P (new_rtx) ? new_rtx
7778 : : (GET_CODE (new_rtx) != SUBREG
7779 5 : ? gen_rtx_CLOBBER (tmode, const0_rtx)
7780 5 : : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7781 :
7782 2077478 : if (mode == tmode)
7783 : return new_rtx;
7784 :
7785 2077449 : if (CONST_SCALAR_INT_P (new_rtx))
7786 5 : return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7787 5 : mode, new_rtx, tmode);
7788 :
7789 : /* If we know that no extraneous bits are set, and that the high
7790 : bit is not set, convert the extraction to the cheaper of
7791 : sign and zero extension, that are equivalent in these cases. */
7792 2077444 : if (flag_expensive_optimizations
7793 2077444 : && (HWI_COMPUTABLE_MODE_P (tmode)
7794 1925592 : && ((nonzero_bits (new_rtx, tmode)
7795 1925592 : & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7796 : == 0)))
7797 : {
7798 7076 : rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7799 7076 : rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7800 :
7801 : /* Prefer ZERO_EXTENSION, since it gives more information to
7802 : backends. */
7803 7076 : if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7804 7076 : <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7805 : return temp;
7806 0 : return temp1;
7807 : }
7808 :
7809 : /* Otherwise, sign- or zero-extend unless we already are in the
7810 : proper mode. */
7811 :
7812 2070368 : return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7813 2070368 : mode, new_rtx));
7814 : }
7815 :
7816 : /* Unless this is a COMPARE or we have a funny memory reference,
7817 : don't do anything with zero-extending field extracts starting at
7818 : the low-order bit since they are simple AND operations. */
7819 2852928 : if (pos_rtx == 0 && pos == 0 && ! in_dest
7820 1779281 : && ! in_compare && unsignedp)
7821 : return 0;
7822 :
7823 : /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7824 : if the position is not a constant and the length is not 1. In all
7825 : other cases, we would only be going outside our object in cases when
7826 : an original shift would have been undefined. */
7827 1477968 : if (MEM_P (inner)
7828 1477968 : && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7829 2963 : || (pos_rtx != 0 && len != 1)))
7830 : return 0;
7831 :
7832 1600765 : enum extraction_pattern pattern = (in_dest ? EP_insv
7833 1471865 : : unsignedp ? EP_extzv : EP_extv);
7834 :
7835 : /* If INNER is not from memory, we want it to have the mode of a register
7836 : extraction pattern's structure operand, or word_mode if there is no
7837 : such pattern. The same applies to extraction_mode and pos_mode
7838 : and their respective operands.
7839 :
7840 : For memory, assume that the desired extraction_mode and pos_mode
7841 : are the same as for a register operation, since at present we don't
7842 : have named patterns for aligned memory structures. */
7843 1477928 : class extraction_insn insn;
7844 1477928 : unsigned int inner_size;
7845 2955856 : if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7846 1477928 : && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7847 : {
7848 1371104 : wanted_inner_reg_mode = insn.struct_mode.require ();
7849 1371104 : pos_mode = insn.pos_mode;
7850 1371104 : extraction_mode = insn.field_mode;
7851 : }
7852 :
7853 : /* Never narrow an object, since that might not be safe. */
7854 :
7855 1477928 : if (mode != VOIDmode
7856 1477928 : && partial_subreg_p (extraction_mode, mode))
7857 : extraction_mode = mode;
7858 :
7859 : /* Punt if len is too large for extraction_mode. */
7860 1477928 : if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7861 : return NULL_RTX;
7862 :
7863 1477916 : if (!MEM_P (inner))
7864 1302742 : wanted_inner_mode = wanted_inner_reg_mode;
7865 : else
7866 : {
7867 : /* Be careful not to go beyond the extracted object and maintain the
7868 : natural alignment of the memory. */
7869 175174 : wanted_inner_mode = smallest_int_mode_for_size (len).require ();
7870 353446 : while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7871 356544 : > GET_MODE_BITSIZE (wanted_inner_mode))
7872 3098 : wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7873 : }
7874 :
7875 1477916 : orig_pos = pos;
7876 :
7877 1477916 : if (BITS_BIG_ENDIAN)
7878 : {
7879 : /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7880 : BITS_BIG_ENDIAN style. If position is constant, compute new
7881 : position. Otherwise, build subtraction.
7882 : Note that POS is relative to the mode of the original argument.
7883 : If it's a MEM we need to recompute POS relative to that.
7884 : However, if we're extracting from (or inserting into) a register,
7885 : we want to recompute POS relative to wanted_inner_mode. */
7886 : int width;
7887 : if (!MEM_P (inner))
7888 : width = GET_MODE_BITSIZE (wanted_inner_mode);
7889 : else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7890 : return NULL_RTX;
7891 :
7892 : if (pos_rtx == 0)
7893 : pos = width - len - pos;
7894 : else
7895 : pos_rtx
7896 : = gen_rtx_MINUS (GET_MODE (pos_rtx),
7897 : gen_int_mode (width - len, GET_MODE (pos_rtx)),
7898 : pos_rtx);
7899 : /* POS may be less than 0 now, but we check for that below.
7900 : Note that it can only be less than 0 if !MEM_P (inner). */
7901 : }
7902 :
7903 : /* If INNER has a wider mode, and this is a constant extraction, try to
7904 : make it smaller and adjust the byte to point to the byte containing
7905 : the value. */
7906 1477916 : if (wanted_inner_mode != VOIDmode
7907 1477916 : && inner_mode != wanted_inner_mode
7908 226274 : && ! pos_rtx
7909 217834 : && partial_subreg_p (wanted_inner_mode, is_mode)
7910 114419 : && MEM_P (inner)
7911 26133 : && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7912 1504049 : && ! MEM_VOLATILE_P (inner))
7913 : {
7914 24580 : poly_int64 offset = 0;
7915 :
7916 : /* The computations below will be correct if the machine is big
7917 : endian in both bits and bytes or little endian in bits and bytes.
7918 : If it is mixed, we must adjust. */
7919 :
7920 : /* If bytes are big endian and we had a paradoxical SUBREG, we must
7921 : adjust OFFSET to compensate. */
7922 24580 : if (BYTES_BIG_ENDIAN
7923 : && paradoxical_subreg_p (is_mode, inner_mode))
7924 : offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7925 :
7926 : /* We can now move to the desired byte. */
7927 49160 : offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7928 24580 : * GET_MODE_SIZE (wanted_inner_mode);
7929 24580 : pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7930 :
7931 24580 : if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7932 : && is_mode != wanted_inner_mode)
7933 : offset = (GET_MODE_SIZE (is_mode)
7934 : - GET_MODE_SIZE (wanted_inner_mode) - offset);
7935 :
7936 24580 : inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7937 : }
7938 :
7939 : /* If INNER is not memory, get it into the proper mode. If we are changing
7940 : its mode, POS must be a constant and smaller than the size of the new
7941 : mode. */
7942 1453336 : else if (!MEM_P (inner))
7943 : {
7944 : /* On the LHS, don't create paradoxical subregs implicitly truncating
7945 : the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7946 1302742 : if (in_dest
7947 1302742 : && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7948 : wanted_inner_mode))
7949 0 : return NULL_RTX;
7950 :
7951 1302742 : if (GET_MODE (inner) != wanted_inner_mode
7952 1302742 : && (pos_rtx != 0
7953 383402 : || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7954 : return NULL_RTX;
7955 :
7956 1236648 : if (orig_pos < 0)
7957 : return NULL_RTX;
7958 :
7959 2454203 : inner = force_to_mode (inner, wanted_inner_mode,
7960 : pos_rtx
7961 1217555 : || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7962 : ? HOST_WIDE_INT_M1U
7963 1057591 : : (((HOST_WIDE_INT_1U << len) - 1)
7964 1057591 : << orig_pos), false);
7965 : }
7966 :
7967 : /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7968 : have to zero extend. Otherwise, we can just use a SUBREG.
7969 :
7970 : We dealt with constant rtxes earlier, so pos_rtx cannot
7971 : have VOIDmode at this point. */
7972 1411822 : if (pos_rtx != 0
7973 1411822 : && (GET_MODE_SIZE (pos_mode)
7974 1433838 : > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7975 : {
7976 78 : rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7977 : GET_MODE (pos_rtx));
7978 :
7979 : /* If we know that no extraneous bits are set, and that the high
7980 : bit is not set, convert extraction to cheaper one - either
7981 : SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7982 : cases. */
7983 78 : if (flag_expensive_optimizations
7984 78 : && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7985 78 : && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7986 78 : & ~(((unsigned HOST_WIDE_INT)
7987 78 : GET_MODE_MASK (GET_MODE (pos_rtx)))
7988 78 : >> 1))
7989 : == 0)))
7990 : {
7991 56 : rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7992 : GET_MODE (pos_rtx));
7993 :
7994 : /* Prefer ZERO_EXTENSION, since it gives more information to
7995 : backends. */
7996 56 : if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7997 56 : < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7998 1411822 : temp = temp1;
7999 : }
8000 : pos_rtx = temp;
8001 : }
8002 :
8003 : /* Make POS_RTX unless we already have it and it is correct. If we don't
8004 : have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
8005 : be a CONST_INT. */
8006 1411822 : if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
8007 : pos_rtx = orig_pos_rtx;
8008 :
8009 494727 : else if (pos_rtx == 0)
8010 472711 : pos_rtx = GEN_INT (pos);
8011 :
8012 : /* Make the required operation. See if we can use existing rtx. */
8013 1411822 : new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
8014 : extraction_mode, inner, GEN_INT (len), pos_rtx);
8015 1411822 : if (! in_dest)
8016 1405803 : new_rtx = gen_lowpart (mode, new_rtx);
8017 :
8018 : return new_rtx;
8019 : }
8020 :
8021 : /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8022 : can be commuted with any other operations in X. Return X without
8023 : that shift if so. */
8024 :
8025 : static rtx
8026 1596252 : extract_left_shift (scalar_int_mode mode, rtx x, int count)
8027 : {
8028 1596252 : enum rtx_code code = GET_CODE (x);
8029 1596252 : rtx tem;
8030 :
8031 1596252 : switch (code)
8032 : {
8033 265469 : case ASHIFT:
8034 : /* This is the shift itself. If it is wide enough, we will return
8035 : either the value being shifted if the shift count is equal to
8036 : COUNT or a shift for the difference. */
8037 265469 : if (CONST_INT_P (XEXP (x, 1))
8038 260150 : && INTVAL (XEXP (x, 1)) >= count)
8039 259128 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8040 259128 : INTVAL (XEXP (x, 1)) - count);
8041 : break;
8042 :
8043 5416 : case NEG: case NOT:
8044 5416 : if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8045 2531 : return simplify_gen_unary (code, mode, tem, mode);
8046 :
8047 : break;
8048 :
8049 556677 : case PLUS: case IOR: case XOR: case AND:
8050 : /* If we can safely shift this constant and we find the inner shift,
8051 : make a new operation. */
8052 556677 : if (CONST_INT_P (XEXP (x, 1))
8053 299947 : && (UINTVAL (XEXP (x, 1))
8054 299947 : & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8055 700310 : && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8056 : {
8057 6941 : HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8058 6941 : return simplify_gen_binary (code, mode, tem,
8059 6941 : gen_int_mode (val, mode));
8060 : }
8061 : break;
8062 :
8063 : default:
8064 : break;
8065 : }
8066 :
8067 : return 0;
8068 : }
8069 :
8070 : /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8071 : level of the expression and MODE is its mode. IN_CODE is as for
8072 : make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8073 : that should be used when recursing on operands of *X_PTR.
8074 :
8075 : There are two possible actions:
8076 :
8077 : - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8078 : equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8079 :
8080 : - Return a new rtx, which the caller returns directly. */
8081 :
8082 : static rtx
8083 282934567 : make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8084 : enum rtx_code in_code,
8085 : enum rtx_code *next_code_ptr)
8086 : {
8087 282934567 : rtx x = *x_ptr;
8088 282934567 : enum rtx_code next_code = *next_code_ptr;
8089 282934567 : enum rtx_code code = GET_CODE (x);
8090 282934567 : int mode_width = GET_MODE_PRECISION (mode);
8091 282934567 : rtx rhs, lhs;
8092 282934567 : rtx new_rtx = 0;
8093 282934567 : int i;
8094 282934567 : rtx tem;
8095 282934567 : scalar_int_mode inner_mode;
8096 282934567 : bool equality_comparison = false;
8097 :
8098 282934567 : if (in_code == EQ)
8099 : {
8100 9223721 : equality_comparison = true;
8101 9223721 : in_code = COMPARE;
8102 : }
8103 :
8104 : /* Process depending on the code of this operation. If NEW is set
8105 : nonzero, it will be returned. */
8106 :
8107 282934567 : switch (code)
8108 : {
8109 6529034 : case ASHIFT:
8110 : /* Convert shifts by constants into multiplications if inside
8111 : an address. */
8112 6529034 : if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8113 1958615 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8114 1958615 : && INTVAL (XEXP (x, 1)) >= 0)
8115 : {
8116 1958615 : HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8117 1958615 : HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8118 :
8119 1958615 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8120 1958615 : if (GET_CODE (new_rtx) == NEG)
8121 : {
8122 9 : new_rtx = XEXP (new_rtx, 0);
8123 9 : multval = -multval;
8124 : }
8125 1958615 : multval = trunc_int_for_mode (multval, mode);
8126 1958615 : new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8127 : }
8128 : break;
8129 :
8130 55280679 : case PLUS:
8131 55280679 : case MINUS:
8132 55280679 : lhs = make_compound_operation (XEXP (x, 0), next_code);
8133 55280679 : rhs = make_compound_operation (XEXP (x, 1), next_code);
8134 55280679 : if (lhs != XEXP (x, 0) || rhs != XEXP (x, 1))
8135 3165766 : return simplify_gen_binary (code, mode, lhs, rhs);
8136 : return x;
8137 :
8138 7481377 : case AND:
8139 : /* If the second operand is not a constant, we can't do anything
8140 : with it. */
8141 7481377 : if (!CONST_INT_P (XEXP (x, 1)))
8142 : break;
8143 :
8144 : /* If the constant is a power of two minus one and the first operand
8145 : is a logical right shift, make an extraction. */
8146 5939304 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8147 5939304 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8148 : {
8149 649601 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8150 649601 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8151 : i, true, false, in_code == COMPARE);
8152 : }
8153 :
8154 : /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8155 5289703 : else if (GET_CODE (XEXP (x, 0)) == SUBREG
8156 1387113 : && subreg_lowpart_p (XEXP (x, 0))
8157 6631386 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8158 : &inner_mode)
8159 1372258 : && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8160 5322353 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8161 : {
8162 30575 : rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8163 30575 : new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8164 30575 : new_rtx = make_extraction (inner_mode, new_rtx, 0,
8165 : XEXP (inner_x0, 1),
8166 : i, true, false, in_code == COMPARE);
8167 :
8168 : /* If we narrowed the mode when dropping the subreg, then we lose. */
8169 91725 : if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8170 30575 : new_rtx = NULL;
8171 :
8172 : /* If that didn't give anything, see if the AND simplifies on
8173 : its own. */
8174 30575 : if (!new_rtx && i >= 0)
8175 : {
8176 3303 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8177 3303 : new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i,
8178 : true, false, in_code == COMPARE);
8179 : }
8180 : }
8181 : /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8182 5259128 : else if ((GET_CODE (XEXP (x, 0)) == XOR
8183 5259128 : || GET_CODE (XEXP (x, 0)) == IOR)
8184 28889 : && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8185 2574 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8186 5259138 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8187 : {
8188 : /* Apply the distributive law, and then try to make extractions. */
8189 10 : new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8190 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8191 : XEXP (x, 1)),
8192 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8193 : XEXP (x, 1)));
8194 10 : new_rtx = make_compound_operation (new_rtx, in_code);
8195 : }
8196 :
8197 : /* If we are have (and (rotate X C) M) and C is larger than the number
8198 : of bits in M, this is an extraction. */
8199 :
8200 5259118 : else if (GET_CODE (XEXP (x, 0)) == ROTATE
8201 935 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8202 925 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8203 5259155 : && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8204 : {
8205 0 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8206 0 : new_rtx = make_extraction (mode, new_rtx,
8207 0 : (GET_MODE_PRECISION (mode)
8208 0 : - INTVAL (XEXP (XEXP (x, 0), 1))),
8209 : NULL_RTX, i, true, false,
8210 : in_code == COMPARE);
8211 : }
8212 :
8213 : /* On machines without logical shifts, if the operand of the AND is
8214 : a logical shift and our mask turns off all the propagated sign
8215 : bits, we can replace the logical shift with an arithmetic shift. */
8216 5259118 : else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8217 88778 : && !have_insn_for (LSHIFTRT, mode)
8218 0 : && have_insn_for (ASHIFTRT, mode)
8219 0 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8220 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8221 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8222 5259118 : && mode_width <= HOST_BITS_PER_WIDE_INT)
8223 : {
8224 0 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8225 :
8226 0 : mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8227 0 : if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8228 0 : SUBST (XEXP (x, 0),
8229 : gen_rtx_ASHIFTRT (mode,
8230 : make_compound_operation (XEXP (XEXP (x,
8231 : 0),
8232 : 0),
8233 : next_code),
8234 : XEXP (XEXP (x, 0), 1)));
8235 : }
8236 :
8237 : /* If the constant is one less than a power of two, this might be
8238 : representable by an extraction even if no shift is present.
8239 : If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8240 : we are in a COMPARE. */
8241 5259118 : else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8242 2701505 : new_rtx = make_extraction (mode,
8243 : make_compound_operation (XEXP (x, 0),
8244 : next_code),
8245 : 0, NULL_RTX, i,
8246 : true, false, in_code == COMPARE);
8247 :
8248 : /* If we are in a comparison and this is an AND with a power of two,
8249 : convert this into the appropriate bit extract. */
8250 2557613 : else if (in_code == COMPARE
8251 466144 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8252 2638115 : && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8253 80502 : new_rtx = make_extraction (mode,
8254 : make_compound_operation (XEXP (x, 0),
8255 : next_code),
8256 : i, NULL_RTX, 1, true, false, true);
8257 :
8258 : /* If the one operand is a paradoxical subreg of a register or memory and
8259 : the constant (limited to the smaller mode) has only zero bits where
8260 : the sub expression has known zero bits, this can be expressed as
8261 : a zero_extend. */
8262 2477111 : else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8263 : {
8264 73928 : rtx sub;
8265 :
8266 73928 : sub = XEXP (XEXP (x, 0), 0);
8267 73928 : machine_mode sub_mode = GET_MODE (sub);
8268 73928 : int sub_width;
8269 30327 : if ((REG_P (sub) || MEM_P (sub))
8270 44467 : && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8271 44467 : && sub_width < mode_width
8272 73928 : && (!WORD_REGISTER_OPERATIONS
8273 : || sub_width >= BITS_PER_WORD
8274 : /* On WORD_REGISTER_OPERATIONS targets the bits
8275 : beyond sub_mode aren't considered undefined,
8276 : so optimize only if it is a MEM load when MEM loads
8277 : zero extend, because then the upper bits are all zero. */
8278 : || (MEM_P (sub)
8279 : && load_extend_op (sub_mode) == ZERO_EXTEND)))
8280 : {
8281 20956 : unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8282 20956 : unsigned HOST_WIDE_INT mask;
8283 :
8284 : /* Original AND constant with all the known zero bits set. */
8285 20956 : mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8286 20956 : if ((mask & mode_mask) == mode_mask)
8287 : {
8288 16985 : new_rtx = make_compound_operation (sub, next_code);
8289 16985 : new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8290 : true, false, in_code == COMPARE);
8291 : }
8292 : }
8293 : }
8294 :
8295 : break;
8296 :
8297 1949178 : case LSHIFTRT:
8298 : /* If the sign bit is known to be zero, replace this with an
8299 : arithmetic shift. */
8300 1949178 : if (have_insn_for (ASHIFTRT, mode)
8301 1949178 : && ! have_insn_for (LSHIFTRT, mode)
8302 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
8303 1949178 : && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8304 : {
8305 0 : new_rtx = gen_rtx_ASHIFTRT (mode,
8306 : make_compound_operation (XEXP (x, 0),
8307 : next_code),
8308 : XEXP (x, 1));
8309 0 : break;
8310 : }
8311 :
8312 : /* fall through */
8313 :
8314 4835160 : case ASHIFTRT:
8315 4835160 : lhs = XEXP (x, 0);
8316 4835160 : rhs = XEXP (x, 1);
8317 :
8318 : /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8319 : this is a SIGN_EXTRACT. */
8320 4835160 : if (CONST_INT_P (rhs)
8321 4656687 : && GET_CODE (lhs) == ASHIFT
8322 1147736 : && CONST_INT_P (XEXP (lhs, 1))
8323 1142421 : && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8324 892516 : && INTVAL (XEXP (lhs, 1)) >= 0
8325 892512 : && INTVAL (rhs) < mode_width)
8326 : {
8327 892511 : new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8328 892511 : new_rtx = make_extraction (mode, new_rtx,
8329 892511 : INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8330 892511 : NULL_RTX, mode_width - INTVAL (rhs),
8331 : code == LSHIFTRT, false,
8332 : in_code == COMPARE);
8333 892511 : break;
8334 : }
8335 :
8336 : /* See if we have operations between an ASHIFTRT and an ASHIFT.
8337 : If so, try to merge the shifts into a SIGN_EXTEND. We could
8338 : also do this for some cases of SIGN_EXTRACT, but it doesn't
8339 : seem worth the effort; the case checked for occurs on Alpha. */
8340 :
8341 3942649 : if (!OBJECT_P (lhs)
8342 1551057 : && ! (GET_CODE (lhs) == SUBREG
8343 88538 : && (OBJECT_P (SUBREG_REG (lhs))))
8344 1477380 : && CONST_INT_P (rhs)
8345 1453221 : && INTVAL (rhs) >= 0
8346 1453221 : && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8347 1447204 : && INTVAL (rhs) < mode_width
8348 5389852 : && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8349 259128 : new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8350 : next_code),
8351 259128 : 0, NULL_RTX, mode_width - INTVAL (rhs),
8352 : code == LSHIFTRT, false, in_code == COMPARE);
8353 :
8354 : break;
8355 :
8356 9663821 : case SUBREG:
8357 : /* Call ourselves recursively on the inner expression. If we are
8358 : narrowing the object and it has a different RTL code from
8359 : what it originally did, do this SUBREG as a force_to_mode. */
8360 9663821 : {
8361 9663821 : rtx inner = SUBREG_REG (x), simplified;
8362 9663821 : enum rtx_code subreg_code = in_code;
8363 :
8364 : /* If the SUBREG is masking of a logical right shift,
8365 : make an extraction. */
8366 9663821 : if (GET_CODE (inner) == LSHIFTRT
8367 9674337 : && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8368 598206 : && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8369 295328 : && CONST_INT_P (XEXP (inner, 1))
8370 289953 : && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8371 9953774 : && subreg_lowpart_p (x))
8372 : {
8373 288587 : new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8374 288587 : int width = GET_MODE_PRECISION (inner_mode)
8375 288587 : - INTVAL (XEXP (inner, 1));
8376 288587 : if (width > mode_width)
8377 : width = mode_width;
8378 288587 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8379 : width, true, false, in_code == COMPARE);
8380 288587 : break;
8381 : }
8382 :
8383 : /* If in_code is COMPARE, it isn't always safe to pass it through
8384 : to the recursive make_compound_operation call. */
8385 9375234 : if (subreg_code == COMPARE
8386 9375234 : && (!subreg_lowpart_p (x)
8387 237656 : || GET_CODE (inner) == SUBREG
8388 : /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8389 : is (const_int 0), rather than
8390 : (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8391 : Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8392 : for non-equality comparisons against 0 is not equivalent
8393 : to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8394 237656 : || (GET_CODE (inner) == AND
8395 1195 : && CONST_INT_P (XEXP (inner, 1))
8396 143 : && partial_subreg_p (x)
8397 286 : && exact_log2 (UINTVAL (XEXP (inner, 1)))
8398 143 : >= GET_MODE_BITSIZE (mode) - 1)))
8399 : subreg_code = SET;
8400 :
8401 9375234 : tem = make_compound_operation (inner, subreg_code);
8402 :
8403 : /* TEM's code might be CLOBBER if combine_simplify_rtx
8404 : could not transform a subexpression, e.g. a volatile MEM.
8405 : simplify_subreg cannot be called with clobber, so bail out. */
8406 9375234 : if (GET_CODE (tem) == CLOBBER)
8407 : return NULL_RTX;
8408 :
8409 9375215 : simplified
8410 9375215 : = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8411 9375215 : if (simplified)
8412 16521 : tem = simplified;
8413 :
8414 9375215 : if (GET_CODE (tem) != GET_CODE (inner)
8415 22276 : && partial_subreg_p (x)
8416 9394306 : && subreg_lowpart_p (x))
8417 : {
8418 19075 : rtx newer
8419 19075 : = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8420 :
8421 : /* If we have something other than a SUBREG, we might have
8422 : done an expansion, so rerun ourselves. */
8423 19075 : if (GET_CODE (newer) != SUBREG)
8424 17071 : newer = make_compound_operation (newer, in_code);
8425 :
8426 : /* force_to_mode can expand compounds. If it just re-expanded
8427 : the compound, use gen_lowpart to convert to the desired
8428 : mode. */
8429 19075 : if (rtx_equal_p (newer, x)
8430 : /* Likewise if it re-expanded the compound only partially.
8431 : This happens for SUBREG of ZERO_EXTRACT if they extract
8432 : the same number of bits. */
8433 19075 : || (GET_CODE (newer) == SUBREG
8434 2149 : && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8435 2149 : || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8436 136 : && GET_CODE (inner) == AND
8437 56 : && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8438 1372 : return gen_lowpart (GET_MODE (x), tem);
8439 :
8440 : return newer;
8441 : }
8442 :
8443 9356140 : if (simplified)
8444 : return tem;
8445 : }
8446 : break;
8447 :
8448 : default:
8449 : break;
8450 : }
8451 :
8452 10561540 : if (new_rtx)
8453 5441703 : *x_ptr = gen_lowpart (mode, new_rtx);
8454 227634427 : *next_code_ptr = next_code;
8455 227634427 : return NULL_RTX;
8456 : }
8457 :
8458 : /* Look at the expression rooted at X. Look for expressions
8459 : equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8460 : Form these expressions.
8461 :
8462 : Return the new rtx, usually just X.
8463 :
8464 : Also, for machines like the VAX that don't have logical shift insns,
8465 : try to convert logical to arithmetic shift operations in cases where
8466 : they are equivalent. This undoes the canonicalizations to logical
8467 : shifts done elsewhere.
8468 :
8469 : We try, as much as possible, to re-use rtl expressions to save memory.
8470 :
8471 : IN_CODE says what kind of expression we are processing. Normally, it is
8472 : SET. In a memory address it is MEM. When processing the arguments of
8473 : a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8474 : precisely it is an equality comparison against zero. */
8475 :
8476 : rtx
8477 486230925 : make_compound_operation (rtx x, enum rtx_code in_code)
8478 : {
8479 486230925 : enum rtx_code code = GET_CODE (x);
8480 486230925 : const char *fmt;
8481 486230925 : int i, j;
8482 486230925 : enum rtx_code next_code;
8483 486230925 : rtx new_rtx, tem;
8484 :
8485 : /* Select the code to be used in recursive calls. Once we are inside an
8486 : address, we stay there. If we have a comparison, set to COMPARE,
8487 : but once inside, go back to our default of SET. */
8488 :
8489 486230925 : next_code = (code == MEM ? MEM
8490 457624141 : : ((code == COMPARE || COMPARISON_P (x))
8491 478488330 : && XEXP (x, 1) == const0_rtx) ? COMPARE
8492 449356036 : : in_code == COMPARE || in_code == EQ ? SET : in_code);
8493 :
8494 486230925 : scalar_int_mode mode;
8495 486230925 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8496 : {
8497 282934567 : rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8498 : &next_code);
8499 282934567 : if (new_rtx)
8500 : return new_rtx;
8501 227634446 : code = GET_CODE (x);
8502 : }
8503 :
8504 : /* Now recursively process each operand of this operation. We need to
8505 : handle ZERO_EXTEND specially so that we don't lose track of the
8506 : inner mode. */
8507 430930804 : if (code == ZERO_EXTEND)
8508 : {
8509 3355546 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8510 6711092 : tem = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8511 3355546 : new_rtx, GET_MODE (XEXP (x, 0)));
8512 3355546 : if (tem)
8513 : return tem;
8514 3345016 : SUBST (XEXP (x, 0), new_rtx);
8515 3345016 : return x;
8516 : }
8517 :
8518 427575258 : fmt = GET_RTX_FORMAT (code);
8519 995082742 : for (i = 0; i < GET_RTX_LENGTH (code); i++)
8520 567507484 : if (fmt[i] == 'e')
8521 : {
8522 217742201 : new_rtx = make_compound_operation (XEXP (x, i), next_code);
8523 217742201 : SUBST (XEXP (x, i), new_rtx);
8524 : }
8525 349765283 : else if (fmt[i] == 'E')
8526 27905877 : for (j = 0; j < XVECLEN (x, i); j++)
8527 : {
8528 20248340 : new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8529 20248340 : SUBST (XVECEXP (x, i, j), new_rtx);
8530 : }
8531 :
8532 427575258 : maybe_swap_commutative_operands (x);
8533 427575258 : return x;
8534 : }
8535 :
8536 : /* Given M see if it is a value that would select a field of bits
8537 : within an item, but not the entire word. Return -1 if not.
8538 : Otherwise, return the starting position of the field, where 0 is the
8539 : low-order bit.
8540 :
8541 : *PLEN is set to the length of the field. */
8542 :
8543 : static int
8544 8670 : get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8545 : {
8546 : /* Get the bit number of the first 1 bit from the right, -1 if none. */
8547 8670 : int pos = m ? ctz_hwi (m) : -1;
8548 8670 : int len = 0;
8549 :
8550 8670 : if (pos >= 0)
8551 : /* Now shift off the low-order zero bits and see if we have a
8552 : power of two minus 1. */
8553 8670 : len = exact_log2 ((m >> pos) + 1);
8554 :
8555 6439 : if (len <= 0)
8556 : pos = -1;
8557 :
8558 8670 : *plen = len;
8559 8670 : return pos;
8560 : }
8561 :
8562 : /* If X refers to a register that equals REG in value, replace these
8563 : references with REG. */
8564 : static rtx
8565 8426 : canon_reg_for_combine (rtx x, rtx reg)
8566 : {
8567 8426 : rtx op0, op1, op2;
8568 8426 : const char *fmt;
8569 8426 : int i;
8570 8426 : bool copied;
8571 :
8572 8426 : enum rtx_code code = GET_CODE (x);
8573 8426 : switch (GET_RTX_CLASS (code))
8574 : {
8575 0 : case RTX_UNARY:
8576 0 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8577 0 : if (op0 != XEXP (x, 0))
8578 0 : return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8579 0 : GET_MODE (reg));
8580 : break;
8581 :
8582 1467 : case RTX_BIN_ARITH:
8583 1467 : case RTX_COMM_ARITH:
8584 1467 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8585 1467 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8586 1467 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8587 0 : return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8588 : break;
8589 :
8590 17 : case RTX_COMPARE:
8591 17 : case RTX_COMM_COMPARE:
8592 17 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8593 17 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8594 17 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8595 0 : return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8596 0 : GET_MODE (op0), op0, op1);
8597 : break;
8598 :
8599 2 : case RTX_TERNARY:
8600 2 : case RTX_BITFIELD_OPS:
8601 2 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8602 2 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8603 2 : op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8604 2 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8605 0 : return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8606 0 : GET_MODE (op0), op0, op1, op2);
8607 : /* FALLTHRU */
8608 :
8609 5076 : case RTX_OBJ:
8610 5076 : if (REG_P (x))
8611 : {
8612 5068 : if (rtx_equal_p (get_last_value (reg), x)
8613 5068 : || rtx_equal_p (reg, get_last_value (x)))
8614 0 : return reg;
8615 : else
8616 : break;
8617 : }
8618 :
8619 : /* fall through */
8620 :
8621 1874 : default:
8622 1874 : fmt = GET_RTX_FORMAT (code);
8623 1874 : copied = false;
8624 3816 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8625 1942 : if (fmt[i] == 'e')
8626 : {
8627 70 : rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8628 70 : if (op != XEXP (x, i))
8629 : {
8630 0 : if (!copied)
8631 : {
8632 0 : copied = true;
8633 0 : x = copy_rtx (x);
8634 : }
8635 0 : XEXP (x, i) = op;
8636 : }
8637 : }
8638 1872 : else if (fmt[i] == 'E')
8639 : {
8640 : int j;
8641 0 : for (j = 0; j < XVECLEN (x, i); j++)
8642 : {
8643 0 : rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8644 0 : if (op != XVECEXP (x, i, j))
8645 : {
8646 0 : if (!copied)
8647 : {
8648 0 : copied = true;
8649 0 : x = copy_rtx (x);
8650 : }
8651 0 : XVECEXP (x, i, j) = op;
8652 : }
8653 : }
8654 : }
8655 :
8656 : break;
8657 : }
8658 :
8659 : return x;
8660 : }
8661 :
8662 : /* Return X converted to MODE. If the value is already truncated to
8663 : MODE we can just return a subreg even though in the general case we
8664 : would need an explicit truncation. */
8665 :
8666 : static rtx
8667 118653343 : gen_lowpart_or_truncate (machine_mode mode, rtx x)
8668 : {
8669 118653343 : if (!CONST_INT_P (x)
8670 113003980 : && partial_subreg_p (mode, GET_MODE (x))
8671 118653343 : && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8672 118653343 : && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8673 : {
8674 : /* Bit-cast X into an integer mode. */
8675 0 : if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8676 0 : x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8677 0 : x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8678 0 : x, GET_MODE (x));
8679 : }
8680 :
8681 118653343 : return gen_lowpart (mode, x);
8682 : }
8683 :
8684 : /* See if X can be simplified knowing that we will only refer to it in
8685 : MODE and will only refer to those bits that are nonzero in MASK.
8686 : If other bits are being computed or if masking operations are done
8687 : that select a superset of the bits in MASK, they can sometimes be
8688 : ignored.
8689 :
8690 : Return a possibly simplified expression, but always convert X to
8691 : MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8692 :
8693 : If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8694 : are all off in X. This is used when X will be complemented, by either
8695 : NOT, NEG, or XOR. */
8696 :
8697 : static rtx
8698 82047207 : force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8699 : bool just_select)
8700 : {
8701 89119922 : enum rtx_code code = GET_CODE (x);
8702 89119922 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8703 89119922 : machine_mode op_mode;
8704 89119922 : unsigned HOST_WIDE_INT nonzero;
8705 :
8706 : /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8707 : code below will do the wrong thing since the mode of such an
8708 : expression is VOIDmode.
8709 :
8710 : Also do nothing if X is a CLOBBER; this can happen if X was
8711 : the return value from a call to gen_lowpart. */
8712 89119922 : if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8713 : return x;
8714 :
8715 : /* We want to perform the operation in its present mode unless we know
8716 : that the operation is valid in MODE, in which case we do the operation
8717 : in MODE. */
8718 145846170 : op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8719 82903476 : && have_insn_for (code, mode))
8720 139708493 : ? mode : GET_MODE (x));
8721 :
8722 : /* It is not valid to do a right-shift in a narrower mode
8723 : than the one it came in with. */
8724 89041153 : if ((code == LSHIFTRT || code == ASHIFTRT)
8725 89041153 : && partial_subreg_p (mode, GET_MODE (x)))
8726 396576 : op_mode = GET_MODE (x);
8727 :
8728 : /* Truncate MASK to fit OP_MODE. */
8729 89041153 : if (op_mode)
8730 82977552 : mask &= GET_MODE_MASK (op_mode);
8731 :
8732 : /* Determine what bits of X are guaranteed to be (non)zero. */
8733 89041153 : nonzero = nonzero_bits (x, mode);
8734 :
8735 : /* If none of the bits in X are needed, return a zero. */
8736 89041153 : if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8737 675353 : x = const0_rtx;
8738 :
8739 : /* If X is a CONST_INT, return a new one. Do this here since the
8740 : test below will fail. */
8741 89041153 : if (CONST_INT_P (x))
8742 : {
8743 6275027 : if (SCALAR_INT_MODE_P (mode))
8744 6275027 : return gen_int_mode (INTVAL (x) & mask, mode);
8745 : else
8746 : {
8747 0 : x = GEN_INT (INTVAL (x) & mask);
8748 0 : return gen_lowpart_common (mode, x);
8749 : }
8750 : }
8751 :
8752 : /* If X is narrower than MODE and we want all the bits in X's mode, just
8753 : get X in the proper mode. */
8754 82766126 : if (paradoxical_subreg_p (mode, GET_MODE (x))
8755 82766126 : && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8756 3434546 : return gen_lowpart (mode, x);
8757 :
8758 : /* We can ignore the effect of a SUBREG if it narrows the mode or
8759 : if the constant masks to zero all the bits the mode doesn't have. */
8760 79331580 : if (GET_CODE (x) == SUBREG
8761 7264156 : && subreg_lowpart_p (x)
8762 86441057 : && (partial_subreg_p (x)
8763 5322489 : || (mask
8764 5322489 : & GET_MODE_MASK (GET_MODE (x))
8765 5322489 : & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8766 7072715 : return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8767 :
8768 72258865 : scalar_int_mode int_mode, xmode;
8769 72258865 : if (is_a <scalar_int_mode> (mode, &int_mode)
8770 72258865 : && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8771 : /* OP_MODE is either MODE or XMODE, so it must be a scalar
8772 : integer too. */
8773 72220953 : return force_int_to_mode (x, int_mode, xmode,
8774 : as_a <scalar_int_mode> (op_mode),
8775 72220953 : mask, just_select);
8776 :
8777 37912 : return gen_lowpart_or_truncate (mode, x);
8778 : }
8779 :
8780 : /* Subroutine of force_to_mode that handles cases in which both X and
8781 : the result are scalar integers. MODE is the mode of the result,
8782 : XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8783 : is preferred for simplified versions of X. The other arguments
8784 : are as for force_to_mode. */
8785 :
8786 : static rtx
8787 72220953 : force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8788 : scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8789 : bool just_select)
8790 : {
8791 72220953 : enum rtx_code code = GET_CODE (x);
8792 72220953 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8793 72220953 : unsigned HOST_WIDE_INT fuller_mask;
8794 72220953 : rtx op0, op1, temp;
8795 72220953 : poly_int64 const_op0;
8796 :
8797 : /* When we have an arithmetic operation, or a shift whose count we
8798 : do not know, we need to assume that all bits up to the highest-order
8799 : bit in MASK will be needed. This is how we form such a mask. */
8800 72220953 : if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8801 : fuller_mask = HOST_WIDE_INT_M1U;
8802 : else
8803 78709037 : fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) - 1);
8804 :
8805 72220953 : switch (code)
8806 : {
8807 : case CLOBBER:
8808 : /* If X is a (clobber (const_int)), return it since we know we are
8809 : generating something that won't match. */
8810 : return x;
8811 :
8812 323888 : case SIGN_EXTEND:
8813 323888 : case ZERO_EXTEND:
8814 323888 : case ZERO_EXTRACT:
8815 323888 : case SIGN_EXTRACT:
8816 323888 : x = expand_compound_operation (x);
8817 323888 : if (GET_CODE (x) != code)
8818 196279 : return force_to_mode (x, mode, mask, next_select);
8819 : break;
8820 :
8821 149 : case TRUNCATE:
8822 : /* Similarly for a truncate. */
8823 149 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8824 :
8825 3581342 : case AND:
8826 : /* If this is an AND with a constant, convert it into an AND
8827 : whose constant is the AND of that constant with MASK. If it
8828 : remains an AND of MASK, delete it since it is redundant. */
8829 :
8830 3581342 : if (CONST_INT_P (XEXP (x, 1)))
8831 : {
8832 5758322 : x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8833 2879161 : mask & INTVAL (XEXP (x, 1)));
8834 2879161 : xmode = op_mode;
8835 :
8836 : /* If X is still an AND, see if it is an AND with a mask that
8837 : is just some low-order bits. If so, and it is MASK, we don't
8838 : need it. */
8839 :
8840 2853414 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8841 5732575 : && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8842 37816 : x = XEXP (x, 0);
8843 :
8844 : /* If it remains an AND, try making another AND with the bits
8845 : in the mode mask that aren't in MASK turned on. If the
8846 : constant in the AND is wide enough, this might make a
8847 : cheaper constant. */
8848 :
8849 2815688 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8850 2815598 : && GET_MODE_MASK (xmode) != mask
8851 2983650 : && HWI_COMPUTABLE_MODE_P (xmode))
8852 : {
8853 104489 : unsigned HOST_WIDE_INT cval
8854 104489 : = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8855 104489 : rtx y;
8856 :
8857 104489 : y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8858 104489 : gen_int_mode (cval, xmode));
8859 104489 : if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8860 104489 : < set_src_cost (x, xmode, optimize_this_for_speed_p))
8861 71915896 : x = y;
8862 : }
8863 :
8864 : break;
8865 : }
8866 :
8867 702181 : goto binop;
8868 :
8869 9981441 : case PLUS:
8870 : /* In (and (plus FOO C1) M), if M is a mask that just turns off
8871 : low-order bits (as in an alignment operation) and FOO is already
8872 : aligned to that boundary, mask C1 to that boundary as well.
8873 : This may eliminate that PLUS and, later, the AND. */
8874 :
8875 9981441 : {
8876 9981441 : unsigned int width = GET_MODE_PRECISION (mode);
8877 9981441 : unsigned HOST_WIDE_INT smask = mask;
8878 :
8879 : /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8880 : number, sign extend it. */
8881 :
8882 9981441 : if (width < HOST_BITS_PER_WIDE_INT
8883 3131016 : && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8884 2805898 : smask |= HOST_WIDE_INT_M1U << width;
8885 :
8886 9981441 : if (CONST_INT_P (XEXP (x, 1))
8887 3718227 : && pow2p_hwi (- smask)
8888 3191202 : && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8889 12781143 : && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8890 10919 : return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8891 10919 : (INTVAL (XEXP (x, 1)) & smask)),
8892 : mode, smask, next_select);
8893 : }
8894 :
8895 : /* fall through */
8896 :
8897 12053128 : case MULT:
8898 : /* Substituting into the operands of a widening MULT is not likely to
8899 : create RTL matching a machine insn. */
8900 12053128 : if (code == MULT
8901 2082606 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8902 2082606 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8903 89005 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8904 89005 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8905 48379 : && REG_P (XEXP (XEXP (x, 0), 0))
8906 42196 : && REG_P (XEXP (XEXP (x, 1), 0)))
8907 34712 : return gen_lowpart_or_truncate (mode, x);
8908 :
8909 : /* For PLUS, MINUS and MULT, we need any bits less significant than the
8910 : most significant bit in MASK since carries from those bits will
8911 : affect the bits we are interested in. */
8912 12018416 : mask = fuller_mask;
8913 12018416 : goto binop;
8914 :
8915 2405329 : case MINUS:
8916 : /* If X is (minus C Y) where C's least set bit is larger than any bit
8917 : in the mask, then we may replace with (neg Y). */
8918 2405329 : if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8919 151012 : && known_alignment (poly_uint64 (const_op0)) > mask)
8920 : {
8921 30 : x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8922 30 : return force_to_mode (x, mode, mask, next_select);
8923 : }
8924 :
8925 : /* Similarly, if C contains every bit in the fuller_mask, then we may
8926 : replace with (not Y). */
8927 2405299 : if (CONST_INT_P (XEXP (x, 0))
8928 150982 : && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8929 : {
8930 326 : x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8931 326 : return force_to_mode (x, mode, mask, next_select);
8932 : }
8933 :
8934 2404973 : mask = fuller_mask;
8935 2404973 : goto binop;
8936 :
8937 2240871 : case IOR:
8938 2240871 : case XOR:
8939 : /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8940 : LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8941 : operation which may be a bitfield extraction. Ensure that the
8942 : constant we form is not wider than the mode of X. */
8943 :
8944 2240871 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8945 62373 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8946 51648 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8947 51648 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8948 51648 : && CONST_INT_P (XEXP (x, 1))
8949 8863 : && ((INTVAL (XEXP (XEXP (x, 0), 1))
8950 17726 : + floor_log2 (INTVAL (XEXP (x, 1))))
8951 8863 : < GET_MODE_PRECISION (xmode))
8952 2240871 : && (UINTVAL (XEXP (x, 1))
8953 4538 : & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8954 : {
8955 8542 : temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8956 4271 : << INTVAL (XEXP (XEXP (x, 0), 1)),
8957 : xmode);
8958 8542 : temp = simplify_gen_binary (GET_CODE (x), xmode,
8959 4271 : XEXP (XEXP (x, 0), 0), temp);
8960 8542 : x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8961 4271 : XEXP (XEXP (x, 0), 1));
8962 4271 : return force_to_mode (x, mode, mask, next_select);
8963 : }
8964 :
8965 17362170 : binop:
8966 : /* For most binary operations, just propagate into the operation and
8967 : change the mode if we have an operation of that mode. */
8968 :
8969 17362170 : op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8970 17362170 : op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8971 :
8972 : /* If we ended up truncating both operands, truncate the result of the
8973 : operation instead. */
8974 17362170 : if (GET_CODE (op0) == TRUNCATE
8975 0 : && GET_CODE (op1) == TRUNCATE)
8976 : {
8977 0 : op0 = XEXP (op0, 0);
8978 0 : op1 = XEXP (op1, 0);
8979 : }
8980 :
8981 17362170 : op0 = gen_lowpart_or_truncate (op_mode, op0);
8982 17362170 : op1 = gen_lowpart_or_truncate (op_mode, op1);
8983 :
8984 17362170 : if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8985 : {
8986 2169411 : x = simplify_gen_binary (code, op_mode, op0, op1);
8987 2169411 : xmode = op_mode;
8988 : }
8989 : break;
8990 :
8991 4284230 : case ASHIFT:
8992 : /* For left shifts, do the same, but just for the first operand.
8993 : However, we cannot do anything with shifts where we cannot
8994 : guarantee that the counts are smaller than the size of the mode
8995 : because such a count will have a different meaning in a
8996 : wider mode. */
8997 :
8998 4078855 : if (! (CONST_INT_P (XEXP (x, 1))
8999 4078859 : && INTVAL (XEXP (x, 1)) >= 0
9000 4078855 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
9001 4286881 : && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
9002 205371 : && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
9003 205371 : < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
9004 : break;
9005 :
9006 : /* If the shift count is a constant and we can do arithmetic in
9007 : the mode of the shift, refine which bits we need. Otherwise, use the
9008 : conservative form of the mask. */
9009 4141781 : if (CONST_INT_P (XEXP (x, 1))
9010 4076208 : && INTVAL (XEXP (x, 1)) >= 0
9011 4076208 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9012 8217989 : && HWI_COMPUTABLE_MODE_P (op_mode))
9013 4075474 : mask >>= INTVAL (XEXP (x, 1));
9014 : else
9015 : mask = fuller_mask;
9016 :
9017 4141781 : op0 = gen_lowpart_or_truncate (op_mode,
9018 : force_to_mode (XEXP (x, 0), mode,
9019 : mask, next_select));
9020 :
9021 4141781 : if (op_mode != xmode || op0 != XEXP (x, 0))
9022 : {
9023 1020963 : x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9024 1020963 : xmode = op_mode;
9025 : }
9026 : break;
9027 :
9028 3053583 : case LSHIFTRT:
9029 : /* Here we can only do something if the shift count is a constant,
9030 : this shift constant is valid for the host, and we can do arithmetic
9031 : in OP_MODE. */
9032 :
9033 3053583 : if (CONST_INT_P (XEXP (x, 1))
9034 2942905 : && INTVAL (XEXP (x, 1)) >= 0
9035 2942904 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9036 5996469 : && HWI_COMPUTABLE_MODE_P (op_mode))
9037 : {
9038 2939552 : rtx inner = XEXP (x, 0);
9039 2939552 : unsigned HOST_WIDE_INT inner_mask;
9040 :
9041 : /* Select the mask of the bits we need for the shift operand. */
9042 2939552 : inner_mask = mask << INTVAL (XEXP (x, 1));
9043 :
9044 : /* We can only change the mode of the shift if we can do arithmetic
9045 : in the mode of the shift and INNER_MASK is no wider than the
9046 : width of X's mode. */
9047 2939552 : if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9048 260277 : op_mode = xmode;
9049 :
9050 2939552 : inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9051 :
9052 2939552 : if (xmode != op_mode || inner != XEXP (x, 0))
9053 : {
9054 792813 : x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9055 792813 : xmode = op_mode;
9056 : }
9057 : }
9058 :
9059 : /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9060 : shift and AND produces only copies of the sign bit (C2 is one less
9061 : than a power of two), we can do this with just a shift. */
9062 :
9063 3053583 : if (GET_CODE (x) == LSHIFTRT
9064 3053541 : && CONST_INT_P (XEXP (x, 1))
9065 : /* The shift puts one of the sign bit copies in the least significant
9066 : bit. */
9067 5885726 : && ((INTVAL (XEXP (x, 1))
9068 2942863 : + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9069 2942863 : >= GET_MODE_PRECISION (xmode))
9070 224159 : && pow2p_hwi (mask + 1)
9071 : /* Number of bits left after the shift must be more than the mask
9072 : needs. */
9073 78558 : && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9074 78558 : <= GET_MODE_PRECISION (xmode))
9075 : /* Must be more sign bit copies than the mask needs. */
9076 3082806 : && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9077 29223 : >= exact_log2 (mask + 1)))
9078 : {
9079 29223 : int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9080 29223 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9081 29223 : gen_int_shift_amount (xmode, nbits));
9082 : }
9083 3053583 : goto shiftrt;
9084 :
9085 2045058 : case ASHIFTRT:
9086 : /* If we are just looking for the sign bit, we don't need this shift at
9087 : all, even if it has a variable count. */
9088 2045058 : if (val_signbit_p (xmode, mask))
9089 1303 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9090 :
9091 : /* If this is a shift by a constant, get a mask that contains those bits
9092 : that are not copies of the sign bit. We then have two cases: If
9093 : MASK only includes those bits, this can be a logical shift, which may
9094 : allow simplifications. If MASK is a single-bit field not within
9095 : those bits, we are requesting a copy of the sign bit and hence can
9096 : shift the sign bit to the appropriate location. */
9097 :
9098 2043755 : if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9099 1998450 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9100 : {
9101 1998339 : unsigned HOST_WIDE_INT nonzero;
9102 1998339 : int i;
9103 :
9104 : /* If the considered data is wider than HOST_WIDE_INT, we can't
9105 : represent a mask for all its bits in a single scalar.
9106 : But we only care about the lower bits, so calculate these. */
9107 :
9108 1998339 : if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9109 : {
9110 406 : nonzero = HOST_WIDE_INT_M1U;
9111 :
9112 : /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9113 : is the number of bits a full-width mask would have set.
9114 : We need only shift if these are fewer than nonzero can
9115 : hold. If not, we must keep all bits set in nonzero. */
9116 :
9117 406 : if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9118 : < HOST_BITS_PER_WIDE_INT)
9119 0 : nonzero >>= INTVAL (XEXP (x, 1))
9120 0 : + HOST_BITS_PER_WIDE_INT
9121 0 : - GET_MODE_PRECISION (xmode);
9122 : }
9123 : else
9124 : {
9125 1997933 : nonzero = GET_MODE_MASK (xmode);
9126 1997933 : nonzero >>= INTVAL (XEXP (x, 1));
9127 : }
9128 :
9129 1998339 : if ((mask & ~nonzero) == 0)
9130 : {
9131 49182 : x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9132 : XEXP (x, 0), INTVAL (XEXP (x, 1)));
9133 49182 : if (GET_CODE (x) != ASHIFTRT)
9134 49182 : return force_to_mode (x, mode, mask, next_select);
9135 : }
9136 :
9137 1949157 : else if ((i = exact_log2 (mask)) >= 0)
9138 : {
9139 190 : x = simplify_shift_const
9140 380 : (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9141 190 : GET_MODE_PRECISION (xmode) - 1 - i);
9142 :
9143 190 : if (GET_CODE (x) != ASHIFTRT)
9144 190 : return force_to_mode (x, mode, mask, next_select);
9145 : }
9146 : }
9147 :
9148 : /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9149 : even if the shift count isn't a constant. */
9150 1994383 : if (mask == 1)
9151 3093 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9152 :
9153 1991290 : shiftrt:
9154 :
9155 : /* If this is a zero- or sign-extension operation that just affects bits
9156 : we don't care about, remove it. Be sure the call above returned
9157 : something that is still a shift. */
9158 :
9159 5047966 : if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9160 5047924 : && CONST_INT_P (XEXP (x, 1))
9161 4891941 : && INTVAL (XEXP (x, 1)) >= 0
9162 4891940 : && (INTVAL (XEXP (x, 1))
9163 9783880 : <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9164 1765670 : && GET_CODE (XEXP (x, 0)) == ASHIFT
9165 5048885 : && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9166 778 : return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, next_select);
9167 :
9168 : break;
9169 :
9170 36952 : case ROTATE:
9171 36952 : case ROTATERT:
9172 : /* If the shift count is constant and we can do computations
9173 : in the mode of X, compute where the bits we care about are.
9174 : Otherwise, we can't do anything. Don't change the mode of
9175 : the shift or propagate MODE into the shift, though. */
9176 36952 : if (CONST_INT_P (XEXP (x, 1))
9177 26628 : && INTVAL (XEXP (x, 1)) >= 0)
9178 : {
9179 26626 : temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9180 26626 : xmode, gen_int_mode (mask, xmode),
9181 : XEXP (x, 1));
9182 26626 : if (temp && CONST_INT_P (temp))
9183 26626 : x = simplify_gen_binary (code, xmode,
9184 : force_to_mode (XEXP (x, 0), xmode,
9185 26626 : INTVAL (temp), next_select),
9186 : XEXP (x, 1));
9187 : }
9188 : break;
9189 :
9190 160142 : case NEG:
9191 : /* If we just want the low-order bit, the NEG isn't needed since it
9192 : won't change the low-order bit. */
9193 160142 : if (mask == 1)
9194 364 : return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9195 :
9196 : /* We need any bits less significant than the most significant bit in
9197 : MASK since carries from those bits will affect the bits we are
9198 : interested in. */
9199 159778 : mask = fuller_mask;
9200 159778 : goto unop;
9201 :
9202 461146 : case NOT:
9203 : /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9204 : same as the XOR case above. Ensure that the constant we form is not
9205 : wider than the mode of X. */
9206 :
9207 461146 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9208 21040 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9209 20467 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9210 40934 : && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9211 20467 : < GET_MODE_PRECISION (xmode))
9212 467700 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9213 : {
9214 6554 : temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9215 6554 : temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9216 13108 : x = simplify_gen_binary (LSHIFTRT, xmode,
9217 6554 : temp, XEXP (XEXP (x, 0), 1));
9218 :
9219 6554 : return force_to_mode (x, mode, mask, next_select);
9220 : }
9221 :
9222 : /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9223 : use the full mask inside the NOT. */
9224 : mask = fuller_mask;
9225 :
9226 614370 : unop:
9227 614370 : op0 = gen_lowpart_or_truncate (op_mode,
9228 : force_to_mode (XEXP (x, 0), mode, mask,
9229 : next_select));
9230 614370 : if (op_mode != xmode || op0 != XEXP (x, 0))
9231 : {
9232 79883 : x = simplify_gen_unary (code, op_mode, op0, op_mode);
9233 79883 : xmode = op_mode;
9234 : }
9235 : break;
9236 :
9237 584224 : case NE:
9238 : /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9239 : in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9240 : which is equal to STORE_FLAG_VALUE. */
9241 584224 : if ((mask & ~STORE_FLAG_VALUE) == 0
9242 2412 : && XEXP (x, 1) == const0_rtx
9243 2391 : && GET_MODE (XEXP (x, 0)) == mode
9244 9 : && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9245 584224 : && (nonzero_bits (XEXP (x, 0), mode)
9246 : == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9247 0 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9248 :
9249 : break;
9250 :
9251 1633004 : case IF_THEN_ELSE:
9252 : /* We have no way of knowing if the IF_THEN_ELSE can itself be
9253 : written in a narrower mode. We play it safe and do not do so. */
9254 :
9255 1633004 : op0 = gen_lowpart_or_truncate (xmode,
9256 : force_to_mode (XEXP (x, 1), mode,
9257 : mask, next_select));
9258 1633004 : op1 = gen_lowpart_or_truncate (xmode,
9259 : force_to_mode (XEXP (x, 2), mode,
9260 : mask, next_select));
9261 1633004 : if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9262 260532 : x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9263 260532 : GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9264 : op0, op1);
9265 : break;
9266 :
9267 : default:
9268 : break;
9269 : }
9270 :
9271 : /* Ensure we return a value of the proper mode. */
9272 71915896 : return gen_lowpart_or_truncate (mode, x);
9273 : }
9274 :
9275 : /* Return nonzero if X is an expression that has one of two values depending on
9276 : whether some other value is zero or nonzero. In that case, we return the
9277 : value that is being tested, *PTRUE is set to the value if the rtx being
9278 : returned has a nonzero value, and *PFALSE is set to the other alternative.
9279 :
9280 : If we return zero, we set *PTRUE and *PFALSE to X. */
9281 :
9282 : static rtx
9283 242509744 : if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9284 : {
9285 242509744 : machine_mode mode = GET_MODE (x);
9286 242509744 : enum rtx_code code = GET_CODE (x);
9287 242509744 : rtx cond0, cond1, true0, true1, false0, false1;
9288 242509744 : unsigned HOST_WIDE_INT nz;
9289 242509744 : scalar_int_mode int_mode;
9290 :
9291 : /* If we are comparing a value against zero, we are done. */
9292 242509744 : if ((code == NE || code == EQ)
9293 2695461 : && XEXP (x, 1) == const0_rtx)
9294 : {
9295 1643403 : *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9296 1643403 : *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9297 1643403 : return XEXP (x, 0);
9298 : }
9299 :
9300 : /* If this is a unary operation whose operand has one of two values, apply
9301 : our opcode to compute those values. */
9302 240866341 : else if (UNARY_P (x)
9303 240866341 : && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9304 : {
9305 488540 : *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9306 977080 : *pfalse = simplify_gen_unary (code, mode, false0,
9307 488540 : GET_MODE (XEXP (x, 0)));
9308 488540 : return cond0;
9309 : }
9310 :
9311 : /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9312 : make can't possibly match and would suppress other optimizations. */
9313 240377801 : else if (code == COMPARE)
9314 : ;
9315 :
9316 : /* If this is a binary operation, see if either side has only one of two
9317 : values. If either one does or if both do and they are conditional on
9318 : the same value, compute the new true and false values. */
9319 235985615 : else if (BINARY_P (x))
9320 : {
9321 87183782 : rtx op0 = XEXP (x, 0);
9322 87183782 : rtx op1 = XEXP (x, 1);
9323 87183782 : cond0 = if_then_else_cond (op0, &true0, &false0);
9324 87183782 : cond1 = if_then_else_cond (op1, &true1, &false1);
9325 :
9326 590522 : if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9327 87719750 : && (REG_P (op0) || REG_P (op1)))
9328 : {
9329 : /* Try to enable a simplification by undoing work done by
9330 : if_then_else_cond if it converted a REG into something more
9331 : complex. */
9332 468307 : if (REG_P (op0))
9333 : {
9334 119320 : cond0 = 0;
9335 119320 : true0 = false0 = op0;
9336 : }
9337 : else
9338 : {
9339 348987 : cond1 = 0;
9340 348987 : true1 = false1 = op1;
9341 : }
9342 : }
9343 :
9344 87183782 : if ((cond0 != 0 || cond1 != 0)
9345 87183782 : && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9346 : {
9347 : /* If if_then_else_cond returned zero, then true/false are the
9348 : same rtl. We must copy one of them to prevent invalid rtl
9349 : sharing. */
9350 5040028 : if (cond0 == 0)
9351 1456665 : true0 = copy_rtx (true0);
9352 3583363 : else if (cond1 == 0)
9353 3528809 : true1 = copy_rtx (true1);
9354 :
9355 5040028 : if (COMPARISON_P (x))
9356 : {
9357 270341 : *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9358 : true0, true1);
9359 270341 : *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9360 : false0, false1);
9361 : }
9362 : else
9363 : {
9364 4769687 : *ptrue = simplify_gen_binary (code, mode, true0, true1);
9365 4769687 : *pfalse = simplify_gen_binary (code, mode, false0, false1);
9366 : }
9367 :
9368 5040028 : return cond0 ? cond0 : cond1;
9369 : }
9370 :
9371 : /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9372 : operands is zero when the other is nonzero, and vice-versa,
9373 : and STORE_FLAG_VALUE is 1 or -1. */
9374 :
9375 82143754 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9376 82143754 : && (code == PLUS || code == IOR || code == XOR || code == MINUS
9377 : || code == UMAX)
9378 33955741 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9379 : {
9380 38141 : rtx op0 = XEXP (XEXP (x, 0), 1);
9381 38141 : rtx op1 = XEXP (XEXP (x, 1), 1);
9382 :
9383 38141 : cond0 = XEXP (XEXP (x, 0), 0);
9384 38141 : cond1 = XEXP (XEXP (x, 1), 0);
9385 :
9386 38141 : if (COMPARISON_P (cond0)
9387 11 : && COMPARISON_P (cond1)
9388 0 : && SCALAR_INT_MODE_P (mode)
9389 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9390 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9391 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9392 0 : || ((swap_condition (GET_CODE (cond0))
9393 0 : == reversed_comparison_code (cond1, NULL))
9394 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9395 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9396 38141 : && ! side_effects_p (x))
9397 : {
9398 0 : *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9399 0 : *pfalse = simplify_gen_binary (MULT, mode,
9400 : (code == MINUS
9401 0 : ? simplify_gen_unary (NEG, mode,
9402 : op1, mode)
9403 : : op1),
9404 : const_true_rtx);
9405 0 : return cond0;
9406 : }
9407 : }
9408 :
9409 : /* Similarly for MULT, AND and UMIN, except that for these the result
9410 : is always zero. */
9411 82143754 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9412 82143754 : && (code == MULT || code == AND || code == UMIN)
9413 11826955 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9414 : {
9415 965 : cond0 = XEXP (XEXP (x, 0), 0);
9416 965 : cond1 = XEXP (XEXP (x, 1), 0);
9417 :
9418 965 : if (COMPARISON_P (cond0)
9419 0 : && COMPARISON_P (cond1)
9420 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9421 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9422 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9423 0 : || ((swap_condition (GET_CODE (cond0))
9424 0 : == reversed_comparison_code (cond1, NULL))
9425 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9426 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9427 965 : && ! side_effects_p (x))
9428 : {
9429 0 : *ptrue = *pfalse = const0_rtx;
9430 0 : return cond0;
9431 : }
9432 : }
9433 : }
9434 :
9435 148801833 : else if (code == IF_THEN_ELSE)
9436 : {
9437 : /* If we have IF_THEN_ELSE already, extract the condition and
9438 : canonicalize it if it is NE or EQ. */
9439 754564 : cond0 = XEXP (x, 0);
9440 754564 : *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9441 754564 : if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9442 263507 : return XEXP (cond0, 0);
9443 491057 : else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9444 : {
9445 34198 : *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9446 34198 : return XEXP (cond0, 0);
9447 : }
9448 : else
9449 : return cond0;
9450 : }
9451 :
9452 : /* If X is a SUBREG, we can narrow both the true and false values
9453 : if the inner expression, if there is a condition. */
9454 148047269 : else if (code == SUBREG
9455 148047269 : && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9456 : &false0)) != 0)
9457 : {
9458 1224794 : true0 = simplify_gen_subreg (mode, true0,
9459 612397 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9460 1224794 : false0 = simplify_gen_subreg (mode, false0,
9461 612397 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9462 612397 : if (true0 && false0)
9463 : {
9464 612397 : *ptrue = true0;
9465 612397 : *pfalse = false0;
9466 612397 : return cond0;
9467 : }
9468 : }
9469 :
9470 : /* If X is a constant, this isn't special and will cause confusions
9471 : if we treat it as such. Likewise if it is equivalent to a constant. */
9472 147434872 : else if (CONSTANT_P (x)
9473 147434872 : || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9474 : ;
9475 :
9476 : /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9477 : will be least confusing to the rest of the compiler. */
9478 99937341 : else if (mode == BImode)
9479 : {
9480 0 : *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9481 0 : return x;
9482 : }
9483 :
9484 : /* If X is known to be either 0 or -1, those are the true and
9485 : false values when testing X. */
9486 99937341 : else if (x == constm1_rtx || x == const0_rtx
9487 99937341 : || (is_a <scalar_int_mode> (mode, &int_mode)
9488 70772357 : && (num_sign_bit_copies (x, int_mode)
9489 70772357 : == GET_MODE_PRECISION (int_mode))))
9490 : {
9491 1006760 : *ptrue = constm1_rtx, *pfalse = const0_rtx;
9492 1006760 : return x;
9493 : }
9494 :
9495 : /* Likewise for 0 or a single bit. */
9496 98930581 : else if (HWI_COMPUTABLE_MODE_P (mode)
9497 66458669 : && pow2p_hwi (nz = nonzero_bits (x, mode)))
9498 : {
9499 1928561 : *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9500 1928561 : return x;
9501 : }
9502 :
9503 : /* Otherwise fail; show no condition with true and false values the same. */
9504 231035491 : *ptrue = *pfalse = x;
9505 231035491 : return 0;
9506 : }
9507 :
9508 : /* Return the value of expression X given the fact that condition COND
9509 : is known to be true when applied to REG as its first operand and VAL
9510 : as its second. X is known to not be shared and so can be modified in
9511 : place.
9512 :
9513 : We only handle the simplest cases, and specifically those cases that
9514 : arise with IF_THEN_ELSE expressions. */
9515 :
9516 : static rtx
9517 676839 : known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9518 : {
9519 676839 : enum rtx_code code = GET_CODE (x);
9520 676839 : const char *fmt;
9521 676839 : int i, j;
9522 :
9523 676839 : if (side_effects_p (x))
9524 : return x;
9525 :
9526 : /* If either operand of the condition is a floating point value,
9527 : then we have to avoid collapsing an EQ comparison. */
9528 676839 : if (cond == EQ
9529 125425 : && rtx_equal_p (x, reg)
9530 83102 : && ! FLOAT_MODE_P (GET_MODE (x))
9531 759941 : && ! FLOAT_MODE_P (GET_MODE (val)))
9532 : return val;
9533 :
9534 593737 : if (cond == UNEQ && rtx_equal_p (x, reg))
9535 : return val;
9536 :
9537 : /* If X is (abs REG) and we know something about REG's relationship
9538 : with zero, we may be able to simplify this. */
9539 :
9540 593737 : if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9541 3 : switch (cond)
9542 : {
9543 1 : case GE: case GT: case EQ:
9544 1 : return XEXP (x, 0);
9545 2 : case LT: case LE:
9546 4 : return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9547 : XEXP (x, 0),
9548 2 : GET_MODE (XEXP (x, 0)));
9549 : default:
9550 : break;
9551 : }
9552 :
9553 : /* The only other cases we handle are MIN, MAX, and comparisons if the
9554 : operands are the same as REG and VAL. */
9555 :
9556 593734 : else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9557 : {
9558 242636 : if (rtx_equal_p (XEXP (x, 0), val))
9559 : {
9560 2 : std::swap (val, reg);
9561 2 : cond = swap_condition (cond);
9562 : }
9563 :
9564 242636 : if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9565 : {
9566 221108 : if (COMPARISON_P (x))
9567 : {
9568 220895 : if (comparison_dominates_p (cond, code))
9569 1286 : return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9570 :
9571 219609 : code = reversed_comparison_code (x, NULL);
9572 219609 : if (code != UNKNOWN
9573 219609 : && comparison_dominates_p (cond, code))
9574 67 : return CONST0_RTX (GET_MODE (x));
9575 : else
9576 : return x;
9577 : }
9578 213 : else if (code == SMAX || code == SMIN
9579 213 : || code == UMIN || code == UMAX)
9580 : {
9581 45 : int unsignedp = (code == UMIN || code == UMAX);
9582 :
9583 : /* Do not reverse the condition when it is NE or EQ.
9584 : This is because we cannot conclude anything about
9585 : the value of 'SMAX (x, y)' when x is not equal to y,
9586 : but we can when x equals y. */
9587 45 : if ((code == SMAX || code == UMAX)
9588 42 : && ! (cond == EQ || cond == NE))
9589 9 : cond = reverse_condition (cond);
9590 :
9591 12 : switch (cond)
9592 : {
9593 2 : case GE: case GT:
9594 2 : return unsignedp ? x : XEXP (x, 1);
9595 10 : case LE: case LT:
9596 10 : return unsignedp ? x : XEXP (x, 0);
9597 0 : case GEU: case GTU:
9598 0 : return unsignedp ? XEXP (x, 1) : x;
9599 0 : case LEU: case LTU:
9600 0 : return unsignedp ? XEXP (x, 0) : x;
9601 : default:
9602 : break;
9603 : }
9604 : }
9605 : }
9606 : }
9607 351098 : else if (code == SUBREG)
9608 : {
9609 8923 : machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9610 8923 : rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9611 :
9612 8923 : if (SUBREG_REG (x) != r)
9613 : {
9614 : /* We must simplify subreg here, before we lose track of the
9615 : original inner_mode. */
9616 26 : new_rtx = simplify_subreg (GET_MODE (x), r,
9617 13 : inner_mode, SUBREG_BYTE (x));
9618 13 : if (new_rtx)
9619 : return new_rtx;
9620 : else
9621 13 : SUBST (SUBREG_REG (x), r);
9622 : }
9623 :
9624 : return x;
9625 : }
9626 : /* We don't have to handle SIGN_EXTEND here, because even in the
9627 : case of replacing something with a modeless CONST_INT, a
9628 : CONST_INT is already (supposed to be) a valid sign extension for
9629 : its narrower mode, which implies it's already properly
9630 : sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9631 : story is different. */
9632 342175 : else if (code == ZERO_EXTEND)
9633 : {
9634 1322 : machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9635 1322 : rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9636 :
9637 1322 : if (XEXP (x, 0) != r)
9638 : {
9639 : /* We must simplify the zero_extend here, before we lose
9640 : track of the original inner_mode. */
9641 0 : new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9642 : r, inner_mode);
9643 0 : if (new_rtx)
9644 : return new_rtx;
9645 : else
9646 0 : SUBST (XEXP (x, 0), r);
9647 : }
9648 :
9649 : return x;
9650 : }
9651 :
9652 362582 : fmt = GET_RTX_FORMAT (code);
9653 820263 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9654 : {
9655 457681 : if (fmt[i] == 'e')
9656 195430 : SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9657 262251 : else if (fmt[i] == 'E')
9658 15148 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9659 12212 : SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9660 : cond, reg, val));
9661 : }
9662 :
9663 : return x;
9664 : }
9665 :
9666 : /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9667 : assignment as a field assignment. */
9668 :
9669 : static bool
9670 460575 : rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9671 : {
9672 460575 : if (widen_x && GET_MODE (x) != GET_MODE (y))
9673 : {
9674 52107 : if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9675 : return false;
9676 52107 : if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9677 : return false;
9678 52107 : x = adjust_address_nv (x, GET_MODE (y),
9679 : byte_lowpart_offset (GET_MODE (y),
9680 : GET_MODE (x)));
9681 : }
9682 :
9683 460575 : if (x == y || rtx_equal_p (x, y))
9684 : return true;
9685 :
9686 451216 : if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9687 : return false;
9688 :
9689 : /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9690 : Note that all SUBREGs of MEM are paradoxical; otherwise they
9691 : would have been rewritten. */
9692 86901 : if (MEM_P (x) && GET_CODE (y) == SUBREG
9693 6313 : && MEM_P (SUBREG_REG (y))
9694 451214 : && rtx_equal_p (SUBREG_REG (y),
9695 0 : gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9696 : return true;
9697 :
9698 56209 : if (MEM_P (y) && GET_CODE (x) == SUBREG
9699 4666 : && MEM_P (SUBREG_REG (x))
9700 451404 : && rtx_equal_p (SUBREG_REG (x),
9701 190 : gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9702 : return true;
9703 :
9704 : /* We used to see if get_last_value of X and Y were the same but that's
9705 : not correct. In one direction, we'll cause the assignment to have
9706 : the wrong destination and in the case, we'll import a register into this
9707 : insn that might have already have been dead. So fail if none of the
9708 : above cases are true. */
9709 : return false;
9710 : }
9711 :
9712 : /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9713 : Return that assignment if so.
9714 :
9715 : We only handle the most common cases. */
9716 :
9717 : static rtx
9718 47849648 : make_field_assignment (rtx x)
9719 : {
9720 47849648 : rtx dest = SET_DEST (x);
9721 47849648 : rtx src = SET_SRC (x);
9722 47849648 : rtx assign;
9723 47849648 : rtx rhs, lhs;
9724 47849648 : HOST_WIDE_INT c1;
9725 47849648 : HOST_WIDE_INT pos;
9726 47849648 : unsigned HOST_WIDE_INT len;
9727 47849648 : rtx other;
9728 :
9729 : /* All the rules in this function are specific to scalar integers. */
9730 47849648 : scalar_int_mode mode;
9731 47849648 : if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9732 : return x;
9733 :
9734 : /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9735 : a clear of a one-bit field. We will have changed it to
9736 : (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9737 : for a SUBREG. */
9738 :
9739 1278910 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9740 1607 : && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9741 545 : && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9742 21956140 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9743 : {
9744 156 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9745 : 1, true, true, false);
9746 156 : if (assign != 0)
9747 153 : return gen_rtx_SET (assign, const0_rtx);
9748 : return x;
9749 : }
9750 :
9751 1278754 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9752 85781 : && subreg_lowpart_p (XEXP (src, 0))
9753 85748 : && partial_subreg_p (XEXP (src, 0))
9754 20034 : && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9755 125 : && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9756 57 : && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9757 21955496 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9758 : {
9759 14 : assign = make_extraction (VOIDmode, dest, 0,
9760 7 : XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9761 : 1, true, true, false);
9762 7 : if (assign != 0)
9763 7 : return gen_rtx_SET (assign, const0_rtx);
9764 : return x;
9765 : }
9766 :
9767 : /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9768 : one-bit field. */
9769 1587956 : if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9770 403477 : && XEXP (XEXP (src, 0), 0) == const1_rtx
9771 21957725 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9772 : {
9773 547 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9774 : 1, true, true, false);
9775 547 : if (assign != 0)
9776 518 : return gen_rtx_SET (assign, const1_rtx);
9777 : return x;
9778 : }
9779 :
9780 : /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9781 : SRC is an AND with all bits of that field set, then we can discard
9782 : the AND. */
9783 21954885 : if (GET_CODE (dest) == ZERO_EXTRACT
9784 2741 : && CONST_INT_P (XEXP (dest, 1))
9785 2741 : && GET_CODE (src) == AND
9786 816 : && CONST_INT_P (XEXP (src, 1)))
9787 : {
9788 816 : HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9789 816 : unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9790 816 : unsigned HOST_WIDE_INT ze_mask;
9791 :
9792 816 : if (width >= HOST_BITS_PER_WIDE_INT)
9793 : ze_mask = -1;
9794 : else
9795 816 : ze_mask = (HOST_WIDE_INT_1U << width) - 1;
9796 :
9797 : /* Complete overlap. We can remove the source AND. */
9798 816 : if ((and_mask & ze_mask) == ze_mask)
9799 768 : return gen_rtx_SET (dest, XEXP (src, 0));
9800 :
9801 : /* Partial overlap. We can reduce the source AND. */
9802 48 : if ((and_mask & ze_mask) != and_mask)
9803 : {
9804 6 : src = gen_rtx_AND (mode, XEXP (src, 0),
9805 : gen_int_mode (and_mask & ze_mask, mode));
9806 6 : return gen_rtx_SET (dest, src);
9807 : }
9808 : }
9809 :
9810 : /* The other case we handle is assignments into a constant-position
9811 : field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9812 : a mask that has all one bits except for a group of zero bits and
9813 : OTHER is known to have zeros where C1 has ones, this is such an
9814 : assignment. Compute the position and length from C1. Shift OTHER
9815 : to the appropriate position, force it to the required mode, and
9816 : make the extraction. Check for the AND in both operands. */
9817 :
9818 : /* One or more SUBREGs might obscure the constant-position field
9819 : assignment. The first one we are likely to encounter is an outer
9820 : narrowing SUBREG, which we can just strip for the purposes of
9821 : identifying the constant-field assignment. */
9822 21954111 : scalar_int_mode src_mode = mode;
9823 21954111 : if (GET_CODE (src) == SUBREG
9824 210257 : && subreg_lowpart_p (src)
9825 22148471 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9826 21954111 : src = SUBREG_REG (src);
9827 :
9828 21954111 : if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9829 : return x;
9830 :
9831 1772274 : rhs = expand_compound_operation (XEXP (src, 0));
9832 1772274 : lhs = expand_compound_operation (XEXP (src, 1));
9833 :
9834 1772274 : if (GET_CODE (rhs) == AND
9835 623251 : && CONST_INT_P (XEXP (rhs, 1))
9836 2114763 : && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9837 8640 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9838 : /* The second SUBREG that might get in the way is a paradoxical
9839 : SUBREG around the first operand of the AND. We want to
9840 : pretend the operand is as wide as the destination here. We
9841 : do this by adjusting the MEM to wider mode for the sole
9842 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9843 : note this trick only works for MEMs. */
9844 1763634 : else if (GET_CODE (rhs) == AND
9845 614611 : && paradoxical_subreg_p (XEXP (rhs, 0))
9846 66125 : && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9847 28624 : && CONST_INT_P (XEXP (rhs, 1))
9848 1792258 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9849 : dest, true))
9850 0 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9851 1763634 : else if (GET_CODE (lhs) == AND
9852 71005 : && CONST_INT_P (XEXP (lhs, 1))
9853 1826718 : && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9854 30 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9855 : /* The second SUBREG that might get in the way is a paradoxical
9856 : SUBREG around the first operand of the AND. We want to
9857 : pretend the operand is as wide as the destination here. We
9858 : do this by adjusting the MEM to wider mode for the sole
9859 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9860 : note this trick only works for MEMs. */
9861 1763604 : else if (GET_CODE (lhs) == AND
9862 70975 : && paradoxical_subreg_p (XEXP (lhs, 0))
9863 37805 : && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9864 23483 : && CONST_INT_P (XEXP (lhs, 1))
9865 1787087 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9866 : dest, true))
9867 0 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9868 : else
9869 : return x;
9870 :
9871 8670 : pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9872 8670 : if (pos < 0
9873 6439 : || pos + len > GET_MODE_PRECISION (mode)
9874 6439 : || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9875 15097 : || (c1 & nonzero_bits (other, mode)) != 0)
9876 : return x;
9877 :
9878 5394 : assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len,
9879 : true, true, false);
9880 5394 : if (assign == 0)
9881 : return x;
9882 :
9883 : /* The mode to use for the source is the mode of the assignment, or of
9884 : what is inside a possible STRICT_LOW_PART. */
9885 10764 : machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9886 5382 : ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9887 :
9888 : /* Shift OTHER right POS places and make it the source, restricting it
9889 : to the proper length and mode. */
9890 :
9891 5382 : src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9892 : src_mode, other, pos),
9893 : dest);
9894 10764 : src = force_to_mode (src, new_mode,
9895 : len >= HOST_BITS_PER_WIDE_INT
9896 : ? HOST_WIDE_INT_M1U
9897 5382 : : (HOST_WIDE_INT_1U << len) - 1, false);
9898 :
9899 : /* If SRC is masked by an AND that does not make a difference in
9900 : the value being stored, strip it. */
9901 5382 : if (GET_CODE (assign) == ZERO_EXTRACT
9902 5341 : && CONST_INT_P (XEXP (assign, 1))
9903 5341 : && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9904 5341 : && GET_CODE (src) == AND
9905 0 : && CONST_INT_P (XEXP (src, 1))
9906 0 : && UINTVAL (XEXP (src, 1))
9907 0 : == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9908 0 : src = XEXP (src, 0);
9909 :
9910 5382 : return gen_rtx_SET (assign, src);
9911 : }
9912 :
9913 : /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9914 : if so. */
9915 :
9916 : static rtx
9917 52282081 : apply_distributive_law (rtx x)
9918 : {
9919 52282081 : enum rtx_code code = GET_CODE (x);
9920 52282081 : enum rtx_code inner_code;
9921 52282081 : rtx lhs, rhs, other;
9922 52282081 : rtx tem;
9923 :
9924 : /* Distributivity is not true for floating point as it can change the
9925 : value. So we don't do it unless -funsafe-math-optimizations. */
9926 52282081 : if (FLOAT_MODE_P (GET_MODE (x))
9927 3641880 : && ! flag_unsafe_math_optimizations)
9928 : return x;
9929 :
9930 : /* The outer operation can only be one of the following: */
9931 49074684 : if (code != IOR && code != AND && code != XOR
9932 49074684 : && code != PLUS && code != MINUS)
9933 : return x;
9934 :
9935 49060808 : lhs = XEXP (x, 0);
9936 49060808 : rhs = XEXP (x, 1);
9937 :
9938 : /* If either operand is a primitive we can't do anything, so get out
9939 : fast. */
9940 49060808 : if (OBJECT_P (lhs) || OBJECT_P (rhs))
9941 : return x;
9942 :
9943 3520431 : lhs = expand_compound_operation (lhs);
9944 3520431 : rhs = expand_compound_operation (rhs);
9945 3520431 : inner_code = GET_CODE (lhs);
9946 3520431 : if (inner_code != GET_CODE (rhs))
9947 : return x;
9948 :
9949 : /* See if the inner and outer operations distribute. */
9950 1011577 : switch (inner_code)
9951 : {
9952 249306 : case LSHIFTRT:
9953 249306 : case ASHIFTRT:
9954 249306 : case AND:
9955 249306 : case IOR:
9956 : /* These all distribute except over PLUS. */
9957 249306 : if (code == PLUS || code == MINUS)
9958 : return x;
9959 : break;
9960 :
9961 101137 : case MULT:
9962 101137 : if (code != PLUS && code != MINUS)
9963 : return x;
9964 : break;
9965 :
9966 : case ASHIFT:
9967 : /* This is also a multiply, so it distributes over everything. */
9968 : break;
9969 :
9970 : /* This used to handle SUBREG, but this turned out to be counter-
9971 : productive, since (subreg (op ...)) usually is not handled by
9972 : insn patterns, and this "optimization" therefore transformed
9973 : recognizable patterns into unrecognizable ones. Therefore the
9974 : SUBREG case was removed from here.
9975 :
9976 : It is possible that distributing SUBREG over arithmetic operations
9977 : leads to an intermediate result than can then be optimized further,
9978 : e.g. by moving the outer SUBREG to the other side of a SET as done
9979 : in simplify_set. This seems to have been the original intent of
9980 : handling SUBREGs here.
9981 :
9982 : However, with current GCC this does not appear to actually happen,
9983 : at least on major platforms. If some case is found where removing
9984 : the SUBREG case here prevents follow-on optimizations, distributing
9985 : SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9986 :
9987 : default:
9988 : return x;
9989 : }
9990 :
9991 : /* Set LHS and RHS to the inner operands (A and B in the example
9992 : above) and set OTHER to the common operand (C in the example).
9993 : There is only one way to do this unless the inner operation is
9994 : commutative. */
9995 270853 : if (COMMUTATIVE_ARITH_P (lhs)
9996 270853 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9997 2521 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9998 268332 : else if (COMMUTATIVE_ARITH_P (lhs)
9999 268332 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
10000 21 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
10001 268311 : else if (COMMUTATIVE_ARITH_P (lhs)
10002 268311 : && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
10003 11408 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
10004 256903 : else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
10005 69699 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
10006 : else
10007 : return x;
10008 :
10009 : /* Form the new inner operation, seeing if it simplifies first. */
10010 83649 : tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10011 :
10012 : /* There is one exception to the general way of distributing:
10013 : (a | c) ^ (b | c) -> (a ^ b) & ~c */
10014 83649 : if (code == XOR && inner_code == IOR)
10015 : {
10016 1275 : inner_code = AND;
10017 1275 : other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10018 : }
10019 :
10020 : /* We may be able to continuing distributing the result, so call
10021 : ourselves recursively on the inner operation before forming the
10022 : outer operation, which we return. */
10023 83649 : return simplify_gen_binary (inner_code, GET_MODE (x),
10024 83649 : apply_distributive_law (tem), other);
10025 : }
10026 :
10027 : /* See if X is of the form (* (+ A B) C), and if so convert to
10028 : (+ (* A C) (* B C)) and try to simplify.
10029 :
10030 : Most of the time, this results in no change. However, if some of
10031 : the operands are the same or inverses of each other, simplifications
10032 : will result.
10033 :
10034 : For example, (and (ior A B) (not B)) can occur as the result of
10035 : expanding a bit field assignment. When we apply the distributive
10036 : law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10037 : which then simplifies to (and (A (not B))).
10038 :
10039 : Note that no checks happen on the validity of applying the inverse
10040 : distributive law. This is pointless since we can do it in the
10041 : few places where this routine is called.
10042 :
10043 : N is the index of the term that is decomposed (the arithmetic operation,
10044 : i.e. (+ A B) in the first example above). !N is the index of the term that
10045 : is distributed, i.e. of C in the first example above. */
10046 : static rtx
10047 1650099 : distribute_and_simplify_rtx (rtx x, int n)
10048 : {
10049 1650099 : machine_mode mode;
10050 1650099 : enum rtx_code outer_code, inner_code;
10051 1650099 : rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10052 :
10053 : /* Distributivity is not true for floating point as it can change the
10054 : value. So we don't do it unless -funsafe-math-optimizations. */
10055 1650099 : if (FLOAT_MODE_P (GET_MODE (x))
10056 164870 : && ! flag_unsafe_math_optimizations)
10057 : return NULL_RTX;
10058 :
10059 1488725 : decomposed = XEXP (x, n);
10060 1488725 : if (!ARITHMETIC_P (decomposed))
10061 : return NULL_RTX;
10062 :
10063 1488725 : mode = GET_MODE (x);
10064 1488725 : outer_code = GET_CODE (x);
10065 1488725 : distributed = XEXP (x, !n);
10066 :
10067 1488725 : inner_code = GET_CODE (decomposed);
10068 1488725 : inner_op0 = XEXP (decomposed, 0);
10069 1488725 : inner_op1 = XEXP (decomposed, 1);
10070 :
10071 : /* Special case (and (xor B C) (not A)), which is equivalent to
10072 : (xor (ior A B) (ior A C)) */
10073 1488725 : if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10074 : {
10075 1270 : distributed = XEXP (distributed, 0);
10076 1270 : outer_code = IOR;
10077 : }
10078 :
10079 1488725 : if (n == 0)
10080 : {
10081 : /* Distribute the second term. */
10082 1441141 : new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10083 1441141 : new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10084 : }
10085 : else
10086 : {
10087 : /* Distribute the first term. */
10088 47584 : new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10089 47584 : new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10090 : }
10091 :
10092 1488725 : tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10093 : new_op0, new_op1));
10094 1488725 : if (GET_CODE (tmp) != outer_code
10095 1488725 : && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10096 261218 : < set_src_cost (x, mode, optimize_this_for_speed_p)))
10097 17162 : return tmp;
10098 :
10099 : return NULL_RTX;
10100 : }
10101 :
10102 : /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10103 : in MODE. Return an equivalent form, if different from (and VAROP
10104 : (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10105 :
10106 : static rtx
10107 12391047 : simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10108 : unsigned HOST_WIDE_INT constop)
10109 : {
10110 12391047 : unsigned HOST_WIDE_INT nonzero;
10111 12391047 : unsigned HOST_WIDE_INT orig_constop;
10112 12391047 : rtx orig_varop;
10113 12391047 : int i;
10114 :
10115 12391047 : orig_varop = varop;
10116 12391047 : orig_constop = constop;
10117 12391047 : if (GET_CODE (varop) == CLOBBER)
10118 : return NULL_RTX;
10119 :
10120 : /* Simplify VAROP knowing that we will be only looking at some of the
10121 : bits in it.
10122 :
10123 : Note by passing in CONSTOP, we guarantee that the bits not set in
10124 : CONSTOP are not significant and will never be examined. We must
10125 : ensure that is the case by explicitly masking out those bits
10126 : before returning. */
10127 12391032 : varop = force_to_mode (varop, mode, constop, false);
10128 :
10129 : /* If VAROP is a CLOBBER, we will fail so return it. */
10130 12391032 : if (GET_CODE (varop) == CLOBBER)
10131 : return varop;
10132 :
10133 : /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10134 : to VAROP and return the new constant. */
10135 12390996 : if (CONST_INT_P (varop))
10136 297692 : return gen_int_mode (INTVAL (varop) & constop, mode);
10137 :
10138 : /* See what bits may be nonzero in VAROP. Unlike the general case of
10139 : a call to nonzero_bits, here we don't care about bits outside
10140 : MODE unless WORD_REGISTER_OPERATIONS is true. */
10141 :
10142 12093304 : scalar_int_mode tmode = mode;
10143 12093304 : if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10144 : tmode = word_mode;
10145 12093304 : nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10146 :
10147 : /* Turn off all bits in the constant that are known to already be zero.
10148 : Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10149 : which is tested below. */
10150 :
10151 12093304 : constop &= nonzero;
10152 :
10153 : /* If we don't have any bits left, return zero. */
10154 12093304 : if (constop == 0 && !side_effects_p (varop))
10155 0 : return const0_rtx;
10156 :
10157 : /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10158 : a power of two, we can replace this with an ASHIFT. */
10159 34413 : if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10160 12098978 : && (i = exact_log2 (constop)) >= 0)
10161 163 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10162 :
10163 : /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10164 : or XOR, then try to apply the distributive law. This may eliminate
10165 : operations if either branch can be simplified because of the AND.
10166 : It may also make some cases more complex, but those cases probably
10167 : won't match a pattern either with or without this. */
10168 :
10169 12093141 : if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10170 : {
10171 82147 : scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10172 82147 : return
10173 82147 : gen_lowpart
10174 82147 : (mode,
10175 : apply_distributive_law
10176 82147 : (simplify_gen_binary (GET_CODE (varop), varop_mode,
10177 : simplify_and_const_int (NULL_RTX, varop_mode,
10178 : XEXP (varop, 0),
10179 : constop),
10180 : simplify_and_const_int (NULL_RTX, varop_mode,
10181 : XEXP (varop, 1),
10182 : constop))));
10183 : }
10184 :
10185 : /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10186 : the AND and see if one of the operands simplifies to zero. If so, we
10187 : may eliminate it. */
10188 :
10189 12010994 : if (GET_CODE (varop) == PLUS
10190 12010994 : && pow2p_hwi (constop + 1))
10191 : {
10192 436458 : rtx o0, o1;
10193 :
10194 436458 : o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10195 436458 : o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10196 436458 : if (o0 == const0_rtx)
10197 : return o1;
10198 436458 : if (o1 == const0_rtx)
10199 : return o0;
10200 : }
10201 :
10202 : /* Make a SUBREG if necessary. If we can't make it, fail. */
10203 12010918 : varop = gen_lowpart (mode, varop);
10204 12010918 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10205 : return NULL_RTX;
10206 :
10207 : /* If we are only masking insignificant bits, return VAROP. */
10208 12010918 : if (constop == nonzero)
10209 : return varop;
10210 :
10211 11549458 : if (varop == orig_varop && constop == orig_constop)
10212 : return NULL_RTX;
10213 :
10214 : /* Otherwise, return an AND. */
10215 6259386 : return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10216 : }
10217 :
10218 :
10219 : /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10220 : in MODE.
10221 :
10222 : Return an equivalent form, if different from X. Otherwise, return X. If
10223 : X is zero, we are to always construct the equivalent form. */
10224 :
10225 : static rtx
10226 12391047 : simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10227 : unsigned HOST_WIDE_INT constop)
10228 : {
10229 12391047 : rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10230 12391047 : if (tem)
10231 : return tem;
10232 :
10233 5290087 : if (!x)
10234 1316533 : x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10235 1316533 : gen_int_mode (constop, mode));
10236 5290087 : if (GET_MODE (x) != mode)
10237 2 : x = gen_lowpart (mode, x);
10238 : return x;
10239 : }
10240 :
10241 : /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10242 : We don't care about bits outside of those defined in MODE.
10243 : We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10244 :
10245 : For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10246 : a shift, AND, or zero_extract, we can do better. */
10247 :
10248 : static rtx
10249 456944084 : reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10250 : scalar_int_mode mode,
10251 : unsigned HOST_WIDE_INT *nonzero)
10252 : {
10253 456944084 : rtx tem;
10254 456944084 : reg_stat_type *rsp;
10255 :
10256 : /* If X is a register whose nonzero bits value is current, use it.
10257 : Otherwise, if X is a register whose value we can find, use that
10258 : value. Otherwise, use the previously-computed global nonzero bits
10259 : for this register. */
10260 :
10261 456944084 : rsp = ®_stat[REGNO (x)];
10262 456944084 : if (rsp->last_set_value != 0
10263 421665627 : && (rsp->last_set_mode == mode
10264 1278 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10265 0 : && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10266 0 : && GET_MODE_CLASS (mode) == MODE_INT))
10267 878608433 : && ((rsp->last_set_label >= label_tick_ebb_start
10268 320466417 : && rsp->last_set_label < label_tick)
10269 398896631 : || (rsp->last_set_label == label_tick
10270 297698699 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10271 129863784 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10272 129810845 : && REGNO (x) < reg_n_sets_max
10273 129810715 : && REG_N_SETS (REGNO (x)) == 1
10274 149729236 : && !REGNO_REG_SET_P
10275 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10276 : REGNO (x)))))
10277 : {
10278 : /* Note that, even if the precision of last_set_mode is lower than that
10279 : of mode, record_value_for_reg invoked nonzero_bits on the register
10280 : with nonzero_bits_mode (because last_set_mode is necessarily integral
10281 : and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10282 : are all valid, hence in mode too since nonzero_bits_mode is defined
10283 : to the largest HWI_COMPUTABLE_MODE_P mode. */
10284 366566013 : *nonzero &= rsp->last_set_nonzero_bits;
10285 366566013 : return NULL;
10286 : }
10287 :
10288 90378071 : tem = get_last_value (x);
10289 90378071 : if (tem)
10290 : {
10291 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
10292 : tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10293 :
10294 : return tem;
10295 : }
10296 :
10297 90378065 : if (nonzero_sign_valid && rsp->nonzero_bits)
10298 : {
10299 56798021 : unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10300 :
10301 56798021 : if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10302 : /* We don't know anything about the upper bits. */
10303 0 : mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10304 :
10305 56798021 : *nonzero &= mask;
10306 : }
10307 :
10308 : return NULL;
10309 : }
10310 :
10311 : /* Given a reg X of mode XMODE, return the number of bits at the high-order
10312 : end of X that are known to be equal to the sign bit. X will be used
10313 : in mode MODE; the returned value will always be between 1 and the
10314 : number of bits in MODE. */
10315 :
10316 : static rtx
10317 133016517 : reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10318 : scalar_int_mode mode,
10319 : unsigned int *result)
10320 : {
10321 133016517 : rtx tem;
10322 133016517 : reg_stat_type *rsp;
10323 :
10324 133016517 : rsp = ®_stat[REGNO (x)];
10325 133016517 : if (rsp->last_set_value != 0
10326 120752349 : && rsp->last_set_mode == mode
10327 253768697 : && ((rsp->last_set_label >= label_tick_ebb_start
10328 91653398 : && rsp->last_set_label < label_tick)
10329 114679833 : || (rsp->last_set_label == label_tick
10330 85581051 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10331 36985399 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10332 36975523 : && REGNO (x) < reg_n_sets_max
10333 36975437 : && REG_N_SETS (REGNO (x)) == 1
10334 42695064 : && !REGNO_REG_SET_P
10335 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10336 : REGNO (x)))))
10337 : {
10338 105088939 : *result = rsp->last_set_sign_bit_copies;
10339 105088939 : return NULL;
10340 : }
10341 :
10342 27927578 : tem = get_last_value (x);
10343 27927578 : if (tem != 0)
10344 : return tem;
10345 :
10346 18497582 : if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10347 42323784 : && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10348 14396211 : *result = rsp->sign_bit_copies;
10349 :
10350 : return NULL;
10351 : }
10352 :
10353 : /* Return the number of "extended" bits there are in X, when interpreted
10354 : as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10355 : unsigned quantities, this is the number of high-order zero bits.
10356 : For signed quantities, this is the number of copies of the sign bit
10357 : minus 1. In both case, this function returns the number of "spare"
10358 : bits. For example, if two quantities for which this function returns
10359 : at least 1 are added, the addition is known not to overflow.
10360 :
10361 : This function will always return 0 unless called during combine, which
10362 : implies that it must be called from a define_split. */
10363 :
10364 : unsigned int
10365 0 : extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10366 : {
10367 0 : if (nonzero_sign_valid == 0)
10368 : return 0;
10369 :
10370 0 : scalar_int_mode int_mode;
10371 0 : return (unsignedp
10372 0 : ? (is_a <scalar_int_mode> (mode, &int_mode)
10373 0 : && HWI_COMPUTABLE_MODE_P (int_mode)
10374 0 : ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10375 0 : - floor_log2 (nonzero_bits (x, int_mode)))
10376 : : 0)
10377 0 : : num_sign_bit_copies (x, mode) - 1);
10378 : }
10379 :
10380 : /* This function is called from `simplify_shift_const' to merge two
10381 : outer operations. Specifically, we have already found that we need
10382 : to perform operation *POP0 with constant *PCONST0 at the outermost
10383 : position. We would now like to also perform OP1 with constant CONST1
10384 : (with *POP0 being done last).
10385 :
10386 : Return true if we can do the operation and update *POP0 and *PCONST0 with
10387 : the resulting operation. *PCOMP_P is set to true if we would need to
10388 : complement the innermost operand, otherwise it is unchanged.
10389 :
10390 : MODE is the mode in which the operation will be done. No bits outside
10391 : the width of this mode matter. It is assumed that the width of this mode
10392 : is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10393 :
10394 : If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10395 : IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10396 : result is simply *PCONST0.
10397 :
10398 : If the resulting operation cannot be expressed as one operation, we
10399 : return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10400 :
10401 : static bool
10402 3755860 : merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10403 : enum rtx_code op1, HOST_WIDE_INT const1,
10404 : machine_mode mode, bool *pcomp_p)
10405 : {
10406 3755860 : enum rtx_code op0 = *pop0;
10407 3755860 : HOST_WIDE_INT const0 = *pconst0;
10408 :
10409 3755860 : const0 &= GET_MODE_MASK (mode);
10410 3755860 : const1 &= GET_MODE_MASK (mode);
10411 :
10412 : /* If OP0 is an AND, clear unimportant bits in CONST1. */
10413 3755860 : if (op0 == AND)
10414 9727 : const1 &= const0;
10415 :
10416 : /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10417 : if OP0 is SET. */
10418 :
10419 3755860 : if (op1 == UNKNOWN || op0 == SET)
10420 : return true;
10421 :
10422 3755860 : else if (op0 == UNKNOWN)
10423 : op0 = op1, const0 = const1;
10424 :
10425 60898 : else if (op0 == op1)
10426 : {
10427 9447 : switch (op0)
10428 : {
10429 9442 : case AND:
10430 9442 : const0 &= const1;
10431 9442 : break;
10432 5 : case IOR:
10433 5 : const0 |= const1;
10434 5 : break;
10435 0 : case XOR:
10436 0 : const0 ^= const1;
10437 0 : break;
10438 0 : case PLUS:
10439 0 : const0 += const1;
10440 0 : break;
10441 : case NEG:
10442 3728167 : op0 = UNKNOWN;
10443 : break;
10444 : default:
10445 : break;
10446 : }
10447 : }
10448 :
10449 : /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10450 51451 : else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10451 : return false;
10452 :
10453 : /* If the two constants aren't the same, we can't do anything. The
10454 : remaining six cases can all be done. */
10455 25093 : else if (const0 != const1)
10456 : return false;
10457 :
10458 : else
10459 23758 : switch (op0)
10460 : {
10461 8 : case IOR:
10462 8 : if (op1 == AND)
10463 : /* (a & b) | b == b */
10464 0 : op0 = SET;
10465 : else /* op1 == XOR */
10466 : /* (a ^ b) | b == a | b */
10467 : {;}
10468 : break;
10469 :
10470 23469 : case XOR:
10471 23469 : if (op1 == AND)
10472 : /* (a & b) ^ b == (~a) & b */
10473 23469 : op0 = AND, *pcomp_p = true;
10474 : else /* op1 == IOR */
10475 : /* (a | b) ^ b == a & ~b */
10476 0 : op0 = AND, const0 = ~const0;
10477 : break;
10478 :
10479 281 : case AND:
10480 281 : if (op1 == IOR)
10481 : /* (a | b) & b == b */
10482 : op0 = SET;
10483 : else /* op1 == XOR */
10484 : /* (a ^ b) & b) == (~a) & b */
10485 281 : *pcomp_p = true;
10486 : break;
10487 : default:
10488 : break;
10489 : }
10490 :
10491 : /* Check for NO-OP cases. */
10492 3728167 : const0 &= GET_MODE_MASK (mode);
10493 3728167 : if (const0 == 0
10494 19310 : && (op0 == IOR || op0 == XOR || op0 == PLUS))
10495 : op0 = UNKNOWN;
10496 3726738 : else if (const0 == 0 && op0 == AND)
10497 : op0 = SET;
10498 3726738 : else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10499 24425 : && op0 == AND)
10500 3728167 : op0 = UNKNOWN;
10501 :
10502 3728167 : *pop0 = op0;
10503 :
10504 : /* ??? Slightly redundant with the above mask, but not entirely.
10505 : Moving this above means we'd have to sign-extend the mode mask
10506 : for the final test. */
10507 3728167 : if (op0 != UNKNOWN && op0 != NEG)
10508 3692459 : *pconst0 = trunc_int_for_mode (const0, mode);
10509 :
10510 : return true;
10511 : }
10512 :
10513 : /* A helper to simplify_shift_const_1 to determine the mode we can perform
10514 : the shift in. The original shift operation CODE is performed on OP in
10515 : ORIG_MODE. Return the wider mode MODE if we can perform the operation
10516 : in that mode. Return ORIG_MODE otherwise. We can also assume that the
10517 : result of the shift is subject to operation OUTER_CODE with operand
10518 : OUTER_CONST. */
10519 :
10520 : static scalar_int_mode
10521 410734 : try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10522 : scalar_int_mode orig_mode, scalar_int_mode mode,
10523 : enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10524 : {
10525 410734 : gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10526 :
10527 : /* In general we can't perform in wider mode for right shift and rotate. */
10528 410734 : switch (code)
10529 : {
10530 34109 : case ASHIFTRT:
10531 : /* We can still widen if the bits brought in from the left are identical
10532 : to the sign bit of ORIG_MODE. */
10533 34109 : if (num_sign_bit_copies (op, mode)
10534 34109 : > (unsigned) (GET_MODE_PRECISION (mode)
10535 34109 : - GET_MODE_PRECISION (orig_mode)))
10536 348 : return mode;
10537 33761 : return orig_mode;
10538 :
10539 74737 : case LSHIFTRT:
10540 : /* Similarly here but with zero bits. */
10541 74737 : if (HWI_COMPUTABLE_MODE_P (mode)
10542 74737 : && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10543 6495 : return mode;
10544 :
10545 : /* We can also widen if the bits brought in will be masked off. This
10546 : operation is performed in ORIG_MODE. */
10547 68242 : if (outer_code == AND)
10548 : {
10549 26838 : int care_bits = low_bitmask_len (orig_mode, outer_const);
10550 :
10551 26838 : if (care_bits >= 0
10552 26838 : && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10553 26820 : return mode;
10554 : }
10555 : /* fall through */
10556 :
10557 41908 : case ROTATE:
10558 41908 : return orig_mode;
10559 :
10560 0 : case ROTATERT:
10561 0 : gcc_unreachable ();
10562 :
10563 301402 : default:
10564 301402 : return mode;
10565 : }
10566 : }
10567 :
10568 : /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10569 : of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10570 : if we cannot simplify it. Otherwise, return a simplified value.
10571 :
10572 : The shift is normally computed in the widest mode we find in VAROP, as
10573 : long as it isn't a different number of words than RESULT_MODE. Exceptions
10574 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
10575 :
10576 : static rtx
10577 24131849 : simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10578 : rtx varop, int orig_count)
10579 : {
10580 24131849 : enum rtx_code orig_code = code;
10581 24131849 : rtx orig_varop = varop;
10582 24131849 : int count, log2;
10583 24131849 : machine_mode mode = result_mode;
10584 24131849 : machine_mode shift_mode;
10585 24131849 : scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10586 : /* We form (outer_op (code varop count) (outer_const)). */
10587 24131849 : enum rtx_code outer_op = UNKNOWN;
10588 24131849 : HOST_WIDE_INT outer_const = 0;
10589 24131849 : bool complement_p = false;
10590 24131849 : rtx new_rtx, x;
10591 :
10592 : /* Make sure and truncate the "natural" shift on the way in. We don't
10593 : want to do this inside the loop as it makes it more difficult to
10594 : combine shifts. */
10595 24131849 : if (SHIFT_COUNT_TRUNCATED)
10596 : orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10597 :
10598 : /* If we were given an invalid count, don't do anything except exactly
10599 : what was requested. */
10600 :
10601 48263638 : if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10602 : return NULL_RTX;
10603 :
10604 : count = orig_count;
10605 :
10606 : /* Unless one of the branches of the `if' in this loop does a `continue',
10607 : we will `break' the loop after the `if'. */
10608 :
10609 28231725 : while (count != 0)
10610 : {
10611 : /* If we have an operand of (clobber (const_int 0)), fail. */
10612 24337223 : if (GET_CODE (varop) == CLOBBER)
10613 24131849 : return NULL_RTX;
10614 :
10615 : /* Convert ROTATERT to ROTATE. */
10616 24337223 : if (code == ROTATERT)
10617 : {
10618 11644 : unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10619 11644 : code = ROTATE;
10620 11644 : count = bitsize - count;
10621 : }
10622 :
10623 24337223 : shift_mode = result_mode;
10624 24337223 : if (shift_mode != mode)
10625 : {
10626 : /* We only change the modes of scalar shifts. */
10627 211322 : int_mode = as_a <scalar_int_mode> (mode);
10628 211322 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10629 211322 : shift_mode = try_widen_shift_mode (code, varop, count,
10630 : int_result_mode, int_mode,
10631 : outer_op, outer_const);
10632 : }
10633 :
10634 24337223 : scalar_int_mode shift_unit_mode;
10635 48674446 : if (!is_a <scalar_int_mode> (GET_MODE_INNER (shift_mode),
10636 : &shift_unit_mode))
10637 : return NULL_RTX;
10638 :
10639 : /* Handle cases where the count is greater than the size of the mode
10640 : minus 1. For ASHIFT, use the size minus one as the count (this can
10641 : occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10642 : take the count modulo the size. For other shifts, the result is
10643 : zero.
10644 :
10645 : Since these shifts are being produced by the compiler by combining
10646 : multiple operations, each of which are defined, we know what the
10647 : result is supposed to be. */
10648 :
10649 24337223 : if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10650 : {
10651 12918 : if (code == ASHIFTRT)
10652 12912 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10653 6 : else if (code == ROTATE || code == ROTATERT)
10654 6 : count %= GET_MODE_PRECISION (shift_unit_mode);
10655 : else
10656 : {
10657 : /* We can't simply return zero because there may be an
10658 : outer op. */
10659 0 : varop = const0_rtx;
10660 0 : count = 0;
10661 0 : break;
10662 : }
10663 : }
10664 :
10665 : /* If we discovered we had to complement VAROP, leave. Making a NOT
10666 : here would cause an infinite loop. */
10667 24337223 : if (complement_p)
10668 : break;
10669 :
10670 24324367 : if (shift_mode == shift_unit_mode)
10671 : {
10672 : /* An arithmetic right shift of a quantity known to be -1 or 0
10673 : is a no-op. */
10674 23654935 : if (code == ASHIFTRT
10675 23654935 : && (num_sign_bit_copies (varop, shift_unit_mode)
10676 4452622 : == GET_MODE_PRECISION (shift_unit_mode)))
10677 : {
10678 : count = 0;
10679 : break;
10680 : }
10681 :
10682 : /* If we are doing an arithmetic right shift and discarding all but
10683 : the sign bit copies, this is equivalent to doing a shift by the
10684 : bitsize minus one. Convert it into that shift because it will
10685 : often allow other simplifications. */
10686 :
10687 23654864 : if (code == ASHIFTRT
10688 23654864 : && (count + num_sign_bit_copies (varop, shift_unit_mode)
10689 4452551 : >= GET_MODE_PRECISION (shift_unit_mode)))
10690 337422 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10691 :
10692 : /* We simplify the tests below and elsewhere by converting
10693 : ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10694 : `make_compound_operation' will convert it to an ASHIFTRT for
10695 : those machines (such as VAX) that don't have an LSHIFTRT. */
10696 23654864 : if (code == ASHIFTRT
10697 4452551 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10698 28082057 : && val_signbit_known_clear_p (shift_unit_mode,
10699 : nonzero_bits (varop,
10700 : shift_unit_mode)))
10701 : code = LSHIFTRT;
10702 :
10703 23625430 : if (((code == LSHIFTRT
10704 5888160 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10705 5866312 : && !(nonzero_bits (varop, shift_unit_mode) >> count))
10706 23652904 : || (code == ASHIFT
10707 13314716 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10708 12842764 : && !((nonzero_bits (varop, shift_unit_mode) << count)
10709 12842764 : & GET_MODE_MASK (shift_unit_mode))))
10710 23629545 : && !side_effects_p (varop))
10711 4115 : varop = const0_rtx;
10712 : }
10713 :
10714 24324296 : switch (GET_CODE (varop))
10715 : {
10716 509084 : case SIGN_EXTEND:
10717 509084 : case ZERO_EXTEND:
10718 509084 : case SIGN_EXTRACT:
10719 509084 : case ZERO_EXTRACT:
10720 509084 : new_rtx = expand_compound_operation (varop);
10721 509084 : if (new_rtx != varop)
10722 : {
10723 68461 : varop = new_rtx;
10724 4100148 : continue;
10725 : }
10726 : break;
10727 :
10728 332997 : case MEM:
10729 : /* The following rules apply only to scalars. */
10730 332997 : if (shift_mode != shift_unit_mode)
10731 : break;
10732 317664 : int_mode = as_a <scalar_int_mode> (mode);
10733 :
10734 : /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10735 : minus the width of a smaller mode, we can do this with a
10736 : SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10737 321396 : if ((code == ASHIFTRT || code == LSHIFTRT)
10738 120838 : && ! mode_dependent_address_p (XEXP (varop, 0),
10739 120838 : MEM_ADDR_SPACE (varop))
10740 120838 : && ! MEM_VOLATILE_P (varop)
10741 436986 : && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10742 313932 : .exists (&tmode)))
10743 : {
10744 3732 : new_rtx = adjust_address_nv (varop, tmode,
10745 : BYTES_BIG_ENDIAN ? 0
10746 : : count / BITS_PER_UNIT);
10747 :
10748 3732 : varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10749 : : ZERO_EXTEND, int_mode, new_rtx);
10750 3732 : count = 0;
10751 3732 : continue;
10752 : }
10753 : break;
10754 :
10755 5064239 : case SUBREG:
10756 : /* The following rules apply only to scalars. */
10757 5064239 : if (shift_mode != shift_unit_mode)
10758 : break;
10759 4595459 : int_mode = as_a <scalar_int_mode> (mode);
10760 4595459 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10761 :
10762 : /* If VAROP is a SUBREG, strip it as long as the inner operand has
10763 : the same number of words as what we've seen so far. Then store
10764 : the widest mode in MODE. */
10765 4595459 : if (subreg_lowpart_p (varop)
10766 28685289 : && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10767 9107424 : && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10768 231666 : && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10769 213013 : == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10770 4795445 : && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10771 : {
10772 199986 : varop = SUBREG_REG (varop);
10773 599958 : if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10774 199986 : mode = inner_mode;
10775 199986 : continue;
10776 : }
10777 : break;
10778 :
10779 408300 : case MULT:
10780 : /* Some machines use MULT instead of ASHIFT because MULT
10781 : is cheaper. But it is still better on those machines to
10782 : merge two shifts into one. */
10783 408300 : if (CONST_INT_P (XEXP (varop, 1))
10784 408300 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10785 : {
10786 0 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10787 0 : varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10788 : XEXP (varop, 0), log2_rtx);
10789 0 : continue;
10790 0 : }
10791 : break;
10792 :
10793 8819 : case UDIV:
10794 : /* Similar, for when divides are cheaper. */
10795 8819 : if (CONST_INT_P (XEXP (varop, 1))
10796 8819 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10797 : {
10798 9 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10799 9 : varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10800 : XEXP (varop, 0), log2_rtx);
10801 9 : continue;
10802 9 : }
10803 : break;
10804 :
10805 382259 : case ASHIFTRT:
10806 : /* If we are extracting just the sign bit of an arithmetic
10807 : right shift, that shift is not needed. However, the sign
10808 : bit of a wider mode may be different from what would be
10809 : interpreted as the sign bit in a narrower mode, so, if
10810 : the result is narrower, don't discard the shift. */
10811 384159 : if (code == LSHIFTRT
10812 15007 : && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10813 382259 : && (GET_MODE_UNIT_BITSIZE (result_mode)
10814 3826 : >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10815 : {
10816 1900 : varop = XEXP (varop, 0);
10817 1900 : continue;
10818 : }
10819 :
10820 : /* fall through */
10821 :
10822 5979142 : case LSHIFTRT:
10823 5979142 : case ASHIFT:
10824 5979142 : case ROTATE:
10825 : /* The following rules apply only to scalars. */
10826 5979142 : if (shift_mode != shift_unit_mode)
10827 : break;
10828 5971310 : int_mode = as_a <scalar_int_mode> (mode);
10829 5971310 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10830 5971310 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10831 :
10832 : /* Here we have two nested shifts. The result is usually the
10833 : AND of a new shift with a mask. We compute the result below. */
10834 5971310 : if (CONST_INT_P (XEXP (varop, 1))
10835 5951338 : && INTVAL (XEXP (varop, 1)) >= 0
10836 5951335 : && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10837 5951335 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
10838 11889288 : && HWI_COMPUTABLE_MODE_P (int_mode))
10839 : {
10840 5917978 : enum rtx_code first_code = GET_CODE (varop);
10841 5917978 : unsigned int first_count = INTVAL (XEXP (varop, 1));
10842 5917978 : unsigned HOST_WIDE_INT mask;
10843 5917978 : rtx mask_rtx;
10844 :
10845 : /* We have one common special case. We can't do any merging if
10846 : the inner code is an ASHIFTRT of a smaller mode. However, if
10847 : we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10848 : with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10849 : we can convert it to
10850 : (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10851 : This simplifies certain SIGN_EXTEND operations. */
10852 5917978 : if (code == ASHIFT && first_code == ASHIFTRT
10853 5917978 : && count == (GET_MODE_PRECISION (int_result_mode)
10854 343267 : - GET_MODE_PRECISION (int_varop_mode)))
10855 : {
10856 : /* C3 has the low-order C1 bits zero. */
10857 :
10858 0 : mask = GET_MODE_MASK (int_mode)
10859 0 : & ~((HOST_WIDE_INT_1U << first_count) - 1);
10860 :
10861 0 : varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10862 : XEXP (varop, 0), mask);
10863 0 : varop = simplify_shift_const (NULL_RTX, ASHIFT,
10864 : int_result_mode, varop, count);
10865 0 : count = first_count;
10866 0 : code = ASHIFTRT;
10867 0 : continue;
10868 : }
10869 :
10870 : /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10871 : than C1 high-order bits equal to the sign bit, we can convert
10872 : this to either an ASHIFT or an ASHIFTRT depending on the
10873 : two counts.
10874 :
10875 : We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10876 :
10877 5919478 : if (code == ASHIFTRT && first_code == ASHIFT
10878 2911176 : && int_varop_mode == shift_unit_mode
10879 8822368 : && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10880 : > first_count))
10881 : {
10882 1500 : varop = XEXP (varop, 0);
10883 1500 : count -= first_count;
10884 1500 : if (count < 0)
10885 : {
10886 4 : count = -count;
10887 4 : code = ASHIFT;
10888 : }
10889 :
10890 1500 : continue;
10891 : }
10892 :
10893 : /* There are some cases we can't do. If CODE is ASHIFTRT,
10894 : we can only do this if FIRST_CODE is also ASHIFTRT.
10895 :
10896 : We can't do the case when CODE is ROTATE and FIRST_CODE is
10897 : ASHIFTRT.
10898 :
10899 : If the mode of this shift is not the mode of the outer shift,
10900 : we can't do this if either shift is a right shift or ROTATE.
10901 :
10902 : Finally, we can't do any of these if the mode is too wide
10903 : unless the codes are the same.
10904 :
10905 : Handle the case where the shift codes are the same
10906 : first. */
10907 :
10908 5916478 : if (code == first_code)
10909 : {
10910 31157 : if (int_varop_mode != int_result_mode
10911 31157 : && (code == ASHIFTRT || code == LSHIFTRT
10912 691 : || code == ROTATE))
10913 : break;
10914 :
10915 30490 : count += first_count;
10916 30490 : varop = XEXP (varop, 0);
10917 30490 : continue;
10918 : }
10919 :
10920 5885321 : if (code == ASHIFTRT
10921 2975597 : || (code == ROTATE && first_code == ASHIFTRT)
10922 2975567 : || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10923 8860888 : || (int_varop_mode != int_result_mode
10924 80948 : && (first_code == ASHIFTRT || first_code == LSHIFTRT
10925 80948 : || first_code == ROTATE
10926 26389 : || code == ROTATE)))
10927 : break;
10928 :
10929 : /* To compute the mask to apply after the shift, shift the
10930 : nonzero bits of the inner shift the same way the
10931 : outer shift will. */
10932 :
10933 2921008 : mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10934 : int_result_mode);
10935 2921008 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10936 2921008 : mask_rtx
10937 2921008 : = simplify_const_binary_operation (code, int_result_mode,
10938 : mask_rtx, count_rtx);
10939 :
10940 : /* Give up if we can't compute an outer operation to use. */
10941 2921008 : if (mask_rtx == 0
10942 2921008 : || !CONST_INT_P (mask_rtx)
10943 5842016 : || ! merge_outer_ops (&outer_op, &outer_const, AND,
10944 : INTVAL (mask_rtx),
10945 : int_result_mode, &complement_p))
10946 : break;
10947 :
10948 : /* If the shifts are in the same direction, we add the
10949 : counts. Otherwise, we subtract them. */
10950 2894756 : if ((code == ASHIFTRT || code == LSHIFTRT)
10951 2894756 : == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10952 11459 : count += first_count;
10953 : else
10954 2883297 : count -= first_count;
10955 :
10956 : /* If COUNT is positive, the new shift is usually CODE,
10957 : except for the two exceptions below, in which case it is
10958 : FIRST_CODE. If the count is negative, FIRST_CODE should
10959 : always be used */
10960 2894756 : if (count > 0
10961 668495 : && ((first_code == ROTATE && code == ASHIFT)
10962 667989 : || (first_code == ASHIFTRT && code == LSHIFTRT)))
10963 : code = first_code;
10964 2883303 : else if (count < 0)
10965 322484 : code = first_code, count = -count;
10966 :
10967 2894756 : varop = XEXP (varop, 0);
10968 2894756 : continue;
10969 2894756 : }
10970 :
10971 : /* If we have (A << B << C) for any shift, we can convert this to
10972 : (A << C << B). This wins if A is a constant. Only try this if
10973 : B is not a constant. */
10974 :
10975 53332 : else if (GET_CODE (varop) == code
10976 5191 : && CONST_INT_P (XEXP (varop, 0))
10977 1023 : && !CONST_INT_P (XEXP (varop, 1)))
10978 : {
10979 : /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10980 : sure the result will be masked. See PR70222. */
10981 1023 : if (code == LSHIFTRT
10982 7 : && int_mode != int_result_mode
10983 1030 : && !merge_outer_ops (&outer_op, &outer_const, AND,
10984 7 : GET_MODE_MASK (int_result_mode)
10985 7 : >> orig_count, int_result_mode,
10986 : &complement_p))
10987 : break;
10988 : /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10989 : up outer sign extension (often left and right shift) is
10990 : hardly more efficient than the original. See PR70429.
10991 : Similarly punt for rotates with different modes.
10992 : See PR97386. */
10993 1023 : if ((code == ASHIFTRT || code == ROTATE)
10994 1023 : && int_mode != int_result_mode)
10995 : break;
10996 :
10997 1009 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10998 1009 : rtx new_rtx = simplify_const_binary_operation (code, int_mode,
10999 : XEXP (varop, 0),
11000 : count_rtx);
11001 1009 : varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
11002 1009 : count = 0;
11003 1009 : continue;
11004 1009 : }
11005 : break;
11006 :
11007 59783 : case NOT:
11008 : /* The following rules apply only to scalars. */
11009 59783 : if (shift_mode != shift_unit_mode)
11010 : break;
11011 :
11012 : /* Make this fit the case below. */
11013 59721 : varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11014 59721 : continue;
11015 :
11016 804464 : case IOR:
11017 804464 : case AND:
11018 804464 : case XOR:
11019 : /* The following rules apply only to scalars. */
11020 804464 : if (shift_mode != shift_unit_mode)
11021 : break;
11022 802535 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11023 802535 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11024 :
11025 : /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11026 : with C the size of VAROP - 1 and the shift is logical if
11027 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11028 : we have an (le X 0) operation. If we have an arithmetic shift
11029 : and STORE_FLAG_VALUE is 1 or we have a logical shift with
11030 : STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11031 :
11032 266026 : if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11033 1581 : && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11034 : && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11035 119 : && (code == LSHIFTRT || code == ASHIFTRT)
11036 119 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11037 802654 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11038 : {
11039 56 : count = 0;
11040 56 : varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11041 : const0_rtx);
11042 :
11043 56 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11044 56 : varop = gen_rtx_NEG (int_varop_mode, varop);
11045 :
11046 56 : continue;
11047 : }
11048 :
11049 : /* If we have (shift (logical)), move the logical to the outside
11050 : to allow it to possibly combine with another logical and the
11051 : shift to combine with another shift. This also canonicalizes to
11052 : what a ZERO_EXTRACT looks like. Also, some machines have
11053 : (and (shift)) insns. */
11054 :
11055 1242873 : if (CONST_INT_P (XEXP (varop, 1))
11056 : /* We can't do this if we have (ashiftrt (xor)) and the
11057 : constant has its sign bit set in shift_unit_mode with
11058 : shift_unit_mode wider than result_mode. */
11059 441676 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11060 8237 : && int_result_mode != shift_unit_mode
11061 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11062 : shift_unit_mode) < 0)
11063 441676 : && (new_rtx = simplify_const_binary_operation
11064 441676 : (code, int_result_mode,
11065 441676 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11066 441676 : gen_int_shift_amount (int_result_mode, count))) != 0
11067 441676 : && CONST_INT_P (new_rtx)
11068 1244155 : && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11069 : INTVAL (new_rtx), int_result_mode,
11070 : &complement_p))
11071 : {
11072 440394 : varop = XEXP (varop, 0);
11073 440394 : continue;
11074 : }
11075 :
11076 : /* If we can't do that, try to simplify the shift in each arm of the
11077 : logical expression, make a new logical expression, and apply
11078 : the inverse distributive law. This also can't be done for
11079 : (ashiftrt (xor)) where we've widened the shift and the constant
11080 : changes the sign bit. */
11081 362085 : if (CONST_INT_P (XEXP (varop, 1))
11082 362085 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11083 48 : && int_result_mode != shift_unit_mode
11084 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11085 : shift_unit_mode) < 0))
11086 : {
11087 1282 : rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11088 : XEXP (varop, 0), count);
11089 1282 : rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11090 : XEXP (varop, 1), count);
11091 :
11092 1282 : varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11093 : lhs, rhs);
11094 1282 : varop = apply_distributive_law (varop);
11095 :
11096 1282 : count = 0;
11097 1282 : continue;
11098 1282 : }
11099 : break;
11100 :
11101 33920 : case EQ:
11102 : /* The following rules apply only to scalars. */
11103 33920 : if (shift_mode != shift_unit_mode)
11104 : break;
11105 33920 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11106 :
11107 : /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11108 : says that the sign bit can be tested, FOO has mode MODE, C is
11109 : GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11110 : that may be nonzero. */
11111 33920 : if (code == LSHIFTRT
11112 0 : && XEXP (varop, 1) == const0_rtx
11113 0 : && GET_MODE (XEXP (varop, 0)) == int_result_mode
11114 0 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11115 33920 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11116 : && STORE_FLAG_VALUE == -1
11117 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11118 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11119 : int_result_mode, &complement_p))
11120 : {
11121 : varop = XEXP (varop, 0);
11122 : count = 0;
11123 : continue;
11124 : }
11125 : break;
11126 :
11127 27258 : case NEG:
11128 : /* The following rules apply only to scalars. */
11129 27258 : if (shift_mode != shift_unit_mode)
11130 : break;
11131 27128 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11132 :
11133 : /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11134 : than the number of bits in the mode is equivalent to A. */
11135 27133 : if (code == LSHIFTRT
11136 5840 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11137 29781 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11138 : {
11139 5 : varop = XEXP (varop, 0);
11140 5 : count = 0;
11141 5 : continue;
11142 : }
11143 :
11144 : /* NEG commutes with ASHIFT since it is multiplication. Move the
11145 : NEG outside to allow shifts to combine. */
11146 45004 : if (code == ASHIFT
11147 27123 : && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11148 : int_result_mode, &complement_p))
11149 : {
11150 17881 : varop = XEXP (varop, 0);
11151 17881 : continue;
11152 : }
11153 : break;
11154 :
11155 1889649 : case PLUS:
11156 : /* The following rules apply only to scalars. */
11157 1889649 : if (shift_mode != shift_unit_mode)
11158 : break;
11159 1844021 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11160 :
11161 : /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11162 : is one less than the number of bits in the mode is
11163 : equivalent to (xor A 1). */
11164 1844021 : if (code == LSHIFTRT
11165 390727 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11166 32164 : && XEXP (varop, 1) == constm1_rtx
11167 15129 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11168 1844021 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11169 : int_result_mode, &complement_p))
11170 : {
11171 0 : count = 0;
11172 0 : varop = XEXP (varop, 0);
11173 0 : continue;
11174 : }
11175 :
11176 : /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11177 : that might be nonzero in BAR are those being shifted out and those
11178 : bits are known zero in FOO, we can replace the PLUS with FOO.
11179 : Similarly in the other operand order. This code occurs when
11180 : we are computing the size of a variable-size array. */
11181 :
11182 1847292 : if ((code == ASHIFTRT || code == LSHIFTRT)
11183 553710 : && count < HOST_BITS_PER_WIDE_INT
11184 552541 : && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11185 2021751 : && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11186 177730 : & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11187 : {
11188 3271 : varop = XEXP (varop, 0);
11189 3271 : continue;
11190 : }
11191 1840791 : else if ((code == ASHIFTRT || code == LSHIFTRT)
11192 550439 : && count < HOST_BITS_PER_WIDE_INT
11193 549270 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11194 548040 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11195 548040 : >> count) == 0
11196 1931846 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11197 91096 : & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11198 : {
11199 41 : varop = XEXP (varop, 1);
11200 41 : continue;
11201 : }
11202 :
11203 : /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11204 2207744 : if (code == ASHIFT
11205 1281481 : && CONST_INT_P (XEXP (varop, 1))
11206 367190 : && (new_rtx = simplify_const_binary_operation
11207 367190 : (ASHIFT, int_result_mode,
11208 367190 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11209 367190 : gen_int_shift_amount (int_result_mode, count))) != 0
11210 367190 : && CONST_INT_P (new_rtx)
11211 2207899 : && merge_outer_ops (&outer_op, &outer_const, PLUS,
11212 : INTVAL (new_rtx), int_result_mode,
11213 : &complement_p))
11214 : {
11215 367035 : varop = XEXP (varop, 0);
11216 367035 : continue;
11217 : }
11218 :
11219 : /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11220 : signbit', and attempt to change the PLUS to an XOR and move it to
11221 : the outer operation as is done above in the AND/IOR/XOR case
11222 : leg for shift(logical). See details in logical handling above
11223 : for reasoning in doing so. */
11224 1481768 : if (code == LSHIFTRT
11225 387516 : && CONST_INT_P (XEXP (varop, 1))
11226 278918 : && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11227 8094 : && (new_rtx = simplify_const_binary_operation
11228 1473674 : (code, int_result_mode,
11229 8094 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11230 8094 : gen_int_shift_amount (int_result_mode, count))) != 0
11231 8094 : && CONST_INT_P (new_rtx)
11232 1481768 : && merge_outer_ops (&outer_op, &outer_const, XOR,
11233 : INTVAL (new_rtx), int_result_mode,
11234 : &complement_p))
11235 : {
11236 8094 : varop = XEXP (varop, 0);
11237 8094 : continue;
11238 : }
11239 :
11240 : break;
11241 :
11242 623250 : case MINUS:
11243 : /* The following rules apply only to scalars. */
11244 623250 : if (shift_mode != shift_unit_mode)
11245 : break;
11246 610250 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11247 :
11248 : /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11249 : with C the size of VAROP - 1 and the shift is logical if
11250 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11251 : we have a (gt X 0) operation. If the shift is arithmetic with
11252 : STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11253 : we have a (neg (gt X 0)) operation. */
11254 :
11255 610250 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11256 610250 : && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11257 12275 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11258 48 : && (code == LSHIFTRT || code == ASHIFTRT)
11259 13 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11260 13 : && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11261 610250 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11262 : {
11263 0 : count = 0;
11264 0 : varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11265 : const0_rtx);
11266 :
11267 0 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11268 0 : varop = gen_rtx_NEG (int_varop_mode, varop);
11269 :
11270 0 : continue;
11271 : }
11272 : break;
11273 :
11274 683 : case TRUNCATE:
11275 : /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11276 : if the truncate does not affect the value. */
11277 683 : if (code == LSHIFTRT
11278 525 : && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11279 525 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11280 683 : && (INTVAL (XEXP (XEXP (varop, 0), 1))
11281 525 : >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11282 1050 : - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11283 : {
11284 525 : rtx varop_inner = XEXP (varop, 0);
11285 525 : int new_count = count + INTVAL (XEXP (varop_inner, 1));
11286 525 : rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11287 525 : new_count);
11288 525 : varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11289 : XEXP (varop_inner, 0),
11290 : new_count_rtx);
11291 525 : varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11292 525 : count = 0;
11293 525 : continue;
11294 525 : }
11295 : break;
11296 :
11297 : default:
11298 : break;
11299 59721 : }
11300 :
11301 : break;
11302 : }
11303 :
11304 24131577 : shift_mode = result_mode;
11305 24131577 : if (shift_mode != mode)
11306 : {
11307 : /* We only change the modes of scalar shifts. */
11308 199412 : int_mode = as_a <scalar_int_mode> (mode);
11309 199412 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11310 199412 : shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11311 : int_mode, outer_op, outer_const);
11312 : }
11313 :
11314 : /* We have now finished analyzing the shift. The result should be
11315 : a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11316 : OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11317 : to the result of the shift. OUTER_CONST is the relevant constant,
11318 : but we must turn off all bits turned off in the shift. */
11319 :
11320 24131577 : if (outer_op == UNKNOWN
11321 20454442 : && orig_code == code && orig_count == count
11322 20405122 : && varop == orig_varop
11323 20231666 : && shift_mode == GET_MODE (varop))
11324 : return NULL_RTX;
11325 :
11326 : /* Make a SUBREG if necessary. If we can't make it, fail. */
11327 3902307 : varop = gen_lowpart (shift_mode, varop);
11328 3902307 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11329 : return NULL_RTX;
11330 :
11331 : /* If we have an outer operation and we just made a shift, it is
11332 : possible that we could have simplified the shift were it not
11333 : for the outer operation. So try to do the simplification
11334 : recursively. */
11335 :
11336 3902307 : if (outer_op != UNKNOWN)
11337 3677135 : x = simplify_shift_const_1 (code, shift_mode, varop, count);
11338 : else
11339 : x = NULL_RTX;
11340 :
11341 3677135 : if (x == NULL_RTX)
11342 3866770 : x = simplify_gen_binary (code, shift_mode, varop,
11343 3866770 : gen_int_shift_amount (shift_mode, count));
11344 :
11345 : /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11346 : turn off all the bits that the shift would have turned off. */
11347 3902307 : if (orig_code == LSHIFTRT && result_mode != shift_mode)
11348 : /* We only change the modes of scalar shifts. */
11349 27222 : x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11350 27222 : x, GET_MODE_MASK (result_mode) >> orig_count);
11351 :
11352 : /* Do the remainder of the processing in RESULT_MODE. */
11353 3902307 : x = gen_lowpart_or_truncate (result_mode, x);
11354 :
11355 : /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11356 : operation. */
11357 3902307 : if (complement_p)
11358 23750 : x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11359 :
11360 3902307 : if (outer_op != UNKNOWN)
11361 : {
11362 3677135 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11363 :
11364 3677135 : if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11365 3677135 : && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11366 1335926 : outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11367 :
11368 3677135 : if (outer_op == AND)
11369 3220872 : x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11370 456263 : else if (outer_op == SET)
11371 : {
11372 : /* This means that we have determined that the result is
11373 : equivalent to a constant. This should be rare. */
11374 0 : if (!side_effects_p (x))
11375 0 : x = GEN_INT (outer_const);
11376 : }
11377 456263 : else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11378 17881 : x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11379 : else
11380 438382 : x = simplify_gen_binary (outer_op, int_result_mode, x,
11381 : GEN_INT (outer_const));
11382 : }
11383 :
11384 : return x;
11385 : }
11386 :
11387 : /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11388 : The result of the shift is RESULT_MODE. If we cannot simplify it,
11389 : return X or, if it is NULL, synthesize the expression with
11390 : simplify_gen_binary. Otherwise, return a simplified value.
11391 :
11392 : The shift is normally computed in the widest mode we find in VAROP, as
11393 : long as it isn't a different number of words than RESULT_MODE. Exceptions
11394 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
11395 :
11396 : static rtx
11397 20454714 : simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11398 : rtx varop, int count)
11399 : {
11400 20454714 : rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11401 20454714 : if (tem)
11402 : return tem;
11403 :
11404 16587944 : if (!x)
11405 4956985 : x = simplify_gen_binary (code, GET_MODE (varop), varop,
11406 4956985 : gen_int_shift_amount (GET_MODE (varop), count));
11407 16587944 : if (GET_MODE (x) != result_mode)
11408 0 : x = gen_lowpart (result_mode, x);
11409 : return x;
11410 : }
11411 :
11412 :
11413 : /* A subroutine of recog_for_combine. See there for arguments and
11414 : return value. */
11415 :
11416 : static int
11417 49699244 : recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11418 : unsigned old_nregs, unsigned new_nregs)
11419 : {
11420 49699244 : rtx pat = *pnewpat;
11421 49699244 : rtx pat_without_clobbers;
11422 49699244 : int insn_code_number;
11423 49699244 : int num_clobbers_to_add = 0;
11424 49699244 : int i;
11425 49699244 : rtx notes = NULL_RTX;
11426 49699244 : rtx old_notes, old_pat;
11427 49699244 : int old_icode;
11428 :
11429 : /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11430 : we use to indicate that something didn't match. If we find such a
11431 : thing, force rejection. */
11432 49699244 : if (GET_CODE (pat) == PARALLEL)
11433 53722253 : for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11434 37033559 : if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11435 7466230 : && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11436 : return -1;
11437 :
11438 49697190 : old_pat = PATTERN (insn);
11439 49697190 : old_notes = REG_NOTES (insn);
11440 49697190 : PATTERN (insn) = pat;
11441 49697190 : REG_NOTES (insn) = NULL_RTX;
11442 :
11443 49697190 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11444 49697190 : if (dump_file && (dump_flags & TDF_DETAILS))
11445 : {
11446 277 : if (insn_code_number < 0)
11447 177 : fputs ("Failed to match this instruction:\n", dump_file);
11448 : else
11449 100 : fputs ("Successfully matched this instruction:\n", dump_file);
11450 277 : print_rtl_single (dump_file, pat);
11451 : }
11452 :
11453 : /* If it isn't, there is the possibility that we previously had an insn
11454 : that clobbered some register as a side effect, but the combined
11455 : insn doesn't need to do that. So try once more without the clobbers
11456 : unless this represents an ASM insn. */
11457 :
11458 39618204 : if (insn_code_number < 0 && ! check_asm_operands (pat)
11459 89313026 : && GET_CODE (pat) == PARALLEL)
11460 : {
11461 : int pos;
11462 :
11463 52216538 : for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11464 36008411 : if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11465 : {
11466 28956647 : if (i != pos)
11467 2365513 : SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11468 28956647 : pos++;
11469 : }
11470 :
11471 16208127 : SUBST_INT (XVECLEN (pat, 0), pos);
11472 :
11473 16208127 : if (pos == 1)
11474 4757730 : pat = XVECEXP (pat, 0, 0);
11475 :
11476 16208127 : PATTERN (insn) = pat;
11477 16208127 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11478 16208127 : if (dump_file && (dump_flags & TDF_DETAILS))
11479 : {
11480 82 : if (insn_code_number < 0)
11481 81 : fputs ("Failed to match this instruction:\n", dump_file);
11482 : else
11483 1 : fputs ("Successfully matched this instruction:\n", dump_file);
11484 82 : print_rtl_single (dump_file, pat);
11485 : }
11486 : }
11487 :
11488 49697190 : pat_without_clobbers = pat;
11489 :
11490 49697190 : PATTERN (insn) = old_pat;
11491 49697190 : REG_NOTES (insn) = old_notes;
11492 :
11493 : /* Recognize all noop sets, these will be killed by followup pass. */
11494 49697190 : if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11495 242022 : insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11496 :
11497 : /* If we had any clobbers to add, make a new pattern than contains
11498 : them. Then check to make sure that all of them are dead. */
11499 49697190 : if (num_clobbers_to_add)
11500 : {
11501 1661039 : rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11502 : rtvec_alloc (GET_CODE (pat) == PARALLEL
11503 : ? (XVECLEN (pat, 0)
11504 : + num_clobbers_to_add)
11505 : : num_clobbers_to_add + 1));
11506 :
11507 1661039 : if (GET_CODE (pat) == PARALLEL)
11508 1452 : for (i = 0; i < XVECLEN (pat, 0); i++)
11509 968 : XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11510 : else
11511 1660555 : XVECEXP (newpat, 0, 0) = pat;
11512 :
11513 1661039 : add_clobbers (newpat, insn_code_number);
11514 :
11515 3199661 : for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11516 3199661 : i < XVECLEN (newpat, 0); i++)
11517 : {
11518 1684275 : if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11519 1684275 : && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11520 : return -1;
11521 1538622 : if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11522 : {
11523 1487462 : gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11524 1487462 : notes = alloc_reg_note (REG_UNUSED,
11525 : XEXP (XVECEXP (newpat, 0, i), 0), notes);
11526 : }
11527 : }
11528 : pat = newpat;
11529 : }
11530 :
11531 49551537 : if (insn_code_number >= 0
11532 49551537 : && insn_code_number != NOOP_MOVE_INSN_CODE)
11533 : {
11534 : /* Create the reg dead notes if needed for the regs that were created via split. */
11535 10252016 : for (; old_nregs < new_nregs; old_nregs++)
11536 2243 : notes = alloc_reg_note (REG_DEAD, regno_reg_rtx[old_nregs], notes);
11537 10249773 : old_pat = PATTERN (insn);
11538 10249773 : old_notes = REG_NOTES (insn);
11539 10249773 : old_icode = INSN_CODE (insn);
11540 10249773 : PATTERN (insn) = pat;
11541 10249773 : REG_NOTES (insn) = notes;
11542 10249773 : INSN_CODE (insn) = insn_code_number;
11543 :
11544 : /* Do not accept an insn if hard register constraints are used. For
11545 : example, assume that the first insn is combined into the last one:
11546 :
11547 : r100=...
11548 : %5=...
11549 : r101=exp(r100)
11550 :
11551 : If the resulting insn has an operand which is constrained to hard
11552 : register %5, then this introduces a conflict since register %5 is live
11553 : at this point. Therefore, skip for now. This is a sledge hammer
11554 : approach. Ideally we would skip based on the fact whether a
11555 : combination crosses a hard register assignment and the corresponding
11556 : hard register is also referred by a single register constraint of the
11557 : resulting insn. */
11558 10249773 : bool has_hard_reg_cstr = false;
11559 10249773 : extract_insn (insn);
11560 34960496 : for (int nop = recog_data.n_operands - 1; nop >= 0; --nop)
11561 24710723 : if (strchr (recog_data.constraints[nop], '{'))
11562 : {
11563 : has_hard_reg_cstr = true;
11564 : break;
11565 : }
11566 :
11567 : /* Don't accept hard register constraints. Allow targets to reject
11568 : combined insn. */
11569 10249773 : if (has_hard_reg_cstr || !targetm.legitimate_combined_insn (insn))
11570 : {
11571 3656 : if (dump_file && (dump_flags & TDF_DETAILS))
11572 : {
11573 0 : if (has_hard_reg_cstr)
11574 0 : fputs ("Instruction makes use of hard register constraints.",
11575 : dump_file);
11576 : else
11577 0 : fputs ("Instruction not appropriate for target.",
11578 : dump_file);
11579 : }
11580 :
11581 : /* Callers expect recog_for_combine to strip
11582 : clobbers from the pattern on failure. */
11583 : pat = pat_without_clobbers;
11584 : notes = NULL_RTX;
11585 :
11586 : insn_code_number = -1;
11587 : }
11588 :
11589 10249773 : PATTERN (insn) = old_pat;
11590 10249773 : REG_NOTES (insn) = old_notes;
11591 10249773 : INSN_CODE (insn) = old_icode;
11592 : }
11593 :
11594 49551537 : *pnewpat = pat;
11595 49551537 : *pnotes = notes;
11596 :
11597 49551537 : return insn_code_number;
11598 : }
11599 :
11600 : /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11601 : expressed as an AND and maybe an LSHIFTRT, to that formulation.
11602 : Return whether anything was so changed. */
11603 :
11604 : static bool
11605 49878458 : change_zero_ext (rtx pat)
11606 : {
11607 49878458 : bool changed = false;
11608 49878458 : rtx *src = &SET_SRC (pat);
11609 :
11610 49878458 : subrtx_ptr_iterator::array_type array;
11611 347969232 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11612 : {
11613 298090774 : rtx x = **iter;
11614 298090774 : scalar_int_mode mode, inner_mode;
11615 298090774 : if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11616 298090774 : continue;
11617 156159309 : int size;
11618 :
11619 156159309 : if (GET_CODE (x) == ZERO_EXTRACT
11620 810490 : && CONST_INT_P (XEXP (x, 1))
11621 810476 : && CONST_INT_P (XEXP (x, 2))
11622 768195 : && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11623 156927500 : && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11624 : {
11625 768173 : size = INTVAL (XEXP (x, 1));
11626 :
11627 768173 : int start = INTVAL (XEXP (x, 2));
11628 768173 : if (BITS_BIG_ENDIAN)
11629 : start = GET_MODE_PRECISION (inner_mode) - size - start;
11630 :
11631 768173 : if (start != 0)
11632 651265 : x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11633 : gen_int_shift_amount (inner_mode, start));
11634 : else
11635 : x = XEXP (x, 0);
11636 :
11637 768173 : if (mode != inner_mode)
11638 : {
11639 148 : if (REG_P (x) && HARD_REGISTER_P (x)
11640 217685 : && !can_change_dest_mode (x, 0, mode))
11641 0 : continue;
11642 :
11643 217685 : x = gen_lowpart_SUBREG (mode, x);
11644 : }
11645 : }
11646 155391136 : else if (GET_CODE (x) == ZERO_EXTEND
11647 2282466 : && GET_CODE (XEXP (x, 0)) == SUBREG
11648 429348 : && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11649 421797 : && !paradoxical_subreg_p (XEXP (x, 0))
11650 155812933 : && subreg_lowpart_p (XEXP (x, 0)))
11651 : {
11652 293136 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11653 293136 : size = GET_MODE_PRECISION (inner_mode);
11654 293136 : x = SUBREG_REG (XEXP (x, 0));
11655 293136 : if (GET_MODE (x) != mode)
11656 : {
11657 17313 : if (REG_P (x) && HARD_REGISTER_P (x)
11658 20183 : && !can_change_dest_mode (x, 0, mode))
11659 0 : continue;
11660 :
11661 20183 : x = gen_lowpart_SUBREG (mode, x);
11662 : }
11663 : }
11664 310195927 : else if (GET_CODE (x) == ZERO_EXTEND
11665 1989330 : && REG_P (XEXP (x, 0))
11666 1017564 : && HARD_REGISTER_P (XEXP (x, 0))
11667 155098073 : && can_change_dest_mode (XEXP (x, 0), 0, mode))
11668 : {
11669 73 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11670 73 : size = GET_MODE_PRECISION (inner_mode);
11671 73 : x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11672 : }
11673 : else
11674 155097927 : continue;
11675 :
11676 1513104 : if (!(GET_CODE (x) == LSHIFTRT
11677 451722 : && CONST_INT_P (XEXP (x, 1))
11678 451722 : && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11679 : {
11680 877820 : wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11681 877820 : x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11682 877820 : }
11683 :
11684 1061382 : SUBST (**iter, x);
11685 1061382 : changed = true;
11686 : }
11687 :
11688 49878458 : if (changed)
11689 9763393 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11690 8715129 : maybe_swap_commutative_operands (**iter);
11691 :
11692 49878458 : rtx *dst = &SET_DEST (pat);
11693 49878458 : scalar_int_mode mode;
11694 49878458 : if (GET_CODE (*dst) == ZERO_EXTRACT
11695 8488 : && REG_P (XEXP (*dst, 0))
11696 262 : && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11697 262 : && CONST_INT_P (XEXP (*dst, 1))
11698 49878720 : && CONST_INT_P (XEXP (*dst, 2)))
11699 : {
11700 166 : rtx reg = XEXP (*dst, 0);
11701 166 : int width = INTVAL (XEXP (*dst, 1));
11702 166 : int offset = INTVAL (XEXP (*dst, 2));
11703 166 : int reg_width = GET_MODE_PRECISION (mode);
11704 166 : if (BITS_BIG_ENDIAN)
11705 : offset = reg_width - width - offset;
11706 :
11707 166 : rtx x, y, z, w;
11708 166 : wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11709 166 : wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11710 166 : x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11711 166 : if (offset)
11712 166 : y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11713 : else
11714 0 : y = SET_SRC (pat);
11715 166 : z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11716 166 : w = gen_rtx_IOR (mode, x, z);
11717 166 : SUBST (SET_DEST (pat), reg);
11718 166 : SUBST (SET_SRC (pat), w);
11719 :
11720 166 : changed = true;
11721 166 : }
11722 :
11723 49878458 : return changed;
11724 49878458 : }
11725 :
11726 : /* Like recog, but we receive the address of a pointer to a new pattern.
11727 : We try to match the rtx that the pointer points to.
11728 : If that fails, we may try to modify or replace the pattern,
11729 : storing the replacement into the same pointer object.
11730 :
11731 : Modifications include deletion or addition of CLOBBERs. If the
11732 : instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11733 : to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11734 : (and undo if that fails).
11735 :
11736 : PNOTES is a pointer to a location where any REG_UNUSED notes added for
11737 : the CLOBBERs are placed.
11738 : If OLD_NREGS != NEW_NREGS, then PNOTES also includes REG_DEAD notes added.
11739 :
11740 : The value is the final insn code from the pattern ultimately matched,
11741 : or -1. */
11742 :
11743 : static int
11744 48410568 : recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11745 : unsigned int old_nregs, unsigned int new_nregs)
11746 : {
11747 48410568 : rtx pat = *pnewpat;
11748 48410568 : int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11749 : old_nregs, new_nregs);
11750 48410568 : if (insn_code_number >= 0 || check_asm_operands (pat))
11751 : return insn_code_number;
11752 :
11753 38081305 : void *marker = get_undo_marker ();
11754 38081305 : bool changed = false;
11755 :
11756 38081305 : if (GET_CODE (pat) == SET)
11757 : {
11758 : /* For an unrecognized single set of a constant, try placing it in
11759 : the constant pool, if this function already uses one. */
11760 22446411 : rtx src = SET_SRC (pat);
11761 22446411 : if (CONSTANT_P (src)
11762 467195 : && !CONST_INT_P (src)
11763 418150 : && crtl->uses_const_pool
11764 365735 : && SET_DEST (pat) != pc_rtx)
11765 : {
11766 365733 : machine_mode mode = GET_MODE (src);
11767 365733 : if (mode == VOIDmode)
11768 1339 : mode = GET_MODE (SET_DEST (pat));
11769 365733 : src = force_const_mem (mode, src);
11770 365733 : if (src)
11771 : {
11772 365723 : SUBST (SET_SRC (pat), src);
11773 365723 : changed = true;
11774 : }
11775 : }
11776 : else
11777 22080678 : changed = change_zero_ext (pat);
11778 : }
11779 15634894 : else if (GET_CODE (pat) == PARALLEL)
11780 : {
11781 : int i;
11782 43674485 : for (i = 0; i < XVECLEN (pat, 0); i++)
11783 : {
11784 28055037 : rtx set = XVECEXP (pat, 0, i);
11785 28055037 : if (GET_CODE (set) == SET)
11786 27797780 : changed |= change_zero_ext (set);
11787 : }
11788 : }
11789 :
11790 38065849 : if (changed)
11791 : {
11792 1288676 : insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11793 : old_nregs, new_nregs);
11794 :
11795 1288676 : if (insn_code_number < 0)
11796 1127432 : undo_to_marker (marker);
11797 : }
11798 :
11799 : return insn_code_number;
11800 : }
11801 :
11802 : /* Like gen_lowpart_general but for use by combine. In combine it
11803 : is not possible to create any new pseudoregs. However, it is
11804 : safe to create invalid memory addresses, because combine will
11805 : try to recognize them and all they will do is make the combine
11806 : attempt fail.
11807 :
11808 : If for some reason this cannot do its job, an rtx
11809 : (clobber (const_int 0)) is returned.
11810 : An insn containing that will not be recognized. */
11811 :
11812 : static rtx
11813 158424020 : gen_lowpart_for_combine (machine_mode omode, rtx x)
11814 : {
11815 158424020 : machine_mode imode = GET_MODE (x);
11816 158424020 : rtx result;
11817 :
11818 158424020 : if (omode == imode)
11819 : return x;
11820 :
11821 : /* We can only support MODE being wider than a word if X is a
11822 : constant integer or has a mode the same size. */
11823 56059885 : if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11824 26561420 : && ! (CONST_SCALAR_INT_P (x)
11825 10186398 : || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11826 3074840 : goto fail;
11827 :
11828 : /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11829 : won't know what to do. So we will strip off the SUBREG here and
11830 : process normally. */
11831 23486580 : if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11832 : {
11833 13428 : x = SUBREG_REG (x);
11834 :
11835 : /* For use in case we fall down into the address adjustments
11836 : further below, we need to adjust the known mode and size of
11837 : x; imode and isize, since we just adjusted x. */
11838 13428 : imode = GET_MODE (x);
11839 :
11840 13428 : if (imode == omode)
11841 : return x;
11842 : }
11843 :
11844 23477656 : result = gen_lowpart_common (omode, x);
11845 :
11846 23477656 : if (result)
11847 : return result;
11848 :
11849 9903314 : if (MEM_P (x))
11850 : {
11851 : /* Refuse to work on a volatile memory ref or one with a mode-dependent
11852 : address. */
11853 1915422 : if (MEM_VOLATILE_P (x)
11854 3782277 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11855 48598 : goto fail;
11856 :
11857 : /* If we want to refer to something bigger than the original memref,
11858 : generate a paradoxical subreg instead. That will force a reload
11859 : of the original memref X. */
11860 1866824 : if (paradoxical_subreg_p (omode, imode)
11861 1866824 : && validate_subreg (omode, GET_MODE (x), x, 0))
11862 1652744 : return gen_rtx_SUBREG (omode, x, 0);
11863 :
11864 214080 : poly_int64 offset = byte_lowpart_offset (omode, imode);
11865 214080 : return adjust_address_nv (x, omode, offset);
11866 : }
11867 :
11868 : /* If X is a comparison operator, rewrite it in a new mode. This
11869 : probably won't match, but may allow further simplifications. */
11870 7987892 : else if (COMPARISON_P (x)
11871 148309 : && SCALAR_INT_MODE_P (imode)
11872 53717 : && SCALAR_INT_MODE_P (omode))
11873 53706 : return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11874 :
11875 : /* If we couldn't simplify X any other way, just enclose it in a
11876 : SUBREG. Normally, this SUBREG won't match, but some patterns may
11877 : include an explicit SUBREG or we may simplify it further in combine. */
11878 : else
11879 : {
11880 7934186 : rtx res;
11881 :
11882 7934186 : if (imode == VOIDmode)
11883 : {
11884 8 : imode = int_mode_for_mode (omode).require ();
11885 8 : x = gen_lowpart_common (imode, x);
11886 8 : if (x == NULL)
11887 0 : goto fail;
11888 : }
11889 7934186 : res = lowpart_subreg (omode, x, imode);
11890 7934186 : if (res)
11891 : return res;
11892 : }
11893 :
11894 16501 : fail:
11895 3139939 : return gen_rtx_CLOBBER (omode, const0_rtx);
11896 : }
11897 :
11898 : /* Like gen_lowpart_for_combine but returns NULL_RTX
11899 : for an error instead of CLOBBER.
11900 : Note no_emit is not called directly from combine but rather from
11901 : simplify_rtx and is expecting a NULL on failure rather than
11902 : a CLOBBER. */
11903 :
11904 : static rtx
11905 1561473 : gen_lowpart_for_combine_no_emit (machine_mode omode, rtx x)
11906 : {
11907 1561473 : rtx tem = gen_lowpart_for_combine (omode, x);
11908 1561473 : if (!tem || GET_CODE (tem) == CLOBBER)
11909 16159 : return NULL_RTX;
11910 : return tem;
11911 : }
11912 :
11913 :
11914 : /* Try to simplify a comparison between OP0 and a constant OP1,
11915 : where CODE is the comparison code that will be tested, into a
11916 : (CODE OP0 const0_rtx) form.
11917 :
11918 : The result is a possibly different comparison code to use.
11919 : *POP0 and *POP1 may be updated. */
11920 :
11921 : static enum rtx_code
11922 16164906 : simplify_compare_const (enum rtx_code code, machine_mode mode,
11923 : rtx *pop0, rtx *pop1)
11924 : {
11925 16164906 : scalar_int_mode int_mode;
11926 16164906 : rtx op0 = *pop0;
11927 16164906 : HOST_WIDE_INT const_op = INTVAL (*pop1);
11928 :
11929 : /* Get the constant we are comparing against and turn off all bits
11930 : not on in our mode. */
11931 16164906 : if (mode != VOIDmode)
11932 15763196 : const_op = trunc_int_for_mode (const_op, mode);
11933 :
11934 : /* If we are comparing against a constant power of two and the value
11935 : being compared can only have that single bit nonzero (e.g., it was
11936 : `and'ed with that bit), we can replace this with a comparison
11937 : with zero. */
11938 16164906 : if (const_op
11939 4252912 : && (code == EQ || code == NE || code == GEU || code == LTU
11940 : /* This optimization is incorrect for signed >= INT_MIN or
11941 : < INT_MIN, those are always true or always false. */
11942 25348 : || ((code == GE || code == LT) && const_op > 0))
11943 2857543 : && is_a <scalar_int_mode> (mode, &int_mode)
11944 2857543 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11945 2838396 : && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11946 17072811 : && (nonzero_bits (op0, int_mode)
11947 907905 : == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11948 : {
11949 5056 : code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11950 : const_op = 0;
11951 : }
11952 :
11953 : /* Similarly, if we are comparing a value known to be either -1 or
11954 : 0 with -1, change it to the opposite comparison against zero. */
11955 2429 : if (const_op == -1
11956 258748 : && (code == EQ || code == NE || code == GT || code == LE
11957 : || code == GEU || code == LTU)
11958 16408970 : && is_a <scalar_int_mode> (mode, &int_mode)
11959 16415939 : && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11960 : {
11961 12025 : code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11962 : const_op = 0;
11963 : }
11964 :
11965 : /* Do some canonicalizations based on the comparison code. We prefer
11966 : comparisons against zero and then prefer equality comparisons.
11967 : If we can reduce the size of a constant, we will do that too. */
11968 16152881 : switch (code)
11969 : {
11970 268684 : case LT:
11971 : /* < C is equivalent to <= (C - 1) */
11972 268684 : if (const_op > 0)
11973 : {
11974 5157 : const_op -= 1;
11975 5157 : code = LE;
11976 : /* ... fall through to LE case below. */
11977 461718 : gcc_fallthrough ();
11978 : }
11979 : else
11980 : break;
11981 :
11982 461718 : case LE:
11983 : /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11984 461718 : if (const_op < 0)
11985 : {
11986 52 : const_op += 1;
11987 52 : code = LT;
11988 : }
11989 :
11990 : /* If we are doing a <= 0 comparison on a value known to have
11991 : a zero sign bit, we can replace this with == 0. */
11992 461666 : else if (const_op == 0
11993 319645 : && is_a <scalar_int_mode> (mode, &int_mode)
11994 319645 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11995 781311 : && (nonzero_bits (op0, int_mode)
11996 319645 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11997 319645 : == 0)
11998 : code = EQ;
11999 : break;
12000 :
12001 239750 : case GE:
12002 : /* >= C is equivalent to > (C - 1). */
12003 239750 : if (const_op > 0)
12004 : {
12005 1317 : const_op -= 1;
12006 1317 : code = GT;
12007 : /* ... fall through to GT below. */
12008 261494 : gcc_fallthrough ();
12009 : }
12010 : else
12011 : break;
12012 :
12013 261494 : case GT:
12014 : /* > C is equivalent to >= (C + 1); we do this for C < 0. */
12015 261494 : if (const_op < 0)
12016 : {
12017 322 : const_op += 1;
12018 322 : code = GE;
12019 : }
12020 :
12021 : /* If we are doing a > 0 comparison on a value known to have
12022 : a zero sign bit, we can replace this with != 0. */
12023 261172 : else if (const_op == 0
12024 133755 : && is_a <scalar_int_mode> (mode, &int_mode)
12025 133755 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12026 394927 : && (nonzero_bits (op0, int_mode)
12027 133755 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12028 133755 : == 0)
12029 : code = NE;
12030 : break;
12031 :
12032 97242 : case LTU:
12033 : /* < C is equivalent to <= (C - 1). */
12034 97242 : if (const_op > 0)
12035 : {
12036 87660 : const_op -= 1;
12037 87660 : code = LEU;
12038 : /* ... fall through ... */
12039 87660 : gcc_fallthrough ();
12040 : }
12041 : /* (unsigned) < 0x80000000 is equivalent to >= 0. */
12042 9582 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12043 9582 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12044 8809 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12045 8809 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12046 : {
12047 : const_op = 0;
12048 : code = GE;
12049 : break;
12050 : }
12051 : else
12052 : break;
12053 :
12054 700154 : case LEU:
12055 : /* unsigned <= 0 is equivalent to == 0 */
12056 700154 : if (const_op == 0)
12057 : code = EQ;
12058 : /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12059 699692 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12060 699692 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12061 697751 : && ((unsigned HOST_WIDE_INT) const_op
12062 : == ((HOST_WIDE_INT_1U
12063 697751 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12064 : {
12065 : const_op = 0;
12066 : code = GE;
12067 : }
12068 : break;
12069 :
12070 31571 : case GEU:
12071 : /* >= C is equivalent to > (C - 1). */
12072 31571 : if (const_op > 1)
12073 : {
12074 22888 : const_op -= 1;
12075 22888 : code = GTU;
12076 : /* ... fall through ... */
12077 22888 : gcc_fallthrough ();
12078 : }
12079 :
12080 : /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12081 8683 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12082 8683 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12083 7427 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12084 7427 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12085 : {
12086 : const_op = 0;
12087 : code = LT;
12088 : break;
12089 : }
12090 : else
12091 : break;
12092 :
12093 523551 : case GTU:
12094 : /* unsigned > 0 is equivalent to != 0 */
12095 523551 : if (const_op == 0)
12096 : code = NE;
12097 : /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12098 523551 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12099 523551 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12100 522374 : && ((unsigned HOST_WIDE_INT) const_op
12101 : == (HOST_WIDE_INT_1U
12102 522374 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12103 : {
12104 : const_op = 0;
12105 : code = LT;
12106 : }
12107 : break;
12108 :
12109 : default:
12110 : break;
12111 : }
12112 :
12113 : /* Narrow non-symmetric comparison of memory and constant as e.g.
12114 : x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12115 : significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
12116 : x0 >= 0x40. */
12117 15447751 : if ((code == LEU || code == LTU || code == GEU || code == GTU)
12118 1238312 : && is_a <scalar_int_mode> (GET_MODE (op0), &int_mode)
12119 1238279 : && HWI_COMPUTABLE_MODE_P (int_mode)
12120 1233132 : && MEM_P (op0)
12121 79503 : && !MEM_VOLATILE_P (op0)
12122 : /* The optimization makes only sense for constants which are big enough
12123 : so that we have a chance to chop off something at all. */
12124 78638 : && ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12125 : /* Ensure that we do not overflow during normalization. */
12126 21635 : && (code != GTU
12127 3875 : || ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12128 : < HOST_WIDE_INT_M1U)
12129 16186541 : && trunc_int_for_mode (const_op, int_mode) == const_op)
12130 : {
12131 21635 : unsigned HOST_WIDE_INT n
12132 21635 : = (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12133 21635 : enum rtx_code adjusted_code;
12134 :
12135 : /* Normalize code to either LEU or GEU. */
12136 21635 : if (code == LTU)
12137 : {
12138 116 : --n;
12139 116 : adjusted_code = LEU;
12140 : }
12141 21519 : else if (code == GTU)
12142 : {
12143 3875 : ++n;
12144 3875 : adjusted_code = GEU;
12145 : }
12146 : else
12147 : adjusted_code = code;
12148 :
12149 21635 : scalar_int_mode narrow_mode_iter;
12150 67114 : FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12151 : {
12152 46141 : unsigned nbits = GET_MODE_PRECISION (int_mode)
12153 46141 : - GET_MODE_PRECISION (narrow_mode_iter);
12154 46141 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12155 46141 : unsigned HOST_WIDE_INT lower_bits = n & mask;
12156 46141 : if ((adjusted_code == LEU && lower_bits == mask)
12157 45886 : || (adjusted_code == GEU && lower_bits == 0))
12158 : {
12159 662 : n >>= nbits;
12160 662 : break;
12161 : }
12162 : }
12163 :
12164 21635 : if (narrow_mode_iter < int_mode)
12165 : {
12166 662 : if (dump_file && (dump_flags & TDF_DETAILS))
12167 : {
12168 12 : fprintf (
12169 : dump_file, "narrow comparison from mode %s to %s: (MEM %s "
12170 : HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12171 12 : HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12172 12 : GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12173 12 : (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12174 12 : GET_RTX_NAME (adjusted_code), n);
12175 : }
12176 662 : poly_int64 offset = (BYTES_BIG_ENDIAN
12177 662 : ? 0
12178 662 : : (GET_MODE_SIZE (int_mode)
12179 662 : - GET_MODE_SIZE (narrow_mode_iter)));
12180 662 : *pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12181 662 : *pop1 = gen_int_mode (n, narrow_mode_iter);
12182 662 : return adjusted_code;
12183 : }
12184 : }
12185 :
12186 16164244 : *pop1 = GEN_INT (const_op);
12187 16164244 : return code;
12188 : }
12189 :
12190 : /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12191 : comparison code that will be tested.
12192 :
12193 : The result is a possibly different comparison code to use. *POP0 and
12194 : *POP1 may be updated.
12195 :
12196 : It is possible that we might detect that a comparison is either always
12197 : true or always false. However, we do not perform general constant
12198 : folding in combine, so this knowledge isn't useful. Such tautologies
12199 : should have been detected earlier. Hence we ignore all such cases. */
12200 :
12201 : static enum rtx_code
12202 24509845 : simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12203 : {
12204 24509845 : rtx op0 = *pop0;
12205 24509845 : rtx op1 = *pop1;
12206 24509845 : rtx tem, tem1;
12207 24509845 : int i;
12208 24509845 : scalar_int_mode mode, inner_mode, tmode;
12209 24509845 : opt_scalar_int_mode tmode_iter;
12210 :
12211 : /* Try a few ways of applying the same transformation to both operands. */
12212 24510095 : while (1)
12213 : {
12214 : /* The test below this one won't handle SIGN_EXTENDs on these machines,
12215 : so check specially. */
12216 24510095 : if (!WORD_REGISTER_OPERATIONS
12217 24510095 : && code != GTU && code != GEU && code != LTU && code != LEU
12218 21305299 : && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12219 1458 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12220 1095 : && GET_CODE (XEXP (op1, 0)) == ASHIFT
12221 725 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12222 724 : && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12223 724 : && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12224 : && (is_a <scalar_int_mode>
12225 724 : (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12226 724 : && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12227 724 : && CONST_INT_P (XEXP (op0, 1))
12228 724 : && XEXP (op0, 1) == XEXP (op1, 1)
12229 91 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12230 91 : && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12231 91 : && (INTVAL (XEXP (op0, 1))
12232 91 : == (GET_MODE_PRECISION (mode)
12233 91 : - GET_MODE_PRECISION (inner_mode))))
12234 : {
12235 91 : op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12236 91 : op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12237 : }
12238 :
12239 : /* If both operands are the same constant shift, see if we can ignore the
12240 : shift. We can if the shift is a rotate or if the bits shifted out of
12241 : this shift are known to be zero for both inputs and if the type of
12242 : comparison is compatible with the shift. */
12243 24510095 : if (GET_CODE (op0) == GET_CODE (op1)
12244 3565647 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12245 3222690 : && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12246 3222690 : || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12247 668 : && (code != GT && code != LT && code != GE && code != LE))
12248 3222074 : || (GET_CODE (op0) == ASHIFTRT
12249 1409 : && (code != GTU && code != LTU
12250 1401 : && code != GEU && code != LEU)))
12251 1980 : && CONST_INT_P (XEXP (op0, 1))
12252 1952 : && INTVAL (XEXP (op0, 1)) >= 0
12253 1952 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12254 24512047 : && XEXP (op0, 1) == XEXP (op1, 1))
12255 : {
12256 878 : machine_mode mode = GET_MODE (op0);
12257 878 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12258 878 : int shift_count = INTVAL (XEXP (op0, 1));
12259 :
12260 878 : if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12261 477 : mask &= (mask >> shift_count) << shift_count;
12262 401 : else if (GET_CODE (op0) == ASHIFT)
12263 401 : mask = (mask & (mask << shift_count)) >> shift_count;
12264 :
12265 878 : if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12266 878 : && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12267 81 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12268 : else
12269 : break;
12270 : }
12271 :
12272 : /* If both operands are AND's of a paradoxical SUBREG by constant, the
12273 : SUBREGs are of the same mode, and, in both cases, the AND would
12274 : be redundant if the comparison was done in the narrower mode,
12275 : do the comparison in the narrower mode (e.g., we are AND'ing with 1
12276 : and the operand's possibly nonzero bits are 0xffffff01; in that case
12277 : if we only care about QImode, we don't need the AND). This case
12278 : occurs if the output mode of an scc insn is not SImode and
12279 : STORE_FLAG_VALUE == 1 (e.g., the 386).
12280 :
12281 : Similarly, check for a case where the AND's are ZERO_EXTEND
12282 : operations from some narrower mode even though a SUBREG is not
12283 : present. */
12284 :
12285 24509217 : else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12286 2568 : && CONST_INT_P (XEXP (op0, 1))
12287 2486 : && CONST_INT_P (XEXP (op1, 1)))
12288 : {
12289 2470 : rtx inner_op0 = XEXP (op0, 0);
12290 2470 : rtx inner_op1 = XEXP (op1, 0);
12291 2470 : HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12292 2470 : HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12293 2470 : bool changed = false;
12294 :
12295 2470 : if (paradoxical_subreg_p (inner_op0)
12296 1023 : && GET_CODE (inner_op1) == SUBREG
12297 489 : && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12298 489 : && (GET_MODE (SUBREG_REG (inner_op0))
12299 489 : == GET_MODE (SUBREG_REG (inner_op1)))
12300 209 : && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12301 : GET_MODE (SUBREG_REG (inner_op0)))) == 0
12302 1721 : && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12303 139 : GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12304 : {
12305 123 : op0 = SUBREG_REG (inner_op0);
12306 123 : op1 = SUBREG_REG (inner_op1);
12307 :
12308 : /* The resulting comparison is always unsigned since we masked
12309 : off the original sign bit. */
12310 123 : code = unsigned_condition (code);
12311 :
12312 123 : changed = true;
12313 : }
12314 :
12315 2347 : else if (c0 == c1)
12316 5084 : FOR_EACH_MODE_UNTIL (tmode,
12317 : as_a <scalar_int_mode> (GET_MODE (op0)))
12318 3113 : if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12319 : {
12320 35 : op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12321 35 : op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12322 35 : code = unsigned_condition (code);
12323 35 : changed = true;
12324 35 : break;
12325 : }
12326 :
12327 2129 : if (! changed)
12328 : break;
12329 : }
12330 :
12331 : /* If both operands are NOT, we can strip off the outer operation
12332 : and adjust the comparison code for swapped operands; similarly for
12333 : NEG, except that this must be an equality comparison. */
12334 24506747 : else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12335 24506747 : || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12336 11 : && (code == EQ || code == NE)))
12337 11 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12338 :
12339 : else
12340 : break;
12341 : }
12342 :
12343 : /* If the first operand is a constant, swap the operands and adjust the
12344 : comparison code appropriately, but don't do this if the second operand
12345 : is already a constant integer. */
12346 24509845 : if (swap_commutative_operands_p (op0, op1))
12347 : {
12348 1533346 : std::swap (op0, op1);
12349 1533346 : code = swap_condition (code);
12350 : }
12351 :
12352 : /* We now enter a loop during which we will try to simplify the comparison.
12353 : For the most part, we only are concerned with comparisons with zero,
12354 : but some things may really be comparisons with zero but not start
12355 : out looking that way. */
12356 :
12357 25631869 : while (CONST_INT_P (op1))
12358 : {
12359 16674524 : machine_mode raw_mode = GET_MODE (op0);
12360 16674524 : scalar_int_mode int_mode;
12361 16674524 : int equality_comparison_p;
12362 16674524 : int sign_bit_comparison_p;
12363 16674524 : int unsigned_comparison_p;
12364 16674524 : HOST_WIDE_INT const_op;
12365 :
12366 : /* We only want to handle integral modes. This catches VOIDmode,
12367 : CCmode, and the floating-point modes. An exception is that we
12368 : can handle VOIDmode if OP0 is a COMPARE or a comparison
12369 : operation. */
12370 :
12371 16674524 : if (GET_MODE_CLASS (raw_mode) != MODE_INT
12372 1724481 : && ! (raw_mode == VOIDmode
12373 401740 : && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12374 : break;
12375 :
12376 : /* Try to simplify the compare to constant, possibly changing the
12377 : comparison op, and/or changing op1 to zero. */
12378 15351753 : code = simplify_compare_const (code, raw_mode, &op0, &op1);
12379 15351753 : const_op = INTVAL (op1);
12380 :
12381 : /* Compute some predicates to simplify code below. */
12382 :
12383 15351753 : equality_comparison_p = (code == EQ || code == NE);
12384 15351753 : sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12385 15351753 : unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12386 15351753 : || code == GEU);
12387 :
12388 : /* If this is a sign bit comparison and we can do arithmetic in
12389 : MODE, say that we will only be needing the sign bit of OP0. */
12390 15351753 : if (sign_bit_comparison_p
12391 457105 : && is_a <scalar_int_mode> (raw_mode, &int_mode)
12392 15808858 : && HWI_COMPUTABLE_MODE_P (int_mode))
12393 456713 : op0 = force_to_mode (op0, int_mode,
12394 : HOST_WIDE_INT_1U
12395 456713 : << (GET_MODE_PRECISION (int_mode) - 1), false);
12396 :
12397 15351753 : if (COMPARISON_P (op0))
12398 : {
12399 : /* We can't do anything if OP0 is a condition code value, rather
12400 : than an actual data value. */
12401 726836 : if (const_op != 0
12402 726836 : || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12403 : break;
12404 :
12405 : /* Get the two operands being compared. */
12406 138387 : if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12407 0 : tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12408 : else
12409 138387 : tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12410 :
12411 : /* Check for the cases where we simply want the result of the
12412 : earlier test or the opposite of that result. */
12413 138387 : if (code == NE || code == EQ
12414 138387 : || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12415 0 : && (code == LT || code == GE)))
12416 : {
12417 138387 : enum rtx_code new_code;
12418 138387 : if (code == LT || code == NE)
12419 138387 : new_code = GET_CODE (op0);
12420 : else
12421 0 : new_code = reversed_comparison_code (op0, NULL);
12422 :
12423 138387 : if (new_code != UNKNOWN)
12424 : {
12425 138387 : code = new_code;
12426 138387 : op0 = tem;
12427 138387 : op1 = tem1;
12428 1122024 : continue;
12429 : }
12430 : }
12431 : break;
12432 : }
12433 :
12434 14624917 : if (raw_mode == VOIDmode)
12435 : break;
12436 14624917 : scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12437 :
12438 : /* Now try cases based on the opcode of OP0. If none of the cases
12439 : does a "continue", we exit this loop immediately after the
12440 : switch. */
12441 :
12442 14624917 : unsigned int mode_width = GET_MODE_PRECISION (mode);
12443 14624917 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12444 14624917 : switch (GET_CODE (op0))
12445 : {
12446 385468 : case ZERO_EXTRACT:
12447 : /* If we are extracting a single bit from a variable position in
12448 : a constant that has only a single bit set and are comparing it
12449 : with zero, we can convert this into an equality comparison
12450 : between the position and the location of the single bit. */
12451 : /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12452 : have already reduced the shift count modulo the word size. */
12453 385468 : if (!SHIFT_COUNT_TRUNCATED
12454 385468 : && CONST_INT_P (XEXP (op0, 0))
12455 9226 : && XEXP (op0, 1) == const1_rtx
12456 9208 : && equality_comparison_p && const_op == 0
12457 394676 : && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12458 : {
12459 0 : if (BITS_BIG_ENDIAN)
12460 : i = BITS_PER_WORD - 1 - i;
12461 :
12462 0 : op0 = XEXP (op0, 2);
12463 0 : op1 = GEN_INT (i);
12464 0 : const_op = i;
12465 :
12466 : /* Result is nonzero iff shift count is equal to I. */
12467 0 : code = reverse_condition (code);
12468 0 : continue;
12469 : }
12470 :
12471 : /* fall through */
12472 :
12473 385472 : case SIGN_EXTRACT:
12474 385472 : tem = expand_compound_operation (op0);
12475 385472 : if (tem != op0)
12476 : {
12477 352286 : op0 = tem;
12478 352286 : continue;
12479 : }
12480 : break;
12481 :
12482 28559 : case NOT:
12483 : /* If testing for equality, we can take the NOT of the constant. */
12484 40636 : if (equality_comparison_p
12485 28559 : && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12486 : {
12487 12077 : op0 = XEXP (op0, 0);
12488 12077 : op1 = tem;
12489 12077 : continue;
12490 : }
12491 :
12492 : /* If just looking at the sign bit, reverse the sense of the
12493 : comparison. */
12494 16482 : if (sign_bit_comparison_p)
12495 : {
12496 16118 : op0 = XEXP (op0, 0);
12497 16118 : code = (code == GE ? LT : GE);
12498 16118 : continue;
12499 : }
12500 : break;
12501 :
12502 246349 : case NEG:
12503 : /* If testing for equality, we can take the NEG of the constant. */
12504 489150 : if (equality_comparison_p
12505 246349 : && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12506 : {
12507 242801 : op0 = XEXP (op0, 0);
12508 242801 : op1 = tem;
12509 242801 : continue;
12510 : }
12511 :
12512 : /* The remaining cases only apply to comparisons with zero. */
12513 3548 : if (const_op != 0)
12514 : break;
12515 :
12516 : /* When X is ABS or is known positive,
12517 : (neg X) is < 0 if and only if X != 0. */
12518 :
12519 3002 : if (sign_bit_comparison_p
12520 2964 : && (GET_CODE (XEXP (op0, 0)) == ABS
12521 2959 : || (mode_width <= HOST_BITS_PER_WIDE_INT
12522 2959 : && (nonzero_bits (XEXP (op0, 0), mode)
12523 2959 : & (HOST_WIDE_INT_1U << (mode_width - 1)))
12524 2959 : == 0)))
12525 : {
12526 38 : op0 = XEXP (op0, 0);
12527 38 : code = (code == LT ? NE : EQ);
12528 38 : continue;
12529 : }
12530 :
12531 : /* If we have NEG of something whose two high-order bits are the
12532 : same, we know that "(-a) < 0" is equivalent to "a > 0". */
12533 2926 : if (num_sign_bit_copies (op0, mode) >= 2)
12534 : {
12535 22 : op0 = XEXP (op0, 0);
12536 22 : code = swap_condition (code);
12537 22 : continue;
12538 : }
12539 : break;
12540 :
12541 146 : case ROTATE:
12542 : /* If we are testing equality and our count is a constant, we
12543 : can perform the inverse operation on our RHS. */
12544 146 : if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12545 146 : && (tem = simplify_binary_operation (ROTATERT, mode,
12546 : op1, XEXP (op0, 1))) != 0)
12547 : {
12548 0 : op0 = XEXP (op0, 0);
12549 0 : op1 = tem;
12550 0 : continue;
12551 : }
12552 :
12553 : /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12554 : a particular bit. Convert it to an AND of a constant of that
12555 : bit. This will be converted into a ZERO_EXTRACT. */
12556 146 : if (const_op == 0 && sign_bit_comparison_p
12557 0 : && CONST_INT_P (XEXP (op0, 1))
12558 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
12559 0 : && UINTVAL (XEXP (op0, 1)) < mode_width)
12560 : {
12561 0 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12562 : (HOST_WIDE_INT_1U
12563 : << (mode_width - 1
12564 0 : - INTVAL (XEXP (op0, 1)))));
12565 0 : code = (code == LT ? NE : EQ);
12566 0 : continue;
12567 : }
12568 :
12569 : /* Fall through. */
12570 :
12571 1546 : case ABS:
12572 : /* ABS is ignorable inside an equality comparison with zero. */
12573 1546 : if (const_op == 0 && equality_comparison_p)
12574 : {
12575 1 : op0 = XEXP (op0, 0);
12576 1 : continue;
12577 : }
12578 : break;
12579 :
12580 1765 : case SIGN_EXTEND:
12581 : /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12582 : (compare FOO CONST) if CONST fits in FOO's mode and we
12583 : are either testing inequality or have an unsigned
12584 : comparison with ZERO_EXTEND or a signed comparison with
12585 : SIGN_EXTEND. But don't do it if we don't have a compare
12586 : insn of the given mode, since we'd have to revert it
12587 : later on, and then we wouldn't know whether to sign- or
12588 : zero-extend. */
12589 1765 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12590 1765 : && ! unsigned_comparison_p
12591 997 : && HWI_COMPUTABLE_MODE_P (mode)
12592 997 : && trunc_int_for_mode (const_op, mode) == const_op
12593 997 : && have_insn_for (COMPARE, mode))
12594 : {
12595 997 : op0 = XEXP (op0, 0);
12596 997 : continue;
12597 : }
12598 : break;
12599 :
12600 485529 : case SUBREG:
12601 : /* Check for the case where we are comparing A - C1 with C2, that is
12602 :
12603 : (subreg:MODE (plus (A) (-C1))) op (C2)
12604 :
12605 : with C1 a constant, and try to lift the SUBREG, i.e. to do the
12606 : comparison in the wider mode. One of the following two conditions
12607 : must be true in order for this to be valid:
12608 :
12609 : 1. The mode extension results in the same bit pattern being added
12610 : on both sides and the comparison is equality or unsigned. As
12611 : C2 has been truncated to fit in MODE, the pattern can only be
12612 : all 0s or all 1s.
12613 :
12614 : 2. The mode extension results in the sign bit being copied on
12615 : each side.
12616 :
12617 : The difficulty here is that we have predicates for A but not for
12618 : (A - C1) so we need to check that C1 is within proper bounds so
12619 : as to perturb A as little as possible. */
12620 :
12621 485529 : if (mode_width <= HOST_BITS_PER_WIDE_INT
12622 485453 : && subreg_lowpart_p (op0)
12623 454620 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12624 : &inner_mode)
12625 452505 : && GET_MODE_PRECISION (inner_mode) > mode_width
12626 452505 : && GET_CODE (SUBREG_REG (op0)) == PLUS
12627 485529 : && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12628 : {
12629 0 : rtx a = XEXP (SUBREG_REG (op0), 0);
12630 0 : HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12631 :
12632 0 : if ((c1 > 0
12633 0 : && (unsigned HOST_WIDE_INT) c1
12634 0 : < HOST_WIDE_INT_1U << (mode_width - 1)
12635 0 : && (equality_comparison_p || unsigned_comparison_p)
12636 : /* (A - C1) zero-extends if it is positive and sign-extends
12637 : if it is negative, C2 both zero- and sign-extends. */
12638 0 : && (((nonzero_bits (a, inner_mode)
12639 0 : & ~GET_MODE_MASK (mode)) == 0
12640 0 : && const_op >= 0)
12641 : /* (A - C1) sign-extends if it is positive and 1-extends
12642 : if it is negative, C2 both sign- and 1-extends. */
12643 0 : || (num_sign_bit_copies (a, inner_mode)
12644 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12645 0 : - mode_width)
12646 0 : && const_op < 0)))
12647 0 : || ((unsigned HOST_WIDE_INT) c1
12648 0 : < HOST_WIDE_INT_1U << (mode_width - 2)
12649 : /* (A - C1) always sign-extends, like C2. */
12650 0 : && num_sign_bit_copies (a, inner_mode)
12651 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12652 0 : - (mode_width - 1))))
12653 : {
12654 0 : op0 = SUBREG_REG (op0);
12655 0 : continue;
12656 : }
12657 : }
12658 :
12659 : /* If the inner mode is narrower and we are extracting the low part,
12660 : we can treat the SUBREG as if it were a ZERO_EXTEND ... */
12661 485529 : if (paradoxical_subreg_p (op0))
12662 : {
12663 : if (WORD_REGISTER_OPERATIONS
12664 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12665 : &inner_mode)
12666 : && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD
12667 : /* On WORD_REGISTER_OPERATIONS targets the bits
12668 : beyond sub_mode aren't considered undefined,
12669 : so optimize only if it is a MEM load when MEM loads
12670 : zero extend, because then the upper bits are all zero. */
12671 : && !(MEM_P (SUBREG_REG (op0))
12672 : && load_extend_op (inner_mode) == ZERO_EXTEND))
12673 : break;
12674 : /* FALLTHROUGH to case ZERO_EXTEND */
12675 : }
12676 485529 : else if (subreg_lowpart_p (op0)
12677 454696 : && GET_MODE_CLASS (mode) == MODE_INT
12678 454696 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12679 452505 : && (code == NE || code == EQ)
12680 320373 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12681 314426 : && !paradoxical_subreg_p (op0)
12682 799955 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12683 314426 : & ~GET_MODE_MASK (mode)) == 0)
12684 : {
12685 : /* Remove outer subregs that don't do anything. */
12686 63081 : tem = gen_lowpart (inner_mode, op1);
12687 :
12688 63081 : if ((nonzero_bits (tem, inner_mode)
12689 63081 : & ~GET_MODE_MASK (mode)) == 0)
12690 : {
12691 62393 : op0 = SUBREG_REG (op0);
12692 62393 : op1 = tem;
12693 62393 : continue;
12694 : }
12695 : break;
12696 : }
12697 : else
12698 : break;
12699 :
12700 : /* FALLTHROUGH */
12701 :
12702 42017 : case ZERO_EXTEND:
12703 42017 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12704 42017 : && (unsigned_comparison_p || equality_comparison_p)
12705 41973 : && HWI_COMPUTABLE_MODE_P (mode)
12706 41973 : && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12707 41973 : && const_op >= 0
12708 41964 : && have_insn_for (COMPARE, mode))
12709 : {
12710 41964 : op0 = XEXP (op0, 0);
12711 41964 : continue;
12712 : }
12713 : break;
12714 :
12715 460047 : case PLUS:
12716 : /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12717 : this for equality comparisons due to pathological cases involving
12718 : overflows. */
12719 514024 : if (equality_comparison_p
12720 460047 : && (tem = simplify_binary_operation (MINUS, mode,
12721 : op1, XEXP (op0, 1))) != 0)
12722 : {
12723 53977 : op0 = XEXP (op0, 0);
12724 53977 : op1 = tem;
12725 53977 : continue;
12726 : }
12727 :
12728 : /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12729 406070 : if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12730 15334 : && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12731 : {
12732 0 : op0 = XEXP (XEXP (op0, 0), 0);
12733 0 : code = (code == LT ? EQ : NE);
12734 0 : continue;
12735 : }
12736 : break;
12737 :
12738 186743 : case MINUS:
12739 : /* We used to optimize signed comparisons against zero, but that
12740 : was incorrect. Unsigned comparisons against zero (GTU, LEU)
12741 : arrive here as equality comparisons, or (GEU, LTU) are
12742 : optimized away. No need to special-case them. */
12743 :
12744 : /* (eq (minus A B) C) -> (eq A (plus B C)) or
12745 : (eq B (minus A C)), whichever simplifies. We can only do
12746 : this for equality comparisons due to pathological cases involving
12747 : overflows. */
12748 219162 : if (equality_comparison_p
12749 186743 : && (tem = simplify_binary_operation (PLUS, mode,
12750 : XEXP (op0, 1), op1)) != 0)
12751 : {
12752 32419 : op0 = XEXP (op0, 0);
12753 32419 : op1 = tem;
12754 32419 : continue;
12755 : }
12756 :
12757 189107 : if (equality_comparison_p
12758 154324 : && (tem = simplify_binary_operation (MINUS, mode,
12759 : XEXP (op0, 0), op1)) != 0)
12760 : {
12761 34783 : op0 = XEXP (op0, 1);
12762 34783 : op1 = tem;
12763 34783 : continue;
12764 : }
12765 :
12766 : /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12767 : of bits in X minus 1, is one iff X > 0. */
12768 15875 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12769 489 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12770 489 : && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12771 119565 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12772 : {
12773 0 : op0 = XEXP (op0, 1);
12774 0 : code = (code == GE ? LE : GT);
12775 0 : continue;
12776 : }
12777 : break;
12778 :
12779 8909 : case XOR:
12780 : /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12781 : if C is zero or B is a constant. */
12782 8925 : if (equality_comparison_p
12783 8909 : && (tem = simplify_binary_operation (XOR, mode,
12784 : XEXP (op0, 1), op1)) != 0)
12785 : {
12786 16 : op0 = XEXP (op0, 0);
12787 16 : op1 = tem;
12788 16 : continue;
12789 : }
12790 : break;
12791 :
12792 :
12793 414703 : case IOR:
12794 : /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12795 : iff X <= 0. */
12796 7543 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12797 1258 : && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12798 414751 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12799 : {
12800 48 : op0 = XEXP (op0, 1);
12801 48 : code = (code == GE ? GT : LE);
12802 48 : continue;
12803 : }
12804 : break;
12805 :
12806 1661181 : case AND:
12807 : /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12808 : will be converted to a ZERO_EXTRACT later. */
12809 1661181 : if (const_op == 0 && equality_comparison_p
12810 1547758 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12811 60881 : && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12812 : {
12813 6830 : op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12814 : XEXP (XEXP (op0, 0), 1));
12815 6830 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12816 6830 : continue;
12817 : }
12818 :
12819 : /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12820 : zero and X is a comparison and C1 and C2 describe only bits set
12821 : in STORE_FLAG_VALUE, we can compare with X. */
12822 1654351 : if (const_op == 0 && equality_comparison_p
12823 1540928 : && mode_width <= HOST_BITS_PER_WIDE_INT
12824 1537039 : && CONST_INT_P (XEXP (op0, 1))
12825 1186510 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12826 506740 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12827 493058 : && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12828 493058 : && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12829 : {
12830 493058 : mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12831 493058 : << INTVAL (XEXP (XEXP (op0, 0), 1)));
12832 493058 : if ((~STORE_FLAG_VALUE & mask) == 0
12833 493058 : && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12834 0 : || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12835 0 : && COMPARISON_P (tem))))
12836 : {
12837 0 : op0 = XEXP (XEXP (op0, 0), 0);
12838 0 : continue;
12839 : }
12840 : }
12841 :
12842 : /* If we are doing an equality comparison of an AND of a bit equal
12843 : to the sign bit, replace this with a LT or GE comparison of
12844 : the underlying value. */
12845 1654907 : if (equality_comparison_p
12846 : && const_op == 0
12847 1540928 : && CONST_INT_P (XEXP (op0, 1))
12848 1186821 : && mode_width <= HOST_BITS_PER_WIDE_INT
12849 1654351 : && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12850 1186510 : == HOST_WIDE_INT_1U << (mode_width - 1)))
12851 : {
12852 556 : op0 = XEXP (op0, 0);
12853 556 : code = (code == EQ ? GE : LT);
12854 556 : continue;
12855 : }
12856 :
12857 : /* If this AND operation is really a ZERO_EXTEND from a narrower
12858 : mode, the constant fits within that mode, and this is either an
12859 : equality or unsigned comparison, try to do this comparison in
12860 : the narrower mode.
12861 :
12862 : Note that in:
12863 :
12864 : (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12865 : -> (ne:DI (reg:SI 4) (const_int 0))
12866 :
12867 : unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12868 : known to hold a value of the required mode the
12869 : transformation is invalid. */
12870 1669742 : if ((equality_comparison_p || unsigned_comparison_p)
12871 1638290 : && CONST_INT_P (XEXP (op0, 1))
12872 3805662 : && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12873 1279345 : & GET_MODE_MASK (mode))
12874 : + 1)) >= 0
12875 888469 : && const_op >> i == 0
12876 2542264 : && int_mode_for_size (i, 1).exists (&tmode))
12877 : {
12878 15947 : op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12879 15947 : continue;
12880 : }
12881 :
12882 : /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12883 1637848 : if (const_op == 0 && equality_comparison_p
12884 1529614 : && XEXP (op0, 1) == const1_rtx
12885 669549 : && GET_CODE (XEXP (op0, 0)) == NOT)
12886 : {
12887 6136 : op0 = simplify_and_const_int (NULL_RTX, mode,
12888 : XEXP (XEXP (op0, 0), 0), 1);
12889 6136 : code = (code == NE ? EQ : NE);
12890 6136 : continue;
12891 : }
12892 :
12893 : /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12894 : (eq (and (lshiftrt X) 1) 0).
12895 : Also handle the case where (not X) is expressed using xor. */
12896 1631712 : if (const_op == 0 && equality_comparison_p
12897 1523478 : && XEXP (op0, 1) == const1_rtx
12898 663413 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12899 : {
12900 500738 : rtx shift_op = XEXP (XEXP (op0, 0), 0);
12901 500738 : rtx shift_count = XEXP (XEXP (op0, 0), 1);
12902 :
12903 503542 : if (GET_CODE (shift_op) == NOT
12904 500738 : || (GET_CODE (shift_op) == XOR
12905 4225 : && CONST_INT_P (XEXP (shift_op, 1))
12906 2804 : && CONST_INT_P (shift_count)
12907 2804 : && HWI_COMPUTABLE_MODE_P (mode)
12908 2804 : && (UINTVAL (XEXP (shift_op, 1))
12909 : == HOST_WIDE_INT_1U
12910 2804 : << INTVAL (shift_count))))
12911 : {
12912 2804 : op0
12913 2804 : = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12914 2804 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12915 2804 : code = (code == NE ? EQ : NE);
12916 2804 : continue;
12917 : }
12918 : }
12919 : break;
12920 :
12921 47693 : case ASHIFT:
12922 : /* If we have (compare (ashift FOO N) (const_int C)) and
12923 : the high order N bits of FOO (N+1 if an inequality comparison)
12924 : are known to be zero, we can do this by comparing FOO with C
12925 : shifted right N bits so long as the low-order N bits of C are
12926 : zero. */
12927 47693 : if (CONST_INT_P (XEXP (op0, 1))
12928 44011 : && INTVAL (XEXP (op0, 1)) >= 0
12929 44011 : && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12930 : < HOST_BITS_PER_WIDE_INT)
12931 44011 : && (((unsigned HOST_WIDE_INT) const_op
12932 44011 : & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12933 : - 1)) == 0)
12934 37121 : && mode_width <= HOST_BITS_PER_WIDE_INT
12935 84784 : && (nonzero_bits (XEXP (op0, 0), mode)
12936 37091 : & ~(mask >> (INTVAL (XEXP (op0, 1))
12937 37091 : + ! equality_comparison_p))) == 0)
12938 : {
12939 : /* We must perform a logical shift, not an arithmetic one,
12940 : as we want the top N bits of C to be zero. */
12941 742 : unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12942 :
12943 742 : temp >>= INTVAL (XEXP (op0, 1));
12944 742 : op1 = gen_int_mode (temp, mode);
12945 742 : op0 = XEXP (op0, 0);
12946 742 : continue;
12947 742 : }
12948 :
12949 : /* If we are doing a sign bit comparison, it means we are testing
12950 : a particular bit. Convert it to the appropriate AND. */
12951 46951 : if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12952 1806 : && mode_width <= HOST_BITS_PER_WIDE_INT)
12953 : {
12954 3612 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12955 : (HOST_WIDE_INT_1U
12956 : << (mode_width - 1
12957 1806 : - INTVAL (XEXP (op0, 1)))));
12958 1806 : code = (code == LT ? NE : EQ);
12959 1806 : continue;
12960 : }
12961 :
12962 : /* If this an equality comparison with zero and we are shifting
12963 : the low bit to the sign bit, we can convert this to an AND of the
12964 : low-order bit. */
12965 45145 : if (const_op == 0 && equality_comparison_p
12966 15196 : && CONST_INT_P (XEXP (op0, 1))
12967 12724 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12968 : {
12969 310 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12970 310 : continue;
12971 : }
12972 : break;
12973 :
12974 44670 : case ASHIFTRT:
12975 : /* If this is an equality comparison with zero, we can do this
12976 : as a logical shift, which might be much simpler. */
12977 44670 : if (equality_comparison_p && const_op == 0
12978 26712 : && CONST_INT_P (XEXP (op0, 1)))
12979 : {
12980 51798 : op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12981 : XEXP (op0, 0),
12982 25899 : INTVAL (XEXP (op0, 1)));
12983 25899 : continue;
12984 : }
12985 :
12986 : /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12987 : do the comparison in a narrower mode. */
12988 23695 : if (! unsigned_comparison_p
12989 17518 : && CONST_INT_P (XEXP (op0, 1))
12990 16613 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12991 5514 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12992 5412 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12993 18771 : .exists (&tmode))
12994 18771 : && (((unsigned HOST_WIDE_INT) const_op
12995 4924 : + (GET_MODE_MASK (tmode) >> 1) + 1)
12996 4924 : <= GET_MODE_MASK (tmode)))
12997 : {
12998 4924 : op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12999 4924 : continue;
13000 : }
13001 :
13002 : /* Likewise if OP0 is a PLUS of a sign extension with a
13003 : constant, which is usually represented with the PLUS
13004 : between the shifts. */
13005 13847 : if (! unsigned_comparison_p
13006 12594 : && CONST_INT_P (XEXP (op0, 1))
13007 11689 : && GET_CODE (XEXP (op0, 0)) == PLUS
13008 54 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
13009 22 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
13010 2 : && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
13011 0 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13012 13847 : .exists (&tmode))
13013 13847 : && (((unsigned HOST_WIDE_INT) const_op
13014 0 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13015 0 : <= GET_MODE_MASK (tmode)))
13016 : {
13017 0 : rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
13018 0 : rtx add_const = XEXP (XEXP (op0, 0), 1);
13019 0 : rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
13020 : add_const, XEXP (op0, 1));
13021 :
13022 0 : op0 = simplify_gen_binary (PLUS, tmode,
13023 0 : gen_lowpart (tmode, inner),
13024 : new_const);
13025 0 : continue;
13026 0 : }
13027 :
13028 : /* FALLTHROUGH */
13029 133023 : case LSHIFTRT:
13030 : /* If we have (compare (xshiftrt FOO N) (const_int C)) and
13031 : the low order N bits of FOO are known to be zero, we can do this
13032 : by comparing FOO with C shifted left N bits so long as no
13033 : overflow occurs. Even if the low order N bits of FOO aren't known
13034 : to be zero, if the comparison is >= or < we can use the same
13035 : optimization and for > or <= by setting all the low
13036 : order N bits in the comparison constant. */
13037 133023 : if (CONST_INT_P (XEXP (op0, 1))
13038 128229 : && INTVAL (XEXP (op0, 1)) > 0
13039 128229 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
13040 127869 : && mode_width <= HOST_BITS_PER_WIDE_INT
13041 133023 : && (((unsigned HOST_WIDE_INT) const_op
13042 254224 : + (GET_CODE (op0) != LSHIFTRT
13043 127112 : ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
13044 : + 1)
13045 : : 0))
13046 127112 : <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
13047 : {
13048 126935 : unsigned HOST_WIDE_INT low_bits
13049 126935 : = (nonzero_bits (XEXP (op0, 0), mode)
13050 126935 : & ((HOST_WIDE_INT_1U
13051 126935 : << INTVAL (XEXP (op0, 1))) - 1));
13052 126935 : if (low_bits == 0 || !equality_comparison_p)
13053 : {
13054 : /* If the shift was logical, then we must make the condition
13055 : unsigned. */
13056 18852 : if (GET_CODE (op0) == LSHIFTRT)
13057 16169 : code = unsigned_condition (code);
13058 :
13059 18852 : const_op = (unsigned HOST_WIDE_INT) const_op
13060 18852 : << INTVAL (XEXP (op0, 1));
13061 18852 : if (low_bits != 0
13062 2973 : && (code == GT || code == GTU
13063 1027 : || code == LE || code == LEU))
13064 2905 : const_op
13065 2905 : |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
13066 18852 : op1 = GEN_INT (const_op);
13067 18852 : op0 = XEXP (op0, 0);
13068 18852 : continue;
13069 : }
13070 : }
13071 :
13072 : /* If we are using this shift to extract just the sign bit, we
13073 : can replace this with an LT or GE comparison. */
13074 114171 : if (const_op == 0
13075 98161 : && (equality_comparison_p || sign_bit_comparison_p)
13076 98125 : && CONST_INT_P (XEXP (op0, 1))
13077 93606 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13078 : {
13079 48891 : op0 = XEXP (op0, 0);
13080 48891 : code = (code == NE || code == GT ? LT : GE);
13081 48891 : continue;
13082 : }
13083 : break;
13084 :
13085 : default:
13086 : break;
13087 : }
13088 :
13089 : break;
13090 : }
13091 :
13092 : /* Now make any compound operations involved in this comparison. Then,
13093 : check for an outermost SUBREG on OP0 that is not doing anything or is
13094 : paradoxical. The latter transformation must only be performed when
13095 : it is known that the "extra" bits will be the same in op0 and op1 or
13096 : that they don't matter. There are three cases to consider:
13097 :
13098 : 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13099 : care bits and we can assume they have any convenient value. So
13100 : making the transformation is safe.
13101 :
13102 : 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13103 : In this case the upper bits of op0 are undefined. We should not make
13104 : the simplification in that case as we do not know the contents of
13105 : those bits.
13106 :
13107 : 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13108 : In that case we know those bits are zeros or ones. We must also be
13109 : sure that they are the same as the upper bits of op1.
13110 :
13111 : We can never remove a SUBREG for a non-equality comparison because
13112 : the sign bit is in a different place in the underlying object. */
13113 :
13114 24509845 : rtx_code op0_mco_code = SET;
13115 24509845 : if (op1 == const0_rtx)
13116 11671573 : op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13117 :
13118 24509845 : op0 = make_compound_operation (op0, op0_mco_code);
13119 24509845 : op1 = make_compound_operation (op1, SET);
13120 :
13121 608144 : if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13122 576340 : && is_int_mode (GET_MODE (op0), &mode)
13123 544991 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13124 25051077 : && (code == NE || code == EQ))
13125 : {
13126 285011 : if (paradoxical_subreg_p (op0))
13127 : {
13128 : /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13129 : implemented. */
13130 0 : if (REG_P (SUBREG_REG (op0)))
13131 : {
13132 0 : op0 = SUBREG_REG (op0);
13133 0 : op1 = gen_lowpart (inner_mode, op1);
13134 : }
13135 : }
13136 285011 : else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13137 285011 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13138 278038 : & ~GET_MODE_MASK (mode)) == 0)
13139 : {
13140 14126 : tem = gen_lowpart (inner_mode, op1);
13141 :
13142 14126 : if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13143 4809 : op0 = SUBREG_REG (op0), op1 = tem;
13144 : }
13145 : }
13146 :
13147 : /* We now do the opposite procedure: Some machines don't have compare
13148 : insns in all modes. If OP0's mode is an integer mode smaller than a
13149 : word and we can't do a compare in that mode, see if there is a larger
13150 : mode for which we can do the compare. There are a number of cases in
13151 : which we can use the wider mode. */
13152 :
13153 24509845 : if (is_int_mode (GET_MODE (op0), &mode)
13154 25187602 : && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13155 8988635 : && ! have_insn_for (COMPARE, mode))
13156 0 : FOR_EACH_WIDER_MODE (tmode_iter, mode)
13157 : {
13158 0 : tmode = tmode_iter.require ();
13159 0 : if (!HWI_COMPUTABLE_MODE_P (tmode))
13160 : break;
13161 0 : if (have_insn_for (COMPARE, tmode))
13162 : {
13163 0 : int zero_extended;
13164 :
13165 : /* If this is a test for negative, we can make an explicit
13166 : test of the sign bit. Test this first so we can use
13167 : a paradoxical subreg to extend OP0. */
13168 :
13169 0 : if (op1 == const0_rtx && (code == LT || code == GE)
13170 0 : && HWI_COMPUTABLE_MODE_P (mode))
13171 : {
13172 0 : unsigned HOST_WIDE_INT sign
13173 0 : = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13174 0 : op0 = simplify_gen_binary (AND, tmode,
13175 0 : gen_lowpart (tmode, op0),
13176 0 : gen_int_mode (sign, tmode));
13177 0 : code = (code == LT) ? NE : EQ;
13178 : break;
13179 : }
13180 :
13181 : /* If the only nonzero bits in OP0 and OP1 are those in the
13182 : narrower mode and this is an equality or unsigned comparison,
13183 : we can use the wider mode. Similarly for sign-extended
13184 : values, in which case it is true for all comparisons. */
13185 0 : zero_extended = ((code == EQ || code == NE
13186 0 : || code == GEU || code == GTU
13187 0 : || code == LEU || code == LTU)
13188 0 : && (nonzero_bits (op0, tmode)
13189 0 : & ~GET_MODE_MASK (mode)) == 0
13190 0 : && ((CONST_INT_P (op1)
13191 0 : || (nonzero_bits (op1, tmode)
13192 0 : & ~GET_MODE_MASK (mode)) == 0)));
13193 :
13194 0 : if (zero_extended
13195 0 : || ((num_sign_bit_copies (op0, tmode)
13196 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13197 0 : - GET_MODE_PRECISION (mode)))
13198 0 : && (num_sign_bit_copies (op1, tmode)
13199 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13200 0 : - GET_MODE_PRECISION (mode)))))
13201 : {
13202 : /* If OP0 is an AND and we don't have an AND in MODE either,
13203 : make a new AND in the proper mode. */
13204 0 : if (GET_CODE (op0) == AND
13205 0 : && !have_insn_for (AND, mode))
13206 0 : op0 = simplify_gen_binary (AND, tmode,
13207 0 : gen_lowpart (tmode,
13208 : XEXP (op0, 0)),
13209 0 : gen_lowpart (tmode,
13210 : XEXP (op0, 1)));
13211 : else
13212 : {
13213 0 : if (zero_extended)
13214 : {
13215 0 : op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13216 : op0, mode);
13217 0 : op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13218 : op1, mode);
13219 : }
13220 : else
13221 : {
13222 0 : op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13223 : op0, mode);
13224 0 : op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13225 : op1, mode);
13226 : }
13227 : break;
13228 : }
13229 : }
13230 : }
13231 : }
13232 :
13233 : /* We may have changed the comparison operands. Re-canonicalize. */
13234 24509845 : if (swap_commutative_operands_p (op0, op1))
13235 : {
13236 63398 : std::swap (op0, op1);
13237 63398 : code = swap_condition (code);
13238 : }
13239 :
13240 : /* If this machine only supports a subset of valid comparisons, see if we
13241 : can convert an unsupported one into a supported one. */
13242 24509845 : target_canonicalize_comparison (&code, &op0, &op1, 0);
13243 :
13244 24509845 : *pop0 = op0;
13245 24509845 : *pop1 = op1;
13246 :
13247 24509845 : return code;
13248 : }
13249 :
13250 : /* Utility function for record_value_for_reg. Count number of
13251 : rtxs in X. */
13252 : static int
13253 2667 : count_rtxs (rtx x)
13254 : {
13255 2667 : enum rtx_code code = GET_CODE (x);
13256 2667 : const char *fmt;
13257 2667 : int i, j, ret = 1;
13258 :
13259 2667 : if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13260 2667 : || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13261 : {
13262 83 : rtx x0 = XEXP (x, 0);
13263 83 : rtx x1 = XEXP (x, 1);
13264 :
13265 83 : if (x0 == x1)
13266 0 : return 1 + 2 * count_rtxs (x0);
13267 :
13268 83 : if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13269 83 : || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13270 0 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13271 0 : return 2 + 2 * count_rtxs (x0)
13272 0 : + count_rtxs (x == XEXP (x1, 0)
13273 0 : ? XEXP (x1, 1) : XEXP (x1, 0));
13274 :
13275 83 : if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13276 83 : || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13277 0 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13278 0 : return 2 + 2 * count_rtxs (x1)
13279 0 : + count_rtxs (x == XEXP (x0, 0)
13280 0 : ? XEXP (x0, 1) : XEXP (x0, 0));
13281 : }
13282 :
13283 2667 : fmt = GET_RTX_FORMAT (code);
13284 5984 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13285 3317 : if (fmt[i] == 'e')
13286 1571 : ret += count_rtxs (XEXP (x, i));
13287 1746 : else if (fmt[i] == 'E')
13288 208 : for (j = 0; j < XVECLEN (x, i); j++)
13289 156 : ret += count_rtxs (XVECEXP (x, i, j));
13290 :
13291 : return ret;
13292 : }
13293 :
13294 : /* Utility function for following routine. Called when X is part of a value
13295 : being stored into last_set_value. Sets last_set_table_tick
13296 : for each register mentioned. Similar to mention_regs in cse.cc */
13297 :
13298 : static void
13299 233437780 : update_table_tick (rtx x)
13300 : {
13301 234129878 : enum rtx_code code = GET_CODE (x);
13302 234129878 : const char *fmt = GET_RTX_FORMAT (code);
13303 234129878 : int i, j;
13304 :
13305 234129878 : if (code == REG)
13306 : {
13307 83425276 : unsigned int regno = REGNO (x);
13308 83425276 : unsigned int endregno = END_REGNO (x);
13309 83425276 : unsigned int r;
13310 :
13311 166961384 : for (r = regno; r < endregno; r++)
13312 : {
13313 83536108 : reg_stat_type *rsp = ®_stat[r];
13314 83536108 : rsp->last_set_table_tick = label_tick;
13315 : }
13316 :
13317 : return;
13318 : }
13319 :
13320 389401782 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13321 239516051 : if (fmt[i] == 'e')
13322 : {
13323 : /* Check for identical subexpressions. If x contains
13324 : identical subexpression we only have to traverse one of
13325 : them. */
13326 138830998 : if (i == 0 && ARITHMETIC_P (x))
13327 : {
13328 : /* Note that at this point x1 has already been
13329 : processed. */
13330 52492728 : rtx x0 = XEXP (x, 0);
13331 52492728 : rtx x1 = XEXP (x, 1);
13332 :
13333 : /* If x0 and x1 are identical then there is no need to
13334 : process x0. */
13335 52492728 : if (x0 == x1)
13336 : break;
13337 :
13338 : /* If x0 is identical to a subexpression of x1 then while
13339 : processing x1, x0 has already been processed. Thus we
13340 : are done with x. */
13341 52366094 : if (ARITHMETIC_P (x1)
13342 232803 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13343 : break;
13344 :
13345 : /* If x1 is identical to a subexpression of x0 then we
13346 : still have to process the rest of x0. */
13347 52365955 : if (ARITHMETIC_P (x0)
13348 9433514 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13349 : {
13350 692098 : update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13351 692098 : break;
13352 : }
13353 : }
13354 :
13355 138012127 : update_table_tick (XEXP (x, i));
13356 : }
13357 100685053 : else if (fmt[i] == 'E')
13358 10433363 : for (j = 0; j < XVECLEN (x, i); j++)
13359 7667042 : update_table_tick (XVECEXP (x, i, j));
13360 : }
13361 :
13362 : /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13363 : are saying that the register is clobbered and we no longer know its
13364 : value. If INSN is zero, don't update reg_stat[].last_set; this is
13365 : only permitted with VALUE also zero and is used to invalidate the
13366 : register. */
13367 :
13368 : static void
13369 114788415 : record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13370 : {
13371 114788415 : unsigned int regno = REGNO (reg);
13372 114788415 : unsigned int endregno = END_REGNO (reg);
13373 114788415 : unsigned int i;
13374 114788415 : reg_stat_type *rsp;
13375 :
13376 : /* If VALUE contains REG and we have a previous value for REG, substitute
13377 : the previous value. */
13378 114788415 : if (value && insn && reg_overlap_mentioned_p (reg, value))
13379 : {
13380 6270846 : rtx tem;
13381 :
13382 : /* Set things up so get_last_value is allowed to see anything set up to
13383 : our insn. */
13384 6270846 : subst_low_luid = DF_INSN_LUID (insn);
13385 6270846 : tem = get_last_value (reg);
13386 :
13387 : /* If TEM is simply a binary operation with two CLOBBERs as operands,
13388 : it isn't going to be useful and will take a lot of time to process,
13389 : so just use the CLOBBER. */
13390 :
13391 6270846 : if (tem)
13392 : {
13393 2482130 : if (ARITHMETIC_P (tem)
13394 2249738 : && GET_CODE (XEXP (tem, 0)) == CLOBBER
13395 1101423 : && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13396 : tem = XEXP (tem, 0);
13397 2480802 : else if (count_occurrences (value, reg, 1) >= 2)
13398 : {
13399 : /* If there are two or more occurrences of REG in VALUE,
13400 : prevent the value from growing too much. */
13401 940 : if (count_rtxs (tem) > param_max_last_value_rtl)
13402 0 : tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13403 : }
13404 :
13405 2482130 : value = replace_rtx (copy_rtx (value), reg, tem);
13406 : }
13407 : }
13408 :
13409 : /* For each register modified, show we don't know its value, that
13410 : we don't know about its bitwise content, that its value has been
13411 : updated, and that we don't know the location of the death of the
13412 : register. */
13413 229932193 : for (i = regno; i < endregno; i++)
13414 : {
13415 115143778 : rsp = ®_stat[i];
13416 :
13417 115143778 : if (insn)
13418 105767306 : rsp->last_set = insn;
13419 :
13420 115143778 : rsp->last_set_value = 0;
13421 115143778 : rsp->last_set_mode = VOIDmode;
13422 115143778 : rsp->last_set_nonzero_bits = 0;
13423 115143778 : rsp->last_set_sign_bit_copies = 0;
13424 115143778 : rsp->last_death = 0;
13425 115143778 : rsp->truncated_to_mode = VOIDmode;
13426 : }
13427 :
13428 : /* Mark registers that are being referenced in this value. */
13429 114788415 : if (value)
13430 87758611 : update_table_tick (value);
13431 :
13432 : /* Now update the status of each register being set.
13433 : If someone is using this register in this block, set this register
13434 : to invalid since we will get confused between the two lives in this
13435 : basic block. This makes using this register always invalid. In cse, we
13436 : scan the table to invalidate all entries using this register, but this
13437 : is too much work for us. */
13438 :
13439 229932193 : for (i = regno; i < endregno; i++)
13440 : {
13441 115143778 : rsp = ®_stat[i];
13442 115143778 : rsp->last_set_label = label_tick;
13443 115143778 : if (!insn
13444 105767306 : || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13445 20023108 : rsp->last_set_invalid = true;
13446 : else
13447 95120670 : rsp->last_set_invalid = false;
13448 : }
13449 :
13450 : /* The value being assigned might refer to X (like in "x++;"). In that
13451 : case, we must replace it with (clobber (const_int 0)) to prevent
13452 : infinite loops. */
13453 114788415 : rsp = ®_stat[regno];
13454 114788415 : if (value && !get_last_value_validate (&value, insn, label_tick, false))
13455 : {
13456 11277248 : value = copy_rtx (value);
13457 11277248 : if (!get_last_value_validate (&value, insn, label_tick, true))
13458 0 : value = 0;
13459 : }
13460 :
13461 : /* For the main register being modified, update the value, the mode, the
13462 : nonzero bits, and the number of sign bit copies. */
13463 :
13464 114788415 : rsp->last_set_value = value;
13465 :
13466 114788415 : if (value)
13467 : {
13468 87758611 : machine_mode mode = GET_MODE (reg);
13469 87758611 : subst_low_luid = DF_INSN_LUID (insn);
13470 87758611 : rsp->last_set_mode = mode;
13471 87758611 : if (GET_MODE_CLASS (mode) == MODE_INT
13472 87758611 : && HWI_COMPUTABLE_MODE_P (mode))
13473 66077035 : mode = nonzero_bits_mode;
13474 87758611 : rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13475 87758611 : rsp->last_set_sign_bit_copies
13476 87758611 : = num_sign_bit_copies (value, GET_MODE (reg));
13477 : }
13478 114788415 : }
13479 :
13480 : /* Called via note_stores from record_dead_and_set_regs to handle one
13481 : SET or CLOBBER in an insn. DATA is the instruction in which the
13482 : set is occurring. */
13483 :
13484 : static void
13485 137303642 : record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13486 : {
13487 137303642 : rtx_insn *record_dead_insn = (rtx_insn *) data;
13488 :
13489 137303642 : if (GET_CODE (dest) == SUBREG)
13490 5 : dest = SUBREG_REG (dest);
13491 :
13492 137303642 : if (!record_dead_insn)
13493 : {
13494 4257120 : if (REG_P (dest))
13495 4257120 : record_value_for_reg (dest, NULL, NULL_RTX);
13496 : return;
13497 : }
13498 :
13499 133046522 : if (REG_P (dest))
13500 : {
13501 : /* If we are setting the whole register, we know its value. */
13502 105593344 : if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13503 87576405 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13504 : /* We can handle a SUBREG if it's the low part, but we must be
13505 : careful with paradoxical SUBREGs on RISC architectures because
13506 : we cannot strip e.g. an extension around a load and record the
13507 : naked load since the RTL middle-end considers that the upper bits
13508 : are defined according to LOAD_EXTEND_OP. */
13509 18016939 : else if (GET_CODE (setter) == SET
13510 629640 : && GET_CODE (SET_DEST (setter)) == SUBREG
13511 617312 : && SUBREG_REG (SET_DEST (setter)) == dest
13512 983545 : && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13513 : BITS_PER_WORD)
13514 18151214 : && subreg_lowpart_p (SET_DEST (setter)))
13515 : {
13516 134275 : if (WORD_REGISTER_OPERATIONS
13517 : && word_register_operation_p (SET_SRC (setter))
13518 : && paradoxical_subreg_p (SET_DEST (setter)))
13519 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13520 134275 : else if (!partial_subreg_p (SET_DEST (setter)))
13521 122163 : record_value_for_reg (dest, record_dead_insn,
13522 122163 : gen_lowpart (GET_MODE (dest),
13523 122163 : SET_SRC (setter)));
13524 : else
13525 : {
13526 12112 : record_value_for_reg (dest, record_dead_insn,
13527 12112 : gen_lowpart (GET_MODE (dest),
13528 12112 : SET_SRC (setter)));
13529 :
13530 12112 : unsigned HOST_WIDE_INT mask;
13531 12112 : reg_stat_type *rsp = ®_stat[REGNO (dest)];
13532 12112 : mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13533 12112 : rsp->last_set_nonzero_bits |= ~mask;
13534 12112 : rsp->last_set_sign_bit_copies = 1;
13535 : }
13536 : }
13537 : /* Otherwise show that we don't know the value. */
13538 : else
13539 17882664 : record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13540 : }
13541 27453178 : else if (MEM_P (dest)
13542 : /* Ignore pushes, they clobber nothing. */
13543 27453178 : && ! push_operand (dest, GET_MODE (dest)))
13544 14128728 : mem_last_set = DF_INSN_LUID (record_dead_insn);
13545 : }
13546 :
13547 : /* Update the records of when each REG was most recently set or killed
13548 : for the things done by INSN. This is the last thing done in processing
13549 : INSN in the combiner loop.
13550 :
13551 : We update reg_stat[], in particular fields last_set, last_set_value,
13552 : last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13553 : last_death, and also the similar information mem_last_set (which insn
13554 : most recently modified memory) and last_call_luid (which insn was the
13555 : most recent subroutine call). */
13556 :
13557 : static void
13558 179341224 : record_dead_and_set_regs (rtx_insn *insn)
13559 : {
13560 179341224 : rtx link;
13561 179341224 : unsigned int i;
13562 :
13563 318221014 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13564 : {
13565 138879790 : if (REG_NOTE_KIND (link) == REG_DEAD
13566 79364127 : && REG_P (XEXP (link, 0)))
13567 : {
13568 79364127 : unsigned int regno = REGNO (XEXP (link, 0));
13569 79364127 : unsigned int endregno = END_REGNO (XEXP (link, 0));
13570 :
13571 158932959 : for (i = regno; i < endregno; i++)
13572 : {
13573 79568832 : reg_stat_type *rsp;
13574 :
13575 79568832 : rsp = ®_stat[i];
13576 79568832 : rsp->last_death = insn;
13577 : }
13578 : }
13579 59515663 : else if (REG_NOTE_KIND (link) == REG_INC)
13580 0 : record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13581 : }
13582 :
13583 179341224 : if (CALL_P (insn))
13584 : {
13585 9546007 : HARD_REG_SET callee_clobbers
13586 9546007 : = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13587 9546007 : hard_reg_set_iterator hrsi;
13588 808036692 : EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13589 : {
13590 798490685 : reg_stat_type *rsp;
13591 :
13592 : /* ??? We could try to preserve some information from the last
13593 : set of register I if the call doesn't actually clobber
13594 : (reg:last_set_mode I), which might be true for ABIs with
13595 : partial clobbers. However, it would be difficult to
13596 : update last_set_nonzero_bits and last_sign_bit_copies
13597 : to account for the part of I that actually was clobbered.
13598 : It wouldn't help much anyway, since we rarely see this
13599 : situation before RA. */
13600 798490685 : rsp = ®_stat[i];
13601 798490685 : rsp->last_set_invalid = true;
13602 798490685 : rsp->last_set = insn;
13603 798490685 : rsp->last_set_value = 0;
13604 798490685 : rsp->last_set_mode = VOIDmode;
13605 798490685 : rsp->last_set_nonzero_bits = 0;
13606 798490685 : rsp->last_set_sign_bit_copies = 0;
13607 798490685 : rsp->last_death = 0;
13608 798490685 : rsp->truncated_to_mode = VOIDmode;
13609 : }
13610 :
13611 9546007 : last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13612 :
13613 : /* We can't combine into a call pattern. Remember, though, that
13614 : the return value register is set at this LUID. We could
13615 : still replace a register with the return value from the
13616 : wrong subroutine call! */
13617 9546007 : note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13618 : }
13619 : else
13620 169795217 : note_stores (insn, record_dead_and_set_regs_1, insn);
13621 179341224 : }
13622 :
13623 : /* If a SUBREG has the promoted bit set, it is in fact a property of the
13624 : register present in the SUBREG, so for each such SUBREG go back and
13625 : adjust nonzero and sign bit information of the registers that are
13626 : known to have some zero/sign bits set.
13627 :
13628 : This is needed because when combine blows the SUBREGs away, the
13629 : information on zero/sign bits is lost and further combines can be
13630 : missed because of that. */
13631 :
13632 : static void
13633 6693 : record_promoted_value (rtx_insn *insn, rtx subreg)
13634 : {
13635 6693 : struct insn_link *links;
13636 6693 : rtx set;
13637 6693 : unsigned int regno = REGNO (SUBREG_REG (subreg));
13638 6693 : machine_mode mode = GET_MODE (subreg);
13639 :
13640 6693 : if (!HWI_COMPUTABLE_MODE_P (mode))
13641 : return;
13642 :
13643 7485 : for (links = LOG_LINKS (insn); links;)
13644 : {
13645 6368 : reg_stat_type *rsp;
13646 :
13647 6368 : insn = links->insn;
13648 6368 : set = single_set (insn);
13649 :
13650 6368 : if (! set || !REG_P (SET_DEST (set))
13651 6364 : || REGNO (SET_DEST (set)) != regno
13652 12086 : || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13653 : {
13654 650 : links = links->next;
13655 650 : continue;
13656 : }
13657 :
13658 5718 : rsp = ®_stat[regno];
13659 5718 : if (rsp->last_set == insn)
13660 : {
13661 5718 : if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13662 5718 : rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13663 : }
13664 :
13665 5718 : if (REG_P (SET_SRC (set)))
13666 : {
13667 142 : regno = REGNO (SET_SRC (set));
13668 142 : links = LOG_LINKS (insn);
13669 : }
13670 : else
13671 : break;
13672 : }
13673 : }
13674 :
13675 : /* Check if X, a register, is known to contain a value already
13676 : truncated to MODE. In this case we can use a subreg to refer to
13677 : the truncated value even though in the generic case we would need
13678 : an explicit truncation. */
13679 :
13680 : static bool
13681 0 : reg_truncated_to_mode (machine_mode mode, const_rtx x)
13682 : {
13683 0 : reg_stat_type *rsp = ®_stat[REGNO (x)];
13684 0 : machine_mode truncated = rsp->truncated_to_mode;
13685 :
13686 0 : if (truncated == 0
13687 0 : || rsp->truncation_label < label_tick_ebb_start)
13688 : return false;
13689 0 : if (!partial_subreg_p (mode, truncated))
13690 : return true;
13691 0 : if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13692 : return true;
13693 : return false;
13694 : }
13695 :
13696 : /* If X is a hard reg or a subreg record the mode that the register is
13697 : accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13698 : able to turn a truncate into a subreg using this information. Return true
13699 : if traversing X is complete. */
13700 :
13701 : static bool
13702 201436215 : record_truncated_value (rtx x)
13703 : {
13704 201436215 : machine_mode truncated_mode;
13705 201436215 : reg_stat_type *rsp;
13706 :
13707 201436215 : if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13708 : {
13709 1875703 : machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13710 1875703 : truncated_mode = GET_MODE (x);
13711 :
13712 1875703 : if (!partial_subreg_p (truncated_mode, original_mode))
13713 : return true;
13714 :
13715 1111130 : truncated_mode = GET_MODE (x);
13716 1111130 : if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13717 : return true;
13718 :
13719 0 : x = SUBREG_REG (x);
13720 0 : }
13721 : /* ??? For hard-regs we now record everything. We might be able to
13722 : optimize this using last_set_mode. */
13723 199560512 : else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13724 21227272 : truncated_mode = GET_MODE (x);
13725 : else
13726 : return false;
13727 :
13728 21227272 : rsp = ®_stat[REGNO (x)];
13729 21227272 : if (rsp->truncated_to_mode == 0
13730 9863971 : || rsp->truncation_label < label_tick_ebb_start
13731 29816979 : || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13732 : {
13733 12638203 : rsp->truncated_to_mode = truncated_mode;
13734 12638203 : rsp->truncation_label = label_tick;
13735 : }
13736 :
13737 : return true;
13738 : }
13739 :
13740 : /* Callback for note_uses. Find hardregs and subregs of pseudos and
13741 : the modes they are used in. This can help turning TRUNCATEs into
13742 : SUBREGs. */
13743 :
13744 : static void
13745 77136941 : record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13746 : {
13747 77136941 : subrtx_var_iterator::array_type array;
13748 278573156 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13749 201436215 : if (record_truncated_value (*iter))
13750 23102975 : iter.skip_subrtxes ();
13751 77136941 : }
13752 :
13753 : /* Scan X for promoted SUBREGs. For each one found,
13754 : note what it implies to the registers used in it. */
13755 :
13756 : static void
13757 366865857 : check_promoted_subreg (rtx_insn *insn, rtx x)
13758 : {
13759 366865857 : if (GET_CODE (x) == SUBREG
13760 2266805 : && SUBREG_PROMOTED_VAR_P (x)
13761 366872550 : && REG_P (SUBREG_REG (x)))
13762 6693 : record_promoted_value (insn, x);
13763 : else
13764 : {
13765 366859164 : const char *format = GET_RTX_FORMAT (GET_CODE (x));
13766 366859164 : int i, j;
13767 :
13768 882875082 : for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13769 516015918 : switch (format[i])
13770 : {
13771 274340792 : case 'e':
13772 274340792 : check_promoted_subreg (insn, XEXP (x, i));
13773 274340792 : break;
13774 11951348 : case 'V':
13775 11951348 : case 'E':
13776 11951348 : if (XVEC (x, i) != 0)
13777 37136461 : for (j = 0; j < XVECLEN (x, i); j++)
13778 25185113 : check_promoted_subreg (insn, XVECEXP (x, i, j));
13779 : break;
13780 : }
13781 : }
13782 366865857 : }
13783 :
13784 : /* Verify that all the registers and memory references mentioned in *LOC are
13785 : still valid. *LOC was part of a value set in INSN when label_tick was
13786 : equal to TICK. Return false if some are not. If REPLACE is true, replace
13787 : the invalid references with (clobber (const_int 0)) and return true. This
13788 : replacement is useful because we often can get useful information about
13789 : the form of a value (e.g., if it was produced by a shift that always
13790 : produces -1 or 0) even though we don't know exactly what registers it
13791 : was produced from. */
13792 :
13793 : static bool
13794 479633207 : get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13795 : {
13796 479633684 : rtx x = *loc;
13797 479633684 : const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13798 479633684 : int len = GET_RTX_LENGTH (GET_CODE (x));
13799 479633684 : int i, j;
13800 :
13801 479633684 : if (REG_P (x))
13802 : {
13803 161150505 : unsigned int regno = REGNO (x);
13804 161150505 : unsigned int endregno = END_REGNO (x);
13805 161150505 : unsigned int j;
13806 :
13807 298557943 : for (j = regno; j < endregno; j++)
13808 : {
13809 161175758 : reg_stat_type *rsp = ®_stat[j];
13810 161175758 : if (rsp->last_set_invalid
13811 : /* If this is a pseudo-register that was only set once and not
13812 : live at the beginning of the function, it is always valid. */
13813 267705135 : || (! (regno >= FIRST_PSEUDO_REGISTER
13814 122660107 : && regno < reg_n_sets_max
13815 122638400 : && REG_N_SETS (regno) == 1
13816 213058754 : && (!REGNO_REG_SET_P
13817 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13818 : regno)))
13819 31104553 : && rsp->last_set_label > tick))
13820 : {
13821 23768320 : if (replace)
13822 12010047 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13823 : return replace;
13824 : }
13825 : }
13826 :
13827 : return true;
13828 : }
13829 : /* If this is a memory reference, make sure that there were no stores after
13830 : it that might have clobbered the value. We don't have alias info, so we
13831 : assume any store invalidates it. Moreover, we only have local UIDs, so
13832 : we also assume that there were stores in the intervening basic blocks. */
13833 35376462 : else if (MEM_P (x) && !MEM_READONLY_P (x)
13834 351735685 : && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13835 : {
13836 7951531 : if (replace)
13837 3979395 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13838 : return replace;
13839 : }
13840 :
13841 775198191 : for (i = 0; i < len; i++)
13842 : {
13843 476735383 : if (fmt[i] == 'e')
13844 : {
13845 : /* Check for identical subexpressions. If x contains
13846 : identical subexpression we only have to traverse one of
13847 : them. */
13848 291440899 : if (i == 1 && ARITHMETIC_P (x))
13849 : {
13850 : /* Note that at this point x0 has already been checked
13851 : and found valid. */
13852 104544630 : rtx x0 = XEXP (x, 0);
13853 104544630 : rtx x1 = XEXP (x, 1);
13854 :
13855 : /* If x0 and x1 are identical then x is also valid. */
13856 104544630 : if (x0 == x1)
13857 : return true;
13858 :
13859 : /* If x1 is identical to a subexpression of x0 then
13860 : while checking x0, x1 has already been checked. Thus
13861 : it is valid and so as x. */
13862 104143968 : if (ARITHMETIC_P (x0)
13863 19624965 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13864 : return true;
13865 :
13866 : /* If x0 is identical to a subexpression of x1 then x is
13867 : valid iff the rest of x1 is valid. */
13868 102080588 : if (ARITHMETIC_P (x1)
13869 367519 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13870 477 : return
13871 477 : get_last_value_validate (&XEXP (x1,
13872 : x0 == XEXP (x1, 0) ? 1 : 0),
13873 477 : insn, tick, replace);
13874 : }
13875 :
13876 288976380 : if (!get_last_value_validate (&XEXP (x, i), insn, tick, replace))
13877 : return false;
13878 : }
13879 185294484 : else if (fmt[i] == 'E')
13880 33577863 : for (j = 0; j < XVECLEN (x, i); j++)
13881 26528471 : if (!get_last_value_validate (&XVECEXP (x, i, j),
13882 : insn, tick, replace))
13883 : return false;
13884 : }
13885 :
13886 : /* If we haven't found a reason for it to be invalid, it is valid. */
13887 : return true;
13888 : }
13889 :
13890 : /* Get the last value assigned to X, if known. Some registers
13891 : in the value may be replaced with (clobber (const_int 0)) if their value
13892 : is known longer known reliably. */
13893 :
13894 : static rtx
13895 235631897 : get_last_value (const_rtx x)
13896 : {
13897 235631897 : unsigned int regno;
13898 235631897 : rtx value;
13899 235631897 : reg_stat_type *rsp;
13900 :
13901 : /* If this is a non-paradoxical SUBREG, get the value of its operand and
13902 : then convert it to the desired mode. If this is a paradoxical SUBREG,
13903 : we cannot predict what values the "extra" bits might have. */
13904 235631897 : if (GET_CODE (x) == SUBREG
13905 14092793 : && subreg_lowpart_p (x)
13906 13583634 : && !paradoxical_subreg_p (x)
13907 244303109 : && (value = get_last_value (SUBREG_REG (x))) != 0)
13908 4417640 : return gen_lowpart (GET_MODE (x), value);
13909 :
13910 231214257 : if (!REG_P (x))
13911 : return 0;
13912 :
13913 200159324 : regno = REGNO (x);
13914 200159324 : rsp = ®_stat[regno];
13915 200159324 : value = rsp->last_set_value;
13916 :
13917 : /* If we don't have a value, or if it isn't for this basic block and
13918 : it's either a hard register, set more than once, or it's a live
13919 : at the beginning of the function, return 0.
13920 :
13921 : Because if it's not live at the beginning of the function then the reg
13922 : is always set before being used (is never used without being set).
13923 : And, if it's set only once, and it's always set before use, then all
13924 : uses must have the same last value, even if it's not from this basic
13925 : block. */
13926 :
13927 200159324 : if (value == 0
13928 200159324 : || (rsp->last_set_label < label_tick_ebb_start
13929 75595803 : && (regno < FIRST_PSEUDO_REGISTER
13930 74736577 : || regno >= reg_n_sets_max
13931 74736577 : || REG_N_SETS (regno) != 1
13932 16577826 : || REGNO_REG_SET_P
13933 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13934 : return 0;
13935 :
13936 : /* If the value was set in a later insn than the ones we are processing,
13937 : we can't use it even if the register was only set once. */
13938 81129184 : if (rsp->last_set_label == label_tick
13939 81129184 : && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13940 : return 0;
13941 :
13942 : /* If fewer bits were set than what we are asked for now, we cannot use
13943 : the value. */
13944 60640758 : if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13945 60640758 : GET_MODE_PRECISION (GET_MODE (x))))
13946 : return 0;
13947 :
13948 : /* If the value has all its registers valid, return it. */
13949 60639336 : if (get_last_value_validate (&value, rsp->last_set,
13950 : rsp->last_set_label, false))
13951 56186175 : return value;
13952 :
13953 : /* Otherwise, make a copy and replace any invalid register with
13954 : (clobber (const_int 0)). If that fails for some reason, return 0. */
13955 :
13956 4453161 : value = copy_rtx (value);
13957 4453161 : if (get_last_value_validate (&value, rsp->last_set,
13958 : rsp->last_set_label, true))
13959 4453161 : return value;
13960 :
13961 : return 0;
13962 : }
13963 :
13964 : /* Define three variables used for communication between the following
13965 : routines. */
13966 :
13967 : static unsigned int reg_dead_regno, reg_dead_endregno;
13968 : static int reg_dead_flag;
13969 : rtx reg_dead_reg;
13970 :
13971 : /* Function called via note_stores from reg_dead_at_p.
13972 :
13973 : If DEST is within [reg_dead_regno, reg_dead_endregno), set
13974 : reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13975 :
13976 : static void
13977 644737 : reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13978 : {
13979 644737 : unsigned int regno, endregno;
13980 :
13981 644737 : if (!REG_P (dest))
13982 : return;
13983 :
13984 592770 : regno = REGNO (dest);
13985 592770 : endregno = END_REGNO (dest);
13986 592770 : if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13987 291306 : reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13988 : }
13989 :
13990 : /* Return true if REG is known to be dead at INSN.
13991 :
13992 : We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13993 : referencing REG, it is dead. If we hit a SET referencing REG, it is
13994 : live. Otherwise, see if it is live or dead at the start of the basic
13995 : block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13996 : must be assumed to be always live. */
13997 :
13998 : static bool
13999 1633115 : reg_dead_at_p (rtx reg, rtx_insn *insn)
14000 : {
14001 1633115 : basic_block block;
14002 1633115 : unsigned int i;
14003 :
14004 : /* Set variables for reg_dead_at_p_1. */
14005 1633115 : reg_dead_regno = REGNO (reg);
14006 1633115 : reg_dead_endregno = END_REGNO (reg);
14007 1633115 : reg_dead_reg = reg;
14008 :
14009 1633115 : reg_dead_flag = 0;
14010 :
14011 : /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
14012 : we allow the machine description to decide whether use-and-clobber
14013 : patterns are OK. */
14014 1633115 : if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
14015 : {
14016 3266230 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14017 1633115 : if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
14018 : return false;
14019 : }
14020 :
14021 : /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
14022 : beginning of basic block. */
14023 1633115 : block = BLOCK_FOR_INSN (insn);
14024 792817 : for (;;)
14025 : {
14026 2425932 : if (INSN_P (insn))
14027 : {
14028 2274229 : if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
14029 : return true;
14030 :
14031 846327 : note_stores (insn, reg_dead_at_p_1, NULL);
14032 846327 : if (reg_dead_flag)
14033 145653 : return reg_dead_flag == 1 ? 1 : 0;
14034 :
14035 700674 : if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
14036 : return true;
14037 : }
14038 :
14039 822742 : if (insn == BB_HEAD (block))
14040 : break;
14041 :
14042 792817 : insn = PREV_INSN (insn);
14043 : }
14044 :
14045 : /* Look at live-in sets for the basic block that we were in. */
14046 59850 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14047 29925 : if (REGNO_REG_SET_P (df_get_live_in (block), i))
14048 : return false;
14049 :
14050 : return true;
14051 : }
14052 :
14053 : /* Note hard registers in X that are used. */
14054 :
14055 : static void
14056 293777055 : mark_used_regs_combine (rtx x)
14057 : {
14058 339425979 : RTX_CODE code = GET_CODE (x);
14059 339425979 : unsigned int regno;
14060 339425979 : int i;
14061 :
14062 339425979 : switch (code)
14063 : {
14064 : case LABEL_REF:
14065 : case SYMBOL_REF:
14066 : case CONST:
14067 : CASE_CONST_ANY:
14068 : case PC:
14069 : case ADDR_VEC:
14070 : case ADDR_DIFF_VEC:
14071 : case ASM_INPUT:
14072 : return;
14073 :
14074 7462734 : case CLOBBER:
14075 : /* If we are clobbering a MEM, mark any hard registers inside the
14076 : address as used. */
14077 7462734 : if (MEM_P (XEXP (x, 0)))
14078 5485 : mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
14079 : return;
14080 :
14081 77223869 : case REG:
14082 77223869 : regno = REGNO (x);
14083 : /* A hard reg in a wide mode may really be multiple registers.
14084 : If so, mark all of them just like the first. */
14085 77223869 : if (regno < FIRST_PSEUDO_REGISTER)
14086 : {
14087 : /* None of this applies to the stack, frame or arg pointers. */
14088 9239230 : if (regno == STACK_POINTER_REGNUM
14089 9239230 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14090 : && regno == HARD_FRAME_POINTER_REGNUM)
14091 8302573 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14092 1109148 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14093 7193425 : || regno == FRAME_POINTER_REGNUM)
14094 : return;
14095 :
14096 1797058 : add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
14097 : }
14098 : return;
14099 :
14100 45643439 : case SET:
14101 45643439 : {
14102 : /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14103 : the address. */
14104 45643439 : rtx testreg = SET_DEST (x);
14105 :
14106 45643439 : while (GET_CODE (testreg) == SUBREG
14107 45658334 : || GET_CODE (testreg) == ZERO_EXTRACT
14108 91633350 : || GET_CODE (testreg) == STRICT_LOW_PART)
14109 338843 : testreg = XEXP (testreg, 0);
14110 :
14111 45643439 : if (MEM_P (testreg))
14112 4852925 : mark_used_regs_combine (XEXP (testreg, 0));
14113 :
14114 45643439 : mark_used_regs_combine (SET_SRC (x));
14115 : }
14116 45643439 : return;
14117 :
14118 135653128 : default:
14119 135653128 : break;
14120 : }
14121 :
14122 : /* Recursively scan the operands of this expression. */
14123 :
14124 135653128 : {
14125 135653128 : const char *fmt = GET_RTX_FORMAT (code);
14126 :
14127 393502600 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14128 : {
14129 257849472 : if (fmt[i] == 'e')
14130 208930673 : mark_used_regs_combine (XEXP (x, i));
14131 48918799 : else if (fmt[i] == 'E')
14132 : {
14133 : int j;
14134 :
14135 67180157 : for (j = 0; j < XVECLEN (x, i); j++)
14136 46592631 : mark_used_regs_combine (XVECEXP (x, i, j));
14137 : }
14138 : }
14139 : }
14140 : }
14141 :
14142 : /* Remove register number REGNO from the dead registers list of INSN.
14143 :
14144 : Return the note used to record the death, if there was one. */
14145 :
14146 : rtx
14147 3185337 : remove_death (unsigned int regno, rtx_insn *insn)
14148 : {
14149 3185337 : rtx note = find_regno_note (insn, REG_DEAD, regno);
14150 :
14151 3185337 : if (note)
14152 519036 : remove_note (insn, note);
14153 :
14154 3185337 : return note;
14155 : }
14156 :
14157 : /* For each register (hardware or pseudo) used within expression X, if its
14158 : death is in an instruction with luid between FROM_LUID (inclusive) and
14159 : TO_INSN (exclusive), put a REG_DEAD note for that register in the
14160 : list headed by PNOTES.
14161 :
14162 : That said, don't move registers killed by maybe_kill_insn.
14163 :
14164 : This is done when X is being merged by combination into TO_INSN. These
14165 : notes will then be distributed as needed. */
14166 :
14167 : static void
14168 24495233 : move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14169 : rtx *pnotes)
14170 : {
14171 25034489 : const char *fmt;
14172 25034489 : int len, i;
14173 25034489 : enum rtx_code code = GET_CODE (x);
14174 :
14175 25034489 : if (code == REG)
14176 : {
14177 6202084 : unsigned int regno = REGNO (x);
14178 6202084 : rtx_insn *where_dead = reg_stat[regno].last_death;
14179 :
14180 : /* If we do not know where the register died, it may still die between
14181 : FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14182 6202084 : if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14183 : {
14184 3366544 : rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14185 3366544 : while (insn
14186 5054052 : && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14187 9369140 : && DF_INSN_LUID (insn) >= from_luid)
14188 : {
14189 2288419 : if (dead_or_set_regno_p (insn, regno))
14190 : {
14191 569423 : if (find_regno_note (insn, REG_DEAD, regno))
14192 6202084 : where_dead = insn;
14193 : break;
14194 : }
14195 :
14196 1718996 : insn = prev_real_nondebug_insn (insn);
14197 : }
14198 : }
14199 :
14200 : /* Don't move the register if it gets killed in between from and to. */
14201 141812 : if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14202 6243750 : && ! reg_referenced_p (x, maybe_kill_insn))
14203 : return;
14204 :
14205 6160418 : if (where_dead
14206 3194368 : && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14207 3035085 : && DF_INSN_LUID (where_dead) >= from_luid
14208 9195279 : && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14209 : {
14210 2742276 : rtx note = remove_death (regno, where_dead);
14211 :
14212 : /* It is possible for the call above to return 0. This can occur
14213 : when last_death points to I2 or I1 that we combined with.
14214 : In that case make a new note.
14215 :
14216 : We must also check for the case where X is a hard register
14217 : and NOTE is a death note for a range of hard registers
14218 : including X. In that case, we must put REG_DEAD notes for
14219 : the remaining registers in place of NOTE. */
14220 :
14221 2742276 : if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14222 2742276 : && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14223 : {
14224 0 : unsigned int deadregno = REGNO (XEXP (note, 0));
14225 0 : unsigned int deadend = END_REGNO (XEXP (note, 0));
14226 0 : unsigned int ourend = END_REGNO (x);
14227 0 : unsigned int i;
14228 :
14229 0 : for (i = deadregno; i < deadend; i++)
14230 0 : if (i < regno || i >= ourend)
14231 0 : add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14232 : }
14233 :
14234 : /* If we didn't find any note, or if we found a REG_DEAD note that
14235 : covers only part of the given reg, and we have a multi-reg hard
14236 : register, then to be safe we must check for REG_DEAD notes
14237 : for each register other than the first. They could have
14238 : their own REG_DEAD notes lying around. */
14239 2742276 : else if ((note == 0
14240 : || (note != 0
14241 76020 : && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14242 76020 : GET_MODE (x))))
14243 2666256 : && regno < FIRST_PSEUDO_REGISTER
14244 3080013 : && REG_NREGS (x) > 1)
14245 : {
14246 0 : unsigned int ourend = END_REGNO (x);
14247 0 : unsigned int i, offset;
14248 0 : rtx oldnotes = 0;
14249 :
14250 0 : if (note)
14251 0 : offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14252 : else
14253 : offset = 1;
14254 :
14255 0 : for (i = regno + offset; i < ourend; i++)
14256 0 : move_deaths (regno_reg_rtx[i],
14257 : maybe_kill_insn, from_luid, to_insn, &oldnotes);
14258 : }
14259 :
14260 2742276 : if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14261 : {
14262 75996 : XEXP (note, 1) = *pnotes;
14263 75996 : *pnotes = note;
14264 : }
14265 : else
14266 2666280 : *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14267 : }
14268 :
14269 : return;
14270 : }
14271 :
14272 18832405 : else if (GET_CODE (x) == SET)
14273 : {
14274 4244159 : rtx dest = SET_DEST (x);
14275 :
14276 4244159 : move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14277 :
14278 : /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14279 : that accesses one word of a multi-word item, some
14280 : piece of everything register in the expression is used by
14281 : this insn, so remove any old death. */
14282 : /* ??? So why do we test for equality of the sizes? */
14283 :
14284 4244159 : if (GET_CODE (dest) == ZERO_EXTRACT
14285 4243715 : || GET_CODE (dest) == STRICT_LOW_PART
14286 8486131 : || (GET_CODE (dest) == SUBREG
14287 78348 : && !read_modify_subreg_p (dest)))
14288 : {
14289 : move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14290 : return;
14291 : }
14292 :
14293 : /* If this is some other SUBREG, we know it replaces the entire
14294 : value, so use that as the destination. */
14295 4181511 : if (GET_CODE (dest) == SUBREG)
14296 17887 : dest = SUBREG_REG (dest);
14297 :
14298 : /* If this is a MEM, adjust deaths of anything used in the address.
14299 : For a REG (the only other possibility), the entire value is
14300 : being replaced so the old value is not used in this insn. */
14301 :
14302 4181511 : if (MEM_P (dest))
14303 476608 : move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14304 : to_insn, pnotes);
14305 : return;
14306 : }
14307 :
14308 14588246 : else if (GET_CODE (x) == CLOBBER)
14309 : return;
14310 :
14311 13963777 : len = GET_RTX_LENGTH (code);
14312 13963777 : fmt = GET_RTX_FORMAT (code);
14313 :
14314 36387304 : for (i = 0; i < len; i++)
14315 : {
14316 22423527 : if (fmt[i] == 'E')
14317 : {
14318 1015050 : int j;
14319 3608023 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14320 2592973 : move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14321 : to_insn, pnotes);
14322 : }
14323 21408477 : else if (fmt[i] == 'e')
14324 13488167 : move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14325 : }
14326 : }
14327 :
14328 : /* Return true if X is the target of a bit-field assignment in BODY, the
14329 : pattern of an insn. X must be a REG. */
14330 :
14331 : static bool
14332 4789125 : reg_bitfield_target_p (rtx x, rtx body)
14333 : {
14334 4789125 : int i;
14335 :
14336 4789125 : if (GET_CODE (body) == SET)
14337 : {
14338 3484000 : rtx dest = SET_DEST (body);
14339 3484000 : rtx target;
14340 3484000 : unsigned int regno, tregno, endregno, endtregno;
14341 :
14342 3484000 : if (GET_CODE (dest) == ZERO_EXTRACT)
14343 426 : target = XEXP (dest, 0);
14344 3483574 : else if (GET_CODE (dest) == STRICT_LOW_PART)
14345 1980 : target = SUBREG_REG (XEXP (dest, 0));
14346 : else
14347 : return false;
14348 :
14349 2406 : if (GET_CODE (target) == SUBREG)
14350 219 : target = SUBREG_REG (target);
14351 :
14352 2406 : if (!REG_P (target))
14353 : return false;
14354 :
14355 2327 : tregno = REGNO (target), regno = REGNO (x);
14356 2327 : if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14357 2317 : return target == x;
14358 :
14359 10 : endtregno = end_hard_regno (GET_MODE (target), tregno);
14360 10 : endregno = end_hard_regno (GET_MODE (x), regno);
14361 :
14362 10 : return endregno > tregno && regno < endtregno;
14363 : }
14364 :
14365 1305125 : else if (GET_CODE (body) == PARALLEL)
14366 1962343 : for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14367 1322375 : if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14368 : return true;
14369 :
14370 : return false;
14371 : }
14372 :
14373 : /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14374 : as appropriate. I3 and I2 are the insns resulting from the combination
14375 : insns including FROM (I2 may be zero).
14376 :
14377 : ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14378 : not need REG_DEAD notes because they are being substituted for. This
14379 : saves searching in the most common cases.
14380 :
14381 : Each note in the list is either ignored or placed on some insns, depending
14382 : on the type of note. */
14383 :
14384 : static void
14385 9954347 : distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14386 : rtx elim_i2, rtx elim_i1, rtx elim_i0)
14387 : {
14388 9954347 : rtx note, next_note;
14389 9954347 : rtx tem_note;
14390 9954347 : rtx_insn *tem_insn;
14391 :
14392 23071551 : for (note = notes; note; note = next_note)
14393 : {
14394 13117204 : rtx_insn *place = 0, *place2 = 0;
14395 :
14396 13117204 : next_note = XEXP (note, 1);
14397 13117204 : switch (REG_NOTE_KIND (note))
14398 : {
14399 : case REG_BR_PROB:
14400 : case REG_BR_PRED:
14401 : /* Doesn't matter much where we put this, as long as it's somewhere.
14402 : It is preferable to keep these notes on branches, which is most
14403 : likely to be i3. */
14404 : place = i3;
14405 : break;
14406 :
14407 0 : case REG_NON_LOCAL_GOTO:
14408 0 : if (JUMP_P (i3))
14409 : place = i3;
14410 : else
14411 : {
14412 0 : gcc_assert (i2 && JUMP_P (i2));
14413 : place = i2;
14414 : }
14415 : break;
14416 :
14417 21317 : case REG_EH_REGION:
14418 21317 : {
14419 : /* The landing pad handling needs to be kept in sync with the
14420 : prerequisite checking in try_combine. */
14421 21317 : int lp_nr = INTVAL (XEXP (note, 0));
14422 : /* A REG_EH_REGION note transferring control can only ever come
14423 : from i3. */
14424 21317 : if (lp_nr > 0)
14425 11699 : gcc_assert (from_insn == i3);
14426 : /* We are making sure there is a single effective REG_EH_REGION
14427 : note and it's valid to put it on i3. */
14428 21317 : if (!insn_could_throw_p (from_insn)
14429 21317 : && !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14430 : /* Throw away stray notes on insns that can never throw or
14431 : make a nonlocal goto. */
14432 : ;
14433 : else
14434 : {
14435 21240 : if (CALL_P (i3))
14436 : place = i3;
14437 : else
14438 : {
14439 2092 : gcc_assert (cfun->can_throw_non_call_exceptions);
14440 : /* If i3 can still trap preserve the note, otherwise we've
14441 : combined things such that we can now prove that the
14442 : instructions can't trap. Drop the note in this case. */
14443 2092 : if (may_trap_p (i3))
14444 : place = i3;
14445 : }
14446 : }
14447 : break;
14448 : }
14449 :
14450 126442 : case REG_ARGS_SIZE:
14451 : /* ??? How to distribute between i3-i1. Assume i3 contains the
14452 : entire adjustment. Assert i3 contains at least some adjust. */
14453 126442 : if (!noop_move_p (i3))
14454 : {
14455 126441 : poly_int64 old_size, args_size = get_args_size (note);
14456 : /* fixup_args_size_notes looks at REG_NORETURN note,
14457 : so ensure the note is placed there first. */
14458 126441 : if (CALL_P (i3))
14459 : {
14460 : rtx *np;
14461 1639 : for (np = &next_note; *np; np = &XEXP (*np, 1))
14462 20 : if (REG_NOTE_KIND (*np) == REG_NORETURN)
14463 : {
14464 9 : rtx n = *np;
14465 9 : *np = XEXP (n, 1);
14466 9 : XEXP (n, 1) = REG_NOTES (i3);
14467 9 : REG_NOTES (i3) = n;
14468 9 : break;
14469 : }
14470 : }
14471 126441 : old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14472 : /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14473 : REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14474 126441 : gcc_assert (maybe_ne (old_size, args_size)
14475 : || (CALL_P (i3)
14476 : && !ACCUMULATE_OUTGOING_ARGS
14477 : && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14478 : }
14479 : break;
14480 :
14481 80424 : case REG_NORETURN:
14482 80424 : case REG_SETJMP:
14483 80424 : case REG_TM:
14484 80424 : case REG_CALL_DECL:
14485 80424 : case REG_UNTYPED_CALL:
14486 80424 : case REG_CALL_NOCF_CHECK:
14487 : /* These notes must remain with the call. It should not be
14488 : possible for both I2 and I3 to be a call. */
14489 80424 : if (CALL_P (i3))
14490 : place = i3;
14491 : else
14492 : {
14493 0 : gcc_assert (i2 && CALL_P (i2));
14494 : place = i2;
14495 : }
14496 : break;
14497 :
14498 1954143 : case REG_UNUSED:
14499 : /* Any clobbers for i3 may still exist, and so we must process
14500 : REG_UNUSED notes from that insn.
14501 :
14502 : Any clobbers from i2 or i1 can only exist if they were added by
14503 : recog_for_combine. In that case, recog_for_combine created the
14504 : necessary REG_UNUSED notes. Trying to keep any original
14505 : REG_UNUSED notes from these insns can cause incorrect output
14506 : if it is for the same register as the original i3 dest.
14507 : In that case, we will notice that the register is set in i3,
14508 : and then add a REG_UNUSED note for the destination of i3, which
14509 : is wrong. However, it is possible to have REG_UNUSED notes from
14510 : i2 or i1 for register which were both used and clobbered, so
14511 : we keep notes from i2 or i1 if they will turn into REG_DEAD
14512 : notes. */
14513 :
14514 : /* If this register is set or clobbered between FROM_INSN and I3,
14515 : we should not create a note for it. */
14516 1954143 : if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14517 : break;
14518 :
14519 : /* If this register is set or clobbered in I3, put the note there
14520 : unless there is one already. */
14521 1868138 : if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14522 : {
14523 1106573 : if (from_insn != i3)
14524 : break;
14525 :
14526 648582 : if (! (REG_P (XEXP (note, 0))
14527 648582 : ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14528 0 : : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14529 : place = i3;
14530 : }
14531 : /* Otherwise, if this register is used by I3, then this register
14532 : now dies here, so we must put a REG_DEAD note here unless there
14533 : is one already. */
14534 761565 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14535 : {
14536 7600 : if (! (REG_P (XEXP (note, 0))
14537 7600 : ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
14538 0 : : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14539 : {
14540 7359 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14541 7359 : place = i3;
14542 : }
14543 : }
14544 :
14545 : /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14546 : but we can't tell which at this point. We must reset any
14547 : expectations we had about the value that was previously
14548 : stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14549 : and, if appropriate, restore its previous value, but we
14550 : don't have enough information for that at this point. */
14551 : else
14552 : {
14553 753965 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14554 :
14555 : /* Otherwise, if this register is now referenced in i2
14556 : then the register used to be modified in one of the
14557 : original insns. If it was i3 (say, in an unused
14558 : parallel), it's now completely gone, so the note can
14559 : be discarded. But if it was modified in i2, i1 or i0
14560 : and we still reference it in i2, then we're
14561 : referencing the previous value, and since the
14562 : register was modified and REG_UNUSED, we know that
14563 : the previous value is now dead. So, if we only
14564 : reference the register in i2, we change the note to
14565 : REG_DEAD, to reflect the previous value. However, if
14566 : we're also setting or clobbering the register as
14567 : scratch, we know (because the register was not
14568 : referenced in i3) that it's unused, just as it was
14569 : unused before, and we place the note in i2. */
14570 16964 : if (from_insn != i3 && i2 && INSN_P (i2)
14571 770929 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14572 : {
14573 24 : if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14574 24 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14575 24 : if (! (REG_P (XEXP (note, 0))
14576 24 : ? find_regno_note (i2, REG_NOTE_KIND (note),
14577 24 : REGNO (XEXP (note, 0)))
14578 0 : : find_reg_note (i2, REG_NOTE_KIND (note),
14579 : XEXP (note, 0))))
14580 : place = i2;
14581 : }
14582 : }
14583 :
14584 : break;
14585 :
14586 392716 : case REG_EQUAL:
14587 392716 : case REG_EQUIV:
14588 392716 : case REG_NOALIAS:
14589 : /* These notes say something about results of an insn. We can
14590 : only support them if they used to be on I3 in which case they
14591 : remain on I3. Otherwise they are ignored.
14592 :
14593 : If the note refers to an expression that is not a constant, we
14594 : must also ignore the note since we cannot tell whether the
14595 : equivalence is still true. It might be possible to do
14596 : slightly better than this (we only have a problem if I2DEST
14597 : or I1DEST is present in the expression), but it doesn't
14598 : seem worth the trouble. */
14599 :
14600 392716 : if (from_insn == i3
14601 193039 : && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14602 : place = i3;
14603 : break;
14604 :
14605 0 : case REG_INC:
14606 : /* These notes say something about how a register is used. They must
14607 : be present on any use of the register in I2 or I3. */
14608 0 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14609 0 : place = i3;
14610 :
14611 0 : if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14612 : {
14613 0 : if (place)
14614 : place2 = i2;
14615 : else
14616 : place = i2;
14617 : }
14618 : break;
14619 :
14620 6839 : case REG_LABEL_TARGET:
14621 6839 : case REG_LABEL_OPERAND:
14622 : /* This can show up in several ways -- either directly in the
14623 : pattern, or hidden off in the constant pool with (or without?)
14624 : a REG_EQUAL note. */
14625 : /* ??? Ignore the without-reg_equal-note problem for now. */
14626 6839 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14627 6839 : || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14628 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14629 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14630 : place = i3;
14631 :
14632 6839 : if (i2
14633 6839 : && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14634 0 : || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14635 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14636 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14637 : {
14638 0 : if (place)
14639 : place2 = i2;
14640 : else
14641 : place = i2;
14642 : }
14643 :
14644 : /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14645 : as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14646 : there. */
14647 6839 : if (place && JUMP_P (place)
14648 5591 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14649 0 : && (JUMP_LABEL (place) == NULL
14650 0 : || JUMP_LABEL (place) == XEXP (note, 0)))
14651 : {
14652 0 : rtx label = JUMP_LABEL (place);
14653 :
14654 0 : if (!label)
14655 0 : JUMP_LABEL (place) = XEXP (note, 0);
14656 0 : else if (LABEL_P (label))
14657 0 : LABEL_NUSES (label)--;
14658 : }
14659 :
14660 6839 : if (place2 && JUMP_P (place2)
14661 0 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14662 0 : && (JUMP_LABEL (place2) == NULL
14663 0 : || JUMP_LABEL (place2) == XEXP (note, 0)))
14664 : {
14665 0 : rtx label = JUMP_LABEL (place2);
14666 :
14667 0 : if (!label)
14668 0 : JUMP_LABEL (place2) = XEXP (note, 0);
14669 0 : else if (LABEL_P (label))
14670 0 : LABEL_NUSES (label)--;
14671 : place2 = 0;
14672 : }
14673 : break;
14674 :
14675 : case REG_NONNEG:
14676 : /* This note says something about the value of a register prior
14677 : to the execution of an insn. It is too much trouble to see
14678 : if the note is still correct in all situations. It is better
14679 : to simply delete it. */
14680 : break;
14681 :
14682 10495306 : case REG_DEAD:
14683 : /* If we replaced the right hand side of FROM_INSN with a
14684 : REG_EQUAL note, the original use of the dying register
14685 : will not have been combined into I3 and I2. In such cases,
14686 : FROM_INSN is guaranteed to be the first of the combined
14687 : instructions, so we simply need to search back before
14688 : FROM_INSN for the previous use or set of this register,
14689 : then alter the notes there appropriately.
14690 :
14691 : If the register is used as an input in I3, it dies there.
14692 : Similarly for I2, if it is nonzero and adjacent to I3.
14693 :
14694 : If the register is not used as an input in either I3 or I2
14695 : and it is not one of the registers we were supposed to eliminate,
14696 : there are two possibilities. We might have a non-adjacent I2
14697 : or we might have somehow eliminated an additional register
14698 : from a computation. For example, we might have had A & B where
14699 : we discover that B will always be zero. In this case we will
14700 : eliminate the reference to A.
14701 :
14702 : In both cases, we must search to see if we can find a previous
14703 : use of A and put the death note there. */
14704 :
14705 10495306 : if (from_insn
14706 7328977 : && from_insn == i2mod
14707 10496936 : && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14708 : tem_insn = from_insn;
14709 : else
14710 : {
14711 10493965 : if (from_insn
14712 7327636 : && CALL_P (from_insn)
14713 10724558 : && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14714 : place = from_insn;
14715 10343789 : else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14716 : {
14717 : /* If the new I2 sets the same register that is marked
14718 : dead in the note, we do not in general know where to
14719 : put the note. One important case we _can_ handle is
14720 : when the note comes from I3. */
14721 39231 : if (from_insn == i3)
14722 : place = i3;
14723 : else
14724 : break;
14725 : }
14726 10304558 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14727 : place = i3;
14728 103247 : else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14729 4107462 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14730 : place = i2;
14731 3962028 : else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14732 3843679 : && !(i2mod
14733 26780 : && reg_overlap_mentioned_p (XEXP (note, 0),
14734 : i2mod_old_rhs)))
14735 145139 : || rtx_equal_p (XEXP (note, 0), elim_i1)
14736 4015838 : || rtx_equal_p (XEXP (note, 0), elim_i0))
14737 : break;
14738 : tem_insn = i3;
14739 : }
14740 :
14741 234411 : if (place == 0)
14742 : {
14743 50701 : basic_block bb = this_basic_block;
14744 :
14745 1526809 : for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14746 : {
14747 1526809 : if (!NONDEBUG_INSN_P (tem_insn))
14748 : {
14749 1077839 : if (tem_insn == BB_HEAD (bb))
14750 : break;
14751 1043384 : continue;
14752 : }
14753 :
14754 : /* If the register is being set at TEM_INSN, see if that is all
14755 : TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14756 : into a REG_UNUSED note instead. Don't delete sets to
14757 : global register vars. */
14758 448970 : if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14759 1454 : || !global_regs[REGNO (XEXP (note, 0))])
14760 450424 : && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14761 : {
14762 15659 : rtx set = single_set (tem_insn);
14763 15659 : rtx inner_dest = 0;
14764 :
14765 15659 : if (set != 0)
14766 12179 : for (inner_dest = SET_DEST (set);
14767 12428 : (GET_CODE (inner_dest) == STRICT_LOW_PART
14768 12428 : || GET_CODE (inner_dest) == SUBREG
14769 12428 : || GET_CODE (inner_dest) == ZERO_EXTRACT);
14770 249 : inner_dest = XEXP (inner_dest, 0))
14771 : ;
14772 :
14773 : /* Verify that it was the set, and not a clobber that
14774 : modified the register.
14775 :
14776 : If we cannot delete the setter due to side
14777 : effects, mark the user with an UNUSED note instead
14778 : of deleting it. */
14779 :
14780 12179 : if (set != 0 && ! side_effects_p (SET_SRC (set))
14781 11809 : && rtx_equal_p (XEXP (note, 0), inner_dest))
14782 : {
14783 : /* Move the notes and links of TEM_INSN elsewhere.
14784 : This might delete other dead insns recursively.
14785 : First set the pattern to something that won't use
14786 : any register. */
14787 11592 : rtx old_notes = REG_NOTES (tem_insn);
14788 :
14789 11592 : PATTERN (tem_insn) = pc_rtx;
14790 11592 : REG_NOTES (tem_insn) = NULL;
14791 :
14792 11592 : distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14793 : NULL_RTX, NULL_RTX, NULL_RTX);
14794 11592 : distribute_links (LOG_LINKS (tem_insn));
14795 :
14796 11592 : unsigned int regno = REGNO (XEXP (note, 0));
14797 11592 : reg_stat_type *rsp = ®_stat[regno];
14798 11592 : if (rsp->last_set == tem_insn)
14799 10197 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14800 :
14801 11592 : SET_INSN_DELETED (tem_insn);
14802 11592 : if (tem_insn == i2)
14803 432724 : i2 = NULL;
14804 : }
14805 : else
14806 : {
14807 4067 : PUT_REG_NOTE_KIND (note, REG_UNUSED);
14808 :
14809 : /* If there isn't already a REG_UNUSED note, put one
14810 : here. Do not place a REG_DEAD note, even if
14811 : the register is also used here; that would not
14812 : match the algorithm used in lifetime analysis
14813 : and can cause the consistency check in the
14814 : scheduler to fail. */
14815 4067 : if (! find_regno_note (tem_insn, REG_UNUSED,
14816 4067 : REGNO (XEXP (note, 0))))
14817 2188 : place = tem_insn;
14818 : break;
14819 : }
14820 : }
14821 433311 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14822 433311 : || (CALL_P (tem_insn)
14823 14248 : && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14824 : {
14825 12179 : place = tem_insn;
14826 :
14827 : /* If we are doing a 3->2 combination, and we have a
14828 : register which formerly died in i3 and was not used
14829 : by i2, which now no longer dies in i3 and is used in
14830 : i2 but does not die in i2, and place is between i2
14831 : and i3, then we may need to move a link from place to
14832 : i2. */
14833 3687 : if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14834 93 : && from_insn
14835 93 : && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14836 12272 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14837 : {
14838 93 : struct insn_link *links = LOG_LINKS (place);
14839 93 : LOG_LINKS (place) = NULL;
14840 93 : distribute_links (links);
14841 : }
14842 : break;
14843 : }
14844 :
14845 432724 : if (tem_insn == BB_HEAD (bb))
14846 : break;
14847 : }
14848 :
14849 : }
14850 :
14851 : /* If the register is set or already dead at PLACE, we needn't do
14852 : anything with this note if it is still a REG_DEAD note.
14853 : We check here if it is set at all, not if is it totally replaced,
14854 : which is what `dead_or_set_p' checks, so also check for it being
14855 : set partially. */
14856 :
14857 6578985 : if (place && REG_NOTE_KIND (note) == REG_DEAD)
14858 : {
14859 6540463 : unsigned int regno = REGNO (XEXP (note, 0));
14860 6540463 : reg_stat_type *rsp = ®_stat[regno];
14861 :
14862 6540463 : if (dead_or_set_p (place, XEXP (note, 0))
14863 6540463 : || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14864 : {
14865 : /* Unless the register previously died in PLACE, clear
14866 : last_death. [I no longer understand why this is
14867 : being done.] */
14868 3073723 : if (rsp->last_death != place)
14869 634894 : rsp->last_death = 0;
14870 : place = 0;
14871 : }
14872 : else
14873 3466740 : rsp->last_death = place;
14874 :
14875 : /* If this is a death note for a hard reg that is occupying
14876 : multiple registers, ensure that we are still using all
14877 : parts of the object. If we find a piece of the object
14878 : that is unused, we must arrange for an appropriate REG_DEAD
14879 : note to be added for it. However, we can't just emit a USE
14880 : and tag the note to it, since the register might actually
14881 : be dead; so we recurse, and the recursive call then finds
14882 : the previous insn that used this register. */
14883 :
14884 4101634 : if (place && REG_NREGS (XEXP (note, 0)) > 1)
14885 : {
14886 776 : unsigned int endregno = END_REGNO (XEXP (note, 0));
14887 776 : bool all_used = true;
14888 776 : unsigned int i;
14889 :
14890 2328 : for (i = regno; i < endregno; i++)
14891 1552 : if ((! refers_to_regno_p (i, PATTERN (place))
14892 1552 : && ! find_regno_fusage (place, USE, i))
14893 3104 : || dead_or_set_regno_p (place, i))
14894 : {
14895 : all_used = false;
14896 : break;
14897 : }
14898 :
14899 776 : if (! all_used)
14900 : {
14901 : /* Put only REG_DEAD notes for pieces that are
14902 : not already dead or set. */
14903 :
14904 0 : for (i = regno; i < endregno;
14905 0 : i += hard_regno_nregs (i, reg_raw_mode[i]))
14906 : {
14907 0 : rtx piece = regno_reg_rtx[i];
14908 0 : basic_block bb = this_basic_block;
14909 :
14910 0 : if (! dead_or_set_p (place, piece)
14911 0 : && ! reg_bitfield_target_p (piece,
14912 0 : PATTERN (place)))
14913 : {
14914 0 : rtx new_note = alloc_reg_note (REG_DEAD, piece,
14915 : NULL_RTX);
14916 :
14917 0 : distribute_notes (new_note, place, place,
14918 : NULL, NULL_RTX, NULL_RTX,
14919 : NULL_RTX);
14920 : }
14921 0 : else if (! refers_to_regno_p (i, PATTERN (place))
14922 0 : && ! find_regno_fusage (place, USE, i))
14923 0 : for (tem_insn = PREV_INSN (place); ;
14924 0 : tem_insn = PREV_INSN (tem_insn))
14925 : {
14926 0 : if (!NONDEBUG_INSN_P (tem_insn))
14927 : {
14928 0 : if (tem_insn == BB_HEAD (bb))
14929 : break;
14930 0 : continue;
14931 : }
14932 0 : if (dead_or_set_p (tem_insn, piece)
14933 0 : || reg_bitfield_target_p (piece,
14934 0 : PATTERN (tem_insn)))
14935 : {
14936 0 : add_reg_note (tem_insn, REG_UNUSED, piece);
14937 0 : break;
14938 : }
14939 : }
14940 : }
14941 :
14942 : place = 0;
14943 : }
14944 : }
14945 : }
14946 : break;
14947 :
14948 0 : default:
14949 : /* Any other notes should not be present at this point in the
14950 : compilation. */
14951 0 : gcc_unreachable ();
14952 : }
14953 :
14954 4287773 : if (place)
14955 : {
14956 4260904 : XEXP (note, 1) = REG_NOTES (place);
14957 4260904 : REG_NOTES (place) = note;
14958 :
14959 : /* Set added_notes_insn to the earliest insn we added a note to. */
14960 4260904 : if (added_notes_insn == 0
14961 4260904 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14962 2819999 : added_notes_insn = place;
14963 : }
14964 :
14965 13117204 : if (place2)
14966 : {
14967 0 : add_shallow_copy_of_reg_note (place2, note);
14968 :
14969 : /* Set added_notes_insn to the earliest insn we added a note to. */
14970 0 : if (added_notes_insn == 0
14971 0 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14972 0 : added_notes_insn = place2;
14973 : }
14974 : }
14975 9954347 : }
14976 :
14977 : /* Similarly to above, distribute the LOG_LINKS that used to be present on
14978 : I3, I2, and I1 to new locations. This is also called to add a link
14979 : pointing at I3 when I3's destination is changed.
14980 :
14981 : If START is nonnull and an insn, we know that the next location for each
14982 : link is no earlier than START. LIMIT is the maximum number of nondebug
14983 : instructions that can be scanned when looking for the next use of a
14984 : definition. */
14985 :
14986 : static void
14987 16197527 : distribute_links (struct insn_link *links, rtx_insn *start, int limit)
14988 : {
14989 16197527 : struct insn_link *link, *next_link;
14990 :
14991 23875282 : for (link = links; link; link = next_link)
14992 : {
14993 7677755 : rtx_insn *place = 0;
14994 7677755 : rtx_insn *insn;
14995 7677755 : rtx set, reg;
14996 :
14997 7677755 : next_link = link->next;
14998 :
14999 : /* If the insn that this link points to is a NOTE, ignore it. */
15000 7677755 : if (NOTE_P (link->insn))
15001 4080496 : continue;
15002 :
15003 3597259 : set = 0;
15004 3597259 : rtx pat = PATTERN (link->insn);
15005 3597259 : if (GET_CODE (pat) == SET)
15006 : set = pat;
15007 623794 : else if (GET_CODE (pat) == PARALLEL)
15008 : {
15009 : int i;
15010 737740 : for (i = 0; i < XVECLEN (pat, 0); i++)
15011 : {
15012 734117 : set = XVECEXP (pat, 0, i);
15013 734117 : if (GET_CODE (set) != SET)
15014 3632 : continue;
15015 :
15016 730485 : reg = SET_DEST (set);
15017 730485 : while (GET_CODE (reg) == ZERO_EXTRACT
15018 739051 : || GET_CODE (reg) == STRICT_LOW_PART
15019 1478059 : || GET_CODE (reg) == SUBREG)
15020 8573 : reg = XEXP (reg, 0);
15021 :
15022 730485 : if (!REG_P (reg))
15023 44425 : continue;
15024 :
15025 686060 : if (REGNO (reg) == link->regno)
15026 : break;
15027 : }
15028 621613 : if (i == XVECLEN (pat, 0))
15029 3623 : continue;
15030 : }
15031 : else
15032 2181 : continue;
15033 :
15034 3591455 : reg = SET_DEST (set);
15035 :
15036 3591455 : while (GET_CODE (reg) == ZERO_EXTRACT
15037 3614589 : || GET_CODE (reg) == STRICT_LOW_PART
15038 7229287 : || GET_CODE (reg) == SUBREG)
15039 23647 : reg = XEXP (reg, 0);
15040 :
15041 3591455 : if (reg == pc_rtx)
15042 490 : continue;
15043 :
15044 : /* A LOG_LINK is defined as being placed on the first insn that uses
15045 : a register and points to the insn that sets the register. Start
15046 : searching at the next insn after the target of the link and stop
15047 : when we reach a set of the register or the end of the basic block.
15048 :
15049 : Note that this correctly handles the link that used to point from
15050 : I3 to I2. Also note that not much searching is typically done here
15051 : since most links don't point very far away. */
15052 :
15053 3590965 : int count = 0;
15054 3590965 : insn = start;
15055 3590965 : if (!insn || NOTE_P (insn))
15056 3539353 : insn = NEXT_INSN (link->insn);
15057 : else
15058 51612 : count = link->insn_count;
15059 11933027 : for (;
15060 15523992 : (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
15061 10678868 : || BB_HEAD (this_basic_block->next_bb) != insn));
15062 11933027 : insn = NEXT_INSN (insn))
15063 15484048 : if (DEBUG_INSN_P (insn))
15064 3292561 : continue;
15065 12191487 : else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
15066 : {
15067 3398174 : if (reg_referenced_p (reg, PATTERN (insn)))
15068 3398174 : place = insn;
15069 : break;
15070 : }
15071 8793313 : else if (CALL_P (insn)
15072 8793313 : && find_reg_fusage (insn, USE, reg))
15073 : {
15074 : place = insn;
15075 : break;
15076 : }
15077 8640646 : else if (INSN_P (insn) && reg_set_p (reg, insn))
15078 : break;
15079 8640466 : else if (count >= limit)
15080 : break;
15081 : else
15082 8640466 : count += 1;
15083 3590965 : link->insn_count = count;
15084 :
15085 : /* If we found a place to put the link, place it there unless there
15086 : is already a link to the same insn as LINK at that point. */
15087 :
15088 3590965 : if (place)
15089 : {
15090 3550841 : struct insn_link *link2;
15091 :
15092 4578793 : FOR_EACH_LOG_LINK (link2, place)
15093 1045355 : if (link2->insn == link->insn && link2->regno == link->regno)
15094 : break;
15095 :
15096 3550841 : if (link2 == NULL)
15097 : {
15098 3533438 : link->next = LOG_LINKS (place);
15099 3533438 : LOG_LINKS (place) = link;
15100 :
15101 : /* Set added_links_insn to the earliest insn we added a
15102 : link to. */
15103 3533438 : if (added_links_insn == 0
15104 3533438 : || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15105 2800221 : added_links_insn = place;
15106 : }
15107 : }
15108 : }
15109 16197527 : }
15110 :
15111 : /* Check for any register or memory mentioned in EQUIV that is not
15112 : mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15113 : of EXPR where some registers may have been replaced by constants. */
15114 :
15115 : static bool
15116 2757588 : unmentioned_reg_p (rtx equiv, rtx expr)
15117 : {
15118 2757588 : subrtx_iterator::array_type array;
15119 7223660 : FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15120 : {
15121 5860846 : const_rtx x = *iter;
15122 4024592 : if ((REG_P (x) || MEM_P (x))
15123 6253541 : && !reg_mentioned_p (x, expr))
15124 1394774 : return true;
15125 : }
15126 1362814 : return false;
15127 2757588 : }
15128 :
15129 : /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15130 : the reg-to-reg copy can usefully combine with later instructions, but we
15131 : do not want to combine the hard reg into later instructions, for that
15132 : restricts register allocation. */
15133 : static void
15134 1064387 : make_more_copies (void)
15135 : {
15136 1064387 : basic_block bb;
15137 :
15138 11640091 : FOR_EACH_BB_FN (bb, cfun)
15139 : {
15140 10575704 : rtx_insn *insn;
15141 :
15142 140925731 : FOR_BB_INSNS (bb, insn)
15143 : {
15144 130350027 : if (!NONDEBUG_INSN_P (insn))
15145 70195077 : continue;
15146 :
15147 60154950 : rtx set = single_set (insn);
15148 60154950 : if (!set)
15149 4080513 : continue;
15150 :
15151 56074437 : rtx dest = SET_DEST (set);
15152 56074437 : if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15153 32083076 : continue;
15154 :
15155 23991361 : rtx src = SET_SRC (set);
15156 23991361 : if (!(REG_P (src) && HARD_REGISTER_P (src)))
15157 20963129 : continue;
15158 3028232 : if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15159 9954 : continue;
15160 :
15161 3018278 : rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15162 :
15163 : /* The "original" pseudo copies have important attributes
15164 : attached, like pointerness. We want that for these copies
15165 : too, for use by insn recognition and later passes. */
15166 3018278 : set_reg_attrs_from_value (new_reg, dest);
15167 :
15168 3018278 : rtx_insn *new_insn = gen_move_insn (new_reg, src);
15169 3018278 : SET_SRC (set) = new_reg;
15170 3018278 : emit_insn_before (new_insn, insn);
15171 3018278 : df_insn_rescan (insn);
15172 : }
15173 : }
15174 1064387 : }
15175 :
15176 : /* Try combining insns through substitution. */
15177 : static void
15178 1064387 : rest_of_handle_combine (void)
15179 : {
15180 1064387 : make_more_copies ();
15181 :
15182 1064387 : df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15183 1064387 : df_note_add_problem ();
15184 1064387 : df_analyze ();
15185 :
15186 1064387 : regstat_init_n_sets_and_refs ();
15187 1064387 : reg_n_sets_max = max_reg_num ();
15188 :
15189 1064387 : bool rebuild_jump_labels_after_combine
15190 1064387 : = combine_instructions (get_insns (), max_reg_num ());
15191 :
15192 : /* Combining insns may have turned an indirect jump into a
15193 : direct jump. Rebuild the JUMP_LABEL fields of jumping
15194 : instructions. */
15195 1064387 : if (rebuild_jump_labels_after_combine)
15196 : {
15197 2360 : if (dom_info_available_p (CDI_DOMINATORS))
15198 0 : free_dominance_info (CDI_DOMINATORS);
15199 2360 : timevar_push (TV_JUMP);
15200 2360 : rebuild_jump_labels (get_insns ());
15201 2360 : cleanup_cfg (0);
15202 2360 : timevar_pop (TV_JUMP);
15203 : }
15204 :
15205 1064387 : regstat_free_n_sets_and_refs ();
15206 1064387 : }
15207 :
15208 : namespace {
15209 :
15210 : const pass_data pass_data_combine =
15211 : {
15212 : RTL_PASS, /* type */
15213 : "combine", /* name */
15214 : OPTGROUP_NONE, /* optinfo_flags */
15215 : TV_COMBINE, /* tv_id */
15216 : PROP_cfglayout, /* properties_required */
15217 : 0, /* properties_provided */
15218 : 0, /* properties_destroyed */
15219 : 0, /* todo_flags_start */
15220 : TODO_df_finish, /* todo_flags_finish */
15221 : };
15222 :
15223 : class pass_combine : public rtl_opt_pass
15224 : {
15225 : public:
15226 294587 : pass_combine (gcc::context *ctxt)
15227 589174 : : rtl_opt_pass (pass_data_combine, ctxt)
15228 : {}
15229 :
15230 : /* opt_pass methods: */
15231 1511392 : bool gate (function *) final override { return (optimize > 0); }
15232 1064387 : unsigned int execute (function *) final override
15233 : {
15234 1064387 : rest_of_handle_combine ();
15235 1064387 : return 0;
15236 : }
15237 :
15238 : }; // class pass_combine
15239 :
15240 : } // anon namespace
15241 :
15242 : rtl_opt_pass *
15243 294587 : make_pass_combine (gcc::context *ctxt)
15244 : {
15245 294587 : return new pass_combine (ctxt);
15246 : }
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