Line data Source code
1 : /* Optimize by combining instructions for GNU compiler.
2 : Copyright (C) 1987-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it under
7 : the terms of the GNU General Public License as published by the Free
8 : Software Foundation; either version 3, or (at your option) any later
9 : version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : /* This module is essentially the "combiner" phase of the U. of Arizona
21 : Portable Optimizer, but redone to work on our list-structured
22 : representation for RTL instead of their string representation.
23 :
24 : The LOG_LINKS of each insn identify the most recent assignment
25 : to each REG used in the insn. It is a list of previous insns,
26 : each of which contains a SET for a REG that is used in this insn
27 : and not used or set in between. LOG_LINKs never cross basic blocks.
28 : They were set up by the preceding pass (lifetime analysis).
29 :
30 : We try to combine each pair of insns joined by a logical link.
31 : We also try to combine triplets of insns A, B and C when C has
32 : a link back to B and B has a link back to A. Likewise for a
33 : small number of quadruplets of insns A, B, C and D for which
34 : there's high likelihood of success.
35 :
36 : We check (with modified_between_p) to avoid combining in such a way
37 : as to move a computation to a place where its value would be different.
38 :
39 : Combination is done by mathematically substituting the previous
40 : insn(s) values for the regs they set into the expressions in
41 : the later insns that refer to these regs. If the result is a valid insn
42 : for our target machine, according to the machine description,
43 : we install it, delete the earlier insns, and update the data flow
44 : information (LOG_LINKS and REG_NOTES) for what we did.
45 :
46 : There are a few exceptions where the dataflow information isn't
47 : completely updated (however this is only a local issue since it is
48 : regenerated before the next pass that uses it):
49 :
50 : - reg_live_length is not updated
51 : - reg_n_refs is not adjusted in the rare case when a register is
52 : no longer required in a computation
53 : - there are extremely rare cases (see distribute_notes) when a
54 : REG_DEAD note is lost
55 : - a LOG_LINKS entry that refers to an insn with multiple SETs may be
56 : removed because there is no way to know which register it was
57 : linking
58 :
59 : To simplify substitution, we combine only when the earlier insn(s)
60 : consist of only a single assignment. To simplify updating afterward,
61 : we never combine when a subroutine call appears in the middle. */
62 :
63 : #include "config.h"
64 : #include "system.h"
65 : #include "coretypes.h"
66 : #include "backend.h"
67 : #include "target.h"
68 : #include "rtl.h"
69 : #include "tree.h"
70 : #include "cfghooks.h"
71 : #include "predict.h"
72 : #include "df.h"
73 : #include "memmodel.h"
74 : #include "tm_p.h"
75 : #include "optabs.h"
76 : #include "regs.h"
77 : #include "emit-rtl.h"
78 : #include "recog.h"
79 : #include "cgraph.h"
80 : #include "stor-layout.h"
81 : #include "cfgrtl.h"
82 : #include "cfgcleanup.h"
83 : /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84 : #include "explow.h"
85 : #include "insn-attr.h"
86 : #include "rtlhooks-def.h"
87 : #include "expr.h"
88 : #include "tree-pass.h"
89 : #include "valtrack.h"
90 : #include "rtl-iter.h"
91 : #include "print-rtl.h"
92 : #include "function-abi.h"
93 : #include "rtlanal.h"
94 :
95 : /* Number of attempts to combine instructions in this function. */
96 :
97 : static int combine_attempts;
98 :
99 : /* Number of attempts that got as far as substitution in this function. */
100 :
101 : static int combine_merges;
102 :
103 : /* Number of instructions combined with added SETs in this function. */
104 :
105 : static int combine_extras;
106 :
107 : /* Number of instructions combined in this function. */
108 :
109 : static int combine_successes;
110 :
111 : /* combine_instructions may try to replace the right hand side of the
112 : second instruction with the value of an associated REG_EQUAL note
113 : before throwing it at try_combine. That is problematic when there
114 : is a REG_DEAD note for a register used in the old right hand side
115 : and can cause distribute_notes to do wrong things. This is the
116 : second instruction if it has been so modified, null otherwise. */
117 :
118 : static rtx_insn *i2mod;
119 :
120 : /* When I2MOD is nonnull, this is a copy of the old right hand side. */
121 :
122 : static rtx i2mod_old_rhs;
123 :
124 : /* When I2MOD is nonnull, this is a copy of the new right hand side. */
125 :
126 : static rtx i2mod_new_rhs;
127 :
128 : struct reg_stat_type {
129 : /* Record last point of death of (hard or pseudo) register n. */
130 : rtx_insn *last_death;
131 :
132 : /* Record last point of modification of (hard or pseudo) register n. */
133 : rtx_insn *last_set;
134 :
135 : /* The next group of fields allows the recording of the last value assigned
136 : to (hard or pseudo) register n. We use this information to see if an
137 : operation being processed is redundant given a prior operation performed
138 : on the register. For example, an `and' with a constant is redundant if
139 : all the zero bits are already known to be turned off.
140 :
141 : We use an approach similar to that used by cse, but change it in the
142 : following ways:
143 :
144 : (1) We do not want to reinitialize at each label.
145 : (2) It is useful, but not critical, to know the actual value assigned
146 : to a register. Often just its form is helpful.
147 :
148 : Therefore, we maintain the following fields:
149 :
150 : last_set_value the last value assigned
151 : last_set_label records the value of label_tick when the
152 : register was assigned
153 : last_set_table_tick records the value of label_tick when a
154 : value using the register is assigned
155 : last_set_invalid set to true when it is not valid
156 : to use the value of this register in some
157 : register's value
158 :
159 : To understand the usage of these tables, it is important to understand
160 : the distinction between the value in last_set_value being valid and
161 : the register being validly contained in some other expression in the
162 : table.
163 :
164 : (The next two parameters are out of date).
165 :
166 : reg_stat[i].last_set_value is valid if it is nonzero, and either
167 : reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168 :
169 : Register I may validly appear in any expression returned for the value
170 : of another register if reg_n_sets[i] is 1. It may also appear in the
171 : value for register J if reg_stat[j].last_set_invalid is zero, or
172 : reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173 :
174 : If an expression is found in the table containing a register which may
175 : not validly appear in an expression, the register is replaced by
176 : something that won't match, (clobber (const_int 0)). */
177 :
178 : /* Record last value assigned to (hard or pseudo) register n. */
179 :
180 : rtx last_set_value;
181 :
182 : /* Record the value of label_tick when an expression involving register n
183 : is placed in last_set_value. */
184 :
185 : int last_set_table_tick;
186 :
187 : /* Record the value of label_tick when the value for register n is placed in
188 : last_set_value. */
189 :
190 : int last_set_label;
191 :
192 : /* These fields are maintained in parallel with last_set_value and are
193 : used to store the mode in which the register was last set, the bits
194 : that were known to be zero when it was last set, and the number of
195 : sign bits copies it was known to have when it was last set. */
196 :
197 : unsigned HOST_WIDE_INT last_set_nonzero_bits;
198 : unsigned short last_set_sign_bit_copies;
199 : machine_mode last_set_mode : MACHINE_MODE_BITSIZE;
200 :
201 : /* Set to true if references to register n in expressions should not be
202 : used. last_set_invalid is set nonzero when this register is being
203 : assigned to and last_set_table_tick == label_tick. */
204 :
205 : bool last_set_invalid;
206 :
207 : /* Some registers that are set more than once and used in more than one
208 : basic block are nevertheless always set in similar ways. For example,
209 : a QImode register may be loaded from memory in two places on a machine
210 : where byte loads zero extend.
211 :
212 : We record in the following fields if a register has some leading bits
213 : that are always equal to the sign bit, and what we know about the
214 : nonzero bits of a register, specifically which bits are known to be
215 : zero.
216 :
217 : If an entry is zero, it means that we don't know anything special. */
218 :
219 : unsigned short sign_bit_copies;
220 :
221 : unsigned HOST_WIDE_INT nonzero_bits;
222 :
223 : /* Record the value of the label_tick when the last truncation
224 : happened. The field truncated_to_mode is only valid if
225 : truncation_label == label_tick. */
226 :
227 : int truncation_label;
228 :
229 : /* Record the last truncation seen for this register. If truncation
230 : is not a nop to this mode we might be able to save an explicit
231 : truncation if we know that value already contains a truncated
232 : value. */
233 :
234 : machine_mode truncated_to_mode : MACHINE_MODE_BITSIZE;
235 : };
236 :
237 :
238 : static vec<reg_stat_type> reg_stat;
239 :
240 : /* One plus the highest pseudo for which we track REG_N_SETS.
241 : regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242 : but during combine_split_insns new pseudos can be created. As we don't have
243 : updated DF information in that case, it is hard to initialize the array
244 : after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245 : so instead of growing the arrays, just assume all newly created pseudos
246 : during combine might be set multiple times. */
247 :
248 : static unsigned int reg_n_sets_max;
249 :
250 : /* Record the luid of the last insn that invalidated memory
251 : (anything that writes memory, and subroutine calls, but not pushes). */
252 :
253 : static int mem_last_set;
254 :
255 : /* Record the luid of the last CALL_INSN
256 : so we can tell whether a potential combination crosses any calls. */
257 :
258 : static int last_call_luid;
259 :
260 : /* When `subst' is called, this is the insn that is being modified
261 : (by combining in a previous insn). The PATTERN of this insn
262 : is still the old pattern partially modified and it should not be
263 : looked at, but this may be used to examine the successors of the insn
264 : to judge whether a simplification is valid. */
265 :
266 : static rtx_insn *subst_insn;
267 :
268 : /* This is the lowest LUID that `subst' is currently dealing with.
269 : get_last_value will not return a value if the register was set at or
270 : after this LUID. If not for this mechanism, we could get confused if
271 : I2 or I1 in try_combine were an insn that used the old value of a register
272 : to obtain a new value. In that case, we might erroneously get the
273 : new value of the register when we wanted the old one. */
274 :
275 : static int subst_low_luid;
276 :
277 : /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 : must consider all these registers to be always live. */
279 :
280 : static HARD_REG_SET newpat_used_regs;
281 :
282 : /* This is an insn to which a LOG_LINKS entry has been added. If this
283 : insn is the earlier than I2 or I3, combine should rescan starting at
284 : that location. */
285 :
286 : static rtx_insn *added_links_insn;
287 :
288 : /* And similarly, for notes. */
289 :
290 : static rtx_insn *added_notes_insn;
291 :
292 : /* Basic block in which we are performing combines. */
293 : static basic_block this_basic_block;
294 : static bool optimize_this_for_speed_p;
295 :
296 :
297 : /* Length of the currently allocated uid_insn_cost array. */
298 :
299 : static int max_uid_known;
300 :
301 : /* The following array records the insn_cost for every insn
302 : in the instruction stream. */
303 :
304 : static int *uid_insn_cost;
305 :
306 : /* The following array records the LOG_LINKS for every insn in the
307 : instruction stream as struct insn_link pointers. */
308 :
309 : struct insn_link {
310 : rtx_insn *insn;
311 : unsigned int regno;
312 : int insn_count;
313 : struct insn_link *next;
314 : };
315 :
316 : static struct insn_link **uid_log_links;
317 :
318 : static inline int
319 783581026 : insn_uid_check (const rtx_insn *insn)
320 : {
321 783581026 : int uid = INSN_UID (insn);
322 783581026 : gcc_checking_assert (uid <= max_uid_known);
323 783581026 : return uid;
324 : }
325 :
326 : #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
327 : #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
328 :
329 : #define FOR_EACH_LOG_LINK(L, INSN) \
330 : for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
331 :
332 : /* Links for LOG_LINKS are allocated from this obstack. */
333 :
334 : static struct obstack insn_link_obstack;
335 :
336 : /* Allocate a link. */
337 :
338 : static inline struct insn_link *
339 39261369 : alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
340 : {
341 39261369 : struct insn_link *l
342 39261369 : = (struct insn_link *) obstack_alloc (&insn_link_obstack,
343 : sizeof (struct insn_link));
344 39261369 : l->insn = insn;
345 39261369 : l->regno = regno;
346 39261369 : l->insn_count = 0;
347 39261369 : l->next = next;
348 39261369 : return l;
349 : }
350 :
351 : /* Incremented for each basic block. */
352 :
353 : static int label_tick;
354 :
355 : /* Reset to label_tick for each extended basic block in scanning order. */
356 :
357 : static int label_tick_ebb_start;
358 :
359 : /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
360 : largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
361 :
362 : static scalar_int_mode nonzero_bits_mode;
363 :
364 : /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
365 : be safely used. It is zero while computing them and after combine has
366 : completed. This former test prevents propagating values based on
367 : previously set values, which can be incorrect if a variable is modified
368 : in a loop. */
369 :
370 : static int nonzero_sign_valid;
371 :
372 :
373 : /* Record one modification to rtl structure
374 : to be undone by storing old_contents into *where. */
375 :
376 : enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
377 :
378 : struct undo
379 : {
380 : struct undo *next;
381 : enum undo_kind kind;
382 : union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
383 : union { rtx *r; int *i; int regno; struct insn_link **l; } where;
384 : };
385 :
386 : /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
387 : num_undo says how many are currently recorded.
388 :
389 : other_insn is nonzero if we have modified some other insn in the process
390 : of working on subst_insn. It must be verified too. */
391 :
392 : struct undobuf
393 : {
394 : struct undo *undos;
395 : struct undo *frees;
396 : rtx_insn *other_insn;
397 : };
398 :
399 : static struct undobuf undobuf;
400 :
401 : /* Number of times the pseudo being substituted for
402 : was found and replaced. */
403 :
404 : static int n_occurrences;
405 :
406 : static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
407 : scalar_int_mode,
408 : unsigned HOST_WIDE_INT *);
409 : static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
410 : scalar_int_mode,
411 : unsigned int *);
412 : static void do_SUBST (rtx *, rtx);
413 : static void do_SUBST_INT (int *, int);
414 : static void init_reg_last (void);
415 : static void setup_incoming_promotions (rtx_insn *);
416 : static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
417 : static bool cant_combine_insn_p (rtx_insn *);
418 : static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
419 : rtx_insn *, rtx_insn *, rtx *, rtx *);
420 : static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
421 : bool, bool, rtx *);
422 : static bool contains_muldiv (rtx);
423 : static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
424 : bool *, rtx_insn *);
425 : static void undo_all (void);
426 : static void undo_commit (void);
427 : static rtx *find_split_point (rtx *, rtx_insn *, bool);
428 : static rtx subst (rtx, rtx, rtx, bool, bool, bool);
429 : static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
430 : static rtx simplify_if_then_else (rtx);
431 : static rtx simplify_set (rtx);
432 : static rtx simplify_logical (rtx);
433 : static rtx expand_compound_operation (rtx);
434 : static const_rtx expand_field_assignment (const_rtx);
435 : static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
436 : unsigned HOST_WIDE_INT, bool, bool, bool);
437 : static int get_pos_from_mask (unsigned HOST_WIDE_INT,
438 : unsigned HOST_WIDE_INT *);
439 : static rtx canon_reg_for_combine (rtx, rtx);
440 : static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
441 : scalar_int_mode, unsigned HOST_WIDE_INT, bool);
442 : static rtx force_to_mode (rtx, machine_mode,
443 : unsigned HOST_WIDE_INT, bool);
444 : static rtx if_then_else_cond (rtx, rtx *, rtx *);
445 : static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
446 : static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
447 : static rtx make_field_assignment (rtx);
448 : static rtx apply_distributive_law (rtx);
449 : static rtx distribute_and_simplify_rtx (rtx, int);
450 : static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
451 : unsigned HOST_WIDE_INT);
452 : static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
453 : unsigned HOST_WIDE_INT);
454 : static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
455 : HOST_WIDE_INT, machine_mode, bool *);
456 : static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
457 : static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
458 : int);
459 : static int recog_for_combine (rtx *, rtx_insn *, rtx *, unsigned = 0, unsigned = 0);
460 : static rtx gen_lowpart_for_combine (machine_mode, rtx);
461 : static rtx gen_lowpart_for_combine_no_emit (machine_mode, rtx);
462 : static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
463 : rtx *, rtx *);
464 : static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
465 : static void update_table_tick (rtx);
466 : static void record_value_for_reg (rtx, rtx_insn *, rtx);
467 : static void check_promoted_subreg (rtx_insn *, rtx);
468 : static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
469 : static void record_dead_and_set_regs (rtx_insn *);
470 : static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
471 : static rtx get_last_value (const_rtx);
472 : static void reg_dead_at_p_1 (rtx, const_rtx, void *);
473 : static bool reg_dead_at_p (rtx, rtx_insn *);
474 : static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
475 : static bool reg_bitfield_target_p (rtx, rtx);
476 : static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
477 : rtx, rtx, rtx);
478 : static void distribute_links (struct insn_link *, rtx_insn * = nullptr,
479 : int limit = INT_MAX);
480 : static void mark_used_regs_combine (rtx);
481 : static void record_promoted_value (rtx_insn *, rtx);
482 : static bool unmentioned_reg_p (rtx, rtx);
483 : static void record_truncated_values (rtx *, void *);
484 : static bool reg_truncated_to_mode (machine_mode, const_rtx);
485 : static rtx gen_lowpart_or_truncate (machine_mode, rtx);
486 :
487 :
488 : /* It is not safe to use ordinary gen_lowpart in combine.
489 : See comments in gen_lowpart_for_combine. */
490 : #undef RTL_HOOKS_GEN_LOWPART
491 : #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
492 :
493 : /* Our implementation of gen_lowpart never emits a new pseudo. */
494 : #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
495 : #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine_no_emit
496 :
497 : #undef RTL_HOOKS_REG_NONZERO_REG_BITS
498 : #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
499 :
500 : #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
501 : #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
502 :
503 : #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
504 : #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
505 :
506 : static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
507 :
508 :
509 : /* Convenience wrapper for the canonicalize_comparison target hook.
510 : Target hooks cannot use enum rtx_code. */
511 : static inline void
512 25418812 : target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
513 : bool op0_preserve_value)
514 : {
515 25418812 : int code_int = (int)*code;
516 25418812 : targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
517 25418812 : *code = (enum rtx_code)code_int;
518 : }
519 :
520 : /* Try to split PATTERN found in INSN. This returns NULL_RTX if
521 : PATTERN cannot be split. Otherwise, it returns an insn sequence.
522 : Updates OLD_NREGS with the max number of regs before the split
523 : and NEW_NREGS after the split.
524 : This is a wrapper around split_insns which ensures that the
525 : reg_stat vector is made larger if the splitter creates a new
526 : register. */
527 :
528 : static rtx_insn *
529 12159128 : combine_split_insns (rtx pattern, rtx_insn *insn,
530 : unsigned int *old_nregs,
531 : unsigned int *new_regs)
532 : {
533 12159128 : rtx_insn *ret;
534 12159128 : unsigned int nregs;
535 12159128 : *old_nregs = max_reg_num ();
536 12159128 : ret = split_insns (pattern, insn);
537 12159128 : *new_regs = nregs = max_reg_num ();
538 24318256 : if (nregs > reg_stat.length ())
539 2276 : reg_stat.safe_grow_cleared (nregs, true);
540 12159128 : return ret;
541 : }
542 :
543 : /* This is used by find_single_use to locate an rtx in LOC that
544 : contains exactly one use of DEST, which is typically a REG.
545 : It returns a pointer to the innermost rtx expression
546 : containing DEST. Appearances of DEST that are being used to
547 : totally replace it are not counted. */
548 :
549 : static rtx *
550 33640606 : find_single_use_1 (rtx dest, rtx *loc)
551 : {
552 40724077 : rtx x = *loc;
553 40724077 : enum rtx_code code = GET_CODE (x);
554 40724077 : rtx *result = NULL;
555 40724077 : rtx *this_result;
556 40724077 : int i;
557 40724077 : const char *fmt;
558 :
559 40724077 : switch (code)
560 : {
561 : case CONST:
562 : case LABEL_REF:
563 : case SYMBOL_REF:
564 : CASE_CONST_ANY:
565 : case CLOBBER:
566 : return 0;
567 :
568 7038377 : case SET:
569 : /* If the destination is anything other than PC, a REG or a SUBREG
570 : of a REG that occupies all of the REG, the insn uses DEST if
571 : it is mentioned in the destination or the source. Otherwise, we
572 : need just check the source. */
573 7038377 : if (GET_CODE (SET_DEST (x)) != PC
574 7038377 : && !REG_P (SET_DEST (x))
575 7040898 : && ! (GET_CODE (SET_DEST (x)) == SUBREG
576 2521 : && REG_P (SUBREG_REG (SET_DEST (x)))
577 2521 : && !read_modify_subreg_p (SET_DEST (x))))
578 : break;
579 :
580 7036998 : return find_single_use_1 (dest, &SET_SRC (x));
581 :
582 46473 : case MEM:
583 46473 : case SUBREG:
584 46473 : return find_single_use_1 (dest, &XEXP (x, 0));
585 :
586 : default:
587 : break;
588 : }
589 :
590 : /* If it wasn't one of the common cases above, check each expression and
591 : vector of this code. Look for a unique usage of DEST. */
592 :
593 20264465 : fmt = GET_RTX_FORMAT (code);
594 54184683 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
595 : {
596 33927687 : if (fmt[i] == 'e')
597 : {
598 33541279 : if (dest == XEXP (x, i)
599 33541279 : || (REG_P (dest) && REG_P (XEXP (x, i))
600 878810 : && REGNO (dest) == REGNO (XEXP (x, i))))
601 : this_result = loc;
602 : else
603 26500109 : this_result = find_single_use_1 (dest, &XEXP (x, i));
604 :
605 33541279 : if (result == NULL)
606 : result = this_result;
607 40839 : else if (this_result)
608 : /* Duplicate usage. */
609 : return NULL;
610 : }
611 386408 : else if (fmt[i] == 'E')
612 : {
613 51546 : int j;
614 :
615 156906 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
616 : {
617 109457 : if (XVECEXP (x, i, j) == dest
618 109457 : || (REG_P (dest)
619 109457 : && REG_P (XVECEXP (x, i, j))
620 4579 : && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
621 : this_result = loc;
622 : else
623 109457 : this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
624 :
625 109457 : if (result == NULL)
626 : result = this_result;
627 17053 : else if (this_result)
628 : return NULL;
629 : }
630 : }
631 : }
632 :
633 : return result;
634 : }
635 :
636 :
637 : /* See if DEST, produced in INSN, is used only a single time in the
638 : sequel. If so, return a pointer to the innermost rtx expression in which
639 : it is used.
640 :
641 : If PLOC is nonzero, *PLOC is set to the insn containing the single use.
642 :
643 : Otherwise, we find the single use by finding an insn that has a
644 : LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
645 : only referenced once in that insn, we know that it must be the first
646 : and last insn referencing DEST. */
647 :
648 : static rtx *
649 7653694 : find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
650 : {
651 7653694 : basic_block bb;
652 7653694 : rtx_insn *next;
653 7653694 : rtx *result;
654 7653694 : struct insn_link *link;
655 :
656 7653694 : if (!REG_P (dest))
657 : return 0;
658 :
659 7653694 : bb = BLOCK_FOR_INSN (insn);
660 10583575 : for (next = NEXT_INSN (insn);
661 10583575 : next && BLOCK_FOR_INSN (next) == bb;
662 2929881 : next = NEXT_INSN (next))
663 9960921 : if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
664 : {
665 9383634 : FOR_EACH_LOG_LINK (link, next)
666 8337642 : if (link->insn == insn && link->regno == REGNO (dest))
667 : break;
668 :
669 8077032 : if (link)
670 : {
671 7031040 : result = find_single_use_1 (dest, &PATTERN (next));
672 7031040 : if (ploc)
673 7031039 : *ploc = next;
674 : return result;
675 : }
676 : }
677 :
678 : return 0;
679 : }
680 :
681 : /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 : insn. The substitution can be undone by undo_all. If INTO is already
683 : set to NEWVAL, do not record this change. Because computing NEWVAL might
684 : also call SUBST, we have to compute it before we put anything into
685 : the undo table. */
686 :
687 : static void
688 769351515 : do_SUBST (rtx *into, rtx newval)
689 : {
690 769351515 : struct undo *buf;
691 769351515 : rtx oldval = *into;
692 :
693 769351515 : if (oldval == newval)
694 : return;
695 :
696 : /* We'd like to catch as many invalid transformations here as
697 : possible. Unfortunately, there are way too many mode changes
698 : that are perfectly valid, so we'd waste too much effort for
699 : little gain doing the checks here. Focus on catching invalid
700 : transformations involving integer constants. */
701 97374065 : if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 59001952 : && CONST_INT_P (newval))
703 : {
704 : /* Sanity check that we're replacing oldval with a CONST_INT
705 : that is a valid sign-extension for the original mode. */
706 1842575 : gcc_assert (INTVAL (newval)
707 : == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
708 :
709 : /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 : CONST_INT is not valid, because after the replacement, the
711 : original mode would be gone. Unfortunately, we can't tell
712 : when do_SUBST is called to replace the operand thereof, so we
713 : perform this test on oldval instead, checking whether an
714 : invalid replacement took place before we got here. */
715 1842575 : gcc_assert (!(GET_CODE (oldval) == SUBREG
716 : && CONST_INT_P (SUBREG_REG (oldval))));
717 1842575 : gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 : && CONST_INT_P (XEXP (oldval, 0))));
719 : }
720 :
721 97374065 : if (undobuf.frees)
722 93190198 : buf = undobuf.frees, undobuf.frees = buf->next;
723 : else
724 4183867 : buf = XNEW (struct undo);
725 :
726 97374065 : buf->kind = UNDO_RTX;
727 97374065 : buf->where.r = into;
728 97374065 : buf->old_contents.r = oldval;
729 97374065 : *into = newval;
730 :
731 97374065 : buf->next = undobuf.undos, undobuf.undos = buf;
732 : }
733 :
734 : #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
735 :
736 : /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 : for the value of a HOST_WIDE_INT value (including CONST_INT) is
738 : not safe. */
739 :
740 : static void
741 16350388 : do_SUBST_INT (int *into, int newval)
742 : {
743 16350388 : struct undo *buf;
744 16350388 : int oldval = *into;
745 :
746 16350388 : if (oldval == newval)
747 : return;
748 :
749 7055713 : if (undobuf.frees)
750 6522189 : buf = undobuf.frees, undobuf.frees = buf->next;
751 : else
752 533524 : buf = XNEW (struct undo);
753 :
754 7055713 : buf->kind = UNDO_INT;
755 7055713 : buf->where.i = into;
756 7055713 : buf->old_contents.i = oldval;
757 7055713 : *into = newval;
758 :
759 7055713 : buf->next = undobuf.undos, undobuf.undos = buf;
760 : }
761 :
762 : #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
763 :
764 : /* Similar to SUBST, but just substitute the mode. This is used when
765 : changing the mode of a pseudo-register, so that any other
766 : references to the entry in the regno_reg_rtx array will change as
767 : well. */
768 :
769 : static void
770 1435549 : subst_mode (int regno, machine_mode newval)
771 : {
772 1435549 : struct undo *buf;
773 1435549 : rtx reg = regno_reg_rtx[regno];
774 1435549 : machine_mode oldval = GET_MODE (reg);
775 :
776 1435549 : if (oldval == newval)
777 : return;
778 :
779 1435549 : if (undobuf.frees)
780 1359037 : buf = undobuf.frees, undobuf.frees = buf->next;
781 : else
782 76512 : buf = XNEW (struct undo);
783 :
784 1435549 : buf->kind = UNDO_MODE;
785 1435549 : buf->where.regno = regno;
786 1435549 : buf->old_contents.m = oldval;
787 1435549 : adjust_reg_mode (reg, newval);
788 :
789 1435549 : buf->next = undobuf.undos, undobuf.undos = buf;
790 : }
791 :
792 : /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
793 :
794 : static void
795 71742 : do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
796 : {
797 71742 : struct undo *buf;
798 71742 : struct insn_link * oldval = *into;
799 :
800 71742 : if (oldval == newval)
801 : return;
802 :
803 71742 : if (undobuf.frees)
804 68562 : buf = undobuf.frees, undobuf.frees = buf->next;
805 : else
806 3180 : buf = XNEW (struct undo);
807 :
808 71742 : buf->kind = UNDO_LINKS;
809 71742 : buf->where.l = into;
810 71742 : buf->old_contents.l = oldval;
811 71742 : *into = newval;
812 :
813 71742 : buf->next = undobuf.undos, undobuf.undos = buf;
814 : }
815 :
816 : #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
817 :
818 : /* Subroutine of try_combine. Determine whether the replacement patterns
819 : NEWPAT, NEWI2PAT and NEWOTHERPAT are more expensive according to insn_cost
820 : than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
821 : that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
822 : undobuf.other_insn may also both be NULL_RTX. Return false if the cost
823 : of all the instructions can be estimated and the replacements are more
824 : expensive than the original sequence. */
825 :
826 : static bool
827 4322049 : combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
828 : rtx newpat, rtx newi2pat, rtx newotherpat,
829 : int insn_code, int i2_code, int other_code)
830 : {
831 4322049 : int i0_cost, i1_cost, i2_cost, i3_cost;
832 4322049 : int new_i2_cost, new_i3_cost;
833 4322049 : int old_cost, new_cost;
834 :
835 : /* Lookup the original insn_costs. */
836 4322049 : i2_cost = INSN_COST (i2);
837 4322049 : i3_cost = INSN_COST (i3);
838 :
839 4322049 : if (i1)
840 : {
841 121523 : i1_cost = INSN_COST (i1);
842 121523 : if (i0)
843 : {
844 4999 : i0_cost = INSN_COST (i0);
845 4866 : old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
846 9856 : ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
847 : }
848 : else
849 : {
850 111935 : old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
851 228457 : ? i1_cost + i2_cost + i3_cost : 0);
852 : i0_cost = 0;
853 : }
854 : }
855 : else
856 : {
857 4200526 : old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
858 : i1_cost = i0_cost = 0;
859 : }
860 :
861 : /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
862 : correct that. */
863 4322049 : if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
864 2235 : old_cost -= i1_cost;
865 :
866 :
867 : /* Calculate the replacement insn_costs. */
868 4322049 : rtx tmp = PATTERN (i3);
869 4322049 : PATTERN (i3) = newpat;
870 4322049 : int tmpi = INSN_CODE (i3);
871 4322049 : INSN_CODE (i3) = insn_code;
872 4322049 : new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
873 4322049 : PATTERN (i3) = tmp;
874 4322049 : INSN_CODE (i3) = tmpi;
875 4322049 : if (newi2pat)
876 : {
877 223303 : tmp = PATTERN (i2);
878 223303 : PATTERN (i2) = newi2pat;
879 223303 : tmpi = INSN_CODE (i2);
880 223303 : INSN_CODE (i2) = i2_code;
881 223303 : new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
882 223303 : PATTERN (i2) = tmp;
883 223303 : INSN_CODE (i2) = tmpi;
884 223303 : new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
885 223303 : ? new_i2_cost + new_i3_cost : 0;
886 : }
887 : else
888 : {
889 : new_cost = new_i3_cost;
890 : new_i2_cost = 0;
891 : }
892 :
893 4322049 : if (undobuf.other_insn)
894 : {
895 223884 : int old_other_cost, new_other_cost;
896 :
897 223884 : old_other_cost = INSN_COST (undobuf.other_insn);
898 223884 : tmp = PATTERN (undobuf.other_insn);
899 223884 : PATTERN (undobuf.other_insn) = newotherpat;
900 223884 : tmpi = INSN_CODE (undobuf.other_insn);
901 223884 : INSN_CODE (undobuf.other_insn) = other_code;
902 223884 : new_other_cost = insn_cost (undobuf.other_insn,
903 : optimize_this_for_speed_p);
904 223884 : PATTERN (undobuf.other_insn) = tmp;
905 223884 : INSN_CODE (undobuf.other_insn) = tmpi;
906 223884 : if (old_other_cost > 0 && new_other_cost > 0)
907 : {
908 223884 : old_cost += old_other_cost;
909 223884 : new_cost += new_other_cost;
910 : }
911 : else
912 : old_cost = 0;
913 : }
914 :
915 : /* Disallow this combination if both new_cost and old_cost are greater than
916 : zero, and new_cost is greater than old cost. */
917 4322049 : bool reject = old_cost > 0 && new_cost > old_cost;
918 :
919 4322049 : if (dump_file)
920 : {
921 492 : fprintf (dump_file, "%s combination of insns ",
922 : reject ? "rejecting" : "allowing");
923 248 : if (i0)
924 0 : fprintf (dump_file, "%d, ", INSN_UID (i0));
925 248 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
926 1 : fprintf (dump_file, "%d, ", INSN_UID (i1));
927 248 : fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
928 :
929 248 : fprintf (dump_file, "original costs ");
930 248 : if (i0)
931 0 : fprintf (dump_file, "%d + ", i0_cost);
932 248 : if (i1 && INSN_UID (i1) != INSN_UID (i2))
933 1 : fprintf (dump_file, "%d + ", i1_cost);
934 248 : fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
935 :
936 248 : if (newi2pat)
937 23 : fprintf (dump_file, "replacement costs %d + %d = %d\n",
938 : new_i2_cost, new_i3_cost, new_cost);
939 : else
940 225 : fprintf (dump_file, "replacement cost %d\n", new_cost);
941 : }
942 :
943 4322049 : if (reject)
944 : return false;
945 :
946 : /* Update the uid_insn_cost array with the replacement costs. */
947 4104409 : INSN_COST (i2) = new_i2_cost;
948 4104409 : INSN_COST (i3) = new_i3_cost;
949 4104409 : if (i1)
950 : {
951 102324 : INSN_COST (i1) = 0;
952 102324 : if (i0)
953 4627 : INSN_COST (i0) = 0;
954 : }
955 :
956 : return true;
957 : }
958 :
959 :
960 : /* Delete any insns that copy a register to itself.
961 : Return true if the CFG was changed. */
962 :
963 : static bool
964 1025352 : delete_noop_moves (void)
965 : {
966 1025352 : rtx_insn *insn, *next;
967 1025352 : basic_block bb;
968 :
969 1025352 : bool edges_deleted = false;
970 :
971 11691335 : FOR_EACH_BB_FN (bb, cfun)
972 : {
973 145603798 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
974 : {
975 134937815 : next = NEXT_INSN (insn);
976 134937815 : if (INSN_P (insn) && noop_move_p (insn))
977 : {
978 6427 : if (dump_file)
979 0 : fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
980 :
981 6427 : edges_deleted |= delete_insn_and_edges (insn);
982 : }
983 : }
984 : }
985 :
986 1025352 : return edges_deleted;
987 : }
988 :
989 :
990 : /* Return false if we do not want to (or cannot) combine DEF. */
991 : static bool
992 43171303 : can_combine_def_p (df_ref def)
993 : {
994 : /* Do not consider if it is pre/post modification in MEM. */
995 43171303 : if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
996 : return false;
997 :
998 41494028 : unsigned int regno = DF_REF_REGNO (def);
999 :
1000 : /* Do not combine frame pointer adjustments. */
1001 41494028 : if ((regno == FRAME_POINTER_REGNUM
1002 0 : && (!reload_completed || frame_pointer_needed))
1003 2062 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1004 41494028 : && regno == HARD_FRAME_POINTER_REGNUM
1005 : && (!reload_completed || frame_pointer_needed))
1006 41491966 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1007 0 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
1008 2062 : return false;
1009 :
1010 : return true;
1011 : }
1012 :
1013 : /* Return false if we do not want to (or cannot) combine USE. */
1014 : static bool
1015 79966715 : can_combine_use_p (df_ref use)
1016 : {
1017 : /* Do not consider the usage of the stack pointer by function call. */
1018 0 : if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1019 0 : return false;
1020 :
1021 : return true;
1022 : }
1023 :
1024 : /* Fill in log links field for all insns. */
1025 :
1026 : static void
1027 1025352 : create_log_links (void)
1028 : {
1029 1025352 : basic_block bb;
1030 1025352 : rtx_insn **next_use;
1031 1025352 : rtx_insn *insn;
1032 1025352 : df_ref def, use;
1033 :
1034 1025352 : next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1035 :
1036 : /* Pass through each block from the end, recording the uses of each
1037 : register and establishing log links when def is encountered.
1038 : Note that we do not clear next_use array in order to save time,
1039 : so we have to test whether the use is in the same basic block as def.
1040 :
1041 : There are a few cases below when we do not consider the definition or
1042 : usage -- these are taken from original flow.c did. Don't ask me why it is
1043 : done this way; I don't know and if it works, I don't want to know. */
1044 :
1045 11691335 : FOR_EACH_BB_FN (bb, cfun)
1046 : {
1047 145587343 : FOR_BB_INSNS_REVERSE (bb, insn)
1048 : {
1049 134921360 : if (!NONDEBUG_INSN_P (insn))
1050 71352873 : continue;
1051 :
1052 : /* Log links are created only once. */
1053 63568487 : gcc_assert (!LOG_LINKS (insn));
1054 :
1055 524972026 : FOR_EACH_INSN_DEF (def, insn)
1056 : {
1057 461403539 : unsigned int regno = DF_REF_REGNO (def);
1058 461403539 : rtx_insn *use_insn;
1059 :
1060 461403539 : if (!next_use[regno])
1061 418232236 : continue;
1062 :
1063 43171303 : if (!can_combine_def_p (def))
1064 1679337 : continue;
1065 :
1066 41491966 : use_insn = next_use[regno];
1067 41491966 : next_use[regno] = NULL;
1068 :
1069 41491966 : if (BLOCK_FOR_INSN (use_insn) != bb)
1070 2318806 : continue;
1071 :
1072 : /* flow.c claimed:
1073 :
1074 : We don't build a LOG_LINK for hard registers contained
1075 : in ASM_OPERANDs. If these registers get replaced,
1076 : we might wind up changing the semantics of the insn,
1077 : even if reload can make what appear to be valid
1078 : assignments later. */
1079 39174012 : if (regno < FIRST_PSEUDO_REGISTER
1080 39173160 : && asm_noperands (PATTERN (use_insn)) >= 0)
1081 852 : continue;
1082 :
1083 : /* Don't add duplicate links between instructions. */
1084 39172308 : struct insn_link *links;
1085 52520903 : FOR_EACH_LOG_LINK (links, use_insn)
1086 13348595 : if (insn == links->insn && regno == links->regno)
1087 : break;
1088 :
1089 39172308 : if (!links)
1090 39172308 : LOG_LINKS (use_insn)
1091 78344616 : = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1092 : }
1093 :
1094 143535202 : FOR_EACH_INSN_USE (use, insn)
1095 155077161 : if (can_combine_use_p (use))
1096 75110446 : next_use[DF_REF_REGNO (use)] = insn;
1097 : }
1098 : }
1099 :
1100 1025352 : free (next_use);
1101 1025352 : }
1102 :
1103 : /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 : true if we found a LOG_LINK that proves that A feeds B. This only works
1105 : if there are no instructions between A and B which could have a link
1106 : depending on A, since in that case we would not record a link for B. */
1107 :
1108 : static bool
1109 13407855 : insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1110 : {
1111 13407855 : struct insn_link *links;
1112 16924240 : FOR_EACH_LOG_LINK (links, b)
1113 14251501 : if (links->insn == a)
1114 : return true;
1115 : return false;
1116 : }
1117 :
1118 : /* Main entry point for combiner. F is the first insn of the function.
1119 : NREGS is the first unused pseudo-reg number.
1120 :
1121 : Return nonzero if the CFG was changed (e.g. if the combiner has
1122 : turned an indirect jump instruction into a direct jump). */
1123 : static bool
1124 1070192 : combine_instructions (rtx_insn *f, unsigned int nregs)
1125 : {
1126 1070192 : rtx_insn *insn, *next;
1127 1070192 : struct insn_link *links, *nextlinks;
1128 1070192 : rtx_insn *first;
1129 1070192 : basic_block last_bb;
1130 :
1131 1070192 : bool new_direct_jump_p = false;
1132 :
1133 3201801 : for (first = f; first && !NONDEBUG_INSN_P (first); )
1134 2131609 : first = NEXT_INSN (first);
1135 1070192 : if (!first)
1136 : return false;
1137 :
1138 1025352 : combine_attempts = 0;
1139 1025352 : combine_merges = 0;
1140 1025352 : combine_extras = 0;
1141 1025352 : combine_successes = 0;
1142 :
1143 1025352 : rtl_hooks = combine_rtl_hooks;
1144 :
1145 1025352 : reg_stat.safe_grow_cleared (nregs, true);
1146 :
1147 1025352 : init_recog_no_volatile ();
1148 :
1149 : /* Allocate array for insn info. */
1150 1025352 : max_uid_known = get_max_uid ();
1151 1025352 : uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1152 1025352 : uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1153 1025352 : gcc_obstack_init (&insn_link_obstack);
1154 :
1155 1025352 : nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1156 :
1157 : /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1158 : problems when, for example, we have j <<= 1 in a loop. */
1159 :
1160 1025352 : nonzero_sign_valid = 0;
1161 1025352 : label_tick = label_tick_ebb_start = 1;
1162 :
1163 : /* Scan all SETs and see if we can deduce anything about what
1164 : bits are known to be zero for some registers and how many copies
1165 : of the sign bit are known to exist for those registers.
1166 :
1167 : Also set any known values so that we can use it while searching
1168 : for what bits are known to be set. */
1169 :
1170 1025352 : setup_incoming_promotions (first);
1171 : /* Allow the entry block and the first block to fall into the same EBB.
1172 : Conceptually the incoming promotions are assigned to the entry block. */
1173 1025352 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1174 :
1175 1025352 : create_log_links ();
1176 11691335 : FOR_EACH_BB_FN (this_basic_block, cfun)
1177 : {
1178 10665983 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1179 10665983 : last_call_luid = 0;
1180 10665983 : mem_last_set = -1;
1181 :
1182 10665983 : label_tick++;
1183 10665983 : if (!single_pred_p (this_basic_block)
1184 10665983 : || single_pred (this_basic_block) != last_bb)
1185 5115672 : label_tick_ebb_start = label_tick;
1186 10665983 : last_bb = this_basic_block;
1187 :
1188 145587343 : FOR_BB_INSNS (this_basic_block, insn)
1189 134921360 : if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1190 : {
1191 118010482 : rtx links;
1192 :
1193 118010482 : subst_low_luid = DF_INSN_LUID (insn);
1194 118010482 : subst_insn = insn;
1195 :
1196 118010482 : note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1197 118010482 : record_dead_and_set_regs (insn);
1198 :
1199 118010482 : if (AUTO_INC_DEC)
1200 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1201 : if (REG_NOTE_KIND (links) == REG_INC)
1202 : set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1203 : insn);
1204 :
1205 : /* Record the current insn_cost of this instruction. */
1206 118010482 : INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1207 118010482 : if (dump_file)
1208 : {
1209 1695 : fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1210 1695 : dump_insn_slim (dump_file, insn);
1211 : }
1212 : }
1213 : }
1214 :
1215 1025352 : nonzero_sign_valid = 1;
1216 :
1217 : /* Now scan all the insns in forward order. */
1218 1025352 : label_tick = label_tick_ebb_start = 1;
1219 1025352 : init_reg_last ();
1220 1025352 : setup_incoming_promotions (first);
1221 1025352 : last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1222 1025352 : int max_combine = param_max_combine_insns;
1223 :
1224 11691335 : FOR_EACH_BB_FN (this_basic_block, cfun)
1225 : {
1226 10665983 : rtx_insn *last_combined_insn = NULL;
1227 :
1228 : /* Ignore instruction combination in basic blocks that are going to
1229 : be removed as unreachable anyway. See PR82386. */
1230 10665983 : if (EDGE_COUNT (this_basic_block->preds) == 0)
1231 1661 : continue;
1232 :
1233 10664322 : optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1234 10664322 : last_call_luid = 0;
1235 10664322 : mem_last_set = -1;
1236 :
1237 10664322 : label_tick++;
1238 10664322 : if (!single_pred_p (this_basic_block)
1239 10664322 : || single_pred (this_basic_block) != last_bb)
1240 5115301 : label_tick_ebb_start = label_tick;
1241 10664322 : last_bb = this_basic_block;
1242 :
1243 10664322 : rtl_profile_for_bb (this_basic_block);
1244 10664322 : for (insn = BB_HEAD (this_basic_block);
1245 150225925 : insn != NEXT_INSN (BB_END (this_basic_block));
1246 135457194 : insn = next ? next : NEXT_INSN (insn))
1247 : {
1248 139561603 : next = 0;
1249 139561603 : if (!NONDEBUG_INSN_P (insn))
1250 71594993 : continue;
1251 :
1252 : while (last_combined_insn
1253 67968395 : && (!NONDEBUG_INSN_P (last_combined_insn)
1254 57493510 : || last_combined_insn->deleted ()))
1255 1785 : last_combined_insn = PREV_INSN (last_combined_insn);
1256 67966610 : if (last_combined_insn == NULL_RTX
1257 57492926 : || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1258 125459331 : || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1259 : last_combined_insn = insn;
1260 :
1261 : /* See if we know about function return values before this
1262 : insn based upon SUBREG flags. */
1263 67966610 : check_promoted_subreg (insn, PATTERN (insn));
1264 :
1265 : /* See if we can find hardregs and subreg of pseudos in
1266 : narrower modes. This could help turning TRUNCATEs
1267 : into SUBREGs. */
1268 67966610 : note_uses (&PATTERN (insn), record_truncated_values, NULL);
1269 :
1270 : /* Try this insn with each insn it links back to. */
1271 :
1272 106199094 : FOR_EACH_LOG_LINK (links, insn)
1273 42209837 : if ((next = try_combine (insn, links->insn, NULL,
1274 : NULL, &new_direct_jump_p,
1275 : last_combined_insn)) != 0)
1276 : {
1277 3977353 : statistics_counter_event (cfun, "two-insn combine", 1);
1278 3977353 : goto retry;
1279 : }
1280 :
1281 : /* Try each sequence of three linked insns ending with this one. */
1282 :
1283 63989257 : if (max_combine >= 3)
1284 101617108 : FOR_EACH_LOG_LINK (links, insn)
1285 : {
1286 37809838 : rtx_insn *link = links->insn;
1287 :
1288 : /* If the linked insn has been replaced by a note, then there
1289 : is no point in pursuing this chain any further. */
1290 37809838 : if (NOTE_P (link))
1291 227 : continue;
1292 :
1293 56291131 : FOR_EACH_LOG_LINK (nextlinks, link)
1294 18561550 : if ((next = try_combine (insn, link, nextlinks->insn,
1295 : NULL, &new_direct_jump_p,
1296 : last_combined_insn)) != 0)
1297 : {
1298 80030 : statistics_counter_event (cfun, "three-insn combine", 1);
1299 80030 : goto retry;
1300 : }
1301 : }
1302 :
1303 : /* Try combining an insn with two different insns whose results it
1304 : uses. */
1305 63807270 : if (max_combine >= 3)
1306 101500010 : FOR_EACH_LOG_LINK (links, insn)
1307 50737480 : for (nextlinks = links->next; nextlinks;
1308 13029518 : nextlinks = nextlinks->next)
1309 13044740 : if ((next = try_combine (insn, links->insn,
1310 : nextlinks->insn, NULL,
1311 : &new_direct_jump_p,
1312 : last_combined_insn)) != 0)
1313 :
1314 : {
1315 15222 : statistics_counter_event (cfun, "three-insn combine", 1);
1316 15222 : goto retry;
1317 : }
1318 :
1319 : /* Try four-instruction combinations. */
1320 63792048 : if (max_combine >= 4)
1321 101476946 : FOR_EACH_LOG_LINK (links, insn)
1322 : {
1323 37689468 : struct insn_link *next1;
1324 37689468 : rtx_insn *link = links->insn;
1325 :
1326 : /* If the linked insn has been replaced by a note, then there
1327 : is no point in pursuing this chain any further. */
1328 37689468 : if (NOTE_P (link))
1329 226 : continue;
1330 :
1331 56147491 : FOR_EACH_LOG_LINK (next1, link)
1332 : {
1333 18459651 : rtx_insn *link1 = next1->insn;
1334 18459651 : if (NOTE_P (link1))
1335 57 : continue;
1336 : /* I0 -> I1 -> I2 -> I3. */
1337 30185714 : FOR_EACH_LOG_LINK (nextlinks, link1)
1338 11727414 : if ((next = try_combine (insn, link, link1,
1339 : nextlinks->insn,
1340 : &new_direct_jump_p,
1341 : last_combined_insn)) != 0)
1342 : {
1343 1294 : statistics_counter_event (cfun, "four-insn combine", 1);
1344 1294 : goto retry;
1345 : }
1346 : /* I0, I1 -> I2, I2 -> I3. */
1347 22476055 : for (nextlinks = next1->next; nextlinks;
1348 4017755 : nextlinks = nextlinks->next)
1349 4017863 : if ((next = try_combine (insn, link, link1,
1350 : nextlinks->insn,
1351 : &new_direct_jump_p,
1352 : last_combined_insn)) != 0)
1353 : {
1354 108 : statistics_counter_event (cfun, "four-insn combine", 1);
1355 108 : goto retry;
1356 : }
1357 : }
1358 :
1359 50713933 : for (next1 = links->next; next1; next1 = next1->next)
1360 : {
1361 13029182 : rtx_insn *link1 = next1->insn;
1362 13029182 : if (NOTE_P (link1))
1363 8 : continue;
1364 : /* I0 -> I2; I1, I2 -> I3. */
1365 16472033 : FOR_EACH_LOG_LINK (nextlinks, link)
1366 3445764 : if ((next = try_combine (insn, link, link1,
1367 : nextlinks->insn,
1368 : &new_direct_jump_p,
1369 : last_combined_insn)) != 0)
1370 : {
1371 2905 : statistics_counter_event (cfun, "four-insn combine", 1);
1372 2905 : goto retry;
1373 : }
1374 : /* I0 -> I1; I1, I2 -> I3. */
1375 16770480 : FOR_EACH_LOG_LINK (nextlinks, link1)
1376 3744395 : if ((next = try_combine (insn, link, link1,
1377 : nextlinks->insn,
1378 : &new_direct_jump_p,
1379 : last_combined_insn)) != 0)
1380 : {
1381 184 : statistics_counter_event (cfun, "four-insn combine", 1);
1382 184 : goto retry;
1383 : }
1384 : }
1385 : }
1386 :
1387 : /* Try this insn with each REG_EQUAL note it links back to. */
1388 101598990 : FOR_EACH_LOG_LINK (links, insn)
1389 : {
1390 37736789 : rtx set, note;
1391 37736789 : rtx_insn *temp = links->insn;
1392 37736789 : if ((set = single_set (temp)) != 0
1393 37343263 : && (note = find_reg_equal_equiv_note (temp)) != 0
1394 2799663 : && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1395 2799663 : && ! side_effects_p (SET_SRC (set))
1396 : /* Avoid using a register that may already been marked
1397 : dead by an earlier instruction. */
1398 2799663 : && ! unmentioned_reg_p (note, SET_SRC (set))
1399 39110063 : && (GET_MODE (note) == VOIDmode
1400 26981 : ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1401 1346293 : : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1402 1346260 : && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1403 0 : || (GET_MODE (XEXP (SET_DEST (set), 0))
1404 : == GET_MODE (note))))))
1405 : {
1406 : /* Temporarily replace the set's source with the
1407 : contents of the REG_EQUAL note. The insn will
1408 : be deleted or recognized by try_combine. */
1409 1373224 : rtx orig_src = SET_SRC (set);
1410 1373224 : rtx orig_dest = SET_DEST (set);
1411 1373224 : if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1412 0 : SET_DEST (set) = XEXP (SET_DEST (set), 0);
1413 1373224 : SET_SRC (set) = note;
1414 1373224 : i2mod = temp;
1415 1373224 : i2mod_old_rhs = copy_rtx (orig_src);
1416 1373224 : i2mod_new_rhs = copy_rtx (note);
1417 1373224 : next = try_combine (insn, i2mod, NULL, NULL,
1418 : &new_direct_jump_p,
1419 : last_combined_insn);
1420 1373224 : i2mod = NULL;
1421 1373224 : if (next)
1422 : {
1423 27313 : statistics_counter_event (cfun, "insn-with-note combine", 1);
1424 27313 : goto retry;
1425 : }
1426 1345911 : INSN_CODE (temp) = -1;
1427 1345911 : SET_SRC (set) = orig_src;
1428 1345911 : SET_DEST (set) = orig_dest;
1429 : }
1430 : }
1431 :
1432 63862201 : if (!NOTE_P (insn))
1433 63862201 : record_dead_and_set_regs (insn);
1434 :
1435 139561603 : retry:
1436 139561603 : ;
1437 : }
1438 : }
1439 :
1440 1025352 : default_rtl_profile ();
1441 1025352 : clear_bb_flags ();
1442 :
1443 1025352 : if (purge_all_dead_edges ())
1444 1274 : new_direct_jump_p = true;
1445 1025352 : if (delete_noop_moves ())
1446 0 : new_direct_jump_p = true;
1447 :
1448 : /* Clean up. */
1449 1025352 : obstack_free (&insn_link_obstack, NULL);
1450 1025352 : free (uid_log_links);
1451 1025352 : free (uid_insn_cost);
1452 1025352 : reg_stat.release ();
1453 :
1454 1025352 : {
1455 1025352 : struct undo *undo, *next;
1456 5822435 : for (undo = undobuf.frees; undo; undo = next)
1457 : {
1458 4797083 : next = undo->next;
1459 4797083 : free (undo);
1460 : }
1461 1025352 : undobuf.frees = 0;
1462 : }
1463 :
1464 1025352 : statistics_counter_event (cfun, "attempts", combine_attempts);
1465 1025352 : statistics_counter_event (cfun, "merges", combine_merges);
1466 1025352 : statistics_counter_event (cfun, "extras", combine_extras);
1467 1025352 : statistics_counter_event (cfun, "successes", combine_successes);
1468 :
1469 1025352 : nonzero_sign_valid = 0;
1470 1025352 : rtl_hooks = general_rtl_hooks;
1471 :
1472 : /* Make recognizer allow volatile MEMs again. */
1473 1025352 : init_recog ();
1474 :
1475 1025352 : return new_direct_jump_p;
1476 : }
1477 :
1478 : /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1479 :
1480 : static void
1481 1025352 : init_reg_last (void)
1482 : {
1483 1025352 : unsigned int i;
1484 1025352 : reg_stat_type *p;
1485 :
1486 148347883 : FOR_EACH_VEC_ELT (reg_stat, i, p)
1487 147322531 : memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1488 1025352 : }
1489 :
1490 : /* Set up any promoted values for incoming argument registers. */
1491 :
1492 : static void
1493 2050704 : setup_incoming_promotions (rtx_insn *first)
1494 : {
1495 2050704 : tree arg;
1496 2050704 : bool strictly_local = false;
1497 :
1498 5551040 : for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 3500336 : arg = DECL_CHAIN (arg))
1500 : {
1501 3500336 : rtx x, reg = DECL_INCOMING_RTL (arg);
1502 3500336 : int uns1, uns3;
1503 3500336 : machine_mode mode1, mode2, mode3, mode4;
1504 :
1505 : /* Only continue if the incoming argument is in a register. */
1506 3500336 : if (!REG_P (reg))
1507 3500236 : continue;
1508 :
1509 : /* Determine, if possible, whether all call sites of the current
1510 : function lie within the current compilation unit. (This does
1511 : take into account the exporting of a function via taking its
1512 : address, and so forth.) */
1513 2757528 : strictly_local
1514 2757528 : = cgraph_node::local_info_node (current_function_decl)->local;
1515 :
1516 : /* The mode and signedness of the argument before any promotions happen
1517 : (equal to the mode of the pseudo holding it at that stage). */
1518 2757528 : mode1 = TYPE_MODE (TREE_TYPE (arg));
1519 2757528 : uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1520 :
1521 : /* The mode and signedness of the argument after any source language and
1522 : TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1523 2757528 : mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1524 2757528 : uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1525 :
1526 : /* The mode and signedness of the argument as it is actually passed,
1527 : see assign_parm_setup_reg in function.cc. */
1528 2757528 : mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1529 2757528 : TREE_TYPE (cfun->decl), 0);
1530 :
1531 : /* The mode of the register in which the argument is being passed. */
1532 2757528 : mode4 = GET_MODE (reg);
1533 :
1534 : /* Eliminate sign extensions in the callee when:
1535 : (a) A mode promotion has occurred; */
1536 2757528 : if (mode1 == mode3)
1537 2757428 : continue;
1538 : /* (b) The mode of the register is the same as the mode of
1539 : the argument as it is passed; */
1540 100 : if (mode3 != mode4)
1541 0 : continue;
1542 : /* (c) There's no language level extension; */
1543 100 : if (mode1 == mode2)
1544 : ;
1545 : /* (c.1) All callers are from the current compilation unit. If that's
1546 : the case we don't have to rely on an ABI, we only have to know
1547 : what we're generating right now, and we know that we will do the
1548 : mode1 to mode2 promotion with the given sign. */
1549 0 : else if (!strictly_local)
1550 0 : continue;
1551 : /* (c.2) The combination of the two promotions is useful. This is
1552 : true when the signs match, or if the first promotion is unsigned.
1553 : In the later case, (sign_extend (zero_extend x)) is the same as
1554 : (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1555 0 : else if (uns1)
1556 0 : uns3 = true;
1557 0 : else if (uns3)
1558 0 : continue;
1559 :
1560 : /* Record that the value was promoted from mode1 to mode3,
1561 : so that any sign extension at the head of the current
1562 : function may be eliminated. */
1563 100 : x = gen_rtx_CLOBBER (mode1, const0_rtx);
1564 100 : x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1565 100 : record_value_for_reg (reg, first, x);
1566 : }
1567 2050704 : }
1568 :
1569 : /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1570 : that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1571 : because some machines (maybe most) will actually do the sign-extension and
1572 : this is the conservative approach.
1573 :
1574 : ??? For 2.5, try to tighten up the MD files in this regard instead of this
1575 : kludge. */
1576 :
1577 : static rtx
1578 0 : sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1579 : {
1580 0 : scalar_int_mode int_mode;
1581 0 : if (CONST_INT_P (src)
1582 0 : && is_a <scalar_int_mode> (mode, &int_mode)
1583 0 : && GET_MODE_PRECISION (int_mode) < prec
1584 0 : && INTVAL (src) > 0
1585 0 : && val_signbit_known_set_p (int_mode, INTVAL (src)))
1586 0 : src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1587 :
1588 0 : return src;
1589 : }
1590 :
1591 : /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1592 : and SET. */
1593 :
1594 : static void
1595 24073844 : update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1596 : rtx x)
1597 : {
1598 24073844 : rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1599 24073844 : unsigned HOST_WIDE_INT bits = 0;
1600 24073844 : rtx reg_equal = NULL, src = SET_SRC (set);
1601 24073844 : unsigned int num = 0;
1602 :
1603 24073844 : if (reg_equal_note)
1604 1011706 : reg_equal = XEXP (reg_equal_note, 0);
1605 :
1606 24073844 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
1607 : {
1608 : src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1609 : if (reg_equal)
1610 : reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1611 : }
1612 :
1613 : /* Don't call nonzero_bits if it cannot change anything. */
1614 24073844 : if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1615 : {
1616 20821155 : machine_mode mode = GET_MODE (x);
1617 20821155 : if (GET_MODE_CLASS (mode) == MODE_INT
1618 20821155 : && HWI_COMPUTABLE_MODE_P (mode))
1619 20821023 : mode = nonzero_bits_mode;
1620 20821155 : bits = nonzero_bits (src, mode);
1621 20821155 : if (reg_equal && bits)
1622 957991 : bits &= nonzero_bits (reg_equal, mode);
1623 20821155 : rsp->nonzero_bits |= bits;
1624 : }
1625 :
1626 : /* Don't call num_sign_bit_copies if it cannot change anything. */
1627 24073844 : if (rsp->sign_bit_copies != 1)
1628 : {
1629 20668036 : num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1630 20668036 : if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1631 : {
1632 955333 : unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1633 955333 : if (num == 0 || numeq > num)
1634 20668036 : num = numeq;
1635 : }
1636 20668036 : if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1637 19946265 : rsp->sign_bit_copies = num;
1638 : }
1639 24073844 : }
1640 :
1641 : /* Called via note_stores. If X is a pseudo that is narrower than
1642 : HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1643 :
1644 : If we are setting only a portion of X and we can't figure out what
1645 : portion, assume all bits will be used since we don't know what will
1646 : be happening.
1647 :
1648 : Similarly, set how many bits of X are known to be copies of the sign bit
1649 : at all locations in the function. This is the smallest number implied
1650 : by any set of X. */
1651 :
1652 : static void
1653 74009021 : set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1654 : {
1655 74009021 : rtx_insn *insn = (rtx_insn *) data;
1656 74009021 : scalar_int_mode mode;
1657 :
1658 74009021 : if (REG_P (x)
1659 59660304 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1660 : /* If this register is undefined at the start of the file, we can't
1661 : say what its contents were. */
1662 59646802 : && ! REGNO_REG_SET_P
1663 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1664 29721561 : && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1665 99024109 : && HWI_COMPUTABLE_MODE_P (mode))
1666 : {
1667 24282155 : reg_stat_type *rsp = ®_stat[REGNO (x)];
1668 :
1669 24282155 : if (set == 0 || GET_CODE (set) == CLOBBER)
1670 : {
1671 22564 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1672 22564 : rsp->sign_bit_copies = 1;
1673 22564 : return;
1674 : }
1675 :
1676 : /* If this register is being initialized using itself, and the
1677 : register is uninitialized in this basic block, and there are
1678 : no LOG_LINKS which set the register, then part of the
1679 : register is uninitialized. In that case we can't assume
1680 : anything about the number of nonzero bits.
1681 :
1682 : ??? We could do better if we checked this in
1683 : reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1684 : could avoid making assumptions about the insn which initially
1685 : sets the register, while still using the information in other
1686 : insns. We would have to be careful to check every insn
1687 : involved in the combination. */
1688 :
1689 24259591 : if (insn
1690 22822993 : && reg_referenced_p (x, PATTERN (insn))
1691 26900893 : && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1692 : REGNO (x)))
1693 : {
1694 267984 : struct insn_link *link;
1695 :
1696 398588 : FOR_EACH_LOG_LINK (link, insn)
1697 311098 : if (dead_or_set_p (link->insn, x))
1698 : break;
1699 267984 : if (!link)
1700 : {
1701 87490 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1702 87490 : rsp->sign_bit_copies = 1;
1703 87490 : return;
1704 : }
1705 : }
1706 :
1707 : /* If this is a complex assignment, see if we can convert it into a
1708 : simple assignment. */
1709 24172101 : set = expand_field_assignment (set);
1710 :
1711 : /* If this is a simple assignment, or we have a paradoxical SUBREG,
1712 : set what we know about X. */
1713 :
1714 24172101 : if (SET_DEST (set) == x
1715 24172101 : || (paradoxical_subreg_p (SET_DEST (set))
1716 4703 : && SUBREG_REG (SET_DEST (set)) == x))
1717 24073844 : update_rsp_from_reg_equal (rsp, insn, set, x);
1718 : else
1719 : {
1720 98257 : rsp->nonzero_bits = GET_MODE_MASK (mode);
1721 98257 : rsp->sign_bit_copies = 1;
1722 : }
1723 : }
1724 : }
1725 :
1726 : /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1727 : optionally insns that were previously combined into I3 or that will be
1728 : combined into the merger of INSN and I3. The order is PRED, PRED2,
1729 : INSN, SUCC, SUCC2, I3.
1730 :
1731 : Return false if the combination is not allowed for any reason.
1732 :
1733 : If the combination is allowed, *PDEST will be set to the single
1734 : destination of INSN and *PSRC to the single source, and this function
1735 : will return true. */
1736 :
1737 : static bool
1738 62590561 : can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1739 : rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1740 : rtx *pdest, rtx *psrc)
1741 : {
1742 62590561 : int i;
1743 62590561 : const_rtx set = 0;
1744 62590561 : rtx src, dest;
1745 62590561 : rtx_insn *p;
1746 62590561 : rtx link;
1747 62590561 : bool all_adjacent = true;
1748 62590561 : bool (*is_volatile_p) (const_rtx);
1749 :
1750 62590561 : if (succ)
1751 : {
1752 14783515 : if (succ2)
1753 : {
1754 2210435 : if (next_active_insn (succ2) != i3)
1755 192036 : all_adjacent = false;
1756 2210435 : if (next_active_insn (succ) != succ2)
1757 2049435 : all_adjacent = false;
1758 : }
1759 12573080 : else if (next_active_insn (succ) != i3)
1760 2049435 : all_adjacent = false;
1761 14783515 : if (next_active_insn (insn) != succ)
1762 17459903 : all_adjacent = false;
1763 : }
1764 47807046 : else if (next_active_insn (insn) != i3)
1765 17459903 : all_adjacent = false;
1766 :
1767 : /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1768 : or a PARALLEL consisting of such a SET and CLOBBERs.
1769 :
1770 : If INSN has CLOBBER parallel parts, ignore them for our processing.
1771 : By definition, these happen during the execution of the insn. When it
1772 : is merged with another insn, all bets are off. If they are, in fact,
1773 : needed and aren't also supplied in I3, they may be added by
1774 : recog_for_combine. Otherwise, it won't match.
1775 :
1776 : We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1777 : note.
1778 :
1779 : Get the source and destination of INSN. If more than one, can't
1780 : combine. */
1781 :
1782 62590561 : if (GET_CODE (PATTERN (insn)) == SET)
1783 : set = PATTERN (insn);
1784 16474736 : else if (GET_CODE (PATTERN (insn)) == PARALLEL
1785 16474736 : && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1786 : {
1787 49371174 : for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1788 : {
1789 33416517 : rtx elt = XVECEXP (PATTERN (insn), 0, i);
1790 :
1791 33416517 : switch (GET_CODE (elt))
1792 : {
1793 : /* This is important to combine floating point insns
1794 : for the SH4 port. */
1795 137517 : case USE:
1796 : /* Combining an isolated USE doesn't make sense.
1797 : We depend here on combinable_i3pat to reject them. */
1798 : /* The code below this loop only verifies that the inputs of
1799 : the SET in INSN do not change. We call reg_set_between_p
1800 : to verify that the REG in the USE does not change between
1801 : I3 and INSN.
1802 : If the USE in INSN was for a pseudo register, the matching
1803 : insn pattern will likely match any register; combining this
1804 : with any other USE would only be safe if we knew that the
1805 : used registers have identical values, or if there was
1806 : something to tell them apart, e.g. different modes. For
1807 : now, we forgo such complicated tests and simply disallow
1808 : combining of USES of pseudo registers with any other USE. */
1809 137517 : if (REG_P (XEXP (elt, 0))
1810 137517 : && GET_CODE (PATTERN (i3)) == PARALLEL)
1811 : {
1812 247 : rtx i3pat = PATTERN (i3);
1813 247 : int i = XVECLEN (i3pat, 0) - 1;
1814 247 : unsigned int regno = REGNO (XEXP (elt, 0));
1815 :
1816 505 : do
1817 : {
1818 505 : rtx i3elt = XVECEXP (i3pat, 0, i);
1819 :
1820 505 : if (GET_CODE (i3elt) == USE
1821 225 : && REG_P (XEXP (i3elt, 0))
1822 757 : && (REGNO (XEXP (i3elt, 0)) == regno
1823 198 : ? reg_set_between_p (XEXP (elt, 0),
1824 27 : PREV_INSN (insn), i3)
1825 : : regno >= FIRST_PSEUDO_REGISTER))
1826 : return false;
1827 : }
1828 307 : while (--i >= 0);
1829 : }
1830 : break;
1831 :
1832 : /* We can ignore CLOBBERs. */
1833 : case CLOBBER:
1834 : break;
1835 :
1836 17066092 : case SET:
1837 : /* Ignore SETs whose result isn't used but not those that
1838 : have side-effects. */
1839 17066092 : if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1840 194900 : && insn_nothrow_p (insn)
1841 17247953 : && !side_effects_p (elt))
1842 : break;
1843 :
1844 : /* If we have already found a SET, this is a second one and
1845 : so we cannot combine with this insn. */
1846 16968990 : if (set)
1847 : return false;
1848 :
1849 : set = elt;
1850 : break;
1851 :
1852 : default:
1853 : /* Anything else means we can't combine. */
1854 : return false;
1855 : }
1856 : }
1857 :
1858 15954657 : if (set == 0
1859 : /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1860 : so don't do anything with it. */
1861 15954657 : || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1862 : return false;
1863 : }
1864 : else
1865 : return false;
1866 :
1867 : if (set == 0)
1868 : return false;
1869 :
1870 : /* The simplification in expand_field_assignment may call back to
1871 : get_last_value, so set safe guard here. */
1872 62050550 : subst_low_luid = DF_INSN_LUID (insn);
1873 :
1874 62050550 : set = expand_field_assignment (set);
1875 62050550 : src = SET_SRC (set), dest = SET_DEST (set);
1876 :
1877 : /* Do not eliminate user-specified register if it is in an
1878 : asm input because we may break the register asm usage defined
1879 : in GCC manual if allow to do so.
1880 : Be aware that this may cover more cases than we expect but this
1881 : should be harmless. */
1882 61488171 : if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1883 62050553 : && extract_asm_operands (PATTERN (i3)))
1884 : return false;
1885 :
1886 : /* Don't eliminate a store in the stack pointer. */
1887 62050550 : if (dest == stack_pointer_rtx
1888 : /* Don't combine with an insn that sets a register to itself if it has
1889 : a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1890 60149859 : || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1891 : /* Can't merge an ASM_OPERANDS. */
1892 60149859 : || GET_CODE (src) == ASM_OPERANDS
1893 : /* Can't merge a function call. */
1894 60146239 : || GET_CODE (src) == CALL
1895 : /* Don't eliminate a function call argument. */
1896 60146239 : || (CALL_P (i3)
1897 8969979 : && (find_reg_fusage (i3, USE, dest)
1898 168772 : || (REG_P (dest)
1899 168772 : && REGNO (dest) < FIRST_PSEUDO_REGISTER
1900 283 : && global_regs[REGNO (dest)])))
1901 : /* Don't substitute into an incremented register. */
1902 : || FIND_REG_INC_NOTE (i3, dest)
1903 : || (succ && FIND_REG_INC_NOTE (succ, dest))
1904 60146239 : || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1905 : /* Don't substitute into a non-local goto, this confuses CFG. */
1906 51345029 : || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1907 : /* Make sure that DEST is not used after INSN but before SUCC, or
1908 : after SUCC and before SUCC2, or after SUCC2 but before I3. */
1909 51344308 : || (!all_adjacent
1910 12615977 : && ((succ2
1911 960698 : && (reg_used_between_p (dest, succ2, i3)
1912 938441 : || reg_used_between_p (dest, succ, succ2)))
1913 12547478 : || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1914 12267437 : || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1915 12267437 : || (succ
1916 : /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1917 : that case SUCC is not in the insn stream, so use SUCC2
1918 : instead for this test. */
1919 10111354 : && reg_used_between_p (dest, insn,
1920 : succ2
1921 892199 : && INSN_UID (succ) == INSN_UID (succ2)
1922 : ? succ2 : succ))))
1923 : /* Make sure that the value that is to be substituted for the register
1924 : does not use any registers whose values alter in between. However,
1925 : If the insns are adjacent, a use can't cross a set even though we
1926 : think it might (this can happen for a sequence of insns each setting
1927 : the same destination; last_set of that register might point to
1928 : a NOTE). If INSN has a REG_EQUIV note, the register is always
1929 : equivalent to the memory so the substitution is valid even if there
1930 : are intervening stores. Also, don't move a volatile asm or
1931 : UNSPEC_VOLATILE across any other insns. */
1932 : || (! all_adjacent
1933 12267437 : && (((!MEM_P (src)
1934 3514950 : || ! find_reg_note (insn, REG_EQUIV, src))
1935 12151879 : && modified_between_p (src, insn, i3))
1936 11108922 : || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1937 11108922 : || GET_CODE (src) == UNSPEC_VOLATILE))
1938 : /* Don't combine across a CALL_INSN, because that would possibly
1939 : change whether the life span of some REGs crosses calls or not,
1940 : and it is a pain to update that information.
1941 : Exception: if source is a constant, moving it later can't hurt.
1942 : Accept that as a special case. */
1943 111877339 : || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1944 : return false;
1945 :
1946 : /* DEST must be a REG. */
1947 49524981 : if (REG_P (dest))
1948 : {
1949 : /* If register alignment is being enforced for multi-word items in all
1950 : cases except for parameters, it is possible to have a register copy
1951 : insn referencing a hard register that is not allowed to contain the
1952 : mode being copied and which would not be valid as an operand of most
1953 : insns. Eliminate this problem by not combining with such an insn.
1954 :
1955 : Also, on some machines we don't want to extend the life of a hard
1956 : register. */
1957 :
1958 48967499 : if (REG_P (src)
1959 48967499 : && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1960 29521 : && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1961 : /* Don't extend the life of a hard register unless it is
1962 : user variable (if we have few registers) or it can't
1963 : fit into the desired register (meaning something special
1964 : is going on).
1965 : Also avoid substituting a return register into I3, because
1966 : reload can't handle a conflict with constraints of other
1967 : inputs. */
1968 2609532 : || (REGNO (src) < FIRST_PSEUDO_REGISTER
1969 37486 : && !targetm.hard_regno_mode_ok (REGNO (src),
1970 37486 : GET_MODE (src)))))
1971 : return false;
1972 : }
1973 : else
1974 : return false;
1975 :
1976 :
1977 48967499 : if (GET_CODE (PATTERN (i3)) == PARALLEL)
1978 36822184 : for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1979 24826496 : if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1980 : {
1981 11662625 : rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1982 :
1983 : /* If the clobber represents an earlyclobber operand, we must not
1984 : substitute an expression containing the clobbered register.
1985 : As we do not analyze the constraint strings here, we have to
1986 : make the conservative assumption. However, if the register is
1987 : a fixed hard reg, the clobber cannot represent any operand;
1988 : we leave it up to the machine description to either accept or
1989 : reject use-and-clobber patterns. */
1990 11662625 : if (!REG_P (reg)
1991 11307564 : || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1992 22921257 : || !fixed_regs[REGNO (reg)])
1993 441733 : if (reg_overlap_mentioned_p (reg, src))
1994 : return false;
1995 : }
1996 :
1997 : /* If INSN contains anything volatile, or is an `asm' (whether volatile
1998 : or not), reject, unless nothing volatile comes between it and I3 */
1999 :
2000 48966844 : if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
2001 : {
2002 : /* Make sure neither succ nor succ2 contains a volatile reference. */
2003 699173 : if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
2004 : return false;
2005 699079 : if (succ != 0 && volatile_refs_p (PATTERN (succ)))
2006 : return false;
2007 : /* We'll check insns between INSN and I3 below. */
2008 : }
2009 :
2010 : /* If INSN is an asm, and DEST is a hard register, reject, since it has
2011 : to be an explicit register variable, and was chosen for a reason. */
2012 :
2013 48930692 : if (GET_CODE (src) == ASM_OPERANDS
2014 48930692 : && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2015 : return false;
2016 :
2017 : /* If INSN contains volatile references (specifically volatile MEMs),
2018 : we cannot combine across any other volatile references.
2019 : Even if INSN doesn't contain volatile references, any intervening
2020 : volatile insn might affect machine state. */
2021 :
2022 97197495 : is_volatile_p = volatile_refs_p (PATTERN (insn))
2023 48930692 : ? volatile_refs_p
2024 : : volatile_insn_p;
2025 :
2026 224930446 : for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2027 127274435 : if (NONDEBUG_INSN_P (p)
2028 62085832 : && p != succ
2029 62085832 : && p != succ2
2030 174376770 : && is_volatile_p (PATTERN (p)))
2031 : return false;
2032 :
2033 : /* If INSN contains an autoincrement or autodecrement, make sure that
2034 : register is not used between there and I3, and not already used in
2035 : I3 either. Neither must it be used in PRED or SUCC, if they exist.
2036 : Also insist that I3 not be a jump if using LRA; if it were one
2037 : and the incremented register were spilled, we would lose.
2038 : Reload handles this correctly. */
2039 :
2040 48725319 : if (AUTO_INC_DEC)
2041 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2042 : if (REG_NOTE_KIND (link) == REG_INC
2043 : && ((JUMP_P (i3) && targetm.lra_p ())
2044 : || reg_used_between_p (XEXP (link, 0), insn, i3)
2045 : || (pred != NULL_RTX
2046 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2047 : || (pred2 != NULL_RTX
2048 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2049 : || (succ != NULL_RTX
2050 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2051 : || (succ2 != NULL_RTX
2052 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2053 : || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2054 : return false;
2055 :
2056 : /* If we get here, we have passed all the tests and the combination is
2057 : to be allowed. */
2058 :
2059 48725319 : *pdest = dest;
2060 48725319 : *psrc = src;
2061 :
2062 48725319 : return true;
2063 : }
2064 :
2065 : /* LOC is the location within I3 that contains its pattern or the component
2066 : of a PARALLEL of the pattern. We validate that it is valid for combining.
2067 :
2068 : One problem is if I3 modifies its output, as opposed to replacing it
2069 : entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2070 : doing so would produce an insn that is not equivalent to the original insns.
2071 :
2072 : Consider:
2073 :
2074 : (set (reg:DI 101) (reg:DI 100))
2075 : (set (subreg:SI (reg:DI 101) 0) <foo>)
2076 :
2077 : This is NOT equivalent to:
2078 :
2079 : (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2080 : (set (reg:DI 101) (reg:DI 100))])
2081 :
2082 : Not only does this modify 100 (in which case it might still be valid
2083 : if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2084 :
2085 : We can also run into a problem if I2 sets a register that I1
2086 : uses and I1 gets directly substituted into I3 (not via I2). In that
2087 : case, we would be getting the wrong value of I2DEST into I3, so we
2088 : must reject the combination. This case occurs when I2 and I1 both
2089 : feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2090 : If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2091 : of a SET must prevent combination from occurring. The same situation
2092 : can occur for I0, in which case I0_NOT_IN_SRC is set.
2093 :
2094 : Before doing the above check, we first try to expand a field assignment
2095 : into a set of logical operations.
2096 :
2097 : If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2098 : we place a register that is both set and used within I3. If more than one
2099 : such register is detected, we fail.
2100 :
2101 : Return true if the combination is valid, false otherwise. */
2102 :
2103 : static bool
2104 70042750 : combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2105 : bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2106 : {
2107 70042750 : rtx x = *loc;
2108 :
2109 70042750 : if (GET_CODE (x) == SET)
2110 : {
2111 47237883 : rtx set = x ;
2112 47237883 : rtx dest = SET_DEST (set);
2113 47237883 : rtx src = SET_SRC (set);
2114 47237883 : rtx inner_dest = dest;
2115 47237883 : rtx subdest;
2116 :
2117 47237883 : while (GET_CODE (inner_dest) == STRICT_LOW_PART
2118 47752261 : || GET_CODE (inner_dest) == SUBREG
2119 47752261 : || GET_CODE (inner_dest) == ZERO_EXTRACT)
2120 514378 : inner_dest = XEXP (inner_dest, 0);
2121 :
2122 : /* Check for the case where I3 modifies its output, as discussed
2123 : above. We don't want to prevent pseudos from being combined
2124 : into the address of a MEM, so only prevent the combination if
2125 : i1 or i2 set the same MEM. */
2126 493704 : if ((inner_dest != dest &&
2127 : (!MEM_P (inner_dest)
2128 770 : || rtx_equal_p (i2dest, inner_dest)
2129 770 : || (i1dest && rtx_equal_p (i1dest, inner_dest))
2130 770 : || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2131 492934 : && (reg_overlap_mentioned_p (i2dest, inner_dest)
2132 362974 : || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2133 361680 : || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2134 :
2135 : /* This is the same test done in can_combine_p except we can't test
2136 : all_adjacent; we don't have to, since this instruction will stay
2137 : in place, thus we are not considering increasing the lifetime of
2138 : INNER_DEST.
2139 :
2140 : Also, if this insn sets a function argument, combining it with
2141 : something that might need a spill could clobber a previous
2142 : function argument; the all_adjacent test in can_combine_p also
2143 : checks this; here, we do a more specific test for this case. */
2144 :
2145 47106537 : || (REG_P (inner_dest)
2146 30363417 : && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2147 7506101 : && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2148 7506101 : GET_MODE (inner_dest)))
2149 47106283 : || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2150 94337041 : || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2151 : return false;
2152 :
2153 : /* If DEST is used in I3, it is being killed in this insn, so
2154 : record that for later. We have to consider paradoxical
2155 : subregs here, since they kill the whole register, but we
2156 : ignore partial subregs, STRICT_LOW_PART, etc.
2157 : Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2158 : STACK_POINTER_REGNUM, since these are always considered to be
2159 : live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2160 47068434 : subdest = dest;
2161 47068434 : if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2162 251969 : subdest = SUBREG_REG (subdest);
2163 47068434 : if (pi3dest_killed
2164 34153415 : && REG_P (subdest)
2165 21727806 : && reg_referenced_p (subdest, PATTERN (i3))
2166 1252485 : && REGNO (subdest) != FRAME_POINTER_REGNUM
2167 1252485 : && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2168 1252485 : || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2169 1252485 : && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2170 1252485 : || (REGNO (subdest) != ARG_POINTER_REGNUM
2171 0 : || ! fixed_regs [REGNO (subdest)]))
2172 48320919 : && REGNO (subdest) != STACK_POINTER_REGNUM)
2173 : {
2174 1214856 : if (*pi3dest_killed)
2175 : return false;
2176 :
2177 1191376 : *pi3dest_killed = subdest;
2178 : }
2179 : }
2180 :
2181 22804867 : else if (GET_CODE (x) == PARALLEL)
2182 : {
2183 : int i;
2184 :
2185 34709063 : for (i = 0; i < XVECLEN (x, 0); i++)
2186 23403427 : if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2187 : i1_not_in_src, i0_not_in_src, pi3dest_killed))
2188 : return false;
2189 : }
2190 :
2191 : return true;
2192 : }
2193 :
2194 : /* Return true if X is an arithmetic expression that contains a multiplication
2195 : and division. We don't count multiplications by powers of two here. */
2196 :
2197 : static bool
2198 17597474 : contains_muldiv (rtx x)
2199 : {
2200 18273486 : switch (GET_CODE (x))
2201 : {
2202 : case MOD: case DIV: case UMOD: case UDIV:
2203 : return true;
2204 :
2205 537320 : case MULT:
2206 537320 : return ! (CONST_INT_P (XEXP (x, 1))
2207 126517 : && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2208 17577646 : default:
2209 17577646 : if (BINARY_P (x))
2210 6023178 : return contains_muldiv (XEXP (x, 0))
2211 6023178 : || contains_muldiv (XEXP (x, 1));
2212 :
2213 11554468 : if (UNARY_P (x))
2214 676012 : return contains_muldiv (XEXP (x, 0));
2215 :
2216 : return false;
2217 : }
2218 : }
2219 :
2220 : /* Determine whether INSN can be used in a combination. Return true if
2221 : not. This is used in try_combine to detect early some cases where we
2222 : can't perform combinations. */
2223 :
2224 : static bool
2225 170406643 : cant_combine_insn_p (rtx_insn *insn)
2226 : {
2227 170406643 : rtx set;
2228 170406643 : rtx src, dest;
2229 :
2230 : /* If this isn't really an insn, we can't do anything.
2231 : This can occur when flow deletes an insn that it has merged into an
2232 : auto-increment address. */
2233 170406643 : if (!NONDEBUG_INSN_P (insn))
2234 : return true;
2235 :
2236 : /* Never combine loads and stores involving hard regs that are likely
2237 : to be spilled. The register allocator can usually handle such
2238 : reg-reg moves by tying. If we allow the combiner to make
2239 : substitutions of likely-spilled regs, reload might die.
2240 : As an exception, we allow combinations involving fixed regs; these are
2241 : not available to the register allocator so there's no risk involved. */
2242 :
2243 170406286 : set = single_set (insn);
2244 170406286 : if (! set)
2245 : return false;
2246 156761618 : src = SET_SRC (set);
2247 156761618 : dest = SET_DEST (set);
2248 156761618 : if (GET_CODE (src) == SUBREG)
2249 1147134 : src = SUBREG_REG (src);
2250 156761618 : if (GET_CODE (dest) == SUBREG)
2251 1732864 : dest = SUBREG_REG (dest);
2252 42649841 : if (REG_P (src) && REG_P (dest)
2253 192577411 : && ((HARD_REGISTER_P (src)
2254 6897261 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2255 : #ifdef LEAF_REGISTERS
2256 : && ! LEAF_REGISTERS [REGNO (src)])
2257 : #else
2258 : )
2259 : #endif
2260 29256746 : || (HARD_REGISTER_P (dest)
2261 20875607 : && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2262 20574047 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2263 25541183 : return true;
2264 :
2265 : return false;
2266 : }
2267 :
2268 : struct likely_spilled_retval_info
2269 : {
2270 : unsigned regno, nregs;
2271 : unsigned mask;
2272 : };
2273 :
2274 : /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2275 : hard registers that are known to be written to / clobbered in full. */
2276 : static void
2277 168839 : likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2278 : {
2279 168839 : struct likely_spilled_retval_info *const info =
2280 : (struct likely_spilled_retval_info *) data;
2281 168839 : unsigned regno, nregs;
2282 168839 : unsigned new_mask;
2283 :
2284 168839 : if (!REG_P (XEXP (set, 0)))
2285 : return;
2286 168839 : regno = REGNO (x);
2287 168839 : if (regno >= info->regno + info->nregs)
2288 : return;
2289 168839 : nregs = REG_NREGS (x);
2290 168839 : if (regno + nregs <= info->regno)
2291 : return;
2292 168839 : new_mask = (2U << (nregs - 1)) - 1;
2293 168839 : if (regno < info->regno)
2294 0 : new_mask >>= info->regno - regno;
2295 : else
2296 168839 : new_mask <<= regno - info->regno;
2297 168839 : info->mask &= ~new_mask;
2298 : }
2299 :
2300 : /* Return true iff part of the return value is live during INSN, and
2301 : it is likely spilled. This can happen when more than one insn is needed
2302 : to copy the return value, e.g. when we consider to combine into the
2303 : second copy insn for a complex value. */
2304 :
2305 : static bool
2306 48162375 : likely_spilled_retval_p (rtx_insn *insn)
2307 : {
2308 48162375 : rtx_insn *use = BB_END (this_basic_block);
2309 48162375 : rtx reg;
2310 48162375 : rtx_insn *p;
2311 48162375 : unsigned regno, nregs;
2312 : /* We assume here that no machine mode needs more than
2313 : 32 hard registers when the value overlaps with a register
2314 : for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2315 48162375 : unsigned mask;
2316 48162375 : struct likely_spilled_retval_info info;
2317 :
2318 48162375 : if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2319 : return false;
2320 3239156 : reg = XEXP (PATTERN (use), 0);
2321 3239156 : if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2322 : return false;
2323 3239156 : regno = REGNO (reg);
2324 3239156 : nregs = REG_NREGS (reg);
2325 3239156 : if (nregs == 1)
2326 : return false;
2327 166222 : mask = (2U << (nregs - 1)) - 1;
2328 :
2329 : /* Disregard parts of the return value that are set later. */
2330 166222 : info.regno = regno;
2331 166222 : info.nregs = nregs;
2332 166222 : info.mask = mask;
2333 564723 : for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2334 232279 : if (INSN_P (p))
2335 232279 : note_stores (p, likely_spilled_retval_1, &info);
2336 332408 : mask = info.mask;
2337 :
2338 : /* Check if any of the (probably) live return value registers is
2339 : likely spilled. */
2340 : nregs --;
2341 332408 : do
2342 : {
2343 332408 : if ((mask & 1 << nregs)
2344 332408 : && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2345 : return true;
2346 332362 : } while (nregs--);
2347 : return false;
2348 : }
2349 :
2350 : /* Adjust INSN after we made a change to its destination.
2351 :
2352 : Changing the destination can invalidate notes that say something about
2353 : the results of the insn and a LOG_LINK pointing to the insn. */
2354 :
2355 : static void
2356 17319 : adjust_for_new_dest (rtx_insn *insn)
2357 : {
2358 : /* For notes, be conservative and simply remove them. */
2359 17319 : remove_reg_equal_equiv_notes (insn, true);
2360 :
2361 : /* The new insn will have a destination that was previously the destination
2362 : of an insn just above it. Call distribute_links to make a LOG_LINK from
2363 : the next use of that destination. */
2364 :
2365 17319 : rtx set = single_set (insn);
2366 17319 : gcc_assert (set);
2367 :
2368 17319 : rtx reg = SET_DEST (set);
2369 :
2370 17319 : while (GET_CODE (reg) == ZERO_EXTRACT
2371 17319 : || GET_CODE (reg) == STRICT_LOW_PART
2372 34638 : || GET_CODE (reg) == SUBREG)
2373 0 : reg = XEXP (reg, 0);
2374 17319 : gcc_assert (REG_P (reg));
2375 :
2376 17319 : distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2377 :
2378 17319 : df_insn_rescan (insn);
2379 17319 : }
2380 :
2381 : /* Return TRUE if combine can reuse reg X in mode MODE.
2382 : ADDED_SETS is trueif the original set is still required. */
2383 : static bool
2384 2722169 : can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2385 : {
2386 2722169 : unsigned int regno;
2387 :
2388 2722169 : if (!REG_P (x))
2389 : return false;
2390 :
2391 : /* Don't change between modes with different underlying register sizes,
2392 : since this could lead to invalid subregs. */
2393 2722169 : if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2394 2722169 : REGMODE_NATURAL_SIZE (GET_MODE (x))))
2395 : return false;
2396 :
2397 2722169 : regno = REGNO (x);
2398 : /* Allow hard registers if the new mode is legal, and occupies no more
2399 : registers than the old mode. */
2400 2722169 : if (regno < FIRST_PSEUDO_REGISTER)
2401 1223957 : return (targetm.hard_regno_mode_ok (regno, mode)
2402 1223957 : && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2403 :
2404 : /* Or a pseudo that is only used once. */
2405 1498212 : return (regno < reg_n_sets_max
2406 1498188 : && REG_N_SETS (regno) == 1
2407 1447511 : && !added_sets
2408 2945723 : && !REG_USERVAR_P (x));
2409 : }
2410 :
2411 :
2412 : /* Check whether X, the destination of a set, refers to part of
2413 : the register specified by REG. */
2414 :
2415 : static bool
2416 17582 : reg_subword_p (rtx x, rtx reg)
2417 : {
2418 : /* Check that reg is an integer mode register. */
2419 17582 : if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2420 : return false;
2421 :
2422 17024 : if (GET_CODE (x) == STRICT_LOW_PART
2423 16593 : || GET_CODE (x) == ZERO_EXTRACT)
2424 455 : x = XEXP (x, 0);
2425 :
2426 17024 : return GET_CODE (x) == SUBREG
2427 16831 : && !paradoxical_subreg_p (x)
2428 16831 : && SUBREG_REG (x) == reg
2429 33855 : && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2430 : }
2431 :
2432 : /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2433 : by an arbitrary number of CLOBBERs. */
2434 : static bool
2435 103029892 : is_parallel_of_n_reg_sets (rtx pat, int n)
2436 : {
2437 103029892 : if (GET_CODE (pat) != PARALLEL)
2438 : return false;
2439 :
2440 27556167 : int len = XVECLEN (pat, 0);
2441 27556167 : if (len < n)
2442 : return false;
2443 :
2444 : int i;
2445 54839781 : for (i = 0; i < n; i++)
2446 51981758 : if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2447 30718722 : || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2448 : return false;
2449 3245489 : for ( ; i < len; i++)
2450 1017859 : switch (GET_CODE (XVECEXP (pat, 0, i)))
2451 : {
2452 387467 : case CLOBBER:
2453 387467 : if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2454 : return false;
2455 387466 : break;
2456 : default:
2457 : return false;
2458 : }
2459 : return true;
2460 : }
2461 :
2462 : /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2463 : CLOBBERs), can be split into individual SETs in that order, without
2464 : changing semantics. */
2465 : static bool
2466 363993 : can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2467 : {
2468 363993 : if (!insn_nothrow_p (insn))
2469 : return false;
2470 :
2471 362472 : rtx pat = PATTERN (insn);
2472 :
2473 362472 : int i, j;
2474 982138 : for (i = 0; i < n; i++)
2475 : {
2476 672305 : if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2477 : return false;
2478 :
2479 669193 : rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2480 :
2481 979026 : for (j = i + 1; j < n; j++)
2482 359360 : if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2483 : return false;
2484 : }
2485 :
2486 : return true;
2487 : }
2488 :
2489 : /* Return whether X is just a single_set, with the source
2490 : a general_operand. */
2491 : static bool
2492 67883264 : is_just_move (rtx_insn *x)
2493 : {
2494 67883264 : rtx set = single_set (x);
2495 67883264 : if (!set)
2496 : return false;
2497 :
2498 67470757 : return general_operand (SET_SRC (set), VOIDmode);
2499 : }
2500 :
2501 : /* Callback function to count autoincs. */
2502 :
2503 : static int
2504 1022926 : count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2505 : {
2506 1022926 : (*((int *) arg))++;
2507 :
2508 1022926 : return 0;
2509 : }
2510 :
2511 : /* Try to combine the insns I0, I1 and I2 into I3.
2512 : Here I0, I1 and I2 appear earlier than I3.
2513 : I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2514 : I3.
2515 :
2516 : If we are combining more than two insns and the resulting insn is not
2517 : recognized, try splitting it into two insns. If that happens, I2 and I3
2518 : are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2519 : Otherwise, I0, I1 and I2 are pseudo-deleted.
2520 :
2521 : Return 0 if the combination does not work. Then nothing is changed.
2522 : If we did the combination, return the insn at which combine should
2523 : resume scanning.
2524 :
2525 : Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2526 : new direct jump instruction.
2527 :
2528 : LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2529 : been I3 passed to an earlier try_combine within the same basic
2530 : block. */
2531 :
2532 : static rtx_insn *
2533 98124787 : try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2534 : bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2535 : {
2536 : /* New patterns for I3 and I2, respectively. */
2537 98124787 : rtx newpat, newi2pat = 0;
2538 98124787 : rtvec newpat_vec_with_clobbers = 0;
2539 98124787 : bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2540 : /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2541 : dead. */
2542 98124787 : bool added_sets_0, added_sets_1, added_sets_2;
2543 : /* Total number of SETs to put into I3. */
2544 98124787 : int total_sets;
2545 : /* Nonzero if I2's or I1's body now appears in I3. */
2546 98124787 : int i2_is_used = 0, i1_is_used = 0;
2547 : /* INSN_CODEs for new I3, new I2, and user of condition code. */
2548 98124787 : int insn_code_number, i2_code_number = 0, other_code_number = 0;
2549 : /* Contains I3 if the destination of I3 is used in its source, which means
2550 : that the old life of I3 is being killed. If that usage is placed into
2551 : I2 and not in I3, a REG_DEAD note must be made. */
2552 98124787 : rtx i3dest_killed = 0;
2553 : /* SET_DEST and SET_SRC of I2, I1 and I0. */
2554 98124787 : rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2555 : /* Copy of SET_SRC of I1 and I0, if needed. */
2556 98124787 : rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2557 : /* Set if I2DEST was reused as a scratch register. */
2558 98124787 : bool i2scratch = false;
2559 : /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2560 98124787 : rtx i0pat = 0, i1pat = 0, i2pat = 0;
2561 : /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2562 98124787 : bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2563 98124787 : bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2564 98124787 : bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2565 98124787 : bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2566 98124787 : bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2567 : /* Notes that must be added to REG_NOTES in I3 and I2. */
2568 98124787 : rtx new_i3_notes, new_i2_notes;
2569 : /* Notes that we substituted I3 into I2 instead of the normal case. */
2570 98124787 : bool i3_subst_into_i2 = false;
2571 : /* Notes that I1, I2 or I3 is a MULT operation. */
2572 98124787 : bool have_mult = false;
2573 98124787 : bool swap_i2i3 = false;
2574 98124787 : bool split_i2i3 = false;
2575 98124787 : bool changed_i3_dest = false;
2576 98124787 : bool i2_was_move = false, i3_was_move = false;
2577 98124787 : int n_auto_inc = 0;
2578 :
2579 98124787 : int maxreg;
2580 98124787 : rtx_insn *temp_insn;
2581 98124787 : rtx temp_expr;
2582 98124787 : struct insn_link *link;
2583 98124787 : rtx other_pat = 0;
2584 98124787 : rtx new_other_notes;
2585 98124787 : int i;
2586 98124787 : scalar_int_mode dest_mode, temp_mode;
2587 98124787 : bool has_non_call_exception = false;
2588 :
2589 : /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2590 : never be). */
2591 98124787 : if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2592 : return 0;
2593 :
2594 : /* Only try four-insn combinations when there's high likelihood of
2595 : success. Look for simple insns, such as loads of constants or
2596 : binary operations involving a constant. */
2597 22535454 : if (i0)
2598 : {
2599 22535454 : int i;
2600 22535454 : int ngood = 0;
2601 22535454 : int nshift = 0;
2602 22535454 : rtx set0, set3;
2603 :
2604 22535454 : if (!flag_expensive_optimizations)
2605 : return 0;
2606 :
2607 88957263 : for (i = 0; i < 4; i++)
2608 : {
2609 72772340 : rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2610 72772340 : rtx set = single_set (insn);
2611 72772340 : rtx src;
2612 72772340 : if (!set)
2613 2321885 : continue;
2614 70450455 : src = SET_SRC (set);
2615 70450455 : if (CONSTANT_P (src))
2616 : {
2617 4869510 : ngood += 2;
2618 4869510 : break;
2619 : }
2620 65580945 : else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2621 8461797 : ngood++;
2622 57119148 : else if (GET_CODE (src) == IF_THEN_ELSE)
2623 2171067 : ngood++;
2624 54948081 : else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2625 54850067 : || GET_CODE (src) == LSHIFTRT)
2626 129722 : nshift++;
2627 : }
2628 :
2629 : /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2630 : are likely manipulating its value. Ideally we'll be able to combine
2631 : all four insns into a bitfield insertion of some kind.
2632 :
2633 : Note the source in I0 might be inside a sign/zero extension and the
2634 : memory modes in I0 and I3 might be different. So extract the address
2635 : from the destination of I3 and search for it in the source of I0.
2636 :
2637 : In the event that there's a match but the source/dest do not actually
2638 : refer to the same memory, the worst that happens is we try some
2639 : combinations that we wouldn't have otherwise. */
2640 21054433 : if ((set0 = single_set (i0))
2641 : /* Ensure the source of SET0 is a MEM, possibly buried inside
2642 : an extension. */
2643 20926680 : && (GET_CODE (SET_SRC (set0)) == MEM
2644 17615452 : || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2645 17615452 : || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2646 551404 : && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2647 3426063 : && (set3 = single_set (i3))
2648 : /* Ensure the destination of SET3 is a MEM. */
2649 2965768 : && GET_CODE (SET_DEST (set3)) == MEM
2650 : /* Would it be better to extract the base address for the MEM
2651 : in SET3 and look for that? I don't have cases where it matters
2652 : but I could envision such cases. */
2653 21355026 : && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2654 22132 : ngood += 2;
2655 :
2656 21054433 : if (ngood < 2 && nshift < 2)
2657 : return 0;
2658 : }
2659 :
2660 : /* Exit early if one of the insns involved can't be used for
2661 : combinations. */
2662 82779460 : if (CALL_P (i2)
2663 77648959 : || (i1 && CALL_P (i1))
2664 74175397 : || (i0 && CALL_P (i0))
2665 73703915 : || cant_combine_insn_p (i3)
2666 70206468 : || cant_combine_insn_p (i2)
2667 53609353 : || (i1 && cant_combine_insn_p (i1))
2668 48402244 : || (i0 && cant_combine_insn_p (i0))
2669 130941835 : || likely_spilled_retval_p (i3))
2670 : return 0;
2671 :
2672 48162329 : combine_attempts++;
2673 48162329 : undobuf.other_insn = 0;
2674 :
2675 : /* Reset the hard register usage information. */
2676 48162329 : CLEAR_HARD_REG_SET (newpat_used_regs);
2677 :
2678 48162329 : if (dump_file && (dump_flags & TDF_DETAILS))
2679 : {
2680 174 : if (i0)
2681 20 : fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2682 20 : INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2683 154 : else if (i1)
2684 26 : fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2685 26 : INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2686 : else
2687 128 : fprintf (dump_file, "\nTrying %d -> %d:\n",
2688 128 : INSN_UID (i2), INSN_UID (i3));
2689 :
2690 174 : if (i0)
2691 20 : dump_insn_slim (dump_file, i0);
2692 174 : if (i1)
2693 46 : dump_insn_slim (dump_file, i1);
2694 174 : dump_insn_slim (dump_file, i2);
2695 174 : dump_insn_slim (dump_file, i3);
2696 : }
2697 :
2698 : /* If multiple insns feed into one of I2 or I3, they can be in any
2699 : order. To simplify the code below, reorder them in sequence. */
2700 48162329 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2701 : std::swap (i0, i2);
2702 48162329 : if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2703 : std::swap (i0, i1);
2704 48162329 : if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2705 : std::swap (i1, i2);
2706 :
2707 48162329 : added_links_insn = 0;
2708 48162329 : added_notes_insn = 0;
2709 :
2710 : /* First check for one important special case that the code below will
2711 : not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2712 : and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2713 : we may be able to replace that destination with the destination of I3.
2714 : This occurs in the common code where we compute both a quotient and
2715 : remainder into a structure, in which case we want to do the computation
2716 : directly into the structure to avoid register-register copies.
2717 :
2718 : Note that this case handles both multiple sets in I2 and also cases
2719 : where I2 has a number of CLOBBERs inside the PARALLEL.
2720 :
2721 : We make very conservative checks below and only try to handle the
2722 : most common cases of this. For example, we only handle the case
2723 : where I2 and I3 are adjacent to avoid making difficult register
2724 : usage tests. */
2725 :
2726 30093463 : if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2727 15644462 : && REG_P (SET_SRC (PATTERN (i3)))
2728 5270183 : && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2729 5028311 : && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2730 4116395 : && GET_CODE (PATTERN (i2)) == PARALLEL
2731 1106886 : && ! side_effects_p (SET_DEST (PATTERN (i3)))
2732 : /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2733 : below would need to check what is inside (and reg_overlap_mentioned_p
2734 : doesn't support those codes anyway). Don't allow those destinations;
2735 : the resulting insn isn't likely to be recognized anyway. */
2736 613948 : && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2737 613928 : && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2738 612717 : && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2739 612717 : SET_DEST (PATTERN (i3)))
2740 48774940 : && next_active_insn (i2) == i3)
2741 : {
2742 401769 : rtx p2 = PATTERN (i2);
2743 :
2744 : /* Make sure that the destination of I3,
2745 : which we are going to substitute into one output of I2,
2746 : is not used within another output of I2. We must avoid making this:
2747 : (parallel [(set (mem (reg 69)) ...)
2748 : (set (reg 69) ...)])
2749 : which is not well-defined as to order of actions.
2750 : (Besides, reload can't handle output reloads for this.)
2751 :
2752 : The problem can also happen if the dest of I3 is a memory ref,
2753 : if another dest in I2 is an indirect memory ref.
2754 :
2755 : Neither can this PARALLEL be an asm. We do not allow combining
2756 : that usually (see can_combine_p), so do not here either. */
2757 401769 : bool ok = true;
2758 1217874 : for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2759 : {
2760 816105 : if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2761 401379 : || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2762 1630790 : && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2763 814685 : SET_DEST (XVECEXP (p2, 0, i))))
2764 : ok = false;
2765 815320 : else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2766 413943 : && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2767 816105 : ok = false;
2768 : }
2769 :
2770 401769 : if (ok)
2771 526008 : for (i = 0; i < XVECLEN (p2, 0); i++)
2772 464621 : if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2773 464621 : && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2774 : {
2775 338455 : combine_merges++;
2776 :
2777 338455 : subst_insn = i3;
2778 338455 : subst_low_luid = DF_INSN_LUID (i2);
2779 :
2780 338455 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2781 338455 : i2src = SET_SRC (XVECEXP (p2, 0, i));
2782 338455 : i2dest = SET_DEST (XVECEXP (p2, 0, i));
2783 338455 : i2dest_killed = dead_or_set_p (i2, i2dest);
2784 :
2785 : /* Replace the dest in I2 with our dest and make the resulting
2786 : insn the new pattern for I3. Then skip to where we validate
2787 : the pattern. Everything was set up above. */
2788 338455 : SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2789 338455 : newpat = p2;
2790 338455 : i3_subst_into_i2 = true;
2791 338455 : goto validate_replacement;
2792 : }
2793 : }
2794 :
2795 : /* If I2 is setting a pseudo to a constant and I3 is setting some
2796 : sub-part of it to another constant, merge them by making a new
2797 : constant. */
2798 47823874 : if (i1 == 0
2799 29755008 : && (temp_expr = single_set (i2)) != 0
2800 29477579 : && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2801 19450325 : && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2802 2891343 : && GET_CODE (PATTERN (i3)) == SET
2803 1438637 : && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2804 47841456 : && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2805 : {
2806 16831 : rtx dest = SET_DEST (PATTERN (i3));
2807 16831 : rtx temp_dest = SET_DEST (temp_expr);
2808 16831 : int offset = -1;
2809 16831 : int width = 0;
2810 :
2811 16831 : if (GET_CODE (dest) == ZERO_EXTRACT)
2812 : {
2813 1 : if (CONST_INT_P (XEXP (dest, 1))
2814 1 : && CONST_INT_P (XEXP (dest, 2))
2815 2 : && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2816 : &dest_mode))
2817 : {
2818 1 : width = INTVAL (XEXP (dest, 1));
2819 1 : offset = INTVAL (XEXP (dest, 2));
2820 1 : dest = XEXP (dest, 0);
2821 1 : if (BITS_BIG_ENDIAN)
2822 : offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2823 : }
2824 : }
2825 : else
2826 : {
2827 16830 : if (GET_CODE (dest) == STRICT_LOW_PART)
2828 431 : dest = XEXP (dest, 0);
2829 16830 : if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2830 : {
2831 16830 : width = GET_MODE_PRECISION (dest_mode);
2832 16830 : offset = 0;
2833 : }
2834 : }
2835 :
2836 16831 : if (offset >= 0)
2837 : {
2838 : /* If this is the low part, we're done. */
2839 16831 : if (subreg_lowpart_p (dest))
2840 : ;
2841 : /* Handle the case where inner is twice the size of outer. */
2842 4980 : else if (GET_MODE_PRECISION (temp_mode)
2843 4980 : == 2 * GET_MODE_PRECISION (dest_mode))
2844 4977 : offset += GET_MODE_PRECISION (dest_mode);
2845 : /* Otherwise give up for now. */
2846 : else
2847 : offset = -1;
2848 : }
2849 :
2850 16828 : if (offset >= 0)
2851 : {
2852 16828 : rtx inner = SET_SRC (PATTERN (i3));
2853 16828 : rtx outer = SET_SRC (temp_expr);
2854 :
2855 33656 : wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2856 16828 : rtx_mode_t (inner, dest_mode),
2857 33656 : offset, width);
2858 :
2859 16828 : combine_merges++;
2860 16828 : subst_insn = i3;
2861 16828 : subst_low_luid = DF_INSN_LUID (i2);
2862 16828 : added_sets_2 = added_sets_1 = added_sets_0 = false;
2863 16828 : i2dest = temp_dest;
2864 16828 : i2dest_killed = dead_or_set_p (i2, i2dest);
2865 :
2866 : /* Replace the source in I2 with the new constant and make the
2867 : resulting insn the new pattern for I3. Then skip to where we
2868 : validate the pattern. Everything was set up above. */
2869 16828 : SUBST (SET_SRC (temp_expr),
2870 : immed_wide_int_const (o, temp_mode));
2871 :
2872 16828 : newpat = PATTERN (i2);
2873 :
2874 : /* The dest of I3 has been replaced with the dest of I2. */
2875 16828 : changed_i3_dest = true;
2876 16828 : goto validate_replacement;
2877 16828 : }
2878 : }
2879 :
2880 : /* If we have no I1 and I2 looks like:
2881 : (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2882 : (set Y OP)])
2883 : make up a dummy I1 that is
2884 : (set Y OP)
2885 : and change I2 to be
2886 : (set (reg:CC X) (compare:CC Y (const_int 0)))
2887 :
2888 : (We can ignore any trailing CLOBBERs.)
2889 :
2890 : This undoes a previous combination and allows us to match a branch-and-
2891 : decrement insn. */
2892 :
2893 47807046 : if (i1 == 0
2894 29738180 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2895 234221 : && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2896 : == MODE_CC)
2897 141881 : && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2898 115291 : && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2899 77308 : && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2900 77308 : SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2901 71960 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2902 47879006 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2903 : {
2904 : /* We make I1 with the same INSN_UID as I2. This gives it
2905 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2906 : never appear in the insn stream so giving it the same INSN_UID
2907 : as I2 will not cause a problem. */
2908 :
2909 143484 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2910 71742 : XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2911 : -1, NULL_RTX);
2912 71742 : INSN_UID (i1) = INSN_UID (i2);
2913 :
2914 71742 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2915 71742 : SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2916 : SET_DEST (PATTERN (i1)));
2917 71742 : unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2918 71742 : SUBST_LINK (LOG_LINKS (i2),
2919 : alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2920 : }
2921 :
2922 : /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2923 : make those two SETs separate I1 and I2 insns, and make an I0 that is
2924 : the original I1. */
2925 47807046 : if (i0 == 0
2926 45066521 : && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2927 363993 : && can_split_parallel_of_n_reg_sets (i2, 2)
2928 309833 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2929 279334 : && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2930 262921 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2931 48069958 : && !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2932 : {
2933 : /* If there is no I1, there is no I0 either. */
2934 262912 : i0 = i1;
2935 :
2936 : /* We make I1 with the same INSN_UID as I2. This gives it
2937 : the same DF_INSN_LUID for value tracking. Our fake I1 will
2938 : never appear in the insn stream so giving it the same INSN_UID
2939 : as I2 will not cause a problem. */
2940 :
2941 525824 : i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2942 262912 : XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2943 : -1, NULL_RTX);
2944 262912 : INSN_UID (i1) = INSN_UID (i2);
2945 :
2946 262912 : SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2947 : }
2948 :
2949 : /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2950 47807046 : if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2951 : {
2952 12220862 : if (dump_file && (dump_flags & TDF_DETAILS))
2953 8 : fprintf (dump_file, "Can't combine i2 into i3\n");
2954 12220862 : undo_all ();
2955 12220862 : return 0;
2956 : }
2957 35586184 : if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2958 : {
2959 1406717 : if (dump_file && (dump_flags & TDF_DETAILS))
2960 0 : fprintf (dump_file, "Can't combine i1 into i3\n");
2961 1406717 : undo_all ();
2962 1406717 : return 0;
2963 : }
2964 34179467 : if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2965 : {
2966 237663 : if (dump_file && (dump_flags & TDF_DETAILS))
2967 0 : fprintf (dump_file, "Can't combine i0 into i3\n");
2968 237663 : undo_all ();
2969 237663 : return 0;
2970 : }
2971 :
2972 : /* With non-call exceptions we can end up trying to combine multiple
2973 : insns with possible EH side effects. Make sure we can combine
2974 : that to a single insn which means there must be at most one insn
2975 : in the combination with an EH side effect. */
2976 33941804 : if (cfun->can_throw_non_call_exceptions)
2977 : {
2978 6115723 : if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2979 6092135 : || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2980 6092053 : || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2981 12207775 : || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2982 : {
2983 23671 : has_non_call_exception = true;
2984 23671 : if (insn_could_throw_p (i3)
2985 23671 : + insn_could_throw_p (i2)
2986 23671 : + (i1 ? insn_could_throw_p (i1) : 0)
2987 23671 : + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2988 : {
2989 172 : if (dump_file && (dump_flags & TDF_DETAILS))
2990 0 : fprintf (dump_file, "Can't combine multiple insns with EH "
2991 : "side-effects\n");
2992 172 : undo_all ();
2993 172 : return 0;
2994 : }
2995 : }
2996 : }
2997 :
2998 : /* Record whether i2 and i3 are trivial moves. */
2999 33941632 : i2_was_move = is_just_move (i2);
3000 33941632 : i3_was_move = is_just_move (i3);
3001 :
3002 : /* Record whether I2DEST is used in I2SRC and similarly for the other
3003 : cases. Knowing this will help in register status updating below. */
3004 33941632 : i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
3005 33941632 : i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
3006 10928651 : i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
3007 33941632 : i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
3008 1972772 : i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
3009 1972772 : i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
3010 33941632 : i2dest_killed = dead_or_set_p (i2, i2dest);
3011 33941632 : i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
3012 33941632 : i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
3013 :
3014 : /* For the earlier insns, determine which of the subsequent ones they
3015 : feed. */
3016 33941632 : i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3017 33941632 : i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3018 3439112 : i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3019 1466340 : : (!reg_overlap_mentioned_p (i1dest, i0dest)
3020 1433612 : && reg_overlap_mentioned_p (i0dest, i2src))));
3021 :
3022 : /* Ensure that I3's pattern can be the destination of combines. */
3023 44870283 : if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3024 10928651 : i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3025 1972772 : i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3026 1943836 : || (i1dest_in_i0src && !i0_feeds_i1_n)),
3027 : &i3dest_killed))
3028 : {
3029 192913 : undo_all ();
3030 192913 : return 0;
3031 : }
3032 :
3033 : /* See if any of the insns is a MULT operation. Unless one is, we will
3034 : reject a combination that is, since it must be slower. Be conservative
3035 : here. */
3036 33748719 : if (GET_CODE (i2src) == MULT
3037 32885244 : || (i1 != 0 && GET_CODE (i1src) == MULT)
3038 32533310 : || (i0 != 0 && GET_CODE (i0src) == MULT)
3039 66233092 : || (GET_CODE (PATTERN (i3)) == SET
3040 25421682 : && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3041 : have_mult = true;
3042 :
3043 : /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3044 : We used to do this EXCEPT in one case: I3 has a post-inc in an
3045 : output operand. However, that exception can give rise to insns like
3046 : mov r3,(r3)+
3047 : which is a famous insn on the PDP-11 where the value of r3 used as the
3048 : source was model-dependent. Avoid this sort of thing. */
3049 :
3050 : #if 0
3051 : if (!(GET_CODE (PATTERN (i3)) == SET
3052 : && REG_P (SET_SRC (PATTERN (i3)))
3053 : && MEM_P (SET_DEST (PATTERN (i3)))
3054 : && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3055 : || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3056 : /* It's not the exception. */
3057 : #endif
3058 33748719 : if (AUTO_INC_DEC)
3059 : {
3060 : rtx link;
3061 : for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3062 : if (REG_NOTE_KIND (link) == REG_INC
3063 : && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3064 : || (i1 != 0
3065 : && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3066 : {
3067 : undo_all ();
3068 : return 0;
3069 : }
3070 : }
3071 :
3072 : /* See if the SETs in I1 or I2 need to be kept around in the merged
3073 : instruction: whenever the value set there is still needed past I3.
3074 : For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3075 :
3076 : For the SET in I1, we have two cases: if I1 and I2 independently feed
3077 : into I3, the set in I1 needs to be kept around unless I1DEST dies
3078 : or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3079 : in I1 needs to be kept around unless I1DEST dies or is set in either
3080 : I2 or I3. The same considerations apply to I0. */
3081 :
3082 33748719 : added_sets_2 = !dead_or_set_p (i3, i2dest);
3083 :
3084 33748719 : if (i1)
3085 10861387 : added_sets_1 = !(dead_or_set_p (i3, i1dest)
3086 8311470 : || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3087 : else
3088 : added_sets_1 = false;
3089 :
3090 33748719 : if (i0)
3091 2856629 : added_sets_0 = !(dead_or_set_p (i3, i0dest)
3092 1761800 : || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3093 354413 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3094 853157 : && dead_or_set_p (i2, i0dest)));
3095 : else
3096 : added_sets_0 = false;
3097 :
3098 : /* We are about to copy insns for the case where they need to be kept
3099 : around. Check that they can be copied in the merged instruction. */
3100 :
3101 33748719 : if (targetm.cannot_copy_insn_p
3102 33748719 : && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3103 0 : || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3104 0 : || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3105 : {
3106 0 : undo_all ();
3107 0 : return 0;
3108 : }
3109 :
3110 : /* We cannot safely duplicate volatile references in any case. */
3111 :
3112 7567600 : if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3113 33712454 : || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3114 67432883 : || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3115 : {
3116 66808 : undo_all ();
3117 66808 : return 0;
3118 : }
3119 :
3120 : /* Count how many auto_inc expressions there were in the original insns;
3121 : we need to have the same number in the resulting patterns. */
3122 :
3123 33681911 : if (i0)
3124 1931822 : for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3125 33681911 : if (i1)
3126 10829384 : for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3127 33681911 : for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3128 33681911 : for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3129 :
3130 : /* If the set in I2 needs to be kept around, we must make a copy of
3131 : PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3132 : PATTERN (I2), we are only substituting for the original I1DEST, not into
3133 : an already-substituted copy. This also prevents making self-referential
3134 : rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3135 : I2DEST. */
3136 :
3137 33681911 : if (added_sets_2)
3138 : {
3139 7528406 : if (GET_CODE (PATTERN (i2)) == PARALLEL)
3140 2332361 : i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3141 : else
3142 5196045 : i2pat = copy_rtx (PATTERN (i2));
3143 : }
3144 :
3145 33681911 : if (added_sets_1)
3146 : {
3147 4097386 : if (GET_CODE (PATTERN (i1)) == PARALLEL)
3148 1292396 : i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3149 : else
3150 2804990 : i1pat = copy_rtx (PATTERN (i1));
3151 : }
3152 :
3153 33681911 : if (added_sets_0)
3154 : {
3155 534286 : if (GET_CODE (PATTERN (i0)) == PARALLEL)
3156 203112 : i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3157 : else
3158 331174 : i0pat = copy_rtx (PATTERN (i0));
3159 : }
3160 :
3161 33681911 : combine_merges++;
3162 :
3163 : /* Substitute in the latest insn for the regs set by the earlier ones. */
3164 :
3165 33681911 : maxreg = max_reg_num ();
3166 :
3167 33681911 : subst_insn = i3;
3168 :
3169 : /* Many machines have insns that can both perform an
3170 : arithmetic operation and set the condition code. These operations will
3171 : be represented as a PARALLEL with the first element of the vector
3172 : being a COMPARE of an arithmetic operation with the constant zero.
3173 : The second element of the vector will set some pseudo to the result
3174 : of the same arithmetic operation. If we simplify the COMPARE, we won't
3175 : match such a pattern and so will generate an extra insn. Here we test
3176 : for this case, where both the comparison and the operation result are
3177 : needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3178 : I2SRC. Later we will make the PARALLEL that contains I2. */
3179 :
3180 22852527 : if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3181 4328244 : && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3182 1845813 : && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3183 34582333 : && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3184 : {
3185 829035 : rtx newpat_dest;
3186 829035 : rtx *cc_use_loc = NULL;
3187 829035 : rtx_insn *cc_use_insn = NULL;
3188 829035 : rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3189 829035 : machine_mode compare_mode, orig_compare_mode;
3190 829035 : enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3191 829035 : scalar_int_mode mode;
3192 :
3193 829035 : newpat = PATTERN (i3);
3194 829035 : newpat_dest = SET_DEST (newpat);
3195 829035 : compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3196 :
3197 829035 : if (undobuf.other_insn == 0
3198 829035 : && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3199 : &cc_use_insn)))
3200 : {
3201 822428 : compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3202 822428 : if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3203 822428 : compare_code = simplify_compare_const (compare_code, mode,
3204 : &op0, &op1);
3205 822428 : target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3206 : }
3207 :
3208 : /* Do the rest only if op1 is const0_rtx, which may be the
3209 : result of simplification. */
3210 829035 : if (op1 == const0_rtx)
3211 : {
3212 : /* If a single use of the CC is found, prepare to modify it
3213 : when SELECT_CC_MODE returns a new CC-class mode, or when
3214 : the above simplify_compare_const() returned a new comparison
3215 : operator. undobuf.other_insn is assigned the CC use insn
3216 : when modifying it. */
3217 521006 : if (cc_use_loc)
3218 : {
3219 : #ifdef SELECT_CC_MODE
3220 518170 : machine_mode new_mode
3221 518170 : = SELECT_CC_MODE (compare_code, op0, op1);
3222 518170 : if (new_mode != orig_compare_mode
3223 518170 : && can_change_dest_mode (SET_DEST (newpat),
3224 : added_sets_2, new_mode))
3225 : {
3226 523 : unsigned int regno = REGNO (newpat_dest);
3227 523 : compare_mode = new_mode;
3228 523 : if (regno < FIRST_PSEUDO_REGISTER)
3229 523 : newpat_dest = gen_rtx_REG (compare_mode, regno);
3230 : else
3231 : {
3232 0 : subst_mode (regno, compare_mode);
3233 0 : newpat_dest = regno_reg_rtx[regno];
3234 : }
3235 : }
3236 : #endif
3237 : /* Cases for modifying the CC-using comparison. */
3238 518170 : if (compare_code != orig_compare_code
3239 545 : && COMPARISON_P (*cc_use_loc))
3240 : {
3241 : /* Replace cc_use_loc with entire new RTX. */
3242 545 : SUBST (*cc_use_loc,
3243 : gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3244 : newpat_dest, const0_rtx));
3245 545 : undobuf.other_insn = cc_use_insn;
3246 : }
3247 517625 : else if (compare_mode != orig_compare_mode)
3248 : {
3249 1 : subrtx_ptr_iterator::array_type array;
3250 :
3251 : /* Just replace the CC reg with a new mode. */
3252 4 : FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3253 : {
3254 3 : rtx *loc = *iter;
3255 3 : if (REG_P (*loc)
3256 3 : && REGNO (*loc) == REGNO (newpat_dest))
3257 : {
3258 1 : SUBST (*loc, newpat_dest);
3259 1 : iter.skip_subrtxes ();
3260 : }
3261 : }
3262 1 : undobuf.other_insn = cc_use_insn;
3263 1 : }
3264 : }
3265 :
3266 : /* Now we modify the current newpat:
3267 : First, SET_DEST(newpat) is updated if the CC mode has been
3268 : altered. For targets without SELECT_CC_MODE, this should be
3269 : optimized away. */
3270 521006 : if (compare_mode != orig_compare_mode)
3271 523 : SUBST (SET_DEST (newpat), newpat_dest);
3272 : /* This is always done to propagate i2src into newpat. */
3273 521006 : SUBST (SET_SRC (newpat),
3274 : gen_rtx_COMPARE (compare_mode, op0, op1));
3275 : /* Create new version of i2pat if needed; the below PARALLEL
3276 : creation needs this to work correctly. */
3277 521006 : if (! rtx_equal_p (i2src, op0))
3278 27 : i2pat = gen_rtx_SET (i2dest, op0);
3279 : i2_is_used = 1;
3280 : }
3281 : }
3282 :
3283 829035 : if (i2_is_used == 0)
3284 : {
3285 : /* It is possible that the source of I2 or I1 may be performing
3286 : an unneeded operation, such as a ZERO_EXTEND of something
3287 : that is known to have the high part zero. Handle that case
3288 : by letting subst look at the inner insns.
3289 :
3290 : Another way to do this would be to have a function that tries
3291 : to simplify a single insn instead of merging two or more
3292 : insns. We don't do this because of the potential of infinite
3293 : loops and because of the potential extra memory required.
3294 : However, doing it the way we are is a bit of a kludge and
3295 : doesn't catch all cases.
3296 :
3297 : But only do this if -fexpensive-optimizations since it slows
3298 : things down and doesn't usually win.
3299 :
3300 : This is not done in the COMPARE case above because the
3301 : unmodified I2PAT is used in the PARALLEL and so a pattern
3302 : with a modified I2SRC would not match. */
3303 :
3304 33160905 : if (flag_expensive_optimizations)
3305 : {
3306 : /* Pass pc_rtx so no substitutions are done, just
3307 : simplifications. */
3308 30903517 : if (i1)
3309 : {
3310 10161385 : subst_low_luid = DF_INSN_LUID (i1);
3311 10161385 : i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3312 : }
3313 :
3314 30903517 : subst_low_luid = DF_INSN_LUID (i2);
3315 30903517 : i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3316 : }
3317 :
3318 33160905 : n_occurrences = 0; /* `subst' counts here */
3319 33160905 : subst_low_luid = DF_INSN_LUID (i2);
3320 :
3321 : /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3322 : copy of I2SRC each time we substitute it, in order to avoid creating
3323 : self-referential RTL when we will be substituting I1SRC for I1DEST
3324 : later. Likewise if I0 feeds into I2, either directly or indirectly
3325 : through I1, and I0DEST is in I0SRC. */
3326 65699451 : newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3327 33160905 : (i1_feeds_i2_n && i1dest_in_i1src)
3328 31926514 : || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3329 : && i0dest_in_i0src));
3330 33160905 : substed_i2 = true;
3331 :
3332 : /* Record whether I2's body now appears within I3's body. */
3333 33160905 : i2_is_used = n_occurrences;
3334 : }
3335 :
3336 : /* If we already got a failure, don't try to do more. Otherwise, try to
3337 : substitute I1 if we have it. */
3338 :
3339 33681911 : if (i1 && GET_CODE (newpat) != CLOBBER)
3340 : {
3341 : /* Before we can do this substitution, we must redo the test done
3342 : above (see detailed comments there) that ensures I1DEST isn't
3343 : mentioned in any SETs in NEWPAT that are field assignments. */
3344 10785017 : if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3345 : false, false, 0))
3346 : {
3347 16 : undo_all ();
3348 16 : return 0;
3349 : }
3350 :
3351 10785001 : n_occurrences = 0;
3352 10785001 : subst_low_luid = DF_INSN_LUID (i1);
3353 :
3354 : /* If the following substitution will modify I1SRC, make a copy of it
3355 : for the case where it is substituted for I1DEST in I2PAT later. */
3356 10785001 : if (added_sets_2 && i1_feeds_i2_n)
3357 1517665 : i1src_copy = copy_rtx (i1src);
3358 :
3359 : /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3360 : copy of I1SRC each time we substitute it, in order to avoid creating
3361 : self-referential RTL when we will be substituting I0SRC for I0DEST
3362 : later. */
3363 10785001 : newpat = subst (newpat, i1dest, i1src, false, false,
3364 : i0_feeds_i1_n && i0dest_in_i0src);
3365 10785001 : substed_i1 = true;
3366 :
3367 : /* Record whether I1's body now appears within I3's body. */
3368 10785001 : i1_is_used = n_occurrences;
3369 : }
3370 :
3371 : /* Likewise for I0 if we have it. */
3372 :
3373 33681895 : if (i0 && GET_CODE (newpat) != CLOBBER)
3374 : {
3375 1912674 : if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3376 : false, false, 0))
3377 : {
3378 0 : undo_all ();
3379 0 : return 0;
3380 : }
3381 :
3382 : /* If the following substitution will modify I0SRC, make a copy of it
3383 : for the case where it is substituted for I0DEST in I1PAT later. */
3384 1912674 : if (added_sets_1 && i0_feeds_i1_n)
3385 370955 : i0src_copy = copy_rtx (i0src);
3386 : /* And a copy for I0DEST in I2PAT substitution. */
3387 1912674 : if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3388 211476 : || (i0_feeds_i2_n)))
3389 346719 : i0src_copy2 = copy_rtx (i0src);
3390 :
3391 1912674 : n_occurrences = 0;
3392 1912674 : subst_low_luid = DF_INSN_LUID (i0);
3393 1912674 : newpat = subst (newpat, i0dest, i0src, false, false, false);
3394 1912674 : substed_i0 = true;
3395 : }
3396 :
3397 33681895 : if (n_auto_inc)
3398 : {
3399 511974 : int new_n_auto_inc = 0;
3400 511974 : for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3401 :
3402 511974 : if (n_auto_inc != new_n_auto_inc)
3403 : {
3404 1024 : if (dump_file && (dump_flags & TDF_DETAILS))
3405 0 : fprintf (dump_file, "Number of auto_inc expressions changed\n");
3406 1024 : undo_all ();
3407 1024 : return 0;
3408 : }
3409 : }
3410 :
3411 : /* Fail if an autoincrement side-effect has been duplicated. Be careful
3412 : to count all the ways that I2SRC and I1SRC can be used. */
3413 33680871 : if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3414 : && i2_is_used + added_sets_2 > 1)
3415 : || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3416 : && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3417 : || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3418 : && (n_occurrences + added_sets_0
3419 : + (added_sets_1 && i0_feeds_i1_n)
3420 : + (added_sets_2 && i0_feeds_i2_n) > 1))
3421 : /* Fail if we tried to make a new register. */
3422 33680871 : || max_reg_num () != maxreg
3423 : /* Fail if we couldn't do something and have a CLOBBER. */
3424 33680871 : || GET_CODE (newpat) == CLOBBER
3425 : /* Fail if this new pattern is a MULT and we didn't have one before
3426 : at the outer level. */
3427 67005461 : || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3428 309766 : && ! have_mult))
3429 : {
3430 387669 : undo_all ();
3431 387669 : return 0;
3432 : }
3433 :
3434 : /* If the actions of the earlier insns must be kept
3435 : in addition to substituting them into the latest one,
3436 : we must make a new PARALLEL for the latest insn
3437 : to hold additional the SETs. */
3438 :
3439 33293202 : if (added_sets_0 || added_sets_1 || added_sets_2)
3440 : {
3441 11083061 : int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3442 11083061 : combine_extras++;
3443 :
3444 11083061 : if (GET_CODE (newpat) == PARALLEL)
3445 : {
3446 2253747 : rtvec old = XVEC (newpat, 0);
3447 2253747 : total_sets = XVECLEN (newpat, 0) + extra_sets;
3448 2253747 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3449 2253747 : memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3450 2253747 : sizeof (old->elem[0]) * old->num_elem);
3451 : }
3452 : else
3453 : {
3454 8829314 : rtx old = newpat;
3455 8829314 : total_sets = 1 + extra_sets;
3456 8829314 : newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3457 8829314 : XVECEXP (newpat, 0, 0) = old;
3458 : }
3459 :
3460 11083061 : if (added_sets_0)
3461 514929 : XVECEXP (newpat, 0, --total_sets) = i0pat;
3462 :
3463 11083061 : if (added_sets_1)
3464 : {
3465 4045598 : rtx t = i1pat;
3466 4045598 : if (i0_feeds_i1_n)
3467 367414 : t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3468 : false, false, false);
3469 :
3470 4045598 : XVECEXP (newpat, 0, --total_sets) = t;
3471 : }
3472 11083061 : if (added_sets_2)
3473 : {
3474 7449753 : rtx t = i2pat;
3475 7449753 : if (i1_feeds_i2_n)
3476 1498847 : t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3477 : i0_feeds_i1_n && i0dest_in_i0src);
3478 7449753 : if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3479 342224 : t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3480 : false, false, false);
3481 :
3482 7449753 : XVECEXP (newpat, 0, --total_sets) = t;
3483 : }
3484 : }
3485 :
3486 25843449 : validate_replacement:
3487 :
3488 : /* Note which hard regs this insn has as inputs. */
3489 33648485 : mark_used_regs_combine (newpat);
3490 :
3491 : /* If recog_for_combine fails, it strips existing clobbers. If we'll
3492 : consider splitting this pattern, we might need these clobbers. */
3493 33648485 : if (i1 && GET_CODE (newpat) == PARALLEL
3494 7456592 : && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3495 : {
3496 1730399 : int len = XVECLEN (newpat, 0);
3497 :
3498 1730399 : newpat_vec_with_clobbers = rtvec_alloc (len);
3499 6972265 : for (i = 0; i < len; i++)
3500 3511467 : RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3501 : }
3502 :
3503 : /* We have recognized nothing yet. */
3504 33648485 : insn_code_number = -1;
3505 :
3506 : /* See if this is a PARALLEL of two SETs where one SET's destination is
3507 : a register that is unused and this isn't marked as an instruction that
3508 : might trap in an EH region. In that case, we just need the other SET.
3509 : We prefer this over the PARALLEL.
3510 :
3511 : This can occur when simplifying a divmod insn. We *must* test for this
3512 : case here because the code below that splits two independent SETs doesn't
3513 : handle this case correctly when it updates the register status.
3514 :
3515 : It's pointless doing this if we originally had two sets, one from
3516 : i3, and one from i2. Combining then splitting the parallel results
3517 : in the original i2 again plus an invalid insn (which we delete).
3518 : The net effect is only to move instructions around, which makes
3519 : debug info less accurate.
3520 :
3521 : If the remaining SET came from I2 its destination should not be used
3522 : between I2 and I3. See PR82024. */
3523 :
3524 7449753 : if (!(added_sets_2 && i1 == 0)
3525 28225191 : && is_parallel_of_n_reg_sets (newpat, 2)
3526 35277901 : && asm_noperands (newpat) < 0)
3527 : {
3528 1628522 : rtx set0 = XVECEXP (newpat, 0, 0);
3529 1628522 : rtx set1 = XVECEXP (newpat, 0, 1);
3530 1628522 : rtx oldpat = newpat;
3531 :
3532 1628522 : if (((REG_P (SET_DEST (set1))
3533 1628522 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3534 1587193 : || (GET_CODE (SET_DEST (set1)) == SUBREG
3535 0 : && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3536 41329 : && insn_nothrow_p (i3)
3537 1668622 : && !side_effects_p (SET_SRC (set1)))
3538 : {
3539 39861 : newpat = set0;
3540 39861 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3541 : }
3542 :
3543 1588661 : else if (((REG_P (SET_DEST (set0))
3544 1588661 : && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3545 1563446 : || (GET_CODE (SET_DEST (set0)) == SUBREG
3546 0 : && find_reg_note (i3, REG_UNUSED,
3547 0 : SUBREG_REG (SET_DEST (set0)))))
3548 25215 : && insn_nothrow_p (i3)
3549 1613275 : && !side_effects_p (SET_SRC (set0)))
3550 : {
3551 24571 : rtx dest = SET_DEST (set1);
3552 24571 : if (GET_CODE (dest) == SUBREG)
3553 0 : dest = SUBREG_REG (dest);
3554 24571 : if (!reg_used_between_p (dest, i2, i3))
3555 : {
3556 24570 : newpat = set1;
3557 24570 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3558 :
3559 24570 : if (insn_code_number >= 0)
3560 : changed_i3_dest = true;
3561 : }
3562 : }
3563 :
3564 39861 : if (insn_code_number < 0)
3565 1622926 : newpat = oldpat;
3566 : }
3567 :
3568 : /* Is the result of combination a valid instruction? */
3569 1622926 : if (insn_code_number < 0)
3570 33642889 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3571 :
3572 : /* If we were combining three insns and the result is a simple SET
3573 : with no ASM_OPERANDS that wasn't recognized, try to split it into two
3574 : insns. There are two ways to do this. It can be split using a
3575 : machine-specific method (like when you have an addition of a large
3576 : constant) or by combine in the function find_split_point. */
3577 :
3578 10625303 : if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3579 38459638 : && asm_noperands (newpat) < 0)
3580 : {
3581 4810596 : rtx parallel, *split;
3582 4810596 : rtx_insn *m_split_insn;
3583 4810596 : unsigned int old_nregs, new_nregs;
3584 :
3585 : /* See if the MD file can split NEWPAT. If it can't, see if letting it
3586 : use I2DEST as a scratch register will help. In the latter case,
3587 : convert I2DEST to the mode of the source of NEWPAT if we can. */
3588 :
3589 4810596 : m_split_insn = combine_split_insns (newpat, i3, &old_nregs, &new_nregs);
3590 :
3591 : /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3592 : inputs of NEWPAT. */
3593 :
3594 : /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3595 : possible to try that as a scratch reg. This would require adding
3596 : more code to make it work though. */
3597 :
3598 4810596 : if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3599 : {
3600 4669482 : machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3601 :
3602 : /* ??? Reusing i2dest without resetting the reg_stat entry for it
3603 : (temporarily, until we are committed to this instruction
3604 : combination) does not work: for example, any call to nonzero_bits
3605 : on the register (from a splitter in the MD file, for example)
3606 : will get the old information, which is invalid.
3607 :
3608 : Since nowadays we can create registers during combine just fine,
3609 : we should just create a new one here, not reuse i2dest. */
3610 :
3611 : /* First try to split using the original register as a
3612 : scratch register. */
3613 4669482 : parallel = gen_rtx_PARALLEL (VOIDmode,
3614 : gen_rtvec (2, newpat,
3615 : gen_rtx_CLOBBER (VOIDmode,
3616 : i2dest)));
3617 4669482 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3618 :
3619 : /* If that didn't work, try changing the mode of I2DEST if
3620 : we can. */
3621 4669482 : if (m_split_insn == 0
3622 4669482 : && new_mode != GET_MODE (i2dest)
3623 1792443 : && new_mode != VOIDmode
3624 5872454 : && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3625 : {
3626 885293 : machine_mode old_mode = GET_MODE (i2dest);
3627 885293 : rtx ni2dest;
3628 :
3629 885293 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3630 8752 : ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3631 : else
3632 : {
3633 876541 : subst_mode (REGNO (i2dest), new_mode);
3634 876541 : ni2dest = regno_reg_rtx[REGNO (i2dest)];
3635 : }
3636 :
3637 885293 : parallel = (gen_rtx_PARALLEL
3638 : (VOIDmode,
3639 : gen_rtvec (2, newpat,
3640 : gen_rtx_CLOBBER (VOIDmode,
3641 : ni2dest))));
3642 885293 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3643 :
3644 885293 : if (m_split_insn == 0
3645 885293 : && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3646 : {
3647 876541 : struct undo *buf;
3648 :
3649 876541 : adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3650 876541 : buf = undobuf.undos;
3651 876541 : undobuf.undos = buf->next;
3652 876541 : buf->next = undobuf.frees;
3653 876541 : undobuf.frees = buf;
3654 : }
3655 : }
3656 :
3657 4669482 : i2scratch = m_split_insn != 0;
3658 : }
3659 :
3660 : /* If recog_for_combine has discarded clobbers, try to use them
3661 : again for the split. */
3662 4810596 : if (m_split_insn == 0 && newpat_vec_with_clobbers)
3663 : {
3664 1678854 : parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3665 1678854 : m_split_insn = combine_split_insns (parallel, i3, &old_nregs, &new_nregs);
3666 : }
3667 :
3668 4822350 : if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3669 : {
3670 1648 : rtx m_split_pat = PATTERN (m_split_insn);
3671 1648 : insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes,
3672 : old_nregs, new_nregs);
3673 1648 : if (insn_code_number >= 0)
3674 251 : newpat = m_split_pat;
3675 : }
3676 10106 : else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3677 4819054 : && (next_nonnote_nondebug_insn (i2) == i3
3678 6 : || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3679 : {
3680 10106 : rtx i2set, i3set;
3681 10106 : rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3682 10106 : newi2pat = PATTERN (m_split_insn);
3683 :
3684 10106 : i3set = single_set (NEXT_INSN (m_split_insn));
3685 10106 : i2set = single_set (m_split_insn);
3686 :
3687 10106 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3688 :
3689 : /* If I2 or I3 has multiple SETs, we won't know how to track
3690 : register status, so don't use these insns. If I2's destination
3691 : is used between I2 and I3, we also can't use these insns. */
3692 :
3693 10106 : if (i2_code_number >= 0 && i2set && i3set
3694 20212 : && (next_nonnote_nondebug_insn (i2) == i3
3695 6 : || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3696 10106 : insn_code_number = recog_for_combine (&newi3pat, i3,
3697 : &new_i3_notes,
3698 : old_nregs, new_nregs);
3699 10106 : if (insn_code_number >= 0)
3700 10106 : newpat = newi3pat;
3701 :
3702 : /* It is possible that both insns now set the destination of I3.
3703 : If so, we must show an extra use of it. */
3704 :
3705 10106 : if (insn_code_number >= 0)
3706 : {
3707 10106 : rtx new_i3_dest = SET_DEST (i3set);
3708 10106 : rtx new_i2_dest = SET_DEST (i2set);
3709 :
3710 10106 : while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3711 10146 : || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3712 20274 : || GET_CODE (new_i3_dest) == SUBREG)
3713 40 : new_i3_dest = XEXP (new_i3_dest, 0);
3714 :
3715 10106 : while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3716 10106 : || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3717 20212 : || GET_CODE (new_i2_dest) == SUBREG)
3718 0 : new_i2_dest = XEXP (new_i2_dest, 0);
3719 :
3720 10106 : if (REG_P (new_i3_dest)
3721 5733 : && REG_P (new_i2_dest)
3722 5733 : && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3723 10106 : && REGNO (new_i2_dest) < reg_n_sets_max)
3724 0 : INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3725 : }
3726 : }
3727 :
3728 : /* If we can split it and use I2DEST, go ahead and see if that
3729 : helps things be recognized. Verify that none of the registers
3730 : are set between I2 and I3. */
3731 1397 : if (insn_code_number < 0
3732 4800239 : && (split = find_split_point (&newpat, i3, false)) != 0
3733 : /* We need I2DEST in the proper mode. If it is a hard register
3734 : or the only use of a pseudo, we can change its mode.
3735 : Make sure we don't change a hard register to have a mode that
3736 : isn't valid for it, or change the number of registers. */
3737 4530992 : && (GET_MODE (*split) == GET_MODE (i2dest)
3738 1685997 : || GET_MODE (*split) == VOIDmode
3739 1306597 : || can_change_dest_mode (i2dest, added_sets_2,
3740 : GET_MODE (*split)))
3741 3786907 : && (next_nonnote_nondebug_insn (i2) == i3
3742 583670 : || !modified_between_p (*split, i2, i3))
3743 : /* We can't overwrite I2DEST if its value is still used by
3744 : NEWPAT. */
3745 3757787 : && ! reg_referenced_p (i2dest, newpat)
3746 : /* We should not split a possibly trapping part when we
3747 : care about non-call EH and have REG_EH_REGION notes
3748 : to distribute. */
3749 8490693 : && ! (cfun->can_throw_non_call_exceptions
3750 396601 : && has_non_call_exception
3751 121 : && may_trap_p (*split)))
3752 : {
3753 3681373 : rtx newdest = i2dest;
3754 3681373 : enum rtx_code split_code = GET_CODE (*split);
3755 3681373 : machine_mode split_mode = GET_MODE (*split);
3756 3681373 : bool subst_done = false;
3757 3681373 : newi2pat = NULL_RTX;
3758 :
3759 3681373 : i2scratch = true;
3760 :
3761 : /* *SPLIT may be part of I2SRC, so make sure we have the
3762 : original expression around for later debug processing.
3763 : We should not need I2SRC any more in other cases. */
3764 3681373 : if (MAY_HAVE_DEBUG_BIND_INSNS)
3765 1831557 : i2src = copy_rtx (i2src);
3766 : else
3767 : i2src = NULL;
3768 :
3769 : /* Get NEWDEST as a register in the proper mode. We have already
3770 : validated that we can do this. */
3771 3681373 : if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3772 : {
3773 559008 : if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3774 0 : newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3775 : else
3776 : {
3777 559008 : subst_mode (REGNO (i2dest), split_mode);
3778 559008 : newdest = regno_reg_rtx[REGNO (i2dest)];
3779 : }
3780 : }
3781 :
3782 : /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3783 : an ASHIFT. This can occur if it was inside a PLUS and hence
3784 : appeared to be a memory address. This is a kludge. */
3785 3681373 : if (split_code == MULT
3786 202245 : && CONST_INT_P (XEXP (*split, 1))
3787 100315 : && INTVAL (XEXP (*split, 1)) > 0
3788 3777347 : && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3789 : {
3790 66889 : rtx i_rtx = gen_int_shift_amount (split_mode, i);
3791 66889 : SUBST (*split, gen_rtx_ASHIFT (split_mode,
3792 : XEXP (*split, 0), i_rtx));
3793 : /* Update split_code because we may not have a multiply
3794 : anymore. */
3795 66889 : split_code = GET_CODE (*split);
3796 : }
3797 :
3798 : /* Similarly for (plus (mult FOO (const_int pow2))). */
3799 3681373 : if (split_code == PLUS
3800 720515 : && GET_CODE (XEXP (*split, 0)) == MULT
3801 113836 : && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3802 39147 : && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3803 3717066 : && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3804 : {
3805 6938 : rtx nsplit = XEXP (*split, 0);
3806 6938 : rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3807 6938 : SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3808 : XEXP (nsplit, 0),
3809 : i_rtx));
3810 : /* Update split_code because we may not have a multiply
3811 : anymore. */
3812 6938 : split_code = GET_CODE (*split);
3813 : }
3814 :
3815 : #ifdef INSN_SCHEDULING
3816 : /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3817 : be written as a ZERO_EXTEND. */
3818 3681373 : if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3819 : {
3820 : /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3821 : what it really is. */
3822 10367 : if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3823 : == SIGN_EXTEND)
3824 : SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3825 : SUBREG_REG (*split)));
3826 : else
3827 10367 : SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3828 : SUBREG_REG (*split)));
3829 : }
3830 : #endif
3831 :
3832 : /* Attempt to split binary operators using arithmetic identities. */
3833 3681373 : if (BINARY_P (SET_SRC (newpat))
3834 3082536 : && split_mode == GET_MODE (SET_SRC (newpat))
3835 5806763 : && ! side_effects_p (SET_SRC (newpat)))
3836 : {
3837 2110514 : rtx setsrc = SET_SRC (newpat);
3838 2110514 : machine_mode mode = GET_MODE (setsrc);
3839 2110514 : enum rtx_code code = GET_CODE (setsrc);
3840 2110514 : rtx src_op0 = XEXP (setsrc, 0);
3841 2110514 : rtx src_op1 = XEXP (setsrc, 1);
3842 :
3843 : /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3844 2110514 : if (rtx_equal_p (src_op0, src_op1))
3845 : {
3846 1568 : newi2pat = gen_rtx_SET (newdest, src_op0);
3847 1568 : SUBST (XEXP (setsrc, 0), newdest);
3848 1568 : SUBST (XEXP (setsrc, 1), newdest);
3849 1568 : subst_done = true;
3850 : }
3851 : /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3852 2108946 : else if ((code == PLUS || code == MULT)
3853 1111653 : && GET_CODE (src_op0) == code
3854 423180 : && GET_CODE (XEXP (src_op0, 0)) == code
3855 181733 : && (INTEGRAL_MODE_P (mode)
3856 : || (FLOAT_MODE_P (mode)
3857 98758 : && flag_unsafe_math_optimizations)))
3858 : {
3859 86776 : rtx p = XEXP (XEXP (src_op0, 0), 0);
3860 86776 : rtx q = XEXP (XEXP (src_op0, 0), 1);
3861 86776 : rtx r = XEXP (src_op0, 1);
3862 86776 : rtx s = src_op1;
3863 :
3864 : /* Split both "((X op Y) op X) op Y" and
3865 : "((X op Y) op Y) op X" as "T op T" where T is
3866 : "X op Y". */
3867 87023 : if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3868 86944 : || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3869 : {
3870 79 : newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3871 79 : SUBST (XEXP (setsrc, 0), newdest);
3872 79 : SUBST (XEXP (setsrc, 1), newdest);
3873 79 : subst_done = true;
3874 : }
3875 : /* Split "((X op X) op Y) op Y)" as "T op T" where
3876 : T is "X op Y". */
3877 86697 : else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3878 : {
3879 41 : rtx tmp = simplify_gen_binary (code, mode, p, r);
3880 41 : newi2pat = gen_rtx_SET (newdest, tmp);
3881 41 : SUBST (XEXP (setsrc, 0), newdest);
3882 41 : SUBST (XEXP (setsrc, 1), newdest);
3883 41 : subst_done = true;
3884 : }
3885 : }
3886 : }
3887 :
3888 1688 : if (!subst_done)
3889 : {
3890 3679685 : newi2pat = gen_rtx_SET (newdest, *split);
3891 3679685 : SUBST (*split, newdest);
3892 : }
3893 :
3894 3681373 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3895 :
3896 : /* recog_for_combine might have added CLOBBERs to newi2pat.
3897 : Make sure NEWPAT does not depend on the clobbered regs. */
3898 3681373 : if (GET_CODE (newi2pat) == PARALLEL)
3899 2493365 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3900 1675025 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3901 : {
3902 856685 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3903 856685 : if (reg_overlap_mentioned_p (reg, newpat))
3904 : {
3905 24082 : undo_all ();
3906 24082 : return 0;
3907 : }
3908 : }
3909 :
3910 : /* If the split point was a MULT and we didn't have one before,
3911 : don't use one now. */
3912 3657291 : if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3913 2175146 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3914 : }
3915 : }
3916 :
3917 : /* Check for a case where we loaded from memory in a narrow mode and
3918 : then sign extended it, but we need both registers. In that case,
3919 : we have a PARALLEL with both loads from the same memory location.
3920 : We can split this into a load from memory followed by a register-register
3921 : copy. This saves at least one insn, more if register allocation can
3922 : eliminate the copy.
3923 :
3924 : We cannot do this if the involved modes have more than one elements,
3925 : like for vector or complex modes.
3926 :
3927 : We cannot do this if the destination of the first assignment is a
3928 : condition code register. We eliminate this case by making sure
3929 : the SET_DEST and SET_SRC have the same mode.
3930 :
3931 : We cannot do this if the destination of the second assignment is
3932 : a register that we have already assumed is zero-extended. Similarly
3933 : for a SUBREG of such a register. */
3934 :
3935 5814707 : else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3936 5755911 : && GET_CODE (newpat) == PARALLEL
3937 5754063 : && XVECLEN (newpat, 0) == 2
3938 4777426 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3939 4777169 : && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3940 23289 : && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3941 23289 : == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3942 23289 : && ! VECTOR_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3943 : && ! COMPLEX_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3944 21857 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3945 21857 : && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3946 21857 : XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3947 6453 : && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3948 6453 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3949 6453 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3950 6453 : && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3951 : (REG_P (temp_expr)
3952 6453 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3953 6528 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3954 : BITS_PER_WORD)
3955 6352 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3956 : HOST_BITS_PER_INT)
3957 1136 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3958 1136 : != GET_MODE_MASK (word_mode))))
3959 6435 : && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3960 0 : && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3961 0 : (REG_P (temp_expr)
3962 0 : && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3963 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3964 : BITS_PER_WORD)
3965 0 : && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3966 : HOST_BITS_PER_INT)
3967 0 : && (reg_stat[REGNO (temp_expr)].nonzero_bits
3968 0 : != GET_MODE_MASK (word_mode)))))
3969 6435 : && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3970 6435 : SET_SRC (XVECEXP (newpat, 0, 1)))
3971 28844279 : && ! find_reg_note (i3, REG_UNUSED,
3972 6390 : SET_DEST (XVECEXP (newpat, 0, 0))))
3973 : {
3974 6390 : rtx ni2dest;
3975 :
3976 6390 : newi2pat = XVECEXP (newpat, 0, 0);
3977 6390 : ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3978 6390 : newpat = XVECEXP (newpat, 0, 1);
3979 6390 : SUBST (SET_SRC (newpat),
3980 : gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3981 6390 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3982 :
3983 6390 : if (i2_code_number >= 0)
3984 0 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3985 :
3986 6390 : if (insn_code_number >= 0)
3987 : swap_i2i3 = 1;
3988 : }
3989 :
3990 : /* Similarly, check for a case where we have a PARALLEL of two independent
3991 : SETs but we started with three insns. In this case, we can do the sets
3992 : as two separate insns. This case occurs when some SET allows two
3993 : other insns to combine, but the destination of that SET is still live.
3994 :
3995 : Also do this if we started with two insns and (at least) one of the
3996 : resulting sets is a noop; this noop will be deleted later.
3997 :
3998 : Also do this if we started with two insns neither of which was a simple
3999 : move. */
4000 :
4001 24729948 : else if (insn_code_number < 0 && asm_noperands (newpat) < 0
4002 24711423 : && GET_CODE (newpat) == PARALLEL
4003 11288706 : && XVECLEN (newpat, 0) == 2
4004 10209045 : && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
4005 10100720 : && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
4006 10036867 : && (i1
4007 5288757 : || set_noop_p (XVECEXP (newpat, 0, 0))
4008 5288285 : || set_noop_p (XVECEXP (newpat, 0, 1))
4009 5288280 : || (!i2_was_move && !i3_was_move))
4010 6647471 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
4011 6646845 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
4012 6646710 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
4013 6646144 : && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
4014 6646130 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
4015 : XVECEXP (newpat, 0, 0))
4016 5554803 : && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4017 5554803 : XVECEXP (newpat, 0, 1))
4018 34700397 : && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4019 443411 : && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4020 : {
4021 5173058 : rtx set0 = XVECEXP (newpat, 0, 0);
4022 5173058 : rtx set1 = XVECEXP (newpat, 0, 1);
4023 :
4024 : /* Normally, it doesn't matter which of the two is done first, but
4025 : one which uses any regs/memory set or used in between i2 and i3
4026 : can't be first. The PARALLEL might also have been pre-existing
4027 : in i3, so we need to make sure that we won't wrongly hoist a SET
4028 : to i2 that would conflict with a death note present in there, or
4029 : would have its dest modified or used between i2 and i3. */
4030 5173058 : if ((set_noop_p (set1)
4031 5173058 : || (!modified_between_p (SET_SRC (set1), i2, i3)
4032 10308350 : && !(REG_P (SET_DEST (set1))
4033 5142133 : && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4034 5190003 : && !(GET_CODE (SET_DEST (set1)) == SUBREG
4035 24084 : && find_reg_note (i2, REG_DEAD,
4036 24084 : SUBREG_REG (SET_DEST (set1))))
4037 5165919 : && !modified_between_p (SET_DEST (set1), i2, i3)
4038 5165919 : && !reg_used_between_p (SET_DEST (set1), i2, i3)))
4039 : /* If I3 is a jump, ensure that set0 is a jump so that
4040 : we do not create invalid RTL. */
4041 10338971 : && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx))
4042 : {
4043 5165913 : newi2pat = set1;
4044 5165913 : newpat = set0;
4045 : }
4046 7145 : else if ((set_noop_p (set0)
4047 7139 : || (!modified_between_p (SET_SRC (set0), i2, i3)
4048 596 : && !(REG_P (SET_DEST (set0))
4049 298 : && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4050 298 : && !(GET_CODE (SET_DEST (set0)) == SUBREG
4051 0 : && find_reg_note (i2, REG_DEAD,
4052 0 : SUBREG_REG (SET_DEST (set0))))
4053 298 : && !modified_between_p (SET_DEST (set0), i2, i3)
4054 297 : && !reg_used_between_p (SET_DEST (set0), i2, i3)))
4055 : /* If I3 is a jump, ensure that set1 is a jump so that
4056 : we do not create invalid RTL. */
4057 7442 : && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx))
4058 : {
4059 303 : newi2pat = set0;
4060 303 : newpat = set1;
4061 : }
4062 : else
4063 : {
4064 6842 : undo_all ();
4065 6842 : return 0;
4066 : }
4067 :
4068 5166216 : i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4069 :
4070 5166216 : if (i2_code_number >= 0)
4071 : {
4072 : /* recog_for_combine might have added CLOBBERs to newi2pat.
4073 : Make sure NEWPAT does not depend on the clobbered regs. */
4074 3801321 : if (GET_CODE (newi2pat) == PARALLEL)
4075 : {
4076 1371949 : for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4077 918872 : if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4078 : {
4079 465795 : rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4080 465795 : if (reg_overlap_mentioned_p (reg, newpat))
4081 : {
4082 5193 : undo_all ();
4083 5193 : return 0;
4084 : }
4085 : }
4086 : }
4087 :
4088 3796128 : insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4089 :
4090 : /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4091 : Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4092 : mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4093 3796128 : if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4094 : {
4095 92399 : for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4096 61610 : if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4097 : {
4098 30821 : rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4099 30821 : if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4100 30821 : || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4101 : {
4102 0 : undo_all ();
4103 0 : return 0;
4104 : }
4105 : }
4106 : }
4107 :
4108 : if (insn_code_number >= 0)
4109 : split_i2i3 = true;
4110 : }
4111 : }
4112 :
4113 : /* If it still isn't recognized, fail and change things back the way they
4114 : were. */
4115 29809850 : if ((insn_code_number < 0
4116 : /* Is the result a reasonable ASM_OPERANDS? */
4117 33441274 : && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4118 : {
4119 29283233 : undo_all ();
4120 29283233 : return 0;
4121 : }
4122 :
4123 : /* If we had to change another insn, make sure it is valid also. */
4124 4329135 : if (undobuf.other_insn)
4125 : {
4126 230970 : CLEAR_HARD_REG_SET (newpat_used_regs);
4127 :
4128 230970 : other_pat = PATTERN (undobuf.other_insn);
4129 230970 : other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4130 : &new_other_notes);
4131 :
4132 230970 : if (other_code_number < 0 && ! check_asm_operands (other_pat))
4133 : {
4134 7086 : undo_all ();
4135 7086 : return 0;
4136 : }
4137 : }
4138 :
4139 : /* Reject this combination if insn_cost reports that the replacement
4140 : instructions are more expensive than the originals. */
4141 4322049 : if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat,
4142 : insn_code_number, i2_code_number,
4143 : other_code_number))
4144 : {
4145 217640 : undo_all ();
4146 217640 : return 0;
4147 : }
4148 :
4149 4104409 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4150 : {
4151 2214466 : struct undo *undo;
4152 :
4153 6631410 : for (undo = undobuf.undos; undo; undo = undo->next)
4154 4416944 : if (undo->kind == UNDO_MODE)
4155 : {
4156 2878 : rtx reg = regno_reg_rtx[undo->where.regno];
4157 2878 : machine_mode new_mode = GET_MODE (reg);
4158 2878 : machine_mode old_mode = undo->old_contents.m;
4159 :
4160 : /* Temporarily revert mode back. */
4161 2878 : adjust_reg_mode (reg, old_mode);
4162 :
4163 2878 : if (reg == i2dest && i2scratch)
4164 : {
4165 : /* If we used i2dest as a scratch register with a
4166 : different mode, substitute it for the original
4167 : i2src while its original mode is temporarily
4168 : restored, and then clear i2scratch so that we don't
4169 : do it again later. */
4170 2878 : propagate_for_debug (i2, last_combined_insn, reg, i2src,
4171 : this_basic_block);
4172 2878 : i2scratch = false;
4173 : /* Put back the new mode. */
4174 2878 : adjust_reg_mode (reg, new_mode);
4175 : }
4176 : else
4177 : {
4178 0 : rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4179 0 : rtx_insn *first, *last;
4180 :
4181 0 : if (reg == i2dest)
4182 : {
4183 : first = i2;
4184 : last = last_combined_insn;
4185 : }
4186 : else
4187 : {
4188 0 : first = i3;
4189 0 : last = undobuf.other_insn;
4190 0 : gcc_assert (last);
4191 0 : if (DF_INSN_LUID (last)
4192 0 : < DF_INSN_LUID (last_combined_insn))
4193 0 : last = last_combined_insn;
4194 : }
4195 :
4196 : /* We're dealing with a reg that changed mode but not
4197 : meaning, so we want to turn it into a subreg for
4198 : the new mode. However, because of REG sharing and
4199 : because its mode had already changed, we have to do
4200 : it in two steps. First, replace any debug uses of
4201 : reg, with its original mode temporarily restored,
4202 : with this copy we have created; then, replace the
4203 : copy with the SUBREG of the original shared reg,
4204 : once again changed to the new mode. */
4205 0 : propagate_for_debug (first, last, reg, tempreg,
4206 : this_basic_block);
4207 0 : adjust_reg_mode (reg, new_mode);
4208 0 : propagate_for_debug (first, last, tempreg,
4209 : lowpart_subreg (old_mode, reg, new_mode),
4210 : this_basic_block);
4211 : }
4212 : }
4213 : }
4214 :
4215 : /* If we will be able to accept this, we have made a
4216 : change to the destination of I3. This requires us to
4217 : do a few adjustments. */
4218 :
4219 4104409 : if (changed_i3_dest)
4220 : {
4221 17319 : PATTERN (i3) = newpat;
4222 17319 : adjust_for_new_dest (i3);
4223 : }
4224 :
4225 4104409 : bool only_i3_changed = !i0 && !i1 && rtx_equal_p (newi2pat, PATTERN (i2));
4226 :
4227 : /* If only i3 has changed, any split of the combined instruction just
4228 : restored i2 to its original state. No destinations moved from i3
4229 : to i2. */
4230 : if (only_i3_changed)
4231 : split_i2i3 = false;
4232 :
4233 : /* We now know that we can do this combination. Merge the insns and
4234 : update the status of registers and LOG_LINKS. */
4235 :
4236 4104409 : if (undobuf.other_insn)
4237 : {
4238 223719 : rtx note, next;
4239 :
4240 223719 : PATTERN (undobuf.other_insn) = other_pat;
4241 :
4242 : /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4243 : ensure that they are still valid. Then add any non-duplicate
4244 : notes added by recog_for_combine. */
4245 668413 : for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4246 : {
4247 444694 : next = XEXP (note, 1);
4248 :
4249 444694 : if ((REG_NOTE_KIND (note) == REG_DEAD
4250 226967 : && !reg_referenced_p (XEXP (note, 0),
4251 226967 : PATTERN (undobuf.other_insn)))
4252 440497 : ||(REG_NOTE_KIND (note) == REG_UNUSED
4253 5 : && !reg_set_p (XEXP (note, 0),
4254 5 : PATTERN (undobuf.other_insn)))
4255 : /* Simply drop equal note since it may be no longer valid
4256 : for other_insn. It may be possible to record that CC
4257 : register is changed and only discard those notes, but
4258 : in practice it's unnecessary complication and doesn't
4259 : give any meaningful improvement.
4260 :
4261 : See PR78559. */
4262 440497 : || REG_NOTE_KIND (note) == REG_EQUAL
4263 885055 : || REG_NOTE_KIND (note) == REG_EQUIV)
4264 4333 : remove_note (undobuf.other_insn, note);
4265 : }
4266 :
4267 223719 : distribute_notes (new_other_notes, undobuf.other_insn,
4268 : undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4269 : NULL_RTX);
4270 : }
4271 :
4272 4104409 : if (swap_i2i3)
4273 : {
4274 : /* I3 now uses what used to be its destination and which is now
4275 : I2's destination. This requires us to do a few adjustments. */
4276 0 : PATTERN (i3) = newpat;
4277 0 : adjust_for_new_dest (i3);
4278 : }
4279 :
4280 4104409 : if (swap_i2i3 || split_i2i3)
4281 : {
4282 : /* We might need a LOG_LINK from I3 to I2. But then we used to
4283 : have one, so we still will.
4284 :
4285 : However, some later insn might be using I2's dest and have
4286 : a LOG_LINK pointing at I3. We should change it to point at
4287 : I2 instead. */
4288 :
4289 : /* newi2pat is usually a SET here; however, recog_for_combine might
4290 : have added some clobbers. */
4291 27625 : rtx x = newi2pat;
4292 27625 : if (GET_CODE (x) == PARALLEL)
4293 544 : x = XVECEXP (newi2pat, 0, 0);
4294 :
4295 27625 : if (REG_P (SET_DEST (x))
4296 8 : || (GET_CODE (SET_DEST (x)) == SUBREG
4297 2 : && REG_P (SUBREG_REG (SET_DEST (x)))))
4298 : {
4299 27619 : unsigned int regno = reg_or_subregno (SET_DEST (x));
4300 :
4301 27619 : bool done = false;
4302 375609 : for (rtx_insn *insn = NEXT_INSN (i3);
4303 375609 : !done
4304 375609 : && insn
4305 374287 : && INSN_P (insn)
4306 723599 : && BLOCK_FOR_INSN (insn) == this_basic_block;
4307 347990 : insn = NEXT_INSN (insn))
4308 : {
4309 347990 : if (DEBUG_INSN_P (insn))
4310 69606 : continue;
4311 278384 : struct insn_link *link;
4312 523049 : FOR_EACH_LOG_LINK (link, insn)
4313 244675 : if (link->insn == i3 && link->regno == regno)
4314 : {
4315 10 : link->insn = i2;
4316 10 : done = true;
4317 10 : break;
4318 : }
4319 : }
4320 : }
4321 : }
4322 :
4323 4104409 : {
4324 4104409 : rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4325 4104409 : struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4326 4104409 : rtx midnotes = 0;
4327 4104409 : int from_luid;
4328 : /* Compute which registers we expect to eliminate. newi2pat may be setting
4329 : either i3dest or i2dest, so we must check it. */
4330 109637 : rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4331 4006042 : || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4332 3919841 : || !i2dest_killed
4333 8023161 : ? 0 : i2dest);
4334 : /* For i1, we need to compute both local elimination and global
4335 : elimination information with respect to newi2pat because i1dest
4336 : may be the same as i3dest, in which case newi2pat may be setting
4337 : i1dest. Global information is used when distributing REG_DEAD
4338 : note for i2 and i3, in which case it does matter if newi2pat sets
4339 : i1dest or not.
4340 :
4341 : Local information is used when distributing REG_DEAD note for i1,
4342 : in which case it doesn't matter if newi2pat sets i1dest or not.
4343 : See PR62151, if we have four insns combination:
4344 : i0: r0 <- i0src
4345 : i1: r1 <- i1src (using r0)
4346 : REG_DEAD (r0)
4347 : i2: r0 <- i2src (using r1)
4348 : i3: r3 <- i3src (using r0)
4349 : ix: using r0
4350 : From i1's point of view, r0 is eliminated, no matter if it is set
4351 : by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4352 : should be discarded.
4353 :
4354 : Note local information only affects cases in forms like "I1->I2->I3",
4355 : "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4356 : "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4357 : i0dest anyway. */
4358 102324 : rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4359 102257 : || !i1dest_killed
4360 4104409 : ? 0 : i1dest);
4361 102256 : rtx elim_i1 = (local_elim_i1 == 0
4362 102256 : || (newi2pat && reg_set_p (i1dest, newi2pat))
4363 102256 : ? 0 : i1dest);
4364 : /* Same case as i1. */
4365 4627 : rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4366 4104409 : ? 0 : i0dest);
4367 4615 : rtx elim_i0 = (local_elim_i0 == 0
4368 4615 : || (newi2pat && reg_set_p (i0dest, newi2pat))
4369 4615 : ? 0 : i0dest);
4370 :
4371 : /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4372 : clear them. */
4373 4104409 : i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4374 4104409 : i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4375 4104409 : if (i1)
4376 102324 : i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4377 4104409 : if (i0)
4378 4627 : i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4379 :
4380 : /* Ensure that we do not have something that should not be shared but
4381 : occurs multiple times in the new insns. Check this by first
4382 : resetting all the `used' flags and then copying anything is shared. */
4383 :
4384 4104409 : reset_used_flags (i3notes);
4385 4104409 : reset_used_flags (i2notes);
4386 4104409 : reset_used_flags (i1notes);
4387 4104409 : reset_used_flags (i0notes);
4388 4104409 : reset_used_flags (newpat);
4389 4104409 : reset_used_flags (newi2pat);
4390 4104409 : if (undobuf.other_insn)
4391 223719 : reset_used_flags (PATTERN (undobuf.other_insn));
4392 :
4393 4104409 : i3notes = copy_rtx_if_shared (i3notes);
4394 4104409 : i2notes = copy_rtx_if_shared (i2notes);
4395 4104409 : i1notes = copy_rtx_if_shared (i1notes);
4396 4104409 : i0notes = copy_rtx_if_shared (i0notes);
4397 4104409 : newpat = copy_rtx_if_shared (newpat);
4398 4104409 : newi2pat = copy_rtx_if_shared (newi2pat);
4399 4104409 : if (undobuf.other_insn)
4400 223719 : reset_used_flags (PATTERN (undobuf.other_insn));
4401 :
4402 4104409 : INSN_CODE (i3) = insn_code_number;
4403 4104409 : PATTERN (i3) = newpat;
4404 :
4405 4104409 : if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4406 : {
4407 243436 : for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4408 164618 : link = XEXP (link, 1))
4409 : {
4410 164618 : if (substed_i2)
4411 : {
4412 : /* I2SRC must still be meaningful at this point. Some
4413 : splitting operations can invalidate I2SRC, but those
4414 : operations do not apply to calls. */
4415 164618 : gcc_assert (i2src);
4416 164618 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4417 : i2dest, i2src);
4418 : }
4419 164618 : if (substed_i1)
4420 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4421 : i1dest, i1src);
4422 164618 : if (substed_i0)
4423 0 : XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4424 : i0dest, i0src);
4425 : }
4426 : }
4427 :
4428 4104409 : if (undobuf.other_insn)
4429 223719 : INSN_CODE (undobuf.other_insn) = other_code_number;
4430 :
4431 : /* We had one special case above where I2 had more than one set and
4432 : we replaced a destination of one of those sets with the destination
4433 : of I3. In that case, we have to update LOG_LINKS of insns later
4434 : in this basic block. Note that this (expensive) case is rare.
4435 :
4436 : Also, in this case, we must pretend that all REG_NOTEs for I2
4437 : actually came from I3, so that REG_UNUSED notes from I2 will be
4438 : properly handled. */
4439 :
4440 4104409 : if (i3_subst_into_i2)
4441 : {
4442 205862 : for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4443 141432 : if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4444 65695 : || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4445 140597 : && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4446 125787 : && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4447 267219 : && ! find_reg_note (i2, REG_UNUSED,
4448 125787 : SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4449 31913173 : for (temp_insn = NEXT_INSN (i2);
4450 : temp_insn
4451 31913173 : && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4452 31665645 : || BB_HEAD (this_basic_block) != temp_insn);
4453 31856468 : temp_insn = NEXT_INSN (temp_insn))
4454 31856468 : if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4455 20327463 : FOR_EACH_LOG_LINK (link, temp_insn)
4456 7494546 : if (link->insn == i2)
4457 440 : link->insn = i3;
4458 :
4459 64430 : if (i3notes)
4460 : {
4461 : rtx link = i3notes;
4462 71971 : while (XEXP (link, 1))
4463 : link = XEXP (link, 1);
4464 64430 : XEXP (link, 1) = i2notes;
4465 : }
4466 : else
4467 : i3notes = i2notes;
4468 : i2notes = 0;
4469 : }
4470 :
4471 4104409 : LOG_LINKS (i3) = NULL;
4472 4104409 : REG_NOTES (i3) = 0;
4473 4104409 : LOG_LINKS (i2) = NULL;
4474 4104409 : REG_NOTES (i2) = 0;
4475 :
4476 4104409 : if (newi2pat)
4477 : {
4478 109637 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4479 10363 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4480 : this_basic_block);
4481 109637 : INSN_CODE (i2) = i2_code_number;
4482 109637 : PATTERN (i2) = newi2pat;
4483 : }
4484 : else
4485 : {
4486 3994772 : if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4487 2147109 : propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4488 : this_basic_block);
4489 3994772 : SET_INSN_DELETED (i2);
4490 : }
4491 :
4492 4104409 : if (i1)
4493 : {
4494 102324 : LOG_LINKS (i1) = NULL;
4495 102324 : REG_NOTES (i1) = 0;
4496 102324 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4497 53506 : propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4498 : this_basic_block);
4499 102324 : SET_INSN_DELETED (i1);
4500 : }
4501 :
4502 4104409 : if (i0)
4503 : {
4504 4627 : LOG_LINKS (i0) = NULL;
4505 4627 : REG_NOTES (i0) = 0;
4506 4627 : if (MAY_HAVE_DEBUG_BIND_INSNS)
4507 2911 : propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4508 : this_basic_block);
4509 4627 : SET_INSN_DELETED (i0);
4510 : }
4511 :
4512 : /* Get death notes for everything that is now used in either I3 or
4513 : I2 and used to die in a previous insn. If we built two new
4514 : patterns, move from I1 to I2 then I2 to I3 so that we get the
4515 : proper movement on registers that I2 modifies. */
4516 :
4517 4627 : if (i0)
4518 4627 : from_luid = DF_INSN_LUID (i0);
4519 4099782 : else if (i1)
4520 97697 : from_luid = DF_INSN_LUID (i1);
4521 : else
4522 4002085 : from_luid = DF_INSN_LUID (i2);
4523 4104409 : if (newi2pat)
4524 109637 : move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4525 4104409 : move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4526 :
4527 : /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4528 4104409 : if (i3notes)
4529 7418596 : distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4530 : elim_i2, elim_i1, elim_i0);
4531 4104409 : if (i2notes)
4532 5720012 : distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4533 : elim_i2, elim_i1, elim_i0);
4534 4104409 : if (i1notes)
4535 59913 : distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4536 : elim_i2, local_elim_i1, local_elim_i0);
4537 4104409 : if (i0notes)
4538 3907 : distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4539 : elim_i2, elim_i1, local_elim_i0);
4540 4104409 : if (midnotes)
4541 4893190 : distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4542 : elim_i2, elim_i1, elim_i0);
4543 :
4544 : /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4545 : know these are REG_UNUSED and want them to go to the desired insn,
4546 : so we always pass it as i3. */
4547 :
4548 4104409 : if (newi2pat && new_i2_notes)
4549 47259 : distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4550 : NULL_RTX);
4551 :
4552 4104409 : if (new_i3_notes)
4553 163411 : distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4554 : NULL_RTX);
4555 :
4556 : /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4557 : put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4558 : I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4559 : in that case, it might delete I2. Similarly for I2 and I1.
4560 : Show an additional death due to the REG_DEAD note we make here. If
4561 : we discard it in distribute_notes, we will decrement it again. */
4562 :
4563 4104409 : if (i3dest_killed)
4564 : {
4565 340646 : rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4566 340646 : if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4567 678 : distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4568 : elim_i1, elim_i0);
4569 : else
4570 678015 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4571 : elim_i2, elim_i1, elim_i0);
4572 : }
4573 :
4574 4104409 : if (i2dest_in_i2src)
4575 : {
4576 85173 : rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4577 85173 : if (newi2pat && reg_set_p (i2dest, newi2pat))
4578 849 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4579 : NULL_RTX, NULL_RTX);
4580 : else
4581 168610 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4582 : NULL_RTX, NULL_RTX, NULL_RTX);
4583 : }
4584 :
4585 4104409 : if (i1dest_in_i1src)
4586 : {
4587 65 : rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4588 65 : if (newi2pat && reg_set_p (i1dest, newi2pat))
4589 5 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4590 : NULL_RTX, NULL_RTX);
4591 : else
4592 102 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4593 : NULL_RTX, NULL_RTX, NULL_RTX);
4594 : }
4595 :
4596 4104409 : if (i0dest_in_i0src)
4597 : {
4598 12 : rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4599 12 : if (newi2pat && reg_set_p (i0dest, newi2pat))
4600 0 : distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4601 : NULL_RTX, NULL_RTX);
4602 : else
4603 24 : distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4604 : NULL_RTX, NULL_RTX, NULL_RTX);
4605 : }
4606 :
4607 4104409 : if (only_i3_changed)
4608 40028 : distribute_links (i3links, i3, param_max_combine_search_insns);
4609 : else
4610 : {
4611 4064381 : distribute_links (i3links);
4612 4064381 : distribute_links (i2links, i2);
4613 4064381 : distribute_links (i1links);
4614 4064381 : distribute_links (i0links);
4615 : }
4616 :
4617 4104409 : if (REG_P (i2dest))
4618 : {
4619 4104409 : struct insn_link *link;
4620 4104409 : rtx_insn *i2_insn = 0;
4621 4104409 : rtx i2_val = 0, set;
4622 :
4623 : /* The insn that used to set this register doesn't exist, and
4624 : this life of the register may not exist either. See if one of
4625 : I3's links points to an insn that sets I2DEST. If it does,
4626 : that is now the last known value for I2DEST. If we don't update
4627 : this and I2 set the register to a value that depended on its old
4628 : contents, we will get confused. If this insn is used, thing
4629 : will be set correctly in combine_instructions. */
4630 7551021 : FOR_EACH_LOG_LINK (link, i3)
4631 3446612 : if ((set = single_set (link->insn)) != 0
4632 3446612 : && rtx_equal_p (i2dest, SET_DEST (set)))
4633 47659 : i2_insn = link->insn, i2_val = SET_SRC (set);
4634 :
4635 4104409 : record_value_for_reg (i2dest, i2_insn, i2_val);
4636 :
4637 : /* If the reg formerly set in I2 died only once and that was in I3,
4638 : zero its use count so it won't make `reload' do any work. */
4639 4104409 : if (! added_sets_2
4640 3969406 : && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4641 3931061 : && ! i2dest_in_i2src
4642 7971092 : && REGNO (i2dest) < reg_n_sets_max)
4643 3866681 : INC_REG_N_SETS (REGNO (i2dest), -1);
4644 : }
4645 :
4646 4104409 : if (i1 && REG_P (i1dest))
4647 : {
4648 102324 : struct insn_link *link;
4649 102324 : rtx_insn *i1_insn = 0;
4650 102324 : rtx i1_val = 0, set;
4651 :
4652 178266 : FOR_EACH_LOG_LINK (link, i3)
4653 75942 : if ((set = single_set (link->insn)) != 0
4654 75942 : && rtx_equal_p (i1dest, SET_DEST (set)))
4655 494 : i1_insn = link->insn, i1_val = SET_SRC (set);
4656 :
4657 102324 : record_value_for_reg (i1dest, i1_insn, i1_val);
4658 :
4659 102324 : if (! added_sets_1
4660 : && ! i1dest_in_i1src
4661 102324 : && REGNO (i1dest) < reg_n_sets_max)
4662 96275 : INC_REG_N_SETS (REGNO (i1dest), -1);
4663 : }
4664 :
4665 4104409 : if (i0 && REG_P (i0dest))
4666 : {
4667 4627 : struct insn_link *link;
4668 4627 : rtx_insn *i0_insn = 0;
4669 4627 : rtx i0_val = 0, set;
4670 :
4671 7089 : FOR_EACH_LOG_LINK (link, i3)
4672 2462 : if ((set = single_set (link->insn)) != 0
4673 2462 : && rtx_equal_p (i0dest, SET_DEST (set)))
4674 0 : i0_insn = link->insn, i0_val = SET_SRC (set);
4675 :
4676 4627 : record_value_for_reg (i0dest, i0_insn, i0_val);
4677 :
4678 4627 : if (! added_sets_0
4679 : && ! i0dest_in_i0src
4680 4627 : && REGNO (i0dest) < reg_n_sets_max)
4681 4566 : INC_REG_N_SETS (REGNO (i0dest), -1);
4682 : }
4683 :
4684 : /* Update reg_stat[].nonzero_bits et al for any changes that may have
4685 : been made to this insn. The order is important, because newi2pat
4686 : can affect nonzero_bits of newpat. */
4687 4104409 : if (newi2pat)
4688 109637 : note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4689 4104409 : note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4690 : }
4691 :
4692 4104409 : if (undobuf.other_insn != NULL_RTX)
4693 : {
4694 223719 : if (dump_file)
4695 : {
4696 12 : fprintf (dump_file, "modifying other_insn ");
4697 12 : dump_insn_slim (dump_file, undobuf.other_insn);
4698 : }
4699 223719 : df_insn_rescan (undobuf.other_insn);
4700 : }
4701 :
4702 4104409 : if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4703 : {
4704 0 : if (dump_file)
4705 : {
4706 0 : fprintf (dump_file, "modifying insn i0 ");
4707 0 : dump_insn_slim (dump_file, i0);
4708 : }
4709 0 : df_insn_rescan (i0);
4710 : }
4711 :
4712 4104409 : if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4713 : {
4714 0 : if (dump_file)
4715 : {
4716 0 : fprintf (dump_file, "modifying insn i1 ");
4717 0 : dump_insn_slim (dump_file, i1);
4718 : }
4719 0 : df_insn_rescan (i1);
4720 : }
4721 :
4722 4104409 : if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4723 : {
4724 109637 : if (dump_file)
4725 : {
4726 19 : fprintf (dump_file, "modifying insn i2 ");
4727 19 : dump_insn_slim (dump_file, i2);
4728 : }
4729 109637 : df_insn_rescan (i2);
4730 : }
4731 :
4732 4104409 : if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4733 : {
4734 4104409 : if (dump_file)
4735 : {
4736 244 : fprintf (dump_file, "modifying insn i3 ");
4737 244 : dump_insn_slim (dump_file, i3);
4738 : }
4739 4104409 : df_insn_rescan (i3);
4740 : }
4741 :
4742 : /* Set new_direct_jump_p if a new return or simple jump instruction
4743 : has been created. Adjust the CFG accordingly. */
4744 4104409 : if (returnjump_p (i3) || any_uncondjump_p (i3))
4745 : {
4746 201 : *new_direct_jump_p = 1;
4747 201 : mark_jump_label (PATTERN (i3), i3, 0);
4748 201 : update_cfg_for_uncondjump (i3);
4749 : }
4750 :
4751 4104409 : if (undobuf.other_insn != NULL_RTX
4752 4104409 : && (returnjump_p (undobuf.other_insn)
4753 223719 : || any_uncondjump_p (undobuf.other_insn)))
4754 : {
4755 1964 : *new_direct_jump_p = 1;
4756 1964 : update_cfg_for_uncondjump (undobuf.other_insn);
4757 : }
4758 :
4759 4104409 : if (GET_CODE (PATTERN (i3)) == TRAP_IF
4760 4104409 : && XEXP (PATTERN (i3), 0) == const1_rtx)
4761 : {
4762 0 : basic_block bb = BLOCK_FOR_INSN (i3);
4763 0 : gcc_assert (bb);
4764 0 : remove_edge (split_block (bb, i3));
4765 0 : emit_barrier_after_bb (bb);
4766 0 : *new_direct_jump_p = 1;
4767 : }
4768 :
4769 4104409 : if (undobuf.other_insn
4770 223719 : && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4771 4104409 : && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4772 : {
4773 0 : basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4774 0 : gcc_assert (bb);
4775 0 : remove_edge (split_block (bb, undobuf.other_insn));
4776 0 : emit_barrier_after_bb (bb);
4777 0 : *new_direct_jump_p = 1;
4778 : }
4779 :
4780 : /* A noop might also need cleaning up of CFG, if it comes from the
4781 : simplification of a jump. */
4782 4104409 : if (JUMP_P (i3)
4783 46474 : && GET_CODE (newpat) == SET
4784 34836 : && SET_SRC (newpat) == pc_rtx
4785 383 : && SET_DEST (newpat) == pc_rtx)
4786 : {
4787 383 : *new_direct_jump_p = 1;
4788 383 : update_cfg_for_uncondjump (i3);
4789 : }
4790 :
4791 4104409 : if (undobuf.other_insn != NULL_RTX
4792 223719 : && JUMP_P (undobuf.other_insn)
4793 217661 : && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4794 217661 : && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4795 4106144 : && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4796 : {
4797 1735 : *new_direct_jump_p = 1;
4798 1735 : update_cfg_for_uncondjump (undobuf.other_insn);
4799 : }
4800 :
4801 4104409 : combine_successes++;
4802 4104409 : undo_commit ();
4803 :
4804 4104409 : if (only_i3_changed)
4805 : return i3;
4806 :
4807 4064381 : rtx_insn *ret = newi2pat ? i2 : i3;
4808 4064381 : if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4809 : ret = added_links_insn;
4810 4064381 : if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4811 : ret = added_notes_insn;
4812 :
4813 : return ret;
4814 : }
4815 :
4816 : /* Get a marker for undoing to the current state. */
4817 :
4818 : static void *
4819 38379814 : get_undo_marker (void)
4820 : {
4821 38379814 : return undobuf.undos;
4822 : }
4823 :
4824 : /* Undo the modifications up to the marker. */
4825 :
4826 : static void
4827 45191513 : undo_to_marker (void *marker)
4828 : {
4829 45191513 : struct undo *undo, *next;
4830 :
4831 142268526 : for (undo = undobuf.undos; undo != marker; undo = next)
4832 : {
4833 97077013 : gcc_assert (undo);
4834 :
4835 97077013 : next = undo->next;
4836 97077013 : switch (undo->kind)
4837 : {
4838 89761758 : case UNDO_RTX:
4839 89761758 : *undo->where.r = undo->old_contents.r;
4840 89761758 : break;
4841 6689962 : case UNDO_INT:
4842 6689962 : *undo->where.i = undo->old_contents.i;
4843 6689962 : break;
4844 553870 : case UNDO_MODE:
4845 553870 : adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4846 : undo->old_contents.m);
4847 553870 : break;
4848 71423 : case UNDO_LINKS:
4849 71423 : *undo->where.l = undo->old_contents.l;
4850 71423 : break;
4851 0 : default:
4852 0 : gcc_unreachable ();
4853 : }
4854 :
4855 97077013 : undo->next = undobuf.frees;
4856 97077013 : undobuf.frees = undo;
4857 : }
4858 :
4859 45191513 : undobuf.undos = (struct undo *) marker;
4860 45191513 : }
4861 :
4862 : /* Undo all the modifications recorded in undobuf. */
4863 :
4864 : static void
4865 44057920 : undo_all (void)
4866 : {
4867 44057920 : undo_to_marker (0);
4868 0 : }
4869 :
4870 : /* We've committed to accepting the changes we made. Move all
4871 : of the undos to the free list. */
4872 :
4873 : static void
4874 4104409 : undo_commit (void)
4875 : {
4876 4104409 : struct undo *undo, *next;
4877 :
4878 12087924 : for (undo = undobuf.undos; undo; undo = next)
4879 : {
4880 7983515 : next = undo->next;
4881 7983515 : undo->next = undobuf.frees;
4882 7983515 : undobuf.frees = undo;
4883 : }
4884 4104409 : undobuf.undos = 0;
4885 4104409 : }
4886 :
4887 : /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4888 : where we have an arithmetic expression and return that point. LOC will
4889 : be inside INSN.
4890 :
4891 : try_combine will call this function to see if an insn can be split into
4892 : two insns. */
4893 :
4894 : static rtx *
4895 31665238 : find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4896 : {
4897 32697415 : rtx x = *loc;
4898 32697415 : enum rtx_code code = GET_CODE (x);
4899 32697415 : rtx *split;
4900 32697415 : unsigned HOST_WIDE_INT len = 0;
4901 32697415 : HOST_WIDE_INT pos = 0;
4902 32697415 : bool unsignedp = false;
4903 32697415 : rtx inner = NULL_RTX;
4904 32697415 : scalar_int_mode mode, inner_mode;
4905 :
4906 : /* First special-case some codes. */
4907 32697415 : switch (code)
4908 : {
4909 1037516 : case SUBREG:
4910 : #ifdef INSN_SCHEDULING
4911 : /* If we are making a paradoxical SUBREG invalid, it becomes a split
4912 : point. */
4913 1037516 : if (MEM_P (SUBREG_REG (x)))
4914 : return loc;
4915 : #endif
4916 1025556 : return find_split_point (&SUBREG_REG (x), insn, false);
4917 :
4918 1534329 : case MEM:
4919 : /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4920 : using LO_SUM and HIGH. */
4921 1534329 : if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4922 : || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4923 : {
4924 : machine_mode address_mode = get_address_mode (x);
4925 :
4926 : SUBST (XEXP (x, 0),
4927 : gen_rtx_LO_SUM (address_mode,
4928 : gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4929 : XEXP (x, 0)));
4930 : return &XEXP (XEXP (x, 0), 0);
4931 : }
4932 :
4933 : /* If we have a PLUS whose second operand is a constant and the
4934 : address is not valid, perhaps we can split it up using
4935 : the machine-specific way to split large constants. We use
4936 : the first pseudo-reg (one of the virtual regs) as a placeholder;
4937 : it will not remain in the result. */
4938 1534329 : if (GET_CODE (XEXP (x, 0)) == PLUS
4939 1016376 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4940 3291249 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4941 740544 : MEM_ADDR_SPACE (x)))
4942 : {
4943 114903 : rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4944 114903 : unsigned int old_nregs, new_nregs;
4945 114903 : rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4946 : subst_insn, &old_nregs, &new_nregs);
4947 :
4948 : /* This should have produced two insns, each of which sets our
4949 : placeholder. If the source of the second is a valid address,
4950 : we can put both sources together and make a split point
4951 : in the middle. */
4952 :
4953 114903 : if (seq
4954 56 : && NEXT_INSN (seq) != NULL_RTX
4955 0 : && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4956 0 : && NONJUMP_INSN_P (seq)
4957 0 : && GET_CODE (PATTERN (seq)) == SET
4958 0 : && SET_DEST (PATTERN (seq)) == reg
4959 0 : && ! reg_mentioned_p (reg,
4960 0 : SET_SRC (PATTERN (seq)))
4961 0 : && NONJUMP_INSN_P (NEXT_INSN (seq))
4962 0 : && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4963 0 : && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4964 114903 : && memory_address_addr_space_p
4965 114903 : (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4966 0 : MEM_ADDR_SPACE (x)))
4967 : {
4968 0 : rtx src1 = SET_SRC (PATTERN (seq));
4969 0 : rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4970 :
4971 : /* Replace the placeholder in SRC2 with SRC1. If we can
4972 : find where in SRC2 it was placed, that can become our
4973 : split point and we can replace this address with SRC2.
4974 : Just try two obvious places. */
4975 :
4976 0 : src2 = replace_rtx (src2, reg, src1);
4977 0 : split = 0;
4978 0 : if (XEXP (src2, 0) == src1)
4979 0 : split = &XEXP (src2, 0);
4980 0 : else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4981 0 : && XEXP (XEXP (src2, 0), 0) == src1)
4982 0 : split = &XEXP (XEXP (src2, 0), 0);
4983 :
4984 0 : if (split)
4985 : {
4986 0 : SUBST (XEXP (x, 0), src2);
4987 88742 : return split;
4988 : }
4989 : }
4990 :
4991 : /* If that didn't work and we have a nested plus, like:
4992 : ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4993 : is valid address, try to split (REG1 * CONST1). */
4994 114903 : if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4995 75502 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4996 58898 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4997 58887 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4998 10 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4999 : 0), 0)))))
5000 : {
5001 58887 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
5002 58887 : XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
5003 117774 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5004 58887 : MEM_ADDR_SPACE (x)))
5005 : {
5006 47397 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5007 47397 : return &XEXP (XEXP (XEXP (x, 0), 0), 0);
5008 : }
5009 11490 : XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
5010 11490 : }
5011 56016 : else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5012 16615 : && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
5013 16604 : && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5014 294 : && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
5015 294 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
5016 : 0), 1)))))
5017 : {
5018 0 : rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
5019 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
5020 0 : if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5021 0 : MEM_ADDR_SPACE (x)))
5022 : {
5023 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5024 0 : return &XEXP (XEXP (XEXP (x, 0), 0), 1);
5025 : }
5026 0 : XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5027 : }
5028 :
5029 : /* If that didn't work, perhaps the first operand is complex and
5030 : needs to be computed separately, so make a split point there.
5031 : This will occur on machines that just support REG + CONST
5032 : and have a constant moved through some previous computation. */
5033 67506 : if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5034 41345 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5035 0 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5036 41345 : return &XEXP (XEXP (x, 0), 0);
5037 : }
5038 :
5039 : /* If we have a PLUS whose first operand is complex, try computing it
5040 : separately by making a split there. */
5041 1445587 : if (GET_CODE (XEXP (x, 0)) == PLUS
5042 2539403 : && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5043 927634 : MEM_ADDR_SPACE (x))
5044 166182 : && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5045 1555219 : && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5046 606 : && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5047 109628 : return &XEXP (XEXP (x, 0), 0);
5048 : break;
5049 :
5050 4800239 : case SET:
5051 : /* See if we can split SET_SRC as it stands. */
5052 4800239 : split = find_split_point (&SET_SRC (x), insn, true);
5053 4800239 : if (split && split != &SET_SRC (x))
5054 : return split;
5055 :
5056 : /* See if we can split SET_DEST as it stands. */
5057 512075 : split = find_split_point (&SET_DEST (x), insn, false);
5058 512075 : if (split && split != &SET_DEST (x))
5059 : return split;
5060 :
5061 : /* See if this is a bitfield assignment with everything constant. If
5062 : so, this is an IOR of an AND, so split it into that. */
5063 481925 : if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5064 3443 : && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5065 : &inner_mode)
5066 3443 : && HWI_COMPUTABLE_MODE_P (inner_mode)
5067 3443 : && CONST_INT_P (XEXP (SET_DEST (x), 1))
5068 3443 : && CONST_INT_P (XEXP (SET_DEST (x), 2))
5069 3281 : && CONST_INT_P (SET_SRC (x))
5070 229 : && ((INTVAL (XEXP (SET_DEST (x), 1))
5071 229 : + INTVAL (XEXP (SET_DEST (x), 2)))
5072 229 : <= GET_MODE_PRECISION (inner_mode))
5073 482154 : && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5074 : {
5075 216 : HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5076 216 : unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5077 216 : rtx dest = XEXP (SET_DEST (x), 0);
5078 216 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5079 216 : unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5080 216 : rtx or_mask;
5081 :
5082 216 : if (BITS_BIG_ENDIAN)
5083 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5084 :
5085 216 : or_mask = gen_int_mode (src << pos, inner_mode);
5086 216 : if (src == mask)
5087 0 : SUBST (SET_SRC (x),
5088 : simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5089 : else
5090 : {
5091 216 : rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5092 216 : SUBST (SET_SRC (x),
5093 : simplify_gen_binary (IOR, inner_mode,
5094 : simplify_gen_binary (AND, inner_mode,
5095 : dest, negmask),
5096 : or_mask));
5097 : }
5098 :
5099 216 : SUBST (SET_DEST (x), dest);
5100 :
5101 216 : split = find_split_point (&SET_SRC (x), insn, true);
5102 216 : if (split && split != &SET_SRC (x))
5103 : return split;
5104 : }
5105 :
5106 : /* Otherwise, see if this is an operation that we can split into two.
5107 : If so, try to split that. */
5108 481709 : code = GET_CODE (SET_SRC (x));
5109 :
5110 481709 : switch (code)
5111 : {
5112 17094 : case AND:
5113 : /* If we are AND'ing with a large constant that is only a single
5114 : bit and the result is only being used in a context where we
5115 : need to know if it is zero or nonzero, replace it with a bit
5116 : extraction. This will avoid the large constant, which might
5117 : have taken more than one insn to make. If the constant were
5118 : not a valid argument to the AND but took only one insn to make,
5119 : this is no worse, but if it took more than one insn, it will
5120 : be better. */
5121 :
5122 17094 : if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5123 11442 : && REG_P (XEXP (SET_SRC (x), 0))
5124 450 : && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5125 2 : && REG_P (SET_DEST (x))
5126 1 : && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5127 1 : && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5128 0 : && XEXP (*split, 0) == SET_DEST (x)
5129 17094 : && XEXP (*split, 1) == const0_rtx)
5130 : {
5131 0 : rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5132 0 : XEXP (SET_SRC (x), 0),
5133 : pos, NULL_RTX, 1,
5134 : true, false, false);
5135 0 : if (extraction != 0)
5136 : {
5137 0 : SUBST (SET_SRC (x), extraction);
5138 0 : return find_split_point (loc, insn, false);
5139 : }
5140 : }
5141 : break;
5142 :
5143 : case NE:
5144 : /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5145 : is known to be on, this can be converted into a NEG of a shift. */
5146 : if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5147 : && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5148 : && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5149 : GET_MODE (XEXP (SET_SRC (x),
5150 : 0))))) >= 1))
5151 : {
5152 : machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5153 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5154 : SUBST (SET_SRC (x),
5155 : gen_rtx_NEG (mode,
5156 : gen_rtx_LSHIFTRT (mode,
5157 : XEXP (SET_SRC (x), 0),
5158 : pos_rtx)));
5159 :
5160 : split = find_split_point (&SET_SRC (x), insn, true);
5161 : if (split && split != &SET_SRC (x))
5162 : return split;
5163 : }
5164 : break;
5165 :
5166 513 : case SIGN_EXTEND:
5167 513 : inner = XEXP (SET_SRC (x), 0);
5168 :
5169 : /* We can't optimize if either mode is a partial integer
5170 : mode as we don't know how many bits are significant
5171 : in those modes. */
5172 513 : if (!is_int_mode (GET_MODE (inner), &inner_mode)
5173 507 : || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5174 : break;
5175 :
5176 507 : pos = 0;
5177 507 : len = GET_MODE_PRECISION (inner_mode);
5178 507 : unsignedp = false;
5179 507 : break;
5180 :
5181 12625 : case SIGN_EXTRACT:
5182 12625 : case ZERO_EXTRACT:
5183 12625 : if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5184 : &inner_mode)
5185 12321 : && CONST_INT_P (XEXP (SET_SRC (x), 1))
5186 12321 : && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5187 : {
5188 11893 : inner = XEXP (SET_SRC (x), 0);
5189 11893 : len = INTVAL (XEXP (SET_SRC (x), 1));
5190 11893 : pos = INTVAL (XEXP (SET_SRC (x), 2));
5191 :
5192 11893 : if (BITS_BIG_ENDIAN)
5193 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5194 11893 : unsignedp = (code == ZERO_EXTRACT);
5195 : }
5196 : break;
5197 :
5198 : default:
5199 : break;
5200 : }
5201 :
5202 481709 : if (len
5203 12400 : && known_subrange_p (pos, len,
5204 12400 : 0, GET_MODE_PRECISION (GET_MODE (inner)))
5205 494109 : && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5206 : {
5207 : /* For unsigned, we have a choice of a shift followed by an
5208 : AND or two shifts. Use two shifts for field sizes where the
5209 : constant might be too large. We assume here that we can
5210 : always at least get 8-bit constants in an AND insn, which is
5211 : true for every current RISC. */
5212 :
5213 12400 : if (unsignedp && len <= 8)
5214 : {
5215 5264 : unsigned HOST_WIDE_INT mask
5216 5264 : = (HOST_WIDE_INT_1U << len) - 1;
5217 5264 : rtx pos_rtx = gen_int_shift_amount (mode, pos);
5218 5264 : SUBST (SET_SRC (x),
5219 : gen_rtx_AND (mode,
5220 : gen_rtx_LSHIFTRT
5221 : (mode, gen_lowpart (mode, inner), pos_rtx),
5222 : gen_int_mode (mask, mode)));
5223 :
5224 5264 : split = find_split_point (&SET_SRC (x), insn, true);
5225 5264 : if (split && split != &SET_SRC (x))
5226 31665238 : return split;
5227 : }
5228 : else
5229 : {
5230 7136 : int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5231 7136 : int right_bits = GET_MODE_PRECISION (mode) - len;
5232 14272 : SUBST (SET_SRC (x),
5233 : gen_rtx_fmt_ee
5234 : (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5235 : gen_rtx_ASHIFT (mode,
5236 : gen_lowpart (mode, inner),
5237 : gen_int_shift_amount (mode, left_bits)),
5238 : gen_int_shift_amount (mode, right_bits)));
5239 :
5240 7136 : split = find_split_point (&SET_SRC (x), insn, true);
5241 7136 : if (split && split != &SET_SRC (x))
5242 31665238 : return split;
5243 : }
5244 : }
5245 :
5246 : /* See if this is a simple operation with a constant as the second
5247 : operand. It might be that this constant is out of range and hence
5248 : could be used as a split point. */
5249 469309 : if (BINARY_P (SET_SRC (x))
5250 205927 : && CONSTANT_P (XEXP (SET_SRC (x), 1))
5251 114916 : && (OBJECT_P (XEXP (SET_SRC (x), 0))
5252 37543 : || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5253 11250 : && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5254 79203 : return &XEXP (SET_SRC (x), 1);
5255 :
5256 : /* Finally, see if this is a simple operation with its first operand
5257 : not in a register. The operation might require this operand in a
5258 : register, so return it as a split point. We can always do this
5259 : because if the first operand were another operation, we would have
5260 : already found it as a split point. */
5261 390106 : if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5262 390106 : && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5263 120859 : return &XEXP (SET_SRC (x), 0);
5264 :
5265 : return 0;
5266 :
5267 1002416 : case AND:
5268 1002416 : case IOR:
5269 : /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5270 : it is better to write this as (not (ior A B)) so we can split it.
5271 : Similarly for IOR. */
5272 1002416 : if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5273 : {
5274 1816 : SUBST (*loc,
5275 : gen_rtx_NOT (GET_MODE (x),
5276 : gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5277 : GET_MODE (x),
5278 : XEXP (XEXP (x, 0), 0),
5279 : XEXP (XEXP (x, 1), 0))));
5280 908 : return find_split_point (loc, insn, set_src);
5281 : }
5282 :
5283 : /* Many RISC machines have a large set of logical insns. If the
5284 : second operand is a NOT, put it first so we will try to split the
5285 : other operand first. */
5286 1001508 : if (GET_CODE (XEXP (x, 1)) == NOT)
5287 : {
5288 5410 : rtx tem = XEXP (x, 0);
5289 5410 : SUBST (XEXP (x, 0), XEXP (x, 1));
5290 5410 : SUBST (XEXP (x, 1), tem);
5291 : }
5292 : /* Many targets have a `(and (not X) Y)` and/or `(ior (not X) Y)` instructions.
5293 : Split at that insns. However if this is
5294 : the SET_SRC, we likely do not have such an instruction and it's
5295 : worthless to try this split. */
5296 1001508 : if (!set_src && GET_CODE (XEXP (x, 0)) == NOT)
5297 : return loc;
5298 : break;
5299 :
5300 3426372 : case PLUS:
5301 3426372 : case MINUS:
5302 : /* Canonicalization can produce (minus A (mult B C)), where C is a
5303 : constant. It may be better to try splitting (plus (mult B -C) A)
5304 : instead if this isn't a multiply by a power of two. */
5305 198285 : if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5306 21493 : && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5307 3432085 : && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5308 : {
5309 5713 : machine_mode mode = GET_MODE (x);
5310 5713 : unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5311 5713 : HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5312 5713 : SUBST (*loc, gen_rtx_PLUS (mode,
5313 : gen_rtx_MULT (mode,
5314 : XEXP (XEXP (x, 1), 0),
5315 : gen_int_mode (other_int,
5316 : mode)),
5317 : XEXP (x, 0)));
5318 5713 : return find_split_point (loc, insn, set_src);
5319 : }
5320 :
5321 : /* Split at a multiply-accumulate instruction. However if this is
5322 : the SET_SRC, we likely do not have such an instruction and it's
5323 : worthless to try this split. */
5324 3420659 : if (!set_src
5325 2035948 : && (GET_CODE (XEXP (x, 0)) == MULT
5326 1920848 : || (GET_CODE (XEXP (x, 0)) == ASHIFT
5327 136989 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5328 : return loc;
5329 :
5330 : default:
5331 : break;
5332 : }
5333 :
5334 : /* Otherwise, select our actions depending on our rtx class. */
5335 26396897 : switch (GET_RTX_CLASS (code))
5336 : {
5337 1515553 : case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5338 1515553 : case RTX_TERNARY:
5339 1515553 : split = find_split_point (&XEXP (x, 2), insn, false);
5340 1515553 : if (split)
5341 : return split;
5342 : /* fall through */
5343 10398638 : case RTX_BIN_ARITH:
5344 10398638 : case RTX_COMM_ARITH:
5345 10398638 : case RTX_COMPARE:
5346 10398638 : case RTX_COMM_COMPARE:
5347 10398638 : split = find_split_point (&XEXP (x, 1), insn, false);
5348 10398638 : if (split)
5349 : return split;
5350 : /* fall through */
5351 10003883 : case RTX_UNARY:
5352 : /* Some machines have (and (shift ...) ...) insns. If X is not
5353 : an AND, but XEXP (X, 0) is, use it as our split point. */
5354 10003883 : if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5355 378005 : return &XEXP (x, 0);
5356 :
5357 9625878 : split = find_split_point (&XEXP (x, 0), insn, false);
5358 9625878 : if (split)
5359 5901956 : return split;
5360 : return loc;
5361 :
5362 : default:
5363 : /* Otherwise, we don't have a split point. */
5364 : return 0;
5365 : }
5366 : }
5367 :
5368 : /* Throughout X, replace FROM with TO, and return the result.
5369 : The result is TO if X is FROM;
5370 : otherwise the result is X, but its contents may have been modified.
5371 : If they were modified, a record was made in undobuf so that
5372 : undo_all will (among other things) return X to its original state.
5373 :
5374 : If the number of changes necessary is too much to record to undo,
5375 : the excess changes are not made, so the result is invalid.
5376 : The changes already made can still be undone.
5377 : undobuf.num_undo is incremented for such changes, so by testing that
5378 : the caller can tell whether the result is valid.
5379 :
5380 : `n_occurrences' is incremented each time FROM is replaced.
5381 :
5382 : IN_DEST is true if we are processing the SET_DEST of a SET.
5383 :
5384 : IN_COND is true if we are at the top level of a condition.
5385 :
5386 : UNIQUE_COPY is true if each substitution must be unique. We do this
5387 : by copying if `n_occurrences' is nonzero. */
5388 :
5389 : static rtx
5390 426057777 : subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5391 : {
5392 426057777 : enum rtx_code code = GET_CODE (x);
5393 426057777 : machine_mode op0_mode = VOIDmode;
5394 426057777 : const char *fmt;
5395 426057777 : int len, i;
5396 426057777 : rtx new_rtx;
5397 :
5398 : /* Two expressions are equal if they are identical copies of a shared
5399 : RTX or if they are both registers with the same register number
5400 : and mode. */
5401 :
5402 : #define COMBINE_RTX_EQUAL_P(X,Y) \
5403 : ((X) == (Y) \
5404 : || (REG_P (X) && REG_P (Y) \
5405 : && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5406 :
5407 : /* Do not substitute into clobbers of regs -- this will never result in
5408 : valid RTL. */
5409 426057777 : if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5410 : return x;
5411 :
5412 415359798 : if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5413 : {
5414 0 : n_occurrences++;
5415 0 : return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5416 : }
5417 :
5418 : /* If X and FROM are the same register but different modes, they
5419 : will not have been seen as equal above. However, the log links code
5420 : will make a LOG_LINKS entry for that case. If we do nothing, we
5421 : will try to rerecognize our original insn and, when it succeeds,
5422 : we will delete the feeding insn, which is incorrect.
5423 :
5424 : So force this insn not to match in this (rare) case. */
5425 92385279 : if (! in_dest && code == REG && REG_P (from)
5426 448491749 : && reg_overlap_mentioned_p (x, from))
5427 4689 : return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5428 :
5429 : /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5430 : of which may contain things that can be combined. */
5431 415355109 : if (code != MEM && code != LO_SUM && OBJECT_P (x))
5432 : return x;
5433 :
5434 : /* It is possible to have a subexpression appear twice in the insn.
5435 : Suppose that FROM is a register that appears within TO.
5436 : Then, after that subexpression has been scanned once by `subst',
5437 : the second time it is scanned, TO may be found. If we were
5438 : to scan TO here, we would find FROM within it and create a
5439 : self-referent rtl structure which is completely wrong. */
5440 222452421 : if (COMBINE_RTX_EQUAL_P (x, to))
5441 : return to;
5442 :
5443 : /* Parallel asm_operands need special attention because all of the
5444 : inputs are shared across the arms. Furthermore, unsharing the
5445 : rtl results in recognition failures. Failure to handle this case
5446 : specially can result in circular rtl.
5447 :
5448 : Solve this by doing a normal pass across the first entry of the
5449 : parallel, and only processing the SET_DESTs of the subsequent
5450 : entries. Ug. */
5451 :
5452 222308192 : if (code == PARALLEL
5453 13301528 : && GET_CODE (XVECEXP (x, 0, 0)) == SET
5454 11285715 : && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5455 : {
5456 21578 : new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5457 :
5458 : /* If this substitution failed, this whole thing fails. */
5459 21578 : if (GET_CODE (new_rtx) == CLOBBER
5460 0 : && XEXP (new_rtx, 0) == const0_rtx)
5461 : return new_rtx;
5462 :
5463 21578 : SUBST (XVECEXP (x, 0, 0), new_rtx);
5464 :
5465 104698 : for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5466 : {
5467 83120 : rtx dest = SET_DEST (XVECEXP (x, 0, i));
5468 :
5469 83120 : if (!REG_P (dest) && GET_CODE (dest) != PC)
5470 : {
5471 2945 : new_rtx = subst (dest, from, to, false, false, unique_copy);
5472 :
5473 : /* If this substitution failed, this whole thing fails. */
5474 2945 : if (GET_CODE (new_rtx) == CLOBBER
5475 0 : && XEXP (new_rtx, 0) == const0_rtx)
5476 : return new_rtx;
5477 :
5478 2945 : SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5479 : }
5480 : }
5481 : }
5482 : else
5483 : {
5484 222286614 : len = GET_RTX_LENGTH (code);
5485 222286614 : fmt = GET_RTX_FORMAT (code);
5486 :
5487 : /* We don't need to process a SET_DEST that is a register or PC, so
5488 : set up to skip this common case. All other cases where we want
5489 : to suppress replacing something inside a SET_SRC are handled via
5490 : the IN_DEST operand. */
5491 222286614 : if (code == SET
5492 48579719 : && (REG_P (SET_DEST (x))
5493 48579719 : || GET_CODE (SET_DEST (x)) == PC))
5494 222286614 : fmt = "ie";
5495 :
5496 : /* Trying to simplify the operands of a widening MULT is not likely
5497 : to create RTL matching a machine insn. */
5498 222286614 : if (code == MULT
5499 4931859 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5500 4931859 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5501 313730 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5502 313730 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5503 234602 : && REG_P (XEXP (XEXP (x, 0), 0))
5504 108266 : && REG_P (XEXP (XEXP (x, 1), 0))
5505 95700 : && from == to)
5506 : return x;
5507 :
5508 :
5509 : /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5510 : constant. */
5511 222227931 : if (fmt[0] == 'e')
5512 163804141 : op0_mode = GET_MODE (XEXP (x, 0));
5513 :
5514 658334421 : for (i = 0; i < len; i++)
5515 : {
5516 437085693 : if (fmt[i] == 'E')
5517 : {
5518 15768362 : int j;
5519 50090118 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5520 : {
5521 34454230 : if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5522 : {
5523 1662 : new_rtx = (unique_copy && n_occurrences
5524 304156 : ? copy_rtx (to) : to);
5525 304137 : n_occurrences++;
5526 : }
5527 : else
5528 : {
5529 34150093 : new_rtx = subst (XVECEXP (x, i, j), from, to,
5530 : false, false, unique_copy);
5531 :
5532 : /* If this substitution failed, this whole thing
5533 : fails. */
5534 34150093 : if (GET_CODE (new_rtx) == CLOBBER
5535 11146704 : && XEXP (new_rtx, 0) == const0_rtx)
5536 : return new_rtx;
5537 : }
5538 :
5539 34321756 : SUBST (XVECEXP (x, i, j), new_rtx);
5540 : }
5541 : }
5542 421317331 : else if (fmt[i] == 'e')
5543 : {
5544 : /* If this is a register being set, ignore it. */
5545 343689846 : new_rtx = XEXP (x, i);
5546 343689846 : if (in_dest
5547 343689846 : && i == 0
5548 5958454 : && (((code == SUBREG || code == ZERO_EXTRACT)
5549 365644 : && REG_P (new_rtx))
5550 5595254 : || code == STRICT_LOW_PART))
5551 : ;
5552 :
5553 343316044 : else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5554 : {
5555 : /* In general, don't install a subreg involving two
5556 : modes not tieable. It can worsen register
5557 : allocation, and can even make invalid reload
5558 : insns, since the reg inside may need to be copied
5559 : from in the outside mode, and that may be invalid
5560 : if it is an fp reg copied in integer mode.
5561 :
5562 : We allow an exception to this: It is valid if
5563 : it is inside another SUBREG and the mode of that
5564 : SUBREG and the mode of the inside of TO is
5565 : tieable. */
5566 :
5567 48782382 : if (GET_CODE (to) == SUBREG
5568 605267 : && !targetm.modes_tieable_p (GET_MODE (to),
5569 605267 : GET_MODE (SUBREG_REG (to)))
5570 49114294 : && ! (code == SUBREG
5571 28945 : && (targetm.modes_tieable_p
5572 28945 : (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5573 300654 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5574 :
5575 48481728 : if (code == SUBREG
5576 2567401 : && REG_P (to)
5577 97835 : && REGNO (to) < FIRST_PSEUDO_REGISTER
5578 48481733 : && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5579 5 : SUBREG_BYTE (x),
5580 5 : GET_MODE (x)) < 0)
5581 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5582 :
5583 48481728 : new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5584 48481728 : n_occurrences++;
5585 : }
5586 : else
5587 : /* If we are in a SET_DEST, suppress most cases unless we
5588 : have gone inside a MEM, in which case we want to
5589 : simplify the address. We assume here that things that
5590 : are actually part of the destination have their inner
5591 : parts in the first expression. This is true for SUBREG,
5592 : STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5593 : things aside from REG and MEM that should appear in a
5594 : SET_DEST. */
5595 338670796 : new_rtx = subst (XEXP (x, i), from, to,
5596 : (((in_dest
5597 5303248 : && (code == SUBREG || code == STRICT_LOW_PART
5598 5303248 : || code == ZERO_EXTRACT))
5599 294525869 : || code == SET)
5600 : && i == 0),
5601 294533662 : code == IF_THEN_ELSE && i == 0,
5602 : unique_copy);
5603 :
5604 : /* If we found that we will have to reject this combination,
5605 : indicate that by returning the CLOBBER ourselves, rather than
5606 : an expression containing it. This will speed things up as
5607 : well as prevent accidents where two CLOBBERs are considered
5608 : to be equal, thus producing an incorrect simplification. */
5609 :
5610 343389192 : if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5611 : return new_rtx;
5612 :
5613 342843369 : if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5614 : {
5615 31751 : machine_mode mode = GET_MODE (x);
5616 :
5617 63502 : x = simplify_subreg (GET_MODE (x), new_rtx,
5618 31751 : GET_MODE (SUBREG_REG (x)),
5619 31751 : SUBREG_BYTE (x));
5620 31751 : if (! x)
5621 2 : x = gen_rtx_CLOBBER (mode, const0_rtx);
5622 : }
5623 342811618 : else if (CONST_SCALAR_INT_P (new_rtx)
5624 : && (GET_CODE (x) == ZERO_EXTEND
5625 62103752 : || GET_CODE (x) == SIGN_EXTEND
5626 : || GET_CODE (x) == FLOAT
5627 : || GET_CODE (x) == UNSIGNED_FLOAT))
5628 : {
5629 137636 : x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5630 : new_rtx,
5631 68818 : GET_MODE (XEXP (x, 0)));
5632 68818 : if (!x)
5633 252 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5634 : }
5635 : /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5636 : etc. arguments, otherwise we can ICE before trying to recog
5637 : it. See PR104446. */
5638 342742800 : else if (CONST_SCALAR_INT_P (new_rtx)
5639 62034934 : && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5640 0 : return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5641 : else
5642 342742800 : SUBST (XEXP (x, i), new_rtx);
5643 : }
5644 : }
5645 : }
5646 :
5647 : /* Check if we are loading something from the constant pool via float
5648 : extension; in this case we would undo compress_float_constant
5649 : optimization and degenerate constant load to an immediate value. */
5650 221270306 : if (GET_CODE (x) == FLOAT_EXTEND
5651 309316 : && MEM_P (XEXP (x, 0))
5652 221334224 : && MEM_READONLY_P (XEXP (x, 0)))
5653 : {
5654 36602 : rtx tmp = avoid_constant_pool_reference (x);
5655 36602 : if (x != tmp)
5656 : return x;
5657 : }
5658 :
5659 : /* Try to simplify X. If the simplification changed the code, it is likely
5660 : that further simplification will help, so loop, but limit the number
5661 : of repetitions that will be performed. */
5662 :
5663 229400607 : for (i = 0; i < 4; i++)
5664 : {
5665 : /* If X is sufficiently simple, don't bother trying to do anything
5666 : with it. */
5667 229346686 : if (code != CONST_INT && code != REG && code != CLOBBER)
5668 228672744 : x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5669 :
5670 229346686 : if (GET_CODE (x) == code)
5671 : break;
5672 :
5673 8166773 : code = GET_CODE (x);
5674 :
5675 : /* We no longer know the original mode of operand 0 since we
5676 : have changed the form of X) */
5677 8166773 : op0_mode = VOIDmode;
5678 : }
5679 :
5680 : return x;
5681 : }
5682 :
5683 : /* If X is a commutative operation whose operands are not in the canonical
5684 : order, use substitutions to swap them. */
5685 :
5686 : static void
5687 668362031 : maybe_swap_commutative_operands (rtx x)
5688 : {
5689 668362031 : if (COMMUTATIVE_ARITH_P (x)
5690 668362031 : && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5691 : {
5692 3538222 : rtx temp = XEXP (x, 0);
5693 3538222 : SUBST (XEXP (x, 0), XEXP (x, 1));
5694 3538222 : SUBST (XEXP (x, 1), temp);
5695 : }
5696 :
5697 : /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5698 : (vec_merge (fma op1 op2 op3) op1 mask). */
5699 668362031 : if (GET_CODE (x) == VEC_MERGE
5700 1107616 : && GET_CODE (XEXP (x, 0)) == FMA)
5701 : {
5702 25271 : rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5703 25271 : rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5704 25271 : rtx masked_op = XEXP (x, 1);
5705 25271 : if (rtx_equal_p (masked_op, fma_op2))
5706 : {
5707 218 : if (GET_CODE (fma_op1) == NEG)
5708 : {
5709 : /* Keep the negate canonicalized to the first operand. */
5710 150 : fma_op1 = XEXP (fma_op1, 0);
5711 150 : SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5712 150 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5713 : }
5714 : else
5715 : {
5716 68 : SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5717 68 : SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5718 : }
5719 : }
5720 : }
5721 :
5722 668362031 : unsigned n_elts = 0;
5723 668362031 : if (GET_CODE (x) == VEC_MERGE
5724 1107616 : && CONST_INT_P (XEXP (x, 2))
5725 1450076 : && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5726 669087069 : && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5727 : /* Two operands have same precedence, then
5728 : first bit of mask select first operand. */
5729 691155 : || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5730 156215 : && !(UINTVAL (XEXP (x, 2)) & 1))))
5731 : {
5732 65874 : rtx temp = XEXP (x, 0);
5733 65874 : unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5734 65874 : unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5735 65874 : if (n_elts == HOST_BITS_PER_WIDE_INT)
5736 : mask = -1;
5737 : else
5738 65733 : mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5739 65874 : SUBST (XEXP (x, 0), XEXP (x, 1));
5740 65874 : SUBST (XEXP (x, 1), temp);
5741 65874 : SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5742 : }
5743 668362031 : }
5744 :
5745 : /* Simplify X, a piece of RTL. We just operate on the expression at the
5746 : outer level; call `subst' to simplify recursively. Return the new
5747 : expression.
5748 :
5749 : OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5750 : if we are inside a SET_DEST. IN_COND is true if we are at the top level
5751 : of a condition. */
5752 :
5753 : static rtx
5754 229634526 : combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5755 : {
5756 229634526 : enum rtx_code code = GET_CODE (x);
5757 229634526 : machine_mode mode = GET_MODE (x);
5758 229634526 : scalar_int_mode int_mode;
5759 229634526 : rtx temp;
5760 229634526 : int i;
5761 :
5762 : /* If this is a commutative operation, put a constant last and a complex
5763 : expression first. We don't need to do this for comparisons here. */
5764 229634526 : maybe_swap_commutative_operands (x);
5765 :
5766 : /* Try to fold this expression in case we have constants that weren't
5767 : present before. */
5768 229634526 : temp = 0;
5769 229634526 : switch (GET_RTX_CLASS (code))
5770 : {
5771 7612529 : case RTX_UNARY:
5772 7612529 : if (op0_mode == VOIDmode)
5773 166333 : op0_mode = GET_MODE (XEXP (x, 0));
5774 7612529 : temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5775 7612529 : break;
5776 18553458 : case RTX_COMPARE:
5777 18553458 : case RTX_COMM_COMPARE:
5778 18553458 : {
5779 18553458 : machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5780 18553458 : if (cmp_mode == VOIDmode)
5781 : {
5782 49328 : cmp_mode = GET_MODE (XEXP (x, 1));
5783 49328 : if (cmp_mode == VOIDmode)
5784 8177 : cmp_mode = op0_mode;
5785 : }
5786 18553458 : temp = simplify_relational_operation (code, mode, cmp_mode,
5787 : XEXP (x, 0), XEXP (x, 1));
5788 : }
5789 18553458 : break;
5790 90720828 : case RTX_COMM_ARITH:
5791 90720828 : case RTX_BIN_ARITH:
5792 90720828 : temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5793 90720828 : break;
5794 14904978 : case RTX_BITFIELD_OPS:
5795 14904978 : case RTX_TERNARY:
5796 14904978 : temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5797 : XEXP (x, 1), XEXP (x, 2));
5798 14904978 : break;
5799 : default:
5800 : break;
5801 : }
5802 :
5803 131791793 : if (temp)
5804 : {
5805 17040016 : x = temp;
5806 17040016 : code = GET_CODE (temp);
5807 17040016 : op0_mode = VOIDmode;
5808 17040016 : mode = GET_MODE (temp);
5809 : }
5810 :
5811 : /* If this is a simple operation applied to an IF_THEN_ELSE, try
5812 : applying it to the arms of the IF_THEN_ELSE. This often simplifies
5813 : things. Check for cases where both arms are testing the same
5814 : condition.
5815 :
5816 : Don't do anything if all operands are very simple. */
5817 :
5818 229634526 : if ((BINARY_P (x)
5819 109013823 : && ((!OBJECT_P (XEXP (x, 0))
5820 42910222 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5821 5264261 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5822 69078873 : || (!OBJECT_P (XEXP (x, 1))
5823 4920498 : && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5824 1948613 : && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5825 186447774 : || (UNARY_P (x)
5826 7488828 : && (!OBJECT_P (XEXP (x, 0))
5827 3409786 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5828 903297 : && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5829 : {
5830 45785634 : rtx cond, true_rtx, false_rtx;
5831 :
5832 45785634 : cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5833 45785634 : if (cond != 0
5834 : /* If everything is a comparison, what we have is highly unlikely
5835 : to be simpler, so don't use it. */
5836 4641459 : && ! (COMPARISON_P (x)
5837 1271458 : && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5838 : /* Similarly, if we end up with one of the expressions the same
5839 : as the original, it is certainly not simpler. */
5840 4464858 : && ! rtx_equal_p (x, true_rtx)
5841 50250492 : && ! rtx_equal_p (x, false_rtx))
5842 : {
5843 4464858 : rtx cop1 = const0_rtx;
5844 4464858 : enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5845 :
5846 4464858 : if (cond_code == NE && COMPARISON_P (cond))
5847 672839 : return x;
5848 :
5849 : /* Simplify the alternative arms; this may collapse the true and
5850 : false arms to store-flag values. Be careful to use copy_rtx
5851 : here since true_rtx or false_rtx might share RTL with x as a
5852 : result of the if_then_else_cond call above. */
5853 3792019 : true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5854 : false, false, false);
5855 3792019 : false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5856 : false, false, false);
5857 :
5858 : /* If true_rtx and false_rtx are not general_operands, an if_then_else
5859 : is unlikely to be simpler. */
5860 3792019 : if (general_operand (true_rtx, VOIDmode)
5861 3792019 : && general_operand (false_rtx, VOIDmode))
5862 : {
5863 1420047 : enum rtx_code reversed;
5864 :
5865 : /* Restarting if we generate a store-flag expression will cause
5866 : us to loop. Just drop through in this case. */
5867 :
5868 : /* If the result values are STORE_FLAG_VALUE and zero, we can
5869 : just make the comparison operation. */
5870 1420047 : if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5871 626758 : x = simplify_gen_relational (cond_code, mode, VOIDmode,
5872 : cond, cop1);
5873 516781 : else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5874 793289 : && ((reversed = reversed_comparison_code_parts
5875 458542 : (cond_code, cond, cop1, NULL))
5876 : != UNKNOWN))
5877 458542 : x = simplify_gen_relational (reversed, mode, VOIDmode,
5878 : cond, cop1);
5879 :
5880 : /* Likewise, we can make the negate of a comparison operation
5881 : if the result values are - STORE_FLAG_VALUE and zero. */
5882 334747 : else if (CONST_INT_P (true_rtx)
5883 234110 : && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5884 46800 : && false_rtx == const0_rtx)
5885 45114 : x = simplify_gen_unary (NEG, mode,
5886 : simplify_gen_relational (cond_code,
5887 : mode, VOIDmode,
5888 : cond, cop1),
5889 : mode);
5890 289633 : else if (CONST_INT_P (false_rtx)
5891 226490 : && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5892 23893 : && true_rtx == const0_rtx
5893 289633 : && ((reversed = reversed_comparison_code_parts
5894 21455 : (cond_code, cond, cop1, NULL))
5895 : != UNKNOWN))
5896 21452 : x = simplify_gen_unary (NEG, mode,
5897 : simplify_gen_relational (reversed,
5898 : mode, VOIDmode,
5899 : cond, cop1),
5900 : mode);
5901 :
5902 1420047 : code = GET_CODE (x);
5903 1420047 : op0_mode = VOIDmode;
5904 : }
5905 : }
5906 : }
5907 :
5908 : /* First see if we can apply the inverse distributive law. */
5909 228961687 : if (code == PLUS || code == MINUS
5910 228961687 : || code == AND || code == IOR || code == XOR)
5911 : {
5912 51657923 : x = apply_distributive_law (x);
5913 51657923 : code = GET_CODE (x);
5914 51657923 : op0_mode = VOIDmode;
5915 : }
5916 :
5917 : /* If CODE is an associative operation not otherwise handled, see if we
5918 : can associate some operands. This can win if they are constants or
5919 : if they are logically related (i.e. (a & b) & a). */
5920 228961687 : if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5921 : || code == AND || code == IOR || code == XOR
5922 : || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5923 56204200 : && ((INTEGRAL_MODE_P (mode) && code != DIV)
5924 4760385 : || (flag_associative_math && FLOAT_MODE_P (mode))))
5925 : {
5926 52084653 : if (GET_CODE (XEXP (x, 0)) == code)
5927 : {
5928 4091192 : rtx other = XEXP (XEXP (x, 0), 0);
5929 4091192 : rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5930 4091192 : rtx inner_op1 = XEXP (x, 1);
5931 4091192 : rtx inner;
5932 :
5933 : /* Make sure we pass the constant operand if any as the second
5934 : one if this is a commutative operation. */
5935 4091192 : if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5936 : std::swap (inner_op0, inner_op1);
5937 4091192 : inner = simplify_binary_operation (code == MINUS ? PLUS
5938 3987849 : : code == DIV ? MULT
5939 : : code,
5940 : mode, inner_op0, inner_op1);
5941 :
5942 : /* For commutative operations, try the other pair if that one
5943 : didn't simplify. */
5944 4091192 : if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5945 : {
5946 3958518 : other = XEXP (XEXP (x, 0), 1);
5947 3958518 : inner = simplify_binary_operation (code, mode,
5948 : XEXP (XEXP (x, 0), 0),
5949 : XEXP (x, 1));
5950 : }
5951 :
5952 4058753 : if (inner)
5953 246167 : return simplify_gen_binary (code, mode, other, inner);
5954 : }
5955 : }
5956 :
5957 : /* A little bit of algebraic simplification here. */
5958 228715520 : switch (code)
5959 : {
5960 22954772 : case PREFETCH:
5961 : /* A prefetch reaches memory through an address, and targets recognize
5962 : that address with the same predicates they use for a MEM, so it
5963 : needs the same treatment. */
5964 22954772 : case MEM:
5965 : /* Ensure that our address has any ASHIFTs converted to MULT in case
5966 : address-recognizing predicates are called later. */
5967 22954772 : temp = make_compound_operation (XEXP (x, 0), MEM);
5968 22954772 : SUBST (XEXP (x, 0), temp);
5969 22954772 : break;
5970 :
5971 9687707 : case SUBREG:
5972 9687707 : if (op0_mode == VOIDmode)
5973 159392 : op0_mode = GET_MODE (SUBREG_REG (x));
5974 :
5975 : /* See if this can be moved to simplify_subreg. */
5976 9687707 : if (CONSTANT_P (SUBREG_REG (x))
5977 45784 : && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5978 : /* Don't call gen_lowpart if the inner mode
5979 : is VOIDmode and we cannot simplify it, as SUBREG without
5980 : inner mode is invalid. */
5981 9710599 : && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5982 0 : || gen_lowpart_common (mode, SUBREG_REG (x))))
5983 22892 : return gen_lowpart (mode, SUBREG_REG (x));
5984 :
5985 9664815 : if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5986 : break;
5987 9664815 : {
5988 9664815 : rtx temp;
5989 19329630 : temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5990 9664815 : SUBREG_BYTE (x));
5991 9664815 : if (temp)
5992 229634526 : return temp;
5993 :
5994 : /* If op is known to have all lower bits zero, the result is zero. */
5995 9018676 : scalar_int_mode int_mode, int_op0_mode;
5996 9018676 : if (!in_dest
5997 5470274 : && is_a <scalar_int_mode> (mode, &int_mode)
5998 5345259 : && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5999 5345259 : && (GET_MODE_PRECISION (int_mode)
6000 5345259 : < GET_MODE_PRECISION (int_op0_mode))
6001 4804747 : && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
6002 : SUBREG_BYTE (x))
6003 4312876 : && HWI_COMPUTABLE_MODE_P (int_op0_mode)
6004 4115378 : && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
6005 4115378 : & GET_MODE_MASK (int_mode)) == 0)
6006 9019666 : && !side_effects_p (SUBREG_REG (x)))
6007 990 : return CONST0_RTX (int_mode);
6008 : }
6009 :
6010 : /* Don't change the mode of the MEM if that would change the meaning
6011 : of the address. */
6012 9017686 : if (MEM_P (SUBREG_REG (x))
6013 9017686 : && (MEM_VOLATILE_P (SUBREG_REG (x))
6014 69686 : || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
6015 69720 : MEM_ADDR_SPACE (SUBREG_REG (x)))))
6016 45328 : return gen_rtx_CLOBBER (mode, const0_rtx);
6017 :
6018 : /* Note that we cannot do any narrowing for non-constants since
6019 : we might have been counting on using the fact that some bits were
6020 : zero. We now do this in the SET. */
6021 :
6022 : break;
6023 :
6024 387891 : case NEG:
6025 387891 : temp = expand_compound_operation (XEXP (x, 0));
6026 :
6027 : /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6028 : replaced by (lshiftrt X C). This will convert
6029 : (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6030 :
6031 387891 : if (GET_CODE (temp) == ASHIFTRT
6032 15118 : && CONST_INT_P (XEXP (temp, 1))
6033 418053 : && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
6034 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
6035 0 : INTVAL (XEXP (temp, 1)));
6036 :
6037 : /* If X has only a single bit that might be nonzero, say, bit I, convert
6038 : (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6039 : MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6040 : (sign_extract X 1 Y). But only do this if TEMP isn't a register
6041 : or a SUBREG of one since we'd be making the expression more
6042 : complex if it was just a register. */
6043 :
6044 387891 : if (!REG_P (temp)
6045 187160 : && ! (GET_CODE (temp) == SUBREG
6046 19693 : && REG_P (SUBREG_REG (temp)))
6047 229777451 : && is_a <scalar_int_mode> (mode, &int_mode)
6048 530816 : && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6049 : {
6050 67490 : rtx temp1 = simplify_shift_const
6051 67490 : (NULL_RTX, ASHIFTRT, int_mode,
6052 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6053 67490 : GET_MODE_PRECISION (int_mode) - 1 - i),
6054 67490 : GET_MODE_PRECISION (int_mode) - 1 - i);
6055 :
6056 : /* If all we did was surround TEMP with the two shifts, we
6057 : haven't improved anything, so don't use it. Otherwise,
6058 : we are better off with TEMP1. */
6059 67490 : if (GET_CODE (temp1) != ASHIFTRT
6060 66989 : || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6061 66989 : || XEXP (XEXP (temp1, 0), 0) != temp)
6062 6645 : return temp1;
6063 : }
6064 : break;
6065 :
6066 9837 : case TRUNCATE:
6067 : /* We can't handle truncation to a partial integer mode here
6068 : because we don't know the real bitsize of the partial
6069 : integer mode. */
6070 9837 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6071 : break;
6072 :
6073 9837 : if (HWI_COMPUTABLE_MODE_P (mode))
6074 0 : SUBST (XEXP (x, 0),
6075 : force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6076 : GET_MODE_MASK (mode), false));
6077 :
6078 : /* We can truncate a constant value and return it. */
6079 9837 : {
6080 9837 : poly_int64 c;
6081 9837 : if (poly_int_rtx_p (XEXP (x, 0), &c))
6082 0 : return gen_int_mode (c, mode);
6083 : }
6084 :
6085 : /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6086 : whose value is a comparison can be replaced with a subreg if
6087 : STORE_FLAG_VALUE permits. */
6088 9837 : if (HWI_COMPUTABLE_MODE_P (mode)
6089 0 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6090 0 : && (temp = get_last_value (XEXP (x, 0)))
6091 0 : && COMPARISON_P (temp)
6092 9837 : && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6093 0 : return gen_lowpart (mode, XEXP (x, 0));
6094 : break;
6095 :
6096 5354 : case CONST:
6097 : /* (const (const X)) can become (const X). Do it this way rather than
6098 : returning the inner CONST since CONST can be shared with a
6099 : REG_EQUAL note. */
6100 5354 : if (GET_CODE (XEXP (x, 0)) == CONST)
6101 0 : SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6102 : break;
6103 :
6104 : case LO_SUM:
6105 : /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6106 : can add in an offset. find_split_point will split this address up
6107 : again if it doesn't match. */
6108 : if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6109 : && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6110 : return XEXP (x, 1);
6111 : break;
6112 :
6113 35215920 : case PLUS:
6114 : /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6115 : when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6116 : bit-field and can be replaced by either a sign_extend or a
6117 : sign_extract. The `and' may be a zero_extend and the two
6118 : <c>, -<c> constants may be reversed. */
6119 35215920 : if (GET_CODE (XEXP (x, 0)) == XOR
6120 35215920 : && is_a <scalar_int_mode> (mode, &int_mode)
6121 13801 : && CONST_INT_P (XEXP (x, 1))
6122 3816 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6123 3157 : && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6124 77 : && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6125 2 : || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6126 39 : && HWI_COMPUTABLE_MODE_P (int_mode)
6127 35215959 : && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6128 0 : && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6129 0 : && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6130 0 : == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6131 39 : || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6132 0 : && known_eq ((GET_MODE_PRECISION
6133 : (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6134 : (unsigned int) i + 1))))
6135 0 : return simplify_shift_const
6136 0 : (NULL_RTX, ASHIFTRT, int_mode,
6137 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6138 : XEXP (XEXP (XEXP (x, 0), 0), 0),
6139 0 : GET_MODE_PRECISION (int_mode) - (i + 1)),
6140 0 : GET_MODE_PRECISION (int_mode) - (i + 1));
6141 :
6142 : /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6143 : can become (ashiftrt (ashift (xor x 1) C) C) where C is
6144 : the bitsize of the mode - 1. This allows simplification of
6145 : "a = (b & 8) == 0;" */
6146 35215920 : if (XEXP (x, 1) == constm1_rtx
6147 743489 : && !REG_P (XEXP (x, 0))
6148 328520 : && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6149 33445 : && REG_P (SUBREG_REG (XEXP (x, 0))))
6150 35507365 : && is_a <scalar_int_mode> (mode, &int_mode)
6151 35517233 : && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6152 9868 : return simplify_shift_const
6153 9868 : (NULL_RTX, ASHIFTRT, int_mode,
6154 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6155 : gen_rtx_XOR (int_mode, XEXP (x, 0),
6156 : const1_rtx),
6157 9868 : GET_MODE_PRECISION (int_mode) - 1),
6158 19736 : GET_MODE_PRECISION (int_mode) - 1);
6159 :
6160 : /* If we are adding two things that have no bits in common, convert
6161 : the addition into an IOR. This will often be further simplified,
6162 : for example in cases like ((a & 1) + (a & 2)), which can
6163 : become a & 3. */
6164 :
6165 35206052 : if (HWI_COMPUTABLE_MODE_P (mode)
6166 31271875 : && (nonzero_bits (XEXP (x, 0), mode)
6167 31271875 : & nonzero_bits (XEXP (x, 1), mode)) == 0)
6168 : {
6169 : /* Try to simplify the expression further. */
6170 961782 : rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6171 961782 : temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6172 :
6173 : /* If we could, great. If not, do not go ahead with the IOR
6174 : replacement, since PLUS appears in many special purpose
6175 : address arithmetic instructions. */
6176 961782 : if (GET_CODE (temp) != CLOBBER
6177 961782 : && (GET_CODE (temp) != IOR
6178 956347 : || ((XEXP (temp, 0) != XEXP (x, 0)
6179 945656 : || XEXP (temp, 1) != XEXP (x, 1))
6180 10691 : && (XEXP (temp, 0) != XEXP (x, 1)
6181 50 : || XEXP (temp, 1) != XEXP (x, 0)))))
6182 : return temp;
6183 : }
6184 :
6185 : /* Canonicalize x + x into x << 1. */
6186 35189976 : if (GET_MODE_CLASS (mode) == MODE_INT
6187 31579701 : && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6188 35193150 : && !side_effects_p (XEXP (x, 0)))
6189 3161 : return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6190 :
6191 : break;
6192 :
6193 4152490 : case MINUS:
6194 : /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6195 : (and <foo> (const_int pow2-1)) */
6196 4152490 : if (is_a <scalar_int_mode> (mode, &int_mode)
6197 3493029 : && GET_CODE (XEXP (x, 1)) == AND
6198 95959 : && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6199 93247 : && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6200 47672 : && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6201 0 : return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6202 0 : -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6203 : break;
6204 :
6205 3263899 : case MULT:
6206 : /* If we have (mult (plus A B) C), apply the distributive law and then
6207 : the inverse distributive law to see if things simplify. This
6208 : occurs mostly in addresses, often when unrolling loops. */
6209 :
6210 3263899 : if (GET_CODE (XEXP (x, 0)) == PLUS)
6211 : {
6212 279944 : rtx result = distribute_and_simplify_rtx (x, 0);
6213 279944 : if (result)
6214 : return result;
6215 : }
6216 :
6217 : /* Try simplify a*(b/c) as (a*b)/c. */
6218 3263076 : if (FLOAT_MODE_P (mode) && flag_associative_math
6219 203419 : && GET_CODE (XEXP (x, 0)) == DIV)
6220 : {
6221 244 : rtx tem = simplify_binary_operation (MULT, mode,
6222 : XEXP (XEXP (x, 0), 0),
6223 : XEXP (x, 1));
6224 244 : if (tem)
6225 32 : return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6226 : }
6227 : break;
6228 :
6229 120107 : case UDIV:
6230 : /* If this is a divide by a power of two, treat it as a shift if
6231 : its first operand is a shift. */
6232 120107 : if (is_a <scalar_int_mode> (mode, &int_mode)
6233 120107 : && CONST_INT_P (XEXP (x, 1))
6234 2000 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6235 0 : && (GET_CODE (XEXP (x, 0)) == ASHIFT
6236 0 : || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6237 0 : || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6238 0 : || GET_CODE (XEXP (x, 0)) == ROTATE
6239 0 : || GET_CODE (XEXP (x, 0)) == ROTATERT))
6240 0 : return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6241 0 : XEXP (x, 0), i);
6242 : break;
6243 :
6244 18485143 : case EQ: case NE:
6245 18485143 : case GT: case GTU: case GE: case GEU:
6246 18485143 : case LT: case LTU: case LE: case LEU:
6247 18485143 : case UNEQ: case LTGT:
6248 18485143 : case UNGT: case UNGE:
6249 18485143 : case UNLT: case UNLE:
6250 18485143 : case UNORDERED: case ORDERED:
6251 : /* If the first operand is a condition code, we can't do anything
6252 : with it. */
6253 18485143 : if (GET_CODE (XEXP (x, 0)) == COMPARE
6254 18485143 : || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6255 : {
6256 13934810 : rtx op0 = XEXP (x, 0);
6257 13934810 : rtx op1 = XEXP (x, 1);
6258 13934810 : enum rtx_code new_code;
6259 :
6260 13934810 : if (GET_CODE (op0) == COMPARE)
6261 0 : op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6262 :
6263 : /* Simplify our comparison, if possible. */
6264 13934810 : new_code = simplify_comparison (code, &op0, &op1);
6265 :
6266 : /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6267 : if only the low-order bit is possibly nonzero in X (such as when
6268 : X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6269 : (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6270 : known to be either 0 or -1, NE becomes a NEG and EQ becomes
6271 : (plus X 1).
6272 :
6273 : Remove any ZERO_EXTRACT we made when thinking this was a
6274 : comparison. It may now be simpler to use, e.g., an AND. If a
6275 : ZERO_EXTRACT is indeed appropriate, it will be placed back by
6276 : the call to make_compound_operation in the SET case.
6277 :
6278 : Don't apply these optimizations if the caller would
6279 : prefer a comparison rather than a value.
6280 : E.g., for the condition in an IF_THEN_ELSE most targets need
6281 : an explicit comparison. */
6282 :
6283 13934810 : if (in_cond)
6284 : ;
6285 :
6286 2158540 : else if (STORE_FLAG_VALUE == 1
6287 : && new_code == NE
6288 2603126 : && is_int_mode (mode, &int_mode)
6289 444801 : && op1 == const0_rtx
6290 230789 : && int_mode == GET_MODE (op0)
6291 2253258 : && nonzero_bits (op0, int_mode) == 1)
6292 215 : return gen_lowpart (int_mode,
6293 472884 : expand_compound_operation (op0));
6294 :
6295 2158325 : else if (STORE_FLAG_VALUE == 1
6296 : && new_code == NE
6297 2601938 : && is_int_mode (mode, &int_mode)
6298 444586 : && op1 == const0_rtx
6299 230574 : && int_mode == GET_MODE (op0)
6300 2252828 : && (num_sign_bit_copies (op0, int_mode)
6301 94503 : == GET_MODE_PRECISION (int_mode)))
6302 : {
6303 973 : op0 = expand_compound_operation (op0);
6304 973 : return simplify_gen_unary (NEG, int_mode,
6305 973 : gen_lowpart (int_mode, op0),
6306 973 : int_mode);
6307 : }
6308 :
6309 2157352 : else if (STORE_FLAG_VALUE == 1
6310 : && new_code == EQ
6311 2494361 : && is_int_mode (mode, &int_mode)
6312 339185 : && op1 == const0_rtx
6313 136531 : && int_mode == GET_MODE (op0)
6314 2201673 : && nonzero_bits (op0, int_mode) == 1)
6315 : {
6316 2176 : op0 = expand_compound_operation (op0);
6317 2176 : return simplify_gen_binary (XOR, int_mode,
6318 2176 : gen_lowpart (int_mode, op0),
6319 2176 : const1_rtx);
6320 : }
6321 :
6322 2155176 : else if (STORE_FLAG_VALUE == 1
6323 : && new_code == EQ
6324 14267889 : && is_int_mode (mode, &int_mode)
6325 337009 : && op1 == const0_rtx
6326 134355 : && int_mode == GET_MODE (op0)
6327 2197321 : && (num_sign_bit_copies (op0, int_mode)
6328 42145 : == GET_MODE_PRECISION (int_mode)))
6329 : {
6330 566 : op0 = expand_compound_operation (op0);
6331 566 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6332 : }
6333 :
6334 : /* If STORE_FLAG_VALUE is -1, we have cases similar to
6335 : those above. */
6336 13930880 : if (in_cond)
6337 : ;
6338 :
6339 13930880 : else if (STORE_FLAG_VALUE == -1
6340 : && new_code == NE
6341 : && is_int_mode (mode, &int_mode)
6342 : && op1 == const0_rtx
6343 : && int_mode == GET_MODE (op0)
6344 : && (num_sign_bit_copies (op0, int_mode)
6345 : == GET_MODE_PRECISION (int_mode)))
6346 : return gen_lowpart (int_mode, expand_compound_operation (op0));
6347 :
6348 13930880 : else if (STORE_FLAG_VALUE == -1
6349 : && new_code == NE
6350 : && is_int_mode (mode, &int_mode)
6351 : && op1 == const0_rtx
6352 : && int_mode == GET_MODE (op0)
6353 : && nonzero_bits (op0, int_mode) == 1)
6354 : {
6355 : op0 = expand_compound_operation (op0);
6356 : return simplify_gen_unary (NEG, int_mode,
6357 : gen_lowpart (int_mode, op0),
6358 : int_mode);
6359 : }
6360 :
6361 13930880 : else if (STORE_FLAG_VALUE == -1
6362 : && new_code == EQ
6363 : && is_int_mode (mode, &int_mode)
6364 : && op1 == const0_rtx
6365 : && int_mode == GET_MODE (op0)
6366 : && (num_sign_bit_copies (op0, int_mode)
6367 : == GET_MODE_PRECISION (int_mode)))
6368 : {
6369 : op0 = expand_compound_operation (op0);
6370 : return simplify_gen_unary (NOT, int_mode,
6371 : gen_lowpart (int_mode, op0),
6372 : int_mode);
6373 : }
6374 :
6375 : /* If X is 0/1, (eq X 0) is X-1. */
6376 13930880 : else if (STORE_FLAG_VALUE == -1
6377 : && new_code == EQ
6378 : && is_int_mode (mode, &int_mode)
6379 : && op1 == const0_rtx
6380 : && int_mode == GET_MODE (op0)
6381 : && nonzero_bits (op0, int_mode) == 1)
6382 : {
6383 : op0 = expand_compound_operation (op0);
6384 : return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6385 : }
6386 :
6387 : /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6388 : one bit that might be nonzero, we can convert (ne x 0) to
6389 : (ashift x c) where C puts the bit in the sign bit. Remove any
6390 : AND with STORE_FLAG_VALUE when we are done, since we are only
6391 : going to test the sign bit. */
6392 13930880 : if (new_code == NE
6393 14370174 : && is_int_mode (mode, &int_mode)
6394 443683 : && HWI_COMPUTABLE_MODE_P (int_mode)
6395 439294 : && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6396 0 : && op1 == const0_rtx
6397 0 : && int_mode == GET_MODE (op0)
6398 13930880 : && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6399 : {
6400 0 : x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6401 : expand_compound_operation (op0),
6402 0 : GET_MODE_PRECISION (int_mode) - 1 - i);
6403 0 : if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6404 0 : return XEXP (x, 0);
6405 : else
6406 : return x;
6407 : }
6408 :
6409 : /* If the code changed, return a whole new comparison.
6410 : We also need to avoid using SUBST in cases where
6411 : simplify_comparison has widened a comparison with a CONST_INT,
6412 : since in that case the wider CONST_INT may fail the sanity
6413 : checks in do_SUBST. */
6414 13930880 : if (new_code != code
6415 13469584 : || (CONST_INT_P (op1)
6416 7638588 : && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6417 9042 : && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6418 468954 : return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6419 :
6420 : /* Otherwise, keep this operation, but maybe change its operands.
6421 : This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6422 13461926 : SUBST (XEXP (x, 0), op0);
6423 13461926 : SUBST (XEXP (x, 1), op1);
6424 : }
6425 : break;
6426 :
6427 13622581 : case IF_THEN_ELSE:
6428 13622581 : return simplify_if_then_else (x);
6429 :
6430 4879487 : case ZERO_EXTRACT:
6431 4879487 : case SIGN_EXTRACT:
6432 4879487 : case ZERO_EXTEND:
6433 4879487 : case SIGN_EXTEND:
6434 : /* If we are processing SET_DEST, we are done. */
6435 4879487 : if (in_dest)
6436 : return x;
6437 :
6438 4876739 : return expand_compound_operation (x);
6439 :
6440 48222255 : case SET:
6441 48222255 : return simplify_set (x);
6442 :
6443 11424985 : case AND:
6444 11424985 : case IOR:
6445 11424985 : return simplify_logical (x);
6446 :
6447 13612080 : case ASHIFT:
6448 13612080 : case LSHIFTRT:
6449 13612080 : case ASHIFTRT:
6450 13612080 : case ROTATE:
6451 13612080 : case ROTATERT:
6452 : /* If this is a shift by a constant amount, simplify it. */
6453 13612080 : if (CONST_INT_P (XEXP (x, 1)))
6454 13110833 : return simplify_shift_const (x, code, mode, XEXP (x, 0),
6455 13110833 : INTVAL (XEXP (x, 1)));
6456 :
6457 : else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6458 : SUBST (XEXP (x, 1),
6459 : force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6460 : (HOST_WIDE_INT_1U
6461 : << exact_log2 (GET_MODE_UNIT_BITSIZE
6462 : (GET_MODE (x)))) - 1, false));
6463 : break;
6464 2037521 : case VEC_SELECT:
6465 2037521 : {
6466 2037521 : rtx trueop0 = XEXP (x, 0);
6467 2037521 : mode = GET_MODE (trueop0);
6468 2037521 : rtx trueop1 = XEXP (x, 1);
6469 : /* If we select a low-part subreg, return that. */
6470 2037521 : if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6471 : {
6472 1173 : rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6473 1173 : if (new_rtx != NULL_RTX)
6474 1173 : return new_rtx;
6475 : }
6476 : }
6477 :
6478 : default:
6479 : break;
6480 : }
6481 :
6482 : return x;
6483 : }
6484 :
6485 : /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6486 :
6487 : static rtx
6488 13622581 : simplify_if_then_else (rtx x)
6489 : {
6490 13622581 : machine_mode mode = GET_MODE (x);
6491 13622581 : rtx cond = XEXP (x, 0);
6492 13622581 : rtx true_rtx = XEXP (x, 1);
6493 13622581 : rtx false_rtx = XEXP (x, 2);
6494 13622581 : enum rtx_code true_code = GET_CODE (cond);
6495 13622581 : bool comparison_p = COMPARISON_P (cond);
6496 13622581 : rtx temp;
6497 13622581 : int i;
6498 13622581 : enum rtx_code false_code;
6499 13622581 : rtx reversed;
6500 13622581 : scalar_int_mode int_mode, inner_mode;
6501 :
6502 : /* Simplify storing of the truth value. */
6503 13622581 : if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6504 0 : return simplify_gen_relational (true_code, mode, VOIDmode,
6505 0 : XEXP (cond, 0), XEXP (cond, 1));
6506 :
6507 : /* Also when the truth value has to be reversed. */
6508 13622036 : if (comparison_p
6509 13622036 : && true_rtx == const0_rtx && false_rtx == const_true_rtx
6510 0 : && (reversed = reversed_comparison (cond, mode)))
6511 : return reversed;
6512 :
6513 : /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6514 : in it is being compared against certain values. Get the true and false
6515 : comparisons and see if that says anything about the value of each arm. */
6516 :
6517 13622581 : if (comparison_p
6518 13622036 : && ((false_code = reversed_comparison_code (cond, NULL))
6519 : != UNKNOWN)
6520 27082369 : && REG_P (XEXP (cond, 0)))
6521 : {
6522 8417717 : HOST_WIDE_INT nzb;
6523 8417717 : rtx from = XEXP (cond, 0);
6524 8417717 : rtx true_val = XEXP (cond, 1);
6525 8417717 : rtx false_val = true_val;
6526 8417717 : bool swapped = false;
6527 :
6528 : /* If FALSE_CODE is EQ, swap the codes and arms. */
6529 :
6530 8417717 : if (false_code == EQ)
6531 : {
6532 3061083 : swapped = true, true_code = EQ, false_code = NE;
6533 3061083 : std::swap (true_rtx, false_rtx);
6534 : }
6535 :
6536 8417717 : scalar_int_mode from_mode;
6537 8417717 : if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6538 : {
6539 : /* If we are comparing against zero and the expression being
6540 : tested has only a single bit that might be nonzero, that is
6541 : its value when it is not equal to zero. Similarly if it is
6542 : known to be -1 or 0. */
6543 6980929 : if (true_code == EQ
6544 5091354 : && true_val == const0_rtx
6545 9088664 : && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6546 : {
6547 239451 : false_code = EQ;
6548 239451 : false_val = gen_int_mode (nzb, from_mode);
6549 : }
6550 6741478 : else if (true_code == EQ
6551 4851903 : && true_val == const0_rtx
6552 8609762 : && (num_sign_bit_copies (from, from_mode)
6553 1868284 : == GET_MODE_PRECISION (from_mode)))
6554 : {
6555 718 : false_code = EQ;
6556 718 : false_val = constm1_rtx;
6557 : }
6558 : }
6559 :
6560 : /* Now simplify an arm if we know the value of the register in the
6561 : branch and it is used in the arm. Be careful due to the potential
6562 : of locally-shared RTL. */
6563 :
6564 8417717 : if (reg_mentioned_p (from, true_rtx))
6565 320825 : true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6566 : from, true_val),
6567 : pc_rtx, pc_rtx, false, false, false);
6568 8417717 : if (reg_mentioned_p (from, false_rtx))
6569 139395 : false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6570 : from, false_val),
6571 : pc_rtx, pc_rtx, false, false, false);
6572 :
6573 13774351 : SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6574 13774351 : SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6575 :
6576 8417717 : true_rtx = XEXP (x, 1);
6577 8417717 : false_rtx = XEXP (x, 2);
6578 8417717 : true_code = GET_CODE (cond);
6579 : }
6580 :
6581 : /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6582 : reversed, do so to avoid needing two sets of patterns for
6583 : subtract-and-branch insns. Similarly if we have a constant in the true
6584 : arm, the false arm is the same as the first operand of the comparison, or
6585 : the false arm is more complicated than the true arm. */
6586 :
6587 13622581 : if (comparison_p
6588 13622036 : && reversed_comparison_code (cond, NULL) != UNKNOWN
6589 27082369 : && (true_rtx == pc_rtx
6590 13459788 : || (CONSTANT_P (true_rtx)
6591 11038187 : && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6592 13419293 : || true_rtx == const0_rtx
6593 13416295 : || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6594 13347461 : || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6595 18818 : && !OBJECT_P (false_rtx))
6596 13343904 : || reg_mentioned_p (true_rtx, false_rtx)
6597 13343808 : || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6598 : {
6599 173006 : SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6600 173006 : SUBST (XEXP (x, 1), false_rtx);
6601 173006 : SUBST (XEXP (x, 2), true_rtx);
6602 :
6603 173006 : std::swap (true_rtx, false_rtx);
6604 173006 : cond = XEXP (x, 0);
6605 :
6606 : /* It is possible that the conditional has been simplified out. */
6607 173006 : true_code = GET_CODE (cond);
6608 173006 : comparison_p = COMPARISON_P (cond);
6609 : }
6610 :
6611 : /* If the two arms are identical, we don't need the comparison. */
6612 :
6613 13622581 : if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6614 : return true_rtx;
6615 :
6616 : /* Convert a == b ? b : a to "a". */
6617 4031166 : if (true_code == EQ && ! side_effects_p (cond)
6618 4012243 : && !HONOR_NANS (mode)
6619 4009165 : && rtx_equal_p (XEXP (cond, 0), false_rtx)
6620 13623042 : && rtx_equal_p (XEXP (cond, 1), true_rtx))
6621 : return false_rtx;
6622 4947629 : else if (true_code == NE && ! side_effects_p (cond)
6623 4898823 : && !HONOR_NANS (mode)
6624 4745056 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6625 13691453 : && rtx_equal_p (XEXP (cond, 1), false_rtx))
6626 : return true_rtx;
6627 :
6628 : /* Look for cases where we have (abs x) or (neg (abs X)). */
6629 :
6630 13622563 : if (GET_MODE_CLASS (mode) == MODE_INT
6631 2229833 : && comparison_p
6632 2229813 : && XEXP (cond, 1) == const0_rtx
6633 1699316 : && GET_CODE (false_rtx) == NEG
6634 159 : && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6635 24 : && rtx_equal_p (true_rtx, XEXP (cond, 0))
6636 13622587 : && ! side_effects_p (true_rtx))
6637 24 : switch (true_code)
6638 : {
6639 24 : case GT:
6640 24 : case GE:
6641 24 : return simplify_gen_unary (ABS, mode, true_rtx, mode);
6642 0 : case LT:
6643 0 : case LE:
6644 0 : return
6645 0 : simplify_gen_unary (NEG, mode,
6646 : simplify_gen_unary (ABS, mode, true_rtx, mode),
6647 0 : mode);
6648 : default:
6649 : break;
6650 : }
6651 :
6652 : /* Look for MIN or MAX. */
6653 :
6654 13622539 : if ((! FLOAT_MODE_P (mode)
6655 170662 : || (flag_unsafe_math_optimizations
6656 438 : && !HONOR_NANS (mode)
6657 438 : && !HONOR_SIGNED_ZEROS (mode)))
6658 13452315 : && comparison_p
6659 13451938 : && rtx_equal_p (XEXP (cond, 0), true_rtx)
6660 142583 : && rtx_equal_p (XEXP (cond, 1), false_rtx)
6661 13742 : && ! side_effects_p (cond))
6662 13738 : switch (true_code)
6663 : {
6664 5138 : case GE:
6665 5138 : case GT:
6666 5138 : return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6667 4767 : case LE:
6668 4767 : case LT:
6669 4767 : return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6670 2926 : case GEU:
6671 2926 : case GTU:
6672 2926 : return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6673 907 : case LEU:
6674 907 : case LTU:
6675 907 : return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6676 : default:
6677 : break;
6678 : }
6679 :
6680 : /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6681 : second operand is zero, this can be done as (OP Z (mult COND C2)) where
6682 : C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6683 : SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6684 : We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6685 : neither 1 or -1, but it isn't worth checking for. */
6686 :
6687 13608801 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6688 : && comparison_p
6689 15738237 : && is_int_mode (mode, &int_mode)
6690 15824874 : && ! side_effects_p (x))
6691 : {
6692 2211974 : rtx t = make_compound_operation (true_rtx, SET);
6693 2211974 : rtx f = make_compound_operation (false_rtx, SET);
6694 2211974 : rtx cond_op0 = XEXP (cond, 0);
6695 2211974 : rtx cond_op1 = XEXP (cond, 1);
6696 2211974 : enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6697 2211974 : scalar_int_mode m = int_mode;
6698 2211974 : rtx z = 0, c1 = NULL_RTX;
6699 :
6700 2211974 : if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6701 : || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6702 : || GET_CODE (t) == ASHIFT
6703 : || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6704 238068 : && rtx_equal_p (XEXP (t, 0), f))
6705 75749 : c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6706 :
6707 : /* If an identity-zero op is commutative, check whether there
6708 : would be a match if we swapped the operands. */
6709 2047933 : else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6710 2037542 : || GET_CODE (t) == XOR)
6711 2149569 : && rtx_equal_p (XEXP (t, 1), f))
6712 10888 : c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6713 2125337 : else if (GET_CODE (t) == SIGN_EXTEND
6714 4649 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6715 4649 : && (GET_CODE (XEXP (t, 0)) == PLUS
6716 4649 : || GET_CODE (XEXP (t, 0)) == MINUS
6717 : || GET_CODE (XEXP (t, 0)) == IOR
6718 : || GET_CODE (XEXP (t, 0)) == XOR
6719 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6720 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6721 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6722 163 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6723 86 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6724 86 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6725 2125337 : && (num_sign_bit_copies (f, GET_MODE (f))
6726 0 : > (unsigned int)
6727 0 : (GET_MODE_PRECISION (int_mode)
6728 0 : - GET_MODE_PRECISION (inner_mode))))
6729 : {
6730 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6731 0 : extend_op = SIGN_EXTEND;
6732 0 : m = inner_mode;
6733 : }
6734 2125337 : else if (GET_CODE (t) == SIGN_EXTEND
6735 4649 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6736 4649 : && (GET_CODE (XEXP (t, 0)) == PLUS
6737 4513 : || GET_CODE (XEXP (t, 0)) == IOR
6738 4509 : || GET_CODE (XEXP (t, 0)) == XOR)
6739 140 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6740 4 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6741 4 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6742 2125341 : && (num_sign_bit_copies (f, GET_MODE (f))
6743 4 : > (unsigned int)
6744 4 : (GET_MODE_PRECISION (int_mode)
6745 4 : - GET_MODE_PRECISION (inner_mode))))
6746 : {
6747 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6748 0 : extend_op = SIGN_EXTEND;
6749 0 : m = inner_mode;
6750 : }
6751 2125337 : else if (GET_CODE (t) == ZERO_EXTEND
6752 5045 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6753 5045 : && (GET_CODE (XEXP (t, 0)) == PLUS
6754 5045 : || GET_CODE (XEXP (t, 0)) == MINUS
6755 : || GET_CODE (XEXP (t, 0)) == IOR
6756 : || GET_CODE (XEXP (t, 0)) == XOR
6757 : || GET_CODE (XEXP (t, 0)) == ASHIFT
6758 : || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6759 : || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6760 1507 : && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6761 104 : && HWI_COMPUTABLE_MODE_P (int_mode)
6762 104 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6763 104 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6764 2125337 : && ((nonzero_bits (f, GET_MODE (f))
6765 0 : & ~GET_MODE_MASK (inner_mode))
6766 : == 0))
6767 : {
6768 0 : c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6769 0 : extend_op = ZERO_EXTEND;
6770 0 : m = inner_mode;
6771 : }
6772 2125337 : else if (GET_CODE (t) == ZERO_EXTEND
6773 5045 : && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6774 5045 : && (GET_CODE (XEXP (t, 0)) == PLUS
6775 4149 : || GET_CODE (XEXP (t, 0)) == IOR
6776 4149 : || GET_CODE (XEXP (t, 0)) == XOR)
6777 896 : && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6778 18 : && HWI_COMPUTABLE_MODE_P (int_mode)
6779 18 : && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6780 18 : && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6781 2125337 : && ((nonzero_bits (f, GET_MODE (f))
6782 0 : & ~GET_MODE_MASK (inner_mode))
6783 : == 0))
6784 : {
6785 0 : c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6786 0 : extend_op = ZERO_EXTEND;
6787 0 : m = inner_mode;
6788 : }
6789 :
6790 86637 : if (z)
6791 : {
6792 86637 : machine_mode cm = m;
6793 86637 : if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6794 2479 : && GET_MODE (c1) != VOIDmode)
6795 1843 : cm = GET_MODE (c1);
6796 86637 : temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6797 : cond_op0, cond_op1),
6798 : pc_rtx, pc_rtx, false, false, false);
6799 86637 : temp = simplify_gen_binary (MULT, cm, temp,
6800 : simplify_gen_binary (MULT, cm, c1,
6801 : const_true_rtx));
6802 86637 : temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6803 86637 : temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6804 :
6805 86637 : if (extend_op != UNKNOWN)
6806 0 : temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6807 :
6808 13622581 : return temp;
6809 : }
6810 : }
6811 :
6812 : /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6813 : 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6814 : negation of a single bit, we can convert this operation to a shift. We
6815 : can actually do this more generally, but it doesn't seem worth it. */
6816 :
6817 13522164 : if (true_code == NE
6818 13522164 : && is_a <scalar_int_mode> (mode, &int_mode)
6819 450488 : && XEXP (cond, 1) == const0_rtx
6820 334436 : && false_rtx == const0_rtx
6821 51849 : && CONST_INT_P (true_rtx)
6822 13524200 : && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6823 0 : && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6824 2036 : || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6825 2036 : == GET_MODE_PRECISION (int_mode))
6826 0 : && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6827 0 : return
6828 0 : simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6829 0 : gen_lowpart (int_mode, XEXP (cond, 0)), i);
6830 :
6831 : /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6832 : non-zero bit in A is C1. */
6833 4930148 : if (true_code == NE && XEXP (cond, 1) == const0_rtx
6834 2320109 : && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6835 13624617 : && is_a <scalar_int_mode> (mode, &int_mode)
6836 2036 : && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6837 5 : && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6838 5 : == nonzero_bits (XEXP (cond, 0), inner_mode)
6839 13522164 : && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6840 : {
6841 0 : rtx val = XEXP (cond, 0);
6842 0 : if (inner_mode == int_mode)
6843 : return val;
6844 0 : else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6845 0 : return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6846 : }
6847 :
6848 : return x;
6849 : }
6850 :
6851 : /* Simplify X, a SET expression. Return the new expression. */
6852 :
6853 : static rtx
6854 48222255 : simplify_set (rtx x)
6855 : {
6856 48222255 : rtx src = SET_SRC (x);
6857 48222255 : rtx dest = SET_DEST (x);
6858 107983646 : machine_mode mode
6859 48222255 : = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6860 48222255 : rtx_insn *other_insn;
6861 48222255 : rtx *cc_use;
6862 48222255 : scalar_int_mode int_mode;
6863 :
6864 : /* (set (pc) (return)) gets written as (return). */
6865 48222255 : if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6866 : return src;
6867 :
6868 : /* Now that we know for sure which bits of SRC we are using, see if we can
6869 : simplify the expression for the object knowing that we only need the
6870 : low-order bits. */
6871 :
6872 48222255 : if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6873 : {
6874 21452744 : src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6875 21452744 : SUBST (SET_SRC (x), src);
6876 : }
6877 :
6878 : /* If the source is a COMPARE, look for the use of the comparison result
6879 : and try to simplify it unless we already have used undobuf.other_insn. */
6880 41397597 : if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6881 6824658 : && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6882 6203803 : && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6883 6203803 : && COMPARISON_P (*cc_use)
6884 54425542 : && rtx_equal_p (XEXP (*cc_use, 0), dest))
6885 : {
6886 6201446 : enum rtx_code old_code = GET_CODE (*cc_use);
6887 6201446 : enum rtx_code new_code;
6888 6201446 : rtx op0, op1, tmp;
6889 6201446 : bool other_changed = false;
6890 6201446 : rtx inner_compare = NULL_RTX;
6891 6201446 : machine_mode compare_mode = GET_MODE (dest);
6892 :
6893 6201446 : if (GET_CODE (src) == COMPARE)
6894 : {
6895 5753471 : op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6896 5753471 : if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6897 : {
6898 0 : inner_compare = op0;
6899 0 : op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6900 : }
6901 : }
6902 : else
6903 447975 : op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6904 :
6905 6201446 : tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6906 : op0, op1);
6907 6201446 : if (!tmp)
6908 : new_code = old_code;
6909 487026 : else if (!CONSTANT_P (tmp))
6910 : {
6911 482296 : new_code = GET_CODE (tmp);
6912 482296 : op0 = XEXP (tmp, 0);
6913 482296 : op1 = XEXP (tmp, 1);
6914 : }
6915 : else
6916 : {
6917 4730 : rtx pat = PATTERN (other_insn);
6918 4730 : undobuf.other_insn = other_insn;
6919 4730 : SUBST (*cc_use, tmp);
6920 :
6921 : /* Attempt to simplify CC user. */
6922 4730 : if (GET_CODE (pat) == SET)
6923 : {
6924 4230 : rtx new_rtx = simplify_rtx (SET_SRC (pat));
6925 4230 : if (new_rtx != NULL_RTX)
6926 3793 : SUBST (SET_SRC (pat), new_rtx);
6927 : }
6928 :
6929 : /* Convert X into a no-op move. */
6930 4730 : SUBST (SET_DEST (x), pc_rtx);
6931 4730 : SUBST (SET_SRC (x), pc_rtx);
6932 4730 : return x;
6933 : }
6934 :
6935 : /* Simplify our comparison, if possible. */
6936 6196716 : new_code = simplify_comparison (new_code, &op0, &op1);
6937 :
6938 : #ifdef SELECT_CC_MODE
6939 : /* If this machine has CC modes other than CCmode, check to see if we
6940 : need to use a different CC mode here. */
6941 6196716 : if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6942 684916 : compare_mode = GET_MODE (op0);
6943 5511800 : else if (inner_compare
6944 0 : && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6945 0 : && new_code == old_code
6946 0 : && op0 == XEXP (inner_compare, 0)
6947 0 : && op1 == XEXP (inner_compare, 1))
6948 0 : compare_mode = GET_MODE (inner_compare);
6949 : else
6950 5511800 : compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6951 :
6952 : /* If the mode changed, we have to change SET_DEST, the mode in the
6953 : compare, and the mode in the place SET_DEST is used. If SET_DEST is
6954 : a hard register, just build new versions with the proper mode. If it
6955 : is a pseudo, we lose unless it is only time we set the pseudo, in
6956 : which case we can safely change its mode. */
6957 6196716 : if (compare_mode != GET_MODE (dest))
6958 : {
6959 212004 : if (can_change_dest_mode (dest, 0, compare_mode))
6960 : {
6961 212004 : unsigned int regno = REGNO (dest);
6962 212004 : rtx new_dest;
6963 :
6964 212004 : if (regno < FIRST_PSEUDO_REGISTER)
6965 212004 : new_dest = gen_rtx_REG (compare_mode, regno);
6966 : else
6967 : {
6968 0 : subst_mode (regno, compare_mode);
6969 0 : new_dest = regno_reg_rtx[regno];
6970 : }
6971 :
6972 212004 : SUBST (SET_DEST (x), new_dest);
6973 212004 : SUBST (XEXP (*cc_use, 0), new_dest);
6974 212004 : other_changed = true;
6975 :
6976 212004 : dest = new_dest;
6977 : }
6978 : }
6979 : #endif /* SELECT_CC_MODE */
6980 :
6981 : /* If the code changed, we have to build a new comparison in
6982 : undobuf.other_insn. */
6983 6196716 : if (new_code != old_code)
6984 : {
6985 617391 : bool other_changed_previously = other_changed;
6986 617391 : unsigned HOST_WIDE_INT mask;
6987 617391 : rtx old_cc_use = *cc_use;
6988 :
6989 617391 : SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6990 : dest, const0_rtx));
6991 617391 : other_changed = true;
6992 :
6993 : /* If the only change we made was to change an EQ into an NE or
6994 : vice versa, OP0 has only one bit that might be nonzero, and OP1
6995 : is zero, check if changing the user of the condition code will
6996 : produce a valid insn. If it won't, we can keep the original code
6997 : in that insn by surrounding our operation with an XOR. */
6998 :
6999 617391 : if (((old_code == NE && new_code == EQ)
7000 577017 : || (old_code == EQ && new_code == NE))
7001 89704 : && ! other_changed_previously && op1 == const0_rtx
7002 86968 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
7003 627337 : && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
7004 : {
7005 9935 : rtx pat = PATTERN (other_insn), note = 0;
7006 :
7007 9935 : if ((recog_for_combine (&pat, other_insn, ¬e) < 0
7008 9935 : && ! check_asm_operands (pat)))
7009 : {
7010 6 : *cc_use = old_cc_use;
7011 6 : other_changed = false;
7012 :
7013 6 : op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
7014 6 : gen_int_mode (mask,
7015 6 : GET_MODE (op0)));
7016 : }
7017 : }
7018 : }
7019 :
7020 5589260 : if (other_changed)
7021 634701 : undobuf.other_insn = other_insn;
7022 :
7023 : /* Don't generate a compare of a CC with 0, just use that CC. */
7024 6196716 : if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
7025 : {
7026 684916 : SUBST (SET_SRC (x), op0);
7027 684916 : src = SET_SRC (x);
7028 : }
7029 : /* Otherwise, if we didn't previously have the same COMPARE we
7030 : want, create it from scratch. */
7031 5511800 : else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
7032 5391002 : || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
7033 : {
7034 1388844 : SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
7035 1388844 : src = SET_SRC (x);
7036 : }
7037 : }
7038 : else
7039 : {
7040 : /* Get SET_SRC in a form where we have placed back any
7041 : compound expressions. Then do the checks below. */
7042 42020809 : src = make_compound_operation (src, SET);
7043 42020809 : SUBST (SET_SRC (x), src);
7044 : }
7045 :
7046 : /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7047 : and X being a REG or (subreg (reg)), we may be able to convert this to
7048 : (set (subreg:m2 x) (op)).
7049 :
7050 : We can always do this if M1 is narrower than M2 because that means that
7051 : we only care about the low bits of the result.
7052 :
7053 : However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7054 : perform a narrower operation than requested since the high-order bits will
7055 : be undefined. On machine where it is defined, this transformation is safe
7056 : as long as M1 and M2 have the same number of words. */
7057 :
7058 431881 : if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7059 415915 : && !OBJECT_P (SUBREG_REG (src))
7060 : && (known_equal_after_align_up
7061 267148 : (GET_MODE_SIZE (GET_MODE (src)),
7062 534296 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7063 267148 : UNITS_PER_WORD))
7064 238154 : && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7065 225090 : && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7066 229 : && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7067 : GET_MODE (SUBREG_REG (src)),
7068 : GET_MODE (src)))
7069 48442386 : && (REG_P (dest)
7070 124004 : || (GET_CODE (dest) == SUBREG
7071 313 : && REG_P (SUBREG_REG (dest)))))
7072 : {
7073 101170 : SUBST (SET_DEST (x),
7074 : gen_lowpart (GET_MODE (SUBREG_REG (src)),
7075 : dest));
7076 101170 : SUBST (SET_SRC (x), SUBREG_REG (src));
7077 :
7078 101170 : src = SET_SRC (x), dest = SET_DEST (x);
7079 : }
7080 :
7081 : /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7082 : would require a paradoxical subreg. Replace the subreg with a
7083 : zero_extend to avoid the reload that would otherwise be required.
7084 : Don't do this unless we have a scalar integer mode, otherwise the
7085 : transformation is incorrect. */
7086 :
7087 48217525 : enum rtx_code extend_op;
7088 48217525 : if (paradoxical_subreg_p (src)
7089 : && MEM_P (SUBREG_REG (src))
7090 : && SCALAR_INT_MODE_P (GET_MODE (src))
7091 : && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7092 : {
7093 : SUBST (SET_SRC (x),
7094 : gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7095 :
7096 : src = SET_SRC (x);
7097 : }
7098 :
7099 : /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7100 : are comparing an item known to be 0 or -1 against 0, use a logical
7101 : operation instead. Check for one of the arms being an IOR of the other
7102 : arm with some value. We compute three terms to be IOR'ed together. In
7103 : practice, at most two will be nonzero. Then we do the IOR's. */
7104 :
7105 48217525 : if (GET_CODE (dest) != PC
7106 37115621 : && GET_CODE (src) == IF_THEN_ELSE
7107 1353796 : && is_int_mode (GET_MODE (src), &int_mode)
7108 1222883 : && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7109 480738 : && XEXP (XEXP (src, 0), 1) == const0_rtx
7110 353709 : && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7111 117368 : && (!HAVE_conditional_move
7112 117368 : || ! can_conditionally_move_p (int_mode))
7113 0 : && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7114 0 : == GET_MODE_PRECISION (int_mode))
7115 48217525 : && ! side_effects_p (src))
7116 : {
7117 0 : rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7118 0 : ? XEXP (src, 1) : XEXP (src, 2));
7119 0 : rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7120 0 : ? XEXP (src, 2) : XEXP (src, 1));
7121 0 : rtx term1 = const0_rtx, term2, term3;
7122 :
7123 0 : if (GET_CODE (true_rtx) == IOR
7124 0 : && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7125 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7126 0 : else if (GET_CODE (true_rtx) == IOR
7127 0 : && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7128 0 : term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7129 0 : else if (GET_CODE (false_rtx) == IOR
7130 0 : && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7131 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7132 0 : else if (GET_CODE (false_rtx) == IOR
7133 0 : && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7134 0 : term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7135 :
7136 0 : term2 = simplify_gen_binary (AND, int_mode,
7137 0 : XEXP (XEXP (src, 0), 0), true_rtx);
7138 0 : term3 = simplify_gen_binary (AND, int_mode,
7139 : simplify_gen_unary (NOT, int_mode,
7140 0 : XEXP (XEXP (src, 0), 0),
7141 : int_mode),
7142 : false_rtx);
7143 :
7144 0 : SUBST (SET_SRC (x),
7145 : simplify_gen_binary (IOR, int_mode,
7146 : simplify_gen_binary (IOR, int_mode,
7147 : term1, term2),
7148 : term3));
7149 :
7150 0 : src = SET_SRC (x);
7151 : }
7152 :
7153 : /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7154 : whole thing fail. */
7155 48217525 : if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7156 : return src;
7157 48217507 : else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7158 : return dest;
7159 : else
7160 : /* Convert this into a field assignment operation, if possible. */
7161 48217465 : return make_field_assignment (x);
7162 : }
7163 :
7164 : /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7165 : result. */
7166 :
7167 : static rtx
7168 11424985 : simplify_logical (rtx x)
7169 : {
7170 11424985 : rtx op0 = XEXP (x, 0);
7171 11424985 : rtx op1 = XEXP (x, 1);
7172 11424985 : scalar_int_mode mode;
7173 :
7174 11424985 : switch (GET_CODE (x))
7175 : {
7176 7252256 : case AND:
7177 : /* We can call simplify_and_const_int only if we don't lose
7178 : any (sign) bits when converting INTVAL (op1) to
7179 : "unsigned HOST_WIDE_INT". */
7180 7252256 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7181 6705178 : && CONST_INT_P (op1)
7182 5253111 : && (HWI_COMPUTABLE_MODE_P (mode)
7183 6723 : || INTVAL (op1) > 0))
7184 : {
7185 5249771 : x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7186 5249771 : if (GET_CODE (x) != AND)
7187 : return x;
7188 :
7189 5224923 : op0 = XEXP (x, 0);
7190 5224923 : op1 = XEXP (x, 1);
7191 : }
7192 :
7193 : /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7194 : apply the distributive law and then the inverse distributive
7195 : law to see if things simplify. */
7196 7227408 : if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7197 : {
7198 121387 : rtx result = distribute_and_simplify_rtx (x, 0);
7199 121387 : if (result)
7200 : return result;
7201 : }
7202 7213542 : if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7203 : {
7204 1941 : rtx result = distribute_and_simplify_rtx (x, 1);
7205 1941 : if (result)
7206 0 : return result;
7207 : }
7208 : break;
7209 :
7210 4172729 : case IOR:
7211 : /* If we have (ior (and A B) C), apply the distributive law and then
7212 : the inverse distributive law to see if things simplify. */
7213 :
7214 4172729 : if (GET_CODE (op0) == AND)
7215 : {
7216 1251700 : rtx result = distribute_and_simplify_rtx (x, 0);
7217 1251700 : if (result)
7218 : return result;
7219 : }
7220 :
7221 4169975 : if (GET_CODE (op1) == AND)
7222 : {
7223 57584 : rtx result = distribute_and_simplify_rtx (x, 1);
7224 57584 : if (result)
7225 4 : return result;
7226 : }
7227 : break;
7228 :
7229 0 : default:
7230 0 : gcc_unreachable ();
7231 : }
7232 :
7233 : return x;
7234 : }
7235 :
7236 : /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7237 : operations" because they can be replaced with two more basic operations.
7238 : ZERO_EXTEND is also considered "compound" because it can be replaced with
7239 : an AND operation, which is simpler, though only one operation.
7240 :
7241 : The function expand_compound_operation is called with an rtx expression
7242 : and will convert it to the appropriate shifts and AND operations,
7243 : simplifying at each stage.
7244 :
7245 : The function make_compound_operation is called to convert an expression
7246 : consisting of shifts and ANDs into the equivalent compound expression.
7247 : It is the inverse of this function, loosely speaking. */
7248 :
7249 : static rtx
7250 16805932 : expand_compound_operation (rtx x)
7251 : {
7252 16805932 : unsigned HOST_WIDE_INT pos = 0, len;
7253 16805932 : bool unsignedp = false;
7254 16805932 : unsigned int modewidth;
7255 16805932 : rtx tem;
7256 16805932 : scalar_int_mode inner_mode;
7257 :
7258 16805932 : switch (GET_CODE (x))
7259 : {
7260 4707013 : case ZERO_EXTEND:
7261 4707013 : unsignedp = true;
7262 : /* FALLTHRU */
7263 6057508 : case SIGN_EXTEND:
7264 : /* We can't necessarily use a const_int for a multiword mode;
7265 : it depends on implicitly extending the value.
7266 : Since we don't know the right way to extend it,
7267 : we can't tell whether the implicit way is right.
7268 :
7269 : Even for a mode that is no wider than a const_int,
7270 : we can't win, because we need to sign extend one of its bits through
7271 : the rest of it, and we don't know which bit. */
7272 6057508 : if (CONST_INT_P (XEXP (x, 0)))
7273 : return x;
7274 :
7275 : /* Reject modes that aren't scalar integers because turning vector
7276 : or complex modes into shifts causes problems. */
7277 6057508 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7278 : return x;
7279 :
7280 : /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7281 : (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7282 : because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7283 : reloaded. If not for that, MEM's would very rarely be safe.
7284 :
7285 : Reject modes bigger than a word, because we might not be able
7286 : to reference a two-register group starting with an arbitrary register
7287 : (and currently gen_lowpart might crash for a SUBREG). */
7288 :
7289 12227819 : if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7290 : return x;
7291 :
7292 5682162 : len = GET_MODE_PRECISION (inner_mode);
7293 : /* If the inner object has VOIDmode (the only way this can happen
7294 : is if it is an ASM_OPERANDS), we can't do anything since we don't
7295 : know how much masking to do. */
7296 5682162 : if (len == 0)
7297 : return x;
7298 :
7299 : break;
7300 :
7301 945394 : case ZERO_EXTRACT:
7302 945394 : unsignedp = true;
7303 :
7304 : /* fall through */
7305 :
7306 974743 : case SIGN_EXTRACT:
7307 : /* If the operand is a CLOBBER, just return it. */
7308 974743 : if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7309 : return XEXP (x, 0);
7310 :
7311 974737 : if (!CONST_INT_P (XEXP (x, 1))
7312 974614 : || !CONST_INT_P (XEXP (x, 2)))
7313 : return x;
7314 :
7315 : /* Reject modes that aren't scalar integers because turning vector
7316 : or complex modes into shifts causes problems. */
7317 901124 : if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7318 : return x;
7319 :
7320 901122 : len = INTVAL (XEXP (x, 1));
7321 901122 : pos = INTVAL (XEXP (x, 2));
7322 :
7323 : /* This should stay within the object being extracted, fail otherwise. */
7324 901122 : if (len + pos > GET_MODE_PRECISION (inner_mode))
7325 : return x;
7326 :
7327 : if (BITS_BIG_ENDIAN)
7328 : pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7329 :
7330 : break;
7331 :
7332 : default:
7333 : return x;
7334 : }
7335 :
7336 : /* We've rejected non-scalar operations by now. */
7337 6583235 : scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7338 :
7339 : /* Convert sign extension to zero extension, if we know that the high
7340 : bit is not set, as this is easier to optimize. It will be converted
7341 : back to cheaper alternative in make_extraction. */
7342 6583235 : if (GET_CODE (x) == SIGN_EXTEND
7343 1194218 : && HWI_COMPUTABLE_MODE_P (mode)
7344 7663880 : && ((nonzero_bits (XEXP (x, 0), inner_mode)
7345 1080645 : & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7346 : == 0))
7347 : {
7348 380 : rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7349 380 : rtx temp2 = expand_compound_operation (temp);
7350 :
7351 : /* Make sure this is a profitable operation. */
7352 380 : if (set_src_cost (x, mode, optimize_this_for_speed_p)
7353 380 : > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7354 : return temp2;
7355 336 : else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7356 336 : > set_src_cost (temp, mode, optimize_this_for_speed_p))
7357 : return temp;
7358 : else
7359 15 : return x;
7360 : }
7361 :
7362 : /* We can optimize some special cases of ZERO_EXTEND. */
7363 6582855 : if (GET_CODE (x) == ZERO_EXTEND)
7364 : {
7365 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7366 : know that the last value didn't have any inappropriate bits
7367 : set. */
7368 4487944 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7369 201 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7370 201 : && HWI_COMPUTABLE_MODE_P (mode)
7371 4488145 : && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7372 201 : & ~GET_MODE_MASK (inner_mode)) == 0)
7373 37 : return XEXP (XEXP (x, 0), 0);
7374 :
7375 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7376 4487907 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7377 677667 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7378 617029 : && subreg_lowpart_p (XEXP (x, 0))
7379 253816 : && HWI_COMPUTABLE_MODE_P (mode)
7380 4719266 : && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7381 231359 : & ~GET_MODE_MASK (inner_mode)) == 0)
7382 66 : return SUBREG_REG (XEXP (x, 0));
7383 :
7384 : /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7385 : is a comparison and STORE_FLAG_VALUE permits. This is like
7386 : the first case, but it works even when MODE is larger
7387 : than HOST_WIDE_INT. */
7388 4487841 : if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7389 164 : && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7390 164 : && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7391 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7392 4487841 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7393 : return XEXP (XEXP (x, 0), 0);
7394 :
7395 : /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7396 4487841 : if (GET_CODE (XEXP (x, 0)) == SUBREG
7397 677601 : && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7398 616963 : && subreg_lowpart_p (XEXP (x, 0))
7399 253750 : && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7400 0 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7401 4487841 : && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7402 : return SUBREG_REG (XEXP (x, 0));
7403 :
7404 : }
7405 :
7406 : /* If we reach here, we want to return a pair of shifts. The inner
7407 : shift is a left shift of BITSIZE - POS - LEN bits. The outer
7408 : shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7409 : logical depending on the value of UNSIGNEDP.
7410 :
7411 : If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7412 : converted into an AND of a shift.
7413 :
7414 : We must check for the case where the left shift would have a negative
7415 : count. This can happen in a case like (x >> 31) & 255 on machines
7416 : that can't shift by a constant. On those machines, we would first
7417 : combine the shift with the AND to produce a variable-position
7418 : extraction. Then the constant of 31 would be substituted in
7419 : to produce such a position. */
7420 :
7421 6582752 : modewidth = GET_MODE_PRECISION (mode);
7422 6582752 : if (modewidth >= pos + len)
7423 : {
7424 6582751 : tem = gen_lowpart (mode, XEXP (x, 0));
7425 6582751 : if (!tem || GET_CODE (tem) == CLOBBER)
7426 : return x;
7427 6927240 : tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7428 3463620 : tem, modewidth - pos - len);
7429 3463620 : tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7430 3463620 : mode, tem, modewidth - len);
7431 : }
7432 1 : else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7433 : {
7434 1 : tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7435 : XEXP (x, 0), pos);
7436 1 : tem = gen_lowpart (mode, tem);
7437 1 : if (!tem || GET_CODE (tem) == CLOBBER)
7438 : return x;
7439 1 : tem = simplify_and_const_int (NULL_RTX, mode, tem,
7440 1 : (HOST_WIDE_INT_1U << len) - 1);
7441 : }
7442 : else
7443 : /* Any other cases we can't handle. */
7444 : return x;
7445 :
7446 : /* If we couldn't do this for some reason, return the original
7447 : expression. */
7448 3463621 : if (GET_CODE (tem) == CLOBBER)
7449 15 : return x;
7450 :
7451 : return tem;
7452 : }
7453 :
7454 : /* X is a SET which contains an assignment of one object into
7455 : a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7456 : or certain SUBREGS). If possible, convert it into a series of
7457 : logical operations.
7458 :
7459 : We half-heartedly support variable positions, but do not at all
7460 : support variable lengths. */
7461 :
7462 : static const_rtx
7463 86222651 : expand_field_assignment (const_rtx x)
7464 : {
7465 86222651 : rtx inner;
7466 86222651 : rtx pos; /* Always counts from low bit. */
7467 86222651 : int len, inner_len;
7468 86222651 : rtx mask, cleared, masked;
7469 86222651 : scalar_int_mode compute_mode;
7470 :
7471 : /* Loop until we find something we can't simplify. */
7472 86491794 : while (1)
7473 : {
7474 86491794 : if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7475 14232 : && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7476 : {
7477 14232 : rtx x0 = XEXP (SET_DEST (x), 0);
7478 14232 : if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7479 : break;
7480 14232 : inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7481 14232 : pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7482 : MAX_MODE_INT);
7483 14232 : }
7484 86477562 : else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7485 4557 : && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7486 : {
7487 4557 : inner = XEXP (SET_DEST (x), 0);
7488 4557 : if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7489 : break;
7490 :
7491 4557 : len = INTVAL (XEXP (SET_DEST (x), 1));
7492 4557 : pos = XEXP (SET_DEST (x), 2);
7493 :
7494 : /* A constant position should stay within the width of INNER. */
7495 4557 : if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7496 : break;
7497 :
7498 : if (BITS_BIG_ENDIAN)
7499 : {
7500 : if (CONST_INT_P (pos))
7501 : pos = GEN_INT (inner_len - len - INTVAL (pos));
7502 : else if (GET_CODE (pos) == MINUS
7503 : && CONST_INT_P (XEXP (pos, 1))
7504 : && INTVAL (XEXP (pos, 1)) == inner_len - len)
7505 : /* If position is ADJUST - X, new position is X. */
7506 : pos = XEXP (pos, 0);
7507 : else
7508 : pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7509 : gen_int_mode (inner_len - len,
7510 : GET_MODE (pos)),
7511 : pos);
7512 : }
7513 : }
7514 :
7515 : /* If the destination is a subreg that overwrites the whole of the inner
7516 : register, we can move the subreg to the source. */
7517 86730149 : else if (GET_CODE (SET_DEST (x)) == SUBREG
7518 : /* We need SUBREGs to compute nonzero_bits properly. */
7519 915270 : && nonzero_sign_valid
7520 87299546 : && !read_modify_subreg_p (SET_DEST (x)))
7521 : {
7522 257144 : x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7523 : gen_lowpart
7524 : (GET_MODE (SUBREG_REG (SET_DEST (x))),
7525 : SET_SRC (x)));
7526 257144 : continue;
7527 : }
7528 : else
7529 : break;
7530 :
7531 21085 : while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7532 2296 : inner = SUBREG_REG (inner);
7533 :
7534 : /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7535 18789 : if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7536 : {
7537 : /* Don't do anything for vector or complex integral types. */
7538 : if (! FLOAT_MODE_P (GET_MODE (inner)))
7539 : break;
7540 :
7541 : /* Try to find an integral mode to pun with. */
7542 38 : if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7543 0 : .exists (&compute_mode))
7544 : break;
7545 :
7546 19 : inner = gen_lowpart (compute_mode, inner);
7547 : }
7548 :
7549 : /* Compute a mask of LEN bits, if we can do this on the host machine. */
7550 14033 : if (len >= HOST_BITS_PER_WIDE_INT)
7551 : break;
7552 :
7553 : /* Don't try to compute in too wide unsupported modes. */
7554 14033 : if (!targetm.scalar_mode_supported_p (compute_mode))
7555 : break;
7556 :
7557 : /* gen_lowpart_for_combine returns CLOBBER on failure. */
7558 14033 : rtx lowpart = gen_lowpart (compute_mode, SET_SRC (x));
7559 14033 : if (GET_CODE (lowpart) == CLOBBER)
7560 : break;
7561 :
7562 : /* Now compute the equivalent expression. Make a copy of INNER
7563 : for the SET_DEST in case it is a MEM into which we will substitute;
7564 : we don't want shared RTL in that case. */
7565 11999 : mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7566 : compute_mode);
7567 11999 : cleared = simplify_gen_binary (AND, compute_mode,
7568 : simplify_gen_unary (NOT, compute_mode,
7569 : simplify_gen_binary (ASHIFT,
7570 : compute_mode,
7571 : mask, pos),
7572 : compute_mode),
7573 : inner);
7574 11999 : masked = simplify_gen_binary (ASHIFT, compute_mode,
7575 : simplify_gen_binary (
7576 : AND, compute_mode, lowpart, mask),
7577 : pos);
7578 :
7579 11999 : x = gen_rtx_SET (copy_rtx (inner),
7580 : simplify_gen_binary (IOR, compute_mode,
7581 : cleared, masked));
7582 : }
7583 :
7584 86222651 : return x;
7585 : }
7586 :
7587 : /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7588 : it is an RTX that represents the (variable) starting position; otherwise,
7589 : POS is the (constant) starting bit position. Both are counted from the LSB.
7590 :
7591 : UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7592 :
7593 : IN_DEST is true if this is a reference in the destination of a SET.
7594 : This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7595 : a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7596 : be used.
7597 :
7598 : IN_COMPARE is true if we are in a COMPARE. This means that a
7599 : ZERO_EXTRACT should be built even for bits starting at bit 0.
7600 :
7601 : MODE is the desired mode of the result (if IN_DEST == 0).
7602 :
7603 : The result is an RTX for the extraction or NULL_RTX if the target
7604 : can't handle it. */
7605 :
7606 : static rtx
7607 5219410 : make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7608 : rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7609 : bool in_dest, bool in_compare)
7610 : {
7611 : /* This mode describes the size of the storage area
7612 : to fetch the overall value from. Within that, we
7613 : ignore the POS lowest bits, etc. */
7614 5219410 : machine_mode is_mode = GET_MODE (inner);
7615 5219410 : machine_mode inner_mode;
7616 5219410 : scalar_int_mode wanted_inner_mode;
7617 5219410 : scalar_int_mode wanted_inner_reg_mode = word_mode;
7618 5219410 : scalar_int_mode pos_mode = word_mode;
7619 5219410 : machine_mode extraction_mode = word_mode;
7620 5219410 : rtx new_rtx = 0;
7621 5219410 : rtx orig_pos_rtx = pos_rtx;
7622 5219410 : HOST_WIDE_INT orig_pos;
7623 :
7624 5219410 : if (pos_rtx && CONST_INT_P (pos_rtx))
7625 946917 : pos = INTVAL (pos_rtx), pos_rtx = 0;
7626 :
7627 5219410 : if (GET_CODE (inner) == SUBREG
7628 2670100 : && subreg_lowpart_p (inner)
7629 7885812 : && (paradoxical_subreg_p (inner)
7630 : /* If trying or potentially trying to extract
7631 : bits outside of is_mode, don't look through
7632 : non-paradoxical SUBREGs. See PR82192. */
7633 188581 : || (pos_rtx == NULL_RTX
7634 188557 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7635 : {
7636 : /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7637 : consider just the QI as the memory to extract from.
7638 : The subreg adds or removes high bits; its mode is
7639 : irrelevant to the meaning of this extraction,
7640 : since POS and LEN count from the lsb. */
7641 2666378 : if (MEM_P (SUBREG_REG (inner)))
7642 497940 : is_mode = GET_MODE (SUBREG_REG (inner));
7643 : inner = SUBREG_REG (inner);
7644 : }
7645 2553032 : else if (GET_CODE (inner) == ASHIFT
7646 142079 : && CONST_INT_P (XEXP (inner, 1))
7647 140889 : && pos_rtx == 0 && pos == 0
7648 140865 : && len > UINTVAL (XEXP (inner, 1)))
7649 : {
7650 : /* We're extracting the least significant bits of an rtx
7651 : (ashift X (const_int C)), where LEN > C. Extract the
7652 : least significant (LEN - C) bits of X, giving an rtx
7653 : whose mode is MODE, then shift it left C times. */
7654 140865 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7655 : 0, 0, len - INTVAL (XEXP (inner, 1)),
7656 : unsignedp, in_dest, in_compare);
7657 140865 : if (new_rtx != 0)
7658 139219 : return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7659 : }
7660 2412167 : else if (GET_CODE (inner) == MULT
7661 175069 : && CONST_INT_P (XEXP (inner, 1))
7662 133927 : && pos_rtx == 0 && pos == 0)
7663 : {
7664 : /* We're extracting the least significant bits of an rtx
7665 : (mult X (const_int 2^C)), where LEN > C. Extract the
7666 : least significant (LEN - C) bits of X, giving an rtx
7667 : whose mode is MODE, then multiply it by 2^C. */
7668 113760 : const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7669 113760 : if (len > 1 && IN_RANGE (shift_amt, 1, len - 1))
7670 : {
7671 109165 : new_rtx = make_extraction (mode, XEXP (inner, 0),
7672 : 0, 0, len - shift_amt,
7673 : unsignedp, in_dest, in_compare);
7674 109165 : if (new_rtx)
7675 109165 : return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7676 : }
7677 : }
7678 2298407 : else if (GET_CODE (inner) == TRUNCATE
7679 : /* If trying or potentially trying to extract
7680 : bits outside of is_mode, don't look through
7681 : TRUNCATE. See PR82192. */
7682 0 : && pos_rtx == NULL_RTX
7683 2298407 : && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7684 0 : inner = XEXP (inner, 0);
7685 :
7686 4971026 : inner_mode = GET_MODE (inner);
7687 :
7688 : /* See if this can be done without an extraction. We never can if the
7689 : width of the field is not the same as that of some integer mode. For
7690 : registers, we can only avoid the extraction if the position is at the
7691 : low-order bit and this is either not in the destination or we have the
7692 : appropriate STRICT_LOW_PART operation available.
7693 :
7694 : For MEM, we can avoid an extract if the field starts on an appropriate
7695 : boundary and we can change the mode of the memory reference. */
7696 :
7697 4971026 : scalar_int_mode tmode;
7698 4971026 : if (int_mode_for_size (len, 1).exists (&tmode)
7699 2421105 : && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7700 2098220 : && !MEM_P (inner)
7701 1710578 : && (pos == 0 || REG_P (inner))
7702 1710578 : && (inner_mode == tmode
7703 268255 : || !REG_P (inner)
7704 2328503 : || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7705 0 : || reg_truncated_to_mode (tmode, inner))
7706 1710578 : && (! in_dest
7707 0 : || (REG_P (inner)
7708 0 : && have_insn_for (STRICT_LOW_PART, tmode))))
7709 569436 : || (MEM_P (inner) && pos_rtx == 0
7710 389016 : && (pos
7711 : % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7712 : : BITS_PER_UNIT)) == 0
7713 : /* We can't do this if we are widening INNER_MODE (it
7714 : may not be aligned, for one thing). */
7715 387994 : && !paradoxical_subreg_p (tmode, inner_mode)
7716 387994 : && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7717 387994 : && (inner_mode == tmode
7718 564 : || (! mode_dependent_address_p (XEXP (inner, 0),
7719 564 : MEM_ADDR_SPACE (inner))
7720 564 : && ! MEM_VOLATILE_P (inner))))))
7721 : {
7722 : /* If INNER is a MEM, make a new MEM that encompasses just the desired
7723 : field. If the original and current mode are the same, we need not
7724 : adjust the offset. Otherwise, we do if bytes big endian.
7725 :
7726 : If INNER is not a MEM, get a piece consisting of just the field
7727 : of interest (in this case POS % BITS_PER_WORD must be 0). */
7728 :
7729 2098559 : if (MEM_P (inner))
7730 : {
7731 387981 : poly_int64 offset;
7732 :
7733 : /* POS counts from lsb, but make OFFSET count in memory order. */
7734 387981 : if (BYTES_BIG_ENDIAN)
7735 : offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7736 : - len - pos);
7737 : else
7738 387981 : offset = pos / BITS_PER_UNIT;
7739 :
7740 387981 : new_rtx = adjust_address_nv (inner, tmode, offset);
7741 : }
7742 1710578 : else if (REG_P (inner))
7743 : {
7744 1075218 : if (tmode != inner_mode)
7745 : {
7746 : /* We can't call gen_lowpart in a DEST since we
7747 : always want a SUBREG (see below) and it would sometimes
7748 : return a new hard register. */
7749 229944 : if (pos || in_dest)
7750 : {
7751 3 : poly_uint64 offset
7752 3 : = subreg_offset_from_lsb (tmode, inner_mode, pos);
7753 :
7754 : /* Avoid creating invalid subregs, for example when
7755 : simplifying (x>>32)&255. */
7756 3 : if (!validate_subreg (tmode, inner_mode, inner, offset))
7757 0 : return NULL_RTX;
7758 :
7759 3 : new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7760 3 : }
7761 : else
7762 229941 : new_rtx = gen_lowpart (tmode, inner);
7763 : }
7764 : else
7765 : new_rtx = inner;
7766 : }
7767 : else
7768 1270720 : new_rtx = force_to_mode (inner, tmode,
7769 : len >= HOST_BITS_PER_WIDE_INT
7770 : ? HOST_WIDE_INT_M1U
7771 635360 : : (HOST_WIDE_INT_1U << len) - 1, false);
7772 :
7773 : /* If this extraction is going into the destination of a SET,
7774 : make a STRICT_LOW_PART unless we made a MEM. */
7775 :
7776 2098559 : if (in_dest)
7777 27 : return (MEM_P (new_rtx) ? new_rtx
7778 : : (GET_CODE (new_rtx) != SUBREG
7779 0 : ? gen_rtx_CLOBBER (tmode, const0_rtx)
7780 0 : : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7781 :
7782 2098532 : if (mode == tmode)
7783 : return new_rtx;
7784 :
7785 2098503 : if (CONST_SCALAR_INT_P (new_rtx))
7786 5 : return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7787 5 : mode, new_rtx, tmode);
7788 :
7789 : /* If we know that no extraneous bits are set, and that the high
7790 : bit is not set, convert the extraction to the cheaper of
7791 : sign and zero extension, that are equivalent in these cases. */
7792 2098498 : if (flag_expensive_optimizations
7793 2098498 : && (HWI_COMPUTABLE_MODE_P (tmode)
7794 1945856 : && ((nonzero_bits (new_rtx, tmode)
7795 1945856 : & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7796 : == 0)))
7797 : {
7798 6978 : rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7799 6978 : rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7800 :
7801 : /* Prefer ZERO_EXTENSION, since it gives more information to
7802 : backends. */
7803 6978 : if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7804 6978 : <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7805 : return temp;
7806 0 : return temp1;
7807 : }
7808 :
7809 : /* Otherwise, sign- or zero-extend unless we already are in the
7810 : proper mode. */
7811 :
7812 2091520 : return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7813 2091520 : mode, new_rtx));
7814 : }
7815 :
7816 : /* Unless this is a COMPARE or we have a funny memory reference,
7817 : don't do anything with zero-extending field extracts starting at
7818 : the low-order bit since they are simple AND operations. */
7819 2872467 : if (pos_rtx == 0 && pos == 0 && ! in_dest
7820 1793083 : && ! in_compare && unsignedp)
7821 : return 0;
7822 :
7823 : /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7824 : if the position is not a constant and the length is not 1. In all
7825 : other cases, we would only be going outside our object in cases when
7826 : an original shift would have been undefined. */
7827 1487660 : if (MEM_P (inner)
7828 1487660 : && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7829 2970 : || (pos_rtx != 0 && len != 1)))
7830 : return 0;
7831 :
7832 1607326 : enum extraction_pattern pattern = (in_dest ? EP_insv
7833 1481895 : : unsignedp ? EP_extzv : EP_extv);
7834 :
7835 : /* If INNER is not from memory, we want it to have the mode of a register
7836 : extraction pattern's structure operand, or word_mode if there is no
7837 : such pattern. The same applies to extraction_mode and pos_mode
7838 : and their respective operands.
7839 :
7840 : For memory, assume that the desired extraction_mode and pos_mode
7841 : are the same as for a register operation, since at present we don't
7842 : have named patterns for aligned memory structures. */
7843 1487620 : class extraction_insn insn;
7844 1487620 : unsigned int inner_size;
7845 2975240 : if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7846 1487620 : && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7847 : {
7848 1383512 : wanted_inner_reg_mode = insn.struct_mode.require ();
7849 1383512 : pos_mode = insn.pos_mode;
7850 1383512 : extraction_mode = insn.field_mode;
7851 : }
7852 :
7853 : /* Never narrow an object, since that might not be safe. */
7854 :
7855 1487620 : if (mode != VOIDmode
7856 1487620 : && partial_subreg_p (extraction_mode, mode))
7857 : extraction_mode = mode;
7858 :
7859 : /* Punt if len is too large for extraction_mode. */
7860 1487620 : if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7861 : return NULL_RTX;
7862 :
7863 1487608 : if (!MEM_P (inner))
7864 1309096 : wanted_inner_mode = wanted_inner_reg_mode;
7865 : else
7866 : {
7867 : /* Be careful not to go beyond the extracted object and maintain the
7868 : natural alignment of the memory. */
7869 178512 : wanted_inner_mode = smallest_int_mode_for_size (len).require ();
7870 360134 : while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7871 363244 : > GET_MODE_BITSIZE (wanted_inner_mode))
7872 3110 : wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7873 : }
7874 :
7875 1487608 : orig_pos = pos;
7876 :
7877 1487608 : if (BITS_BIG_ENDIAN)
7878 : {
7879 : /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7880 : BITS_BIG_ENDIAN style. If position is constant, compute new
7881 : position. Otherwise, build subtraction.
7882 : Note that POS is relative to the mode of the original argument.
7883 : If it's a MEM we need to recompute POS relative to that.
7884 : However, if we're extracting from (or inserting into) a register,
7885 : we want to recompute POS relative to wanted_inner_mode. */
7886 : int width;
7887 : if (!MEM_P (inner))
7888 : width = GET_MODE_BITSIZE (wanted_inner_mode);
7889 : else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7890 : return NULL_RTX;
7891 :
7892 : if (pos_rtx == 0)
7893 : pos = width - len - pos;
7894 : else
7895 : pos_rtx
7896 : = gen_rtx_MINUS (GET_MODE (pos_rtx),
7897 : gen_int_mode (width - len, GET_MODE (pos_rtx)),
7898 : pos_rtx);
7899 : /* POS may be less than 0 now, but we check for that below.
7900 : Note that it can only be less than 0 if !MEM_P (inner). */
7901 : }
7902 :
7903 : /* If INNER has a wider mode, and this is a constant extraction, try to
7904 : make it smaller and adjust the byte to point to the byte containing
7905 : the value. */
7906 1487608 : if (wanted_inner_mode != VOIDmode
7907 1487608 : && inner_mode != wanted_inner_mode
7908 226024 : && ! pos_rtx
7909 217579 : && partial_subreg_p (wanted_inner_mode, is_mode)
7910 112230 : && MEM_P (inner)
7911 26513 : && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7912 1514121 : && ! MEM_VOLATILE_P (inner))
7913 : {
7914 24962 : poly_int64 offset = 0;
7915 :
7916 : /* The computations below will be correct if the machine is big
7917 : endian in both bits and bytes or little endian in bits and bytes.
7918 : If it is mixed, we must adjust. */
7919 :
7920 : /* If bytes are big endian and we had a paradoxical SUBREG, we must
7921 : adjust OFFSET to compensate. */
7922 24962 : if (BYTES_BIG_ENDIAN
7923 : && paradoxical_subreg_p (is_mode, inner_mode))
7924 : offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7925 :
7926 : /* We can now move to the desired byte. */
7927 49924 : offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7928 24962 : * GET_MODE_SIZE (wanted_inner_mode);
7929 24962 : pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7930 :
7931 24962 : if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7932 : && is_mode != wanted_inner_mode)
7933 : offset = (GET_MODE_SIZE (is_mode)
7934 : - GET_MODE_SIZE (wanted_inner_mode) - offset);
7935 :
7936 24962 : inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7937 : }
7938 :
7939 : /* If INNER is not memory, get it into the proper mode. If we are changing
7940 : its mode, POS must be a constant and smaller than the size of the new
7941 : mode. */
7942 1462646 : else if (!MEM_P (inner))
7943 : {
7944 : /* On the LHS, don't create paradoxical subregs implicitly truncating
7945 : the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7946 1309096 : if (in_dest
7947 1309096 : && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7948 : wanted_inner_mode))
7949 0 : return NULL_RTX;
7950 :
7951 1309096 : if (GET_MODE (inner) != wanted_inner_mode
7952 1309096 : && (pos_rtx != 0
7953 382132 : || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7954 : return NULL_RTX;
7955 :
7956 1245729 : if (orig_pos < 0)
7957 : return NULL_RTX;
7958 :
7959 2472334 : inner = force_to_mode (inner, wanted_inner_mode,
7960 : pos_rtx
7961 1226605 : || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7962 : ? HOST_WIDE_INT_M1U
7963 1065651 : : (((HOST_WIDE_INT_1U << len) - 1)
7964 1065651 : << orig_pos), false);
7965 : }
7966 :
7967 : /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7968 : have to zero extend. Otherwise, we can just use a SUBREG.
7969 :
7970 : We dealt with constant rtxes earlier, so pos_rtx cannot
7971 : have VOIDmode at this point. */
7972 1424241 : if (pos_rtx != 0
7973 1424241 : && (GET_MODE_SIZE (pos_mode)
7974 1446295 : > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7975 : {
7976 78 : rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7977 : GET_MODE (pos_rtx));
7978 :
7979 : /* If we know that no extraneous bits are set, and that the high
7980 : bit is not set, convert extraction to cheaper one - either
7981 : SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7982 : cases. */
7983 78 : if (flag_expensive_optimizations
7984 78 : && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7985 78 : && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7986 78 : & ~(((unsigned HOST_WIDE_INT)
7987 78 : GET_MODE_MASK (GET_MODE (pos_rtx)))
7988 78 : >> 1))
7989 : == 0)))
7990 : {
7991 56 : rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7992 : GET_MODE (pos_rtx));
7993 :
7994 : /* Prefer ZERO_EXTENSION, since it gives more information to
7995 : backends. */
7996 56 : if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7997 56 : < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7998 1424241 : temp = temp1;
7999 : }
8000 : pos_rtx = temp;
8001 : }
8002 :
8003 : /* Make POS_RTX unless we already have it and it is correct. If we don't
8004 : have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
8005 : be a CONST_INT. */
8006 1424241 : if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
8007 : pos_rtx = orig_pos_rtx;
8008 :
8009 501626 : else if (pos_rtx == 0)
8010 479572 : pos_rtx = GEN_INT (pos);
8011 :
8012 : /* Make the required operation. See if we can use existing rtx. */
8013 1424241 : new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
8014 : extraction_mode, inner, GEN_INT (len), pos_rtx);
8015 1424241 : if (! in_dest)
8016 1418560 : new_rtx = gen_lowpart (mode, new_rtx);
8017 :
8018 : return new_rtx;
8019 : }
8020 :
8021 : /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8022 : can be commuted with any other operations in X. Return X without
8023 : that shift if so. */
8024 :
8025 : static rtx
8026 1611057 : extract_left_shift (scalar_int_mode mode, rtx x, int count)
8027 : {
8028 1611057 : enum rtx_code code = GET_CODE (x);
8029 1611057 : rtx tem;
8030 :
8031 1611057 : switch (code)
8032 : {
8033 265930 : case ASHIFT:
8034 : /* This is the shift itself. If it is wide enough, we will return
8035 : either the value being shifted if the shift count is equal to
8036 : COUNT or a shift for the difference. */
8037 265930 : if (CONST_INT_P (XEXP (x, 1))
8038 260598 : && INTVAL (XEXP (x, 1)) >= count)
8039 259384 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8040 259384 : INTVAL (XEXP (x, 1)) - count);
8041 : break;
8042 :
8043 5368 : case NEG: case NOT:
8044 5368 : if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8045 2565 : return simplify_gen_unary (code, mode, tem, mode);
8046 :
8047 : break;
8048 :
8049 570098 : case PLUS: case IOR: case XOR: case AND:
8050 : /* If we can safely shift this constant and we find the inner shift,
8051 : make a new operation. */
8052 570098 : if (CONST_INT_P (XEXP (x, 1))
8053 302287 : && (UINTVAL (XEXP (x, 1))
8054 302287 : & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8055 714085 : && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8056 : {
8057 6830 : HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8058 6830 : return simplify_gen_binary (code, mode, tem,
8059 6830 : gen_int_mode (val, mode));
8060 : }
8061 : break;
8062 :
8063 : default:
8064 : break;
8065 : }
8066 :
8067 : return 0;
8068 : }
8069 :
8070 : /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8071 : level of the expression and MODE is its mode. IN_CODE is as for
8072 : make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8073 : that should be used when recursing on operands of *X_PTR.
8074 :
8075 : There are two possible actions:
8076 :
8077 : - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8078 : equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8079 :
8080 : - Return a new rtx, which the caller returns directly. */
8081 :
8082 : static rtx
8083 285353499 : make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8084 : enum rtx_code in_code,
8085 : enum rtx_code *next_code_ptr)
8086 : {
8087 285353499 : rtx x = *x_ptr;
8088 285353499 : enum rtx_code next_code = *next_code_ptr;
8089 285353499 : enum rtx_code code = GET_CODE (x);
8090 285353499 : int mode_width = GET_MODE_PRECISION (mode);
8091 285353499 : rtx rhs, lhs;
8092 285353499 : rtx new_rtx = 0;
8093 285353499 : int i;
8094 285353499 : rtx tem;
8095 285353499 : scalar_int_mode inner_mode;
8096 285353499 : bool equality_comparison = false;
8097 :
8098 285353499 : if (in_code == EQ)
8099 : {
8100 9211557 : equality_comparison = true;
8101 9211557 : in_code = COMPARE;
8102 : }
8103 :
8104 : /* Process depending on the code of this operation. If NEW is set
8105 : nonzero, it will be returned. */
8106 :
8107 285353499 : switch (code)
8108 : {
8109 6522661 : case ASHIFT:
8110 : /* Convert shifts by constants into multiplications if inside
8111 : an address. */
8112 6522661 : if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8113 1963387 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8114 1963387 : && INTVAL (XEXP (x, 1)) >= 0)
8115 : {
8116 1963387 : HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8117 1963387 : HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8118 :
8119 1963387 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8120 1963387 : if (GET_CODE (new_rtx) == NEG)
8121 : {
8122 9 : new_rtx = XEXP (new_rtx, 0);
8123 9 : multval = -multval;
8124 : }
8125 1963387 : multval = trunc_int_for_mode (multval, mode);
8126 1963387 : new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8127 : }
8128 : break;
8129 :
8130 56417502 : case PLUS:
8131 56417502 : case MINUS:
8132 56417502 : lhs = make_compound_operation (XEXP (x, 0), next_code);
8133 56417502 : rhs = make_compound_operation (XEXP (x, 1), next_code);
8134 56417502 : if (lhs != XEXP (x, 0) || rhs != XEXP (x, 1))
8135 3229796 : return simplify_gen_binary (code, mode, lhs, rhs);
8136 : return x;
8137 :
8138 7558806 : case AND:
8139 : /* If the second operand is not a constant, we can't do anything
8140 : with it. */
8141 7558806 : if (!CONST_INT_P (XEXP (x, 1)))
8142 : break;
8143 :
8144 : /* If the constant is a power of two minus one and the first operand
8145 : is a logical right shift, make an extraction. */
8146 5976306 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8147 5976306 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8148 : {
8149 653994 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8150 653994 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8151 : i, true, false, in_code == COMPARE);
8152 : }
8153 :
8154 : /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8155 5322312 : else if (GET_CODE (XEXP (x, 0)) == SUBREG
8156 1389992 : && subreg_lowpart_p (XEXP (x, 0))
8157 6666820 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8158 : &inner_mode)
8159 1375089 : && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8160 5354991 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8161 : {
8162 30581 : rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8163 30581 : new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8164 30581 : new_rtx = make_extraction (inner_mode, new_rtx, 0,
8165 : XEXP (inner_x0, 1),
8166 : i, true, false, in_code == COMPARE);
8167 :
8168 : /* If we narrowed the mode when dropping the subreg, then we lose. */
8169 91743 : if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8170 30581 : new_rtx = NULL;
8171 :
8172 : /* If that didn't give anything, see if the AND simplifies on
8173 : its own. */
8174 30581 : if (!new_rtx && i >= 0)
8175 : {
8176 3315 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8177 3315 : new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i,
8178 : true, false, in_code == COMPARE);
8179 : }
8180 : }
8181 : /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8182 5291731 : else if ((GET_CODE (XEXP (x, 0)) == XOR
8183 5291731 : || GET_CODE (XEXP (x, 0)) == IOR)
8184 29257 : && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8185 2579 : && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8186 5291741 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8187 : {
8188 : /* Apply the distributive law, and then try to make extractions. */
8189 10 : new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8190 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8191 : XEXP (x, 1)),
8192 : gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8193 : XEXP (x, 1)));
8194 10 : new_rtx = make_compound_operation (new_rtx, in_code);
8195 : }
8196 :
8197 : /* If we are have (and (rotate X C) M) and C is larger than the number
8198 : of bits in M, this is an extraction. */
8199 :
8200 5291721 : else if (GET_CODE (XEXP (x, 0)) == ROTATE
8201 935 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8202 925 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8203 5291758 : && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8204 : {
8205 0 : new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8206 0 : new_rtx = make_extraction (mode, new_rtx,
8207 0 : (GET_MODE_PRECISION (mode)
8208 0 : - INTVAL (XEXP (XEXP (x, 0), 1))),
8209 : NULL_RTX, i, true, false,
8210 : in_code == COMPARE);
8211 : }
8212 :
8213 : /* On machines without logical shifts, if the operand of the AND is
8214 : a logical shift and our mask turns off all the propagated sign
8215 : bits, we can replace the logical shift with an arithmetic shift. */
8216 5291721 : else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8217 89560 : && !have_insn_for (LSHIFTRT, mode)
8218 0 : && have_insn_for (ASHIFTRT, mode)
8219 0 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8220 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8221 0 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8222 5291721 : && mode_width <= HOST_BITS_PER_WIDE_INT)
8223 : {
8224 0 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8225 :
8226 0 : mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8227 0 : if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8228 0 : SUBST (XEXP (x, 0),
8229 : gen_rtx_ASHIFTRT (mode,
8230 : make_compound_operation (XEXP (XEXP (x,
8231 : 0),
8232 : 0),
8233 : next_code),
8234 : XEXP (XEXP (x, 0), 1)));
8235 : }
8236 :
8237 : /* If the constant is one less than a power of two, this might be
8238 : representable by an extraction even if no shift is present.
8239 : If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8240 : we are in a COMPARE. */
8241 5291721 : else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8242 2735581 : new_rtx = make_extraction (mode,
8243 : make_compound_operation (XEXP (x, 0),
8244 : next_code),
8245 : 0, NULL_RTX, i,
8246 : true, false, in_code == COMPARE);
8247 :
8248 : /* If we are in a comparison and this is an AND with a power of two,
8249 : convert this into the appropriate bit extract. */
8250 2556140 : else if (in_code == COMPARE
8251 477528 : && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8252 2637432 : && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8253 81292 : new_rtx = make_extraction (mode,
8254 : make_compound_operation (XEXP (x, 0),
8255 : next_code),
8256 : i, NULL_RTX, 1, true, false, true);
8257 :
8258 : /* If the one operand is a paradoxical subreg of a register or memory and
8259 : the constant (limited to the smaller mode) has only zero bits where
8260 : the sub expression has known zero bits, this can be expressed as
8261 : a zero_extend. */
8262 2474848 : else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8263 : {
8264 75247 : rtx sub;
8265 :
8266 75247 : sub = XEXP (XEXP (x, 0), 0);
8267 75247 : machine_mode sub_mode = GET_MODE (sub);
8268 75247 : int sub_width;
8269 30031 : if ((REG_P (sub) || MEM_P (sub))
8270 45759 : && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8271 45759 : && sub_width < mode_width
8272 75247 : && (!WORD_REGISTER_OPERATIONS
8273 : || sub_width >= BITS_PER_WORD
8274 : /* On WORD_REGISTER_OPERATIONS targets the bits
8275 : beyond sub_mode aren't considered undefined,
8276 : so optimize only if it is a MEM load when MEM loads
8277 : zero extend, because then the upper bits are all zero. */
8278 : || (MEM_P (sub)
8279 : && load_extend_op (sub_mode) == ZERO_EXTEND)))
8280 : {
8281 22205 : unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8282 22205 : unsigned HOST_WIDE_INT mask;
8283 :
8284 : /* Original AND constant with all the known zero bits set. */
8285 22205 : mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8286 22205 : if ((mask & mode_mask) == mode_mask)
8287 : {
8288 17017 : new_rtx = make_compound_operation (sub, next_code);
8289 17017 : new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8290 : true, false, in_code == COMPARE);
8291 : }
8292 : }
8293 : }
8294 :
8295 : break;
8296 :
8297 1959257 : case LSHIFTRT:
8298 : /* If the sign bit is known to be zero, replace this with an
8299 : arithmetic shift. */
8300 1959257 : if (have_insn_for (ASHIFTRT, mode)
8301 1959257 : && ! have_insn_for (LSHIFTRT, mode)
8302 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
8303 1959257 : && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8304 : {
8305 0 : new_rtx = gen_rtx_ASHIFTRT (mode,
8306 : make_compound_operation (XEXP (x, 0),
8307 : next_code),
8308 : XEXP (x, 1));
8309 0 : break;
8310 : }
8311 :
8312 : /* fall through */
8313 :
8314 4867255 : case ASHIFTRT:
8315 4867255 : lhs = XEXP (x, 0);
8316 4867255 : rhs = XEXP (x, 1);
8317 :
8318 : /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8319 : this is a SIGN_EXTRACT. */
8320 4867255 : if (CONST_INT_P (rhs)
8321 4686748 : && GET_CODE (lhs) == ASHIFT
8322 1147932 : && CONST_INT_P (XEXP (lhs, 1))
8323 1142604 : && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8324 892546 : && INTVAL (XEXP (lhs, 1)) >= 0
8325 892542 : && INTVAL (rhs) < mode_width)
8326 : {
8327 892541 : new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8328 892541 : new_rtx = make_extraction (mode, new_rtx,
8329 892541 : INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8330 892541 : NULL_RTX, mode_width - INTVAL (rhs),
8331 : code == LSHIFTRT, false,
8332 : in_code == COMPARE);
8333 892541 : break;
8334 : }
8335 :
8336 : /* See if we have operations between an ASHIFTRT and an ASHIFT.
8337 : If so, try to merge the shifts into a SIGN_EXTEND. We could
8338 : also do this for some cases of SIGN_EXTRACT, but it doesn't
8339 : seem worth the effort; the case checked for occurs on Alpha. */
8340 :
8341 3974714 : if (!OBJECT_P (lhs)
8342 1547256 : && ! (GET_CODE (lhs) == SUBREG
8343 69032 : && (OBJECT_P (SUBREG_REG (lhs))))
8344 1493021 : && CONST_INT_P (rhs)
8345 1467725 : && INTVAL (rhs) >= 0
8346 1467725 : && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8347 1461703 : && INTVAL (rhs) < mode_width
8348 5436416 : && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8349 259384 : new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8350 : next_code),
8351 259384 : 0, NULL_RTX, mode_width - INTVAL (rhs),
8352 : code == LSHIFTRT, false, in_code == COMPARE);
8353 :
8354 : break;
8355 :
8356 9684801 : case SUBREG:
8357 : /* Call ourselves recursively on the inner expression. If we are
8358 : narrowing the object and it has a different RTL code from
8359 : what it originally did, do this SUBREG as a force_to_mode. */
8360 9684801 : {
8361 9684801 : rtx inner = SUBREG_REG (x), simplified;
8362 9684801 : enum rtx_code subreg_code = in_code;
8363 :
8364 : /* If the SUBREG is masking of a logical right shift,
8365 : make an extraction. */
8366 9684801 : if (GET_CODE (inner) == LSHIFTRT
8367 9695503 : && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8368 601250 : && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8369 296708 : && CONST_INT_P (XEXP (inner, 1))
8370 291315 : && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8371 9976116 : && subreg_lowpart_p (x))
8372 : {
8373 289923 : new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8374 289923 : int width = GET_MODE_PRECISION (inner_mode)
8375 289923 : - INTVAL (XEXP (inner, 1));
8376 289923 : if (width > mode_width)
8377 : width = mode_width;
8378 289923 : new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8379 : width, true, false, in_code == COMPARE);
8380 289923 : break;
8381 : }
8382 :
8383 : /* If in_code is COMPARE, it isn't always safe to pass it through
8384 : to the recursive make_compound_operation call. */
8385 9394878 : if (subreg_code == COMPARE
8386 9394878 : && (!subreg_lowpart_p (x)
8387 240122 : || GET_CODE (inner) == SUBREG
8388 : /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8389 : is (const_int 0), rather than
8390 : (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8391 : Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8392 : for non-equality comparisons against 0 is not equivalent
8393 : to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8394 240122 : || (GET_CODE (inner) == AND
8395 1234 : && CONST_INT_P (XEXP (inner, 1))
8396 175 : && partial_subreg_p (x)
8397 350 : && exact_log2 (UINTVAL (XEXP (inner, 1)))
8398 175 : >= GET_MODE_BITSIZE (mode) - 1)))
8399 : subreg_code = SET;
8400 :
8401 9394878 : tem = make_compound_operation (inner, subreg_code);
8402 :
8403 : /* TEM's code might be CLOBBER if combine_simplify_rtx
8404 : could not transform a subexpression, e.g. a volatile MEM.
8405 : simplify_subreg cannot be called with clobber, so bail out. */
8406 9394878 : if (GET_CODE (tem) == CLOBBER)
8407 : return NULL_RTX;
8408 :
8409 9394859 : simplified
8410 9394859 : = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8411 9394859 : if (simplified)
8412 16643 : tem = simplified;
8413 :
8414 9394859 : if (GET_CODE (tem) != GET_CODE (inner)
8415 22510 : && partial_subreg_p (x)
8416 9414168 : && subreg_lowpart_p (x))
8417 : {
8418 19293 : rtx newer
8419 19293 : = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8420 :
8421 : /* If we have something other than a SUBREG, we might have
8422 : done an expansion, so rerun ourselves. */
8423 19293 : if (GET_CODE (newer) != SUBREG)
8424 17212 : newer = make_compound_operation (newer, in_code);
8425 :
8426 : /* force_to_mode can expand compounds. If it just re-expanded
8427 : the compound, use gen_lowpart to convert to the desired
8428 : mode. */
8429 19293 : if (rtx_equal_p (newer, x)
8430 : /* Likewise if it re-expanded the compound only partially.
8431 : This happens for SUBREG of ZERO_EXTRACT if they extract
8432 : the same number of bits. */
8433 19293 : || (GET_CODE (newer) == SUBREG
8434 2330 : && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8435 2330 : || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8436 140 : && GET_CODE (inner) == AND
8437 60 : && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8438 1373 : return gen_lowpart (GET_MODE (x), tem);
8439 :
8440 : return newer;
8441 : }
8442 :
8443 9375566 : if (simplified)
8444 : return tem;
8445 : }
8446 : break;
8447 :
8448 : default:
8449 : break;
8450 : }
8451 :
8452 10639040 : if (new_rtx)
8453 5480286 : *x_ptr = gen_lowpart (mode, new_rtx);
8454 228916312 : *next_code_ptr = next_code;
8455 228916312 : return NULL_RTX;
8456 : }
8457 :
8458 : /* Look at the expression rooted at X. Look for expressions
8459 : equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8460 : Form these expressions.
8461 :
8462 : Return the new rtx, usually just X.
8463 :
8464 : Also, for machines like the VAX that don't have logical shift insns,
8465 : try to convert logical to arithmetic shift operations in cases where
8466 : they are equivalent. This undoes the canonicalizations to logical
8467 : shifts done elsewhere.
8468 :
8469 : We try, as much as possible, to re-use rtl expressions to save memory.
8470 :
8471 : IN_CODE says what kind of expression we are processing. Normally, it is
8472 : SET. In a memory address it is MEM. When processing the arguments of
8473 : a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8474 : precisely it is an equality comparison against zero. */
8475 :
8476 : rtx
8477 489734540 : make_compound_operation (rtx x, enum rtx_code in_code)
8478 : {
8479 489734540 : enum rtx_code code = GET_CODE (x);
8480 489734540 : const char *fmt;
8481 489734540 : int i, j;
8482 489734540 : enum rtx_code next_code;
8483 489734540 : rtx new_rtx, tem;
8484 :
8485 : /* Select the code to be used in recursive calls. Once we are inside an
8486 : address, we stay there. If we have a comparison, set to COMPARE,
8487 : but once inside, go back to our default of SET. */
8488 :
8489 489734540 : next_code = (code == MEM ? MEM
8490 460804539 : : ((code == COMPARE || COMPARISON_P (x))
8491 481718908 : && XEXP (x, 1) == const0_rtx) ? COMPARE
8492 452546497 : : in_code == COMPARE || in_code == EQ ? SET : in_code);
8493 :
8494 489734540 : scalar_int_mode mode;
8495 489734540 : if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8496 : {
8497 285353499 : rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8498 : &next_code);
8499 285353499 : if (new_rtx)
8500 : return new_rtx;
8501 228916331 : code = GET_CODE (x);
8502 : }
8503 :
8504 : /* Now recursively process each operand of this operation. We need to
8505 : handle ZERO_EXTEND specially so that we don't lose track of the
8506 : inner mode. */
8507 433297372 : if (code == ZERO_EXTEND)
8508 : {
8509 3405815 : new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8510 6811630 : tem = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8511 3405815 : new_rtx, GET_MODE (XEXP (x, 0)));
8512 3405815 : if (tem)
8513 : return tem;
8514 3395528 : SUBST (XEXP (x, 0), new_rtx);
8515 3395528 : return x;
8516 : }
8517 :
8518 429891557 : fmt = GET_RTX_FORMAT (code);
8519 1000086609 : for (i = 0; i < GET_RTX_LENGTH (code); i++)
8520 570195052 : if (fmt[i] == 'e')
8521 : {
8522 218145523 : new_rtx = make_compound_operation (XEXP (x, i), next_code);
8523 218145523 : SUBST (XEXP (x, i), new_rtx);
8524 : }
8525 352049529 : else if (fmt[i] == 'E')
8526 27791235 : for (j = 0; j < XVECLEN (x, i); j++)
8527 : {
8528 20225764 : new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8529 20225764 : SUBST (XVECEXP (x, i, j), new_rtx);
8530 : }
8531 :
8532 429891557 : maybe_swap_commutative_operands (x);
8533 429891557 : return x;
8534 : }
8535 :
8536 : /* Given M see if it is a value that would select a field of bits
8537 : within an item, but not the entire word. Return -1 if not.
8538 : Otherwise, return the starting position of the field, where 0 is the
8539 : low-order bit.
8540 :
8541 : *PLEN is set to the length of the field. */
8542 :
8543 : static int
8544 6799 : get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8545 : {
8546 : /* Get the bit number of the first 1 bit from the right, -1 if none. */
8547 6799 : int pos = m ? ctz_hwi (m) : -1;
8548 6799 : int len = 0;
8549 :
8550 6799 : if (pos >= 0)
8551 : /* Now shift off the low-order zero bits and see if we have a
8552 : power of two minus 1. */
8553 6799 : len = exact_log2 ((m >> pos) + 1);
8554 :
8555 6067 : if (len <= 0)
8556 : pos = -1;
8557 :
8558 6799 : *plen = len;
8559 6799 : return pos;
8560 : }
8561 :
8562 : /* If X refers to a register that equals REG in value, replace these
8563 : references with REG. */
8564 : static rtx
8565 7617 : canon_reg_for_combine (rtx x, rtx reg)
8566 : {
8567 7617 : rtx op0, op1, op2;
8568 7617 : const char *fmt;
8569 7617 : int i;
8570 7617 : bool copied;
8571 :
8572 7617 : enum rtx_code code = GET_CODE (x);
8573 7617 : switch (GET_RTX_CLASS (code))
8574 : {
8575 0 : case RTX_UNARY:
8576 0 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8577 0 : if (op0 != XEXP (x, 0))
8578 0 : return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8579 0 : GET_MODE (reg));
8580 : break;
8581 :
8582 1261 : case RTX_BIN_ARITH:
8583 1261 : case RTX_COMM_ARITH:
8584 1261 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8585 1261 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8586 1261 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8587 0 : return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8588 : break;
8589 :
8590 2 : case RTX_COMPARE:
8591 2 : case RTX_COMM_COMPARE:
8592 2 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8593 2 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8594 2 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8595 0 : return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8596 0 : GET_MODE (op0), op0, op1);
8597 : break;
8598 :
8599 2 : case RTX_TERNARY:
8600 2 : case RTX_BITFIELD_OPS:
8601 2 : op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8602 2 : op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8603 2 : op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8604 2 : if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8605 0 : return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8606 0 : GET_MODE (op0), op0, op1, op2);
8607 : /* FALLTHRU */
8608 :
8609 4789 : case RTX_OBJ:
8610 4789 : if (REG_P (x))
8611 : {
8612 4787 : if (rtx_equal_p (get_last_value (reg), x)
8613 4787 : || rtx_equal_p (reg, get_last_value (x)))
8614 0 : return reg;
8615 : else
8616 : break;
8617 : }
8618 :
8619 : /* fall through */
8620 :
8621 1567 : default:
8622 1567 : fmt = GET_RTX_FORMAT (code);
8623 1567 : copied = false;
8624 3193 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8625 1626 : if (fmt[i] == 'e')
8626 : {
8627 61 : rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8628 61 : if (op != XEXP (x, i))
8629 : {
8630 0 : if (!copied)
8631 : {
8632 0 : copied = true;
8633 0 : x = copy_rtx (x);
8634 : }
8635 0 : XEXP (x, i) = op;
8636 : }
8637 : }
8638 1565 : else if (fmt[i] == 'E')
8639 : {
8640 : int j;
8641 0 : for (j = 0; j < XVECLEN (x, i); j++)
8642 : {
8643 0 : rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8644 0 : if (op != XVECEXP (x, i, j))
8645 : {
8646 0 : if (!copied)
8647 : {
8648 0 : copied = true;
8649 0 : x = copy_rtx (x);
8650 : }
8651 0 : XVECEXP (x, i, j) = op;
8652 : }
8653 : }
8654 : }
8655 :
8656 : break;
8657 : }
8658 :
8659 : return x;
8660 : }
8661 :
8662 : /* Return X converted to MODE. If the value is already truncated to
8663 : MODE we can just return a subreg even though in the general case we
8664 : would need an explicit truncation. */
8665 :
8666 : static rtx
8667 119953078 : gen_lowpart_or_truncate (machine_mode mode, rtx x)
8668 : {
8669 119953078 : if (!CONST_INT_P (x)
8670 114230270 : && partial_subreg_p (mode, GET_MODE (x))
8671 119953078 : && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8672 119953078 : && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8673 : {
8674 : /* Bit-cast X into an integer mode. */
8675 0 : if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8676 0 : x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8677 0 : x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8678 0 : x, GET_MODE (x));
8679 : }
8680 :
8681 119953078 : return gen_lowpart (mode, x);
8682 : }
8683 :
8684 : /* See if X can be simplified knowing that we will only refer to it in
8685 : MODE and will only refer to those bits that are nonzero in MASK.
8686 : If other bits are being computed or if masking operations are done
8687 : that select a superset of the bits in MASK, they can sometimes be
8688 : ignored.
8689 :
8690 : Return a possibly simplified expression, but always convert X to
8691 : MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8692 :
8693 : If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8694 : are all off in X. This is used when X will be complemented, by either
8695 : NOT, NEG, or XOR. */
8696 :
8697 : static rtx
8698 82870011 : force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8699 : bool just_select)
8700 : {
8701 89889645 : enum rtx_code code = GET_CODE (x);
8702 89889645 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8703 89889645 : machine_mode op_mode;
8704 89889645 : unsigned HOST_WIDE_INT nonzero;
8705 :
8706 : /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8707 : code below will do the wrong thing since the mode of such an
8708 : expression is VOIDmode.
8709 :
8710 : Also do nothing if X is a CLOBBER; this can happen if X was
8711 : the return value from a call to gen_lowpart. */
8712 89889645 : if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8713 : return x;
8714 :
8715 : /* We want to perform the operation in its present mode unless we know
8716 : that the operation is valid in MODE, in which case we do the operation
8717 : in MODE. */
8718 147047150 : op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8719 83590397 : && have_insn_for (code, mode))
8720 140827252 : ? mode : GET_MODE (x));
8721 :
8722 : /* It is not valid to do a right-shift in a narrower mode
8723 : than the one it came in with. */
8724 89810295 : if ((code == LSHIFTRT || code == ASHIFTRT)
8725 89810295 : && partial_subreg_p (mode, GET_MODE (x)))
8726 398568 : op_mode = GET_MODE (x);
8727 :
8728 : /* Truncate MASK to fit OP_MODE. */
8729 89810295 : if (op_mode)
8730 83665042 : mask &= GET_MODE_MASK (op_mode);
8731 :
8732 : /* Determine what bits of X are guaranteed to be (non)zero. */
8733 89810295 : nonzero = nonzero_bits (x, mode);
8734 :
8735 : /* If none of the bits in X are needed, return a zero. */
8736 89810295 : if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8737 677533 : x = const0_rtx;
8738 :
8739 : /* If X is a CONST_INT, return a new one. Do this here since the
8740 : test below will fail. */
8741 89810295 : if (CONST_INT_P (x))
8742 : {
8743 6356692 : if (SCALAR_INT_MODE_P (mode))
8744 6356692 : return gen_int_mode (INTVAL (x) & mask, mode);
8745 : else
8746 : {
8747 0 : x = GEN_INT (INTVAL (x) & mask);
8748 0 : return gen_lowpart_common (mode, x);
8749 : }
8750 : }
8751 :
8752 : /* If X is narrower than MODE and we want all the bits in X's mode, just
8753 : get X in the proper mode. */
8754 83453603 : if (paradoxical_subreg_p (mode, GET_MODE (x))
8755 83453603 : && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8756 3453380 : return gen_lowpart (mode, x);
8757 :
8758 : /* We can ignore the effect of a SUBREG if it narrows the mode or
8759 : if the constant masks to zero all the bits the mode doesn't have. */
8760 80000223 : if (GET_CODE (x) == SUBREG
8761 7207945 : && subreg_lowpart_p (x)
8762 87054441 : && (partial_subreg_p (x)
8763 5253458 : || (mask
8764 5253458 : & GET_MODE_MASK (GET_MODE (x))
8765 5253458 : & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8766 7019634 : return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8767 :
8768 72980589 : scalar_int_mode int_mode, xmode;
8769 72980589 : if (is_a <scalar_int_mode> (mode, &int_mode)
8770 72980589 : && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8771 : /* OP_MODE is either MODE or XMODE, so it must be a scalar
8772 : integer too. */
8773 72942322 : return force_int_to_mode (x, int_mode, xmode,
8774 : as_a <scalar_int_mode> (op_mode),
8775 72942322 : mask, just_select);
8776 :
8777 38267 : return gen_lowpart_or_truncate (mode, x);
8778 : }
8779 :
8780 : /* Subroutine of force_to_mode that handles cases in which both X and
8781 : the result are scalar integers. MODE is the mode of the result,
8782 : XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8783 : is preferred for simplified versions of X. The other arguments
8784 : are as for force_to_mode. */
8785 :
8786 : static rtx
8787 72942322 : force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8788 : scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8789 : bool just_select)
8790 : {
8791 72942322 : enum rtx_code code = GET_CODE (x);
8792 72942322 : bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8793 72942322 : unsigned HOST_WIDE_INT fuller_mask;
8794 72942322 : rtx op0, op1, temp;
8795 72942322 : poly_int64 const_op0;
8796 :
8797 : /* When we have an arithmetic operation, or a shift whose count we
8798 : do not know, we need to assume that all bits up to the highest-order
8799 : bit in MASK will be needed. This is how we form such a mask. */
8800 72942322 : if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8801 : fuller_mask = HOST_WIDE_INT_M1U;
8802 : else
8803 78375151 : fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) - 1);
8804 :
8805 72942322 : switch (code)
8806 : {
8807 : case CLOBBER:
8808 : /* If X is a (clobber (const_int)), return it since we know we are
8809 : generating something that won't match. */
8810 : return x;
8811 :
8812 325368 : case SIGN_EXTEND:
8813 325368 : case ZERO_EXTEND:
8814 325368 : case ZERO_EXTRACT:
8815 325368 : case SIGN_EXTRACT:
8816 325368 : x = expand_compound_operation (x);
8817 325368 : if (GET_CODE (x) != code)
8818 193962 : return force_to_mode (x, mode, mask, next_select);
8819 : break;
8820 :
8821 146 : case TRUNCATE:
8822 : /* Similarly for a truncate. */
8823 146 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8824 :
8825 3626044 : case AND:
8826 : /* If this is an AND with a constant, convert it into an AND
8827 : whose constant is the AND of that constant with MASK. If it
8828 : remains an AND of MASK, delete it since it is redundant. */
8829 :
8830 3626044 : if (CONST_INT_P (XEXP (x, 1)))
8831 : {
8832 5786838 : x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8833 2893419 : mask & INTVAL (XEXP (x, 1)));
8834 2893419 : xmode = op_mode;
8835 :
8836 : /* If X is still an AND, see if it is an AND with a mask that
8837 : is just some low-order bits. If so, and it is MASK, we don't
8838 : need it. */
8839 :
8840 2867476 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8841 5760895 : && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8842 37499 : x = XEXP (x, 0);
8843 :
8844 : /* If it remains an AND, try making another AND with the bits
8845 : in the mode mask that aren't in MASK turned on. If the
8846 : constant in the AND is wide enough, this might make a
8847 : cheaper constant. */
8848 :
8849 2830067 : if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8850 2829977 : && GET_MODE_MASK (xmode) != mask
8851 3000367 : && HWI_COMPUTABLE_MODE_P (xmode))
8852 : {
8853 106948 : unsigned HOST_WIDE_INT cval
8854 106948 : = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8855 106948 : rtx y;
8856 :
8857 106948 : y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8858 106948 : gen_int_mode (cval, xmode));
8859 106948 : if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8860 106948 : < set_src_cost (x, xmode, optimize_this_for_speed_p))
8861 72639279 : x = y;
8862 : }
8863 :
8864 : break;
8865 : }
8866 :
8867 732625 : goto binop;
8868 :
8869 10596681 : case PLUS:
8870 : /* In (and (plus FOO C1) M), if M is a mask that just turns off
8871 : low-order bits (as in an alignment operation) and FOO is already
8872 : aligned to that boundary, mask C1 to that boundary as well.
8873 : This may eliminate that PLUS and, later, the AND. */
8874 :
8875 10596681 : {
8876 10596681 : unsigned int width = GET_MODE_PRECISION (mode);
8877 10596681 : unsigned HOST_WIDE_INT smask = mask;
8878 :
8879 : /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8880 : number, sign extend it. */
8881 :
8882 10596681 : if (width < HOST_BITS_PER_WIDE_INT
8883 3259686 : && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8884 2920738 : smask |= HOST_WIDE_INT_M1U << width;
8885 :
8886 10596681 : if (CONST_INT_P (XEXP (x, 1))
8887 3795550 : && pow2p_hwi (- smask)
8888 3254196 : && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8889 13458412 : && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8890 10949 : return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8891 10949 : (INTVAL (XEXP (x, 1)) & smask)),
8892 : mode, smask, next_select);
8893 : }
8894 :
8895 : /* fall through */
8896 :
8897 12683672 : case MULT:
8898 : /* Substituting into the operands of a widening MULT is not likely to
8899 : create RTL matching a machine insn. */
8900 12683672 : if (code == MULT
8901 2097940 : && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8902 2097940 : || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8903 86847 : && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8904 86847 : || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8905 48687 : && REG_P (XEXP (XEXP (x, 0), 0))
8906 41835 : && REG_P (XEXP (XEXP (x, 1), 0)))
8907 34451 : return gen_lowpart_or_truncate (mode, x);
8908 :
8909 : /* For PLUS, MINUS and MULT, we need any bits less significant than the
8910 : most significant bit in MASK since carries from those bits will
8911 : affect the bits we are interested in. */
8912 12649221 : mask = fuller_mask;
8913 12649221 : goto binop;
8914 :
8915 2397266 : case MINUS:
8916 : /* If X is (minus C Y) where C's least set bit is larger than any bit
8917 : in the mask, then we may replace with (neg Y). */
8918 2397266 : if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8919 150616 : && known_alignment (poly_uint64 (const_op0)) > mask)
8920 : {
8921 30 : x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8922 30 : return force_to_mode (x, mode, mask, next_select);
8923 : }
8924 :
8925 : /* Similarly, if C contains every bit in the fuller_mask, then we may
8926 : replace with (not Y). */
8927 2397236 : if (CONST_INT_P (XEXP (x, 0))
8928 150586 : && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8929 : {
8930 328 : x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8931 328 : return force_to_mode (x, mode, mask, next_select);
8932 : }
8933 :
8934 2396908 : mask = fuller_mask;
8935 2396908 : goto binop;
8936 :
8937 1890705 : case IOR:
8938 1890705 : case XOR:
8939 : /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8940 : LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8941 : operation which may be a bitfield extraction. Ensure that the
8942 : constant we form is not wider than the mode of X. */
8943 :
8944 1890705 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8945 59457 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8946 48702 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8947 48702 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8948 48702 : && CONST_INT_P (XEXP (x, 1))
8949 8487 : && ((INTVAL (XEXP (XEXP (x, 0), 1))
8950 16974 : + floor_log2 (INTVAL (XEXP (x, 1))))
8951 8487 : < GET_MODE_PRECISION (xmode))
8952 1890705 : && (UINTVAL (XEXP (x, 1))
8953 4296 : & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8954 : {
8955 8170 : temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8956 4085 : << INTVAL (XEXP (XEXP (x, 0), 1)),
8957 : xmode);
8958 8170 : temp = simplify_gen_binary (GET_CODE (x), xmode,
8959 4085 : XEXP (XEXP (x, 0), 0), temp);
8960 8170 : x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8961 4085 : XEXP (XEXP (x, 0), 1));
8962 4085 : return force_to_mode (x, mode, mask, next_select);
8963 : }
8964 :
8965 17665374 : binop:
8966 : /* For most binary operations, just propagate into the operation and
8967 : change the mode if we have an operation of that mode. */
8968 :
8969 17665374 : op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8970 17665374 : op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8971 :
8972 : /* If we ended up truncating both operands, truncate the result of the
8973 : operation instead. */
8974 17665374 : if (GET_CODE (op0) == TRUNCATE
8975 0 : && GET_CODE (op1) == TRUNCATE)
8976 : {
8977 0 : op0 = XEXP (op0, 0);
8978 0 : op1 = XEXP (op1, 0);
8979 : }
8980 :
8981 17665374 : op0 = gen_lowpart_or_truncate (op_mode, op0);
8982 17665374 : op1 = gen_lowpart_or_truncate (op_mode, op1);
8983 :
8984 17665374 : if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8985 : {
8986 2180476 : x = simplify_gen_binary (code, op_mode, op0, op1);
8987 2180476 : xmode = op_mode;
8988 : }
8989 : break;
8990 :
8991 4231052 : case ASHIFT:
8992 : /* For left shifts, do the same, but just for the first operand.
8993 : However, we cannot do anything with shifts where we cannot
8994 : guarantee that the counts are smaller than the size of the mode
8995 : because such a count will have a different meaning in a
8996 : wider mode. */
8997 :
8998 4024665 : if (! (CONST_INT_P (XEXP (x, 1))
8999 4024669 : && INTVAL (XEXP (x, 1)) >= 0
9000 4024665 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
9001 4233692 : && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
9002 206383 : && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
9003 206383 : < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
9004 : break;
9005 :
9006 : /* If the shift count is a constant and we can do arithmetic in
9007 : the mode of the shift, refine which bits we need. Otherwise, use the
9008 : conservative form of the mask. */
9009 4088640 : if (CONST_INT_P (XEXP (x, 1))
9010 4022029 : && INTVAL (XEXP (x, 1)) >= 0
9011 4022029 : && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9012 8110669 : && HWI_COMPUTABLE_MODE_P (op_mode))
9013 4021279 : mask >>= INTVAL (XEXP (x, 1));
9014 : else
9015 : mask = fuller_mask;
9016 :
9017 4088640 : op0 = gen_lowpart_or_truncate (op_mode,
9018 : force_to_mode (XEXP (x, 0), mode,
9019 : mask, next_select));
9020 :
9021 4088640 : if (op_mode != xmode || op0 != XEXP (x, 0))
9022 : {
9023 969586 : x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9024 969586 : xmode = op_mode;
9025 : }
9026 : break;
9027 :
9028 3092690 : case LSHIFTRT:
9029 : /* Here we can only do something if the shift count is a constant,
9030 : this shift constant is valid for the host, and we can do arithmetic
9031 : in OP_MODE. */
9032 :
9033 3092690 : if (CONST_INT_P (XEXP (x, 1))
9034 2981604 : && INTVAL (XEXP (x, 1)) >= 0
9035 2981603 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9036 6074195 : && HWI_COMPUTABLE_MODE_P (op_mode))
9037 : {
9038 2978119 : rtx inner = XEXP (x, 0);
9039 2978119 : unsigned HOST_WIDE_INT inner_mask;
9040 :
9041 : /* Select the mask of the bits we need for the shift operand. */
9042 2978119 : inner_mask = mask << INTVAL (XEXP (x, 1));
9043 :
9044 : /* We can only change the mode of the shift if we can do arithmetic
9045 : in the mode of the shift and INNER_MASK is no wider than the
9046 : width of X's mode. */
9047 2978119 : if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9048 260711 : op_mode = xmode;
9049 :
9050 2978119 : inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9051 :
9052 2978119 : if (xmode != op_mode || inner != XEXP (x, 0))
9053 : {
9054 799541 : x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9055 799541 : xmode = op_mode;
9056 : }
9057 : }
9058 :
9059 : /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9060 : shift and AND produces only copies of the sign bit (C2 is one less
9061 : than a power of two), we can do this with just a shift. */
9062 :
9063 3092690 : if (GET_CODE (x) == LSHIFTRT
9064 3092633 : && CONST_INT_P (XEXP (x, 1))
9065 : /* The shift puts one of the sign bit copies in the least significant
9066 : bit. */
9067 5963094 : && ((INTVAL (XEXP (x, 1))
9068 2981547 : + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9069 2981547 : >= GET_MODE_PRECISION (xmode))
9070 240995 : && pow2p_hwi (mask + 1)
9071 : /* Number of bits left after the shift must be more than the mask
9072 : needs. */
9073 78461 : && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9074 78461 : <= GET_MODE_PRECISION (xmode))
9075 : /* Must be more sign bit copies than the mask needs. */
9076 3121405 : && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9077 28715 : >= exact_log2 (mask + 1)))
9078 : {
9079 28715 : int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9080 28715 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9081 28715 : gen_int_shift_amount (xmode, nbits));
9082 : }
9083 3092690 : goto shiftrt;
9084 :
9085 2058432 : case ASHIFTRT:
9086 : /* If we are just looking for the sign bit, we don't need this shift at
9087 : all, even if it has a variable count. */
9088 2058432 : if (val_signbit_p (xmode, mask))
9089 1178 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9090 :
9091 : /* If this is a shift by a constant, get a mask that contains those bits
9092 : that are not copies of the sign bit. We then have two cases: If
9093 : MASK only includes those bits, this can be a logical shift, which may
9094 : allow simplifications. If MASK is a single-bit field not within
9095 : those bits, we are requesting a copy of the sign bit and hence can
9096 : shift the sign bit to the appropriate location. */
9097 :
9098 2057254 : if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9099 2011532 : && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9100 : {
9101 2011421 : unsigned HOST_WIDE_INT nonzero;
9102 2011421 : int i;
9103 :
9104 : /* If the considered data is wider than HOST_WIDE_INT, we can't
9105 : represent a mask for all its bits in a single scalar.
9106 : But we only care about the lower bits, so calculate these. */
9107 :
9108 2011421 : if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9109 : {
9110 412 : nonzero = HOST_WIDE_INT_M1U;
9111 :
9112 : /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9113 : is the number of bits a full-width mask would have set.
9114 : We need only shift if these are fewer than nonzero can
9115 : hold. If not, we must keep all bits set in nonzero. */
9116 :
9117 412 : if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9118 : < HOST_BITS_PER_WIDE_INT)
9119 0 : nonzero >>= INTVAL (XEXP (x, 1))
9120 0 : + HOST_BITS_PER_WIDE_INT
9121 0 : - GET_MODE_PRECISION (xmode);
9122 : }
9123 : else
9124 : {
9125 2011009 : nonzero = GET_MODE_MASK (xmode);
9126 2011009 : nonzero >>= INTVAL (XEXP (x, 1));
9127 : }
9128 :
9129 2011421 : if ((mask & ~nonzero) == 0)
9130 : {
9131 49843 : x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9132 : XEXP (x, 0), INTVAL (XEXP (x, 1)));
9133 49843 : if (GET_CODE (x) != ASHIFTRT)
9134 49843 : return force_to_mode (x, mode, mask, next_select);
9135 : }
9136 :
9137 1961578 : else if ((i = exact_log2 (mask)) >= 0)
9138 : {
9139 190 : x = simplify_shift_const
9140 380 : (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9141 190 : GET_MODE_PRECISION (xmode) - 1 - i);
9142 :
9143 190 : if (GET_CODE (x) != ASHIFTRT)
9144 190 : return force_to_mode (x, mode, mask, next_select);
9145 : }
9146 : }
9147 :
9148 : /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9149 : even if the shift count isn't a constant. */
9150 2007221 : if (mask == 1)
9151 3110 : x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9152 :
9153 2004111 : shiftrt:
9154 :
9155 : /* If this is a zero- or sign-extension operation that just affects bits
9156 : we don't care about, remove it. Be sure the call above returned
9157 : something that is still a shift. */
9158 :
9159 5099911 : if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9160 5099854 : && CONST_INT_P (XEXP (x, 1))
9161 4943046 : && INTVAL (XEXP (x, 1)) >= 0
9162 4943045 : && (INTVAL (XEXP (x, 1))
9163 9886090 : <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9164 1782309 : && GET_CODE (XEXP (x, 0)) == ASHIFT
9165 5100916 : && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9166 783 : return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, next_select);
9167 :
9168 : break;
9169 :
9170 36828 : case ROTATE:
9171 36828 : case ROTATERT:
9172 : /* If the shift count is constant and we can do computations
9173 : in the mode of X, compute where the bits we care about are.
9174 : Otherwise, we can't do anything. Don't change the mode of
9175 : the shift or propagate MODE into the shift, though. */
9176 36828 : if (CONST_INT_P (XEXP (x, 1))
9177 26500 : && INTVAL (XEXP (x, 1)) >= 0)
9178 : {
9179 26498 : temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9180 26498 : xmode, gen_int_mode (mask, xmode),
9181 : XEXP (x, 1));
9182 26498 : if (temp && CONST_INT_P (temp))
9183 26498 : x = simplify_gen_binary (code, xmode,
9184 : force_to_mode (XEXP (x, 0), xmode,
9185 26498 : INTVAL (temp), next_select),
9186 : XEXP (x, 1));
9187 : }
9188 : break;
9189 :
9190 160294 : case NEG:
9191 : /* If we just want the low-order bit, the NEG isn't needed since it
9192 : won't change the low-order bit. */
9193 160294 : if (mask == 1)
9194 370 : return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9195 :
9196 : /* We need any bits less significant than the most significant bit in
9197 : MASK since carries from those bits will affect the bits we are
9198 : interested in. */
9199 159924 : mask = fuller_mask;
9200 159924 : goto unop;
9201 :
9202 479706 : case NOT:
9203 : /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9204 : same as the XOR case above. Ensure that the constant we form is not
9205 : wider than the mode of X. */
9206 :
9207 479706 : if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9208 21020 : && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9209 20447 : && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9210 40894 : && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9211 20447 : < GET_MODE_PRECISION (xmode))
9212 486434 : && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9213 : {
9214 6728 : temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9215 6728 : temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9216 13456 : x = simplify_gen_binary (LSHIFTRT, xmode,
9217 6728 : temp, XEXP (XEXP (x, 0), 1));
9218 :
9219 6728 : return force_to_mode (x, mode, mask, next_select);
9220 : }
9221 :
9222 : /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9223 : use the full mask inside the NOT. */
9224 : mask = fuller_mask;
9225 :
9226 632902 : unop:
9227 632902 : op0 = gen_lowpart_or_truncate (op_mode,
9228 : force_to_mode (XEXP (x, 0), mode, mask,
9229 : next_select));
9230 632902 : if (op_mode != xmode || op0 != XEXP (x, 0))
9231 : {
9232 79507 : x = simplify_gen_unary (code, op_mode, op0, op_mode);
9233 79507 : xmode = op_mode;
9234 : }
9235 : break;
9236 :
9237 586898 : case NE:
9238 : /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9239 : in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9240 : which is equal to STORE_FLAG_VALUE. */
9241 586898 : if ((mask & ~STORE_FLAG_VALUE) == 0
9242 2461 : && XEXP (x, 1) == const0_rtx
9243 2440 : && GET_MODE (XEXP (x, 0)) == mode
9244 9 : && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9245 586898 : && (nonzero_bits (XEXP (x, 0), mode)
9246 : == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9247 0 : return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9248 :
9249 : break;
9250 :
9251 1645428 : case IF_THEN_ELSE:
9252 : /* We have no way of knowing if the IF_THEN_ELSE can itself be
9253 : written in a narrower mode. We play it safe and do not do so. */
9254 :
9255 1645428 : op0 = gen_lowpart_or_truncate (xmode,
9256 : force_to_mode (XEXP (x, 1), mode,
9257 : mask, next_select));
9258 1645428 : op1 = gen_lowpart_or_truncate (xmode,
9259 : force_to_mode (XEXP (x, 2), mode,
9260 : mask, next_select));
9261 1645428 : if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9262 265324 : x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9263 265324 : GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9264 : op0, op1);
9265 : break;
9266 :
9267 : default:
9268 : break;
9269 : }
9270 :
9271 : /* Ensure we return a value of the proper mode. */
9272 72639279 : return gen_lowpart_or_truncate (mode, x);
9273 : }
9274 :
9275 : /* Return nonzero if X is an expression that has one of two values depending on
9276 : whether some other value is zero or nonzero. In that case, we return the
9277 : value that is being tested, *PTRUE is set to the value if the rtx being
9278 : returned has a nonzero value, and *PFALSE is set to the other alternative.
9279 :
9280 : If we return zero, we set *PTRUE and *PFALSE to X. */
9281 :
9282 : static rtx
9283 245842285 : if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9284 : {
9285 245842285 : machine_mode mode = GET_MODE (x);
9286 245842285 : enum rtx_code code = GET_CODE (x);
9287 245842285 : rtx cond0, cond1, true0, true1, false0, false1;
9288 245842285 : unsigned HOST_WIDE_INT nz;
9289 245842285 : scalar_int_mode int_mode;
9290 :
9291 : /* If we are comparing a value against zero, we are done. */
9292 245842285 : if ((code == NE || code == EQ)
9293 2713102 : && XEXP (x, 1) == const0_rtx)
9294 : {
9295 1646603 : *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9296 1646603 : *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9297 1646603 : return XEXP (x, 0);
9298 : }
9299 :
9300 : /* If this is a unary operation whose operand has one of two values, apply
9301 : our opcode to compute those values. */
9302 244195682 : else if (UNARY_P (x)
9303 244195682 : && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9304 : {
9305 510672 : *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9306 1021344 : *pfalse = simplify_gen_unary (code, mode, false0,
9307 510672 : GET_MODE (XEXP (x, 0)));
9308 510672 : return cond0;
9309 : }
9310 :
9311 : /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9312 : make can't possibly match and would suppress other optimizations. */
9313 243685010 : else if (code == COMPARE)
9314 : ;
9315 :
9316 : /* If this is a binary operation, see if either side has only one of two
9317 : values. If either one does or if both do and they are conditional on
9318 : the same value, compute the new true and false values. */
9319 239278745 : else if (BINARY_P (x))
9320 : {
9321 88471321 : rtx op0 = XEXP (x, 0);
9322 88471321 : rtx op1 = XEXP (x, 1);
9323 88471321 : cond0 = if_then_else_cond (op0, &true0, &false0);
9324 88471321 : cond1 = if_then_else_cond (op1, &true1, &false1);
9325 :
9326 482584 : if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9327 88898419 : && (REG_P (op0) || REG_P (op1)))
9328 : {
9329 : /* Try to enable a simplification by undoing work done by
9330 : if_then_else_cond if it converted a REG into something more
9331 : complex. */
9332 357613 : if (REG_P (op0))
9333 : {
9334 72675 : cond0 = 0;
9335 72675 : true0 = false0 = op0;
9336 : }
9337 : else
9338 : {
9339 284938 : cond1 = 0;
9340 284938 : true1 = false1 = op1;
9341 : }
9342 : }
9343 :
9344 88471321 : if ((cond0 != 0 || cond1 != 0)
9345 88471321 : && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9346 : {
9347 : /* If if_then_else_cond returned zero, then true/false are the
9348 : same rtl. We must copy one of them to prevent invalid rtl
9349 : sharing. */
9350 4987663 : if (cond0 == 0)
9351 1389069 : true0 = copy_rtx (true0);
9352 3598594 : else if (cond1 == 0)
9353 3543108 : true1 = copy_rtx (true1);
9354 :
9355 4987663 : if (COMPARISON_P (x))
9356 : {
9357 271370 : *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9358 : true0, true1);
9359 271370 : *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9360 : false0, false1);
9361 : }
9362 : else
9363 : {
9364 4716293 : *ptrue = simplify_gen_binary (code, mode, true0, true1);
9365 4716293 : *pfalse = simplify_gen_binary (code, mode, false0, false1);
9366 : }
9367 :
9368 4987663 : return cond0 ? cond0 : cond1;
9369 : }
9370 :
9371 : /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9372 : operands is zero when the other is nonzero, and vice-versa,
9373 : and STORE_FLAG_VALUE is 1 or -1. */
9374 :
9375 83483658 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9376 83483658 : && (code == PLUS || code == IOR || code == XOR || code == MINUS
9377 : || code == UMAX)
9378 34825480 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9379 : {
9380 38137 : rtx op0 = XEXP (XEXP (x, 0), 1);
9381 38137 : rtx op1 = XEXP (XEXP (x, 1), 1);
9382 :
9383 38137 : cond0 = XEXP (XEXP (x, 0), 0);
9384 38137 : cond1 = XEXP (XEXP (x, 1), 0);
9385 :
9386 38137 : if (COMPARISON_P (cond0)
9387 11 : && COMPARISON_P (cond1)
9388 0 : && SCALAR_INT_MODE_P (mode)
9389 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9390 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9391 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9392 0 : || ((swap_condition (GET_CODE (cond0))
9393 0 : == reversed_comparison_code (cond1, NULL))
9394 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9395 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9396 38137 : && ! side_effects_p (x))
9397 : {
9398 0 : *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9399 0 : *pfalse = simplify_gen_binary (MULT, mode,
9400 : (code == MINUS
9401 0 : ? simplify_gen_unary (NEG, mode,
9402 : op1, mode)
9403 : : op1),
9404 : const_true_rtx);
9405 0 : return cond0;
9406 : }
9407 : }
9408 :
9409 : /* Similarly for MULT, AND and UMIN, except that for these the result
9410 : is always zero. */
9411 83483658 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9412 83483658 : && (code == MULT || code == AND || code == UMIN)
9413 12161116 : && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9414 : {
9415 965 : cond0 = XEXP (XEXP (x, 0), 0);
9416 965 : cond1 = XEXP (XEXP (x, 1), 0);
9417 :
9418 965 : if (COMPARISON_P (cond0)
9419 0 : && COMPARISON_P (cond1)
9420 0 : && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9421 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9422 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9423 0 : || ((swap_condition (GET_CODE (cond0))
9424 0 : == reversed_comparison_code (cond1, NULL))
9425 0 : && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9426 0 : && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9427 965 : && ! side_effects_p (x))
9428 : {
9429 0 : *ptrue = *pfalse = const0_rtx;
9430 0 : return cond0;
9431 : }
9432 : }
9433 : }
9434 :
9435 150807424 : else if (code == IF_THEN_ELSE)
9436 : {
9437 : /* If we have IF_THEN_ELSE already, extract the condition and
9438 : canonicalize it if it is NE or EQ. */
9439 753766 : cond0 = XEXP (x, 0);
9440 753766 : *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9441 753766 : if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9442 263338 : return XEXP (cond0, 0);
9443 490428 : else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9444 : {
9445 34130 : *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9446 34130 : return XEXP (cond0, 0);
9447 : }
9448 : else
9449 : return cond0;
9450 : }
9451 :
9452 : /* If X is a SUBREG, we can narrow both the true and false values
9453 : if the inner expression, if there is a condition. */
9454 150053658 : else if (code == SUBREG
9455 150053658 : && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9456 : &false0)) != 0)
9457 : {
9458 1264192 : true0 = simplify_gen_subreg (mode, true0,
9459 632096 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9460 1264192 : false0 = simplify_gen_subreg (mode, false0,
9461 632096 : GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9462 632096 : if (true0 && false0)
9463 : {
9464 632096 : *ptrue = true0;
9465 632096 : *pfalse = false0;
9466 632096 : return cond0;
9467 : }
9468 : }
9469 :
9470 : /* If X is a constant, this isn't special and will cause confusions
9471 : if we treat it as such. Likewise if it is equivalent to a constant. */
9472 149421562 : else if (CONSTANT_P (x)
9473 149421562 : || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9474 : ;
9475 :
9476 : /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9477 : will be least confusing to the rest of the compiler. */
9478 101205494 : else if (mode == BImode)
9479 : {
9480 0 : *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9481 0 : return x;
9482 : }
9483 :
9484 : /* If X is known to be either 0 or -1, those are the true and
9485 : false values when testing X. */
9486 101205494 : else if (x == constm1_rtx || x == const0_rtx
9487 101205494 : || (is_a <scalar_int_mode> (mode, &int_mode)
9488 71961746 : && (num_sign_bit_copies (x, int_mode)
9489 71961746 : == GET_MODE_PRECISION (int_mode))))
9490 : {
9491 1023517 : *ptrue = constm1_rtx, *pfalse = const0_rtx;
9492 1023517 : return x;
9493 : }
9494 :
9495 : /* Likewise for 0 or a single bit. */
9496 100181977 : else if (HWI_COMPUTABLE_MODE_P (mode)
9497 67612912 : && pow2p_hwi (nz = nonzero_bits (x, mode)))
9498 : {
9499 1769642 : *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9500 1769642 : return x;
9501 : }
9502 :
9503 : /* Otherwise fail; show no condition with true and false values the same. */
9504 234518326 : *ptrue = *pfalse = x;
9505 234518326 : return 0;
9506 : }
9507 :
9508 : /* Return the value of expression X given the fact that condition COND
9509 : is known to be true when applied to REG as its first operand and VAL
9510 : as its second. X is known to not be shared and so can be modified in
9511 : place.
9512 :
9513 : We only handle the simplest cases, and specifically those cases that
9514 : arise with IF_THEN_ELSE expressions. */
9515 :
9516 : static rtx
9517 679019 : known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9518 : {
9519 679019 : enum rtx_code code = GET_CODE (x);
9520 679019 : const char *fmt;
9521 679019 : int i, j;
9522 :
9523 679019 : if (side_effects_p (x))
9524 : return x;
9525 :
9526 : /* If either operand of the condition is a floating point value,
9527 : then we have to avoid collapsing an EQ comparison. */
9528 679019 : if (cond == EQ
9529 125780 : && rtx_equal_p (x, reg)
9530 83291 : && ! FLOAT_MODE_P (GET_MODE (x))
9531 762310 : && ! FLOAT_MODE_P (GET_MODE (val)))
9532 : return val;
9533 :
9534 595728 : if (cond == UNEQ && rtx_equal_p (x, reg))
9535 : return val;
9536 :
9537 : /* If X is (abs REG) and we know something about REG's relationship
9538 : with zero, we may be able to simplify this. */
9539 :
9540 595728 : if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9541 3 : switch (cond)
9542 : {
9543 1 : case GE: case GT: case EQ:
9544 1 : return XEXP (x, 0);
9545 2 : case LT: case LE:
9546 4 : return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9547 : XEXP (x, 0),
9548 2 : GET_MODE (XEXP (x, 0)));
9549 : default:
9550 : break;
9551 : }
9552 :
9553 : /* The only other cases we handle are MIN, MAX, and comparisons if the
9554 : operands are the same as REG and VAL. */
9555 :
9556 595725 : else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9557 : {
9558 242915 : if (rtx_equal_p (XEXP (x, 0), val))
9559 : {
9560 2 : std::swap (val, reg);
9561 2 : cond = swap_condition (cond);
9562 : }
9563 :
9564 242915 : if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9565 : {
9566 221245 : if (COMPARISON_P (x))
9567 : {
9568 220992 : if (comparison_dominates_p (cond, code))
9569 1286 : return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9570 :
9571 219706 : code = reversed_comparison_code (x, NULL);
9572 219706 : if (code != UNKNOWN
9573 219706 : && comparison_dominates_p (cond, code))
9574 67 : return CONST0_RTX (GET_MODE (x));
9575 : else
9576 : return x;
9577 : }
9578 253 : else if (code == SMAX || code == SMIN
9579 253 : || code == UMIN || code == UMAX)
9580 : {
9581 45 : int unsignedp = (code == UMIN || code == UMAX);
9582 :
9583 : /* Do not reverse the condition when it is NE or EQ.
9584 : This is because we cannot conclude anything about
9585 : the value of 'SMAX (x, y)' when x is not equal to y,
9586 : but we can when x equals y. */
9587 45 : if ((code == SMAX || code == UMAX)
9588 42 : && ! (cond == EQ || cond == NE))
9589 9 : cond = reverse_condition (cond);
9590 :
9591 12 : switch (cond)
9592 : {
9593 2 : case GE: case GT:
9594 2 : return unsignedp ? x : XEXP (x, 1);
9595 10 : case LE: case LT:
9596 10 : return unsignedp ? x : XEXP (x, 0);
9597 0 : case GEU: case GTU:
9598 0 : return unsignedp ? XEXP (x, 1) : x;
9599 0 : case LEU: case LTU:
9600 0 : return unsignedp ? XEXP (x, 0) : x;
9601 : default:
9602 : break;
9603 : }
9604 : }
9605 : }
9606 : }
9607 352810 : else if (code == SUBREG)
9608 : {
9609 9190 : machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9610 9190 : rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9611 :
9612 9190 : if (SUBREG_REG (x) != r)
9613 : {
9614 : /* We must simplify subreg here, before we lose track of the
9615 : original inner_mode. */
9616 334 : new_rtx = simplify_subreg (GET_MODE (x), r,
9617 167 : inner_mode, SUBREG_BYTE (x));
9618 167 : if (new_rtx)
9619 : return new_rtx;
9620 : else
9621 167 : SUBST (SUBREG_REG (x), r);
9622 : }
9623 :
9624 : return x;
9625 : }
9626 : /* We don't have to handle SIGN_EXTEND here, because even in the
9627 : case of replacing something with a modeless CONST_INT, a
9628 : CONST_INT is already (supposed to be) a valid sign extension for
9629 : its narrower mode, which implies it's already properly
9630 : sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9631 : story is different. */
9632 343620 : else if (code == ZERO_EXTEND)
9633 : {
9634 1324 : machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9635 1324 : rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9636 :
9637 1324 : if (XEXP (x, 0) != r)
9638 : {
9639 : /* We must simplify the zero_extend here, before we lose
9640 : track of the original inner_mode. */
9641 0 : new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9642 : r, inner_mode);
9643 0 : if (new_rtx)
9644 : return new_rtx;
9645 : else
9646 0 : SUBST (XEXP (x, 0), r);
9647 : }
9648 :
9649 : return x;
9650 : }
9651 :
9652 364207 : fmt = GET_RTX_FORMAT (code);
9653 823807 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9654 : {
9655 459600 : if (fmt[i] == 'e')
9656 196075 : SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9657 263525 : else if (fmt[i] == 'E')
9658 15144 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9659 12210 : SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9660 : cond, reg, val));
9661 : }
9662 :
9663 : return x;
9664 : }
9665 :
9666 : /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9667 : assignment as a field assignment. */
9668 :
9669 : static bool
9670 376112 : rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9671 : {
9672 376112 : if (widen_x && GET_MODE (x) != GET_MODE (y))
9673 : {
9674 44810 : if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9675 : return false;
9676 44810 : if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9677 : return false;
9678 44810 : x = adjust_address_nv (x, GET_MODE (y),
9679 : byte_lowpart_offset (GET_MODE (y),
9680 : GET_MODE (x)));
9681 : }
9682 :
9683 376112 : if (x == y || rtx_equal_p (x, y))
9684 : return true;
9685 :
9686 368618 : if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9687 : return false;
9688 :
9689 : /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9690 : Note that all SUBREGs of MEM are paradoxical; otherwise they
9691 : would have been rewritten. */
9692 73977 : if (MEM_P (x) && GET_CODE (y) == SUBREG
9693 6318 : && MEM_P (SUBREG_REG (y))
9694 368616 : && rtx_equal_p (SUBREG_REG (y),
9695 0 : gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9696 : return true;
9697 :
9698 48396 : if (MEM_P (y) && GET_CODE (x) == SUBREG
9699 4033 : && MEM_P (SUBREG_REG (x))
9700 368704 : && rtx_equal_p (SUBREG_REG (x),
9701 88 : gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9702 : return true;
9703 :
9704 : /* We used to see if get_last_value of X and Y were the same but that's
9705 : not correct. In one direction, we'll cause the assignment to have
9706 : the wrong destination and in the case, we'll import a register into this
9707 : insn that might have already have been dead. So fail if none of the
9708 : above cases are true. */
9709 : return false;
9710 : }
9711 :
9712 : /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9713 : Return that assignment if so.
9714 :
9715 : We only handle the most common cases. */
9716 :
9717 : static rtx
9718 48217465 : make_field_assignment (rtx x)
9719 : {
9720 48217465 : rtx dest = SET_DEST (x);
9721 48217465 : rtx src = SET_SRC (x);
9722 48217465 : rtx assign;
9723 48217465 : rtx rhs, lhs;
9724 48217465 : HOST_WIDE_INT c1;
9725 48217465 : HOST_WIDE_INT pos;
9726 48217465 : unsigned HOST_WIDE_INT len;
9727 48217465 : rtx other;
9728 :
9729 : /* All the rules in this function are specific to scalar integers. */
9730 48217465 : scalar_int_mode mode;
9731 48217465 : if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9732 : return x;
9733 :
9734 : /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9735 : a clear of a one-bit field. We will have changed it to
9736 : (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9737 : for a SUBREG. */
9738 :
9739 1280921 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9740 1609 : && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9741 547 : && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9742 22092507 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9743 : {
9744 156 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9745 : 1, true, true, false);
9746 156 : if (assign != 0)
9747 153 : return gen_rtx_SET (assign, const0_rtx);
9748 : return x;
9749 : }
9750 :
9751 1280765 : if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9752 87350 : && subreg_lowpart_p (XEXP (src, 0))
9753 87317 : && partial_subreg_p (XEXP (src, 0))
9754 20132 : && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9755 125 : && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9756 57 : && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9757 22091861 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9758 : {
9759 14 : assign = make_extraction (VOIDmode, dest, 0,
9760 7 : XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9761 : 1, true, true, false);
9762 7 : if (assign != 0)
9763 7 : return gen_rtx_SET (assign, const0_rtx);
9764 : return x;
9765 : }
9766 :
9767 : /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9768 : one-bit field. */
9769 1366808 : if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9770 344495 : && XEXP (XEXP (src, 0), 0) == const1_rtx
9771 22094099 : && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9772 : {
9773 553 : assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9774 : 1, true, true, false);
9775 553 : if (assign != 0)
9776 524 : return gen_rtx_SET (assign, const1_rtx);
9777 : return x;
9778 : }
9779 :
9780 : /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9781 : SRC is an AND with all bits of that field set, then we can discard
9782 : the AND. */
9783 22091244 : if (GET_CODE (dest) == ZERO_EXTRACT
9784 2747 : && CONST_INT_P (XEXP (dest, 1))
9785 2747 : && GET_CODE (src) == AND
9786 834 : && CONST_INT_P (XEXP (src, 1)))
9787 : {
9788 834 : HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9789 834 : unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9790 834 : unsigned HOST_WIDE_INT ze_mask;
9791 :
9792 834 : if (width >= HOST_BITS_PER_WIDE_INT)
9793 : ze_mask = -1;
9794 : else
9795 834 : ze_mask = (HOST_WIDE_INT_1U << width) - 1;
9796 :
9797 : /* Complete overlap. We can remove the source AND. */
9798 834 : if ((and_mask & ze_mask) == ze_mask)
9799 768 : return gen_rtx_SET (dest, XEXP (src, 0));
9800 :
9801 : /* Partial overlap. We can reduce the source AND. */
9802 66 : if ((and_mask & ze_mask) != and_mask)
9803 : {
9804 6 : src = gen_rtx_AND (mode, XEXP (src, 0),
9805 : gen_int_mode (and_mask & ze_mask, mode));
9806 6 : return gen_rtx_SET (dest, src);
9807 : }
9808 : }
9809 :
9810 : /* The other case we handle is assignments into a constant-position
9811 : field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9812 : a mask that has all one bits except for a group of zero bits and
9813 : OTHER is known to have zeros where C1 has ones, this is such an
9814 : assignment. Compute the position and length from C1. Shift OTHER
9815 : to the appropriate position, force it to the required mode, and
9816 : make the extraction. Check for the AND in both operands. */
9817 :
9818 : /* One or more SUBREGs might obscure the constant-position field
9819 : assignment. The first one we are likely to encounter is an outer
9820 : narrowing SUBREG, which we can just strip for the purposes of
9821 : identifying the constant-field assignment. */
9822 22090470 : scalar_int_mode src_mode = mode;
9823 22090470 : if (GET_CODE (src) == SUBREG
9824 212108 : && subreg_lowpart_p (src)
9825 22286594 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9826 22090470 : src = SUBREG_REG (src);
9827 :
9828 22090470 : if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9829 : return x;
9830 :
9831 1552820 : rhs = expand_compound_operation (XEXP (src, 0));
9832 1552820 : lhs = expand_compound_operation (XEXP (src, 1));
9833 :
9834 1552820 : if (GET_CODE (rhs) == AND
9835 562496 : && CONST_INT_P (XEXP (rhs, 1))
9836 1832808 : && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9837 6790 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9838 : /* The second SUBREG that might get in the way is a paradoxical
9839 : SUBREG around the first operand of the AND. We want to
9840 : pretend the operand is as wide as the destination here. We
9841 : do this by adjusting the MEM to wider mode for the sole
9842 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9843 : note this trick only works for MEMs. */
9844 1546030 : else if (GET_CODE (rhs) == AND
9845 555706 : && paradoxical_subreg_p (XEXP (rhs, 0))
9846 46286 : && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9847 24238 : && CONST_INT_P (XEXP (rhs, 1))
9848 1570268 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9849 : dest, true))
9850 0 : c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9851 1546030 : else if (GET_CODE (lhs) == AND
9852 56729 : && CONST_INT_P (XEXP (lhs, 1))
9853 1594438 : && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9854 9 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9855 : /* The second SUBREG that might get in the way is a paradoxical
9856 : SUBREG around the first operand of the AND. We want to
9857 : pretend the operand is as wide as the destination here. We
9858 : do this by adjusting the MEM to wider mode for the sole
9859 : purpose of the call to rtx_equal_for_field_assignment_p. Also
9860 : note this trick only works for MEMs. */
9861 1546021 : else if (GET_CODE (lhs) == AND
9862 56720 : && paradoxical_subreg_p (XEXP (lhs, 0))
9863 29359 : && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9864 20572 : && CONST_INT_P (XEXP (lhs, 1))
9865 1566593 : && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9866 : dest, true))
9867 0 : c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9868 : else
9869 : return x;
9870 :
9871 6799 : pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9872 6799 : if (pos < 0
9873 6067 : || pos + len > GET_MODE_PRECISION (mode)
9874 6067 : || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9875 12854 : || (c1 & nonzero_bits (other, mode)) != 0)
9876 : return x;
9877 :
9878 5036 : assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len,
9879 : true, true, false);
9880 5036 : if (assign == 0)
9881 : return x;
9882 :
9883 : /* The mode to use for the source is the mode of the assignment, or of
9884 : what is inside a possible STRICT_LOW_PART. */
9885 10048 : machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9886 5024 : ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9887 :
9888 : /* Shift OTHER right POS places and make it the source, restricting it
9889 : to the proper length and mode. */
9890 :
9891 5024 : src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9892 : src_mode, other, pos),
9893 : dest);
9894 10048 : src = force_to_mode (src, new_mode,
9895 : len >= HOST_BITS_PER_WIDE_INT
9896 : ? HOST_WIDE_INT_M1U
9897 5024 : : (HOST_WIDE_INT_1U << len) - 1, false);
9898 :
9899 : /* If SRC is masked by an AND that does not make a difference in
9900 : the value being stored, strip it. */
9901 5024 : if (GET_CODE (assign) == ZERO_EXTRACT
9902 4997 : && CONST_INT_P (XEXP (assign, 1))
9903 4997 : && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9904 4997 : && GET_CODE (src) == AND
9905 0 : && CONST_INT_P (XEXP (src, 1))
9906 0 : && UINTVAL (XEXP (src, 1))
9907 0 : == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9908 0 : src = XEXP (src, 0);
9909 :
9910 5024 : return gen_rtx_SET (assign, src);
9911 : }
9912 :
9913 : /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9914 : if so. */
9915 :
9916 : static rtx
9917 53376432 : apply_distributive_law (rtx x)
9918 : {
9919 53376432 : enum rtx_code code = GET_CODE (x);
9920 53376432 : enum rtx_code inner_code;
9921 53376432 : rtx lhs, rhs, other;
9922 53376432 : rtx tem;
9923 :
9924 : /* Distributivity is not true for floating point as it can change the
9925 : value. So we don't do it unless -funsafe-math-optimizations. */
9926 53376432 : if (FLOAT_MODE_P (GET_MODE (x))
9927 3649229 : && ! flag_unsafe_math_optimizations)
9928 : return x;
9929 :
9930 : /* The outer operation can only be one of the following: */
9931 50161706 : if (code != IOR && code != AND && code != XOR
9932 50161706 : && code != PLUS && code != MINUS)
9933 : return x;
9934 :
9935 50147566 : lhs = XEXP (x, 0);
9936 50147566 : rhs = XEXP (x, 1);
9937 :
9938 : /* If either operand is a primitive we can't do anything, so get out
9939 : fast. */
9940 50147566 : if (OBJECT_P (lhs) || OBJECT_P (rhs))
9941 : return x;
9942 :
9943 3602396 : lhs = expand_compound_operation (lhs);
9944 3602396 : rhs = expand_compound_operation (rhs);
9945 3602396 : inner_code = GET_CODE (lhs);
9946 3602396 : if (inner_code != GET_CODE (rhs))
9947 : return x;
9948 :
9949 : /* See if the inner and outer operations distribute. */
9950 1033975 : switch (inner_code)
9951 : {
9952 268602 : case LSHIFTRT:
9953 268602 : case ASHIFTRT:
9954 268602 : case AND:
9955 268602 : case IOR:
9956 : /* These all distribute except over PLUS. */
9957 268602 : if (code == PLUS || code == MINUS)
9958 : return x;
9959 : break;
9960 :
9961 100942 : case MULT:
9962 100942 : if (code != PLUS && code != MINUS)
9963 : return x;
9964 : break;
9965 :
9966 : case ASHIFT:
9967 : /* This is also a multiply, so it distributes over everything. */
9968 : break;
9969 :
9970 : /* This used to handle SUBREG, but this turned out to be counter-
9971 : productive, since (subreg (op ...)) usually is not handled by
9972 : insn patterns, and this "optimization" therefore transformed
9973 : recognizable patterns into unrecognizable ones. Therefore the
9974 : SUBREG case was removed from here.
9975 :
9976 : It is possible that distributing SUBREG over arithmetic operations
9977 : leads to an intermediate result than can then be optimized further,
9978 : e.g. by moving the outer SUBREG to the other side of a SET as done
9979 : in simplify_set. This seems to have been the original intent of
9980 : handling SUBREGs here.
9981 :
9982 : However, with current GCC this does not appear to actually happen,
9983 : at least on major platforms. If some case is found where removing
9984 : the SUBREG case here prevents follow-on optimizations, distributing
9985 : SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9986 :
9987 : default:
9988 : return x;
9989 : }
9990 :
9991 : /* Set LHS and RHS to the inner operands (A and B in the example
9992 : above) and set OTHER to the common operand (C in the example).
9993 : There is only one way to do this unless the inner operation is
9994 : commutative. */
9995 281726 : if (COMMUTATIVE_ARITH_P (lhs)
9996 281726 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9997 2205 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9998 279521 : else if (COMMUTATIVE_ARITH_P (lhs)
9999 279521 : && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
10000 21 : other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
10001 279500 : else if (COMMUTATIVE_ARITH_P (lhs)
10002 279500 : && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
10003 11364 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
10004 268136 : else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
10005 69785 : other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
10006 : else
10007 : return x;
10008 :
10009 : /* Form the new inner operation, seeing if it simplifies first. */
10010 83375 : tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10011 :
10012 : /* There is one exception to the general way of distributing:
10013 : (a | c) ^ (b | c) -> (a ^ b) & ~c */
10014 83375 : if (code == XOR && inner_code == IOR)
10015 : {
10016 1269 : inner_code = AND;
10017 1269 : other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10018 : }
10019 :
10020 : /* We may be able to continuing distributing the result, so call
10021 : ourselves recursively on the inner operation before forming the
10022 : outer operation, which we return. */
10023 83375 : return simplify_gen_binary (inner_code, GET_MODE (x),
10024 83375 : apply_distributive_law (tem), other);
10025 : }
10026 :
10027 : /* See if X is of the form (* (+ A B) C), and if so convert to
10028 : (+ (* A C) (* B C)) and try to simplify.
10029 :
10030 : Most of the time, this results in no change. However, if some of
10031 : the operands are the same or inverses of each other, simplifications
10032 : will result.
10033 :
10034 : For example, (and (ior A B) (not B)) can occur as the result of
10035 : expanding a bit field assignment. When we apply the distributive
10036 : law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10037 : which then simplifies to (and (A (not B))).
10038 :
10039 : Note that no checks happen on the validity of applying the inverse
10040 : distributive law. This is pointless since we can do it in the
10041 : few places where this routine is called.
10042 :
10043 : N is the index of the term that is decomposed (the arithmetic operation,
10044 : i.e. (+ A B) in the first example above). !N is the index of the term that
10045 : is distributed, i.e. of C in the first example above. */
10046 : static rtx
10047 1712556 : distribute_and_simplify_rtx (rtx x, int n)
10048 : {
10049 1712556 : machine_mode mode;
10050 1712556 : enum rtx_code outer_code, inner_code;
10051 1712556 : rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10052 :
10053 : /* Distributivity is not true for floating point as it can change the
10054 : value. So we don't do it unless -funsafe-math-optimizations. */
10055 1712556 : if (FLOAT_MODE_P (GET_MODE (x))
10056 165060 : && ! flag_unsafe_math_optimizations)
10057 : return NULL_RTX;
10058 :
10059 1550992 : decomposed = XEXP (x, n);
10060 1550992 : if (!ARITHMETIC_P (decomposed))
10061 : return NULL_RTX;
10062 :
10063 1550992 : mode = GET_MODE (x);
10064 1550992 : outer_code = GET_CODE (x);
10065 1550992 : distributed = XEXP (x, !n);
10066 :
10067 1550992 : inner_code = GET_CODE (decomposed);
10068 1550992 : inner_op0 = XEXP (decomposed, 0);
10069 1550992 : inner_op1 = XEXP (decomposed, 1);
10070 :
10071 : /* Special case (and (xor B C) (not A)), which is equivalent to
10072 : (xor (ior A B) (ior A C)) */
10073 43378 : if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT
10074 : /* But not when A is a paradoxical subreg since the masking effect
10075 : of the outer AND is lost and the duplicated use can result in
10076 : undefined bits to be exposed when spilling. */
10077 1552257 : && !contains_paradoxical_subreg_p (XEXP (distributed, 0)))
10078 : {
10079 1264 : distributed = XEXP (distributed, 0);
10080 1264 : outer_code = IOR;
10081 : }
10082 :
10083 1550992 : if (n == 0)
10084 : {
10085 : /* Distribute the second term. */
10086 1499921 : new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10087 1499921 : new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10088 : }
10089 : else
10090 : {
10091 : /* Distribute the first term. */
10092 51071 : new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10093 51071 : new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10094 : }
10095 :
10096 1550992 : tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10097 : new_op0, new_op1));
10098 1550992 : if (GET_CODE (tmp) != outer_code
10099 1550992 : && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10100 265703 : < set_src_cost (x, mode, optimize_this_for_speed_p)))
10101 17447 : return tmp;
10102 :
10103 : return NULL_RTX;
10104 : }
10105 :
10106 : /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10107 : in MODE. Return an equivalent form, if different from (and VAROP
10108 : (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10109 :
10110 : static rtx
10111 12436323 : simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10112 : unsigned HOST_WIDE_INT constop)
10113 : {
10114 12436323 : unsigned HOST_WIDE_INT nonzero;
10115 12436323 : unsigned HOST_WIDE_INT orig_constop;
10116 12436323 : rtx orig_varop;
10117 12436323 : int i;
10118 :
10119 12436323 : orig_varop = varop;
10120 12436323 : orig_constop = constop;
10121 12436323 : if (GET_CODE (varop) == CLOBBER)
10122 : return NULL_RTX;
10123 :
10124 : /* Simplify VAROP knowing that we will be only looking at some of the
10125 : bits in it.
10126 :
10127 : Note by passing in CONSTOP, we guarantee that the bits not set in
10128 : CONSTOP are not significant and will never be examined. We must
10129 : ensure that is the case by explicitly masking out those bits
10130 : before returning. */
10131 12436308 : varop = force_to_mode (varop, mode, constop, false);
10132 :
10133 : /* If VAROP is a CLOBBER, we will fail so return it. */
10134 12436308 : if (GET_CODE (varop) == CLOBBER)
10135 : return varop;
10136 :
10137 : /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10138 : to VAROP and return the new constant. */
10139 12436272 : if (CONST_INT_P (varop))
10140 303586 : return gen_int_mode (INTVAL (varop) & constop, mode);
10141 :
10142 : /* See what bits may be nonzero in VAROP. Unlike the general case of
10143 : a call to nonzero_bits, here we don't care about bits outside
10144 : MODE unless WORD_REGISTER_OPERATIONS is true. */
10145 :
10146 12132686 : scalar_int_mode tmode = mode;
10147 12132686 : if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10148 : tmode = word_mode;
10149 12132686 : nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10150 :
10151 : /* Turn off all bits in the constant that are known to already be zero.
10152 : Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10153 : which is tested below. */
10154 :
10155 12132686 : constop &= nonzero;
10156 :
10157 : /* If we don't have any bits left, return zero. */
10158 12132686 : if (constop == 0 && !side_effects_p (varop))
10159 0 : return const0_rtx;
10160 :
10161 : /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10162 : a power of two, we can replace this with an ASHIFT. */
10163 34553 : if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10164 12138438 : && (i = exact_log2 (constop)) >= 0)
10165 163 : return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10166 :
10167 : /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10168 : or XOR, then try to apply the distributive law. This may eliminate
10169 : operations if either branch can be simplified because of the AND.
10170 : It may also make some cases more complex, but those cases probably
10171 : won't match a pattern either with or without this. */
10172 :
10173 12132523 : if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10174 : {
10175 82811 : scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10176 82811 : return
10177 82811 : gen_lowpart
10178 82811 : (mode,
10179 : apply_distributive_law
10180 82811 : (simplify_gen_binary (GET_CODE (varop), varop_mode,
10181 : simplify_and_const_int (NULL_RTX, varop_mode,
10182 : XEXP (varop, 0),
10183 : constop),
10184 : simplify_and_const_int (NULL_RTX, varop_mode,
10185 : XEXP (varop, 1),
10186 : constop))));
10187 : }
10188 :
10189 : /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10190 : the AND and see if one of the operands simplifies to zero. If so, we
10191 : may eliminate it. */
10192 :
10193 12049712 : if (GET_CODE (varop) == PLUS
10194 12049712 : && pow2p_hwi (constop + 1))
10195 : {
10196 444738 : rtx o0, o1;
10197 :
10198 444738 : o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10199 444738 : o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10200 444738 : if (o0 == const0_rtx)
10201 : return o1;
10202 444738 : if (o1 == const0_rtx)
10203 : return o0;
10204 : }
10205 :
10206 : /* Make a SUBREG if necessary. If we can't make it, fail. */
10207 12049637 : varop = gen_lowpart (mode, varop);
10208 12049637 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10209 : return NULL_RTX;
10210 :
10211 : /* If we are only masking insignificant bits, return VAROP. */
10212 12049637 : if (constop == nonzero)
10213 : return varop;
10214 :
10215 11585414 : if (varop == orig_varop && constop == orig_constop)
10216 : return NULL_RTX;
10217 :
10218 : /* Otherwise, return an AND. */
10219 6206244 : return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10220 : }
10221 :
10222 :
10223 : /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10224 : in MODE.
10225 :
10226 : Return an equivalent form, if different from X. Otherwise, return X. If
10227 : X is zero, we are to always construct the equivalent form. */
10228 :
10229 : static rtx
10230 12436323 : simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10231 : unsigned HOST_WIDE_INT constop)
10232 : {
10233 12436323 : rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10234 12436323 : if (tem)
10235 : return tem;
10236 :
10237 5379185 : if (!x)
10238 1331758 : x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10239 1331758 : gen_int_mode (constop, mode));
10240 5379185 : if (GET_MODE (x) != mode)
10241 2 : x = gen_lowpart (mode, x);
10242 : return x;
10243 : }
10244 :
10245 : /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10246 : We don't care about bits outside of those defined in MODE.
10247 : We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10248 :
10249 : For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10250 : a shift, AND, or zero_extract, we can do better. */
10251 :
10252 : static rtx
10253 463936209 : reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10254 : scalar_int_mode mode,
10255 : unsigned HOST_WIDE_INT *nonzero)
10256 : {
10257 463936209 : rtx tem;
10258 463936209 : reg_stat_type *rsp;
10259 :
10260 : /* If X is a register whose nonzero bits value is current, use it.
10261 : Otherwise, if X is a register whose value we can find, use that
10262 : value. Otherwise, use the previously-computed global nonzero bits
10263 : for this register. */
10264 :
10265 463936209 : rsp = ®_stat[REGNO (x)];
10266 463936209 : if (rsp->last_set_value != 0
10267 428303925 : && (rsp->last_set_mode == mode
10268 1278 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10269 0 : && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10270 0 : && GET_MODE_CLASS (mode) == MODE_INT))
10271 892238856 : && ((rsp->last_set_label >= label_tick_ebb_start
10272 325548336 : && rsp->last_set_label < label_tick)
10273 405352066 : || (rsp->last_set_label == label_tick
10274 302597755 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10275 132342674 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10276 132289348 : && REGNO (x) < reg_n_sets_max
10277 132289218 : && REG_N_SETS (REGNO (x)) == 1
10278 153187464 : && !REGNO_REG_SET_P
10279 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10280 : REGNO (x)))))
10281 : {
10282 : /* Note that, even if the precision of last_set_mode is lower than that
10283 : of mode, record_value_for_reg invoked nonzero_bits on the register
10284 : with nonzero_bits_mode (because last_set_mode is necessarily integral
10285 : and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10286 : are all valid, hence in mode too since nonzero_bits_mode is defined
10287 : to the largest HWI_COMPUTABLE_MODE_P mode. */
10288 372454754 : *nonzero &= rsp->last_set_nonzero_bits;
10289 372454754 : return NULL;
10290 : }
10291 :
10292 91481455 : tem = get_last_value (x);
10293 91481455 : if (tem)
10294 : {
10295 : if (SHORT_IMMEDIATES_SIGN_EXTEND)
10296 : tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10297 :
10298 : return tem;
10299 : }
10300 :
10301 91481449 : if (nonzero_sign_valid && rsp->nonzero_bits)
10302 : {
10303 57572822 : unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10304 :
10305 57572822 : if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10306 : /* We don't know anything about the upper bits. */
10307 0 : mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10308 :
10309 57572822 : *nonzero &= mask;
10310 : }
10311 :
10312 : return NULL;
10313 : }
10314 :
10315 : /* Given a reg X of mode XMODE, return the number of bits at the high-order
10316 : end of X that are known to be equal to the sign bit. X will be used
10317 : in mode MODE; the returned value will always be between 1 and the
10318 : number of bits in MODE. */
10319 :
10320 : static rtx
10321 134975605 : reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10322 : scalar_int_mode mode,
10323 : unsigned int *result)
10324 : {
10325 134975605 : rtx tem;
10326 134975605 : reg_stat_type *rsp;
10327 :
10328 134975605 : rsp = ®_stat[REGNO (x)];
10329 134975605 : if (rsp->last_set_value != 0
10330 122583225 : && rsp->last_set_mode == mode
10331 257558661 : && ((rsp->last_set_label >= label_tick_ebb_start
10332 93124615 : && rsp->last_set_label < label_tick)
10333 116470003 : || (rsp->last_set_label == label_tick
10334 87011562 : && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10335 37596342 : || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10336 37586403 : && REGNO (x) < reg_n_sets_max
10337 37586317 : && REG_N_SETS (REGNO (x)) == 1
10338 43556208 : && !REGNO_REG_SET_P
10339 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10340 : REGNO (x)))))
10341 : {
10342 106739550 : *result = rsp->last_set_sign_bit_copies;
10343 106739550 : return NULL;
10344 : }
10345 :
10346 28236055 : tem = get_last_value (x);
10347 28236055 : if (tem != 0)
10348 : return tem;
10349 :
10350 18701624 : if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10351 42798869 : && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10352 14562819 : *result = rsp->sign_bit_copies;
10353 :
10354 : return NULL;
10355 : }
10356 :
10357 : /* Return the number of "extended" bits there are in X, when interpreted
10358 : as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10359 : unsigned quantities, this is the number of high-order zero bits.
10360 : For signed quantities, this is the number of copies of the sign bit
10361 : minus 1. In both case, this function returns the number of "spare"
10362 : bits. For example, if two quantities for which this function returns
10363 : at least 1 are added, the addition is known not to overflow.
10364 :
10365 : This function will always return 0 unless called during combine, which
10366 : implies that it must be called from a define_split. */
10367 :
10368 : unsigned int
10369 0 : extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10370 : {
10371 0 : if (nonzero_sign_valid == 0)
10372 : return 0;
10373 :
10374 0 : scalar_int_mode int_mode;
10375 0 : return (unsignedp
10376 0 : ? (is_a <scalar_int_mode> (mode, &int_mode)
10377 0 : && HWI_COMPUTABLE_MODE_P (int_mode)
10378 0 : ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10379 0 : - floor_log2 (nonzero_bits (x, int_mode)))
10380 : : 0)
10381 0 : : num_sign_bit_copies (x, mode) - 1);
10382 : }
10383 :
10384 : /* This function is called from `simplify_shift_const' to merge two
10385 : outer operations. Specifically, we have already found that we need
10386 : to perform operation *POP0 with constant *PCONST0 at the outermost
10387 : position. We would now like to also perform OP1 with constant CONST1
10388 : (with *POP0 being done last).
10389 :
10390 : Return true if we can do the operation and update *POP0 and *PCONST0 with
10391 : the resulting operation. *PCOMP_P is set to true if we would need to
10392 : complement the innermost operand, otherwise it is unchanged.
10393 :
10394 : MODE is the mode in which the operation will be done. No bits outside
10395 : the width of this mode matter. It is assumed that the width of this mode
10396 : is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10397 :
10398 : If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10399 : IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10400 : result is simply *PCONST0.
10401 :
10402 : If the resulting operation cannot be expressed as one operation, we
10403 : return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10404 :
10405 : static bool
10406 3754544 : merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10407 : enum rtx_code op1, HOST_WIDE_INT const1,
10408 : machine_mode mode, bool *pcomp_p)
10409 : {
10410 3754544 : enum rtx_code op0 = *pop0;
10411 3754544 : HOST_WIDE_INT const0 = *pconst0;
10412 :
10413 3754544 : const0 &= GET_MODE_MASK (mode);
10414 3754544 : const1 &= GET_MODE_MASK (mode);
10415 :
10416 : /* If OP0 is an AND, clear unimportant bits in CONST1. */
10417 3754544 : if (op0 == AND)
10418 24666 : const1 &= const0;
10419 :
10420 : /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10421 : if OP0 is SET. */
10422 :
10423 3754544 : if (op1 == UNKNOWN || op0 == SET)
10424 : return true;
10425 :
10426 3754544 : else if (op0 == UNKNOWN)
10427 : op0 = op1, const0 = const1;
10428 :
10429 76625 : else if (op0 == op1)
10430 : {
10431 24379 : switch (op0)
10432 : {
10433 24379 : case AND:
10434 24379 : const0 &= const1;
10435 24379 : break;
10436 0 : case IOR:
10437 0 : const0 |= const1;
10438 0 : break;
10439 0 : case XOR:
10440 0 : const0 ^= const1;
10441 0 : break;
10442 0 : case PLUS:
10443 0 : const0 += const1;
10444 0 : break;
10445 : case NEG:
10446 3726547 : op0 = UNKNOWN;
10447 : break;
10448 : default:
10449 : break;
10450 : }
10451 : }
10452 :
10453 : /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10454 52246 : else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10455 : return false;
10456 :
10457 : /* If the two constants aren't the same, we can't do anything. The
10458 : remaining six cases can all be done. */
10459 25391 : else if (const0 != const1)
10460 : return false;
10461 :
10462 : else
10463 24249 : switch (op0)
10464 : {
10465 8 : case IOR:
10466 8 : if (op1 == AND)
10467 : /* (a & b) | b == b */
10468 0 : op0 = SET;
10469 : else /* op1 == XOR */
10470 : /* (a ^ b) | b == a | b */
10471 : {;}
10472 : break;
10473 :
10474 23958 : case XOR:
10475 23958 : if (op1 == AND)
10476 : /* (a & b) ^ b == (~a) & b */
10477 23958 : op0 = AND, *pcomp_p = true;
10478 : else /* op1 == IOR */
10479 : /* (a | b) ^ b == a & ~b */
10480 0 : op0 = AND, const0 = ~const0;
10481 : break;
10482 :
10483 283 : case AND:
10484 283 : if (op1 == IOR)
10485 : /* (a | b) & b == b */
10486 : op0 = SET;
10487 : else /* op1 == XOR */
10488 : /* (a ^ b) & b) == (~a) & b */
10489 283 : *pcomp_p = true;
10490 : break;
10491 : default:
10492 : break;
10493 : }
10494 :
10495 : /* Check for NO-OP cases. */
10496 3726547 : const0 &= GET_MODE_MASK (mode);
10497 3726547 : if (const0 == 0
10498 19553 : && (op0 == IOR || op0 == XOR || op0 == PLUS))
10499 : op0 = UNKNOWN;
10500 3725099 : else if (const0 == 0 && op0 == AND)
10501 : op0 = SET;
10502 3725099 : else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10503 24997 : && op0 == AND)
10504 3726547 : op0 = UNKNOWN;
10505 :
10506 3726547 : *pop0 = op0;
10507 :
10508 : /* ??? Slightly redundant with the above mask, but not entirely.
10509 : Moving this above means we'd have to sign-extend the mode mask
10510 : for the final test. */
10511 3726547 : if (op0 != UNKNOWN && op0 != NEG)
10512 3690490 : *pconst0 = trunc_int_for_mode (const0, mode);
10513 :
10514 : return true;
10515 : }
10516 :
10517 : /* A helper to simplify_shift_const_1 to determine the mode we can perform
10518 : the shift in. The original shift operation CODE is performed on OP in
10519 : ORIG_MODE. Return the wider mode MODE if we can perform the operation
10520 : in that mode. Return ORIG_MODE otherwise. We can also assume that the
10521 : result of the shift is subject to operation OUTER_CODE with operand
10522 : OUTER_CONST. */
10523 :
10524 : static scalar_int_mode
10525 407014 : try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10526 : scalar_int_mode orig_mode, scalar_int_mode mode,
10527 : enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10528 : {
10529 407014 : gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10530 :
10531 : /* In general we can't perform in wider mode for right shift and rotate. */
10532 407014 : switch (code)
10533 : {
10534 30317 : case ASHIFTRT:
10535 : /* We can still widen if the bits brought in from the left are identical
10536 : to the sign bit of ORIG_MODE. */
10537 30317 : if (num_sign_bit_copies (op, mode)
10538 30317 : > (unsigned) (GET_MODE_PRECISION (mode)
10539 30317 : - GET_MODE_PRECISION (orig_mode)))
10540 348 : return mode;
10541 29969 : return orig_mode;
10542 :
10543 73949 : case LSHIFTRT:
10544 : /* Similarly here but with zero bits. */
10545 73949 : if (HWI_COMPUTABLE_MODE_P (mode)
10546 73949 : && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10547 6423 : return mode;
10548 :
10549 : /* We can also widen if the bits brought in will be masked off. This
10550 : operation is performed in ORIG_MODE. */
10551 67526 : if (outer_code == AND)
10552 : {
10553 26952 : int care_bits = low_bitmask_len (orig_mode, outer_const);
10554 :
10555 26952 : if (care_bits >= 0
10556 26952 : && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10557 26934 : return mode;
10558 : }
10559 : /* fall through */
10560 :
10561 41078 : case ROTATE:
10562 41078 : return orig_mode;
10563 :
10564 0 : case ROTATERT:
10565 0 : gcc_unreachable ();
10566 :
10567 302262 : default:
10568 302262 : return mode;
10569 : }
10570 : }
10571 :
10572 : /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10573 : of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10574 : if we cannot simplify it. Otherwise, return a simplified value.
10575 :
10576 : The shift is normally computed in the widest mode we find in VAROP, as
10577 : long as it isn't a different number of words than RESULT_MODE. Exceptions
10578 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
10579 :
10580 : static rtx
10581 24196018 : simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10582 : rtx varop, int orig_count)
10583 : {
10584 24196018 : enum rtx_code orig_code = code;
10585 24196018 : rtx orig_varop = varop;
10586 24196018 : int count, log2;
10587 24196018 : machine_mode mode = result_mode;
10588 24196018 : machine_mode shift_mode;
10589 24196018 : scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10590 : /* We form (outer_op (code varop count) (outer_const)). */
10591 24196018 : enum rtx_code outer_op = UNKNOWN;
10592 24196018 : HOST_WIDE_INT outer_const = 0;
10593 24196018 : bool complement_p = false;
10594 24196018 : rtx new_rtx, x;
10595 :
10596 : /* Make sure and truncate the "natural" shift on the way in. We don't
10597 : want to do this inside the loop as it makes it more difficult to
10598 : combine shifts. */
10599 24196018 : if (SHIFT_COUNT_TRUNCATED)
10600 : orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10601 :
10602 : /* If we were given an invalid count, don't do anything except exactly
10603 : what was requested. */
10604 :
10605 48391976 : if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10606 : return NULL_RTX;
10607 :
10608 : count = orig_count;
10609 :
10610 : /* Unless one of the branches of the `if' in this loop does a `continue',
10611 : we will `break' the loop after the `if'. */
10612 :
10613 28292486 : while (count != 0)
10614 : {
10615 : /* If we have an operand of (clobber (const_int 0)), fail. */
10616 24479661 : if (GET_CODE (varop) == CLOBBER)
10617 24196018 : return NULL_RTX;
10618 :
10619 : /* Convert ROTATERT to ROTATE. */
10620 24479661 : if (code == ROTATERT)
10621 : {
10622 11602 : unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10623 11602 : code = ROTATE;
10624 11602 : count = bitsize - count;
10625 : }
10626 :
10627 24479661 : shift_mode = result_mode;
10628 24479661 : if (shift_mode != mode)
10629 : {
10630 : /* We only change the modes of scalar shifts. */
10631 209397 : int_mode = as_a <scalar_int_mode> (mode);
10632 209397 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10633 209397 : shift_mode = try_widen_shift_mode (code, varop, count,
10634 : int_result_mode, int_mode,
10635 : outer_op, outer_const);
10636 : }
10637 :
10638 24479661 : scalar_int_mode shift_unit_mode;
10639 48959322 : if (!is_a <scalar_int_mode> (GET_MODE_INNER (shift_mode),
10640 : &shift_unit_mode))
10641 : return NULL_RTX;
10642 :
10643 : /* Handle cases where the count is greater than the size of the mode
10644 : minus 1. For ASHIFT, use the size minus one as the count (this can
10645 : occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10646 : take the count modulo the size. For other shifts, the result is
10647 : zero.
10648 :
10649 : Since these shifts are being produced by the compiler by combining
10650 : multiple operations, each of which are defined, we know what the
10651 : result is supposed to be. */
10652 :
10653 24479661 : if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10654 : {
10655 12416 : if (code == ASHIFTRT)
10656 12410 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10657 6 : else if (code == ROTATE || code == ROTATERT)
10658 6 : count %= GET_MODE_PRECISION (shift_unit_mode);
10659 : else
10660 : {
10661 : /* We can't simply return zero because there may be an
10662 : outer op. */
10663 0 : varop = const0_rtx;
10664 0 : count = 0;
10665 0 : break;
10666 : }
10667 : }
10668 :
10669 : /* If we discovered we had to complement VAROP, leave. Making a NOT
10670 : here would cause an infinite loop. */
10671 24479661 : if (complement_p)
10672 : break;
10673 :
10674 24466454 : if (shift_mode == shift_unit_mode)
10675 : {
10676 : /* An arithmetic right shift of a quantity known to be -1 or 0
10677 : is a no-op. */
10678 23740088 : if (code == ASHIFTRT
10679 23740088 : && (num_sign_bit_copies (varop, shift_unit_mode)
10680 4475485 : == GET_MODE_PRECISION (shift_unit_mode)))
10681 : {
10682 : count = 0;
10683 : break;
10684 : }
10685 :
10686 : /* If we are doing an arithmetic right shift and discarding all but
10687 : the sign bit copies, this is equivalent to doing a shift by the
10688 : bitsize minus one. Convert it into that shift because it will
10689 : often allow other simplifications. */
10690 :
10691 23740016 : if (code == ASHIFTRT
10692 23740016 : && (count + num_sign_bit_copies (varop, shift_unit_mode)
10693 4475413 : >= GET_MODE_PRECISION (shift_unit_mode)))
10694 338707 : count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10695 :
10696 : /* We simplify the tests below and elsewhere by converting
10697 : ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10698 : `make_compound_operation' will convert it to an ASHIFTRT for
10699 : those machines (such as VAX) that don't have an LSHIFTRT. */
10700 23740016 : if (code == ASHIFTRT
10701 4475413 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10702 28191546 : && val_signbit_known_clear_p (shift_unit_mode,
10703 : nonzero_bits (varop,
10704 : shift_unit_mode)))
10705 : code = LSHIFTRT;
10706 :
10707 23710819 : if (((code == LSHIFTRT
10708 5939118 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10709 5917083 : && !(nonzero_bits (varop, shift_unit_mode) >> count))
10710 23738058 : || (code == ASHIFT
10711 13325868 : && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10712 12851475 : && !((nonzero_bits (varop, shift_unit_mode) << count)
10713 12851475 : & GET_MODE_MASK (shift_unit_mode))))
10714 23714906 : && !side_effects_p (varop))
10715 4087 : varop = const0_rtx;
10716 : }
10717 :
10718 24466382 : switch (GET_CODE (varop))
10719 : {
10720 513152 : case SIGN_EXTEND:
10721 513152 : case ZERO_EXTEND:
10722 513152 : case SIGN_EXTRACT:
10723 513152 : case ZERO_EXTRACT:
10724 513152 : new_rtx = expand_compound_operation (varop);
10725 513152 : if (new_rtx != varop)
10726 : {
10727 68466 : varop = new_rtx;
10728 4096740 : continue;
10729 : }
10730 : break;
10731 :
10732 337186 : case MEM:
10733 : /* The following rules apply only to scalars. */
10734 337186 : if (shift_mode != shift_unit_mode)
10735 : break;
10736 324090 : int_mode = as_a <scalar_int_mode> (mode);
10737 :
10738 : /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10739 : minus the width of a smaller mode, we can do this with a
10740 : SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10741 327691 : if ((code == ASHIFTRT || code == LSHIFTRT)
10742 123813 : && ! mode_dependent_address_p (XEXP (varop, 0),
10743 123813 : MEM_ADDR_SPACE (varop))
10744 123813 : && ! MEM_VOLATILE_P (varop)
10745 446384 : && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10746 320489 : .exists (&tmode)))
10747 : {
10748 3601 : new_rtx = adjust_address_nv (varop, tmode,
10749 : BYTES_BIG_ENDIAN ? 0
10750 : : count / BITS_PER_UNIT);
10751 :
10752 3601 : varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10753 : : ZERO_EXTEND, int_mode, new_rtx);
10754 3601 : count = 0;
10755 3601 : continue;
10756 : }
10757 : break;
10758 :
10759 5020807 : case SUBREG:
10760 : /* The following rules apply only to scalars. */
10761 5020807 : if (shift_mode != shift_unit_mode)
10762 : break;
10763 4573652 : int_mode = as_a <scalar_int_mode> (mode);
10764 4573652 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10765 :
10766 : /* If VAROP is a SUBREG, strip it as long as the inner operand has
10767 : the same number of words as what we've seen so far. Then store
10768 : the widest mode in MODE. */
10769 4573652 : if (subreg_lowpart_p (varop)
10770 28727702 : && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10771 9063912 : && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10772 229700 : && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10773 211307 : == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10774 4771835 : && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10775 : {
10776 198183 : varop = SUBREG_REG (varop);
10777 594549 : if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10778 198183 : mode = inner_mode;
10779 198183 : continue;
10780 : }
10781 : break;
10782 :
10783 413836 : case MULT:
10784 : /* Some machines use MULT instead of ASHIFT because MULT
10785 : is cheaper. But it is still better on those machines to
10786 : merge two shifts into one. */
10787 413836 : if (CONST_INT_P (XEXP (varop, 1))
10788 413836 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10789 : {
10790 0 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10791 0 : varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10792 : XEXP (varop, 0), log2_rtx);
10793 0 : continue;
10794 0 : }
10795 : break;
10796 :
10797 8803 : case UDIV:
10798 : /* Similar, for when divides are cheaper. */
10799 8803 : if (CONST_INT_P (XEXP (varop, 1))
10800 8803 : && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10801 : {
10802 9 : rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10803 9 : varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10804 : XEXP (varop, 0), log2_rtx);
10805 9 : continue;
10806 9 : }
10807 : break;
10808 :
10809 381976 : case ASHIFTRT:
10810 : /* If we are extracting just the sign bit of an arithmetic
10811 : right shift, that shift is not needed. However, the sign
10812 : bit of a wider mode may be different from what would be
10813 : interpreted as the sign bit in a narrower mode, so, if
10814 : the result is narrower, don't discard the shift. */
10815 383899 : if (code == LSHIFTRT
10816 14569 : && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10817 381976 : && (GET_MODE_UNIT_BITSIZE (result_mode)
10818 3872 : >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10819 : {
10820 1923 : varop = XEXP (varop, 0);
10821 1923 : continue;
10822 : }
10823 :
10824 : /* fall through */
10825 :
10826 5988135 : case LSHIFTRT:
10827 5988135 : case ASHIFT:
10828 5988135 : case ROTATE:
10829 : /* The following rules apply only to scalars. */
10830 5988135 : if (shift_mode != shift_unit_mode)
10831 : break;
10832 5972294 : int_mode = as_a <scalar_int_mode> (mode);
10833 5972294 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10834 5972294 : int_result_mode = as_a <scalar_int_mode> (result_mode);
10835 :
10836 : /* Here we have two nested shifts. The result is usually the
10837 : AND of a new shift with a mask. We compute the result below. */
10838 5972294 : if (CONST_INT_P (XEXP (varop, 1))
10839 5952128 : && INTVAL (XEXP (varop, 1)) >= 0
10840 5952125 : && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10841 5952125 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
10842 11893686 : && HWI_COMPUTABLE_MODE_P (int_mode))
10843 : {
10844 5921392 : enum rtx_code first_code = GET_CODE (varop);
10845 5921392 : unsigned int first_count = INTVAL (XEXP (varop, 1));
10846 5921392 : unsigned HOST_WIDE_INT mask;
10847 5921392 : rtx mask_rtx;
10848 :
10849 : /* We have one common special case. We can't do any merging if
10850 : the inner code is an ASHIFTRT of a smaller mode. However, if
10851 : we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10852 : with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10853 : we can convert it to
10854 : (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10855 : This simplifies certain SIGN_EXTEND operations. */
10856 5921392 : if (code == ASHIFT && first_code == ASHIFTRT
10857 5921392 : && count == (GET_MODE_PRECISION (int_result_mode)
10858 344691 : - GET_MODE_PRECISION (int_varop_mode)))
10859 : {
10860 : /* C3 has the low-order C1 bits zero. */
10861 :
10862 0 : mask = GET_MODE_MASK (int_mode)
10863 0 : & ~((HOST_WIDE_INT_1U << first_count) - 1);
10864 :
10865 0 : varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10866 : XEXP (varop, 0), mask);
10867 0 : varop = simplify_shift_const (NULL_RTX, ASHIFT,
10868 : int_result_mode, varop, count);
10869 0 : count = first_count;
10870 0 : code = ASHIFTRT;
10871 0 : continue;
10872 : }
10873 :
10874 : /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10875 : than C1 high-order bits equal to the sign bit, we can convert
10876 : this to either an ASHIFT or an ASHIFTRT depending on the
10877 : two counts.
10878 :
10879 : We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10880 :
10881 5922894 : if (code == ASHIFTRT && first_code == ASHIFT
10882 2917142 : && int_varop_mode == shift_unit_mode
10883 8831770 : && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10884 : > first_count))
10885 : {
10886 1502 : varop = XEXP (varop, 0);
10887 1502 : count -= first_count;
10888 1502 : if (count < 0)
10889 : {
10890 4 : count = -count;
10891 4 : code = ASHIFT;
10892 : }
10893 :
10894 1502 : continue;
10895 : }
10896 :
10897 : /* There are some cases we can't do. If CODE is ASHIFTRT,
10898 : we can only do this if FIRST_CODE is also ASHIFTRT.
10899 :
10900 : We can't do the case when CODE is ROTATE and FIRST_CODE is
10901 : ASHIFTRT.
10902 :
10903 : If the mode of this shift is not the mode of the outer shift,
10904 : we can't do this if either shift is a right shift or ROTATE.
10905 :
10906 : Finally, we can't do any of these if the mode is too wide
10907 : unless the codes are the same.
10908 :
10909 : Handle the case where the shift codes are the same
10910 : first. */
10911 :
10912 5919890 : if (code == first_code)
10913 : {
10914 31248 : if (int_varop_mode != int_result_mode
10915 31248 : && (code == ASHIFTRT || code == LSHIFTRT
10916 685 : || code == ROTATE))
10917 : break;
10918 :
10919 30587 : count += first_count;
10920 30587 : varop = XEXP (varop, 0);
10921 30587 : continue;
10922 : }
10923 :
10924 5888642 : if (code == ASHIFTRT
10925 2972954 : || (code == ROTATE && first_code == ASHIFTRT)
10926 2972924 : || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10927 8861566 : || (int_varop_mode != int_result_mode
10928 81356 : && (first_code == ASHIFTRT || first_code == LSHIFTRT
10929 81356 : || first_code == ROTATE
10930 26501 : || code == ROTATE)))
10931 : break;
10932 :
10933 : /* To compute the mask to apply after the shift, shift the
10934 : nonzero bits of the inner shift the same way the
10935 : outer shift will. */
10936 :
10937 2918069 : mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10938 : int_result_mode);
10939 2918069 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10940 2918069 : mask_rtx
10941 2918069 : = simplify_const_binary_operation (code, int_result_mode,
10942 : mask_rtx, count_rtx);
10943 :
10944 : /* Give up if we can't compute an outer operation to use. */
10945 2918069 : if (mask_rtx == 0
10946 2918069 : || !CONST_INT_P (mask_rtx)
10947 5836138 : || ! merge_outer_ops (&outer_op, &outer_const, AND,
10948 : INTVAL (mask_rtx),
10949 : int_result_mode, &complement_p))
10950 : break;
10951 :
10952 : /* If the shifts are in the same direction, we add the
10953 : counts. Otherwise, we subtract them. */
10954 2891562 : if ((code == ASHIFTRT || code == LSHIFTRT)
10955 2891562 : == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10956 11066 : count += first_count;
10957 : else
10958 2880496 : count -= first_count;
10959 :
10960 : /* If COUNT is positive, the new shift is usually CODE,
10961 : except for the two exceptions below, in which case it is
10962 : FIRST_CODE. If the count is negative, FIRST_CODE should
10963 : always be used */
10964 2891562 : if (count > 0
10965 705271 : && ((first_code == ROTATE && code == ASHIFT)
10966 704765 : || (first_code == ASHIFTRT && code == LSHIFTRT)))
10967 : code = first_code;
10968 2880502 : else if (count < 0)
10969 323408 : code = first_code, count = -count;
10970 :
10971 2891562 : varop = XEXP (varop, 0);
10972 2891562 : continue;
10973 2891562 : }
10974 :
10975 : /* If we have (A << B << C) for any shift, we can convert this to
10976 : (A << C << B). This wins if A is a constant. Only try this if
10977 : B is not a constant. */
10978 :
10979 50902 : else if (GET_CODE (varop) == code
10980 5278 : && CONST_INT_P (XEXP (varop, 0))
10981 1047 : && !CONST_INT_P (XEXP (varop, 1)))
10982 : {
10983 : /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10984 : sure the result will be masked. See PR70222. */
10985 1047 : if (code == LSHIFTRT
10986 7 : && int_mode != int_result_mode
10987 1054 : && !merge_outer_ops (&outer_op, &outer_const, AND,
10988 7 : GET_MODE_MASK (int_result_mode)
10989 7 : >> orig_count, int_result_mode,
10990 : &complement_p))
10991 : break;
10992 : /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10993 : up outer sign extension (often left and right shift) is
10994 : hardly more efficient than the original. See PR70429.
10995 : Similarly punt for rotates with different modes.
10996 : See PR97386. */
10997 1047 : if ((code == ASHIFTRT || code == ROTATE)
10998 1047 : && int_mode != int_result_mode)
10999 : break;
11000 :
11001 1033 : rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
11002 1033 : rtx new_rtx = simplify_const_binary_operation (code, int_mode,
11003 : XEXP (varop, 0),
11004 : count_rtx);
11005 1033 : varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
11006 1033 : count = 0;
11007 1033 : continue;
11008 1033 : }
11009 : break;
11010 :
11011 59606 : case NOT:
11012 : /* The following rules apply only to scalars. */
11013 59606 : if (shift_mode != shift_unit_mode)
11014 : break;
11015 :
11016 : /* Make this fit the case below. */
11017 59589 : varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11018 59589 : continue;
11019 :
11020 718508 : case IOR:
11021 718508 : case AND:
11022 718508 : case XOR:
11023 : /* The following rules apply only to scalars. */
11024 718508 : if (shift_mode != shift_unit_mode)
11025 : break;
11026 714413 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11027 714413 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11028 :
11029 : /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11030 : with C the size of VAROP - 1 and the shift is logical if
11031 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11032 : we have an (le X 0) operation. If we have an arithmetic shift
11033 : and STORE_FLAG_VALUE is 1 or we have a logical shift with
11034 : STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11035 :
11036 187711 : if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11037 1542 : && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11038 : && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11039 140 : && (code == LSHIFTRT || code == ASHIFTRT)
11040 140 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11041 714553 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11042 : {
11043 56 : count = 0;
11044 56 : varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11045 : const0_rtx);
11046 :
11047 56 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11048 56 : varop = gen_rtx_NEG (int_varop_mode, varop);
11049 :
11050 56 : continue;
11051 : }
11052 :
11053 : /* If we have (shift (logical)), move the logical to the outside
11054 : to allow it to possibly combine with another logical and the
11055 : shift to combine with another shift. This also canonicalizes to
11056 : what a ZERO_EXTRACT looks like. Also, some machines have
11057 : (and (shift)) insns. */
11058 :
11059 1140814 : if (CONST_INT_P (XEXP (varop, 1))
11060 : /* We can't do this if we have (ashiftrt (xor)) and the
11061 : constant has its sign bit set in shift_unit_mode with
11062 : shift_unit_mode wider than result_mode. */
11063 427788 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11064 8703 : && int_result_mode != shift_unit_mode
11065 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11066 : shift_unit_mode) < 0)
11067 427788 : && (new_rtx = simplify_const_binary_operation
11068 427788 : (code, int_result_mode,
11069 427788 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11070 427788 : gen_int_shift_amount (int_result_mode, count))) != 0
11071 427788 : && CONST_INT_P (new_rtx)
11072 1142145 : && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11073 : INTVAL (new_rtx), int_result_mode,
11074 : &complement_p))
11075 : {
11076 426457 : varop = XEXP (varop, 0);
11077 426457 : continue;
11078 : }
11079 :
11080 : /* If we can't do that, try to simplify the shift in each arm of the
11081 : logical expression, make a new logical expression, and apply
11082 : the inverse distributive law. This also can't be done for
11083 : (ashiftrt (xor)) where we've widened the shift and the constant
11084 : changes the sign bit. */
11085 287900 : if (CONST_INT_P (XEXP (varop, 1))
11086 287900 : && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11087 48 : && int_result_mode != shift_unit_mode
11088 0 : && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11089 : shift_unit_mode) < 0))
11090 : {
11091 1331 : rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11092 : XEXP (varop, 0), count);
11093 1331 : rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11094 : XEXP (varop, 1), count);
11095 :
11096 1331 : varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11097 : lhs, rhs);
11098 1331 : varop = apply_distributive_law (varop);
11099 :
11100 1331 : count = 0;
11101 1331 : continue;
11102 1331 : }
11103 : break;
11104 :
11105 34152 : case EQ:
11106 : /* The following rules apply only to scalars. */
11107 34152 : if (shift_mode != shift_unit_mode)
11108 : break;
11109 34152 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11110 :
11111 : /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11112 : says that the sign bit can be tested, FOO has mode MODE, C is
11113 : GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11114 : that may be nonzero. */
11115 34152 : if (code == LSHIFTRT
11116 0 : && XEXP (varop, 1) == const0_rtx
11117 0 : && GET_MODE (XEXP (varop, 0)) == int_result_mode
11118 0 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11119 34152 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11120 : && STORE_FLAG_VALUE == -1
11121 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11122 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11123 : int_result_mode, &complement_p))
11124 : {
11125 : varop = XEXP (varop, 0);
11126 : count = 0;
11127 : continue;
11128 : }
11129 : break;
11130 :
11131 27440 : case NEG:
11132 : /* The following rules apply only to scalars. */
11133 27440 : if (shift_mode != shift_unit_mode)
11134 : break;
11135 27310 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11136 :
11137 : /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11138 : than the number of bits in the mode is equivalent to A. */
11139 27315 : if (code == LSHIFTRT
11140 5783 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11141 29969 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11142 : {
11143 5 : varop = XEXP (varop, 0);
11144 5 : count = 0;
11145 5 : continue;
11146 : }
11147 :
11148 : /* NEG commutes with ASHIFT since it is multiplication. Move the
11149 : NEG outside to allow shifts to combine. */
11150 45410 : if (code == ASHIFT
11151 27305 : && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11152 : int_result_mode, &complement_p))
11153 : {
11154 18105 : varop = XEXP (varop, 0);
11155 18105 : continue;
11156 : }
11157 : break;
11158 :
11159 2045165 : case PLUS:
11160 : /* The following rules apply only to scalars. */
11161 2045165 : if (shift_mode != shift_unit_mode)
11162 : break;
11163 1965012 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11164 :
11165 : /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11166 : is one less than the number of bits in the mode is
11167 : equivalent to (xor A 1). */
11168 1965012 : if (code == LSHIFTRT
11169 404106 : && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11170 34095 : && XEXP (varop, 1) == constm1_rtx
11171 16681 : && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11172 1965012 : && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11173 : int_result_mode, &complement_p))
11174 : {
11175 0 : count = 0;
11176 0 : varop = XEXP (varop, 0);
11177 0 : continue;
11178 : }
11179 :
11180 : /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11181 : that might be nonzero in BAR are those being shifted out and those
11182 : bits are known zero in FOO, we can replace the PLUS with FOO.
11183 : Similarly in the other operand order. This code occurs when
11184 : we are computing the size of a variable-size array. */
11185 :
11186 1968370 : if ((code == ASHIFTRT || code == LSHIFTRT)
11187 573966 : && count < HOST_BITS_PER_WIDE_INT
11188 572797 : && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11189 2144766 : && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11190 179754 : & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11191 : {
11192 3358 : varop = XEXP (varop, 0);
11193 3358 : continue;
11194 : }
11195 1961686 : else if ((code == ASHIFTRT || code == LSHIFTRT)
11196 570608 : && count < HOST_BITS_PER_WIDE_INT
11197 569439 : && HWI_COMPUTABLE_MODE_P (int_result_mode)
11198 568201 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11199 568201 : >> count) == 0
11200 2056409 : && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11201 94755 : & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11202 : {
11203 32 : varop = XEXP (varop, 1);
11204 32 : continue;
11205 : }
11206 :
11207 : /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11208 2343632 : if (code == ASHIFT
11209 1382216 : && CONST_INT_P (XEXP (varop, 1))
11210 382165 : && (new_rtx = simplify_const_binary_operation
11211 382165 : (ASHIFT, int_result_mode,
11212 382165 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11213 382165 : gen_int_shift_amount (int_result_mode, count))) != 0
11214 382165 : && CONST_INT_P (new_rtx)
11215 2343787 : && merge_outer_ops (&outer_op, &outer_const, PLUS,
11216 : INTVAL (new_rtx), int_result_mode,
11217 : &complement_p))
11218 : {
11219 382010 : varop = XEXP (varop, 0);
11220 382010 : continue;
11221 : }
11222 :
11223 : /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11224 : signbit', and attempt to change the PLUS to an XOR and move it to
11225 : the outer operation as is done above in the AND/IOR/XOR case
11226 : leg for shift(logical). See details in logical handling above
11227 : for reasoning in doing so. */
11228 1588018 : if (code == LSHIFTRT
11229 400818 : && CONST_INT_P (XEXP (varop, 1))
11230 281565 : && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11231 8406 : && (new_rtx = simplify_const_binary_operation
11232 1579612 : (code, int_result_mode,
11233 8406 : gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11234 8406 : gen_int_shift_amount (int_result_mode, count))) != 0
11235 8406 : && CONST_INT_P (new_rtx)
11236 1588018 : && merge_outer_ops (&outer_op, &outer_const, XOR,
11237 : INTVAL (new_rtx), int_result_mode,
11238 : &complement_p))
11239 : {
11240 8406 : varop = XEXP (varop, 0);
11241 8406 : continue;
11242 : }
11243 :
11244 : break;
11245 :
11246 632975 : case MINUS:
11247 : /* The following rules apply only to scalars. */
11248 632975 : if (shift_mode != shift_unit_mode)
11249 : break;
11250 613544 : int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11251 :
11252 : /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11253 : with C the size of VAROP - 1 and the shift is logical if
11254 : STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11255 : we have a (gt X 0) operation. If the shift is arithmetic with
11256 : STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11257 : we have a (neg (gt X 0)) operation. */
11258 :
11259 613544 : if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11260 613544 : && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11261 12278 : && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11262 48 : && (code == LSHIFTRT || code == ASHIFTRT)
11263 13 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11264 13 : && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11265 613544 : && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11266 : {
11267 0 : count = 0;
11268 0 : varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11269 : const0_rtx);
11270 :
11271 0 : if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11272 0 : varop = gen_rtx_NEG (int_varop_mode, varop);
11273 :
11274 0 : continue;
11275 : }
11276 : break;
11277 :
11278 683 : case TRUNCATE:
11279 : /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11280 : if the truncate does not affect the value. */
11281 683 : if (code == LSHIFTRT
11282 525 : && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11283 525 : && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11284 683 : && (INTVAL (XEXP (XEXP (varop, 0), 1))
11285 525 : >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11286 1050 : - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11287 : {
11288 525 : rtx varop_inner = XEXP (varop, 0);
11289 525 : int new_count = count + INTVAL (XEXP (varop_inner, 1));
11290 525 : rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11291 525 : new_count);
11292 525 : varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11293 : XEXP (varop_inner, 0),
11294 : new_count_rtx);
11295 525 : varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11296 525 : count = 0;
11297 525 : continue;
11298 525 : }
11299 : break;
11300 :
11301 : default:
11302 : break;
11303 59589 : }
11304 :
11305 : break;
11306 : }
11307 :
11308 24195746 : shift_mode = result_mode;
11309 24195746 : if (shift_mode != mode)
11310 : {
11311 : /* We only change the modes of scalar shifts. */
11312 197617 : int_mode = as_a <scalar_int_mode> (mode);
11313 197617 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11314 197617 : shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11315 : int_mode, outer_op, outer_const);
11316 : }
11317 :
11318 : /* We have now finished analyzing the shift. The result should be
11319 : a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11320 : OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11321 : to the result of the shift. OUTER_CONST is the relevant constant,
11322 : but we must turn off all bits turned off in the shift. */
11323 :
11324 24195746 : if (outer_op == UNKNOWN
11325 20535779 : && orig_code == code && orig_count == count
11326 20487685 : && varop == orig_varop
11327 20316255 : && shift_mode == GET_MODE (varop))
11328 : return NULL_RTX;
11329 :
11330 : /* Make a SUBREG if necessary. If we can't make it, fail. */
11331 3881826 : varop = gen_lowpart (shift_mode, varop);
11332 3881826 : if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11333 : return NULL_RTX;
11334 :
11335 : /* If we have an outer operation and we just made a shift, it is
11336 : possible that we could have simplified the shift were it not
11337 : for the outer operation. So try to do the simplification
11338 : recursively. */
11339 :
11340 3881826 : if (outer_op != UNKNOWN)
11341 3659967 : x = simplify_shift_const_1 (code, shift_mode, varop, count);
11342 : else
11343 : x = NULL_RTX;
11344 :
11345 3659967 : if (x == NULL_RTX)
11346 3845943 : x = simplify_gen_binary (code, shift_mode, varop,
11347 3845943 : gen_int_shift_amount (shift_mode, count));
11348 :
11349 : /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11350 : turn off all the bits that the shift would have turned off. */
11351 3881826 : if (orig_code == LSHIFTRT && result_mode != shift_mode)
11352 : /* We only change the modes of scalar shifts. */
11353 27296 : x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11354 27296 : x, GET_MODE_MASK (result_mode) >> orig_count);
11355 :
11356 : /* Do the remainder of the processing in RESULT_MODE. */
11357 3881826 : x = gen_lowpart_or_truncate (result_mode, x);
11358 :
11359 : /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11360 : operation. */
11361 3881826 : if (complement_p)
11362 24241 : x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11363 :
11364 3881826 : if (outer_op != UNKNOWN)
11365 : {
11366 3659967 : int_result_mode = as_a <scalar_int_mode> (result_mode);
11367 :
11368 3659967 : if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11369 3659967 : && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11370 1341712 : outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11371 :
11372 3659967 : if (outer_op == AND)
11373 3192850 : x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11374 467117 : else if (outer_op == SET)
11375 : {
11376 : /* This means that we have determined that the result is
11377 : equivalent to a constant. This should be rare. */
11378 0 : if (!side_effects_p (x))
11379 0 : x = GEN_INT (outer_const);
11380 : }
11381 467117 : else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11382 18105 : x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11383 : else
11384 449012 : x = simplify_gen_binary (outer_op, int_result_mode, x,
11385 : GEN_INT (outer_const));
11386 : }
11387 :
11388 : return x;
11389 : }
11390 :
11391 : /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11392 : The result of the shift is RESULT_MODE. If we cannot simplify it,
11393 : return X or, if it is NULL, synthesize the expression with
11394 : simplify_gen_binary. Otherwise, return a simplified value.
11395 :
11396 : The shift is normally computed in the widest mode we find in VAROP, as
11397 : long as it isn't a different number of words than RESULT_MODE. Exceptions
11398 : are ASHIFTRT and ROTATE, which are always done in their original mode. */
11399 :
11400 : static rtx
11401 20536051 : simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11402 : rtx varop, int count)
11403 : {
11404 20536051 : rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11405 20536051 : if (tem)
11406 : return tem;
11407 :
11408 16690108 : if (!x)
11409 4948035 : x = simplify_gen_binary (code, GET_MODE (varop), varop,
11410 4948035 : gen_int_shift_amount (GET_MODE (varop), count));
11411 16690108 : if (GET_MODE (x) != result_mode)
11412 0 : x = gen_lowpart (result_mode, x);
11413 : return x;
11414 : }
11415 :
11416 :
11417 : /* A subroutine of recog_for_combine. See there for arguments and
11418 : return value. */
11419 :
11420 : static int
11421 50093255 : recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11422 : unsigned old_nregs, unsigned new_nregs)
11423 : {
11424 50093255 : rtx pat = *pnewpat;
11425 50093255 : rtx pat_without_clobbers;
11426 50093255 : int insn_code_number;
11427 50093255 : int num_clobbers_to_add = 0;
11428 50093255 : int i;
11429 50093255 : rtx notes = NULL_RTX;
11430 50093255 : rtx old_notes, old_pat;
11431 50093255 : int old_icode;
11432 :
11433 : /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11434 : we use to indicate that something didn't match. If we find such a
11435 : thing, force rejection. */
11436 50093255 : if (GET_CODE (pat) == PARALLEL)
11437 54237862 : for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11438 37402384 : if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11439 7550857 : && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11440 : return -1;
11441 :
11442 50091199 : old_pat = PATTERN (insn);
11443 50091199 : old_notes = REG_NOTES (insn);
11444 50091199 : PATTERN (insn) = pat;
11445 50091199 : REG_NOTES (insn) = NULL_RTX;
11446 :
11447 50091199 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11448 50091199 : if (dump_file && (dump_flags & TDF_DETAILS))
11449 : {
11450 277 : if (insn_code_number < 0)
11451 177 : fputs ("Failed to match this instruction:\n", dump_file);
11452 : else
11453 100 : fputs ("Successfully matched this instruction:\n", dump_file);
11454 277 : print_rtl_single (dump_file, pat);
11455 : }
11456 :
11457 : /* If it isn't, there is the possibility that we previously had an insn
11458 : that clobbered some register as a side effect, but the combined
11459 : insn doesn't need to do that. So try once more without the clobbers
11460 : unless this represents an ASM insn. */
11461 :
11462 39922559 : if (insn_code_number < 0 && ! check_asm_operands (pat)
11463 90011390 : && GET_CODE (pat) == PARALLEL)
11464 : {
11465 : int pos;
11466 :
11467 52718603 : for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11468 36368215 : if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11469 : {
11470 29235151 : if (i != pos)
11471 2440725 : SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11472 29235151 : pos++;
11473 : }
11474 :
11475 16350388 : SUBST_INT (XVECLEN (pat, 0), pos);
11476 :
11477 16350388 : if (pos == 1)
11478 4767410 : pat = XVECEXP (pat, 0, 0);
11479 :
11480 16350388 : PATTERN (insn) = pat;
11481 16350388 : insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11482 16350388 : if (dump_file && (dump_flags & TDF_DETAILS))
11483 : {
11484 82 : if (insn_code_number < 0)
11485 81 : fputs ("Failed to match this instruction:\n", dump_file);
11486 : else
11487 1 : fputs ("Successfully matched this instruction:\n", dump_file);
11488 82 : print_rtl_single (dump_file, pat);
11489 : }
11490 : }
11491 :
11492 50091199 : pat_without_clobbers = pat;
11493 :
11494 50091199 : PATTERN (insn) = old_pat;
11495 50091199 : REG_NOTES (insn) = old_notes;
11496 :
11497 : /* Recognize all noop sets, these will be killed by followup pass. */
11498 50091199 : if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11499 241928 : insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11500 :
11501 : /* If we had any clobbers to add, make a new pattern than contains
11502 : them. Then check to make sure that all of them are dead. */
11503 50091199 : if (num_clobbers_to_add)
11504 : {
11505 1652438 : rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11506 : rtvec_alloc (GET_CODE (pat) == PARALLEL
11507 : ? (XVECLEN (pat, 0)
11508 : + num_clobbers_to_add)
11509 : : num_clobbers_to_add + 1));
11510 :
11511 1652438 : if (GET_CODE (pat) == PARALLEL)
11512 1455 : for (i = 0; i < XVECLEN (pat, 0); i++)
11513 970 : XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11514 : else
11515 1651953 : XVECEXP (newpat, 0, 0) = pat;
11516 :
11517 1652438 : add_clobbers (newpat, insn_code_number);
11518 :
11519 3179148 : for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11520 3179148 : i < XVECLEN (newpat, 0); i++)
11521 : {
11522 1674436 : if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11523 1674436 : && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11524 : return -1;
11525 1526710 : if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11526 : {
11527 1476610 : gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11528 1476610 : notes = alloc_reg_note (REG_UNUSED,
11529 : XEXP (XVECEXP (newpat, 0, i), 0), notes);
11530 : }
11531 : }
11532 : pat = newpat;
11533 : }
11534 :
11535 49943473 : if (insn_code_number >= 0
11536 49943473 : && insn_code_number != NOOP_MOVE_INSN_CODE)
11537 : {
11538 : /* Create the reg dead notes if needed for the regs that were created via split. */
11539 10341488 : for (; old_nregs < new_nregs; old_nregs++)
11540 2276 : notes = alloc_reg_note (REG_DEAD, regno_reg_rtx[old_nregs], notes);
11541 10339212 : old_pat = PATTERN (insn);
11542 10339212 : old_notes = REG_NOTES (insn);
11543 10339212 : old_icode = INSN_CODE (insn);
11544 10339212 : PATTERN (insn) = pat;
11545 10339212 : REG_NOTES (insn) = notes;
11546 10339212 : INSN_CODE (insn) = insn_code_number;
11547 :
11548 : /* Do not accept an insn if hard register constraints are used. For
11549 : example, assume that the first insn is combined into the last one:
11550 :
11551 : r100=...
11552 : %5=...
11553 : r101=exp(r100)
11554 :
11555 : If the resulting insn has an operand which is constrained to hard
11556 : register %5, then this introduces a conflict since register %5 is live
11557 : at this point. Therefore, skip for now. This is a sledge hammer
11558 : approach. Ideally we would skip based on the fact whether a
11559 : combination crosses a hard register assignment and the corresponding
11560 : hard register is also referred by a single register constraint of the
11561 : resulting insn. */
11562 10339212 : bool has_hard_reg_cstr = false;
11563 10339212 : extract_insn (insn);
11564 35241331 : for (int nop = recog_data.n_operands - 1; nop >= 0; --nop)
11565 24902119 : if (strchr (recog_data.constraints[nop], '{'))
11566 : {
11567 : has_hard_reg_cstr = true;
11568 : break;
11569 : }
11570 :
11571 : /* Don't accept hard register constraints. Allow targets to reject
11572 : combined insn. */
11573 10339212 : if (has_hard_reg_cstr || !targetm.legitimate_combined_insn (insn))
11574 : {
11575 3660 : if (dump_file && (dump_flags & TDF_DETAILS))
11576 : {
11577 0 : if (has_hard_reg_cstr)
11578 0 : fputs ("Instruction makes use of hard register constraints.",
11579 : dump_file);
11580 : else
11581 0 : fputs ("Instruction not appropriate for target.",
11582 : dump_file);
11583 : }
11584 :
11585 : /* Callers expect recog_for_combine to strip
11586 : clobbers from the pattern on failure. */
11587 : pat = pat_without_clobbers;
11588 : notes = NULL_RTX;
11589 :
11590 : insn_code_number = -1;
11591 : }
11592 :
11593 10339212 : PATTERN (insn) = old_pat;
11594 10339212 : REG_NOTES (insn) = old_notes;
11595 10339212 : INSN_CODE (insn) = old_icode;
11596 : }
11597 :
11598 49943473 : *pnewpat = pat;
11599 49943473 : *pnotes = notes;
11600 :
11601 49943473 : return insn_code_number;
11602 : }
11603 :
11604 : /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11605 : expressed as an AND and maybe an LSHIFTRT, to that formulation.
11606 : Return whether anything was so changed. */
11607 :
11608 : static bool
11609 50301963 : change_zero_ext (rtx pat)
11610 : {
11611 50301963 : bool changed = false;
11612 50301963 : rtx *src = &SET_SRC (pat);
11613 :
11614 50301963 : subrtx_ptr_iterator::array_type array;
11615 350909787 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11616 : {
11617 300607824 : rtx x = **iter;
11618 300607824 : scalar_int_mode mode, inner_mode;
11619 300607824 : if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11620 300607824 : continue;
11621 157879766 : int size;
11622 :
11623 157879766 : if (GET_CODE (x) == ZERO_EXTRACT
11624 810065 : && CONST_INT_P (XEXP (x, 1))
11625 810051 : && CONST_INT_P (XEXP (x, 2))
11626 767880 : && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11627 158647642 : && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11628 : {
11629 767858 : size = INTVAL (XEXP (x, 1));
11630 :
11631 767858 : int start = INTVAL (XEXP (x, 2));
11632 767858 : if (BITS_BIG_ENDIAN)
11633 : start = GET_MODE_PRECISION (inner_mode) - size - start;
11634 :
11635 767858 : if (start != 0)
11636 648085 : x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11637 : gen_int_shift_amount (inner_mode, start));
11638 : else
11639 : x = XEXP (x, 0);
11640 :
11641 767858 : if (mode != inner_mode)
11642 : {
11643 151 : if (REG_P (x) && HARD_REGISTER_P (x)
11644 211569 : && !can_change_dest_mode (x, 0, mode))
11645 0 : continue;
11646 :
11647 211569 : x = gen_lowpart_SUBREG (mode, x);
11648 : }
11649 : }
11650 157111908 : else if (GET_CODE (x) == ZERO_EXTEND
11651 2305341 : && GET_CODE (XEXP (x, 0)) == SUBREG
11652 440198 : && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11653 432495 : && !paradoxical_subreg_p (XEXP (x, 0))
11654 157544403 : && subreg_lowpart_p (XEXP (x, 0)))
11655 : {
11656 304058 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11657 304058 : size = GET_MODE_PRECISION (inner_mode);
11658 304058 : x = SUBREG_REG (XEXP (x, 0));
11659 304058 : if (GET_MODE (x) != mode)
11660 : {
11661 18245 : if (REG_P (x) && HARD_REGISTER_P (x)
11662 21137 : && !can_change_dest_mode (x, 0, mode))
11663 0 : continue;
11664 :
11665 21137 : x = gen_lowpart_SUBREG (mode, x);
11666 : }
11667 : }
11668 313615627 : else if (GET_CODE (x) == ZERO_EXTEND
11669 2001283 : && REG_P (XEXP (x, 0))
11670 1024074 : && HARD_REGISTER_P (XEXP (x, 0))
11671 156807923 : && can_change_dest_mode (XEXP (x, 0), 0, mode))
11672 : {
11673 73 : inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11674 73 : size = GET_MODE_PRECISION (inner_mode);
11675 73 : x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11676 : }
11677 : else
11678 156807777 : continue;
11679 :
11680 1526998 : if (!(GET_CODE (x) == LSHIFTRT
11681 455009 : && CONST_INT_P (XEXP (x, 1))
11682 455009 : && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11683 : {
11684 887363 : wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11685 887363 : x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11686 887363 : }
11687 :
11688 1071989 : SUBST (**iter, x);
11689 1071989 : changed = true;
11690 : }
11691 :
11692 50301963 : if (changed)
11693 9894643 : FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11694 8835948 : maybe_swap_commutative_operands (**iter);
11695 :
11696 50301963 : rtx *dst = &SET_DEST (pat);
11697 50301963 : scalar_int_mode mode;
11698 50301963 : if (GET_CODE (*dst) == ZERO_EXTRACT
11699 7993 : && REG_P (XEXP (*dst, 0))
11700 243 : && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11701 243 : && CONST_INT_P (XEXP (*dst, 1))
11702 50302206 : && CONST_INT_P (XEXP (*dst, 2)))
11703 : {
11704 144 : rtx reg = XEXP (*dst, 0);
11705 144 : int width = INTVAL (XEXP (*dst, 1));
11706 144 : int offset = INTVAL (XEXP (*dst, 2));
11707 144 : int reg_width = GET_MODE_PRECISION (mode);
11708 144 : if (BITS_BIG_ENDIAN)
11709 : offset = reg_width - width - offset;
11710 :
11711 144 : rtx x, y, z, w;
11712 144 : wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11713 144 : wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11714 144 : x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11715 144 : if (offset)
11716 144 : y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11717 : else
11718 0 : y = SET_SRC (pat);
11719 144 : z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11720 144 : w = gen_rtx_IOR (mode, x, z);
11721 144 : SUBST (SET_DEST (pat), reg);
11722 144 : SUBST (SET_SRC (pat), w);
11723 :
11724 144 : changed = true;
11725 144 : }
11726 :
11727 50301963 : return changed;
11728 50301963 : }
11729 :
11730 : /* Like recog, but we receive the address of a pointer to a new pattern.
11731 : We try to match the rtx that the pointer points to.
11732 : If that fails, we may try to modify or replace the pattern,
11733 : storing the replacement into the same pointer object.
11734 :
11735 : Modifications include deletion or addition of CLOBBERs. If the
11736 : instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11737 : to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11738 : (and undo if that fails).
11739 :
11740 : PNOTES is a pointer to a location where any REG_UNUSED notes added for
11741 : the CLOBBERs are placed.
11742 : If OLD_NREGS != NEW_NREGS, then PNOTES also includes REG_DEAD notes added.
11743 :
11744 : The value is the final insn code from the pattern ultimately matched,
11745 : or -1. */
11746 :
11747 : static int
11748 48795338 : recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes,
11749 : unsigned int old_nregs, unsigned int new_nregs)
11750 : {
11751 48795338 : rtx pat = *pnewpat;
11752 48795338 : int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11753 : old_nregs, new_nregs);
11754 48795338 : if (insn_code_number >= 0 || check_asm_operands (pat))
11755 : return insn_code_number;
11756 :
11757 38379814 : void *marker = get_undo_marker ();
11758 38379814 : bool changed = false;
11759 :
11760 38379814 : if (GET_CODE (pat) == SET)
11761 : {
11762 : /* For an unrecognized single set of a constant, try placing it in
11763 : the constant pool, if this function already uses one. */
11764 22610369 : rtx src = SET_SRC (pat);
11765 22610369 : if (CONSTANT_P (src)
11766 472198 : && !CONST_INT_P (src)
11767 422116 : && crtl->uses_const_pool
11768 369894 : && SET_DEST (pat) != pc_rtx)
11769 : {
11770 369892 : machine_mode mode = GET_MODE (src);
11771 369892 : if (mode == VOIDmode)
11772 1343 : mode = GET_MODE (SET_DEST (pat));
11773 369892 : src = force_const_mem (mode, src);
11774 369892 : if (src)
11775 : {
11776 369882 : SUBST (SET_SRC (pat), src);
11777 369882 : changed = true;
11778 : }
11779 : }
11780 : else
11781 22240477 : changed = change_zero_ext (pat);
11782 : }
11783 15769445 : else if (GET_CODE (pat) == PARALLEL)
11784 : {
11785 : int i;
11786 44073390 : for (i = 0; i < XVECLEN (pat, 0); i++)
11787 : {
11788 28319594 : rtx set = XVECEXP (pat, 0, i);
11789 28319594 : if (GET_CODE (set) == SET)
11790 28061486 : changed |= change_zero_ext (set);
11791 : }
11792 : }
11793 :
11794 38364155 : if (changed)
11795 : {
11796 1297917 : insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes,
11797 : old_nregs, new_nregs);
11798 :
11799 1297917 : if (insn_code_number < 0)
11800 1133593 : undo_to_marker (marker);
11801 : }
11802 :
11803 : return insn_code_number;
11804 : }
11805 :
11806 : /* Like gen_lowpart_general but for use by combine. In combine it
11807 : is not possible to create any new pseudoregs. However, it is
11808 : safe to create invalid memory addresses, because combine will
11809 : try to recognize them and all they will do is make the combine
11810 : attempt fail.
11811 :
11812 : If for some reason this cannot do its job, an rtx
11813 : (clobber (const_int 0)) is returned.
11814 : An insn containing that will not be recognized. */
11815 :
11816 : static rtx
11817 159883639 : gen_lowpart_for_combine (machine_mode omode, rtx x)
11818 : {
11819 159883639 : machine_mode imode = GET_MODE (x);
11820 159883639 : rtx result;
11821 :
11822 159883639 : if (omode == imode)
11823 : return x;
11824 :
11825 : /* We can only support MODE being wider than a word if X is a
11826 : constant integer or has a mode the same size. */
11827 56251434 : if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11828 26653602 : && ! (CONST_SCALAR_INT_P (x)
11829 10298010 : || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11830 3100557 : goto fail;
11831 :
11832 : /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11833 : won't know what to do. So we will strip off the SUBREG here and
11834 : process normally. */
11835 23553045 : if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11836 : {
11837 13519 : x = SUBREG_REG (x);
11838 :
11839 : /* For use in case we fall down into the address adjustments
11840 : further below, we need to adjust the known mode and size of
11841 : x; imode and isize, since we just adjusted x. */
11842 13519 : imode = GET_MODE (x);
11843 :
11844 13519 : if (imode == omode)
11845 : return x;
11846 : }
11847 :
11848 23544111 : result = gen_lowpart_common (omode, x);
11849 :
11850 23544111 : if (result)
11851 : return result;
11852 :
11853 9956753 : if (MEM_P (x))
11854 : {
11855 : /* Refuse to work on a volatile memory ref or one with a mode-dependent
11856 : address. */
11857 1941124 : if (MEM_VOLATILE_P (x)
11858 3831762 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11859 50512 : goto fail;
11860 :
11861 : /* If we want to refer to something bigger than the original memref,
11862 : generate a paradoxical subreg instead. That will force a reload
11863 : of the original memref X. */
11864 1890612 : if (paradoxical_subreg_p (omode, imode)
11865 1890612 : && validate_subreg (omode, GET_MODE (x), x, 0))
11866 1664573 : return gen_rtx_SUBREG (omode, x, 0);
11867 :
11868 226039 : poly_int64 offset = byte_lowpart_offset (omode, imode);
11869 226039 : return adjust_address_nv (x, omode, offset);
11870 : }
11871 :
11872 : /* If X is a comparison operator, rewrite it in a new mode. This
11873 : probably won't match, but may allow further simplifications. */
11874 8015629 : else if (COMPARISON_P (x)
11875 150379 : && SCALAR_INT_MODE_P (imode)
11876 53993 : && SCALAR_INT_MODE_P (omode))
11877 53982 : return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11878 :
11879 : /* If we couldn't simplify X any other way, just enclose it in a
11880 : SUBREG. Normally, this SUBREG won't match, but some patterns may
11881 : include an explicit SUBREG or we may simplify it further in combine. */
11882 : else
11883 : {
11884 7961647 : rtx res;
11885 :
11886 7961647 : if (imode == VOIDmode)
11887 : {
11888 8 : imode = int_mode_for_mode (omode).require ();
11889 8 : x = gen_lowpart_common (imode, x);
11890 8 : if (x == NULL)
11891 0 : goto fail;
11892 : }
11893 7961647 : res = lowpart_subreg (omode, x, imode);
11894 7961647 : if (res)
11895 : return res;
11896 : }
11897 :
11898 16392 : fail:
11899 3167461 : return gen_rtx_CLOBBER (omode, const0_rtx);
11900 : }
11901 :
11902 : /* Like gen_lowpart_for_combine but returns NULL_RTX
11903 : for an error instead of CLOBBER.
11904 : Note no_emit is not called directly from combine but rather from
11905 : simplify_rtx and is expecting a NULL on failure rather than
11906 : a CLOBBER. */
11907 :
11908 : static rtx
11909 1573660 : gen_lowpart_for_combine_no_emit (machine_mode omode, rtx x)
11910 : {
11911 1573660 : rtx tem = gen_lowpart_for_combine (omode, x);
11912 1573660 : if (!tem || GET_CODE (tem) == CLOBBER)
11913 16133 : return NULL_RTX;
11914 : return tem;
11915 : }
11916 :
11917 :
11918 : /* Try to simplify a comparison between OP0 and a constant OP1,
11919 : where CODE is the comparison code that will be tested, into a
11920 : (CODE OP0 const0_rtx) form.
11921 :
11922 : The result is a possibly different comparison code to use.
11923 : *POP0 and *POP1 may be updated. */
11924 :
11925 : static enum rtx_code
11926 16208075 : simplify_compare_const (enum rtx_code code, machine_mode mode,
11927 : rtx *pop0, rtx *pop1)
11928 : {
11929 16208075 : scalar_int_mode int_mode;
11930 16208075 : rtx op0 = *pop0;
11931 16208075 : HOST_WIDE_INT const_op = INTVAL (*pop1);
11932 :
11933 : /* Get the constant we are comparing against and turn off all bits
11934 : not on in our mode. */
11935 16208075 : if (mode != VOIDmode)
11936 15807347 : const_op = trunc_int_for_mode (const_op, mode);
11937 :
11938 : /* If we are comparing against a constant power of two and the value
11939 : being compared can only have that single bit nonzero (e.g., it was
11940 : `and'ed with that bit), we can replace this with a comparison
11941 : with zero. */
11942 16208075 : if (const_op
11943 4293079 : && (code == EQ || code == NE || code == GEU || code == LTU
11944 : /* This optimization is incorrect for signed >= INT_MIN or
11945 : < INT_MIN, those are always true or always false. */
11946 25808 : || ((code == GE || code == LT) && const_op > 0))
11947 2878677 : && is_a <scalar_int_mode> (mode, &int_mode)
11948 2878677 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11949 2859483 : && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11950 17126618 : && (nonzero_bits (op0, int_mode)
11951 918543 : == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11952 : {
11953 5078 : code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11954 : const_op = 0;
11955 : }
11956 :
11957 : /* Similarly, if we are comparing a value known to be either -1 or
11958 : 0 with -1, change it to the opposite comparison against zero. */
11959 2450 : if (const_op == -1
11960 260793 : && (code == EQ || code == NE || code == GT || code == LE
11961 : || code == GEU || code == LTU)
11962 16454018 : && is_a <scalar_int_mode> (mode, &int_mode)
11963 16461138 : && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11964 : {
11965 12198 : code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11966 : const_op = 0;
11967 : }
11968 :
11969 : /* Do some canonicalizations based on the comparison code. We prefer
11970 : comparisons against zero and then prefer equality comparisons.
11971 : If we can reduce the size of a constant, we will do that too. */
11972 16195877 : switch (code)
11973 : {
11974 272754 : case LT:
11975 : /* < C is equivalent to <= (C - 1) */
11976 272754 : if (const_op > 0)
11977 : {
11978 5116 : const_op -= 1;
11979 5116 : code = LE;
11980 : /* ... fall through to LE case below. */
11981 462279 : gcc_fallthrough ();
11982 : }
11983 : else
11984 : break;
11985 :
11986 462279 : case LE:
11987 : /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11988 462279 : if (const_op < 0)
11989 : {
11990 52 : const_op += 1;
11991 52 : code = LT;
11992 : }
11993 :
11994 : /* If we are doing a <= 0 comparison on a value known to have
11995 : a zero sign bit, we can replace this with == 0. */
11996 462227 : else if (const_op == 0
11997 320628 : && is_a <scalar_int_mode> (mode, &int_mode)
11998 320628 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11999 782855 : && (nonzero_bits (op0, int_mode)
12000 320628 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12001 320628 : == 0)
12002 : code = EQ;
12003 : break;
12004 :
12005 239404 : case GE:
12006 : /* >= C is equivalent to > (C - 1). */
12007 239404 : if (const_op > 0)
12008 : {
12009 1264 : const_op -= 1;
12010 1264 : code = GT;
12011 : /* ... fall through to GT below. */
12012 263663 : gcc_fallthrough ();
12013 : }
12014 : else
12015 : break;
12016 :
12017 263663 : case GT:
12018 : /* > C is equivalent to >= (C + 1); we do this for C < 0. */
12019 263663 : if (const_op < 0)
12020 : {
12021 322 : const_op += 1;
12022 322 : code = GE;
12023 : }
12024 :
12025 : /* If we are doing a > 0 comparison on a value known to have
12026 : a zero sign bit, we can replace this with != 0. */
12027 263341 : else if (const_op == 0
12028 133717 : && is_a <scalar_int_mode> (mode, &int_mode)
12029 133717 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12030 397058 : && (nonzero_bits (op0, int_mode)
12031 133717 : & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12032 133717 : == 0)
12033 : code = NE;
12034 : break;
12035 :
12036 98640 : case LTU:
12037 : /* < C is equivalent to <= (C - 1). */
12038 98640 : if (const_op > 0)
12039 : {
12040 88973 : const_op -= 1;
12041 88973 : code = LEU;
12042 : /* ... fall through ... */
12043 88973 : gcc_fallthrough ();
12044 : }
12045 : /* (unsigned) < 0x80000000 is equivalent to >= 0. */
12046 9667 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12047 9667 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12048 8894 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12049 8894 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12050 : {
12051 : const_op = 0;
12052 : code = GE;
12053 : break;
12054 : }
12055 : else
12056 : break;
12057 :
12058 709219 : case LEU:
12059 : /* unsigned <= 0 is equivalent to == 0 */
12060 709219 : if (const_op == 0)
12061 : code = EQ;
12062 : /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
12063 708761 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12064 708761 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12065 706820 : && ((unsigned HOST_WIDE_INT) const_op
12066 : == ((HOST_WIDE_INT_1U
12067 706820 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12068 : {
12069 : const_op = 0;
12070 : code = GE;
12071 : }
12072 : break;
12073 :
12074 32430 : case GEU:
12075 : /* >= C is equivalent to > (C - 1). */
12076 32430 : if (const_op > 1)
12077 : {
12078 23738 : const_op -= 1;
12079 23738 : code = GTU;
12080 : /* ... fall through ... */
12081 23738 : gcc_fallthrough ();
12082 : }
12083 :
12084 : /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12085 8692 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12086 8692 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12087 7432 : && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12088 7432 : == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12089 : {
12090 : const_op = 0;
12091 : code = LT;
12092 : break;
12093 : }
12094 : else
12095 : break;
12096 :
12097 533249 : case GTU:
12098 : /* unsigned > 0 is equivalent to != 0 */
12099 533249 : if (const_op == 0)
12100 : code = NE;
12101 : /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12102 533249 : else if (is_a <scalar_int_mode> (mode, &int_mode)
12103 533249 : && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12104 532070 : && ((unsigned HOST_WIDE_INT) const_op
12105 : == (HOST_WIDE_INT_1U
12106 532070 : << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12107 : {
12108 : const_op = 0;
12109 : code = LT;
12110 : }
12111 : break;
12112 :
12113 : default:
12114 : break;
12115 : }
12116 :
12117 : /* Narrow non-symmetric comparison of memory and constant as e.g.
12118 : x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12119 : significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
12120 : x0 >= 0x40. */
12121 15481757 : if ((code == LEU || code == LTU || code == GEU || code == GTU)
12122 1257174 : && is_a <scalar_int_mode> (GET_MODE (op0), &int_mode)
12123 1257141 : && HWI_COMPUTABLE_MODE_P (int_mode)
12124 1251988 : && MEM_P (op0)
12125 82909 : && !MEM_VOLATILE_P (op0)
12126 : /* The optimization makes only sense for constants which are big enough
12127 : so that we have a chance to chop off something at all. */
12128 82044 : && ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12129 : /* Ensure that we do not overflow during normalization. */
12130 21875 : && (code != GTU
12131 3878 : || ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12132 : < HOST_WIDE_INT_M1U)
12133 16229950 : && trunc_int_for_mode (const_op, int_mode) == const_op)
12134 : {
12135 21875 : unsigned HOST_WIDE_INT n
12136 21875 : = (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12137 21875 : enum rtx_code adjusted_code;
12138 :
12139 : /* Normalize code to either LEU or GEU. */
12140 21875 : if (code == LTU)
12141 : {
12142 116 : --n;
12143 116 : adjusted_code = LEU;
12144 : }
12145 21759 : else if (code == GTU)
12146 : {
12147 3878 : ++n;
12148 3878 : adjusted_code = GEU;
12149 : }
12150 : else
12151 : adjusted_code = code;
12152 :
12153 21875 : scalar_int_mode narrow_mode_iter;
12154 67905 : FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12155 : {
12156 46693 : unsigned nbits = GET_MODE_PRECISION (int_mode)
12157 46693 : - GET_MODE_PRECISION (narrow_mode_iter);
12158 46693 : unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12159 46693 : unsigned HOST_WIDE_INT lower_bits = n & mask;
12160 46693 : if ((adjusted_code == LEU && lower_bits == mask)
12161 46437 : || (adjusted_code == GEU && lower_bits == 0))
12162 : {
12163 663 : n >>= nbits;
12164 663 : break;
12165 : }
12166 : }
12167 :
12168 21875 : if (narrow_mode_iter < int_mode)
12169 : {
12170 663 : if (dump_file && (dump_flags & TDF_DETAILS))
12171 : {
12172 12 : fprintf (
12173 : dump_file, "narrow comparison from mode %s to %s: (MEM %s "
12174 : HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12175 12 : HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12176 12 : GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12177 12 : (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12178 12 : GET_RTX_NAME (adjusted_code), n);
12179 : }
12180 663 : poly_int64 offset = (BYTES_BIG_ENDIAN
12181 663 : ? 0
12182 663 : : (GET_MODE_SIZE (int_mode)
12183 663 : - GET_MODE_SIZE (narrow_mode_iter)));
12184 663 : *pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12185 663 : *pop1 = gen_int_mode (n, narrow_mode_iter);
12186 663 : return adjusted_code;
12187 : }
12188 : }
12189 :
12190 16207412 : *pop1 = GEN_INT (const_op);
12191 16207412 : return code;
12192 : }
12193 :
12194 : /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12195 : comparison code that will be tested.
12196 :
12197 : The result is a possibly different comparison code to use. *POP0 and
12198 : *POP1 may be updated.
12199 :
12200 : It is possible that we might detect that a comparison is either always
12201 : true or always false. However, we do not perform general constant
12202 : folding in combine, so this knowledge isn't useful. Such tautologies
12203 : should have been detected earlier. Hence we ignore all such cases. */
12204 :
12205 : static enum rtx_code
12206 24596384 : simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12207 : {
12208 24596384 : rtx op0 = *pop0;
12209 24596384 : rtx op1 = *pop1;
12210 24596384 : rtx tem, tem1;
12211 24596384 : int i;
12212 24596384 : scalar_int_mode mode, inner_mode, tmode;
12213 24596384 : opt_scalar_int_mode tmode_iter;
12214 :
12215 : /* Try a few ways of applying the same transformation to both operands. */
12216 24596626 : while (1)
12217 : {
12218 : /* The test below this one won't handle SIGN_EXTENDs on these machines,
12219 : so check specially. */
12220 24596626 : if (!WORD_REGISTER_OPERATIONS
12221 24596626 : && code != GTU && code != GEU && code != LTU && code != LEU
12222 21361993 : && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12223 1456 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12224 1095 : && GET_CODE (XEXP (op1, 0)) == ASHIFT
12225 725 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12226 724 : && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12227 724 : && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12228 : && (is_a <scalar_int_mode>
12229 724 : (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12230 724 : && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12231 724 : && CONST_INT_P (XEXP (op0, 1))
12232 724 : && XEXP (op0, 1) == XEXP (op1, 1)
12233 91 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12234 91 : && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12235 91 : && (INTVAL (XEXP (op0, 1))
12236 91 : == (GET_MODE_PRECISION (mode)
12237 91 : - GET_MODE_PRECISION (inner_mode))))
12238 : {
12239 91 : op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12240 91 : op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12241 : }
12242 :
12243 : /* If both operands are the same constant shift, see if we can ignore the
12244 : shift. We can if the shift is a rotate or if the bits shifted out of
12245 : this shift are known to be zero for both inputs and if the type of
12246 : comparison is compatible with the shift. */
12247 24596626 : if (GET_CODE (op0) == GET_CODE (op1)
12248 3572885 : && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12249 3216218 : && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12250 3216218 : || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12251 668 : && (code != GT && code != LT && code != GE && code != LE))
12252 3215602 : || (GET_CODE (op0) == ASHIFTRT
12253 1407 : && (code != GTU && code != LTU
12254 1399 : && code != GEU && code != LEU)))
12255 1978 : && CONST_INT_P (XEXP (op0, 1))
12256 1952 : && INTVAL (XEXP (op0, 1)) >= 0
12257 1952 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12258 24598578 : && XEXP (op0, 1) == XEXP (op1, 1))
12259 : {
12260 878 : machine_mode mode = GET_MODE (op0);
12261 878 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12262 878 : int shift_count = INTVAL (XEXP (op0, 1));
12263 :
12264 878 : if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12265 477 : mask &= (mask >> shift_count) << shift_count;
12266 401 : else if (GET_CODE (op0) == ASHIFT)
12267 401 : mask = (mask & (mask << shift_count)) >> shift_count;
12268 :
12269 878 : if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12270 878 : && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12271 81 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12272 : else
12273 : break;
12274 : }
12275 :
12276 : /* If both operands are AND's of a paradoxical SUBREG by constant, the
12277 : SUBREGs are of the same mode, and, in both cases, the AND would
12278 : be redundant if the comparison was done in the narrower mode,
12279 : do the comparison in the narrower mode (e.g., we are AND'ing with 1
12280 : and the operand's possibly nonzero bits are 0xffffff01; in that case
12281 : if we only care about QImode, we don't need the AND). This case
12282 : occurs if the output mode of an scc insn is not SImode and
12283 : STORE_FLAG_VALUE == 1 (e.g., the 386).
12284 :
12285 : Similarly, check for a case where the AND's are ZERO_EXTEND
12286 : operations from some narrower mode even though a SUBREG is not
12287 : present. */
12288 :
12289 24595748 : else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12290 2592 : && CONST_INT_P (XEXP (op0, 1))
12291 2510 : && CONST_INT_P (XEXP (op1, 1)))
12292 : {
12293 2468 : rtx inner_op0 = XEXP (op0, 0);
12294 2468 : rtx inner_op1 = XEXP (op1, 0);
12295 2468 : HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12296 2468 : HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12297 2468 : bool changed = false;
12298 :
12299 2468 : if (paradoxical_subreg_p (inner_op0)
12300 1021 : && GET_CODE (inner_op1) == SUBREG
12301 479 : && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12302 479 : && (GET_MODE (SUBREG_REG (inner_op0))
12303 479 : == GET_MODE (SUBREG_REG (inner_op1)))
12304 195 : && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12305 : GET_MODE (SUBREG_REG (inner_op0)))) == 0
12306 1705 : && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12307 125 : GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12308 : {
12309 115 : op0 = SUBREG_REG (inner_op0);
12310 115 : op1 = SUBREG_REG (inner_op1);
12311 :
12312 : /* The resulting comparison is always unsigned since we masked
12313 : off the original sign bit. */
12314 115 : code = unsigned_condition (code);
12315 :
12316 115 : changed = true;
12317 : }
12318 :
12319 2353 : else if (c0 == c1)
12320 5066 : FOR_EACH_MODE_UNTIL (tmode,
12321 : as_a <scalar_int_mode> (GET_MODE (op0)))
12322 3101 : if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12323 : {
12324 35 : op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12325 35 : op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12326 35 : code = unsigned_condition (code);
12327 35 : changed = true;
12328 35 : break;
12329 : }
12330 :
12331 2115 : if (! changed)
12332 : break;
12333 : }
12334 :
12335 : /* If both operands are NOT, we can strip off the outer operation
12336 : and adjust the comparison code for swapped operands; similarly for
12337 : NEG, except that this must be an equality comparison. */
12338 24593280 : else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12339 24593280 : || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12340 11 : && (code == EQ || code == NE)))
12341 11 : op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12342 :
12343 : else
12344 : break;
12345 : }
12346 :
12347 : /* If the first operand is a constant, swap the operands and adjust the
12348 : comparison code appropriately, but don't do this if the second operand
12349 : is already a constant integer. */
12350 24596384 : if (swap_commutative_operands_p (op0, op1))
12351 : {
12352 1546383 : std::swap (op0, op1);
12353 1546383 : code = swap_condition (code);
12354 : }
12355 :
12356 : /* We now enter a loop during which we will try to simplify the comparison.
12357 : For the most part, we only are concerned with comparisons with zero,
12358 : but some things may really be comparisons with zero but not start
12359 : out looking that way. */
12360 :
12361 25724579 : while (CONST_INT_P (op1))
12362 : {
12363 16709931 : machine_mode raw_mode = GET_MODE (op0);
12364 16709931 : scalar_int_mode int_mode;
12365 16709931 : int equality_comparison_p;
12366 16709931 : int sign_bit_comparison_p;
12367 16709931 : int unsigned_comparison_p;
12368 16709931 : HOST_WIDE_INT const_op;
12369 :
12370 : /* We only want to handle integral modes. This catches VOIDmode,
12371 : CCmode, and the floating-point modes. An exception is that we
12372 : can handle VOIDmode if OP0 is a COMPARE or a comparison
12373 : operation. */
12374 :
12375 16709931 : if (GET_MODE_CLASS (raw_mode) != MODE_INT
12376 1725012 : && ! (raw_mode == VOIDmode
12377 400758 : && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12378 : break;
12379 :
12380 : /* Try to simplify the compare to constant, possibly changing the
12381 : comparison op, and/or changing op1 to zero. */
12382 15385647 : code = simplify_compare_const (code, raw_mode, &op0, &op1);
12383 15385647 : const_op = INTVAL (op1);
12384 :
12385 : /* Compute some predicates to simplify code below. */
12386 :
12387 15385647 : equality_comparison_p = (code == EQ || code == NE);
12388 15385647 : sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12389 15385647 : unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12390 15385647 : || code == GEU);
12391 :
12392 : /* If this is a sign bit comparison and we can do arithmetic in
12393 : MODE, say that we will only be needing the sign bit of OP0. */
12394 15385647 : if (sign_bit_comparison_p
12395 459590 : && is_a <scalar_int_mode> (raw_mode, &int_mode)
12396 15845237 : && HWI_COMPUTABLE_MODE_P (int_mode))
12397 459198 : op0 = force_to_mode (op0, int_mode,
12398 : HOST_WIDE_INT_1U
12399 459198 : << (GET_MODE_PRECISION (int_mode) - 1), false);
12400 :
12401 15385647 : if (COMPARISON_P (op0))
12402 : {
12403 : /* We can't do anything if OP0 is a condition code value, rather
12404 : than an actual data value. */
12405 726529 : if (const_op != 0
12406 726529 : || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12407 : break;
12408 :
12409 : /* Get the two operands being compared. */
12410 138626 : if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12411 0 : tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12412 : else
12413 138626 : tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12414 :
12415 : /* Check for the cases where we simply want the result of the
12416 : earlier test or the opposite of that result. */
12417 138626 : if (code == NE || code == EQ
12418 138626 : || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12419 0 : && (code == LT || code == GE)))
12420 : {
12421 138626 : enum rtx_code new_code;
12422 138626 : if (code == LT || code == NE)
12423 138626 : new_code = GET_CODE (op0);
12424 : else
12425 0 : new_code = reversed_comparison_code (op0, NULL);
12426 :
12427 138626 : if (new_code != UNKNOWN)
12428 : {
12429 138626 : code = new_code;
12430 138626 : op0 = tem;
12431 138626 : op1 = tem1;
12432 1128195 : continue;
12433 : }
12434 : }
12435 : break;
12436 : }
12437 :
12438 14659118 : if (raw_mode == VOIDmode)
12439 : break;
12440 14659118 : scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12441 :
12442 : /* Now try cases based on the opcode of OP0. If none of the cases
12443 : does a "continue", we exit this loop immediately after the
12444 : switch. */
12445 :
12446 14659118 : unsigned int mode_width = GET_MODE_PRECISION (mode);
12447 14659118 : unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12448 14659118 : switch (GET_CODE (op0))
12449 : {
12450 388036 : case ZERO_EXTRACT:
12451 : /* If we are extracting a single bit from a variable position in
12452 : a constant that has only a single bit set and are comparing it
12453 : with zero, we can convert this into an equality comparison
12454 : between the position and the location of the single bit. */
12455 : /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12456 : have already reduced the shift count modulo the word size. */
12457 388036 : if (!SHIFT_COUNT_TRUNCATED
12458 388036 : && CONST_INT_P (XEXP (op0, 0))
12459 9097 : && XEXP (op0, 1) == const1_rtx
12460 9079 : && equality_comparison_p && const_op == 0
12461 397115 : && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12462 : {
12463 0 : if (BITS_BIG_ENDIAN)
12464 : i = BITS_PER_WORD - 1 - i;
12465 :
12466 0 : op0 = XEXP (op0, 2);
12467 0 : op1 = GEN_INT (i);
12468 0 : const_op = i;
12469 :
12470 : /* Result is nonzero iff shift count is equal to I. */
12471 0 : code = reverse_condition (code);
12472 0 : continue;
12473 : }
12474 :
12475 : /* fall through */
12476 :
12477 388040 : case SIGN_EXTRACT:
12478 388040 : tem = expand_compound_operation (op0);
12479 388040 : if (tem != op0)
12480 : {
12481 355652 : op0 = tem;
12482 355652 : continue;
12483 : }
12484 : break;
12485 :
12486 28713 : case NOT:
12487 : /* If testing for equality, we can take the NOT of the constant. */
12488 40964 : if (equality_comparison_p
12489 28713 : && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12490 : {
12491 12251 : op0 = XEXP (op0, 0);
12492 12251 : op1 = tem;
12493 12251 : continue;
12494 : }
12495 :
12496 : /* If just looking at the sign bit, reverse the sense of the
12497 : comparison. */
12498 16462 : if (sign_bit_comparison_p)
12499 : {
12500 16114 : op0 = XEXP (op0, 0);
12501 16114 : code = (code == GE ? LT : GE);
12502 16114 : continue;
12503 : }
12504 : break;
12505 :
12506 246680 : case NEG:
12507 : /* If testing for equality, we can take the NEG of the constant. */
12508 489767 : if (equality_comparison_p
12509 246680 : && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12510 : {
12511 243087 : op0 = XEXP (op0, 0);
12512 243087 : op1 = tem;
12513 243087 : continue;
12514 : }
12515 :
12516 : /* The remaining cases only apply to comparisons with zero. */
12517 3593 : if (const_op != 0)
12518 : break;
12519 :
12520 : /* When X is ABS or is known positive,
12521 : (neg X) is < 0 if and only if X != 0. */
12522 :
12523 3007 : if (sign_bit_comparison_p
12524 2969 : && (GET_CODE (XEXP (op0, 0)) == ABS
12525 2962 : || (mode_width <= HOST_BITS_PER_WIDE_INT
12526 2962 : && (nonzero_bits (XEXP (op0, 0), mode)
12527 2962 : & (HOST_WIDE_INT_1U << (mode_width - 1)))
12528 2962 : == 0)))
12529 : {
12530 38 : op0 = XEXP (op0, 0);
12531 38 : code = (code == LT ? NE : EQ);
12532 38 : continue;
12533 : }
12534 :
12535 : /* If we have NEG of something whose two high-order bits are the
12536 : same, we know that "(-a) < 0" is equivalent to "a > 0". */
12537 2931 : if (num_sign_bit_copies (op0, mode) >= 2)
12538 : {
12539 22 : op0 = XEXP (op0, 0);
12540 22 : code = swap_condition (code);
12541 22 : continue;
12542 : }
12543 : break;
12544 :
12545 146 : case ROTATE:
12546 : /* If we are testing equality and our count is a constant, we
12547 : can perform the inverse operation on our RHS. */
12548 146 : if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12549 146 : && (tem = simplify_binary_operation (ROTATERT, mode,
12550 : op1, XEXP (op0, 1))) != 0)
12551 : {
12552 0 : op0 = XEXP (op0, 0);
12553 0 : op1 = tem;
12554 0 : continue;
12555 : }
12556 :
12557 : /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12558 : a particular bit. Convert it to an AND of a constant of that
12559 : bit. This will be converted into a ZERO_EXTRACT. */
12560 146 : if (const_op == 0 && sign_bit_comparison_p
12561 0 : && CONST_INT_P (XEXP (op0, 1))
12562 0 : && mode_width <= HOST_BITS_PER_WIDE_INT
12563 0 : && UINTVAL (XEXP (op0, 1)) < mode_width)
12564 : {
12565 0 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12566 : (HOST_WIDE_INT_1U
12567 : << (mode_width - 1
12568 0 : - INTVAL (XEXP (op0, 1)))));
12569 0 : code = (code == LT ? NE : EQ);
12570 0 : continue;
12571 : }
12572 :
12573 : /* Fall through. */
12574 :
12575 1554 : case ABS:
12576 : /* ABS is ignorable inside an equality comparison with zero. */
12577 1554 : if (const_op == 0 && equality_comparison_p)
12578 : {
12579 1 : op0 = XEXP (op0, 0);
12580 1 : continue;
12581 : }
12582 : break;
12583 :
12584 1764 : case SIGN_EXTEND:
12585 : /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12586 : (compare FOO CONST) if CONST fits in FOO's mode and we
12587 : are either testing inequality or have an unsigned
12588 : comparison with ZERO_EXTEND or a signed comparison with
12589 : SIGN_EXTEND. But don't do it if we don't have a compare
12590 : insn of the given mode, since we'd have to revert it
12591 : later on, and then we wouldn't know whether to sign- or
12592 : zero-extend. */
12593 1764 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12594 1764 : && ! unsigned_comparison_p
12595 996 : && HWI_COMPUTABLE_MODE_P (mode)
12596 996 : && trunc_int_for_mode (const_op, mode) == const_op
12597 996 : && have_insn_for (COMPARE, mode))
12598 : {
12599 996 : op0 = XEXP (op0, 0);
12600 996 : continue;
12601 : }
12602 : break;
12603 :
12604 491521 : case SUBREG:
12605 : /* Check for the case where we are comparing A - C1 with C2, that is
12606 :
12607 : (subreg:MODE (plus (A) (-C1))) op (C2)
12608 :
12609 : with C1 a constant, and try to lift the SUBREG, i.e. to do the
12610 : comparison in the wider mode. One of the following two conditions
12611 : must be true in order for this to be valid:
12612 :
12613 : 1. The mode extension results in the same bit pattern being added
12614 : on both sides and the comparison is equality or unsigned. As
12615 : C2 has been truncated to fit in MODE, the pattern can only be
12616 : all 0s or all 1s.
12617 :
12618 : 2. The mode extension results in the sign bit being copied on
12619 : each side.
12620 :
12621 : The difficulty here is that we have predicates for A but not for
12622 : (A - C1) so we need to check that C1 is within proper bounds so
12623 : as to perturb A as little as possible. */
12624 :
12625 491521 : if (mode_width <= HOST_BITS_PER_WIDE_INT
12626 491445 : && subreg_lowpart_p (op0)
12627 460691 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12628 : &inner_mode)
12629 458576 : && GET_MODE_PRECISION (inner_mode) > mode_width
12630 458576 : && GET_CODE (SUBREG_REG (op0)) == PLUS
12631 491521 : && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12632 : {
12633 0 : rtx a = XEXP (SUBREG_REG (op0), 0);
12634 0 : HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12635 :
12636 0 : if ((c1 > 0
12637 0 : && (unsigned HOST_WIDE_INT) c1
12638 0 : < HOST_WIDE_INT_1U << (mode_width - 1)
12639 0 : && (equality_comparison_p || unsigned_comparison_p)
12640 : /* (A - C1) zero-extends if it is positive and sign-extends
12641 : if it is negative, C2 both zero- and sign-extends. */
12642 0 : && (((nonzero_bits (a, inner_mode)
12643 0 : & ~GET_MODE_MASK (mode)) == 0
12644 0 : && const_op >= 0)
12645 : /* (A - C1) sign-extends if it is positive and 1-extends
12646 : if it is negative, C2 both sign- and 1-extends. */
12647 0 : || (num_sign_bit_copies (a, inner_mode)
12648 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12649 0 : - mode_width)
12650 0 : && const_op < 0)))
12651 0 : || ((unsigned HOST_WIDE_INT) c1
12652 0 : < HOST_WIDE_INT_1U << (mode_width - 2)
12653 : /* (A - C1) always sign-extends, like C2. */
12654 0 : && num_sign_bit_copies (a, inner_mode)
12655 0 : > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12656 0 : - (mode_width - 1))))
12657 : {
12658 0 : op0 = SUBREG_REG (op0);
12659 0 : continue;
12660 : }
12661 : }
12662 :
12663 : /* If the inner mode is narrower and we are extracting the low part,
12664 : we can treat the SUBREG as if it were a ZERO_EXTEND ... */
12665 491521 : if (paradoxical_subreg_p (op0))
12666 : {
12667 : if (WORD_REGISTER_OPERATIONS
12668 : && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12669 : &inner_mode)
12670 : && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD
12671 : /* On WORD_REGISTER_OPERATIONS targets the bits
12672 : beyond sub_mode aren't considered undefined,
12673 : so optimize only if it is a MEM load when MEM loads
12674 : zero extend, because then the upper bits are all zero. */
12675 : && !(MEM_P (SUBREG_REG (op0))
12676 : && load_extend_op (inner_mode) == ZERO_EXTEND))
12677 : break;
12678 : /* FALLTHROUGH to case ZERO_EXTEND */
12679 : }
12680 491521 : else if (subreg_lowpart_p (op0)
12681 460767 : && GET_MODE_CLASS (mode) == MODE_INT
12682 460767 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12683 458576 : && (code == NE || code == EQ)
12684 322681 : && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12685 316746 : && !paradoxical_subreg_p (op0)
12686 808267 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12687 316746 : & ~GET_MODE_MASK (mode)) == 0)
12688 : {
12689 : /* Remove outer subregs that don't do anything. */
12690 63146 : tem = gen_lowpart (inner_mode, op1);
12691 :
12692 63146 : if ((nonzero_bits (tem, inner_mode)
12693 63146 : & ~GET_MODE_MASK (mode)) == 0)
12694 : {
12695 62478 : op0 = SUBREG_REG (op0);
12696 62478 : op1 = tem;
12697 62478 : continue;
12698 : }
12699 : break;
12700 : }
12701 : else
12702 : break;
12703 :
12704 : /* FALLTHROUGH */
12705 :
12706 42073 : case ZERO_EXTEND:
12707 42073 : if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12708 42073 : && (unsigned_comparison_p || equality_comparison_p)
12709 42035 : && HWI_COMPUTABLE_MODE_P (mode)
12710 42035 : && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12711 42035 : && const_op >= 0
12712 42026 : && have_insn_for (COMPARE, mode))
12713 : {
12714 42026 : op0 = XEXP (op0, 0);
12715 42026 : continue;
12716 : }
12717 : break;
12718 :
12719 468656 : case PLUS:
12720 : /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12721 : this for equality comparisons due to pathological cases involving
12722 : overflows. */
12723 523933 : if (equality_comparison_p
12724 468656 : && (tem = simplify_binary_operation (MINUS, mode,
12725 : op1, XEXP (op0, 1))) != 0)
12726 : {
12727 55277 : op0 = XEXP (op0, 0);
12728 55277 : op1 = tem;
12729 55277 : continue;
12730 : }
12731 :
12732 : /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12733 413379 : if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12734 15293 : && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12735 : {
12736 0 : op0 = XEXP (XEXP (op0, 0), 0);
12737 0 : code = (code == LT ? EQ : NE);
12738 0 : continue;
12739 : }
12740 : break;
12741 :
12742 187334 : case MINUS:
12743 : /* We used to optimize signed comparisons against zero, but that
12744 : was incorrect. Unsigned comparisons against zero (GTU, LEU)
12745 : arrive here as equality comparisons, or (GEU, LTU) are
12746 : optimized away. No need to special-case them. */
12747 :
12748 : /* (eq (minus A B) C) -> (eq A (plus B C)) or
12749 : (eq B (minus A C)), whichever simplifies. We can only do
12750 : this for equality comparisons due to pathological cases involving
12751 : overflows. */
12752 219597 : if (equality_comparison_p
12753 187334 : && (tem = simplify_binary_operation (PLUS, mode,
12754 : XEXP (op0, 1), op1)) != 0)
12755 : {
12756 32263 : op0 = XEXP (op0, 0);
12757 32263 : op1 = tem;
12758 32263 : continue;
12759 : }
12760 :
12761 189688 : if (equality_comparison_p
12762 155071 : && (tem = simplify_binary_operation (MINUS, mode,
12763 : XEXP (op0, 0), op1)) != 0)
12764 : {
12765 34617 : op0 = XEXP (op0, 1);
12766 34617 : op1 = tem;
12767 34617 : continue;
12768 : }
12769 :
12770 : /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12771 : of bits in X minus 1, is one iff X > 0. */
12772 15749 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12773 489 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12774 489 : && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12775 120478 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12776 : {
12777 0 : op0 = XEXP (op0, 1);
12778 0 : code = (code == GE ? LE : GT);
12779 0 : continue;
12780 : }
12781 : break;
12782 :
12783 8971 : case XOR:
12784 : /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12785 : if C is zero or B is a constant. */
12786 8987 : if (equality_comparison_p
12787 8971 : && (tem = simplify_binary_operation (XOR, mode,
12788 : XEXP (op0, 1), op1)) != 0)
12789 : {
12790 16 : op0 = XEXP (op0, 0);
12791 16 : op1 = tem;
12792 16 : continue;
12793 : }
12794 : break;
12795 :
12796 :
12797 394452 : case IOR:
12798 : /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12799 : iff X <= 0. */
12800 7510 : if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12801 1246 : && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12802 394500 : && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12803 : {
12804 48 : op0 = XEXP (op0, 1);
12805 48 : code = (code == GE ? GT : LE);
12806 48 : continue;
12807 : }
12808 : break;
12809 :
12810 1686070 : case AND:
12811 : /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12812 : will be converted to a ZERO_EXTRACT later. */
12813 1686070 : if (const_op == 0 && equality_comparison_p
12814 1569025 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12815 60929 : && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12816 : {
12817 6839 : op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12818 : XEXP (XEXP (op0, 0), 1));
12819 6839 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12820 6839 : continue;
12821 : }
12822 :
12823 : /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12824 : zero and X is a comparison and C1 and C2 describe only bits set
12825 : in STORE_FLAG_VALUE, we can compare with X. */
12826 1679231 : if (const_op == 0 && equality_comparison_p
12827 1562186 : && mode_width <= HOST_BITS_PER_WIDE_INT
12828 1558291 : && CONST_INT_P (XEXP (op0, 1))
12829 1204210 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12830 509232 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12831 495543 : && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12832 495543 : && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12833 : {
12834 495543 : mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12835 495543 : << INTVAL (XEXP (XEXP (op0, 0), 1)));
12836 495543 : if ((~STORE_FLAG_VALUE & mask) == 0
12837 495543 : && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12838 0 : || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12839 0 : && COMPARISON_P (tem))))
12840 : {
12841 0 : op0 = XEXP (XEXP (op0, 0), 0);
12842 0 : continue;
12843 : }
12844 : }
12845 :
12846 : /* If we are doing an equality comparison of an AND of a bit equal
12847 : to the sign bit, replace this with a LT or GE comparison of
12848 : the underlying value. */
12849 1679791 : if (equality_comparison_p
12850 : && const_op == 0
12851 1562186 : && CONST_INT_P (XEXP (op0, 1))
12852 1204521 : && mode_width <= HOST_BITS_PER_WIDE_INT
12853 1679231 : && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12854 1204210 : == HOST_WIDE_INT_1U << (mode_width - 1)))
12855 : {
12856 560 : op0 = XEXP (op0, 0);
12857 560 : code = (code == EQ ? GE : LT);
12858 560 : continue;
12859 : }
12860 :
12861 : /* If this AND operation is really a ZERO_EXTEND from a narrower
12862 : mode, the constant fits within that mode, and this is either an
12863 : equality or unsigned comparison, try to do this comparison in
12864 : the narrower mode.
12865 :
12866 : Note that in:
12867 :
12868 : (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12869 : -> (ne:DI (reg:SI 4) (const_int 0))
12870 :
12871 : unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12872 : known to hold a value of the required mode the
12873 : transformation is invalid. */
12874 1694710 : if ((equality_comparison_p || unsigned_comparison_p)
12875 1662782 : && CONST_INT_P (XEXP (op0, 1))
12876 3859707 : && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12877 1298337 : & GET_MODE_MASK (mode))
12878 : + 1)) >= 0
12879 898738 : && const_op >> i == 0
12880 2577409 : && int_mode_for_size (i, 1).exists (&tmode))
12881 : {
12882 16039 : op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12883 16039 : continue;
12884 : }
12885 :
12886 : /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12887 1662632 : if (const_op == 0 && equality_comparison_p
12888 1550816 : && XEXP (op0, 1) == const1_rtx
12889 676892 : && GET_CODE (XEXP (op0, 0)) == NOT)
12890 : {
12891 6246 : op0 = simplify_and_const_int (NULL_RTX, mode,
12892 : XEXP (XEXP (op0, 0), 0), 1);
12893 6246 : code = (code == NE ? EQ : NE);
12894 6246 : continue;
12895 : }
12896 :
12897 : /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12898 : (eq (and (lshiftrt X) 1) 0).
12899 : Also handle the case where (not X) is expressed using xor. */
12900 1656386 : if (const_op == 0 && equality_comparison_p
12901 1544570 : && XEXP (op0, 1) == const1_rtx
12902 670646 : && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12903 : {
12904 503378 : rtx shift_op = XEXP (XEXP (op0, 0), 0);
12905 503378 : rtx shift_count = XEXP (XEXP (op0, 0), 1);
12906 :
12907 506206 : if (GET_CODE (shift_op) == NOT
12908 503378 : || (GET_CODE (shift_op) == XOR
12909 4249 : && CONST_INT_P (XEXP (shift_op, 1))
12910 2828 : && CONST_INT_P (shift_count)
12911 2828 : && HWI_COMPUTABLE_MODE_P (mode)
12912 2828 : && (UINTVAL (XEXP (shift_op, 1))
12913 : == HOST_WIDE_INT_1U
12914 2828 : << INTVAL (shift_count))))
12915 : {
12916 2828 : op0
12917 2828 : = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12918 2828 : op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12919 2828 : code = (code == NE ? EQ : NE);
12920 2828 : continue;
12921 : }
12922 : }
12923 : break;
12924 :
12925 48629 : case ASHIFT:
12926 : /* If we have (compare (ashift FOO N) (const_int C)) and
12927 : the high order N bits of FOO (N+1 if an inequality comparison)
12928 : are known to be zero, we can do this by comparing FOO with C
12929 : shifted right N bits so long as the low-order N bits of C are
12930 : zero. */
12931 48629 : if (CONST_INT_P (XEXP (op0, 1))
12932 44863 : && INTVAL (XEXP (op0, 1)) >= 0
12933 44863 : && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12934 : < HOST_BITS_PER_WIDE_INT)
12935 44863 : && (((unsigned HOST_WIDE_INT) const_op
12936 44863 : & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12937 : - 1)) == 0)
12938 37948 : && mode_width <= HOST_BITS_PER_WIDE_INT
12939 86557 : && (nonzero_bits (XEXP (op0, 0), mode)
12940 37928 : & ~(mask >> (INTVAL (XEXP (op0, 1))
12941 37928 : + ! equality_comparison_p))) == 0)
12942 : {
12943 : /* We must perform a logical shift, not an arithmetic one,
12944 : as we want the top N bits of C to be zero. */
12945 756 : unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12946 :
12947 756 : temp >>= INTVAL (XEXP (op0, 1));
12948 756 : op1 = gen_int_mode (temp, mode);
12949 756 : op0 = XEXP (op0, 0);
12950 756 : continue;
12951 756 : }
12952 :
12953 : /* If we are doing a sign bit comparison, it means we are testing
12954 : a particular bit. Convert it to the appropriate AND. */
12955 47873 : if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12956 1672 : && mode_width <= HOST_BITS_PER_WIDE_INT)
12957 : {
12958 3344 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12959 : (HOST_WIDE_INT_1U
12960 : << (mode_width - 1
12961 1672 : - INTVAL (XEXP (op0, 1)))));
12962 1672 : code = (code == LT ? NE : EQ);
12963 1672 : continue;
12964 : }
12965 :
12966 : /* If this an equality comparison with zero and we are shifting
12967 : the low bit to the sign bit, we can convert this to an AND of the
12968 : low-order bit. */
12969 46201 : if (const_op == 0 && equality_comparison_p
12970 15783 : && CONST_INT_P (XEXP (op0, 1))
12971 13187 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12972 : {
12973 303 : op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12974 303 : continue;
12975 : }
12976 : break;
12977 :
12978 44710 : case ASHIFTRT:
12979 : /* If this is an equality comparison with zero, we can do this
12980 : as a logical shift, which might be much simpler. */
12981 44710 : if (equality_comparison_p && const_op == 0
12982 26756 : && CONST_INT_P (XEXP (op0, 1)))
12983 : {
12984 51990 : op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12985 : XEXP (op0, 0),
12986 25995 : INTVAL (XEXP (op0, 1)));
12987 25995 : continue;
12988 : }
12989 :
12990 : /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12991 : do the comparison in a narrower mode. */
12992 23697 : if (! unsigned_comparison_p
12993 17466 : && CONST_INT_P (XEXP (op0, 1))
12994 16613 : && GET_CODE (XEXP (op0, 0)) == ASHIFT
12995 5572 : && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12996 5470 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12997 18715 : .exists (&tmode))
12998 18715 : && (((unsigned HOST_WIDE_INT) const_op
12999 4982 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13000 4982 : <= GET_MODE_MASK (tmode)))
13001 : {
13002 4982 : op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
13003 4982 : continue;
13004 : }
13005 :
13006 : /* Likewise if OP0 is a PLUS of a sign extension with a
13007 : constant, which is usually represented with the PLUS
13008 : between the shifts. */
13009 13733 : if (! unsigned_comparison_p
13010 12484 : && CONST_INT_P (XEXP (op0, 1))
13011 11631 : && GET_CODE (XEXP (op0, 0)) == PLUS
13012 54 : && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
13013 22 : && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
13014 2 : && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
13015 0 : && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13016 13733 : .exists (&tmode))
13017 13733 : && (((unsigned HOST_WIDE_INT) const_op
13018 0 : + (GET_MODE_MASK (tmode) >> 1) + 1)
13019 0 : <= GET_MODE_MASK (tmode)))
13020 : {
13021 0 : rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
13022 0 : rtx add_const = XEXP (XEXP (op0, 0), 1);
13023 0 : rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
13024 : add_const, XEXP (op0, 1));
13025 :
13026 0 : op0 = simplify_gen_binary (PLUS, tmode,
13027 0 : gen_lowpart (tmode, inner),
13028 : new_const);
13029 0 : continue;
13030 0 : }
13031 :
13032 : /* FALLTHROUGH */
13033 133508 : case LSHIFTRT:
13034 : /* If we have (compare (xshiftrt FOO N) (const_int C)) and
13035 : the low order N bits of FOO are known to be zero, we can do this
13036 : by comparing FOO with C shifted left N bits so long as no
13037 : overflow occurs. Even if the low order N bits of FOO aren't known
13038 : to be zero, if the comparison is >= or < we can use the same
13039 : optimization and for > or <= by setting all the low
13040 : order N bits in the comparison constant. */
13041 133508 : if (CONST_INT_P (XEXP (op0, 1))
13042 128706 : && INTVAL (XEXP (op0, 1)) > 0
13043 128706 : && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
13044 128346 : && mode_width <= HOST_BITS_PER_WIDE_INT
13045 133508 : && (((unsigned HOST_WIDE_INT) const_op
13046 255178 : + (GET_CODE (op0) != LSHIFTRT
13047 127589 : ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
13048 : + 1)
13049 : : 0))
13050 127589 : <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
13051 : {
13052 127412 : unsigned HOST_WIDE_INT low_bits
13053 127412 : = (nonzero_bits (XEXP (op0, 0), mode)
13054 127412 : & ((HOST_WIDE_INT_1U
13055 127412 : << INTVAL (XEXP (op0, 1))) - 1));
13056 127412 : if (low_bits == 0 || !equality_comparison_p)
13057 : {
13058 : /* If the shift was logical, then we must make the condition
13059 : unsigned. */
13060 19246 : if (GET_CODE (op0) == LSHIFTRT)
13061 16566 : code = unsigned_condition (code);
13062 :
13063 19246 : const_op = (unsigned HOST_WIDE_INT) const_op
13064 19246 : << INTVAL (XEXP (op0, 1));
13065 19246 : if (low_bits != 0
13066 3015 : && (code == GT || code == GTU
13067 1029 : || code == LE || code == LEU))
13068 2947 : const_op
13069 2947 : |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
13070 19246 : op1 = GEN_INT (const_op);
13071 19246 : op0 = XEXP (op0, 0);
13072 19246 : continue;
13073 : }
13074 : }
13075 :
13076 : /* If we are using this shift to extract just the sign bit, we
13077 : can replace this with an LT or GE comparison. */
13078 114262 : if (const_op == 0
13079 98319 : && (equality_comparison_p || sign_bit_comparison_p)
13080 98283 : && CONST_INT_P (XEXP (op0, 1))
13081 93808 : && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13082 : {
13083 49217 : op0 = XEXP (op0, 0);
13084 49217 : code = (code == NE || code == GT ? LT : GE);
13085 49217 : continue;
13086 : }
13087 : break;
13088 :
13089 : default:
13090 : break;
13091 : }
13092 :
13093 : break;
13094 : }
13095 :
13096 : /* Now make any compound operations involved in this comparison. Then,
13097 : check for an outermost SUBREG on OP0 that is not doing anything or is
13098 : paradoxical. The latter transformation must only be performed when
13099 : it is known that the "extra" bits will be the same in op0 and op1 or
13100 : that they don't matter. There are three cases to consider:
13101 :
13102 : 1. SUBREG_REG (op0) is a register. In this case the bits are don't
13103 : care bits and we can assume they have any convenient value. So
13104 : making the transformation is safe.
13105 :
13106 : 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13107 : In this case the upper bits of op0 are undefined. We should not make
13108 : the simplification in that case as we do not know the contents of
13109 : those bits.
13110 :
13111 : 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13112 : In that case we know those bits are zeros or ones. We must also be
13113 : sure that they are the same as the upper bits of op1.
13114 :
13115 : We can never remove a SUBREG for a non-equality comparison because
13116 : the sign bit is in a different place in the underlying object. */
13117 :
13118 24596384 : rtx_code op0_mco_code = SET;
13119 24596384 : if (op1 == const0_rtx)
13120 11663165 : op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13121 :
13122 24596384 : op0 = make_compound_operation (op0, op0_mco_code);
13123 24596384 : op1 = make_compound_operation (op1, SET);
13124 :
13125 613730 : if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13126 581976 : && is_int_mode (GET_MODE (op0), &mode)
13127 551460 : && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13128 25144078 : && (code == NE || code == EQ))
13129 : {
13130 287222 : if (paradoxical_subreg_p (op0))
13131 : {
13132 : /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13133 : implemented. */
13134 0 : if (REG_P (SUBREG_REG (op0)))
13135 : {
13136 0 : op0 = SUBREG_REG (op0);
13137 0 : op1 = gen_lowpart (inner_mode, op1);
13138 : }
13139 : }
13140 287222 : else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13141 287222 : && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13142 280255 : & ~GET_MODE_MASK (mode)) == 0)
13143 : {
13144 13962 : tem = gen_lowpart (inner_mode, op1);
13145 :
13146 13962 : if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13147 4704 : op0 = SUBREG_REG (op0), op1 = tem;
13148 : }
13149 : }
13150 :
13151 : /* We now do the opposite procedure: Some machines don't have compare
13152 : insns in all modes. If OP0's mode is an integer mode smaller than a
13153 : word and we can't do a compare in that mode, see if there is a larger
13154 : mode for which we can do the compare. There are a number of cases in
13155 : which we can use the wider mode. */
13156 :
13157 24596384 : if (is_int_mode (GET_MODE (op0), &mode)
13158 25282845 : && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13159 8892624 : && ! have_insn_for (COMPARE, mode))
13160 0 : FOR_EACH_WIDER_MODE (tmode_iter, mode)
13161 : {
13162 0 : tmode = tmode_iter.require ();
13163 0 : if (!HWI_COMPUTABLE_MODE_P (tmode))
13164 : break;
13165 0 : if (have_insn_for (COMPARE, tmode))
13166 : {
13167 0 : int zero_extended;
13168 :
13169 : /* If this is a test for negative, we can make an explicit
13170 : test of the sign bit. Test this first so we can use
13171 : a paradoxical subreg to extend OP0. */
13172 :
13173 0 : if (op1 == const0_rtx && (code == LT || code == GE)
13174 0 : && HWI_COMPUTABLE_MODE_P (mode))
13175 : {
13176 0 : unsigned HOST_WIDE_INT sign
13177 0 : = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13178 0 : op0 = simplify_gen_binary (AND, tmode,
13179 0 : gen_lowpart (tmode, op0),
13180 0 : gen_int_mode (sign, tmode));
13181 0 : code = (code == LT) ? NE : EQ;
13182 : break;
13183 : }
13184 :
13185 : /* If the only nonzero bits in OP0 and OP1 are those in the
13186 : narrower mode and this is an equality or unsigned comparison,
13187 : we can use the wider mode. Similarly for sign-extended
13188 : values, in which case it is true for all comparisons. */
13189 0 : zero_extended = ((code == EQ || code == NE
13190 0 : || code == GEU || code == GTU
13191 0 : || code == LEU || code == LTU)
13192 0 : && (nonzero_bits (op0, tmode)
13193 0 : & ~GET_MODE_MASK (mode)) == 0
13194 0 : && ((CONST_INT_P (op1)
13195 0 : || (nonzero_bits (op1, tmode)
13196 0 : & ~GET_MODE_MASK (mode)) == 0)));
13197 :
13198 0 : if (zero_extended
13199 0 : || ((num_sign_bit_copies (op0, tmode)
13200 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13201 0 : - GET_MODE_PRECISION (mode)))
13202 0 : && (num_sign_bit_copies (op1, tmode)
13203 0 : > (unsigned int) (GET_MODE_PRECISION (tmode)
13204 0 : - GET_MODE_PRECISION (mode)))))
13205 : {
13206 : /* If OP0 is an AND and we don't have an AND in MODE either,
13207 : make a new AND in the proper mode. */
13208 0 : if (GET_CODE (op0) == AND
13209 0 : && !have_insn_for (AND, mode))
13210 0 : op0 = simplify_gen_binary (AND, tmode,
13211 0 : gen_lowpart (tmode,
13212 : XEXP (op0, 0)),
13213 0 : gen_lowpart (tmode,
13214 : XEXP (op0, 1)));
13215 : else
13216 : {
13217 0 : if (zero_extended)
13218 : {
13219 0 : op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13220 : op0, mode);
13221 0 : op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13222 : op1, mode);
13223 : }
13224 : else
13225 : {
13226 0 : op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13227 : op0, mode);
13228 0 : op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13229 : op1, mode);
13230 : }
13231 : break;
13232 : }
13233 : }
13234 : }
13235 : }
13236 :
13237 : /* We may have changed the comparison operands. Re-canonicalize. */
13238 24596384 : if (swap_commutative_operands_p (op0, op1))
13239 : {
13240 63670 : std::swap (op0, op1);
13241 63670 : code = swap_condition (code);
13242 : }
13243 :
13244 : /* If this machine only supports a subset of valid comparisons, see if we
13245 : can convert an unsupported one into a supported one. */
13246 24596384 : target_canonicalize_comparison (&code, &op0, &op1, 0);
13247 :
13248 24596384 : *pop0 = op0;
13249 24596384 : *pop1 = op1;
13250 :
13251 24596384 : return code;
13252 : }
13253 :
13254 : /* Utility function for record_value_for_reg. Count number of
13255 : rtxs in X. */
13256 : static int
13257 2656 : count_rtxs (rtx x)
13258 : {
13259 2656 : enum rtx_code code = GET_CODE (x);
13260 2656 : const char *fmt;
13261 2656 : int i, j, ret = 1;
13262 :
13263 2656 : if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13264 2656 : || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13265 : {
13266 83 : rtx x0 = XEXP (x, 0);
13267 83 : rtx x1 = XEXP (x, 1);
13268 :
13269 83 : if (x0 == x1)
13270 0 : return 1 + 2 * count_rtxs (x0);
13271 :
13272 83 : if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13273 83 : || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13274 0 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13275 0 : return 2 + 2 * count_rtxs (x0)
13276 0 : + count_rtxs (x == XEXP (x1, 0)
13277 0 : ? XEXP (x1, 1) : XEXP (x1, 0));
13278 :
13279 83 : if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13280 83 : || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13281 0 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13282 0 : return 2 + 2 * count_rtxs (x1)
13283 0 : + count_rtxs (x == XEXP (x0, 0)
13284 0 : ? XEXP (x0, 1) : XEXP (x0, 0));
13285 : }
13286 :
13287 2656 : fmt = GET_RTX_FORMAT (code);
13288 5955 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13289 3299 : if (fmt[i] == 'e')
13290 1566 : ret += count_rtxs (XEXP (x, i));
13291 1733 : else if (fmt[i] == 'E')
13292 208 : for (j = 0; j < XVECLEN (x, i); j++)
13293 156 : ret += count_rtxs (XVECEXP (x, i, j));
13294 :
13295 : return ret;
13296 : }
13297 :
13298 : /* Utility function for following routine. Called when X is part of a value
13299 : being stored into last_set_value. Sets last_set_table_tick
13300 : for each register mentioned. Similar to mention_regs in cse.cc */
13301 :
13302 : static void
13303 235090876 : update_table_tick (rtx x)
13304 : {
13305 235784957 : enum rtx_code code = GET_CODE (x);
13306 235784957 : const char *fmt = GET_RTX_FORMAT (code);
13307 235784957 : int i, j;
13308 :
13309 235784957 : if (code == REG)
13310 : {
13311 84167542 : unsigned int regno = REGNO (x);
13312 84167542 : unsigned int endregno = END_REGNO (x);
13313 84167542 : unsigned int r;
13314 :
13315 168446012 : for (r = regno; r < endregno; r++)
13316 : {
13317 84278470 : reg_stat_type *rsp = ®_stat[r];
13318 84278470 : rsp->last_set_table_tick = label_tick;
13319 : }
13320 :
13321 : return;
13322 : }
13323 :
13324 391825181 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13325 241025865 : if (fmt[i] == 'e')
13326 : {
13327 : /* Check for identical subexpressions. If x contains
13328 : identical subexpression we only have to traverse one of
13329 : them. */
13330 139680122 : if (i == 0 && ARITHMETIC_P (x))
13331 : {
13332 : /* Note that at this point x1 has already been
13333 : processed. */
13334 52796075 : rtx x0 = XEXP (x, 0);
13335 52796075 : rtx x1 = XEXP (x, 1);
13336 :
13337 : /* If x0 and x1 are identical then there is no need to
13338 : process x0. */
13339 52796075 : if (x0 == x1)
13340 : break;
13341 :
13342 : /* If x0 is identical to a subexpression of x1 then while
13343 : processing x1, x0 has already been processed. Thus we
13344 : are done with x. */
13345 52672202 : if (ARITHMETIC_P (x1)
13346 234277 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13347 : break;
13348 :
13349 : /* If x1 is identical to a subexpression of x0 then we
13350 : still have to process the rest of x0. */
13351 52672057 : if (ARITHMETIC_P (x0)
13352 9453875 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13353 : {
13354 694081 : update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13355 694081 : break;
13356 : }
13357 : }
13358 :
13359 138862023 : update_table_tick (XEXP (x, i));
13360 : }
13361 101345743 : else if (fmt[i] == 'E')
13362 10348294 : for (j = 0; j < XVECLEN (x, i); j++)
13363 7645516 : update_table_tick (XVECEXP (x, i, j));
13364 : }
13365 :
13366 : /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13367 : are saying that the register is clobbered and we no longer know its
13368 : value. If INSN is zero, don't update reg_stat[].last_set; this is
13369 : only permitted with VALUE also zero and is used to invalidate the
13370 : register. */
13371 :
13372 : static void
13373 115862008 : record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13374 : {
13375 115862008 : unsigned int regno = REGNO (reg);
13376 115862008 : unsigned int endregno = END_REGNO (reg);
13377 115862008 : unsigned int i;
13378 115862008 : reg_stat_type *rsp;
13379 :
13380 : /* If VALUE contains REG and we have a previous value for REG, substitute
13381 : the previous value. */
13382 115862008 : if (value && insn && reg_overlap_mentioned_p (reg, value))
13383 : {
13384 6287374 : rtx tem;
13385 :
13386 : /* Set things up so get_last_value is allowed to see anything set up to
13387 : our insn. */
13388 6287374 : subst_low_luid = DF_INSN_LUID (insn);
13389 6287374 : tem = get_last_value (reg);
13390 :
13391 : /* If TEM is simply a binary operation with two CLOBBERs as operands,
13392 : it isn't going to be useful and will take a lot of time to process,
13393 : so just use the CLOBBER. */
13394 :
13395 6287374 : if (tem)
13396 : {
13397 2487764 : if (ARITHMETIC_P (tem)
13398 2253694 : && GET_CODE (XEXP (tem, 0)) == CLOBBER
13399 1101873 : && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13400 : tem = XEXP (tem, 0);
13401 2486409 : else if (count_occurrences (value, reg, 1) >= 2)
13402 : {
13403 : /* If there are two or more occurrences of REG in VALUE,
13404 : prevent the value from growing too much. */
13405 934 : if (count_rtxs (tem) > param_max_last_value_rtl)
13406 0 : tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13407 : }
13408 :
13409 2487764 : value = replace_rtx (copy_rtx (value), reg, tem);
13410 : }
13411 : }
13412 :
13413 : /* For each register modified, show we don't know its value, that
13414 : we don't know about its bitwise content, that its value has been
13415 : updated, and that we don't know the location of the death of the
13416 : register. */
13417 232080459 : for (i = regno; i < endregno; i++)
13418 : {
13419 116218451 : rsp = ®_stat[i];
13420 :
13421 116218451 : if (insn)
13422 106722026 : rsp->last_set = insn;
13423 :
13424 116218451 : rsp->last_set_value = 0;
13425 116218451 : rsp->last_set_mode = VOIDmode;
13426 116218451 : rsp->last_set_nonzero_bits = 0;
13427 116218451 : rsp->last_set_sign_bit_copies = 0;
13428 116218451 : rsp->last_death = 0;
13429 116218451 : rsp->truncated_to_mode = VOIDmode;
13430 : }
13431 :
13432 : /* Mark registers that are being referenced in this value. */
13433 115862008 : if (value)
13434 88583337 : update_table_tick (value);
13435 :
13436 : /* Now update the status of each register being set.
13437 : If someone is using this register in this block, set this register
13438 : to invalid since we will get confused between the two lives in this
13439 : basic block. This makes using this register always invalid. In cse, we
13440 : scan the table to invalidate all entries using this register, but this
13441 : is too much work for us. */
13442 :
13443 232080459 : for (i = regno; i < endregno; i++)
13444 : {
13445 116218451 : rsp = ®_stat[i];
13446 116218451 : rsp->last_set_label = label_tick;
13447 116218451 : if (!insn
13448 106722026 : || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13449 20175219 : rsp->last_set_invalid = true;
13450 : else
13451 96043232 : rsp->last_set_invalid = false;
13452 : }
13453 :
13454 : /* The value being assigned might refer to X (like in "x++;"). In that
13455 : case, we must replace it with (clobber (const_int 0)) to prevent
13456 : infinite loops. */
13457 115862008 : rsp = ®_stat[regno];
13458 115862008 : if (value && !get_last_value_validate (&value, insn, label_tick, false))
13459 : {
13460 11386065 : value = copy_rtx (value);
13461 11386065 : if (!get_last_value_validate (&value, insn, label_tick, true))
13462 0 : value = 0;
13463 : }
13464 :
13465 : /* For the main register being modified, update the value, the mode, the
13466 : nonzero bits, and the number of sign bit copies. */
13467 :
13468 115862008 : rsp->last_set_value = value;
13469 :
13470 115862008 : if (value)
13471 : {
13472 88583337 : machine_mode mode = GET_MODE (reg);
13473 88583337 : subst_low_luid = DF_INSN_LUID (insn);
13474 88583337 : rsp->last_set_mode = mode;
13475 88583337 : if (GET_MODE_CLASS (mode) == MODE_INT
13476 88583337 : && HWI_COMPUTABLE_MODE_P (mode))
13477 66818766 : mode = nonzero_bits_mode;
13478 88583337 : rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13479 88583337 : rsp->last_set_sign_bit_copies
13480 88583337 : = num_sign_bit_copies (value, GET_MODE (reg));
13481 : }
13482 115862008 : }
13483 :
13484 : /* Called via note_stores from record_dead_and_set_regs to handle one
13485 : SET or CLOBBER in an insn. DATA is the instruction in which the
13486 : set is occurring. */
13487 :
13488 : static void
13489 138506961 : record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13490 : {
13491 138506961 : rtx_insn *record_dead_insn = (rtx_insn *) data;
13492 :
13493 138506961 : if (GET_CODE (dest) == SUBREG)
13494 0 : dest = SUBREG_REG (dest);
13495 :
13496 138506961 : if (!record_dead_insn)
13497 : {
13498 4330125 : if (REG_P (dest))
13499 4330125 : record_value_for_reg (dest, NULL, NULL_RTX);
13500 : return;
13501 : }
13502 :
13503 134176836 : if (REG_P (dest))
13504 : {
13505 : /* If we are setting the whole register, we know its value. */
13506 106547474 : if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13507 88400742 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13508 : /* We can handle a SUBREG if it's the low part, but we must be
13509 : careful with paradoxical SUBREGs on RISC architectures because
13510 : we cannot strip e.g. an extension around a load and record the
13511 : naked load since the RTL middle-end considers that the upper bits
13512 : are defined according to LOAD_EXTEND_OP. */
13513 18146732 : else if (GET_CODE (setter) == SET
13514 631694 : && GET_CODE (SET_DEST (setter)) == SUBREG
13515 619236 : && SUBREG_REG (SET_DEST (setter)) == dest
13516 987205 : && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13517 : BITS_PER_WORD)
13518 18281074 : && subreg_lowpart_p (SET_DEST (setter)))
13519 : {
13520 134342 : if (WORD_REGISTER_OPERATIONS
13521 : && word_register_operation_p (SET_SRC (setter))
13522 : && paradoxical_subreg_p (SET_DEST (setter)))
13523 : record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13524 134342 : else if (!partial_subreg_p (SET_DEST (setter)))
13525 122210 : record_value_for_reg (dest, record_dead_insn,
13526 122210 : gen_lowpart (GET_MODE (dest),
13527 122210 : SET_SRC (setter)));
13528 : else
13529 : {
13530 12132 : record_value_for_reg (dest, record_dead_insn,
13531 12132 : gen_lowpart (GET_MODE (dest),
13532 12132 : SET_SRC (setter)));
13533 :
13534 12132 : unsigned HOST_WIDE_INT mask;
13535 12132 : reg_stat_type *rsp = ®_stat[REGNO (dest)];
13536 12132 : mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13537 12132 : rsp->last_set_nonzero_bits |= ~mask;
13538 12132 : rsp->last_set_sign_bit_copies = 1;
13539 : }
13540 : }
13541 : /* Otherwise show that we don't know the value. */
13542 : else
13543 18012390 : record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13544 : }
13545 27629362 : else if (MEM_P (dest)
13546 : /* Ignore pushes, they clobber nothing. */
13547 27629362 : && ! push_operand (dest, GET_MODE (dest)))
13548 14231888 : mem_last_set = DF_INSN_LUID (record_dead_insn);
13549 : }
13550 :
13551 : /* Update the records of when each REG was most recently set or killed
13552 : for the things done by INSN. This is the last thing done in processing
13553 : INSN in the combiner loop.
13554 :
13555 : We update reg_stat[], in particular fields last_set, last_set_value,
13556 : last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13557 : last_death, and also the similar information mem_last_set (which insn
13558 : most recently modified memory) and last_call_luid (which insn was the
13559 : most recent subroutine call). */
13560 :
13561 : static void
13562 181872683 : record_dead_and_set_regs (rtx_insn *insn)
13563 : {
13564 181872683 : rtx link;
13565 181872683 : unsigned int i;
13566 :
13567 322271387 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13568 : {
13569 140398704 : if (REG_NOTE_KIND (link) == REG_DEAD
13570 80215731 : && REG_P (XEXP (link, 0)))
13571 : {
13572 80215731 : unsigned int regno = REGNO (XEXP (link, 0));
13573 80215731 : unsigned int endregno = END_REGNO (XEXP (link, 0));
13574 :
13575 160636443 : for (i = regno; i < endregno; i++)
13576 : {
13577 80420712 : reg_stat_type *rsp;
13578 :
13579 80420712 : rsp = ®_stat[i];
13580 80420712 : rsp->last_death = insn;
13581 : }
13582 : }
13583 60182973 : else if (REG_NOTE_KIND (link) == REG_INC)
13584 0 : record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13585 : }
13586 :
13587 181872683 : if (CALL_P (insn))
13588 : {
13589 9713074 : HARD_REG_SET callee_clobbers
13590 9713074 : = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13591 9713074 : hard_reg_set_iterator hrsi;
13592 822385256 : EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13593 : {
13594 812672182 : reg_stat_type *rsp;
13595 :
13596 : /* ??? We could try to preserve some information from the last
13597 : set of register I if the call doesn't actually clobber
13598 : (reg:last_set_mode I), which might be true for ABIs with
13599 : partial clobbers. However, it would be difficult to
13600 : update last_set_nonzero_bits and last_sign_bit_copies
13601 : to account for the part of I that actually was clobbered.
13602 : It wouldn't help much anyway, since we rarely see this
13603 : situation before RA. */
13604 812672182 : rsp = ®_stat[i];
13605 812672182 : rsp->last_set_invalid = true;
13606 812672182 : rsp->last_set = insn;
13607 812672182 : rsp->last_set_value = 0;
13608 812672182 : rsp->last_set_mode = VOIDmode;
13609 812672182 : rsp->last_set_nonzero_bits = 0;
13610 812672182 : rsp->last_set_sign_bit_copies = 0;
13611 812672182 : rsp->last_death = 0;
13612 812672182 : rsp->truncated_to_mode = VOIDmode;
13613 : }
13614 :
13615 9713074 : last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13616 :
13617 : /* We can't combine into a call pattern. Remember, though, that
13618 : the return value register is set at this LUID. We could
13619 : still replace a register with the return value from the
13620 : wrong subroutine call! */
13621 9713074 : note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13622 : }
13623 : else
13624 172159609 : note_stores (insn, record_dead_and_set_regs_1, insn);
13625 181872683 : }
13626 :
13627 : /* If a SUBREG has the promoted bit set, it is in fact a property of the
13628 : register present in the SUBREG, so for each such SUBREG go back and
13629 : adjust nonzero and sign bit information of the registers that are
13630 : known to have some zero/sign bits set.
13631 :
13632 : This is needed because when combine blows the SUBREGs away, the
13633 : information on zero/sign bits is lost and further combines can be
13634 : missed because of that. */
13635 :
13636 : static void
13637 6091 : record_promoted_value (rtx_insn *insn, rtx subreg)
13638 : {
13639 6091 : struct insn_link *links;
13640 6091 : rtx set;
13641 6091 : unsigned int regno = REGNO (SUBREG_REG (subreg));
13642 6091 : machine_mode mode = GET_MODE (subreg);
13643 :
13644 6091 : if (!HWI_COMPUTABLE_MODE_P (mode))
13645 : return;
13646 :
13647 6824 : for (links = LOG_LINKS (insn); links;)
13648 : {
13649 6112 : reg_stat_type *rsp;
13650 :
13651 6112 : insn = links->insn;
13652 6112 : set = single_set (insn);
13653 :
13654 6112 : if (! set || !REG_P (SET_DEST (set))
13655 6108 : || REGNO (SET_DEST (set)) != regno
13656 11633 : || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13657 : {
13658 591 : links = links->next;
13659 591 : continue;
13660 : }
13661 :
13662 5521 : rsp = ®_stat[regno];
13663 5521 : if (rsp->last_set == insn)
13664 : {
13665 5521 : if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13666 5521 : rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13667 : }
13668 :
13669 5521 : if (REG_P (SET_SRC (set)))
13670 : {
13671 142 : regno = REGNO (SET_SRC (set));
13672 142 : links = LOG_LINKS (insn);
13673 : }
13674 : else
13675 : break;
13676 : }
13677 : }
13678 :
13679 : /* Check if X, a register, is known to contain a value already
13680 : truncated to MODE. In this case we can use a subreg to refer to
13681 : the truncated value even though in the generic case we would need
13682 : an explicit truncation. */
13683 :
13684 : static bool
13685 0 : reg_truncated_to_mode (machine_mode mode, const_rtx x)
13686 : {
13687 0 : reg_stat_type *rsp = ®_stat[REGNO (x)];
13688 0 : machine_mode truncated = rsp->truncated_to_mode;
13689 :
13690 0 : if (truncated == 0
13691 0 : || rsp->truncation_label < label_tick_ebb_start)
13692 : return false;
13693 0 : if (!partial_subreg_p (mode, truncated))
13694 : return true;
13695 0 : if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13696 : return true;
13697 : return false;
13698 : }
13699 :
13700 : /* If X is a hard reg or a subreg record the mode that the register is
13701 : accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13702 : able to turn a truncate into a subreg using this information. Return true
13703 : if traversing X is complete. */
13704 :
13705 : static bool
13706 203123958 : record_truncated_value (rtx x)
13707 : {
13708 203123958 : machine_mode truncated_mode;
13709 203123958 : reg_stat_type *rsp;
13710 :
13711 203123958 : if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13712 : {
13713 1876345 : machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13714 1876345 : truncated_mode = GET_MODE (x);
13715 :
13716 1876345 : if (!partial_subreg_p (truncated_mode, original_mode))
13717 : return true;
13718 :
13719 1116502 : truncated_mode = GET_MODE (x);
13720 1116502 : if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13721 : return true;
13722 :
13723 0 : x = SUBREG_REG (x);
13724 0 : }
13725 : /* ??? For hard-regs we now record everything. We might be able to
13726 : optimize this using last_set_mode. */
13727 201247613 : else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13728 21363090 : truncated_mode = GET_MODE (x);
13729 : else
13730 : return false;
13731 :
13732 21363090 : rsp = ®_stat[REGNO (x)];
13733 21363090 : if (rsp->truncated_to_mode == 0
13734 9920628 : || rsp->truncation_label < label_tick_ebb_start
13735 29995244 : || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13736 : {
13737 12731578 : rsp->truncated_to_mode = truncated_mode;
13738 12731578 : rsp->truncation_label = label_tick;
13739 : }
13740 :
13741 : return true;
13742 : }
13743 :
13744 : /* Callback for note_uses. Find hardregs and subregs of pseudos and
13745 : the modes they are used in. This can help turning TRUNCATEs into
13746 : SUBREGs. */
13747 :
13748 : static void
13749 77816127 : record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13750 : {
13751 77816127 : subrtx_var_iterator::array_type array;
13752 280940085 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13753 203123958 : if (record_truncated_value (*iter))
13754 23239435 : iter.skip_subrtxes ();
13755 77816127 : }
13756 :
13757 : /* Scan X for promoted SUBREGs. For each one found,
13758 : note what it implies to the registers used in it. */
13759 :
13760 : static void
13761 369989605 : check_promoted_subreg (rtx_insn *insn, rtx x)
13762 : {
13763 369989605 : if (GET_CODE (x) == SUBREG
13764 2268695 : && SUBREG_PROMOTED_VAR_P (x)
13765 369995696 : && REG_P (SUBREG_REG (x)))
13766 6091 : record_promoted_value (insn, x);
13767 : else
13768 : {
13769 369983514 : const char *format = GET_RTX_FORMAT (GET_CODE (x));
13770 369983514 : int i, j;
13771 :
13772 890477533 : for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13773 520494019 : switch (format[i])
13774 : {
13775 276701422 : case 'e':
13776 276701422 : check_promoted_subreg (insn, XEXP (x, i));
13777 276701422 : break;
13778 11991022 : case 'V':
13779 11991022 : case 'E':
13780 11991022 : if (XVEC (x, i) != 0)
13781 37312595 : for (j = 0; j < XVECLEN (x, i); j++)
13782 25321573 : check_promoted_subreg (insn, XVECEXP (x, i, j));
13783 : break;
13784 : }
13785 : }
13786 369989605 : }
13787 :
13788 : /* Verify that all the registers and memory references mentioned in *LOC are
13789 : still valid. *LOC was part of a value set in INSN when label_tick was
13790 : equal to TICK. Return false if some are not. If REPLACE is true, replace
13791 : the invalid references with (clobber (const_int 0)) and return true. This
13792 : replacement is useful because we often can get useful information about
13793 : the form of a value (e.g., if it was produced by a shift that always
13794 : produces -1 or 0) even though we don't know exactly what registers it
13795 : was produced from. */
13796 :
13797 : static bool
13798 484668541 : get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13799 : {
13800 484669104 : rtx x = *loc;
13801 484669104 : const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13802 484669104 : int len = GET_RTX_LENGTH (GET_CODE (x));
13803 484669104 : int i, j;
13804 :
13805 484669104 : if (REG_P (x))
13806 : {
13807 162796382 : unsigned int regno = REGNO (x);
13808 162796382 : unsigned int endregno = END_REGNO (x);
13809 162796382 : unsigned int j;
13810 :
13811 301630274 : for (j = regno; j < endregno; j++)
13812 : {
13813 162821589 : reg_stat_type *rsp = ®_stat[j];
13814 162821589 : if (rsp->last_set_invalid
13815 : /* If this is a pseudo-register that was only set once and not
13816 : live at the beginning of the function, it is always valid. */
13817 270443396 : || (! (regno >= FIRST_PSEUDO_REGISTER
13818 123918437 : && regno < reg_n_sets_max
13819 123897414 : && REG_N_SETS (regno) == 1
13820 215243614 : && (!REGNO_REG_SET_P
13821 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13822 : regno)))
13823 31443184 : && rsp->last_set_label > tick))
13824 : {
13825 23987697 : if (replace)
13826 12122646 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13827 : return replace;
13828 : }
13829 : }
13830 :
13831 : return true;
13832 : }
13833 : /* If this is a memory reference, make sure that there were no stores after
13834 : it that might have clobbered the value. We don't have alias info, so we
13835 : assume any store invalidates it. Moreover, we only have local UIDs, so
13836 : we also assume that there were stores in the intervening basic blocks. */
13837 35806689 : else if (MEM_P (x) && !MEM_READONLY_P (x)
13838 355505211 : && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13839 : {
13840 8004984 : if (replace)
13841 4006248 : *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13842 : return replace;
13843 : }
13844 :
13845 783516525 : for (i = 0; i < len; i++)
13846 : {
13847 481760563 : if (fmt[i] == 'e')
13848 : {
13849 : /* Check for identical subexpressions. If x contains
13850 : identical subexpression we only have to traverse one of
13851 : them. */
13852 294579667 : if (i == 1 && ARITHMETIC_P (x))
13853 : {
13854 : /* Note that at this point x0 has already been checked
13855 : and found valid. */
13856 105629381 : rtx x0 = XEXP (x, 0);
13857 105629381 : rtx x1 = XEXP (x, 1);
13858 :
13859 : /* If x0 and x1 are identical then x is also valid. */
13860 105629381 : if (x0 == x1)
13861 : return true;
13862 :
13863 : /* If x1 is identical to a subexpression of x0 then
13864 : while checking x0, x1 has already been checked. Thus
13865 : it is valid and so as x. */
13866 105239008 : if (ARITHMETIC_P (x0)
13867 19657452 : && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13868 : return true;
13869 :
13870 : /* If x0 is identical to a subexpression of x1 then x is
13871 : valid iff the rest of x1 is valid. */
13872 103166551 : if (ARITHMETIC_P (x1)
13873 370886 : && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13874 563 : return
13875 563 : get_last_value_validate (&XEXP (x1,
13876 : x0 == XEXP (x1, 0) ? 1 : 0),
13877 563 : insn, tick, replace);
13878 : }
13879 :
13880 292116274 : if (!get_last_value_validate (&XEXP (x, i), insn, tick, replace))
13881 : return false;
13882 : }
13883 187180896 : else if (fmt[i] == 'E')
13884 33564971 : for (j = 0; j < XVECLEN (x, i); j++)
13885 26579348 : if (!get_last_value_validate (&XVECEXP (x, i, j),
13886 : insn, tick, replace))
13887 : return false;
13888 : }
13889 :
13890 : /* If we haven't found a reason for it to be invalid, it is valid. */
13891 : return true;
13892 : }
13893 :
13894 : /* Get the last value assigned to X, if known. Some registers
13895 : in the value may be replaced with (clobber (const_int 0)) if their value
13896 : is known longer known reliably. */
13897 :
13898 : static rtx
13899 238389952 : get_last_value (const_rtx x)
13900 : {
13901 238389952 : unsigned int regno;
13902 238389952 : rtx value;
13903 238389952 : reg_stat_type *rsp;
13904 :
13905 : /* If this is a non-paradoxical SUBREG, get the value of its operand and
13906 : then convert it to the desired mode. If this is a paradoxical SUBREG,
13907 : we cannot predict what values the "extra" bits might have. */
13908 238389952 : if (GET_CODE (x) == SUBREG
13909 14127192 : && subreg_lowpart_p (x)
13910 13619275 : && !paradoxical_subreg_p (x)
13911 247083970 : && (value = get_last_value (SUBREG_REG (x))) != 0)
13912 4455174 : return gen_lowpart (GET_MODE (x), value);
13913 :
13914 233934778 : if (!REG_P (x))
13915 : return 0;
13916 :
13917 202771993 : regno = REGNO (x);
13918 202771993 : rsp = ®_stat[regno];
13919 202771993 : value = rsp->last_set_value;
13920 :
13921 : /* If we don't have a value, or if it isn't for this basic block and
13922 : it's either a hard register, set more than once, or it's a live
13923 : at the beginning of the function, return 0.
13924 :
13925 : Because if it's not live at the beginning of the function then the reg
13926 : is always set before being used (is never used without being set).
13927 : And, if it's set only once, and it's always set before use, then all
13928 : uses must have the same last value, even if it's not from this basic
13929 : block. */
13930 :
13931 202771993 : if (value == 0
13932 202771993 : || (rsp->last_set_label < label_tick_ebb_start
13933 76562865 : && (regno < FIRST_PSEUDO_REGISTER
13934 75703506 : || regno >= reg_n_sets_max
13935 75703506 : || REG_N_SETS (regno) != 1
13936 16943064 : || REGNO_REG_SET_P
13937 : (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13938 : return 0;
13939 :
13940 : /* If the value was set in a later insn than the ones we are processing,
13941 : we can't use it even if the register was only set once. */
13942 82463348 : if (rsp->last_set_label == label_tick
13943 82463348 : && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13944 : return 0;
13945 :
13946 : /* If fewer bits were set than what we are asked for now, we cannot use
13947 : the value. */
13948 61527217 : if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13949 61527217 : GET_MODE_PRECISION (GET_MODE (x))))
13950 : return 0;
13951 :
13952 : /* If the value has all its registers valid, return it. */
13953 61525795 : if (get_last_value_validate (&value, rsp->last_set,
13954 : rsp->last_set_label, false))
13955 57048073 : return value;
13956 :
13957 : /* Otherwise, make a copy and replace any invalid register with
13958 : (clobber (const_int 0)). If that fails for some reason, return 0. */
13959 :
13960 4477722 : value = copy_rtx (value);
13961 4477722 : if (get_last_value_validate (&value, rsp->last_set,
13962 : rsp->last_set_label, true))
13963 4477722 : return value;
13964 :
13965 : return 0;
13966 : }
13967 :
13968 : /* Define three variables used for communication between the following
13969 : routines. */
13970 :
13971 : static unsigned int reg_dead_regno, reg_dead_endregno;
13972 : static int reg_dead_flag;
13973 : rtx reg_dead_reg;
13974 :
13975 : /* Function called via note_stores from reg_dead_at_p.
13976 :
13977 : If DEST is within [reg_dead_regno, reg_dead_endregno), set
13978 : reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13979 :
13980 : static void
13981 655497 : reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13982 : {
13983 655497 : unsigned int regno, endregno;
13984 :
13985 655497 : if (!REG_P (dest))
13986 : return;
13987 :
13988 603392 : regno = REGNO (dest);
13989 603392 : endregno = END_REGNO (dest);
13990 603392 : if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13991 295452 : reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13992 : }
13993 :
13994 : /* Return true if REG is known to be dead at INSN.
13995 :
13996 : We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13997 : referencing REG, it is dead. If we hit a SET referencing REG, it is
13998 : live. Otherwise, see if it is live or dead at the start of the basic
13999 : block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
14000 : must be assumed to be always live. */
14001 :
14002 : static bool
14003 1624336 : reg_dead_at_p (rtx reg, rtx_insn *insn)
14004 : {
14005 1624336 : basic_block block;
14006 1624336 : unsigned int i;
14007 :
14008 : /* Set variables for reg_dead_at_p_1. */
14009 1624336 : reg_dead_regno = REGNO (reg);
14010 1624336 : reg_dead_endregno = END_REGNO (reg);
14011 1624336 : reg_dead_reg = reg;
14012 :
14013 1624336 : reg_dead_flag = 0;
14014 :
14015 : /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
14016 : we allow the machine description to decide whether use-and-clobber
14017 : patterns are OK. */
14018 1624336 : if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
14019 : {
14020 3248672 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14021 1624336 : if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
14022 : return false;
14023 : }
14024 :
14025 : /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
14026 : beginning of basic block. */
14027 1624336 : block = BLOCK_FOR_INSN (insn);
14028 809642 : for (;;)
14029 : {
14030 2433978 : if (INSN_P (insn))
14031 : {
14032 2280076 : if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
14033 : return true;
14034 :
14035 863925 : note_stores (insn, reg_dead_at_p_1, NULL);
14036 863925 : if (reg_dead_flag)
14037 147726 : return reg_dead_flag == 1 ? 1 : 0;
14038 :
14039 716199 : if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
14040 : return true;
14041 : }
14042 :
14043 839713 : if (insn == BB_HEAD (block))
14044 : break;
14045 :
14046 809642 : insn = PREV_INSN (insn);
14047 : }
14048 :
14049 : /* Look at live-in sets for the basic block that we were in. */
14050 60142 : for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14051 30071 : if (REGNO_REG_SET_P (df_get_live_in (block), i))
14052 : return false;
14053 :
14054 : return true;
14055 : }
14056 :
14057 : /* Note hard registers in X that are used. */
14058 :
14059 : static void
14060 296125618 : mark_used_regs_combine (rtx x)
14061 : {
14062 342151818 : RTX_CODE code = GET_CODE (x);
14063 342151818 : unsigned int regno;
14064 342151818 : int i;
14065 :
14066 342151818 : switch (code)
14067 : {
14068 : case LABEL_REF:
14069 : case SYMBOL_REF:
14070 : case CONST:
14071 : CASE_CONST_ANY:
14072 : case PC:
14073 : case ADDR_VEC:
14074 : case ADDR_DIFF_VEC:
14075 : case ASM_INPUT:
14076 : return;
14077 :
14078 7547326 : case CLOBBER:
14079 : /* If we are clobbering a MEM, mark any hard registers inside the
14080 : address as used. */
14081 7547326 : if (MEM_P (XEXP (x, 0)))
14082 5495 : mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
14083 : return;
14084 :
14085 77861931 : case REG:
14086 77861931 : regno = REGNO (x);
14087 : /* A hard reg in a wide mode may really be multiple registers.
14088 : If so, mark all of them just like the first. */
14089 77861931 : if (regno < FIRST_PSEUDO_REGISTER)
14090 : {
14091 : /* None of this applies to the stack, frame or arg pointers. */
14092 9302952 : if (regno == STACK_POINTER_REGNUM
14093 9302952 : || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14094 : && regno == HARD_FRAME_POINTER_REGNUM)
14095 8384447 : || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14096 1129558 : && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14097 7254889 : || regno == FRAME_POINTER_REGNUM)
14098 : return;
14099 :
14100 1780918 : add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
14101 : }
14102 : return;
14103 :
14104 46020705 : case SET:
14105 46020705 : {
14106 : /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14107 : the address. */
14108 46020705 : rtx testreg = SET_DEST (x);
14109 :
14110 46020705 : while (GET_CODE (testreg) == SUBREG
14111 46035247 : || GET_CODE (testreg) == ZERO_EXTRACT
14112 92387537 : || GET_CODE (testreg) == STRICT_LOW_PART)
14113 338521 : testreg = XEXP (testreg, 0);
14114 :
14115 46020705 : if (MEM_P (testreg))
14116 4865572 : mark_used_regs_combine (XEXP (testreg, 0));
14117 :
14118 46020705 : mark_used_regs_combine (SET_SRC (x));
14119 : }
14120 46020705 : return;
14121 :
14122 136712550 : default:
14123 136712550 : break;
14124 : }
14125 :
14126 : /* Recursively scan the operands of this expression. */
14127 :
14128 136712550 : {
14129 136712550 : const char *fmt = GET_RTX_FORMAT (code);
14130 :
14131 396652751 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14132 : {
14133 259940201 : if (fmt[i] == 'e')
14134 210719480 : mark_used_regs_combine (XEXP (x, i));
14135 49220721 : else if (fmt[i] == 'E')
14136 : {
14137 : int j;
14138 :
14139 67539163 : for (j = 0; j < XVECLEN (x, i); j++)
14140 46892081 : mark_used_regs_combine (XVECEXP (x, i, j));
14141 : }
14142 : }
14143 : }
14144 : }
14145 :
14146 : /* Remove register number REGNO from the dead registers list of INSN.
14147 :
14148 : Return the note used to record the death, if there was one. */
14149 :
14150 : rtx
14151 3208988 : remove_death (unsigned int regno, rtx_insn *insn)
14152 : {
14153 3208988 : rtx note = find_regno_note (insn, REG_DEAD, regno);
14154 :
14155 3208988 : if (note)
14156 523348 : remove_note (insn, note);
14157 :
14158 3208988 : return note;
14159 : }
14160 :
14161 : /* For each register (hardware or pseudo) used within expression X, if its
14162 : death is in an instruction with luid between FROM_LUID (inclusive) and
14163 : TO_INSN (exclusive), put a REG_DEAD note for that register in the
14164 : list headed by PNOTES.
14165 :
14166 : That said, don't move registers killed by maybe_kill_insn.
14167 :
14168 : This is done when X is being merged by combination into TO_INSN. These
14169 : notes will then be distributed as needed. */
14170 :
14171 : static void
14172 24779075 : move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14173 : rtx *pnotes)
14174 : {
14175 25318654 : const char *fmt;
14176 25318654 : int len, i;
14177 25318654 : enum rtx_code code = GET_CODE (x);
14178 :
14179 25318654 : if (code == REG)
14180 : {
14181 6249196 : unsigned int regno = REGNO (x);
14182 6249196 : rtx_insn *where_dead = reg_stat[regno].last_death;
14183 :
14184 : /* If we do not know where the register died, it may still die between
14185 : FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14186 6249196 : if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14187 : {
14188 3394012 : rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14189 3394012 : while (insn
14190 5094714 : && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14191 9434862 : && DF_INSN_LUID (insn) >= from_luid)
14192 : {
14193 2304474 : if (dead_or_set_regno_p (insn, regno))
14194 : {
14195 572249 : if (find_regno_note (insn, REG_DEAD, regno))
14196 6249196 : where_dead = insn;
14197 : break;
14198 : }
14199 :
14200 1732225 : insn = prev_real_nondebug_insn (insn);
14201 : }
14202 : }
14203 :
14204 : /* Don't move the register if it gets killed in between from and to. */
14205 149108 : if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14206 6291201 : && ! reg_referenced_p (x, maybe_kill_insn))
14207 : return;
14208 :
14209 6207191 : if (where_dead
14210 3215162 : && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14211 3054746 : && DF_INSN_LUID (where_dead) >= from_luid
14212 9261708 : && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14213 : {
14214 2761111 : rtx note = remove_death (regno, where_dead);
14215 :
14216 : /* It is possible for the call above to return 0. This can occur
14217 : when last_death points to I2 or I1 that we combined with.
14218 : In that case make a new note.
14219 :
14220 : We must also check for the case where X is a hard register
14221 : and NOTE is a death note for a range of hard registers
14222 : including X. In that case, we must put REG_DEAD notes for
14223 : the remaining registers in place of NOTE. */
14224 :
14225 2761111 : if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14226 2761111 : && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14227 : {
14228 0 : unsigned int deadregno = REGNO (XEXP (note, 0));
14229 0 : unsigned int deadend = END_REGNO (XEXP (note, 0));
14230 0 : unsigned int ourend = END_REGNO (x);
14231 0 : unsigned int i;
14232 :
14233 0 : for (i = deadregno; i < deadend; i++)
14234 0 : if (i < regno || i >= ourend)
14235 0 : add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14236 : }
14237 :
14238 : /* If we didn't find any note, or if we found a REG_DEAD note that
14239 : covers only part of the given reg, and we have a multi-reg hard
14240 : register, then to be safe we must check for REG_DEAD notes
14241 : for each register other than the first. They could have
14242 : their own REG_DEAD notes lying around. */
14243 2761111 : else if ((note == 0
14244 : || (note != 0
14245 75516 : && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14246 75516 : GET_MODE (x))))
14247 2685595 : && regno < FIRST_PSEUDO_REGISTER
14248 3098922 : && REG_NREGS (x) > 1)
14249 : {
14250 0 : unsigned int ourend = END_REGNO (x);
14251 0 : unsigned int i, offset;
14252 0 : rtx oldnotes = 0;
14253 :
14254 0 : if (note)
14255 0 : offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14256 : else
14257 : offset = 1;
14258 :
14259 0 : for (i = regno + offset; i < ourend; i++)
14260 0 : move_deaths (regno_reg_rtx[i],
14261 : maybe_kill_insn, from_luid, to_insn, &oldnotes);
14262 : }
14263 :
14264 2761111 : if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14265 : {
14266 75492 : XEXP (note, 1) = *pnotes;
14267 75492 : *pnotes = note;
14268 : }
14269 : else
14270 2685619 : *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14271 : }
14272 :
14273 : return;
14274 : }
14275 :
14276 19069458 : else if (GET_CODE (x) == SET)
14277 : {
14278 4288721 : rtx dest = SET_DEST (x);
14279 :
14280 4288721 : move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14281 :
14282 : /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14283 : that accesses one word of a multi-word item, some
14284 : piece of everything register in the expression is used by
14285 : this insn, so remove any old death. */
14286 : /* ??? So why do we test for equality of the sizes? */
14287 :
14288 4288721 : if (GET_CODE (dest) == ZERO_EXTRACT
14289 4288277 : || GET_CODE (dest) == STRICT_LOW_PART
14290 8575258 : || (GET_CODE (dest) == SUBREG
14291 78464 : && !read_modify_subreg_p (dest)))
14292 : {
14293 : move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14294 : return;
14295 : }
14296 :
14297 : /* If this is some other SUBREG, we know it replaces the entire
14298 : value, so use that as the destination. */
14299 4225856 : if (GET_CODE (dest) == SUBREG)
14300 17783 : dest = SUBREG_REG (dest);
14301 :
14302 : /* If this is a MEM, adjust deaths of anything used in the address.
14303 : For a REG (the only other possibility), the entire value is
14304 : being replaced so the old value is not used in this insn. */
14305 :
14306 4225856 : if (MEM_P (dest))
14307 476714 : move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14308 : to_insn, pnotes);
14309 : return;
14310 : }
14311 :
14312 14780737 : else if (GET_CODE (x) == CLOBBER)
14313 : return;
14314 :
14315 14136845 : len = GET_RTX_LENGTH (code);
14316 14136845 : fmt = GET_RTX_FORMAT (code);
14317 :
14318 36850285 : for (i = 0; i < len; i++)
14319 : {
14320 22713440 : if (fmt[i] == 'E')
14321 : {
14322 1029141 : int j;
14323 3657510 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14324 2628369 : move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14325 : to_insn, pnotes);
14326 : }
14327 21684299 : else if (fmt[i] == 'e')
14328 13647939 : move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14329 : }
14330 : }
14331 :
14332 : /* Return true if X is the target of a bit-field assignment in BODY, the
14333 : pattern of an insn. X must be a REG. */
14334 :
14335 : static bool
14336 4822384 : reg_bitfield_target_p (rtx x, rtx body)
14337 : {
14338 4822384 : int i;
14339 :
14340 4822384 : if (GET_CODE (body) == SET)
14341 : {
14342 3507094 : rtx dest = SET_DEST (body);
14343 3507094 : rtx target;
14344 3507094 : unsigned int regno, tregno, endregno, endtregno;
14345 :
14346 3507094 : if (GET_CODE (dest) == ZERO_EXTRACT)
14347 426 : target = XEXP (dest, 0);
14348 3506668 : else if (GET_CODE (dest) == STRICT_LOW_PART)
14349 1957 : target = SUBREG_REG (XEXP (dest, 0));
14350 : else
14351 : return false;
14352 :
14353 2383 : if (GET_CODE (target) == SUBREG)
14354 219 : target = SUBREG_REG (target);
14355 :
14356 2383 : if (!REG_P (target))
14357 : return false;
14358 :
14359 2304 : tregno = REGNO (target), regno = REGNO (x);
14360 2304 : if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14361 2304 : return target == x;
14362 :
14363 0 : endtregno = end_hard_regno (GET_MODE (target), tregno);
14364 0 : endregno = end_hard_regno (GET_MODE (x), regno);
14365 :
14366 0 : return endregno > tregno && regno < endtregno;
14367 : }
14368 :
14369 1315290 : else if (GET_CODE (body) == PARALLEL)
14370 1977716 : for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14371 1332607 : if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14372 : return true;
14373 :
14374 : return false;
14375 : }
14376 :
14377 : /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14378 : as appropriate. I3 and I2 are the insns resulting from the combination
14379 : insns including FROM (I2 may be zero).
14380 :
14381 : ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14382 : not need REG_DEAD notes because they are being substituted for. This
14383 : saves searching in the most common cases.
14384 :
14385 : Each note in the list is either ignored or placed on some insns, depending
14386 : on the type of note. */
14387 :
14388 : static void
14389 10046904 : distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14390 : rtx elim_i2, rtx elim_i1, rtx elim_i0)
14391 : {
14392 10046904 : rtx note, next_note;
14393 10046904 : rtx tem_note;
14394 10046904 : rtx_insn *tem_insn;
14395 :
14396 23282420 : for (note = notes; note; note = next_note)
14397 : {
14398 13235516 : rtx_insn *place = 0, *place2 = 0;
14399 :
14400 13235516 : next_note = XEXP (note, 1);
14401 13235516 : switch (REG_NOTE_KIND (note))
14402 : {
14403 : case REG_BR_PROB:
14404 : case REG_BR_PRED:
14405 : /* Doesn't matter much where we put this, as long as it's somewhere.
14406 : It is preferable to keep these notes on branches, which is most
14407 : likely to be i3. */
14408 : place = i3;
14409 : break;
14410 :
14411 0 : case REG_NON_LOCAL_GOTO:
14412 0 : if (JUMP_P (i3))
14413 : place = i3;
14414 : else
14415 : {
14416 0 : gcc_assert (i2 && JUMP_P (i2));
14417 : place = i2;
14418 : }
14419 : break;
14420 :
14421 21435 : case REG_EH_REGION:
14422 21435 : {
14423 : /* The landing pad handling needs to be kept in sync with the
14424 : prerequisite checking in try_combine. */
14425 21435 : int lp_nr = INTVAL (XEXP (note, 0));
14426 : /* A REG_EH_REGION note transferring control can only ever come
14427 : from i3. */
14428 21435 : if (lp_nr > 0)
14429 11781 : gcc_assert (from_insn == i3);
14430 : /* We are making sure there is a single effective REG_EH_REGION
14431 : note and it's valid to put it on i3. */
14432 21435 : if (!insn_could_throw_p (from_insn)
14433 21435 : && !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14434 : /* Throw away stray notes on insns that can never throw or
14435 : make a nonlocal goto. */
14436 : ;
14437 : else
14438 : {
14439 21358 : if (CALL_P (i3))
14440 : place = i3;
14441 : else
14442 : {
14443 2084 : gcc_assert (cfun->can_throw_non_call_exceptions);
14444 : /* If i3 can still trap preserve the note, otherwise we've
14445 : combined things such that we can now prove that the
14446 : instructions can't trap. Drop the note in this case. */
14447 2084 : if (may_trap_p (i3))
14448 : place = i3;
14449 : }
14450 : }
14451 : break;
14452 : }
14453 :
14454 126312 : case REG_ARGS_SIZE:
14455 : /* ??? How to distribute between i3-i1. Assume i3 contains the
14456 : entire adjustment. Assert i3 contains at least some adjust. */
14457 126312 : if (!noop_move_p (i3))
14458 : {
14459 126311 : poly_int64 old_size, args_size = get_args_size (note);
14460 : /* fixup_args_size_notes looks at REG_NORETURN note,
14461 : so ensure the note is placed there first. */
14462 126311 : if (CALL_P (i3))
14463 : {
14464 : rtx *np;
14465 1661 : for (np = &next_note; *np; np = &XEXP (*np, 1))
14466 20 : if (REG_NOTE_KIND (*np) == REG_NORETURN)
14467 : {
14468 9 : rtx n = *np;
14469 9 : *np = XEXP (n, 1);
14470 9 : XEXP (n, 1) = REG_NOTES (i3);
14471 9 : REG_NOTES (i3) = n;
14472 9 : break;
14473 : }
14474 : }
14475 126311 : old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14476 : /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14477 : REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14478 126311 : gcc_assert (maybe_ne (old_size, args_size)
14479 : || (CALL_P (i3)
14480 : && !ACCUMULATE_OUTGOING_ARGS
14481 : && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14482 : }
14483 : break;
14484 :
14485 81049 : case REG_NORETURN:
14486 81049 : case REG_SETJMP:
14487 81049 : case REG_TM:
14488 81049 : case REG_CALL_DECL:
14489 81049 : case REG_UNTYPED_CALL:
14490 81049 : case REG_CALL_NOCF_CHECK:
14491 : /* These notes must remain with the call. It should not be
14492 : possible for both I2 and I3 to be a call. */
14493 81049 : if (CALL_P (i3))
14494 : place = i3;
14495 : else
14496 : {
14497 0 : gcc_assert (i2 && CALL_P (i2));
14498 : place = i2;
14499 : }
14500 : break;
14501 :
14502 1996333 : case REG_UNUSED:
14503 : /* Any clobbers for i3 may still exist, and so we must process
14504 : REG_UNUSED notes from that insn.
14505 :
14506 : Any clobbers from i2 or i1 can only exist if they were added by
14507 : recog_for_combine. In that case, recog_for_combine created the
14508 : necessary REG_UNUSED notes. Trying to keep any original
14509 : REG_UNUSED notes from these insns can cause incorrect output
14510 : if it is for the same register as the original i3 dest.
14511 : In that case, we will notice that the register is set in i3,
14512 : and then add a REG_UNUSED note for the destination of i3, which
14513 : is wrong. However, it is possible to have REG_UNUSED notes from
14514 : i2 or i1 for register which were both used and clobbered, so
14515 : we keep notes from i2 or i1 if they will turn into REG_DEAD
14516 : notes. */
14517 :
14518 : /* If this register is set or clobbered between FROM_INSN and I3,
14519 : we should not create a note for it. */
14520 1996333 : if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14521 : break;
14522 :
14523 : /* If this register is set or clobbered in I3, put the note there
14524 : unless there is one already. */
14525 1907087 : if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14526 : {
14527 1136596 : if (from_insn != i3)
14528 : break;
14529 :
14530 668126 : if (! (REG_P (XEXP (note, 0))
14531 668126 : ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14532 0 : : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14533 : place = i3;
14534 : }
14535 : /* Otherwise, if this register is used by I3, then this register
14536 : now dies here, so we must put a REG_DEAD note here unless there
14537 : is one already. */
14538 770491 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14539 : {
14540 7661 : if (! (REG_P (XEXP (note, 0))
14541 7661 : ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
14542 0 : : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14543 : {
14544 7406 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14545 7406 : place = i3;
14546 : }
14547 : }
14548 :
14549 : /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14550 : but we can't tell which at this point. We must reset any
14551 : expectations we had about the value that was previously
14552 : stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14553 : and, if appropriate, restore its previous value, but we
14554 : don't have enough information for that at this point. */
14555 : else
14556 : {
14557 762830 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14558 :
14559 : /* Otherwise, if this register is now referenced in i2
14560 : then the register used to be modified in one of the
14561 : original insns. If it was i3 (say, in an unused
14562 : parallel), it's now completely gone, so the note can
14563 : be discarded. But if it was modified in i2, i1 or i0
14564 : and we still reference it in i2, then we're
14565 : referencing the previous value, and since the
14566 : register was modified and REG_UNUSED, we know that
14567 : the previous value is now dead. So, if we only
14568 : reference the register in i2, we change the note to
14569 : REG_DEAD, to reflect the previous value. However, if
14570 : we're also setting or clobbering the register as
14571 : scratch, we know (because the register was not
14572 : referenced in i3) that it's unused, just as it was
14573 : unused before, and we place the note in i2. */
14574 16915 : if (from_insn != i3 && i2 && INSN_P (i2)
14575 779745 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14576 : {
14577 24 : if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14578 24 : PUT_REG_NOTE_KIND (note, REG_DEAD);
14579 24 : if (! (REG_P (XEXP (note, 0))
14580 24 : ? find_regno_note (i2, REG_NOTE_KIND (note),
14581 24 : REGNO (XEXP (note, 0)))
14582 0 : : find_reg_note (i2, REG_NOTE_KIND (note),
14583 : XEXP (note, 0))))
14584 : place = i2;
14585 : }
14586 : }
14587 :
14588 : break;
14589 :
14590 394269 : case REG_EQUAL:
14591 394269 : case REG_EQUIV:
14592 394269 : case REG_NOALIAS:
14593 : /* These notes say something about results of an insn. We can
14594 : only support them if they used to be on I3 in which case they
14595 : remain on I3. Otherwise they are ignored.
14596 :
14597 : If the note refers to an expression that is not a constant, we
14598 : must also ignore the note since we cannot tell whether the
14599 : equivalence is still true. It might be possible to do
14600 : slightly better than this (we only have a problem if I2DEST
14601 : or I1DEST is present in the expression), but it doesn't
14602 : seem worth the trouble. */
14603 :
14604 394269 : if (from_insn == i3
14605 194309 : && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14606 : place = i3;
14607 : break;
14608 :
14609 0 : case REG_INC:
14610 : /* These notes say something about how a register is used. They must
14611 : be present on any use of the register in I2 or I3. */
14612 0 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14613 0 : place = i3;
14614 :
14615 0 : if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14616 : {
14617 0 : if (place)
14618 : place2 = i2;
14619 : else
14620 : place = i2;
14621 : }
14622 : break;
14623 :
14624 7205 : case REG_LABEL_TARGET:
14625 7205 : case REG_LABEL_OPERAND:
14626 : /* This can show up in several ways -- either directly in the
14627 : pattern, or hidden off in the constant pool with (or without?)
14628 : a REG_EQUAL note. */
14629 : /* ??? Ignore the without-reg_equal-note problem for now. */
14630 7205 : if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14631 7205 : || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14632 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14633 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14634 : place = i3;
14635 :
14636 7205 : if (i2
14637 7205 : && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14638 0 : || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14639 0 : && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14640 0 : && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14641 : {
14642 0 : if (place)
14643 : place2 = i2;
14644 : else
14645 : place = i2;
14646 : }
14647 :
14648 : /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14649 : as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14650 : there. */
14651 7205 : if (place && JUMP_P (place)
14652 5957 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14653 0 : && (JUMP_LABEL (place) == NULL
14654 0 : || JUMP_LABEL (place) == XEXP (note, 0)))
14655 : {
14656 0 : rtx label = JUMP_LABEL (place);
14657 :
14658 0 : if (!label)
14659 0 : JUMP_LABEL (place) = XEXP (note, 0);
14660 0 : else if (LABEL_P (label))
14661 0 : LABEL_NUSES (label)--;
14662 : }
14663 :
14664 7205 : if (place2 && JUMP_P (place2)
14665 0 : && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14666 0 : && (JUMP_LABEL (place2) == NULL
14667 0 : || JUMP_LABEL (place2) == XEXP (note, 0)))
14668 : {
14669 0 : rtx label = JUMP_LABEL (place2);
14670 :
14671 0 : if (!label)
14672 0 : JUMP_LABEL (place2) = XEXP (note, 0);
14673 0 : else if (LABEL_P (label))
14674 0 : LABEL_NUSES (label)--;
14675 : place2 = 0;
14676 : }
14677 : break;
14678 :
14679 : case REG_NONNEG:
14680 : /* This note says something about the value of a register prior
14681 : to the execution of an insn. It is too much trouble to see
14682 : if the note is still correct in all situations. It is better
14683 : to simply delete it. */
14684 : break;
14685 :
14686 10568813 : case REG_DEAD:
14687 : /* If we replaced the right hand side of FROM_INSN with a
14688 : REG_EQUAL note, the original use of the dying register
14689 : will not have been combined into I3 and I2. In such cases,
14690 : FROM_INSN is guaranteed to be the first of the combined
14691 : instructions, so we simply need to search back before
14692 : FROM_INSN for the previous use or set of this register,
14693 : then alter the notes there appropriately.
14694 :
14695 : If the register is used as an input in I3, it dies there.
14696 : Similarly for I2, if it is nonzero and adjacent to I3.
14697 :
14698 : If the register is not used as an input in either I3 or I2
14699 : and it is not one of the registers we were supposed to eliminate,
14700 : there are two possibilities. We might have a non-adjacent I2
14701 : or we might have somehow eliminated an additional register
14702 : from a computation. For example, we might have had A & B where
14703 : we discover that B will always be zero. In this case we will
14704 : eliminate the reference to A.
14705 :
14706 : In both cases, we must search to see if we can find a previous
14707 : use of A and put the death note there. */
14708 :
14709 10568813 : if (from_insn
14710 7381806 : && from_insn == i2mod
14711 10570453 : && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14712 : tem_insn = from_insn;
14713 : else
14714 : {
14715 10567464 : if (from_insn
14716 7380457 : && CALL_P (from_insn)
14717 10799410 : && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14718 : place = from_insn;
14719 10416560 : else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14720 : {
14721 : /* If the new I2 sets the same register that is marked
14722 : dead in the note, we do not in general know where to
14723 : put the note. One important case we _can_ handle is
14724 : when the note comes from I3. */
14725 39538 : if (from_insn == i3)
14726 : place = i3;
14727 : else
14728 : break;
14729 : }
14730 10377022 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14731 : place = i3;
14732 104506 : else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14733 4139547 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14734 : place = i2;
14735 3992213 : else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14736 3872903 : && !(i2mod
14737 26979 : && reg_overlap_mentioned_p (XEXP (note, 0),
14738 : i2mod_old_rhs)))
14739 146299 : || rtx_equal_p (XEXP (note, 0), elim_i1)
14740 4046673 : || rtx_equal_p (XEXP (note, 0), elim_i0))
14741 : break;
14742 : tem_insn = i3;
14743 : }
14744 :
14745 236112 : if (place == 0)
14746 : {
14747 51244 : basic_block bb = this_basic_block;
14748 :
14749 1172346 : for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14750 : {
14751 1172346 : if (!NONDEBUG_INSN_P (tem_insn))
14752 : {
14753 825915 : if (tem_insn == BB_HEAD (bb))
14754 : break;
14755 790971 : continue;
14756 : }
14757 :
14758 : /* If the register is being set at TEM_INSN, see if that is all
14759 : TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14760 : into a REG_UNUSED note instead. Don't delete sets to
14761 : global register vars. */
14762 346431 : if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14763 1368 : || !global_regs[REGNO (XEXP (note, 0))])
14764 347799 : && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14765 : {
14766 15585 : rtx set = single_set (tem_insn);
14767 15585 : rtx inner_dest = 0;
14768 :
14769 15585 : if (set != 0)
14770 12019 : for (inner_dest = SET_DEST (set);
14771 12268 : (GET_CODE (inner_dest) == STRICT_LOW_PART
14772 12268 : || GET_CODE (inner_dest) == SUBREG
14773 12268 : || GET_CODE (inner_dest) == ZERO_EXTRACT);
14774 249 : inner_dest = XEXP (inner_dest, 0))
14775 : ;
14776 :
14777 : /* Verify that it was the set, and not a clobber that
14778 : modified the register.
14779 :
14780 : If we cannot delete the setter due to side
14781 : effects, mark the user with an UNUSED note instead
14782 : of deleting it. */
14783 :
14784 12019 : if (set != 0 && ! side_effects_p (SET_SRC (set))
14785 11646 : && rtx_equal_p (XEXP (note, 0), inner_dest))
14786 : {
14787 : /* Move the notes and links of TEM_INSN elsewhere.
14788 : This might delete other dead insns recursively.
14789 : First set the pattern to something that won't use
14790 : any register. */
14791 11527 : rtx old_notes = REG_NOTES (tem_insn);
14792 :
14793 11527 : PATTERN (tem_insn) = pc_rtx;
14794 11527 : REG_NOTES (tem_insn) = NULL;
14795 :
14796 11527 : distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14797 : NULL_RTX, NULL_RTX, NULL_RTX);
14798 11527 : distribute_links (LOG_LINKS (tem_insn));
14799 :
14800 11527 : unsigned int regno = REGNO (XEXP (note, 0));
14801 11527 : reg_stat_type *rsp = ®_stat[regno];
14802 11527 : if (rsp->last_set == tem_insn)
14803 10119 : record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14804 :
14805 11527 : SET_INSN_DELETED (tem_insn);
14806 11527 : if (tem_insn == i2)
14807 330131 : i2 = NULL;
14808 : }
14809 : else
14810 : {
14811 4058 : PUT_REG_NOTE_KIND (note, REG_UNUSED);
14812 :
14813 : /* If there isn't already a REG_UNUSED note, put one
14814 : here. Do not place a REG_DEAD note, even if
14815 : the register is also used here; that would not
14816 : match the algorithm used in lifetime analysis
14817 : and can cause the consistency check in the
14818 : scheduler to fail. */
14819 4058 : if (! find_regno_note (tem_insn, REG_UNUSED,
14820 4058 : REGNO (XEXP (note, 0))))
14821 2233 : place = tem_insn;
14822 : break;
14823 : }
14824 : }
14825 330846 : else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14826 330846 : || (CALL_P (tem_insn)
14827 14446 : && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14828 : {
14829 12242 : place = tem_insn;
14830 :
14831 : /* If we are doing a 3->2 combination, and we have a
14832 : register which formerly died in i3 and was not used
14833 : by i2, which now no longer dies in i3 and is used in
14834 : i2 but does not die in i2, and place is between i2
14835 : and i3, then we may need to move a link from place to
14836 : i2. */
14837 3864 : if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14838 93 : && from_insn
14839 93 : && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14840 12335 : && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14841 : {
14842 93 : struct insn_link *links = LOG_LINKS (place);
14843 93 : LOG_LINKS (place) = NULL;
14844 93 : distribute_links (links);
14845 : }
14846 : break;
14847 : }
14848 :
14849 330131 : if (tem_insn == BB_HEAD (bb))
14850 : break;
14851 : }
14852 :
14853 : }
14854 :
14855 : /* If the register is set or already dead at PLACE, we needn't do
14856 : anything with this note if it is still a REG_DEAD note.
14857 : We check here if it is set at all, not if is it totally replaced,
14858 : which is what `dead_or_set_p' checks, so also check for it being
14859 : set partially. */
14860 :
14861 6622885 : if (place && REG_NOTE_KIND (note) == REG_DEAD)
14862 : {
14863 6583883 : unsigned int regno = REGNO (XEXP (note, 0));
14864 6583883 : reg_stat_type *rsp = ®_stat[regno];
14865 :
14866 6583883 : if (dead_or_set_p (place, XEXP (note, 0))
14867 6583883 : || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14868 : {
14869 : /* Unless the register previously died in PLACE, clear
14870 : last_death. [I no longer understand why this is
14871 : being done.] */
14872 3094106 : if (rsp->last_death != place)
14873 636034 : rsp->last_death = 0;
14874 : place = 0;
14875 : }
14876 : else
14877 3489777 : rsp->last_death = place;
14878 :
14879 : /* If this is a death note for a hard reg that is occupying
14880 : multiple registers, ensure that we are still using all
14881 : parts of the object. If we find a piece of the object
14882 : that is unused, we must arrange for an appropriate REG_DEAD
14883 : note to be added for it. However, we can't just emit a USE
14884 : and tag the note to it, since the register might actually
14885 : be dead; so we recurse, and the recursive call then finds
14886 : the previous insn that used this register. */
14887 :
14888 4125811 : if (place && REG_NREGS (XEXP (note, 0)) > 1)
14889 : {
14890 773 : unsigned int endregno = END_REGNO (XEXP (note, 0));
14891 773 : bool all_used = true;
14892 773 : unsigned int i;
14893 :
14894 2319 : for (i = regno; i < endregno; i++)
14895 1546 : if ((! refers_to_regno_p (i, PATTERN (place))
14896 1546 : && ! find_regno_fusage (place, USE, i))
14897 3092 : || dead_or_set_regno_p (place, i))
14898 : {
14899 : all_used = false;
14900 : break;
14901 : }
14902 :
14903 773 : if (! all_used)
14904 : {
14905 : /* Put only REG_DEAD notes for pieces that are
14906 : not already dead or set. */
14907 :
14908 0 : for (i = regno; i < endregno;
14909 0 : i += hard_regno_nregs (i, reg_raw_mode[i]))
14910 : {
14911 0 : rtx piece = regno_reg_rtx[i];
14912 0 : basic_block bb = this_basic_block;
14913 :
14914 0 : if (! dead_or_set_p (place, piece)
14915 0 : && ! reg_bitfield_target_p (piece,
14916 0 : PATTERN (place)))
14917 : {
14918 0 : rtx new_note = alloc_reg_note (REG_DEAD, piece,
14919 : NULL_RTX);
14920 :
14921 0 : distribute_notes (new_note, place, place,
14922 : NULL, NULL_RTX, NULL_RTX,
14923 : NULL_RTX);
14924 : }
14925 0 : else if (! refers_to_regno_p (i, PATTERN (place))
14926 0 : && ! find_regno_fusage (place, USE, i))
14927 0 : for (tem_insn = PREV_INSN (place); ;
14928 0 : tem_insn = PREV_INSN (tem_insn))
14929 : {
14930 0 : if (!NONDEBUG_INSN_P (tem_insn))
14931 : {
14932 0 : if (tem_insn == BB_HEAD (bb))
14933 : break;
14934 0 : continue;
14935 : }
14936 0 : if (dead_or_set_p (tem_insn, piece)
14937 0 : || reg_bitfield_target_p (piece,
14938 0 : PATTERN (tem_insn)))
14939 : {
14940 0 : add_reg_note (tem_insn, REG_UNUSED, piece);
14941 0 : break;
14942 : }
14943 : }
14944 : }
14945 :
14946 : place = 0;
14947 : }
14948 : }
14949 : }
14950 : break;
14951 :
14952 0 : default:
14953 : /* Any other notes should not be present at this point in the
14954 : compilation. */
14955 0 : gcc_unreachable ();
14956 : }
14957 :
14958 4330538 : if (place)
14959 : {
14960 4304550 : XEXP (note, 1) = REG_NOTES (place);
14961 4304550 : REG_NOTES (place) = note;
14962 :
14963 : /* Set added_notes_insn to the earliest insn we added a note to. */
14964 4304550 : if (added_notes_insn == 0
14965 4304550 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14966 2846565 : added_notes_insn = place;
14967 : }
14968 :
14969 13235516 : if (place2)
14970 : {
14971 0 : add_shallow_copy_of_reg_note (place2, note);
14972 :
14973 : /* Set added_notes_insn to the earliest insn we added a note to. */
14974 0 : if (added_notes_insn == 0
14975 0 : || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14976 0 : added_notes_insn = place2;
14977 : }
14978 : }
14979 10046904 : }
14980 :
14981 : /* Similarly to above, distribute the LOG_LINKS that used to be present on
14982 : I3, I2, and I1 to new locations. This is also called to add a link
14983 : pointing at I3 when I3's destination is changed.
14984 :
14985 : If START is nonnull and an insn, we know that the next location for each
14986 : link is no earlier than START. LIMIT is the maximum number of nondebug
14987 : instructions that can be scanned when looking for the next use of a
14988 : definition. */
14989 :
14990 : static void
14991 16326491 : distribute_links (struct insn_link *links, rtx_insn *start, int limit)
14992 : {
14993 16326491 : struct insn_link *link, *next_link;
14994 :
14995 24059032 : for (link = links; link; link = next_link)
14996 : {
14997 7732541 : rtx_insn *place = 0;
14998 7732541 : rtx_insn *insn;
14999 7732541 : rtx set, reg;
15000 :
15001 7732541 : next_link = link->next;
15002 :
15003 : /* If the insn that this link points to is a NOTE, ignore it. */
15004 7732541 : if (NOTE_P (link->insn))
15005 4111091 : continue;
15006 :
15007 3621450 : set = 0;
15008 3621450 : rtx pat = PATTERN (link->insn);
15009 3621450 : if (GET_CODE (pat) == SET)
15010 : set = pat;
15011 634906 : else if (GET_CODE (pat) == PARALLEL)
15012 : {
15013 : int i;
15014 748933 : for (i = 0; i < XVECLEN (pat, 0); i++)
15015 : {
15016 745329 : set = XVECEXP (pat, 0, i);
15017 745329 : if (GET_CODE (set) != SET)
15018 3613 : continue;
15019 :
15020 741716 : reg = SET_DEST (set);
15021 741716 : while (GET_CODE (reg) == ZERO_EXTRACT
15022 750310 : || GET_CODE (reg) == STRICT_LOW_PART
15023 1500576 : || GET_CODE (reg) == SUBREG)
15024 8601 : reg = XEXP (reg, 0);
15025 :
15026 741716 : if (!REG_P (reg))
15027 44441 : continue;
15028 :
15029 697275 : if (REGNO (reg) == link->regno)
15030 : break;
15031 : }
15032 632684 : if (i == XVECLEN (pat, 0))
15033 3604 : continue;
15034 : }
15035 : else
15036 2222 : continue;
15037 :
15038 3615624 : reg = SET_DEST (set);
15039 :
15040 3615624 : while (GET_CODE (reg) == ZERO_EXTRACT
15041 3638881 : || GET_CODE (reg) == STRICT_LOW_PART
15042 7277868 : || GET_CODE (reg) == SUBREG)
15043 23772 : reg = XEXP (reg, 0);
15044 :
15045 3615624 : if (reg == pc_rtx)
15046 396 : continue;
15047 :
15048 : /* A LOG_LINK is defined as being placed on the first insn that uses
15049 : a register and points to the insn that sets the register. Start
15050 : searching at the next insn after the target of the link and stop
15051 : when we reach a set of the register or the end of the basic block.
15052 :
15053 : Note that this correctly handles the link that used to point from
15054 : I3 to I2. Also note that not much searching is typically done here
15055 : since most links don't point very far away. */
15056 :
15057 3615228 : int count = 0;
15058 3615228 : insn = start;
15059 3615228 : if (!insn || NOTE_P (insn))
15060 3556600 : insn = NEXT_INSN (link->insn);
15061 : else
15062 58628 : count = link->insn_count;
15063 11983666 : for (;
15064 15598894 : (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
15065 10782194 : || BB_HEAD (this_basic_block->next_bb) != insn));
15066 11983666 : insn = NEXT_INSN (insn))
15067 15552744 : if (DEBUG_INSN_P (insn))
15068 3300775 : continue;
15069 12251969 : else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
15070 : {
15071 3415506 : if (reg_referenced_p (reg, PATTERN (insn)))
15072 3415506 : place = insn;
15073 : break;
15074 : }
15075 8836463 : else if (CALL_P (insn)
15076 8836463 : && find_reg_fusage (insn, USE, reg))
15077 : {
15078 : place = insn;
15079 : break;
15080 : }
15081 8683071 : else if (INSN_P (insn) && reg_set_p (reg, insn))
15082 : break;
15083 8682891 : else if (count >= limit)
15084 : break;
15085 : else
15086 8682891 : count += 1;
15087 3615228 : link->insn_count = count;
15088 :
15089 : /* If we found a place to put the link, place it there unless there
15090 : is already a link to the same insn as LINK at that point. */
15091 :
15092 3615228 : if (place)
15093 : {
15094 3568898 : struct insn_link *link2;
15095 :
15096 4599639 : FOR_EACH_LOG_LINK (link2, place)
15097 1048024 : if (link2->insn == link->insn && link2->regno == link->regno)
15098 : break;
15099 :
15100 3568898 : if (link2 == NULL)
15101 : {
15102 3551615 : link->next = LOG_LINKS (place);
15103 3551615 : LOG_LINKS (place) = link;
15104 :
15105 : /* Set added_links_insn to the earliest insn we added a
15106 : link to. */
15107 3551615 : if (added_links_insn == 0
15108 3551615 : || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15109 2815453 : added_links_insn = place;
15110 : }
15111 : }
15112 : }
15113 16326491 : }
15114 :
15115 : /* Check for any register or memory mentioned in EQUIV that is not
15116 : mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15117 : of EXPR where some registers may have been replaced by constants. */
15118 :
15119 : static bool
15120 2799663 : unmentioned_reg_p (rtx equiv, rtx expr)
15121 : {
15122 2799663 : subrtx_iterator::array_type array;
15123 7338549 : FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15124 : {
15125 5965275 : const_rtx x = *iter;
15126 4095794 : if ((REG_P (x) || MEM_P (x))
15127 6362819 : && !reg_mentioned_p (x, expr))
15128 1426389 : return true;
15129 : }
15130 1373274 : return false;
15131 2799663 : }
15132 :
15133 : /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15134 : the reg-to-reg copy can usefully combine with later instructions, but we
15135 : do not want to combine the hard reg into later instructions, for that
15136 : restricts register allocation. */
15137 : static void
15138 1070192 : make_more_copies (void)
15139 : {
15140 1070192 : basic_block bb;
15141 :
15142 11781790 : FOR_EACH_BB_FN (bb, cfun)
15143 : {
15144 10711598 : rtx_insn *insn;
15145 :
15146 143171734 : FOR_BB_INSNS (bb, insn)
15147 : {
15148 132460136 : if (!NONDEBUG_INSN_P (insn))
15149 71761257 : continue;
15150 :
15151 60698879 : rtx set = single_set (insn);
15152 60698879 : if (!set)
15153 4131874 : continue;
15154 :
15155 56567005 : rtx dest = SET_DEST (set);
15156 56567005 : if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15157 32381656 : continue;
15158 :
15159 24185349 : rtx src = SET_SRC (set);
15160 24185349 : if (!(REG_P (src) && HARD_REGISTER_P (src)))
15161 21112709 : continue;
15162 3072640 : if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15163 9966 : continue;
15164 :
15165 3062674 : rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15166 :
15167 : /* The "original" pseudo copies have important attributes
15168 : attached, like pointerness. We want that for these copies
15169 : too, for use by insn recognition and later passes. */
15170 3062674 : set_reg_attrs_from_value (new_reg, dest);
15171 :
15172 3062674 : rtx_insn *new_insn = gen_move_insn (new_reg, src);
15173 3062674 : SET_SRC (set) = new_reg;
15174 3062674 : emit_insn_before (new_insn, insn);
15175 3062674 : df_insn_rescan (insn);
15176 : }
15177 : }
15178 1070192 : }
15179 :
15180 : /* Try combining insns through substitution. */
15181 : static void
15182 1070192 : rest_of_handle_combine (void)
15183 : {
15184 1070192 : make_more_copies ();
15185 :
15186 1070192 : df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15187 1070192 : df_note_add_problem ();
15188 1070192 : df_analyze ();
15189 :
15190 1070192 : regstat_init_n_sets_and_refs ();
15191 1070192 : reg_n_sets_max = max_reg_num ();
15192 :
15193 1070192 : bool rebuild_jump_labels_after_combine
15194 1070192 : = combine_instructions (get_insns (), max_reg_num ());
15195 :
15196 : /* Combining insns may have turned an indirect jump into a
15197 : direct jump. Rebuild the JUMP_LABEL fields of jumping
15198 : instructions. */
15199 1070192 : if (rebuild_jump_labels_after_combine)
15200 : {
15201 2367 : if (dom_info_available_p (CDI_DOMINATORS))
15202 0 : free_dominance_info (CDI_DOMINATORS);
15203 2367 : timevar_push (TV_JUMP);
15204 2367 : rebuild_jump_labels (get_insns ());
15205 2367 : cleanup_cfg (0);
15206 2367 : timevar_pop (TV_JUMP);
15207 : }
15208 :
15209 1070192 : regstat_free_n_sets_and_refs ();
15210 1070192 : }
15211 :
15212 : namespace {
15213 :
15214 : const pass_data pass_data_combine =
15215 : {
15216 : RTL_PASS, /* type */
15217 : "combine", /* name */
15218 : OPTGROUP_NONE, /* optinfo_flags */
15219 : TV_COMBINE, /* tv_id */
15220 : PROP_cfglayout, /* properties_required */
15221 : 0, /* properties_provided */
15222 : 0, /* properties_destroyed */
15223 : 0, /* todo_flags_start */
15224 : TODO_df_finish, /* todo_flags_finish */
15225 : };
15226 :
15227 : class pass_combine : public rtl_opt_pass
15228 : {
15229 : public:
15230 294536 : pass_combine (gcc::context *ctxt)
15231 589072 : : rtl_opt_pass (pass_data_combine, ctxt)
15232 : {}
15233 :
15234 : /* opt_pass methods: */
15235 1515929 : bool gate (function *) final override { return (optimize > 0); }
15236 1070192 : unsigned int execute (function *) final override
15237 : {
15238 1070192 : rest_of_handle_combine ();
15239 1070192 : return 0;
15240 : }
15241 :
15242 : }; // class pass_combine
15243 :
15244 : } // anon namespace
15245 :
15246 : rtl_opt_pass *
15247 294536 : make_pass_combine (gcc::context *ctxt)
15248 : {
15249 294536 : return new pass_combine (ctxt);
15250 : }
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