Line data Source code
1 : /* IA-32 common hooks.
2 : Copyright (C) 1988-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify
7 : it under the terms of the GNU General Public License as published by
8 : the Free Software Foundation; either version 3, or (at your option)
9 : any later version.
10 :
11 : GCC is distributed in the hope that it will be useful,
12 : but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : GNU General Public License for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "diagnostic-core.h"
24 : #include "tm.h"
25 : #include "memmodel.h"
26 : #include "tm_p.h"
27 : #include "common/common-target.h"
28 : #include "common/common-target-def.h"
29 : #include "opts.h"
30 : #include "flags.h"
31 :
32 : /* Define a set of ISAs which are available when a given ISA is
33 : enabled. MMX and SSE ISAs are handled separately. */
34 :
35 : #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 : #define OPTION_MASK_ISA_3DNOW_SET \
37 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 : #define OPTION_MASK_ISA_3DNOW_A_SET \
39 : (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 :
41 : #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 : #define OPTION_MASK_ISA_SSE2_SET \
43 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 : #define OPTION_MASK_ISA_SSE3_SET \
45 : (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 : #define OPTION_MASK_ISA_SSSE3_SET \
47 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 : #define OPTION_MASK_ISA_SSE4_1_SET \
49 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 : #define OPTION_MASK_ISA_SSE4_2_SET \
51 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 : #define OPTION_MASK_ISA_AVX_SET \
53 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 : | OPTION_MASK_ISA_XSAVE_SET)
55 : #define OPTION_MASK_ISA_FMA_SET \
56 : (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 : #define OPTION_MASK_ISA_AVX2_SET \
58 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 : #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 : #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 : #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 : (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 : #define OPTION_MASK_ISA_AVX512F_SET \
64 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 : #define OPTION_MASK_ISA_AVX512CD_SET \
66 : (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 : #define OPTION_MASK_ISA_AVX512DQ_SET \
68 : (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 : #define OPTION_MASK_ISA_AVX512BW_SET \
70 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 : #define OPTION_MASK_ISA_AVX512VL_SET \
72 : (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 : #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 : (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 : #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 : #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 : (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 : #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 : (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 : #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 : #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 : #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 : (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 : #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 : (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 : #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 : (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 : #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 : #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 : #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 : #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 : #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 : #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 : #define OPTION_MASK_ISA_XSAVES_SET \
96 : (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 : #define OPTION_MASK_ISA_XSAVEC_SET \
98 : (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 : #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 : #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 : #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 : #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 : #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 : #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 : #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 : #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 : #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 : #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 : #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 : #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 : #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 : #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 : #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 : #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 : #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
121 : #define OPTION_MASK_ISA_AVX10_1_SET \
122 : (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
123 : | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
124 : | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
125 : | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
126 : | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
127 : | OPTION_MASK_ISA_AVX512BITALG_SET)
128 : #define OPTION_MASK_ISA2_AVX10_1_SET \
129 : (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
130 : | OPTION_MASK_ISA2_AVX10_1)
131 : #define OPTION_MASK_ISA2_AVX10_2_SET \
132 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
133 : #define OPTION_MASK_ISA2_AMX_AVX512_SET \
134 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
135 : #define OPTION_MASK_ISA2_AMX_FP8_SET \
136 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
137 : #define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
138 : #define OPTION_MASK_ISA2_AMX_MOVRS_SET \
139 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS)
140 : #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
141 :
142 : /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
143 : as -msse4.2. */
144 : #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
145 :
146 : #define OPTION_MASK_ISA_SSE4A_SET \
147 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
148 : #define OPTION_MASK_ISA_FMA4_SET \
149 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
150 : | OPTION_MASK_ISA_AVX_SET)
151 : #define OPTION_MASK_ISA_XOP_SET \
152 : (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
153 : #define OPTION_MASK_ISA_LWP_SET \
154 : OPTION_MASK_ISA_LWP
155 :
156 : /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
157 : #define OPTION_MASK_ISA_AES_SET \
158 : (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
159 : #define OPTION_MASK_ISA_SHA_SET \
160 : (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
161 : #define OPTION_MASK_ISA_PCLMUL_SET \
162 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
163 :
164 : #define OPTION_MASK_ISA_ABM_SET \
165 : (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
166 :
167 : #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
168 : #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
169 : #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
170 : #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
171 : #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
172 : #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
173 : #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
174 : #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
175 : #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
176 : #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
177 : #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
178 : #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
179 :
180 : #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
181 : #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
182 : #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
183 : #define OPTION_MASK_ISA_F16C_SET \
184 : (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
185 : #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
186 : #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
187 : #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
188 : #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
189 : #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
190 : #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
191 : #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
192 : #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
193 : #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
194 : (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
195 : | OPTION_MASK_ISA_AVX_SET)
196 : #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
197 : #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
198 : #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
199 : #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
200 : #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
201 : #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
202 : #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
203 : #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
204 : #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
205 : #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
206 : #define OPTION_MASK_ISA2_WIDEKL_SET \
207 : (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
208 :
209 : /* Define a set of ISAs which aren't available when a given ISA is
210 : disabled. MMX and SSE ISAs are handled separately. */
211 :
212 : #define OPTION_MASK_ISA_MMX_UNSET \
213 : (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
214 : #define OPTION_MASK_ISA_3DNOW_UNSET \
215 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
216 : #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
217 :
218 : #define OPTION_MASK_ISA_SSE_UNSET \
219 : (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
220 : #define OPTION_MASK_ISA_SSE2_UNSET \
221 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
222 : #define OPTION_MASK_ISA_SSE3_UNSET \
223 : (OPTION_MASK_ISA_SSE3 \
224 : | OPTION_MASK_ISA_SSSE3_UNSET \
225 : | OPTION_MASK_ISA_SSE4A_UNSET )
226 : #define OPTION_MASK_ISA_SSSE3_UNSET \
227 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
228 : #define OPTION_MASK_ISA_SSE4_1_UNSET \
229 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
230 : #define OPTION_MASK_ISA_SSE4_2_UNSET \
231 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
232 : #define OPTION_MASK_ISA_AVX_UNSET \
233 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
234 : | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
235 : | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
236 : #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
237 : #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
238 : #define OPTION_MASK_ISA_XSAVE_UNSET \
239 : (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
240 : | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
241 : | OPTION_MASK_ISA_AVX_UNSET)
242 : #define OPTION_MASK_ISA2_XSAVE_UNSET \
243 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
244 : #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
245 : #define OPTION_MASK_ISA_AVX2_UNSET \
246 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
247 : #define OPTION_MASK_ISA2_AVX2_UNSET \
248 : (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
249 : | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
250 : | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
251 : #define OPTION_MASK_ISA_AVX512F_UNSET \
252 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
253 : | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
254 : | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
255 : | OPTION_MASK_ISA_AVX512VNNI_UNSET \
256 : | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
257 : #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
258 : #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
259 : #define OPTION_MASK_ISA_AVX512BW_UNSET \
260 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
261 : | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
262 : #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
263 : #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
264 : #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
265 : #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
266 : #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
267 : #define OPTION_MASK_ISA2_AVX512FP16_UNSET \
268 : (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
269 : #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
270 : #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
271 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
272 : #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
273 : #define OPTION_MASK_ISA2_AVX512BF16_UNSET \
274 : (OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
275 : #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
276 : #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
277 : #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
278 : #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
279 : #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
280 : #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
281 : #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
282 : #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
283 : #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
284 : #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
285 : #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
286 : #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
287 : #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
288 : #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
289 : #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
290 : #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
291 : #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
292 : #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
293 : #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
294 : #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
295 : #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
296 : #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
297 : #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
298 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
299 : #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
300 : #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
301 : (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
302 : | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
303 : | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
304 : | OPTION_MASK_ISA2_AMX_FP8_UNSET | OPTION_MASK_ISA2_AMX_MOVRS_UNSET)
305 : #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
306 : #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
307 : #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
308 : #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
309 : #define OPTION_MASK_ISA2_KL_UNSET \
310 : (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
311 : #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
312 : #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
313 : #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
314 : #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
315 : #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
316 : #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
317 : #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
318 : #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
319 : #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
320 : #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
321 : #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
322 : #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
323 : #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
324 : #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
325 : #define OPTION_MASK_ISA2_AVX10_1_UNSET \
326 : (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET)
327 : #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
328 : #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
329 : #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
330 : #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
331 : #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
332 : #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
333 :
334 : /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
335 : as -mno-sse4.1. */
336 : #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
337 :
338 : #define OPTION_MASK_ISA_SSE4A_UNSET \
339 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
340 :
341 : #define OPTION_MASK_ISA_FMA4_UNSET \
342 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
343 : #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
344 : #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
345 :
346 : #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
347 : #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
348 : #define OPTION_MASK_ISA_PCLMUL_UNSET \
349 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
350 : #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
351 : #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
352 : #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
353 : #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
354 : #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
355 : #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
356 : #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
357 : #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
358 : #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
359 : #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
360 : #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
361 : #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
362 : #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
363 :
364 : #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
365 : #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
366 : #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
367 : #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
368 :
369 : #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
370 : (OPTION_MASK_ISA_MMX_UNSET \
371 : | OPTION_MASK_ISA_SSE_UNSET)
372 :
373 : #define OPTION_MASK_ISA2_AVX512F_UNSET \
374 : (OPTION_MASK_ISA2_AVX512BW_UNSET \
375 : | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
376 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
377 : | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
378 : #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
379 : OPTION_MASK_ISA2_SSE_UNSET
380 : #define OPTION_MASK_ISA2_AVX_UNSET \
381 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
382 : | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
383 : | OPTION_MASK_ISA2_SM4_UNSET)
384 : #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
385 : #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
386 : #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
387 : #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
388 : #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
389 : #define OPTION_MASK_ISA2_SSE2_UNSET \
390 : (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
391 : #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
392 :
393 : #define OPTION_MASK_ISA2_AVX512BW_UNSET \
394 : (OPTION_MASK_ISA2_AVX512BF16_UNSET \
395 : | OPTION_MASK_ISA2_AVX512FP16_UNSET \
396 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
397 : | OPTION_MASK_ISA2_AVX512BMM_UNSET)
398 : #define OPTION_MASK_ISA2_AVX512CD_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
399 : #define OPTION_MASK_ISA2_AVX512DQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
400 : #define OPTION_MASK_ISA2_AVX512VL_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
401 : #define OPTION_MASK_ISA2_AVX512IFMA_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
402 : #define OPTION_MASK_ISA2_AVX512VNNI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
403 : #define OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
404 : #define OPTION_MASK_ISA2_AVX512VBMI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
405 : #define OPTION_MASK_ISA2_AVX512VBMI2_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
406 : #define OPTION_MASK_ISA2_AVX512BITALG_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
407 :
408 : /* Set 1 << value as value of -malign-FLAG option. */
409 :
410 : static void
411 1 : set_malign_value (const char **flag, unsigned value)
412 : {
413 1 : char *r = XNEWVEC (char, 6);
414 1 : sprintf (r, "%d", 1 << value);
415 1 : *flag = r;
416 1 : }
417 :
418 : /* Implement TARGET_HANDLE_OPTION. */
419 :
420 : bool
421 67658227 : ix86_handle_option (struct gcc_options *opts,
422 : struct gcc_options *opts_set ATTRIBUTE_UNUSED,
423 : const struct cl_decoded_option *decoded,
424 : location_t loc)
425 : {
426 67658227 : size_t code = decoded->opt_index;
427 67658227 : int value = decoded->value;
428 :
429 67658227 : switch (code)
430 : {
431 1973339 : case OPT_mgeneral_regs_only:
432 1973339 : if (value)
433 : {
434 1973339 : HOST_WIDE_INT general_regs_only_flags = 0;
435 1973339 : HOST_WIDE_INT general_regs_only_flags2 = 0;
436 :
437 : /* NB: Enable the GPR only instructions which are enabled
438 : implicitly by SSE ISAs unless they have been disabled
439 : explicitly. */
440 1973339 : if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
441 : {
442 6481 : if (!TARGET_EXPLICIT_CRC32_P (opts))
443 4570 : general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
444 6481 : if (!TARGET_EXPLICIT_POPCNT_P (opts))
445 4552 : general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
446 : }
447 1973339 : if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
448 : {
449 6889 : if (!TARGET_EXPLICIT_MWAIT_P (opts))
450 1973339 : general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
451 : }
452 :
453 : /* Disable MMX, SSE and x87 instructions if only
454 : general registers are allowed. */
455 1973339 : opts->x_ix86_isa_flags
456 1973339 : &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
457 1973339 : opts->x_ix86_isa_flags2
458 1973339 : &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
459 1973339 : opts->x_ix86_isa_flags |= general_regs_only_flags;
460 1973339 : opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
461 1973339 : opts->x_ix86_isa_flags_explicit
462 1973339 : |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
463 : | general_regs_only_flags);
464 1973339 : opts->x_ix86_isa_flags2_explicit
465 1973339 : |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
466 : | general_regs_only_flags2);
467 :
468 1973339 : opts->x_target_flags &= ~MASK_80387;
469 : }
470 : else
471 0 : gcc_unreachable ();
472 1973339 : return true;
473 :
474 3465 : case OPT_mmmx:
475 3465 : if (value)
476 : {
477 1646 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
478 1646 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
479 : }
480 : else
481 : {
482 1819 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
483 1819 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
484 : }
485 : return true;
486 :
487 83628 : case OPT_m3dnow:
488 83628 : if (value)
489 : {
490 83615 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
491 83615 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
492 : }
493 : else
494 : {
495 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
496 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
497 : }
498 : return true;
499 :
500 6029 : case OPT_m3dnowa:
501 6029 : if (value)
502 : {
503 6028 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
504 6028 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
505 : }
506 : else
507 : {
508 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
509 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
510 : }
511 : return true;
512 :
513 33888 : case OPT_msse:
514 33888 : if (value)
515 : {
516 33786 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
517 33786 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
518 : }
519 : else
520 : {
521 102 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
522 102 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
523 102 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
524 102 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
525 : }
526 : return true;
527 :
528 86958 : case OPT_msse2:
529 86958 : if (value)
530 : {
531 86843 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
532 86843 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
533 : }
534 : else
535 : {
536 115 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
537 115 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
538 115 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
539 115 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
540 : }
541 : return true;
542 :
543 24528 : case OPT_msse3:
544 24528 : if (value)
545 : {
546 24445 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
547 24445 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
548 : }
549 : else
550 : {
551 83 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
552 83 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
553 83 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
554 83 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
555 : }
556 : return true;
557 :
558 45805 : case OPT_mssse3:
559 45805 : if (value)
560 : {
561 45797 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
562 45797 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
563 : }
564 : else
565 : {
566 8 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
567 8 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
568 8 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
569 8 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
570 : }
571 : return true;
572 :
573 78715 : case OPT_msse4_1:
574 78715 : if (value)
575 : {
576 78688 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
577 78688 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
578 : }
579 : else
580 : {
581 27 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
582 27 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
583 27 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
584 27 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
585 : }
586 : return true;
587 :
588 29438 : case OPT_msse4_2:
589 29438 : if (value)
590 : {
591 29425 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
592 29425 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
593 : }
594 : else
595 : {
596 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
597 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
598 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
599 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
600 : }
601 : return true;
602 :
603 297860 : case OPT_mavx:
604 297860 : if (value)
605 : {
606 296237 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
607 296237 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
608 : }
609 : else
610 : {
611 1623 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
612 1623 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
613 1623 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
614 1623 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
615 : }
616 : return true;
617 :
618 612099 : case OPT_mavx2:
619 612099 : if (value)
620 : {
621 612023 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
622 612023 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
623 : }
624 : else
625 : {
626 76 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
627 76 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
628 76 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
629 76 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
630 : }
631 : return true;
632 :
633 5013741 : case OPT_mavx512f:
634 5013741 : if (value)
635 : {
636 5013626 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
637 5013626 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
638 : }
639 : else
640 : {
641 115 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
642 115 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
643 115 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
644 115 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
645 : }
646 : return true;
647 :
648 415508 : case OPT_mavx512cd:
649 415508 : if (value)
650 : {
651 415484 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
652 415484 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
653 : }
654 : else
655 : {
656 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
657 24 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
658 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512CD_UNSET;
659 24 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512CD_UNSET;
660 : }
661 : return true;
662 :
663 61959 : case OPT_mrdpid:
664 61959 : if (value)
665 : {
666 61958 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
667 61958 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
668 : }
669 : else
670 : {
671 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
672 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
673 : }
674 : return true;
675 :
676 362617 : case OPT_mgfni:
677 362617 : if (value)
678 : {
679 362604 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
680 362604 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
681 : }
682 : else
683 : {
684 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
685 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
686 : }
687 : return true;
688 :
689 124575 : case OPT_mshstk:
690 124575 : if (value)
691 : {
692 124563 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
693 124563 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
694 : }
695 : else
696 : {
697 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
698 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
699 : }
700 : return true;
701 :
702 90230 : case OPT_mvaes:
703 90230 : if (value)
704 : {
705 90218 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
706 90218 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
707 90218 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
708 90218 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
709 : }
710 : else
711 : {
712 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
713 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
714 : }
715 : return true;
716 :
717 74364 : case OPT_mvpclmulqdq:
718 74364 : if (value)
719 : {
720 74352 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
721 74352 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
722 : }
723 : else
724 : {
725 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
726 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
727 : }
728 : return true;
729 :
730 25363 : case OPT_mmovdiri:
731 25363 : if (value)
732 : {
733 25352 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
734 25352 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
735 : }
736 : else
737 : {
738 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
739 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
740 : }
741 : return true;
742 :
743 15373 : case OPT_mmovdir64b:
744 15373 : if (value)
745 : {
746 15362 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
747 15362 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
748 : }
749 : else
750 : {
751 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
752 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
753 : }
754 : return true;
755 :
756 15368 : case OPT_mcldemote:
757 15368 : if (value)
758 : {
759 15357 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
760 15357 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
761 : }
762 : else
763 : {
764 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
765 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
766 : }
767 : return true;
768 :
769 35551 : case OPT_mwaitpkg:
770 35551 : if (value)
771 : {
772 35540 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
773 35540 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
774 : }
775 : else
776 : {
777 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
778 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
779 : }
780 : return true;
781 :
782 71404 : case OPT_menqcmd:
783 71404 : if (value)
784 : {
785 71392 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
786 71392 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
787 : }
788 : else
789 : {
790 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
791 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
792 : }
793 : return true;
794 :
795 145566 : case OPT_mkl:
796 145566 : if (value)
797 : {
798 145554 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
799 145554 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
800 :
801 : /* The Keylocker instructions need XMM registers from SSE2. */
802 145554 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
803 145554 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
804 : }
805 : else
806 : {
807 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
808 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
809 : }
810 : return true;
811 :
812 154228 : case OPT_mwidekl:
813 154228 : if (value)
814 : {
815 154216 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
816 154216 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
817 :
818 : /* The Widekl instructions need XMM registers from SSE2. */
819 154216 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
820 154216 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
821 : }
822 : else
823 : {
824 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
825 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
826 : }
827 : return true;
828 :
829 87520 : case OPT_mserialize:
830 87520 : if (value)
831 : {
832 87507 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
833 87507 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
834 : }
835 : else
836 : {
837 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
838 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
839 : }
840 : return true;
841 :
842 46434 : case OPT_muintr:
843 46434 : if (value)
844 : {
845 46422 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
846 46422 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
847 : }
848 : else
849 : {
850 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
851 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
852 : }
853 : return true;
854 :
855 16907 : case OPT_mhreset:
856 16907 : if (value)
857 : {
858 16895 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
859 16895 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
860 : }
861 : else
862 : {
863 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
864 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
865 : }
866 : return true;
867 :
868 1437478 : case OPT_mavx512vbmi2:
869 1437478 : if (value)
870 : {
871 1437467 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
872 1437467 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
873 : }
874 : else
875 : {
876 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
877 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
878 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
879 11 : opts->x_ix86_isa_flags2_explicit
880 11 : |= OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
881 : }
882 : return true;
883 :
884 7946713 : case OPT_mavx512fp16:
885 7946713 : if (value)
886 : {
887 7946698 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
888 7946698 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
889 7946698 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
890 7946698 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
891 : }
892 : else
893 : {
894 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
895 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
896 : }
897 : return true;
898 :
899 282136 : case OPT_mavx512vnni:
900 282136 : if (value)
901 : {
902 282124 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
903 282124 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
904 : }
905 : else
906 : {
907 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
908 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
909 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VNNI_UNSET;
910 12 : opts->x_ix86_isa_flags2_explicit
911 12 : |= OPTION_MASK_ISA2_AVX512VNNI_UNSET;
912 : }
913 : return true;
914 :
915 184961 : case OPT_mavx512vpopcntdq:
916 184961 : if (value)
917 : {
918 184937 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
919 184937 : opts->x_ix86_isa_flags_explicit
920 184937 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
921 : }
922 : else
923 : {
924 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
925 24 : opts->x_ix86_isa_flags_explicit
926 24 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
927 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
928 24 : opts->x_ix86_isa_flags2_explicit
929 24 : |= OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
930 : }
931 : return true;
932 :
933 243097 : case OPT_mavx512bitalg:
934 243097 : if (value)
935 : {
936 243086 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
937 243086 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
938 : }
939 : else
940 : {
941 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
942 11 : opts->x_ix86_isa_flags_explicit
943 11 : |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
944 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BITALG_UNSET;
945 11 : opts->x_ix86_isa_flags2_explicit
946 11 : |= OPTION_MASK_ISA2_AVX512BITALG_UNSET;
947 : }
948 : return true;
949 :
950 418434 : case OPT_mavx512bf16:
951 418434 : if (value)
952 : {
953 418420 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
954 418420 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
955 418420 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
956 418420 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
957 : }
958 : else
959 : {
960 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
961 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
962 : }
963 : return true;
964 :
965 140468 : case OPT_mavx512bmm:
966 140468 : if (value)
967 : {
968 140457 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BMM_SET;
969 140457 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_SET;
970 140457 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
971 140457 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
972 : }
973 : else
974 : {
975 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BMM_UNSET;
976 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_UNSET;
977 : }
978 : return true;
979 :
980 155398 : case OPT_mavxvnni:
981 155398 : if (value)
982 : {
983 155384 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
984 155384 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
985 155384 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
986 155384 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
987 : }
988 : else
989 : {
990 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
991 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
992 : }
993 : return true;
994 :
995 111054 : case OPT_msgx:
996 111054 : if (value)
997 : {
998 111042 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
999 111042 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
1000 : }
1001 : else
1002 : {
1003 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
1004 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
1005 : }
1006 : return true;
1007 :
1008 71039 : case OPT_mpconfig:
1009 71039 : if (value)
1010 : {
1011 71028 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
1012 71028 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
1013 : }
1014 : else
1015 : {
1016 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
1017 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
1018 : }
1019 : return true;
1020 :
1021 61328 : case OPT_mwbnoinvd:
1022 61328 : if (value)
1023 : {
1024 61328 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1025 61328 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1026 : }
1027 : else
1028 : {
1029 0 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1030 0 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1031 : }
1032 : return true;
1033 :
1034 3606508 : case OPT_mavx512dq:
1035 3606508 : if (value)
1036 : {
1037 3606475 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1038 3606475 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1039 : }
1040 : else
1041 : {
1042 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1043 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1044 33 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512DQ_UNSET;
1045 33 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512DQ_UNSET;
1046 : }
1047 : return true;
1048 :
1049 6870995 : case OPT_mavx512bw:
1050 6870995 : if (value)
1051 : {
1052 6870938 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1053 6870938 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1054 : }
1055 : else
1056 : {
1057 57 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1058 57 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1059 57 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1060 57 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1061 : }
1062 : return true;
1063 :
1064 20510417 : case OPT_mavx512vl:
1065 20510417 : if (value)
1066 : {
1067 20510357 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1068 20510357 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1069 : }
1070 : else
1071 : {
1072 60 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1073 60 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1074 60 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VL_UNSET;
1075 60 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VL_UNSET;
1076 : }
1077 : return true;
1078 :
1079 146144 : case OPT_mavx512ifma:
1080 146144 : if (value)
1081 : {
1082 146132 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1083 146132 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1084 : }
1085 : else
1086 : {
1087 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1088 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1089 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1090 12 : opts->x_ix86_isa_flags2_explicit
1091 12 : |= OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1092 : }
1093 : return true;
1094 :
1095 301471 : case OPT_mavx512vbmi:
1096 301471 : if (value)
1097 : {
1098 301459 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1099 301459 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1100 : }
1101 : else
1102 : {
1103 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1104 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1105 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1106 12 : opts->x_ix86_isa_flags2_explicit
1107 12 : |= OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1108 : }
1109 : return true;
1110 :
1111 140910 : case OPT_mavx512vp2intersect:
1112 140910 : if (value)
1113 : {
1114 140898 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1115 140898 : opts->x_ix86_isa_flags2_explicit |=
1116 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1117 140898 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1118 140898 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1119 : }
1120 : else
1121 : {
1122 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1123 12 : opts->x_ix86_isa_flags2_explicit |=
1124 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1125 : }
1126 : return true;
1127 :
1128 97584 : case OPT_mtsxldtrk:
1129 97584 : if (value)
1130 : {
1131 97572 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1132 97572 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1133 : }
1134 : else
1135 : {
1136 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1137 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1138 : }
1139 : return true;
1140 :
1141 105064 : case OPT_mamx_tile:
1142 105064 : if (value)
1143 : {
1144 105052 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1145 105052 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1146 105052 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1147 105052 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1148 : }
1149 : else
1150 : {
1151 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1152 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1153 : }
1154 : return true;
1155 :
1156 75878 : case OPT_mamx_int8:
1157 75878 : if (value)
1158 : {
1159 75866 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1160 75866 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1161 : }
1162 : else
1163 : {
1164 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1165 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1166 : }
1167 : return true;
1168 :
1169 75881 : case OPT_mamx_bf16:
1170 75881 : if (value)
1171 : {
1172 75869 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1173 75869 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1174 : }
1175 : else
1176 : {
1177 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1178 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1179 : }
1180 : return true;
1181 :
1182 115751 : case OPT_mavxifma:
1183 115751 : if (value)
1184 : {
1185 115739 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1186 115739 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1187 115739 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1188 115739 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1189 : }
1190 : else
1191 : {
1192 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1193 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1194 : }
1195 : return true;
1196 :
1197 195394 : case OPT_mavxvnniint8:
1198 195394 : if (value)
1199 : {
1200 195381 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1201 195381 : opts->x_ix86_isa_flags2_explicit |=
1202 : OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1203 195381 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1204 195381 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1205 : }
1206 : else
1207 : {
1208 13 : opts->x_ix86_isa_flags2 &=
1209 : ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1210 13 : opts->x_ix86_isa_flags2_explicit |=
1211 : OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1212 : }
1213 : return true;
1214 :
1215 215337 : case OPT_mavxneconvert:
1216 215337 : if (value)
1217 : {
1218 215323 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1219 215323 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1220 215323 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1221 215323 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1222 : }
1223 : else
1224 : {
1225 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1226 14 : opts->x_ix86_isa_flags2_explicit
1227 14 : |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1228 : }
1229 : return true;
1230 :
1231 70695 : case OPT_mcmpccxadd:
1232 70695 : if (value)
1233 : {
1234 70683 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1235 70683 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1236 : }
1237 : else
1238 : {
1239 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1240 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1241 : }
1242 : return true;
1243 :
1244 70711 : case OPT_mamx_fp16:
1245 70711 : if (value)
1246 : {
1247 70699 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1248 70699 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1249 : }
1250 : else
1251 : {
1252 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1253 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1254 : }
1255 : return true;
1256 :
1257 70699 : case OPT_mprefetchi:
1258 70699 : if (value)
1259 : {
1260 70687 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1261 70687 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1262 : }
1263 : else
1264 : {
1265 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1266 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1267 : }
1268 : return true;
1269 :
1270 157711 : case OPT_mraoint:
1271 157711 : if (value)
1272 : {
1273 157699 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1274 157699 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1275 : }
1276 : else
1277 : {
1278 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1279 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1280 : }
1281 : return true;
1282 :
1283 75890 : case OPT_mamx_complex:
1284 75890 : if (value)
1285 : {
1286 75878 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1287 75878 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1288 : }
1289 : else
1290 : {
1291 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1292 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1293 : }
1294 : return true;
1295 :
1296 195395 : case OPT_mavxvnniint16:
1297 195395 : if (value)
1298 : {
1299 195382 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1300 195382 : opts->x_ix86_isa_flags2_explicit |=
1301 : OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1302 195382 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1303 195382 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1304 : }
1305 : else
1306 : {
1307 13 : opts->x_ix86_isa_flags2 &=
1308 : ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1309 13 : opts->x_ix86_isa_flags2_explicit |=
1310 : OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1311 : }
1312 : return true;
1313 :
1314 105388 : case OPT_msm3:
1315 105388 : if (value)
1316 : {
1317 105376 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1318 105376 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1319 105376 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1320 105376 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1321 : }
1322 : else
1323 : {
1324 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1325 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1326 : }
1327 : return true;
1328 :
1329 105802 : case OPT_msha512:
1330 105802 : if (value)
1331 : {
1332 105790 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1333 105790 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1334 105790 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1335 105790 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1336 : }
1337 : else
1338 : {
1339 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1340 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1341 : }
1342 : return true;
1343 :
1344 140873 : case OPT_msm4:
1345 140873 : if (value)
1346 : {
1347 140861 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1348 140861 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1349 140861 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1350 140861 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1351 : }
1352 : else
1353 : {
1354 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1355 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1356 : }
1357 : return true;
1358 :
1359 118 : case OPT_mapxf:
1360 118 : if (value)
1361 : {
1362 84 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1363 84 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1364 84 : opts->x_ix86_apx_features = apx_all;
1365 : }
1366 : else
1367 : {
1368 34 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1369 34 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1370 34 : opts->x_ix86_apx_features = apx_none;
1371 : }
1372 : return true;
1373 :
1374 27121 : case OPT_musermsr:
1375 27121 : if (value)
1376 : {
1377 27109 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1378 27109 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1379 : }
1380 : else
1381 : {
1382 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1383 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1384 : }
1385 : return true;
1386 :
1387 27 : case OPT_mavx10_1:
1388 27 : if (value)
1389 : {
1390 15 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
1391 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
1392 15 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1393 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1394 : }
1395 : else
1396 : {
1397 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
1398 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
1399 : }
1400 : return true;
1401 :
1402 7609706 : case OPT_mavx10_2:
1403 7609706 : if (value)
1404 : {
1405 7609692 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
1406 7609692 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
1407 7609692 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1408 7609692 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1409 : }
1410 : else
1411 : {
1412 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET;
1413 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET;
1414 : }
1415 : return true;
1416 :
1417 75893 : case OPT_mamx_avx512:
1418 75893 : if (value)
1419 : {
1420 75877 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1421 75877 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1422 75877 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
1423 75877 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
1424 : }
1425 : else
1426 : {
1427 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1428 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1429 : }
1430 : return true;
1431 :
1432 70712 : case OPT_mamx_fp8:
1433 70712 : if (value)
1434 : {
1435 70700 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP8_SET;
1436 70700 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_SET;
1437 : }
1438 : else
1439 : {
1440 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP8_UNSET;
1441 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_UNSET;
1442 : }
1443 : return true;
1444 :
1445 486377 : case OPT_mmovrs:
1446 486377 : if (value)
1447 : {
1448 486364 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
1449 486364 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
1450 : }
1451 : else
1452 : {
1453 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
1454 13 : opts->x_ix86_isa_flags2_explicit |=
1455 : OPTION_MASK_ISA2_MOVRS_UNSET;
1456 : }
1457 : return true;
1458 :
1459 75803 : case OPT_mamx_movrs:
1460 75803 : if (value)
1461 : {
1462 75791 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1463 75791 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1464 : }
1465 : else
1466 : {
1467 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1468 12 : opts->x_ix86_isa_flags2_explicit |=
1469 : OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1470 : }
1471 : return true;
1472 :
1473 357687 : case OPT_mfma:
1474 357687 : if (value)
1475 : {
1476 357675 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1477 357675 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1478 : }
1479 : else
1480 : {
1481 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1482 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1483 : }
1484 : return true;
1485 :
1486 121679 : case OPT_mrtm:
1487 121679 : if (value)
1488 : {
1489 121666 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1490 121666 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1491 : }
1492 : else
1493 : {
1494 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1495 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1496 : }
1497 : return true;
1498 :
1499 198 : case OPT_msse4:
1500 198 : if (value)
1501 : {
1502 151 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1503 151 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1504 : }
1505 : else
1506 : {
1507 47 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1508 47 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1509 47 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1510 47 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1511 : }
1512 : return true;
1513 :
1514 77382 : case OPT_msse4a:
1515 77382 : if (value)
1516 : {
1517 77380 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1518 77380 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1519 : }
1520 : else
1521 : {
1522 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1523 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1524 : }
1525 : return true;
1526 :
1527 92086 : case OPT_mfma4:
1528 92086 : if (value)
1529 : {
1530 92055 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1531 92055 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1532 : }
1533 : else
1534 : {
1535 31 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1536 31 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1537 : }
1538 : return true;
1539 :
1540 181782 : case OPT_mxop:
1541 181782 : if (value)
1542 : {
1543 181749 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1544 181749 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1545 : }
1546 : else
1547 : {
1548 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1549 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1550 : }
1551 : return true;
1552 :
1553 124861 : case OPT_mlwp:
1554 124861 : if (value)
1555 : {
1556 124848 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1557 124848 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1558 : }
1559 : else
1560 : {
1561 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1562 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1563 : }
1564 : return true;
1565 :
1566 58479 : case OPT_mabm:
1567 58479 : if (value)
1568 : {
1569 58475 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1570 58475 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1571 : }
1572 : else
1573 : {
1574 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1575 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1576 : }
1577 : return true;
1578 :
1579 316331 : case OPT_mbmi:
1580 316331 : if (value)
1581 : {
1582 316330 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1583 316330 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1584 : }
1585 : else
1586 : {
1587 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1588 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1589 : }
1590 : return true;
1591 :
1592 133876 : case OPT_mbmi2:
1593 133876 : if (value)
1594 : {
1595 133871 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1596 133871 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1597 : }
1598 : else
1599 : {
1600 5 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1601 5 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1602 : }
1603 : return true;
1604 :
1605 114521 : case OPT_mlzcnt:
1606 114521 : if (value)
1607 : {
1608 114515 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1609 114515 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1610 : }
1611 : else
1612 : {
1613 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1614 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1615 : }
1616 : return true;
1617 :
1618 265955 : case OPT_mtbm:
1619 265955 : if (value)
1620 : {
1621 265942 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1622 265942 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1623 : }
1624 : else
1625 : {
1626 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1627 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1628 : }
1629 : return true;
1630 :
1631 64568 : case OPT_mpopcnt:
1632 64568 : if (value)
1633 : {
1634 64552 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1635 64552 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1636 : }
1637 : else
1638 : {
1639 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1640 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1641 : }
1642 : return true;
1643 :
1644 17 : case OPT_msahf:
1645 17 : if (value)
1646 : {
1647 15 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1648 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1649 : }
1650 : else
1651 : {
1652 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1653 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1654 : }
1655 : return true;
1656 :
1657 67 : case OPT_mcx16:
1658 67 : if (value)
1659 : {
1660 65 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1661 65 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1662 : }
1663 : else
1664 : {
1665 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1666 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1667 : }
1668 : return true;
1669 :
1670 30 : case OPT_mmovbe:
1671 30 : if (value)
1672 : {
1673 25 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1674 25 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1675 : }
1676 : else
1677 : {
1678 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1679 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1680 : }
1681 : return true;
1682 :
1683 11134 : case OPT_mcrc32:
1684 11134 : if (value)
1685 : {
1686 11130 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1687 11130 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1688 : }
1689 : else
1690 : {
1691 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1692 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1693 : }
1694 : return true;
1695 :
1696 83760 : case OPT_maes:
1697 83760 : if (value)
1698 : {
1699 83758 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1700 83758 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1701 : }
1702 : else
1703 : {
1704 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1705 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1706 : }
1707 : return true;
1708 :
1709 144887 : case OPT_msha:
1710 144887 : if (value)
1711 : {
1712 144886 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1713 144886 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1714 : }
1715 : else
1716 : {
1717 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1718 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1719 : }
1720 : return true;
1721 :
1722 73777 : case OPT_mpclmul:
1723 73777 : if (value)
1724 : {
1725 73776 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1726 73776 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1727 : }
1728 : else
1729 : {
1730 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1731 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1732 : }
1733 : return true;
1734 :
1735 156495 : case OPT_mfsgsbase:
1736 156495 : if (value)
1737 : {
1738 156494 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1739 156494 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1740 : }
1741 : else
1742 : {
1743 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1744 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1745 : }
1746 : return true;
1747 :
1748 112429 : case OPT_mrdrnd:
1749 112429 : if (value)
1750 : {
1751 112428 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1752 112428 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1753 : }
1754 : else
1755 : {
1756 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1757 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1758 : }
1759 : return true;
1760 :
1761 25368 : case OPT_mptwrite:
1762 25368 : if (value)
1763 : {
1764 25357 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1765 25357 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1766 : }
1767 : else
1768 : {
1769 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1770 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1771 : }
1772 : return true;
1773 :
1774 132163 : case OPT_mf16c:
1775 132163 : if (value)
1776 : {
1777 132162 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1778 132162 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1779 : }
1780 : else
1781 : {
1782 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1783 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1784 : }
1785 : return true;
1786 :
1787 60647 : case OPT_mfxsr:
1788 60647 : if (value)
1789 : {
1790 60645 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1791 60645 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1792 : }
1793 : else
1794 : {
1795 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1796 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1797 : }
1798 : return true;
1799 :
1800 6927 : case OPT_mxsave:
1801 6927 : if (value)
1802 : {
1803 6921 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1804 6921 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1805 : }
1806 : else
1807 : {
1808 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1809 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1810 6 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1811 6 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1812 : }
1813 : return true;
1814 :
1815 85745 : case OPT_mxsaveopt:
1816 85745 : if (value)
1817 : {
1818 85744 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1819 85744 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1820 : }
1821 : else
1822 : {
1823 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1824 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1825 : }
1826 : return true;
1827 :
1828 71860 : case OPT_mxsavec:
1829 71860 : if (value)
1830 : {
1831 71858 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1832 71858 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1833 : }
1834 : else
1835 : {
1836 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1837 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1838 : }
1839 : return true;
1840 :
1841 91831 : case OPT_mxsaves:
1842 91831 : if (value)
1843 : {
1844 91829 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1845 91829 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1846 : }
1847 : else
1848 : {
1849 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1850 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1851 : }
1852 : return true;
1853 :
1854 95835 : case OPT_mrdseed:
1855 95835 : if (value)
1856 : {
1857 95833 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1858 95833 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1859 : }
1860 : else
1861 : {
1862 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1863 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1864 : }
1865 : return true;
1866 :
1867 59107 : case OPT_mprfchw:
1868 59107 : if (value)
1869 : {
1870 59105 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1871 59105 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1872 : }
1873 : else
1874 : {
1875 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1876 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1877 : }
1878 : return true;
1879 :
1880 60637 : case OPT_madx:
1881 60637 : if (value)
1882 : {
1883 60633 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1884 60633 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1885 : }
1886 : else
1887 : {
1888 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1889 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1890 : }
1891 : return true;
1892 :
1893 61921 : case OPT_mclflushopt:
1894 61921 : if (value)
1895 : {
1896 61919 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1897 61919 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1898 : }
1899 : else
1900 : {
1901 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1902 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1903 : }
1904 : return true;
1905 :
1906 61940 : case OPT_mclwb:
1907 61940 : if (value)
1908 : {
1909 61938 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1910 61938 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1911 : }
1912 : else
1913 : {
1914 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1915 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1916 : }
1917 : return true;
1918 :
1919 71453 : case OPT_mmwaitx:
1920 71453 : if (value)
1921 : {
1922 71451 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1923 71451 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1924 : }
1925 : else
1926 : {
1927 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1928 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1929 : }
1930 : return true;
1931 :
1932 25693 : case OPT_mmwait:
1933 25693 : if (value)
1934 : {
1935 25692 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1936 25692 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1937 : }
1938 : else
1939 : {
1940 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1941 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1942 : }
1943 : return true;
1944 :
1945 61367 : case OPT_mclzero:
1946 61367 : if (value)
1947 : {
1948 61365 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1949 61365 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1950 : }
1951 : else
1952 : {
1953 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1954 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1955 : }
1956 : return true;
1957 :
1958 71966 : case OPT_mpku:
1959 71966 : if (value)
1960 : {
1961 71953 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1962 71953 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1963 : }
1964 : else
1965 : {
1966 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1967 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1968 : }
1969 : return true;
1970 :
1971 :
1972 1 : case OPT_malign_loops_:
1973 1 : warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1974 : "use %<-falign-loops%>");
1975 1 : if (value > MAX_CODE_ALIGN)
1976 0 : error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1977 : value, MAX_CODE_ALIGN);
1978 : else
1979 1 : set_malign_value (&opts->x_str_align_loops, value);
1980 : return true;
1981 :
1982 0 : case OPT_malign_jumps_:
1983 0 : warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1984 : "use %<-falign-jumps%>");
1985 0 : if (value > MAX_CODE_ALIGN)
1986 0 : error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1987 : value, MAX_CODE_ALIGN);
1988 : else
1989 0 : set_malign_value (&opts->x_str_align_jumps, value);
1990 : return true;
1991 :
1992 0 : case OPT_malign_functions_:
1993 0 : warning_at (loc, 0,
1994 : "%<-malign-functions%> is obsolete, "
1995 : "use %<-falign-functions%>");
1996 0 : if (value > MAX_CODE_ALIGN)
1997 0 : error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1998 : value, MAX_CODE_ALIGN);
1999 : else
2000 0 : set_malign_value (&opts->x_str_align_functions, value);
2001 : return true;
2002 :
2003 20 : case OPT_mbranch_cost_:
2004 20 : if (value > 5)
2005 : {
2006 0 : error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
2007 0 : opts->x_ix86_branch_cost = 5;
2008 : }
2009 : return true;
2010 :
2011 : default:
2012 : return true;
2013 : }
2014 : }
2015 :
2016 : static const struct default_options ix86_option_optimization_table[] =
2017 : {
2018 : /* Enable redundant extension instructions removal at -O2 and higher. */
2019 : { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
2020 : /* Enable function splitting at -O2 and higher. */
2021 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
2022 : /* The STC algorithm produces the smallest code at -Os, for x86. */
2023 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
2024 : REORDER_BLOCKS_ALGORITHM_STC },
2025 :
2026 : /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2027 : loop unrolling at -O2. */
2028 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
2029 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
2030 : /* Turns off -frename-registers and -fweb which are enabled by
2031 : funroll-loops. */
2032 : { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
2033 : { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
2034 : /* Turn off -fschedule-insns by default. It tends to make the
2035 : problem with not enough registers even worse. */
2036 : { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
2037 :
2038 : #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2039 : SUBTARGET_OPTIMIZATION_OPTIONS,
2040 : #endif
2041 : { OPT_LEVELS_NONE, 0, NULL, 0 }
2042 : };
2043 :
2044 : /* Implement TARGET_OPTION_INIT_STRUCT. */
2045 :
2046 : static void
2047 48374170 : ix86_option_init_struct (struct gcc_options *opts)
2048 : {
2049 48374170 : if (TARGET_MACHO)
2050 : /* The Darwin libraries never set errno, so we might as well
2051 : avoid calling them when that's the only reason we would. */
2052 : opts->x_flag_errno_math = 0;
2053 :
2054 48374170 : opts->x_flag_pcc_struct_return = 2;
2055 48374170 : opts->x_flag_asynchronous_unwind_tables = 2;
2056 48374170 : }
2057 :
2058 : /* On the x86 -fsplit-stack and -fstack-protector both use the same
2059 : field in the TCB, so they cannot be used together. */
2060 :
2061 : static bool
2062 6364 : ix86_supports_split_stack (bool report,
2063 : struct gcc_options *opts ATTRIBUTE_UNUSED)
2064 : {
2065 : #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2066 6364 : if (!OPTION_GLIBC_P (opts))
2067 : #endif
2068 : {
2069 0 : if (report)
2070 0 : error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2071 0 : return false;
2072 : }
2073 :
2074 : bool ret = true;
2075 :
2076 : #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2077 : if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
2078 : {
2079 : if (report)
2080 : error ("%<-fsplit-stack%> requires "
2081 : "assembler support for CFI directives");
2082 : ret = false;
2083 : }
2084 : #endif
2085 :
2086 : return ret;
2087 : }
2088 :
2089 : /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2090 :
2091 : static enum unwind_info_type
2092 9230545 : i386_except_unwind_info (struct gcc_options *opts)
2093 : {
2094 : /* Honor the --enable-sjlj-exceptions configure switch. */
2095 : #ifdef CONFIG_SJLJ_EXCEPTIONS
2096 : if (CONFIG_SJLJ_EXCEPTIONS)
2097 : return UI_SJLJ;
2098 : #endif
2099 :
2100 : /* On windows 64, prefer SEH exceptions over anything else. */
2101 9230545 : if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
2102 : return UI_SEH;
2103 :
2104 9230545 : if (DWARF2_UNWIND_INFO)
2105 9230545 : return UI_DWARF2;
2106 :
2107 : return UI_SJLJ;
2108 : }
2109 :
2110 : #undef TARGET_EXCEPT_UNWIND_INFO
2111 : #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2112 :
2113 : #undef TARGET_DEFAULT_TARGET_FLAGS
2114 : #define TARGET_DEFAULT_TARGET_FLAGS \
2115 : (TARGET_DEFAULT \
2116 : | TARGET_SUBTARGET_DEFAULT \
2117 : | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2118 :
2119 : #undef TARGET_HANDLE_OPTION
2120 : #define TARGET_HANDLE_OPTION ix86_handle_option
2121 :
2122 : #undef TARGET_OPTION_OPTIMIZATION_TABLE
2123 : #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2124 : #undef TARGET_OPTION_INIT_STRUCT
2125 : #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2126 :
2127 : #undef TARGET_SUPPORTS_SPLIT_STACK
2128 : #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2129 :
2130 : /* This table must be in sync with enum processor_type in i386.h. */
2131 : const char *const processor_names[] =
2132 : {
2133 : "generic",
2134 : "i386",
2135 : "i486",
2136 : "pentium",
2137 : "lakemont",
2138 : "pentiumpro",
2139 : "pentium4",
2140 : "nocona",
2141 : "core2",
2142 : "nehalem",
2143 : "sandybridge",
2144 : "haswell",
2145 : "bonnell",
2146 : "silvermont",
2147 : "goldmont",
2148 : "goldmont-plus",
2149 : "tremont",
2150 : "sierraforest",
2151 : "grandridge",
2152 : "clearwaterforest",
2153 : "skylake",
2154 : "skylake-avx512",
2155 : "cannonlake",
2156 : "icelake-client",
2157 : "icelake-server",
2158 : "cascadelake",
2159 : "tigerlake",
2160 : "cooperlake",
2161 : "sapphirerapids",
2162 : "alderlake",
2163 : "rocketlake",
2164 : "graniterapids",
2165 : "graniterapids-d",
2166 : "arrowlake",
2167 : "arrowlake-s",
2168 : "pantherlake",
2169 : "diamondrapids",
2170 : "novalake",
2171 : "intel",
2172 : "lujiazui",
2173 : "yongfeng",
2174 : "shijidadao",
2175 : "geode",
2176 : "k6",
2177 : "athlon",
2178 : "k8",
2179 : "amdfam10",
2180 : "bdver1",
2181 : "bdver2",
2182 : "bdver3",
2183 : "bdver4",
2184 : "btver1",
2185 : "btver2",
2186 : "znver1",
2187 : "znver2",
2188 : "znver3",
2189 : "znver4",
2190 : "znver5",
2191 : "znver6",
2192 : "c86-4g-m4",
2193 : "c86-4g-m6",
2194 : "c86-4g-m7",
2195 : "c86-4g-m8"
2196 : };
2197 :
2198 : /* Guarantee that the array is aligned with enum processor_type. */
2199 : STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2200 :
2201 : const pta processor_alias_table[] =
2202 : {
2203 : {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2204 : {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2205 : {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2206 : {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2207 : {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2208 : 0, P_NONE},
2209 : {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2210 : {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2211 : {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2212 : 0, P_NONE},
2213 : {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2214 : {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2215 : 0, P_NONE},
2216 : {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2217 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2218 : {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2219 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2220 : {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2221 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2222 : {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2223 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2224 : {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2225 : {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2226 : {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2227 : 0, P_NONE},
2228 : {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2229 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2230 : {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2231 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2232 : {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2233 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2234 : {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2235 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2236 : {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2237 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2238 : {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2239 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2240 : {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2241 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2242 : | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2243 : {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2244 : M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2245 : {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2246 : M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2247 : {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2248 : M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2249 : {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2250 : M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2251 : {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2252 : PTA_SANDYBRIDGE,
2253 : M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2254 : {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2255 : PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2256 : {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2257 : PTA_IVYBRIDGE,
2258 : M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2259 : {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2260 : PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2261 : {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2262 : M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2263 : {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2264 : 0, P_PROC_DYNAMIC},
2265 : {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2266 : M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2267 : {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2268 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2269 : {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2270 : PTA_SKYLAKE_AVX512,
2271 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2272 : {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2273 : M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2274 : {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2275 : PTA_ICELAKE_CLIENT,
2276 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2277 : {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2278 : PTA_ROCKETLAKE,
2279 : M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2280 : {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2281 : PTA_ICELAKE_SERVER,
2282 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2283 : {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2284 : PTA_CASCADELAKE,
2285 : M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2286 : {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2287 : M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2288 : {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2289 : M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2290 : {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2291 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2292 : {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2293 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2294 : {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2295 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2296 : {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2297 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2298 : {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2299 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2300 : {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2301 : M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1},
2302 : {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2303 : PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2304 : P_PROC_AVX10_1},
2305 : {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2306 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2307 : {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2308 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2309 : {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2310 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2311 : {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2312 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2313 : {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS,
2314 : M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_2},
2315 : {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2316 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2317 : {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
2318 : M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
2319 : {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2320 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2321 : {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2322 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2323 : {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2324 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2325 : {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2326 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2327 : {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2328 : M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2329 : {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2330 : M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2331 : {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2332 : M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2333 : {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2334 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2335 : {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2336 : M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2337 : {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2338 : M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2339 : {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2340 : PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2341 : {"intel", PROCESSOR_INTEL, CPU_HASWELL, PTA_HASWELL,
2342 : M_VENDOR (VENDOR_INTEL), P_NONE},
2343 : {"geode", PROCESSOR_GEODE, CPU_GEODE,
2344 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2345 : {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2346 : {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2347 : {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2348 : {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2349 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2350 : {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2351 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2352 : {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2353 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2354 : {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2355 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2356 : {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2357 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2358 : {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2359 : {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2360 : 0, P_NONE},
2361 : {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2362 : 0, P_NONE},
2363 : {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2364 : 0, P_NONE},
2365 : {"eden-x2", PROCESSOR_K8, CPU_K8,
2366 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2367 : 0, P_NONE},
2368 : {"nano", PROCESSOR_K8, CPU_K8,
2369 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2370 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2371 : {"nano-1000", PROCESSOR_K8, CPU_K8,
2372 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2373 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2374 : {"nano-2000", PROCESSOR_K8, CPU_K8,
2375 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2376 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2377 : {"nano-3000", PROCESSOR_K8, CPU_K8,
2378 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2379 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2380 : {"nano-x2", PROCESSOR_K8, CPU_K8,
2381 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2382 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2383 : {"eden-x4", PROCESSOR_K8, CPU_K8,
2384 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2385 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2386 : {"nano-x4", PROCESSOR_K8, CPU_K8,
2387 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2388 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2389 : {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2390 : PTA_LUJIAZUI,
2391 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2392 : {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2393 : PTA_YONGFENG,
2394 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2395 : {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2396 : PTA_YONGFENG,
2397 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2398 : {"k8", PROCESSOR_K8, CPU_K8,
2399 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2400 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2401 : {"k8-sse3", PROCESSOR_K8, CPU_K8,
2402 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2403 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2404 : {"opteron", PROCESSOR_K8, CPU_K8,
2405 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2406 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2407 : {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2408 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2409 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2410 : {"athlon64", PROCESSOR_K8, CPU_K8,
2411 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2412 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2413 : {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2414 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2415 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2416 : {"athlon-fx", PROCESSOR_K8, CPU_K8,
2417 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2418 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2419 : {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2420 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2421 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2422 : 0, P_PROC_DYNAMIC},
2423 : {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2424 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2425 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2426 : M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2427 : {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2428 : PTA_BDVER1,
2429 : M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2430 : {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2431 : PTA_BDVER2,
2432 : M_CPU_SUBTYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2433 : {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2434 : PTA_BDVER3,
2435 : M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2436 : {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2437 : PTA_BDVER4,
2438 : M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2439 : {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2440 : PTA_ZNVER1,
2441 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2442 : {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2443 : PTA_ZNVER2,
2444 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2445 : {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2446 : PTA_ZNVER3,
2447 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2448 : {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2449 : PTA_ZNVER4,
2450 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2451 : {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2452 : PTA_ZNVER5,
2453 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2454 : {"znver6", PROCESSOR_ZNVER6, CPU_ZNVER5,
2455 : PTA_ZNVER6,
2456 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER6), P_PROC_AVX512F},
2457 : {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2458 : PTA_BTVER1,
2459 : M_CPU_TYPE (AMD_BTVER1), P_PROC_SSE4_A},
2460 : {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2461 : PTA_BTVER2,
2462 : M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2463 : {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
2464 : PTA_C86_4G_M4,
2465 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
2466 : {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
2467 : PTA_C86_4G_M6,
2468 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
2469 : {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
2470 : PTA_C86_4G_M7,
2471 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
2472 : {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8,
2473 : PTA_C86_4G_M8,
2474 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F},
2475 :
2476 : {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2477 : PTA_64BIT
2478 : | PTA_HLE /* flags are only used for -march switch. */,
2479 : 0, P_NONE},
2480 :
2481 : {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2482 : M_VENDOR (VENDOR_AMD), P_NONE},
2483 : {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2484 : M_CPU_TYPE (AMDFAM10H), P_NONE},
2485 : {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2486 : M_CPU_TYPE (AMDFAM15H), P_NONE},
2487 : {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2488 : M_CPU_TYPE (AMDFAM17H), P_NONE},
2489 : {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2490 : M_CPU_TYPE (AMDFAM19H), P_NONE},
2491 : {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2492 : M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
2493 : {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2494 : M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
2495 : {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2496 : M_VENDOR (VENDOR_HYGON), P_NONE},
2497 : {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2498 : M_CPU_TYPE (HYGONFAM18H), P_NONE},
2499 : };
2500 :
2501 : /* NB: processor_alias_table stops at the "generic" entry. */
2502 : unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
2503 : unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2504 :
2505 : /* Provide valid option values for -march and -mtune options. */
2506 :
2507 : vec<const char *>
2508 157845 : ix86_get_valid_option_values (int option_code,
2509 : const char *prefix ATTRIBUTE_UNUSED)
2510 : {
2511 157845 : vec<const char *> v;
2512 157845 : v.create (0);
2513 157845 : opt_code opt = (opt_code) option_code;
2514 :
2515 157845 : switch (opt)
2516 : {
2517 : case OPT_march_:
2518 72963 : for (unsigned i = 0; i < pta_size; i++)
2519 : {
2520 72360 : const char *name = processor_alias_table[i].name;
2521 72360 : gcc_checking_assert (name != NULL);
2522 72360 : v.safe_push (name);
2523 : }
2524 : #ifdef HAVE_LOCAL_CPU_DETECT
2525 : /* Add also "native" as possible value. */
2526 603 : v.safe_push ("native");
2527 : #endif
2528 :
2529 603 : break;
2530 : case OPT_mtune_:
2531 38592 : for (unsigned i = 0; i < PROCESSOR_max; i++)
2532 : {
2533 37989 : const char *name = processor_names[i];
2534 37989 : gcc_checking_assert (name != NULL);
2535 37989 : v.safe_push (name);
2536 : }
2537 : break;
2538 : default:
2539 : break;
2540 : }
2541 :
2542 157845 : return v;
2543 : }
2544 :
2545 : #undef TARGET_GET_VALID_OPTION_VALUES
2546 : #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2547 :
2548 : struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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