Line data Source code
1 : /* IA-32 common hooks.
2 : Copyright (C) 1988-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify
7 : it under the terms of the GNU General Public License as published by
8 : the Free Software Foundation; either version 3, or (at your option)
9 : any later version.
10 :
11 : GCC is distributed in the hope that it will be useful,
12 : but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : GNU General Public License for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "diagnostic-core.h"
24 : #include "tm.h"
25 : #include "memmodel.h"
26 : #include "tm_p.h"
27 : #include "common/common-target.h"
28 : #include "common/common-target-def.h"
29 : #include "opts.h"
30 : #include "flags.h"
31 :
32 : /* Define a set of ISAs which are available when a given ISA is
33 : enabled. MMX and SSE ISAs are handled separately. */
34 :
35 : #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 : #define OPTION_MASK_ISA_3DNOW_SET \
37 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 : #define OPTION_MASK_ISA_3DNOW_A_SET \
39 : (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 :
41 : #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 : #define OPTION_MASK_ISA_SSE2_SET \
43 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 : #define OPTION_MASK_ISA_SSE3_SET \
45 : (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 : #define OPTION_MASK_ISA_SSSE3_SET \
47 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 : #define OPTION_MASK_ISA_SSE4_1_SET \
49 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 : #define OPTION_MASK_ISA_SSE4_2_SET \
51 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 : #define OPTION_MASK_ISA_AVX_SET \
53 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 : | OPTION_MASK_ISA_XSAVE_SET)
55 : #define OPTION_MASK_ISA_FMA_SET \
56 : (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 : #define OPTION_MASK_ISA_AVX2_SET \
58 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 : #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 : #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 : #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 : (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 : #define OPTION_MASK_ISA_AVX512F_SET \
64 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 : #define OPTION_MASK_ISA_AVX512CD_SET \
66 : (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 : #define OPTION_MASK_ISA_AVX512DQ_SET \
68 : (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 : #define OPTION_MASK_ISA_AVX512BW_SET \
70 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 : #define OPTION_MASK_ISA_AVX512VL_SET \
72 : (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 : #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 : (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 : #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 : #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 : (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 : #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 : (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 : #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 : #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 : #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 : (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 : #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 : (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 : #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 : (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 : #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 : #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 : #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 : #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 : #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 : #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 : #define OPTION_MASK_ISA_XSAVES_SET \
96 : (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 : #define OPTION_MASK_ISA_XSAVEC_SET \
98 : (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 : #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 : #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 : #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 : #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 : #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 : #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 : #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 : #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 : #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 : #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 : #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 : #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 : #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 : #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 : #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 : #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 : #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
121 : #define OPTION_MASK_ISA_AVX10_1_SET \
122 : (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
123 : | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
124 : | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
125 : | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
126 : | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
127 : | OPTION_MASK_ISA_AVX512BITALG_SET)
128 : #define OPTION_MASK_ISA2_AVX10_1_SET \
129 : (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
130 : | OPTION_MASK_ISA2_AVX10_1)
131 : #define OPTION_MASK_ISA2_AVX10_2_SET \
132 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
133 : #define OPTION_MASK_ISA2_AMX_AVX512_SET \
134 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
135 : #define OPTION_MASK_ISA2_AMX_FP8_SET \
136 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
137 : #define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
138 : #define OPTION_MASK_ISA2_AMX_MOVRS_SET \
139 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS)
140 : #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
141 : #define OPTION_MASK_ISA2_AVX10V2AUX_SET \
142 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V2AUX)
143 : #define OPTION_MASK_ISA2_ACEV1_SET \
144 : (OPTION_MASK_ISA2_AVX10V2AUX_SET | OPTION_MASK_ISA2_ACEV1)
145 :
146 : /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
147 : as -msse4.2. */
148 : #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
149 :
150 : #define OPTION_MASK_ISA_SSE4A_SET \
151 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
152 : #define OPTION_MASK_ISA_FMA4_SET \
153 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
154 : | OPTION_MASK_ISA_AVX_SET)
155 : #define OPTION_MASK_ISA_XOP_SET \
156 : (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
157 : #define OPTION_MASK_ISA_LWP_SET \
158 : OPTION_MASK_ISA_LWP
159 :
160 : /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
161 : #define OPTION_MASK_ISA_AES_SET \
162 : (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
163 : #define OPTION_MASK_ISA_SHA_SET \
164 : (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
165 : #define OPTION_MASK_ISA_PCLMUL_SET \
166 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
167 :
168 : #define OPTION_MASK_ISA_ABM_SET \
169 : (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
170 :
171 : #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
172 : #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
173 : #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
174 : #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
175 : #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
176 : #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
177 : #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
178 : #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
179 : #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
180 : #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
181 : #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
182 : #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
183 :
184 : #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
185 : #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
186 : #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
187 : #define OPTION_MASK_ISA_F16C_SET \
188 : (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
189 : #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
190 : #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
191 : #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
192 : #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
193 : #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
194 : #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
195 : #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
196 : #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
197 : #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
198 : (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
199 : | OPTION_MASK_ISA_AVX_SET)
200 : #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
201 : #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
202 : #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
203 : #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
204 : #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
205 : #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
206 : #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
207 : #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
208 : #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
209 : #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
210 : #define OPTION_MASK_ISA2_WIDEKL_SET \
211 : (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
212 :
213 : /* Define a set of ISAs which aren't available when a given ISA is
214 : disabled. MMX and SSE ISAs are handled separately. */
215 :
216 : #define OPTION_MASK_ISA_MMX_UNSET \
217 : (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
218 : #define OPTION_MASK_ISA_3DNOW_UNSET \
219 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
220 : #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
221 :
222 : #define OPTION_MASK_ISA_SSE_UNSET \
223 : (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
224 : #define OPTION_MASK_ISA_SSE2_UNSET \
225 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
226 : #define OPTION_MASK_ISA_SSE3_UNSET \
227 : (OPTION_MASK_ISA_SSE3 \
228 : | OPTION_MASK_ISA_SSSE3_UNSET \
229 : | OPTION_MASK_ISA_SSE4A_UNSET )
230 : #define OPTION_MASK_ISA_SSSE3_UNSET \
231 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
232 : #define OPTION_MASK_ISA_SSE4_1_UNSET \
233 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
234 : #define OPTION_MASK_ISA_SSE4_2_UNSET \
235 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
236 : #define OPTION_MASK_ISA_AVX_UNSET \
237 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
238 : | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
239 : | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
240 : #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
241 : #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
242 : #define OPTION_MASK_ISA_XSAVE_UNSET \
243 : (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
244 : | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
245 : | OPTION_MASK_ISA_AVX_UNSET)
246 : #define OPTION_MASK_ISA2_XSAVE_UNSET \
247 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
248 : #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
249 : #define OPTION_MASK_ISA_AVX2_UNSET \
250 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
251 : #define OPTION_MASK_ISA2_AVX2_UNSET \
252 : (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
253 : | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
254 : | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
255 : #define OPTION_MASK_ISA_AVX512F_UNSET \
256 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
257 : | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
258 : | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
259 : | OPTION_MASK_ISA_AVX512VNNI_UNSET \
260 : | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
261 : #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
262 : #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
263 : #define OPTION_MASK_ISA_AVX512BW_UNSET \
264 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
265 : | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
266 : #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
267 : #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
268 : #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
269 : #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
270 : #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
271 : #define OPTION_MASK_ISA2_AVX512FP16_UNSET \
272 : (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
273 : #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
274 : #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
275 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
276 : #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
277 : #define OPTION_MASK_ISA2_AVX512BF16_UNSET \
278 : (OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
279 : #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
280 : #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
281 : #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
282 : #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
283 : #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
284 : #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
285 : #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
286 : #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
287 : #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
288 : #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
289 : #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
290 : #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
291 : #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
292 : #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
293 : #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
294 : #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
295 : #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
296 : #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
297 : #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
298 : #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
299 : #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
300 : #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
301 : #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
302 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
303 : #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
304 : #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
305 : (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
306 : | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
307 : | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
308 : | OPTION_MASK_ISA2_AMX_FP8_UNSET | OPTION_MASK_ISA2_AMX_MOVRS_UNSET)
309 : #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
310 : #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
311 : #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
312 : #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
313 : #define OPTION_MASK_ISA2_KL_UNSET \
314 : (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
315 : #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
316 : #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
317 : #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
318 : #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
319 : #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
320 : #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
321 : #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
322 : #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
323 : #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
324 : #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
325 : #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
326 : #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
327 : #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
328 : #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
329 : #define OPTION_MASK_ISA2_AVX10_1_UNSET \
330 : (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
331 : | OPTION_MASK_ISA2_AVX10V2AUX_UNSET)
332 : #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
333 : #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
334 : #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
335 : #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
336 : #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
337 : #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
338 : #define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \
339 : (OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET)
340 : #define OPTION_MASK_ISA2_ACEV1_UNSET OPTION_MASK_ISA2_ACEV1
341 :
342 : /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
343 : as -mno-sse4.1. */
344 : #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
345 :
346 : #define OPTION_MASK_ISA_SSE4A_UNSET \
347 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
348 :
349 : #define OPTION_MASK_ISA_FMA4_UNSET \
350 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
351 : #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
352 : #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
353 :
354 : #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
355 : #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
356 : #define OPTION_MASK_ISA_PCLMUL_UNSET \
357 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
358 : #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
359 : #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
360 : #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
361 : #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
362 : #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
363 : #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
364 : #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
365 : #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
366 : #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
367 : #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
368 : #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
369 : #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
370 : #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
371 :
372 : #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
373 : #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
374 : #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
375 : #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
376 :
377 : #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
378 : (OPTION_MASK_ISA_MMX_UNSET \
379 : | OPTION_MASK_ISA_SSE_UNSET)
380 :
381 : #define OPTION_MASK_ISA2_AVX512F_UNSET \
382 : (OPTION_MASK_ISA2_AVX512BW_UNSET \
383 : | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
384 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
385 : | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
386 : #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
387 : OPTION_MASK_ISA2_SSE_UNSET
388 : #define OPTION_MASK_ISA2_AVX_UNSET \
389 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
390 : | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
391 : | OPTION_MASK_ISA2_SM4_UNSET)
392 : #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
393 : #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
394 : #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
395 : #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
396 : #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
397 : #define OPTION_MASK_ISA2_SSE2_UNSET \
398 : (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
399 : #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
400 :
401 : #define OPTION_MASK_ISA2_AVX512BW_UNSET \
402 : (OPTION_MASK_ISA2_AVX512BF16_UNSET \
403 : | OPTION_MASK_ISA2_AVX512FP16_UNSET \
404 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
405 : | OPTION_MASK_ISA2_AVX512BMM_UNSET)
406 : #define OPTION_MASK_ISA2_AVX512CD_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
407 : #define OPTION_MASK_ISA2_AVX512DQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
408 : #define OPTION_MASK_ISA2_AVX512VL_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
409 : #define OPTION_MASK_ISA2_AVX512IFMA_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
410 : #define OPTION_MASK_ISA2_AVX512VNNI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
411 : #define OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
412 : #define OPTION_MASK_ISA2_AVX512VBMI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
413 : #define OPTION_MASK_ISA2_AVX512VBMI2_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
414 : #define OPTION_MASK_ISA2_AVX512BITALG_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
415 :
416 : /* Set 1 << value as value of -malign-FLAG option. */
417 :
418 : static void
419 1 : set_malign_value (const char **flag, unsigned value)
420 : {
421 1 : char *r = XNEWVEC (char, 6);
422 1 : sprintf (r, "%d", 1 << value);
423 1 : *flag = r;
424 1 : }
425 :
426 : /* Implement TARGET_HANDLE_OPTION. */
427 :
428 : bool
429 70018402 : ix86_handle_option (struct gcc_options *opts,
430 : struct gcc_options *opts_set ATTRIBUTE_UNUSED,
431 : const struct cl_decoded_option *decoded,
432 : location_t loc)
433 : {
434 70018402 : size_t code = decoded->opt_index;
435 70018402 : int value = decoded->value;
436 :
437 70018402 : switch (code)
438 : {
439 1981195 : case OPT_mgeneral_regs_only:
440 1981195 : if (value)
441 : {
442 1981195 : HOST_WIDE_INT general_regs_only_flags = 0;
443 1981195 : HOST_WIDE_INT general_regs_only_flags2 = 0;
444 :
445 : /* NB: Enable the GPR only instructions which are enabled
446 : implicitly by SSE ISAs unless they have been disabled
447 : explicitly. */
448 1981195 : if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
449 : {
450 6500 : if (!TARGET_EXPLICIT_CRC32_P (opts))
451 4589 : general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
452 6500 : if (!TARGET_EXPLICIT_POPCNT_P (opts))
453 4571 : general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
454 : }
455 1981195 : if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
456 : {
457 6908 : if (!TARGET_EXPLICIT_MWAIT_P (opts))
458 1981195 : general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
459 : }
460 :
461 : /* Disable MMX, SSE and x87 instructions if only
462 : general registers are allowed. */
463 1981195 : opts->x_ix86_isa_flags
464 1981195 : &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
465 1981195 : opts->x_ix86_isa_flags2
466 1981195 : &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
467 1981195 : opts->x_ix86_isa_flags |= general_regs_only_flags;
468 1981195 : opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
469 1981195 : opts->x_ix86_isa_flags_explicit
470 1981195 : |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
471 : | general_regs_only_flags);
472 1981195 : opts->x_ix86_isa_flags2_explicit
473 1981195 : |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
474 : | general_regs_only_flags2);
475 :
476 1981195 : opts->x_target_flags &= ~MASK_80387;
477 : }
478 : else
479 0 : gcc_unreachable ();
480 1981195 : return true;
481 :
482 3468 : case OPT_mmmx:
483 3468 : if (value)
484 : {
485 1648 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
486 1648 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
487 : }
488 : else
489 : {
490 1820 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
491 1820 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
492 : }
493 : return true;
494 :
495 85435 : case OPT_m3dnow:
496 85435 : if (value)
497 : {
498 85419 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
499 85419 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
500 : }
501 : else
502 : {
503 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
504 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
505 : }
506 : return true;
507 :
508 6073 : case OPT_m3dnowa:
509 6073 : if (value)
510 : {
511 6072 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
512 6072 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
513 : }
514 : else
515 : {
516 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
517 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
518 : }
519 : return true;
520 :
521 34129 : case OPT_msse:
522 34129 : if (value)
523 : {
524 34024 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
525 34024 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
526 : }
527 : else
528 : {
529 105 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
530 105 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
531 105 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
532 105 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
533 : }
534 : return true;
535 :
536 87407 : case OPT_msse2:
537 87407 : if (value)
538 : {
539 87284 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
540 87284 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
541 : }
542 : else
543 : {
544 123 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
545 123 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
546 123 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
547 123 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
548 : }
549 : return true;
550 :
551 24958 : case OPT_msse3:
552 24958 : if (value)
553 : {
554 24873 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
555 24873 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
556 : }
557 : else
558 : {
559 85 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
560 85 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
561 85 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
562 85 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
563 : }
564 : return true;
565 :
566 46278 : case OPT_mssse3:
567 46278 : if (value)
568 : {
569 46268 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
570 46268 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
571 : }
572 : else
573 : {
574 10 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
575 10 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
576 10 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
577 10 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
578 : }
579 : return true;
580 :
581 79278 : case OPT_msse4_1:
582 79278 : if (value)
583 : {
584 79246 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
585 79246 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
586 : }
587 : else
588 : {
589 32 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
590 32 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
591 32 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
592 32 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
593 : }
594 : return true;
595 :
596 29876 : case OPT_msse4_2:
597 29876 : if (value)
598 : {
599 29862 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
600 29862 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
601 : }
602 : else
603 : {
604 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
605 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
606 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
607 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
608 : }
609 : return true;
610 :
611 300412 : case OPT_mavx:
612 300412 : if (value)
613 : {
614 298768 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
615 298768 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
616 : }
617 : else
618 : {
619 1644 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
620 1644 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
621 1644 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
622 1644 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
623 : }
624 : return true;
625 :
626 614145 : case OPT_mavx2:
627 614145 : if (value)
628 : {
629 614066 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
630 614066 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
631 : }
632 : else
633 : {
634 79 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
635 79 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
636 79 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
637 79 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
638 : }
639 : return true;
640 :
641 5014134 : case OPT_mavx512f:
642 5014134 : if (value)
643 : {
644 5013990 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
645 5013990 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
646 : }
647 : else
648 : {
649 144 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
650 144 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
651 144 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
652 144 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
653 : }
654 : return true;
655 :
656 415767 : case OPT_mavx512cd:
657 415767 : if (value)
658 : {
659 415741 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
660 415741 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
661 : }
662 : else
663 : {
664 26 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
665 26 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
666 26 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512CD_UNSET;
667 26 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512CD_UNSET;
668 : }
669 : return true;
670 :
671 63297 : case OPT_mrdpid:
672 63297 : if (value)
673 : {
674 63296 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
675 63296 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
676 : }
677 : else
678 : {
679 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
680 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
681 : }
682 : return true;
683 :
684 365771 : case OPT_mgfni:
685 365771 : if (value)
686 : {
687 365752 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
688 365752 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
689 : }
690 : else
691 : {
692 19 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
693 19 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
694 : }
695 : return true;
696 :
697 125163 : case OPT_mshstk:
698 125163 : if (value)
699 : {
700 125149 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
701 125149 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
702 : }
703 : else
704 : {
705 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
706 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
707 : }
708 : return true;
709 :
710 90592 : case OPT_mvaes:
711 90592 : if (value)
712 : {
713 90578 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
714 90578 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
715 90578 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
716 90578 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
717 : }
718 : else
719 : {
720 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
721 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
722 : }
723 : return true;
724 :
725 75690 : case OPT_mvpclmulqdq:
726 75690 : if (value)
727 : {
728 75676 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
729 75676 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
730 : }
731 : else
732 : {
733 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
734 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
735 : }
736 : return true;
737 :
738 25464 : case OPT_mmovdiri:
739 25464 : if (value)
740 : {
741 25451 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
742 25451 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
743 : }
744 : else
745 : {
746 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
747 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
748 : }
749 : return true;
750 :
751 15434 : case OPT_mmovdir64b:
752 15434 : if (value)
753 : {
754 15421 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
755 15421 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
756 : }
757 : else
758 : {
759 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
760 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
761 : }
762 : return true;
763 :
764 15430 : case OPT_mcldemote:
765 15430 : if (value)
766 : {
767 15417 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
768 15417 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
769 : }
770 : else
771 : {
772 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
773 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
774 : }
775 : return true;
776 :
777 35693 : case OPT_mwaitpkg:
778 35693 : if (value)
779 : {
780 35680 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
781 35680 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
782 : }
783 : else
784 : {
785 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
786 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
787 : }
788 : return true;
789 :
790 72718 : case OPT_menqcmd:
791 72718 : if (value)
792 : {
793 72704 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
794 72704 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
795 : }
796 : else
797 : {
798 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
799 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
800 : }
801 : return true;
802 :
803 147888 : case OPT_mkl:
804 147888 : if (value)
805 : {
806 147874 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
807 147874 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
808 :
809 : /* The Keylocker instructions need XMM registers from SSE2. */
810 147874 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
811 147874 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
812 : }
813 : else
814 : {
815 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
816 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
817 : }
818 : return true;
819 :
820 156590 : case OPT_mwidekl:
821 156590 : if (value)
822 : {
823 156576 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
824 156576 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
825 :
826 : /* The Widekl instructions need XMM registers from SSE2. */
827 156576 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
828 156576 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
829 : }
830 : else
831 : {
832 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
833 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
834 : }
835 : return true;
836 :
837 89602 : case OPT_mserialize:
838 89602 : if (value)
839 : {
840 89587 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
841 89587 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
842 : }
843 : else
844 : {
845 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
846 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
847 : }
848 : return true;
849 :
850 46616 : case OPT_muintr:
851 46616 : if (value)
852 : {
853 46602 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
854 46602 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
855 : }
856 : else
857 : {
858 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
859 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
860 : }
861 : return true;
862 :
863 16969 : case OPT_mhreset:
864 16969 : if (value)
865 : {
866 16955 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
867 16955 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
868 : }
869 : else
870 : {
871 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
872 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
873 : }
874 : return true;
875 :
876 1438993 : case OPT_mavx512vbmi2:
877 1438993 : if (value)
878 : {
879 1438980 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
880 1438980 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
881 : }
882 : else
883 : {
884 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
885 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
886 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
887 13 : opts->x_ix86_isa_flags2_explicit
888 13 : |= OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
889 : }
890 : return true;
891 :
892 7953904 : case OPT_mavx512fp16:
893 7953904 : if (value)
894 : {
895 7953887 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
896 7953887 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
897 7953887 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
898 7953887 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
899 : }
900 : else
901 : {
902 17 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
903 17 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
904 : }
905 : return true;
906 :
907 282426 : case OPT_mavx512vnni:
908 282426 : if (value)
909 : {
910 282412 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
911 282412 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
912 : }
913 : else
914 : {
915 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
916 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
917 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VNNI_UNSET;
918 14 : opts->x_ix86_isa_flags2_explicit
919 14 : |= OPTION_MASK_ISA2_AVX512VNNI_UNSET;
920 : }
921 : return true;
922 :
923 185155 : case OPT_mavx512vpopcntdq:
924 185155 : if (value)
925 : {
926 185129 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
927 185129 : opts->x_ix86_isa_flags_explicit
928 185129 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
929 : }
930 : else
931 : {
932 26 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
933 26 : opts->x_ix86_isa_flags_explicit
934 26 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
935 26 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
936 26 : opts->x_ix86_isa_flags2_explicit
937 26 : |= OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
938 : }
939 : return true;
940 :
941 243350 : case OPT_mavx512bitalg:
942 243350 : if (value)
943 : {
944 243337 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
945 243337 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
946 : }
947 : else
948 : {
949 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
950 13 : opts->x_ix86_isa_flags_explicit
951 13 : |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
952 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BITALG_UNSET;
953 13 : opts->x_ix86_isa_flags2_explicit
954 13 : |= OPTION_MASK_ISA2_AVX512BITALG_UNSET;
955 : }
956 : return true;
957 :
958 418851 : case OPT_mavx512bf16:
959 418851 : if (value)
960 : {
961 418826 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
962 418826 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
963 418826 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
964 418826 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
965 : }
966 : else
967 : {
968 25 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
969 25 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
970 : }
971 : return true;
972 :
973 141030 : case OPT_mavx512bmm:
974 141030 : if (value)
975 : {
976 141017 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BMM_SET;
977 141017 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_SET;
978 141017 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
979 141017 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
980 : }
981 : else
982 : {
983 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BMM_UNSET;
984 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_UNSET;
985 : }
986 : return true;
987 :
988 157759 : case OPT_mavxvnni:
989 157759 : if (value)
990 : {
991 157743 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
992 157743 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
993 157743 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
994 157743 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
995 : }
996 : else
997 : {
998 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
999 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
1000 : }
1001 : return true;
1002 :
1003 112592 : case OPT_msgx:
1004 112592 : if (value)
1005 : {
1006 112578 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
1007 112578 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
1008 : }
1009 : else
1010 : {
1011 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
1012 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
1013 : }
1014 : return true;
1015 :
1016 72353 : case OPT_mpconfig:
1017 72353 : if (value)
1018 : {
1019 72340 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
1020 72340 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
1021 : }
1022 : else
1023 : {
1024 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
1025 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
1026 : }
1027 : return true;
1028 :
1029 62602 : case OPT_mwbnoinvd:
1030 62602 : if (value)
1031 : {
1032 62602 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1033 62602 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1034 : }
1035 : else
1036 : {
1037 0 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1038 0 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1039 : }
1040 : return true;
1041 :
1042 3608479 : case OPT_mavx512dq:
1043 3608479 : if (value)
1044 : {
1045 3608444 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1046 3608444 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1047 : }
1048 : else
1049 : {
1050 35 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1051 35 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1052 35 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512DQ_UNSET;
1053 35 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512DQ_UNSET;
1054 : }
1055 : return true;
1056 :
1057 6872494 : case OPT_mavx512bw:
1058 6872494 : if (value)
1059 : {
1060 6872435 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1061 6872435 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1062 : }
1063 : else
1064 : {
1065 59 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1066 59 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1067 59 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1068 59 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1069 : }
1070 : return true;
1071 :
1072 20520893 : case OPT_mavx512vl:
1073 20520893 : if (value)
1074 : {
1075 20520832 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1076 20520832 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1077 : }
1078 : else
1079 : {
1080 61 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1081 61 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1082 61 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VL_UNSET;
1083 61 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VL_UNSET;
1084 : }
1085 : return true;
1086 :
1087 146297 : case OPT_mavx512ifma:
1088 146297 : if (value)
1089 : {
1090 146283 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1091 146283 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1092 : }
1093 : else
1094 : {
1095 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1096 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1097 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1098 14 : opts->x_ix86_isa_flags2_explicit
1099 14 : |= OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1100 : }
1101 : return true;
1102 :
1103 301789 : case OPT_mavx512vbmi:
1104 301789 : if (value)
1105 : {
1106 301769 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1107 301769 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1108 : }
1109 : else
1110 : {
1111 20 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1112 20 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1113 20 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1114 20 : opts->x_ix86_isa_flags2_explicit
1115 20 : |= OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1116 : }
1117 : return true;
1118 :
1119 143212 : case OPT_mavx512vp2intersect:
1120 143212 : if (value)
1121 : {
1122 143198 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1123 143198 : opts->x_ix86_isa_flags2_explicit |=
1124 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1125 143198 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1126 143198 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1127 : }
1128 : else
1129 : {
1130 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1131 14 : opts->x_ix86_isa_flags2_explicit |=
1132 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1133 : }
1134 : return true;
1135 :
1136 99706 : case OPT_mtsxldtrk:
1137 99706 : if (value)
1138 : {
1139 99692 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1140 99692 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1141 : }
1142 : else
1143 : {
1144 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1145 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1146 : }
1147 : return true;
1148 :
1149 107226 : case OPT_mamx_tile:
1150 107226 : if (value)
1151 : {
1152 107212 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1153 107212 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1154 107212 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1155 107212 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1156 : }
1157 : else
1158 : {
1159 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1160 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1161 : }
1162 : return true;
1163 :
1164 77920 : case OPT_mamx_int8:
1165 77920 : if (value)
1166 : {
1167 77906 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1168 77906 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1169 : }
1170 : else
1171 : {
1172 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1173 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1174 : }
1175 : return true;
1176 :
1177 77923 : case OPT_mamx_bf16:
1178 77923 : if (value)
1179 : {
1180 77909 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1181 77909 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1182 : }
1183 : else
1184 : {
1185 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1186 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1187 : }
1188 : return true;
1189 :
1190 117954 : case OPT_mavxifma:
1191 117954 : if (value)
1192 : {
1193 117940 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1194 117940 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1195 117940 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1196 117940 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1197 : }
1198 : else
1199 : {
1200 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1201 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1202 : }
1203 : return true;
1204 :
1205 197915 : case OPT_mavxvnniint8:
1206 197915 : if (value)
1207 : {
1208 197900 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1209 197900 : opts->x_ix86_isa_flags2_explicit |=
1210 : OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1211 197900 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1212 197900 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1213 : }
1214 : else
1215 : {
1216 15 : opts->x_ix86_isa_flags2 &=
1217 : ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1218 15 : opts->x_ix86_isa_flags2_explicit |=
1219 : OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1220 : }
1221 : return true;
1222 :
1223 217950 : case OPT_mavxneconvert:
1224 217950 : if (value)
1225 : {
1226 217925 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1227 217925 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1228 217925 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1229 217925 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1230 : }
1231 : else
1232 : {
1233 25 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1234 25 : opts->x_ix86_isa_flags2_explicit
1235 25 : |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1236 : }
1237 : return true;
1238 :
1239 72001 : case OPT_mcmpccxadd:
1240 72001 : if (value)
1241 : {
1242 71987 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1243 71987 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1244 : }
1245 : else
1246 : {
1247 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1248 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1249 : }
1250 : return true;
1251 :
1252 72733 : case OPT_mamx_fp16:
1253 72733 : if (value)
1254 : {
1255 72719 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1256 72719 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1257 : }
1258 : else
1259 : {
1260 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1261 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1262 : }
1263 : return true;
1264 :
1265 72005 : case OPT_mprefetchi:
1266 72005 : if (value)
1267 : {
1268 71991 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1269 71991 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1270 : }
1271 : else
1272 : {
1273 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1274 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1275 : }
1276 : return true;
1277 :
1278 160073 : case OPT_mraoint:
1279 160073 : if (value)
1280 : {
1281 160059 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1282 160059 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1283 : }
1284 : else
1285 : {
1286 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1287 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1288 : }
1289 : return true;
1290 :
1291 77931 : case OPT_mamx_complex:
1292 77931 : if (value)
1293 : {
1294 77917 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1295 77917 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1296 : }
1297 : else
1298 : {
1299 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1300 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1301 : }
1302 : return true;
1303 :
1304 197916 : case OPT_mavxvnniint16:
1305 197916 : if (value)
1306 : {
1307 197901 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1308 197901 : opts->x_ix86_isa_flags2_explicit |=
1309 : OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1310 197901 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1311 197901 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1312 : }
1313 : else
1314 : {
1315 15 : opts->x_ix86_isa_flags2 &=
1316 : ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1317 15 : opts->x_ix86_isa_flags2_explicit |=
1318 : OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1319 : }
1320 : return true;
1321 :
1322 107546 : case OPT_msm3:
1323 107546 : if (value)
1324 : {
1325 107532 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1326 107532 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1327 107532 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1328 107532 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1329 : }
1330 : else
1331 : {
1332 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1333 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1334 : }
1335 : return true;
1336 :
1337 107965 : case OPT_msha512:
1338 107965 : if (value)
1339 : {
1340 107951 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1341 107951 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1342 107951 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1343 107951 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1344 : }
1345 : else
1346 : {
1347 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1348 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1349 : }
1350 : return true;
1351 :
1352 143174 : case OPT_msm4:
1353 143174 : if (value)
1354 : {
1355 143160 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1356 143160 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1357 143160 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1358 143160 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1359 : }
1360 : else
1361 : {
1362 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1363 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1364 : }
1365 : return true;
1366 :
1367 125 : case OPT_mapxf:
1368 125 : if (value)
1369 : {
1370 89 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1371 89 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1372 89 : opts->x_ix86_apx_features = apx_all;
1373 : }
1374 : else
1375 : {
1376 36 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1377 36 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1378 36 : opts->x_ix86_apx_features = apx_none;
1379 : }
1380 : return true;
1381 :
1382 27223 : case OPT_musermsr:
1383 27223 : if (value)
1384 : {
1385 27209 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1386 27209 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1387 : }
1388 : else
1389 : {
1390 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1391 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1392 : }
1393 : return true;
1394 :
1395 31 : case OPT_mavx10_1:
1396 31 : if (value)
1397 : {
1398 17 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
1399 17 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
1400 17 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1401 17 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1402 : }
1403 : else
1404 : {
1405 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
1406 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
1407 : }
1408 : return true;
1409 :
1410 7717127 : case OPT_mavx10_2:
1411 7717127 : if (value)
1412 : {
1413 7717111 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
1414 7717111 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
1415 7717111 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1416 7717111 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1417 : }
1418 : else
1419 : {
1420 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET;
1421 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET;
1422 : }
1423 : return true;
1424 :
1425 1752189 : case OPT_mavx10v2aux:
1426 1752189 : if (value)
1427 : {
1428 1752175 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1429 1752175 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1430 1752175 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1431 1752175 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1432 : }
1433 : else
1434 : {
1435 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1436 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1437 : }
1438 : return true;
1439 :
1440 77935 : case OPT_mamx_avx512:
1441 77935 : if (value)
1442 : {
1443 77917 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1444 77917 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1445 77917 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
1446 77917 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
1447 : }
1448 : else
1449 : {
1450 18 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1451 18 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1452 : }
1453 : return true;
1454 :
1455 72735 : case OPT_mamx_fp8:
1456 72735 : if (value)
1457 : {
1458 72721 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP8_SET;
1459 72721 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_SET;
1460 : }
1461 : else
1462 : {
1463 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP8_UNSET;
1464 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_UNSET;
1465 : }
1466 : return true;
1467 :
1468 490079 : case OPT_mmovrs:
1469 490079 : if (value)
1470 : {
1471 490064 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
1472 490064 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
1473 : }
1474 : else
1475 : {
1476 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
1477 15 : opts->x_ix86_isa_flags2_explicit |=
1478 : OPTION_MASK_ISA2_MOVRS_UNSET;
1479 : }
1480 : return true;
1481 :
1482 77845 : case OPT_mamx_movrs:
1483 77845 : if (value)
1484 : {
1485 77831 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1486 77831 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1487 : }
1488 : else
1489 : {
1490 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1491 14 : opts->x_ix86_isa_flags2_explicit |=
1492 : OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1493 : }
1494 : return true;
1495 :
1496 328017 : case OPT_macev1:
1497 328017 : if (value)
1498 : {
1499 328003 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ACEV1_SET;
1500 328003 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACEV1_SET;
1501 328003 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1502 328003 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1503 : }
1504 : else
1505 : {
1506 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ACEV1_UNSET;
1507 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACEV1_UNSET;
1508 : }
1509 : return true;
1510 :
1511 360069 : case OPT_mfma:
1512 360069 : if (value)
1513 : {
1514 360057 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1515 360057 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1516 : }
1517 : else
1518 : {
1519 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1520 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1521 : }
1522 : return true;
1523 :
1524 123897 : case OPT_mrtm:
1525 123897 : if (value)
1526 : {
1527 123882 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1528 123882 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1529 : }
1530 : else
1531 : {
1532 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1533 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1534 : }
1535 : return true;
1536 :
1537 214 : case OPT_msse4:
1538 214 : if (value)
1539 : {
1540 165 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1541 165 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1542 : }
1543 : else
1544 : {
1545 49 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1546 49 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1547 49 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1548 49 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1549 : }
1550 : return true;
1551 :
1552 79456 : case OPT_msse4a:
1553 79456 : if (value)
1554 : {
1555 79454 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1556 79454 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1557 : }
1558 : else
1559 : {
1560 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1561 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1562 : }
1563 : return true;
1564 :
1565 94030 : case OPT_mfma4:
1566 94030 : if (value)
1567 : {
1568 93997 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1569 93997 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1570 : }
1571 : else
1572 : {
1573 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1574 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1575 : }
1576 : return true;
1577 :
1578 184427 : case OPT_mxop:
1579 184427 : if (value)
1580 : {
1581 184392 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1582 184392 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1583 : }
1584 : else
1585 : {
1586 35 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1587 35 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1588 : }
1589 : return true;
1590 :
1591 126787 : case OPT_mlwp:
1592 126787 : if (value)
1593 : {
1594 126772 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1595 126772 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1596 : }
1597 : else
1598 : {
1599 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1600 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1601 : }
1602 : return true;
1603 :
1604 60097 : case OPT_mabm:
1605 60097 : if (value)
1606 : {
1607 60093 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1608 60093 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1609 : }
1610 : else
1611 : {
1612 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1613 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1614 : }
1615 : return true;
1616 :
1617 318913 : case OPT_mbmi:
1618 318913 : if (value)
1619 : {
1620 318912 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1621 318912 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1622 : }
1623 : else
1624 : {
1625 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1626 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1627 : }
1628 : return true;
1629 :
1630 135815 : case OPT_mbmi2:
1631 135815 : if (value)
1632 : {
1633 135809 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1634 135809 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1635 : }
1636 : else
1637 : {
1638 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1639 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1640 : }
1641 : return true;
1642 :
1643 116391 : case OPT_mlzcnt:
1644 116391 : if (value)
1645 : {
1646 116385 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1647 116385 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1648 : }
1649 : else
1650 : {
1651 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1652 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1653 : }
1654 : return true;
1655 :
1656 268449 : case OPT_mtbm:
1657 268449 : if (value)
1658 : {
1659 268434 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1660 268434 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1661 : }
1662 : else
1663 : {
1664 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1665 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1666 : }
1667 : return true;
1668 :
1669 66255 : case OPT_mpopcnt:
1670 66255 : if (value)
1671 : {
1672 66239 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1673 66239 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1674 : }
1675 : else
1676 : {
1677 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1678 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1679 : }
1680 : return true;
1681 :
1682 19 : case OPT_msahf:
1683 19 : if (value)
1684 : {
1685 17 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1686 17 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1687 : }
1688 : else
1689 : {
1690 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1691 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1692 : }
1693 : return true;
1694 :
1695 72 : case OPT_mcx16:
1696 72 : if (value)
1697 : {
1698 67 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1699 67 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1700 : }
1701 : else
1702 : {
1703 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1704 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1705 : }
1706 : return true;
1707 :
1708 32 : case OPT_mmovbe:
1709 32 : if (value)
1710 : {
1711 27 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1712 27 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1713 : }
1714 : else
1715 : {
1716 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1717 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1718 : }
1719 : return true;
1720 :
1721 11153 : case OPT_mcrc32:
1722 11153 : if (value)
1723 : {
1724 11149 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1725 11149 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1726 : }
1727 : else
1728 : {
1729 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1730 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1731 : }
1732 : return true;
1733 :
1734 85539 : case OPT_maes:
1735 85539 : if (value)
1736 : {
1737 85537 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1738 85537 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1739 : }
1740 : else
1741 : {
1742 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1743 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1744 : }
1745 : return true;
1746 :
1747 147205 : case OPT_msha:
1748 147205 : if (value)
1749 : {
1750 147204 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1751 147204 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1752 : }
1753 : else
1754 : {
1755 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1756 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1757 : }
1758 : return true;
1759 :
1760 75515 : case OPT_mpclmul:
1761 75515 : if (value)
1762 : {
1763 75514 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1764 75514 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1765 : }
1766 : else
1767 : {
1768 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1769 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1770 : }
1771 : return true;
1772 :
1773 158857 : case OPT_mfsgsbase:
1774 158857 : if (value)
1775 : {
1776 158856 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1777 158856 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1778 : }
1779 : else
1780 : {
1781 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1782 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1783 : }
1784 : return true;
1785 :
1786 114611 : case OPT_mrdrnd:
1787 114611 : if (value)
1788 : {
1789 114610 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1790 114610 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1791 : }
1792 : else
1793 : {
1794 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1795 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1796 : }
1797 : return true;
1798 :
1799 25470 : case OPT_mptwrite:
1800 25470 : if (value)
1801 : {
1802 25457 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1803 25457 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1804 : }
1805 : else
1806 : {
1807 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1808 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1809 : }
1810 : return true;
1811 :
1812 134406 : case OPT_mf16c:
1813 134406 : if (value)
1814 : {
1815 134405 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1816 134405 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1817 : }
1818 : else
1819 : {
1820 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1821 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1822 : }
1823 : return true;
1824 :
1825 62329 : case OPT_mfxsr:
1826 62329 : if (value)
1827 : {
1828 62327 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1829 62327 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1830 : }
1831 : else
1832 : {
1833 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1834 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1835 : }
1836 : return true;
1837 :
1838 6942 : case OPT_mxsave:
1839 6942 : if (value)
1840 : {
1841 6936 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1842 6936 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1843 : }
1844 : else
1845 : {
1846 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1847 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1848 6 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1849 6 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1850 : }
1851 : return true;
1852 :
1853 87527 : case OPT_mxsaveopt:
1854 87527 : if (value)
1855 : {
1856 87526 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1857 87526 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1858 : }
1859 : else
1860 : {
1861 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1862 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1863 : }
1864 : return true;
1865 :
1866 73238 : case OPT_mxsavec:
1867 73238 : if (value)
1868 : {
1869 73236 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1870 73236 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1871 : }
1872 : else
1873 : {
1874 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1875 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1876 : }
1877 : return true;
1878 :
1879 93289 : case OPT_mxsaves:
1880 93289 : if (value)
1881 : {
1882 93287 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1883 93287 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1884 : }
1885 : else
1886 : {
1887 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1888 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1889 : }
1890 : return true;
1891 :
1892 97657 : case OPT_mrdseed:
1893 97657 : if (value)
1894 : {
1895 97655 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1896 97655 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1897 : }
1898 : else
1899 : {
1900 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1901 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1902 : }
1903 : return true;
1904 :
1905 60789 : case OPT_mprfchw:
1906 60789 : if (value)
1907 : {
1908 60787 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1909 60787 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1910 : }
1911 : else
1912 : {
1913 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1914 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1915 : }
1916 : return true;
1917 :
1918 62320 : case OPT_madx:
1919 62320 : if (value)
1920 : {
1921 62316 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1922 62316 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1923 : }
1924 : else
1925 : {
1926 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1927 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1928 : }
1929 : return true;
1930 :
1931 63259 : case OPT_mclflushopt:
1932 63259 : if (value)
1933 : {
1934 63257 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1935 63257 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1936 : }
1937 : else
1938 : {
1939 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1940 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1941 : }
1942 : return true;
1943 :
1944 63278 : case OPT_mclwb:
1945 63278 : if (value)
1946 : {
1947 63276 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1948 63276 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1949 : }
1950 : else
1951 : {
1952 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1953 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1954 : }
1955 : return true;
1956 :
1957 72767 : case OPT_mmwaitx:
1958 72767 : if (value)
1959 : {
1960 72765 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1961 72765 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1962 : }
1963 : else
1964 : {
1965 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1966 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1967 : }
1968 : return true;
1969 :
1970 25793 : case OPT_mmwait:
1971 25793 : if (value)
1972 : {
1973 25792 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1974 25792 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1975 : }
1976 : else
1977 : {
1978 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1979 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1980 : }
1981 : return true;
1982 :
1983 62641 : case OPT_mclzero:
1984 62641 : if (value)
1985 : {
1986 62639 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1987 62639 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1988 : }
1989 : else
1990 : {
1991 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1992 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1993 : }
1994 : return true;
1995 :
1996 73344 : case OPT_mpku:
1997 73344 : if (value)
1998 : {
1999 73329 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
2000 73329 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
2001 : }
2002 : else
2003 : {
2004 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
2005 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
2006 : }
2007 : return true;
2008 :
2009 :
2010 1 : case OPT_malign_loops_:
2011 1 : warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
2012 : "use %<-falign-loops%>");
2013 1 : if (value > MAX_CODE_ALIGN)
2014 0 : error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
2015 : value, MAX_CODE_ALIGN);
2016 : else
2017 1 : set_malign_value (&opts->x_str_align_loops, value);
2018 : return true;
2019 :
2020 0 : case OPT_malign_jumps_:
2021 0 : warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
2022 : "use %<-falign-jumps%>");
2023 0 : if (value > MAX_CODE_ALIGN)
2024 0 : error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
2025 : value, MAX_CODE_ALIGN);
2026 : else
2027 0 : set_malign_value (&opts->x_str_align_jumps, value);
2028 : return true;
2029 :
2030 0 : case OPT_malign_functions_:
2031 0 : warning_at (loc, 0,
2032 : "%<-malign-functions%> is obsolete, "
2033 : "use %<-falign-functions%>");
2034 0 : if (value > MAX_CODE_ALIGN)
2035 0 : error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
2036 : value, MAX_CODE_ALIGN);
2037 : else
2038 0 : set_malign_value (&opts->x_str_align_functions, value);
2039 : return true;
2040 :
2041 20 : case OPT_mbranch_cost_:
2042 20 : if (value > 5)
2043 : {
2044 0 : error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
2045 0 : opts->x_ix86_branch_cost = 5;
2046 : }
2047 : return true;
2048 :
2049 : default:
2050 : return true;
2051 : }
2052 : }
2053 :
2054 : static const struct default_options ix86_option_optimization_table[] =
2055 : {
2056 : /* Enable redundant extension instructions removal at -O2 and higher. */
2057 : { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
2058 : /* Enable function splitting at -O2 and higher. */
2059 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
2060 : /* The STC algorithm produces the smallest code at -Os, for x86. */
2061 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
2062 : REORDER_BLOCKS_ALGORITHM_STC },
2063 :
2064 : /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2065 : loop unrolling at -O2. */
2066 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
2067 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
2068 : /* Turns off -frename-registers and -fweb which are enabled by
2069 : funroll-loops. */
2070 : { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
2071 : { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
2072 : /* Turn off -fschedule-insns by default. It tends to make the
2073 : problem with not enough registers even worse. */
2074 : { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
2075 :
2076 : #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2077 : SUBTARGET_OPTIMIZATION_OPTIONS,
2078 : #endif
2079 : { OPT_LEVELS_NONE, 0, NULL, 0 }
2080 : };
2081 :
2082 : /* Implement TARGET_OPTION_INIT_STRUCT. */
2083 :
2084 : static void
2085 50442935 : ix86_option_init_struct (struct gcc_options *opts)
2086 : {
2087 50442935 : if (TARGET_MACHO)
2088 : /* The Darwin libraries never set errno, so we might as well
2089 : avoid calling them when that's the only reason we would. */
2090 : opts->x_flag_errno_math = 0;
2091 :
2092 50442935 : opts->x_flag_pcc_struct_return = 2;
2093 50442935 : opts->x_flag_asynchronous_unwind_tables = 2;
2094 50442935 : }
2095 :
2096 : /* On the x86 -fsplit-stack and -fstack-protector both use the same
2097 : field in the TCB, so they cannot be used together. */
2098 :
2099 : static bool
2100 6362 : ix86_supports_split_stack (bool report,
2101 : struct gcc_options *opts ATTRIBUTE_UNUSED)
2102 : {
2103 : #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2104 6362 : if (!OPTION_GLIBC_P (opts))
2105 : #endif
2106 : {
2107 0 : if (report)
2108 0 : error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2109 : return false;
2110 : }
2111 :
2112 : bool ret = true;
2113 :
2114 : #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2115 : if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
2116 : {
2117 : if (report)
2118 : error ("%<-fsplit-stack%> requires "
2119 : "assembler support for CFI directives");
2120 : ret = false;
2121 : }
2122 : #endif
2123 :
2124 : return ret;
2125 : }
2126 :
2127 : /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2128 :
2129 : static enum unwind_info_type
2130 9279260 : i386_except_unwind_info (struct gcc_options *opts)
2131 : {
2132 : /* Honor the --enable-sjlj-exceptions configure switch. */
2133 : #ifdef CONFIG_SJLJ_EXCEPTIONS
2134 : if (CONFIG_SJLJ_EXCEPTIONS)
2135 : return UI_SJLJ;
2136 : #endif
2137 :
2138 : /* On windows 64, prefer SEH exceptions over anything else. */
2139 9279260 : if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
2140 : return UI_SEH;
2141 :
2142 9279260 : if (DWARF2_UNWIND_INFO)
2143 9279260 : return UI_DWARF2;
2144 :
2145 : return UI_SJLJ;
2146 : }
2147 :
2148 : #undef TARGET_EXCEPT_UNWIND_INFO
2149 : #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2150 :
2151 : #undef TARGET_DEFAULT_TARGET_FLAGS
2152 : #define TARGET_DEFAULT_TARGET_FLAGS \
2153 : (TARGET_DEFAULT \
2154 : | TARGET_SUBTARGET_DEFAULT \
2155 : | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2156 :
2157 : #undef TARGET_HANDLE_OPTION
2158 : #define TARGET_HANDLE_OPTION ix86_handle_option
2159 :
2160 : #undef TARGET_OPTION_OPTIMIZATION_TABLE
2161 : #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2162 : #undef TARGET_OPTION_INIT_STRUCT
2163 : #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2164 :
2165 : #undef TARGET_SUPPORTS_SPLIT_STACK
2166 : #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2167 :
2168 : /* This table must be in sync with enum processor_type in i386.h. */
2169 : const char *const processor_names[] =
2170 : {
2171 : "generic",
2172 : "i386",
2173 : "i486",
2174 : "pentium",
2175 : "lakemont",
2176 : "pentiumpro",
2177 : "pentium4",
2178 : "nocona",
2179 : "core2",
2180 : "nehalem",
2181 : "sandybridge",
2182 : "haswell",
2183 : "bonnell",
2184 : "silvermont",
2185 : "goldmont",
2186 : "goldmont-plus",
2187 : "tremont",
2188 : "sierraforest",
2189 : "grandridge",
2190 : "clearwaterforest",
2191 : "skylake",
2192 : "skylake-avx512",
2193 : "cannonlake",
2194 : "icelake-client",
2195 : "icelake-server",
2196 : "cascadelake",
2197 : "tigerlake",
2198 : "cooperlake",
2199 : "sapphirerapids",
2200 : "alderlake",
2201 : "rocketlake",
2202 : "graniterapids",
2203 : "graniterapids-d",
2204 : "arrowlake",
2205 : "arrowlake-s",
2206 : "pantherlake",
2207 : "diamondrapids",
2208 : "novalake",
2209 : "intel",
2210 : "lujiazui",
2211 : "yongfeng",
2212 : "shijidadao",
2213 : "geode",
2214 : "k6",
2215 : "athlon",
2216 : "k8",
2217 : "amdfam10",
2218 : "bdver1",
2219 : "bdver2",
2220 : "bdver3",
2221 : "bdver4",
2222 : "btver1",
2223 : "btver2",
2224 : "znver1",
2225 : "znver2",
2226 : "znver3",
2227 : "znver4",
2228 : "znver5",
2229 : "znver6",
2230 : "c86-4g-m4",
2231 : "c86-4g-m6",
2232 : "c86-4g-m7",
2233 : "c86-4g-m8"
2234 : };
2235 :
2236 : /* Guarantee that the array is aligned with enum processor_type. */
2237 : STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2238 :
2239 : const pta processor_alias_table[] =
2240 : {
2241 : {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2242 : {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2243 : {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2244 : {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2245 : {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2246 : 0, P_NONE},
2247 : {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2248 : {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2249 : {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2250 : 0, P_NONE},
2251 : {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2252 : {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2253 : 0, P_NONE},
2254 : {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2255 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2256 : {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2257 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2258 : {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2259 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2260 : {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2261 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2262 : {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2263 : {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2264 : {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2265 : 0, P_NONE},
2266 : {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2267 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2268 : {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2269 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2270 : {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2271 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2272 : {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2273 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2274 : {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2275 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2276 : {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2277 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2278 : {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2279 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2280 : | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2281 : {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2282 : M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2283 : {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2284 : M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2285 : {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2286 : M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2287 : {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2288 : M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2289 : {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2290 : PTA_SANDYBRIDGE,
2291 : M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2292 : {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2293 : PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2294 : {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2295 : PTA_IVYBRIDGE,
2296 : M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2297 : {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2298 : PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2299 : {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2300 : M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2301 : {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2302 : 0, P_PROC_DYNAMIC},
2303 : {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2304 : M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2305 : {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2306 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2307 : {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2308 : PTA_SKYLAKE_AVX512,
2309 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2310 : {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2311 : M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2312 : {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2313 : PTA_ICELAKE_CLIENT,
2314 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2315 : {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2316 : PTA_ROCKETLAKE,
2317 : M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2318 : {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2319 : PTA_ICELAKE_SERVER,
2320 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2321 : {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2322 : PTA_CASCADELAKE,
2323 : M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2324 : {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2325 : M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2326 : {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2327 : M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2328 : {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2329 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2330 : {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2331 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2332 : {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2333 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2334 : {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2335 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2336 : {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2337 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2338 : {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2339 : M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1},
2340 : {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2341 : PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2342 : P_PROC_AVX10_1},
2343 : {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2344 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2345 : {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2346 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2347 : {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2348 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2349 : {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2350 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2351 : {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS,
2352 : M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_2},
2353 : {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2354 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2355 : {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
2356 : M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
2357 : {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2358 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2359 : {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2360 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2361 : {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2362 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2363 : {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2364 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2365 : {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2366 : M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2367 : {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2368 : M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2369 : {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2370 : M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2371 : {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2372 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2373 : {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2374 : M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2375 : {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2376 : M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2377 : {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2378 : PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2379 : {"intel", PROCESSOR_INTEL, CPU_HASWELL, PTA_HASWELL,
2380 : M_VENDOR (VENDOR_INTEL), P_NONE},
2381 : {"geode", PROCESSOR_GEODE, CPU_GEODE,
2382 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2383 : {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2384 : {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2385 : {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2386 : {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2387 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2388 : {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2389 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2390 : {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2391 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2392 : {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2393 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2394 : {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2395 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2396 : {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2397 : {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2398 : 0, P_NONE},
2399 : {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2400 : 0, P_NONE},
2401 : {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2402 : 0, P_NONE},
2403 : {"eden-x2", PROCESSOR_K8, CPU_K8,
2404 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2405 : 0, P_NONE},
2406 : {"nano", PROCESSOR_K8, CPU_K8,
2407 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2408 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2409 : {"nano-1000", PROCESSOR_K8, CPU_K8,
2410 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2411 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2412 : {"nano-2000", PROCESSOR_K8, CPU_K8,
2413 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2414 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2415 : {"nano-3000", PROCESSOR_K8, CPU_K8,
2416 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2417 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2418 : {"nano-x2", PROCESSOR_K8, CPU_K8,
2419 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2420 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2421 : {"eden-x4", PROCESSOR_K8, CPU_K8,
2422 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2423 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2424 : {"nano-x4", PROCESSOR_K8, CPU_K8,
2425 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2426 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2427 : {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2428 : PTA_LUJIAZUI,
2429 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2430 : {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2431 : PTA_YONGFENG,
2432 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2433 : {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2434 : PTA_YONGFENG,
2435 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2436 : {"k8", PROCESSOR_K8, CPU_K8,
2437 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2438 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2439 : {"k8-sse3", PROCESSOR_K8, CPU_K8,
2440 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2441 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2442 : {"opteron", PROCESSOR_K8, CPU_K8,
2443 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2444 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2445 : {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2446 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2447 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2448 : {"athlon64", PROCESSOR_K8, CPU_K8,
2449 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2450 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2451 : {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2452 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2453 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2454 : {"athlon-fx", PROCESSOR_K8, CPU_K8,
2455 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2456 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2457 : {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2458 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2459 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2460 : 0, P_PROC_DYNAMIC},
2461 : {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2462 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2463 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2464 : M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2465 : {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2466 : PTA_BDVER1,
2467 : M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2468 : {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2469 : PTA_BDVER2,
2470 : M_CPU_SUBTYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2471 : {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2472 : PTA_BDVER3,
2473 : M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2474 : {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2475 : PTA_BDVER4,
2476 : M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2477 : {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2478 : PTA_ZNVER1,
2479 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2480 : {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2481 : PTA_ZNVER2,
2482 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2483 : {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2484 : PTA_ZNVER3,
2485 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2486 : {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2487 : PTA_ZNVER4,
2488 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2489 : {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2490 : PTA_ZNVER5,
2491 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2492 : {"znver6", PROCESSOR_ZNVER6, CPU_ZNVER5,
2493 : PTA_ZNVER6,
2494 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER6), P_PROC_AVX512F},
2495 : {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2496 : PTA_BTVER1,
2497 : M_CPU_TYPE (AMD_BTVER1), P_PROC_SSE4_A},
2498 : {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2499 : PTA_BTVER2,
2500 : M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2501 : {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
2502 : PTA_C86_4G_M4,
2503 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
2504 : {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
2505 : PTA_C86_4G_M6,
2506 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
2507 : {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
2508 : PTA_C86_4G_M7,
2509 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
2510 : {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8,
2511 : PTA_C86_4G_M8,
2512 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F},
2513 :
2514 : {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2515 : PTA_64BIT
2516 : | PTA_HLE /* flags are only used for -march switch. */,
2517 : 0, P_NONE},
2518 :
2519 : {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2520 : M_VENDOR (VENDOR_AMD), P_NONE},
2521 : {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2522 : M_CPU_TYPE (AMDFAM10H), P_NONE},
2523 : {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2524 : M_CPU_TYPE (AMDFAM15H), P_NONE},
2525 : {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2526 : M_CPU_TYPE (AMDFAM17H), P_NONE},
2527 : {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2528 : M_CPU_TYPE (AMDFAM19H), P_NONE},
2529 : {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2530 : M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
2531 : {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2532 : M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
2533 : {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2534 : M_VENDOR (VENDOR_HYGON), P_NONE},
2535 : {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2536 : M_CPU_TYPE (HYGONFAM18H), P_NONE},
2537 : };
2538 :
2539 : /* NB: processor_alias_table stops at the "generic" entry. */
2540 : unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
2541 : unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2542 :
2543 : /* Provide valid option values for -march and -mtune options. */
2544 :
2545 : vec<const char *>
2546 156802 : ix86_get_valid_option_values (int option_code,
2547 : const char *prefix ATTRIBUTE_UNUSED)
2548 : {
2549 156802 : vec<const char *> v;
2550 156802 : v.create (0);
2551 156802 : opt_code opt = (opt_code) option_code;
2552 :
2553 156802 : switch (opt)
2554 : {
2555 : case OPT_march_:
2556 71995 : for (unsigned i = 0; i < pta_size; i++)
2557 : {
2558 71400 : const char *name = processor_alias_table[i].name;
2559 71400 : gcc_checking_assert (name != NULL);
2560 71400 : v.safe_push (name);
2561 : }
2562 : #ifdef HAVE_LOCAL_CPU_DETECT
2563 : /* Add also "native" as possible value. */
2564 595 : v.safe_push ("native");
2565 : #endif
2566 :
2567 595 : break;
2568 : case OPT_mtune_:
2569 38080 : for (unsigned i = 0; i < PROCESSOR_max; i++)
2570 : {
2571 37485 : const char *name = processor_names[i];
2572 37485 : gcc_checking_assert (name != NULL);
2573 37485 : v.safe_push (name);
2574 : }
2575 : break;
2576 : default:
2577 : break;
2578 : }
2579 :
2580 156802 : return v;
2581 : }
2582 :
2583 : #undef TARGET_GET_VALID_OPTION_VALUES
2584 : #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2585 :
2586 : struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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