Line data Source code
1 : /* IA-32 common hooks.
2 : Copyright (C) 1988-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify
7 : it under the terms of the GNU General Public License as published by
8 : the Free Software Foundation; either version 3, or (at your option)
9 : any later version.
10 :
11 : GCC is distributed in the hope that it will be useful,
12 : but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : GNU General Public License for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "diagnostic-core.h"
24 : #include "tm.h"
25 : #include "memmodel.h"
26 : #include "tm_p.h"
27 : #include "common/common-target.h"
28 : #include "common/common-target-def.h"
29 : #include "opts.h"
30 : #include "flags.h"
31 :
32 : /* Define a set of ISAs which are available when a given ISA is
33 : enabled. MMX and SSE ISAs are handled separately. */
34 :
35 : #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 : #define OPTION_MASK_ISA_3DNOW_SET \
37 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 : #define OPTION_MASK_ISA_3DNOW_A_SET \
39 : (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 :
41 : #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 : #define OPTION_MASK_ISA_SSE2_SET \
43 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 : #define OPTION_MASK_ISA_SSE3_SET \
45 : (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 : #define OPTION_MASK_ISA_SSSE3_SET \
47 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 : #define OPTION_MASK_ISA_SSE4_1_SET \
49 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 : #define OPTION_MASK_ISA_SSE4_2_SET \
51 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 : #define OPTION_MASK_ISA_AVX_SET \
53 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 : | OPTION_MASK_ISA_XSAVE_SET)
55 : #define OPTION_MASK_ISA_FMA_SET \
56 : (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 : #define OPTION_MASK_ISA_AVX2_SET \
58 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 : #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 : #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 : #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 : (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 : #define OPTION_MASK_ISA_AVX512F_SET \
64 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 : #define OPTION_MASK_ISA_AVX512CD_SET \
66 : (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 : #define OPTION_MASK_ISA_AVX512DQ_SET \
68 : (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 : #define OPTION_MASK_ISA_AVX512BW_SET \
70 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 : #define OPTION_MASK_ISA_AVX512VL_SET \
72 : (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 : #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 : (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 : #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 : #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 : (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 : #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 : (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 : #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 : #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 : #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 : (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 : #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 : (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 : #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 : (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 : #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 : #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 : #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 : #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 : #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 : #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 : #define OPTION_MASK_ISA_XSAVES_SET \
96 : (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 : #define OPTION_MASK_ISA_XSAVEC_SET \
98 : (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 : #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 : #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 : #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 : #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 : #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 : #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 : #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 : #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 : #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 : #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 : #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 : #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 : #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 : #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 : #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 : #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 : #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
121 : #define OPTION_MASK_ISA_AVX10_1_SET \
122 : (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
123 : | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
124 : | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
125 : | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
126 : | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
127 : | OPTION_MASK_ISA_AVX512BITALG_SET)
128 : #define OPTION_MASK_ISA2_AVX10_1_SET \
129 : (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
130 : | OPTION_MASK_ISA2_AVX10_1)
131 : #define OPTION_MASK_ISA2_AVX10_2_SET \
132 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
133 : #define OPTION_MASK_ISA2_AMX_AVX512_SET \
134 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
135 : #define OPTION_MASK_ISA2_AMX_FP8_SET \
136 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
137 : #define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
138 : #define OPTION_MASK_ISA2_AMX_MOVRS_SET \
139 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS)
140 : #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
141 : #define OPTION_MASK_ISA2_AVX10V2AUX_SET \
142 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V2AUX)
143 : /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
144 : as -msse4.2. */
145 : #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
146 :
147 : #define OPTION_MASK_ISA_SSE4A_SET \
148 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
149 : #define OPTION_MASK_ISA_FMA4_SET \
150 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
151 : | OPTION_MASK_ISA_AVX_SET)
152 : #define OPTION_MASK_ISA_XOP_SET \
153 : (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
154 : #define OPTION_MASK_ISA_LWP_SET \
155 : OPTION_MASK_ISA_LWP
156 :
157 : /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
158 : #define OPTION_MASK_ISA_AES_SET \
159 : (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
160 : #define OPTION_MASK_ISA_SHA_SET \
161 : (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
162 : #define OPTION_MASK_ISA_PCLMUL_SET \
163 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
164 :
165 : #define OPTION_MASK_ISA_ABM_SET \
166 : (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
167 :
168 : #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
169 : #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
170 : #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
171 : #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
172 : #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
173 : #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
174 : #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
175 : #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
176 : #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
177 : #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
178 : #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
179 : #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
180 :
181 : #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
182 : #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
183 : #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
184 : #define OPTION_MASK_ISA_F16C_SET \
185 : (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
186 : #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
187 : #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
188 : #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
189 : #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
190 : #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
191 : #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
192 : #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
193 : #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
194 : #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
195 : (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
196 : | OPTION_MASK_ISA_AVX_SET)
197 : #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
198 : #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
199 : #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
200 : #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
201 : #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
202 : #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
203 : #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
204 : #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
205 : #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
206 : #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
207 : #define OPTION_MASK_ISA2_WIDEKL_SET \
208 : (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
209 :
210 : /* Define a set of ISAs which aren't available when a given ISA is
211 : disabled. MMX and SSE ISAs are handled separately. */
212 :
213 : #define OPTION_MASK_ISA_MMX_UNSET \
214 : (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
215 : #define OPTION_MASK_ISA_3DNOW_UNSET \
216 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
217 : #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
218 :
219 : #define OPTION_MASK_ISA_SSE_UNSET \
220 : (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
221 : #define OPTION_MASK_ISA_SSE2_UNSET \
222 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
223 : #define OPTION_MASK_ISA_SSE3_UNSET \
224 : (OPTION_MASK_ISA_SSE3 \
225 : | OPTION_MASK_ISA_SSSE3_UNSET \
226 : | OPTION_MASK_ISA_SSE4A_UNSET )
227 : #define OPTION_MASK_ISA_SSSE3_UNSET \
228 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
229 : #define OPTION_MASK_ISA_SSE4_1_UNSET \
230 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
231 : #define OPTION_MASK_ISA_SSE4_2_UNSET \
232 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
233 : #define OPTION_MASK_ISA_AVX_UNSET \
234 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
235 : | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
236 : | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
237 : #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
238 : #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
239 : #define OPTION_MASK_ISA_XSAVE_UNSET \
240 : (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
241 : | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
242 : | OPTION_MASK_ISA_AVX_UNSET)
243 : #define OPTION_MASK_ISA2_XSAVE_UNSET \
244 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
245 : #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
246 : #define OPTION_MASK_ISA_AVX2_UNSET \
247 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
248 : #define OPTION_MASK_ISA2_AVX2_UNSET \
249 : (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
250 : | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
251 : | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
252 : #define OPTION_MASK_ISA_AVX512F_UNSET \
253 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
254 : | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
255 : | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
256 : | OPTION_MASK_ISA_AVX512VNNI_UNSET \
257 : | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
258 : #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
259 : #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
260 : #define OPTION_MASK_ISA_AVX512BW_UNSET \
261 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
262 : | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
263 : #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
264 : #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
265 : #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
266 : #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
267 : #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
268 : #define OPTION_MASK_ISA2_AVX512FP16_UNSET \
269 : (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
270 : #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
271 : #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
272 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
273 : #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
274 : #define OPTION_MASK_ISA2_AVX512BF16_UNSET \
275 : (OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
276 : #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
277 : #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
278 : #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
279 : #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
280 : #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
281 : #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
282 : #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
283 : #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
284 : #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
285 : #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
286 : #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
287 : #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
288 : #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
289 : #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
290 : #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
291 : #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
292 : #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
293 : #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
294 : #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
295 : #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
296 : #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
297 : #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
298 : #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
299 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
300 : #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
301 : #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
302 : (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
303 : | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
304 : | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
305 : | OPTION_MASK_ISA2_AMX_FP8_UNSET | OPTION_MASK_ISA2_AMX_MOVRS_UNSET)
306 : #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
307 : #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
308 : #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
309 : #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
310 : #define OPTION_MASK_ISA2_KL_UNSET \
311 : (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
312 : #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
313 : #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
314 : #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
315 : #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
316 : #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
317 : #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
318 : #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
319 : #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
320 : #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
321 : #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
322 : #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
323 : #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
324 : #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
325 : #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
326 : #define OPTION_MASK_ISA2_AVX10_1_UNSET \
327 : (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
328 : | OPTION_MASK_ISA2_AVX10V2AUX_UNSET)
329 : #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
330 : #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
331 : #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
332 : #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
333 : #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
334 : #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
335 : #define OPTION_MASK_ISA2_AVX10V2AUX_UNSET OPTION_MASK_ISA2_AVX10V2AUX
336 :
337 : /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
338 : as -mno-sse4.1. */
339 : #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
340 :
341 : #define OPTION_MASK_ISA_SSE4A_UNSET \
342 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
343 :
344 : #define OPTION_MASK_ISA_FMA4_UNSET \
345 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
346 : #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
347 : #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
348 :
349 : #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
350 : #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
351 : #define OPTION_MASK_ISA_PCLMUL_UNSET \
352 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
353 : #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
354 : #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
355 : #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
356 : #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
357 : #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
358 : #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
359 : #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
360 : #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
361 : #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
362 : #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
363 : #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
364 : #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
365 : #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
366 :
367 : #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
368 : #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
369 : #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
370 : #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
371 :
372 : #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
373 : (OPTION_MASK_ISA_MMX_UNSET \
374 : | OPTION_MASK_ISA_SSE_UNSET)
375 :
376 : #define OPTION_MASK_ISA2_AVX512F_UNSET \
377 : (OPTION_MASK_ISA2_AVX512BW_UNSET \
378 : | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
379 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
380 : | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
381 : #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
382 : OPTION_MASK_ISA2_SSE_UNSET
383 : #define OPTION_MASK_ISA2_AVX_UNSET \
384 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
385 : | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
386 : | OPTION_MASK_ISA2_SM4_UNSET)
387 : #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
388 : #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
389 : #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
390 : #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
391 : #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
392 : #define OPTION_MASK_ISA2_SSE2_UNSET \
393 : (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
394 : #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
395 :
396 : #define OPTION_MASK_ISA2_AVX512BW_UNSET \
397 : (OPTION_MASK_ISA2_AVX512BF16_UNSET \
398 : | OPTION_MASK_ISA2_AVX512FP16_UNSET \
399 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
400 : | OPTION_MASK_ISA2_AVX512BMM_UNSET)
401 : #define OPTION_MASK_ISA2_AVX512CD_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
402 : #define OPTION_MASK_ISA2_AVX512DQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
403 : #define OPTION_MASK_ISA2_AVX512VL_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
404 : #define OPTION_MASK_ISA2_AVX512IFMA_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
405 : #define OPTION_MASK_ISA2_AVX512VNNI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
406 : #define OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
407 : #define OPTION_MASK_ISA2_AVX512VBMI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
408 : #define OPTION_MASK_ISA2_AVX512VBMI2_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
409 : #define OPTION_MASK_ISA2_AVX512BITALG_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
410 :
411 : /* Set 1 << value as value of -malign-FLAG option. */
412 :
413 : static void
414 1 : set_malign_value (const char **flag, unsigned value)
415 : {
416 1 : char *r = XNEWVEC (char, 6);
417 1 : sprintf (r, "%d", 1 << value);
418 1 : *flag = r;
419 1 : }
420 :
421 : /* Implement TARGET_HANDLE_OPTION. */
422 :
423 : bool
424 69684369 : ix86_handle_option (struct gcc_options *opts,
425 : struct gcc_options *opts_set ATTRIBUTE_UNUSED,
426 : const struct cl_decoded_option *decoded,
427 : location_t loc)
428 : {
429 69684369 : size_t code = decoded->opt_index;
430 69684369 : int value = decoded->value;
431 :
432 69684369 : switch (code)
433 : {
434 1980800 : case OPT_mgeneral_regs_only:
435 1980800 : if (value)
436 : {
437 1980800 : HOST_WIDE_INT general_regs_only_flags = 0;
438 1980800 : HOST_WIDE_INT general_regs_only_flags2 = 0;
439 :
440 : /* NB: Enable the GPR only instructions which are enabled
441 : implicitly by SSE ISAs unless they have been disabled
442 : explicitly. */
443 1980800 : if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
444 : {
445 6499 : if (!TARGET_EXPLICIT_CRC32_P (opts))
446 4588 : general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
447 6499 : if (!TARGET_EXPLICIT_POPCNT_P (opts))
448 4570 : general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
449 : }
450 1980800 : if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
451 : {
452 6907 : if (!TARGET_EXPLICIT_MWAIT_P (opts))
453 1980800 : general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
454 : }
455 :
456 : /* Disable MMX, SSE and x87 instructions if only
457 : general registers are allowed. */
458 1980800 : opts->x_ix86_isa_flags
459 1980800 : &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
460 1980800 : opts->x_ix86_isa_flags2
461 1980800 : &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
462 1980800 : opts->x_ix86_isa_flags |= general_regs_only_flags;
463 1980800 : opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
464 1980800 : opts->x_ix86_isa_flags_explicit
465 1980800 : |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
466 : | general_regs_only_flags);
467 1980800 : opts->x_ix86_isa_flags2_explicit
468 1980800 : |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
469 : | general_regs_only_flags2);
470 :
471 1980800 : opts->x_target_flags &= ~MASK_80387;
472 : }
473 : else
474 0 : gcc_unreachable ();
475 1980800 : return true;
476 :
477 3465 : case OPT_mmmx:
478 3465 : if (value)
479 : {
480 1646 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
481 1646 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
482 : }
483 : else
484 : {
485 1819 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
486 1819 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
487 : }
488 : return true;
489 :
490 85224 : case OPT_m3dnow:
491 85224 : if (value)
492 : {
493 85211 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
494 85211 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
495 : }
496 : else
497 : {
498 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
499 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
500 : }
501 : return true;
502 :
503 6073 : case OPT_m3dnowa:
504 6073 : if (value)
505 : {
506 6072 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
507 6072 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
508 : }
509 : else
510 : {
511 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
512 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
513 : }
514 : return true;
515 :
516 34127 : case OPT_msse:
517 34127 : if (value)
518 : {
519 34023 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
520 34023 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
521 : }
522 : else
523 : {
524 104 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
525 104 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
526 104 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
527 104 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
528 : }
529 : return true;
530 :
531 87326 : case OPT_msse2:
532 87326 : if (value)
533 : {
534 87205 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
535 87205 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
536 : }
537 : else
538 : {
539 121 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
540 121 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
541 121 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
542 121 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
543 : }
544 : return true;
545 :
546 24904 : case OPT_msse3:
547 24904 : if (value)
548 : {
549 24819 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
550 24819 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
551 : }
552 : else
553 : {
554 85 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
555 85 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
556 85 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
557 85 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
558 : }
559 : return true;
560 :
561 46224 : case OPT_mssse3:
562 46224 : if (value)
563 : {
564 46214 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
565 46214 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
566 : }
567 : else
568 : {
569 10 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
570 10 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
571 10 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
572 10 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
573 : }
574 : return true;
575 :
576 79213 : case OPT_msse4_1:
577 79213 : if (value)
578 : {
579 79181 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
580 79181 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
581 : }
582 : else
583 : {
584 32 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
585 32 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
586 32 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
587 32 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
588 : }
589 : return true;
590 :
591 29821 : case OPT_msse4_2:
592 29821 : if (value)
593 : {
594 29808 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
595 29808 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
596 : }
597 : else
598 : {
599 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
600 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
601 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
602 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
603 : }
604 : return true;
605 :
606 300134 : case OPT_mavx:
607 300134 : if (value)
608 : {
609 298495 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
610 298495 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
611 : }
612 : else
613 : {
614 1639 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
615 1639 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
616 1639 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
617 1639 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
618 : }
619 : return true;
620 :
621 614321 : case OPT_mavx2:
622 614321 : if (value)
623 : {
624 614243 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
625 614243 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
626 : }
627 : else
628 : {
629 78 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
630 78 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
631 78 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
632 78 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
633 : }
634 : return true;
635 :
636 5016897 : case OPT_mavx512f:
637 5016897 : if (value)
638 : {
639 5016761 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
640 5016761 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
641 : }
642 : else
643 : {
644 136 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
645 136 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
646 136 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
647 136 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
648 : }
649 : return true;
650 :
651 415850 : case OPT_mavx512cd:
652 415850 : if (value)
653 : {
654 415826 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
655 415826 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
656 : }
657 : else
658 : {
659 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
660 24 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
661 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512CD_UNSET;
662 24 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512CD_UNSET;
663 : }
664 : return true;
665 :
666 63098 : case OPT_mrdpid:
667 63098 : if (value)
668 : {
669 63097 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
670 63097 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
671 : }
672 : else
673 : {
674 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
675 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
676 : }
677 : return true;
678 :
679 365449 : case OPT_mgfni:
680 365449 : if (value)
681 : {
682 365433 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
683 365433 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
684 : }
685 : else
686 : {
687 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
688 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
689 : }
690 : return true;
691 :
692 125066 : case OPT_mshstk:
693 125066 : if (value)
694 : {
695 125054 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
696 125054 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
697 : }
698 : else
699 : {
700 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
701 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
702 : }
703 : return true;
704 :
705 90572 : case OPT_mvaes:
706 90572 : if (value)
707 : {
708 90560 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
709 90560 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
710 90560 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
711 90560 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
712 : }
713 : else
714 : {
715 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
716 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
717 : }
718 : return true;
719 :
720 75526 : case OPT_mvpclmulqdq:
721 75526 : if (value)
722 : {
723 75514 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
724 75514 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
725 : }
726 : else
727 : {
728 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
729 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
730 : }
731 : return true;
732 :
733 25457 : case OPT_mmovdiri:
734 25457 : if (value)
735 : {
736 25446 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
737 25446 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
738 : }
739 : else
740 : {
741 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
742 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
743 : }
744 : return true;
745 :
746 15429 : case OPT_mmovdir64b:
747 15429 : if (value)
748 : {
749 15418 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
750 15418 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
751 : }
752 : else
753 : {
754 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
755 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
756 : }
757 : return true;
758 :
759 15425 : case OPT_mcldemote:
760 15425 : if (value)
761 : {
762 15414 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
763 15414 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
764 : }
765 : else
766 : {
767 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
768 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
769 : }
770 : return true;
771 :
772 35684 : case OPT_mwaitpkg:
773 35684 : if (value)
774 : {
775 35673 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
776 35673 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
777 : }
778 : else
779 : {
780 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
781 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
782 : }
783 : return true;
784 :
785 72555 : case OPT_menqcmd:
786 72555 : if (value)
787 : {
788 72543 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
789 72543 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
790 : }
791 : else
792 : {
793 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
794 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
795 : }
796 : return true;
797 :
798 147611 : case OPT_mkl:
799 147611 : if (value)
800 : {
801 147599 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
802 147599 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
803 :
804 : /* The Keylocker instructions need XMM registers from SSE2. */
805 147599 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
806 147599 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
807 : }
808 : else
809 : {
810 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
811 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
812 : }
813 : return true;
814 :
815 156311 : case OPT_mwidekl:
816 156311 : if (value)
817 : {
818 156299 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
819 156299 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
820 :
821 : /* The Widekl instructions need XMM registers from SSE2. */
822 156299 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
823 156299 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
824 : }
825 : else
826 : {
827 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
828 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
829 : }
830 : return true;
831 :
832 89337 : case OPT_mserialize:
833 89337 : if (value)
834 : {
835 89324 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
836 89324 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
837 : }
838 : else
839 : {
840 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
841 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
842 : }
843 : return true;
844 :
845 46605 : case OPT_muintr:
846 46605 : if (value)
847 : {
848 46593 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
849 46593 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
850 : }
851 : else
852 : {
853 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
854 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
855 : }
856 : return true;
857 :
858 16964 : case OPT_mhreset:
859 16964 : if (value)
860 : {
861 16952 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
862 16952 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
863 : }
864 : else
865 : {
866 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
867 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
868 : }
869 : return true;
870 :
871 1439292 : case OPT_mavx512vbmi2:
872 1439292 : if (value)
873 : {
874 1439281 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
875 1439281 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
876 : }
877 : else
878 : {
879 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
880 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
881 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
882 11 : opts->x_ix86_isa_flags2_explicit
883 11 : |= OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
884 : }
885 : return true;
886 :
887 7955701 : case OPT_mavx512fp16:
888 7955701 : if (value)
889 : {
890 7955686 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
891 7955686 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
892 7955686 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
893 7955686 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
894 : }
895 : else
896 : {
897 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
898 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
899 : }
900 : return true;
901 :
902 282482 : case OPT_mavx512vnni:
903 282482 : if (value)
904 : {
905 282470 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
906 282470 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
907 : }
908 : else
909 : {
910 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
911 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
912 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VNNI_UNSET;
913 12 : opts->x_ix86_isa_flags2_explicit
914 12 : |= OPTION_MASK_ISA2_AVX512VNNI_UNSET;
915 : }
916 : return true;
917 :
918 185191 : case OPT_mavx512vpopcntdq:
919 185191 : if (value)
920 : {
921 185167 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
922 185167 : opts->x_ix86_isa_flags_explicit
923 185167 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
924 : }
925 : else
926 : {
927 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
928 24 : opts->x_ix86_isa_flags_explicit
929 24 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
930 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
931 24 : opts->x_ix86_isa_flags2_explicit
932 24 : |= OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
933 : }
934 : return true;
935 :
936 243398 : case OPT_mavx512bitalg:
937 243398 : if (value)
938 : {
939 243387 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
940 243387 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
941 : }
942 : else
943 : {
944 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
945 11 : opts->x_ix86_isa_flags_explicit
946 11 : |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
947 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BITALG_UNSET;
948 11 : opts->x_ix86_isa_flags2_explicit
949 11 : |= OPTION_MASK_ISA2_AVX512BITALG_UNSET;
950 : }
951 : return true;
952 :
953 418930 : case OPT_mavx512bf16:
954 418930 : if (value)
955 : {
956 418910 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
957 418910 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
958 418910 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
959 418910 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
960 : }
961 : else
962 : {
963 20 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
964 20 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
965 : }
966 : return true;
967 :
968 141000 : case OPT_mavx512bmm:
969 141000 : if (value)
970 : {
971 140989 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BMM_SET;
972 140989 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_SET;
973 140989 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
974 140989 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
975 : }
976 : else
977 : {
978 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BMM_UNSET;
979 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_UNSET;
980 : }
981 : return true;
982 :
983 157480 : case OPT_mavxvnni:
984 157480 : if (value)
985 : {
986 157466 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
987 157466 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
988 157466 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
989 157466 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
990 : }
991 : else
992 : {
993 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
994 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
995 : }
996 : return true;
997 :
998 112383 : case OPT_msgx:
999 112383 : if (value)
1000 : {
1001 112371 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
1002 112371 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
1003 : }
1004 : else
1005 : {
1006 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
1007 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
1008 : }
1009 : return true;
1010 :
1011 72190 : case OPT_mpconfig:
1012 72190 : if (value)
1013 : {
1014 72179 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
1015 72179 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
1016 : }
1017 : else
1018 : {
1019 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
1020 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
1021 : }
1022 : return true;
1023 :
1024 62441 : case OPT_mwbnoinvd:
1025 62441 : if (value)
1026 : {
1027 62441 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1028 62441 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1029 : }
1030 : else
1031 : {
1032 0 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1033 0 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1034 : }
1035 : return true;
1036 :
1037 3609278 : case OPT_mavx512dq:
1038 3609278 : if (value)
1039 : {
1040 3609245 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1041 3609245 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1042 : }
1043 : else
1044 : {
1045 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1046 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1047 33 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512DQ_UNSET;
1048 33 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512DQ_UNSET;
1049 : }
1050 : return true;
1051 :
1052 6874111 : case OPT_mavx512bw:
1053 6874111 : if (value)
1054 : {
1055 6874054 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1056 6874054 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1057 : }
1058 : else
1059 : {
1060 57 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1061 57 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1062 57 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1063 57 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1064 : }
1065 : return true;
1066 :
1067 20525784 : case OPT_mavx512vl:
1068 20525784 : if (value)
1069 : {
1070 20525725 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1071 20525725 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1072 : }
1073 : else
1074 : {
1075 59 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1076 59 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1077 59 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VL_UNSET;
1078 59 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VL_UNSET;
1079 : }
1080 : return true;
1081 :
1082 146325 : case OPT_mavx512ifma:
1083 146325 : if (value)
1084 : {
1085 146313 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1086 146313 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1087 : }
1088 : else
1089 : {
1090 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1091 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1092 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1093 12 : opts->x_ix86_isa_flags2_explicit
1094 12 : |= OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1095 : }
1096 : return true;
1097 :
1098 301842 : case OPT_mavx512vbmi:
1099 301842 : if (value)
1100 : {
1101 301830 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1102 301830 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1103 : }
1104 : else
1105 : {
1106 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1107 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1108 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1109 12 : opts->x_ix86_isa_flags2_explicit
1110 12 : |= OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1111 : }
1112 : return true;
1113 :
1114 142936 : case OPT_mavx512vp2intersect:
1115 142936 : if (value)
1116 : {
1117 142924 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1118 142924 : opts->x_ix86_isa_flags2_explicit |=
1119 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1120 142924 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1121 142924 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1122 : }
1123 : else
1124 : {
1125 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1126 12 : opts->x_ix86_isa_flags2_explicit |=
1127 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1128 : }
1129 : return true;
1130 :
1131 99439 : case OPT_mtsxldtrk:
1132 99439 : if (value)
1133 : {
1134 99427 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1135 99427 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1136 : }
1137 : else
1138 : {
1139 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1140 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1141 : }
1142 : return true;
1143 :
1144 106957 : case OPT_mamx_tile:
1145 106957 : if (value)
1146 : {
1147 106945 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1148 106945 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1149 106945 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1150 106945 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1151 : }
1152 : else
1153 : {
1154 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1155 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1156 : }
1157 : return true;
1158 :
1159 77658 : case OPT_mamx_int8:
1160 77658 : if (value)
1161 : {
1162 77646 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1163 77646 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1164 : }
1165 : else
1166 : {
1167 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1168 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1169 : }
1170 : return true;
1171 :
1172 77660 : case OPT_mamx_bf16:
1173 77660 : if (value)
1174 : {
1175 77648 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1176 77648 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1177 : }
1178 : else
1179 : {
1180 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1181 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1182 : }
1183 : return true;
1184 :
1185 117682 : case OPT_mavxifma:
1186 117682 : if (value)
1187 : {
1188 117670 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1189 117670 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1190 117670 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1191 117670 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1192 : }
1193 : else
1194 : {
1195 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1196 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1197 : }
1198 : return true;
1199 :
1200 197629 : case OPT_mavxvnniint8:
1201 197629 : if (value)
1202 : {
1203 197616 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1204 197616 : opts->x_ix86_isa_flags2_explicit |=
1205 : OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1206 197616 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1207 197616 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1208 : }
1209 : else
1210 : {
1211 13 : opts->x_ix86_isa_flags2 &=
1212 : ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1213 13 : opts->x_ix86_isa_flags2_explicit |=
1214 : OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1215 : }
1216 : return true;
1217 :
1218 217654 : case OPT_mavxneconvert:
1219 217654 : if (value)
1220 : {
1221 217634 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1222 217634 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1223 217634 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1224 217634 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1225 : }
1226 : else
1227 : {
1228 20 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1229 20 : opts->x_ix86_isa_flags2_explicit
1230 20 : |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1231 : }
1232 : return true;
1233 :
1234 71838 : case OPT_mcmpccxadd:
1235 71838 : if (value)
1236 : {
1237 71826 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1238 71826 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1239 : }
1240 : else
1241 : {
1242 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1243 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1244 : }
1245 : return true;
1246 :
1247 72471 : case OPT_mamx_fp16:
1248 72471 : if (value)
1249 : {
1250 72459 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1251 72459 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1252 : }
1253 : else
1254 : {
1255 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1256 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1257 : }
1258 : return true;
1259 :
1260 71842 : case OPT_mprefetchi:
1261 71842 : if (value)
1262 : {
1263 71830 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1264 71830 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1265 : }
1266 : else
1267 : {
1268 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1269 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1270 : }
1271 : return true;
1272 :
1273 159794 : case OPT_mraoint:
1274 159794 : if (value)
1275 : {
1276 159782 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1277 159782 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1278 : }
1279 : else
1280 : {
1281 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1282 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1283 : }
1284 : return true;
1285 :
1286 77668 : case OPT_mamx_complex:
1287 77668 : if (value)
1288 : {
1289 77656 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1290 77656 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1291 : }
1292 : else
1293 : {
1294 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1295 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1296 : }
1297 : return true;
1298 :
1299 197628 : case OPT_mavxvnniint16:
1300 197628 : if (value)
1301 : {
1302 197615 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1303 197615 : opts->x_ix86_isa_flags2_explicit |=
1304 : OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1305 197615 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1306 197615 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1307 : }
1308 : else
1309 : {
1310 13 : opts->x_ix86_isa_flags2 &=
1311 : ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1312 13 : opts->x_ix86_isa_flags2_explicit |=
1313 : OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1314 : }
1315 : return true;
1316 :
1317 107277 : case OPT_msm3:
1318 107277 : if (value)
1319 : {
1320 107265 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1321 107265 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1322 107265 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1323 107265 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1324 : }
1325 : else
1326 : {
1327 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1328 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1329 : }
1330 : return true;
1331 :
1332 107695 : case OPT_msha512:
1333 107695 : if (value)
1334 : {
1335 107683 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1336 107683 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1337 107683 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1338 107683 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1339 : }
1340 : else
1341 : {
1342 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1343 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1344 : }
1345 : return true;
1346 :
1347 142898 : case OPT_msm4:
1348 142898 : if (value)
1349 : {
1350 142886 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1351 142886 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1352 142886 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1353 142886 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1354 : }
1355 : else
1356 : {
1357 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1358 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1359 : }
1360 : return true;
1361 :
1362 123 : case OPT_mapxf:
1363 123 : if (value)
1364 : {
1365 89 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1366 89 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1367 89 : opts->x_ix86_apx_features = apx_all;
1368 : }
1369 : else
1370 : {
1371 34 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1372 34 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1373 34 : opts->x_ix86_apx_features = apx_none;
1374 : }
1375 : return true;
1376 :
1377 27216 : case OPT_musermsr:
1378 27216 : if (value)
1379 : {
1380 27204 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1381 27204 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1382 : }
1383 : else
1384 : {
1385 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1386 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1387 : }
1388 : return true;
1389 :
1390 29 : case OPT_mavx10_1:
1391 29 : if (value)
1392 : {
1393 17 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
1394 17 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
1395 17 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1396 17 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1397 : }
1398 : else
1399 : {
1400 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
1401 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
1402 : }
1403 : return true;
1404 :
1405 7715292 : case OPT_mavx10_2:
1406 7715292 : if (value)
1407 : {
1408 7715278 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
1409 7715278 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
1410 7715278 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1411 7715278 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1412 : }
1413 : else
1414 : {
1415 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET;
1416 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET;
1417 : }
1418 : return true;
1419 :
1420 1752264 : case OPT_mavx10v2aux:
1421 1752264 : if (value)
1422 : {
1423 1752252 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1424 1752252 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1425 1752252 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1426 1752252 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1427 : }
1428 : else
1429 : {
1430 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1431 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1432 : }
1433 : return true;
1434 :
1435 77672 : case OPT_mamx_avx512:
1436 77672 : if (value)
1437 : {
1438 77656 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1439 77656 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1440 77656 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
1441 77656 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
1442 : }
1443 : else
1444 : {
1445 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1446 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1447 : }
1448 : return true;
1449 :
1450 72472 : case OPT_mamx_fp8:
1451 72472 : if (value)
1452 : {
1453 72460 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP8_SET;
1454 72460 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_SET;
1455 : }
1456 : else
1457 : {
1458 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP8_UNSET;
1459 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_UNSET;
1460 : }
1461 : return true;
1462 :
1463 489733 : case OPT_mmovrs:
1464 489733 : if (value)
1465 : {
1466 489720 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
1467 489720 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
1468 : }
1469 : else
1470 : {
1471 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
1472 13 : opts->x_ix86_isa_flags2_explicit |=
1473 : OPTION_MASK_ISA2_MOVRS_UNSET;
1474 : }
1475 : return true;
1476 :
1477 77582 : case OPT_mamx_movrs:
1478 77582 : if (value)
1479 : {
1480 77570 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1481 77570 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1482 : }
1483 : else
1484 : {
1485 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1486 12 : opts->x_ix86_isa_flags2_explicit |=
1487 : OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1488 : }
1489 : return true;
1490 :
1491 359809 : case OPT_mfma:
1492 359809 : if (value)
1493 : {
1494 359797 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1495 359797 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1496 : }
1497 : else
1498 : {
1499 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1500 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1501 : }
1502 : return true;
1503 :
1504 123625 : case OPT_mrtm:
1505 123625 : if (value)
1506 : {
1507 123612 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1508 123612 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1509 : }
1510 : else
1511 : {
1512 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1513 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1514 : }
1515 : return true;
1516 :
1517 206 : case OPT_msse4:
1518 206 : if (value)
1519 : {
1520 159 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1521 159 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1522 : }
1523 : else
1524 : {
1525 47 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1526 47 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1527 47 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1528 47 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1529 : }
1530 : return true;
1531 :
1532 79194 : case OPT_msse4a:
1533 79194 : if (value)
1534 : {
1535 79192 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1536 79192 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1537 : }
1538 : else
1539 : {
1540 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1541 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1542 : }
1543 : return true;
1544 :
1545 93782 : case OPT_mfma4:
1546 93782 : if (value)
1547 : {
1548 93751 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1549 93751 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1550 : }
1551 : else
1552 : {
1553 31 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1554 31 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1555 : }
1556 : return true;
1557 :
1558 184179 : case OPT_mxop:
1559 184179 : if (value)
1560 : {
1561 184146 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1562 184146 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1563 : }
1564 : else
1565 : {
1566 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1567 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1568 : }
1569 : return true;
1570 :
1571 126526 : case OPT_mlwp:
1572 126526 : if (value)
1573 : {
1574 126513 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1575 126513 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1576 : }
1577 : else
1578 : {
1579 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1580 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1581 : }
1582 : return true;
1583 :
1584 59887 : case OPT_mabm:
1585 59887 : if (value)
1586 : {
1587 59883 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1588 59883 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1589 : }
1590 : else
1591 : {
1592 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1593 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1594 : }
1595 : return true;
1596 :
1597 318614 : case OPT_mbmi:
1598 318614 : if (value)
1599 : {
1600 318613 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1601 318613 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1602 : }
1603 : else
1604 : {
1605 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1606 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1607 : }
1608 : return true;
1609 :
1610 135552 : case OPT_mbmi2:
1611 135552 : if (value)
1612 : {
1613 135546 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1614 135546 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1615 : }
1616 : else
1617 : {
1618 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1619 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1620 : }
1621 : return true;
1622 :
1623 116132 : case OPT_mlzcnt:
1624 116132 : if (value)
1625 : {
1626 116126 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1627 116126 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1628 : }
1629 : else
1630 : {
1631 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1632 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1633 : }
1634 : return true;
1635 :
1636 268160 : case OPT_mtbm:
1637 268160 : if (value)
1638 : {
1639 268147 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1640 268147 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1641 : }
1642 : else
1643 : {
1644 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1645 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1646 : }
1647 : return true;
1648 :
1649 66007 : case OPT_mpopcnt:
1650 66007 : if (value)
1651 : {
1652 65991 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1653 65991 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1654 : }
1655 : else
1656 : {
1657 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1658 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1659 : }
1660 : return true;
1661 :
1662 17 : case OPT_msahf:
1663 17 : if (value)
1664 : {
1665 15 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1666 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1667 : }
1668 : else
1669 : {
1670 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1671 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1672 : }
1673 : return true;
1674 :
1675 70 : case OPT_mcx16:
1676 70 : if (value)
1677 : {
1678 65 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1679 65 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1680 : }
1681 : else
1682 : {
1683 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1684 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1685 : }
1686 : return true;
1687 :
1688 30 : case OPT_mmovbe:
1689 30 : if (value)
1690 : {
1691 25 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1692 25 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1693 : }
1694 : else
1695 : {
1696 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1697 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1698 : }
1699 : return true;
1700 :
1701 11153 : case OPT_mcrc32:
1702 11153 : if (value)
1703 : {
1704 11149 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1705 11149 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1706 : }
1707 : else
1708 : {
1709 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1710 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1711 : }
1712 : return true;
1713 :
1714 85286 : case OPT_maes:
1715 85286 : if (value)
1716 : {
1717 85284 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1718 85284 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1719 : }
1720 : else
1721 : {
1722 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1723 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1724 : }
1725 : return true;
1726 :
1727 146929 : case OPT_msha:
1728 146929 : if (value)
1729 : {
1730 146928 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1731 146928 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1732 : }
1733 : else
1734 : {
1735 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1736 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1737 : }
1738 : return true;
1739 :
1740 75264 : case OPT_mpclmul:
1741 75264 : if (value)
1742 : {
1743 75263 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1744 75263 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1745 : }
1746 : else
1747 : {
1748 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1749 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1750 : }
1751 : return true;
1752 :
1753 158578 : case OPT_mfsgsbase:
1754 158578 : if (value)
1755 : {
1756 158577 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1757 158577 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1758 : }
1759 : else
1760 : {
1761 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1762 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1763 : }
1764 : return true;
1765 :
1766 114341 : case OPT_mrdrnd:
1767 114341 : if (value)
1768 : {
1769 114340 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1770 114340 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1771 : }
1772 : else
1773 : {
1774 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1775 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1776 : }
1777 : return true;
1778 :
1779 25463 : case OPT_mptwrite:
1780 25463 : if (value)
1781 : {
1782 25452 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1783 25452 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1784 : }
1785 : else
1786 : {
1787 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1788 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1789 : }
1790 : return true;
1791 :
1792 134119 : case OPT_mf16c:
1793 134119 : if (value)
1794 : {
1795 134118 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1796 134118 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1797 : }
1798 : else
1799 : {
1800 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1801 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1802 : }
1803 : return true;
1804 :
1805 62081 : case OPT_mfxsr:
1806 62081 : if (value)
1807 : {
1808 62079 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1809 62079 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1810 : }
1811 : else
1812 : {
1813 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1814 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1815 : }
1816 : return true;
1817 :
1818 6940 : case OPT_mxsave:
1819 6940 : if (value)
1820 : {
1821 6934 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1822 6934 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1823 : }
1824 : else
1825 : {
1826 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1827 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1828 6 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1829 6 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1830 : }
1831 : return true;
1832 :
1833 87274 : case OPT_mxsaveopt:
1834 87274 : if (value)
1835 : {
1836 87273 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1837 87273 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1838 : }
1839 : else
1840 : {
1841 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1842 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1843 : }
1844 : return true;
1845 :
1846 73037 : case OPT_mxsavec:
1847 73037 : if (value)
1848 : {
1849 73035 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1850 73035 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1851 : }
1852 : else
1853 : {
1854 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1855 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1856 : }
1857 : return true;
1858 :
1859 93084 : case OPT_mxsaves:
1860 93084 : if (value)
1861 : {
1862 93082 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1863 93082 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1864 : }
1865 : else
1866 : {
1867 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1868 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1869 : }
1870 : return true;
1871 :
1872 97402 : case OPT_mrdseed:
1873 97402 : if (value)
1874 : {
1875 97400 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1876 97400 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1877 : }
1878 : else
1879 : {
1880 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1881 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1882 : }
1883 : return true;
1884 :
1885 60541 : case OPT_mprfchw:
1886 60541 : if (value)
1887 : {
1888 60539 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1889 60539 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1890 : }
1891 : else
1892 : {
1893 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1894 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1895 : }
1896 : return true;
1897 :
1898 62071 : case OPT_madx:
1899 62071 : if (value)
1900 : {
1901 62067 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1902 62067 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1903 : }
1904 : else
1905 : {
1906 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1907 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1908 : }
1909 : return true;
1910 :
1911 63060 : case OPT_mclflushopt:
1912 63060 : if (value)
1913 : {
1914 63058 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1915 63058 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1916 : }
1917 : else
1918 : {
1919 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1920 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1921 : }
1922 : return true;
1923 :
1924 63079 : case OPT_mclwb:
1925 63079 : if (value)
1926 : {
1927 63077 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1928 63077 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1929 : }
1930 : else
1931 : {
1932 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1933 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1934 : }
1935 : return true;
1936 :
1937 72604 : case OPT_mmwaitx:
1938 72604 : if (value)
1939 : {
1940 72602 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1941 72602 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1942 : }
1943 : else
1944 : {
1945 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1946 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1947 : }
1948 : return true;
1949 :
1950 25788 : case OPT_mmwait:
1951 25788 : if (value)
1952 : {
1953 25787 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1954 25787 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1955 : }
1956 : else
1957 : {
1958 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1959 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1960 : }
1961 : return true;
1962 :
1963 62480 : case OPT_mclzero:
1964 62480 : if (value)
1965 : {
1966 62478 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1967 62478 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1968 : }
1969 : else
1970 : {
1971 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1972 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1973 : }
1974 : return true;
1975 :
1976 73143 : case OPT_mpku:
1977 73143 : if (value)
1978 : {
1979 73130 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1980 73130 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1981 : }
1982 : else
1983 : {
1984 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1985 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1986 : }
1987 : return true;
1988 :
1989 :
1990 1 : case OPT_malign_loops_:
1991 1 : warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1992 : "use %<-falign-loops%>");
1993 1 : if (value > MAX_CODE_ALIGN)
1994 0 : error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1995 : value, MAX_CODE_ALIGN);
1996 : else
1997 1 : set_malign_value (&opts->x_str_align_loops, value);
1998 : return true;
1999 :
2000 0 : case OPT_malign_jumps_:
2001 0 : warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
2002 : "use %<-falign-jumps%>");
2003 0 : if (value > MAX_CODE_ALIGN)
2004 0 : error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
2005 : value, MAX_CODE_ALIGN);
2006 : else
2007 0 : set_malign_value (&opts->x_str_align_jumps, value);
2008 : return true;
2009 :
2010 0 : case OPT_malign_functions_:
2011 0 : warning_at (loc, 0,
2012 : "%<-malign-functions%> is obsolete, "
2013 : "use %<-falign-functions%>");
2014 0 : if (value > MAX_CODE_ALIGN)
2015 0 : error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
2016 : value, MAX_CODE_ALIGN);
2017 : else
2018 0 : set_malign_value (&opts->x_str_align_functions, value);
2019 : return true;
2020 :
2021 20 : case OPT_mbranch_cost_:
2022 20 : if (value > 5)
2023 : {
2024 0 : error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
2025 0 : opts->x_ix86_branch_cost = 5;
2026 : }
2027 : return true;
2028 :
2029 : default:
2030 : return true;
2031 : }
2032 : }
2033 :
2034 : static const struct default_options ix86_option_optimization_table[] =
2035 : {
2036 : /* Enable redundant extension instructions removal at -O2 and higher. */
2037 : { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
2038 : /* Enable function splitting at -O2 and higher. */
2039 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
2040 : /* The STC algorithm produces the smallest code at -Os, for x86. */
2041 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
2042 : REORDER_BLOCKS_ALGORITHM_STC },
2043 :
2044 : /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2045 : loop unrolling at -O2. */
2046 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
2047 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
2048 : /* Turns off -frename-registers and -fweb which are enabled by
2049 : funroll-loops. */
2050 : { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
2051 : { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
2052 : /* Turn off -fschedule-insns by default. It tends to make the
2053 : problem with not enough registers even worse. */
2054 : { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
2055 :
2056 : #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2057 : SUBTARGET_OPTIMIZATION_OPTIONS,
2058 : #endif
2059 : { OPT_LEVELS_NONE, 0, NULL, 0 }
2060 : };
2061 :
2062 : /* Implement TARGET_OPTION_INIT_STRUCT. */
2063 :
2064 : static void
2065 50201064 : ix86_option_init_struct (struct gcc_options *opts)
2066 : {
2067 50201064 : if (TARGET_MACHO)
2068 : /* The Darwin libraries never set errno, so we might as well
2069 : avoid calling them when that's the only reason we would. */
2070 : opts->x_flag_errno_math = 0;
2071 :
2072 50201064 : opts->x_flag_pcc_struct_return = 2;
2073 50201064 : opts->x_flag_asynchronous_unwind_tables = 2;
2074 50201064 : }
2075 :
2076 : /* On the x86 -fsplit-stack and -fstack-protector both use the same
2077 : field in the TCB, so they cannot be used together. */
2078 :
2079 : static bool
2080 6366 : ix86_supports_split_stack (bool report,
2081 : struct gcc_options *opts ATTRIBUTE_UNUSED)
2082 : {
2083 : #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2084 6366 : if (!OPTION_GLIBC_P (opts))
2085 : #endif
2086 : {
2087 0 : if (report)
2088 0 : error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2089 : return false;
2090 : }
2091 :
2092 : bool ret = true;
2093 :
2094 : #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2095 : if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
2096 : {
2097 : if (report)
2098 : error ("%<-fsplit-stack%> requires "
2099 : "assembler support for CFI directives");
2100 : ret = false;
2101 : }
2102 : #endif
2103 :
2104 : return ret;
2105 : }
2106 :
2107 : /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2108 :
2109 : static enum unwind_info_type
2110 9287242 : i386_except_unwind_info (struct gcc_options *opts)
2111 : {
2112 : /* Honor the --enable-sjlj-exceptions configure switch. */
2113 : #ifdef CONFIG_SJLJ_EXCEPTIONS
2114 : if (CONFIG_SJLJ_EXCEPTIONS)
2115 : return UI_SJLJ;
2116 : #endif
2117 :
2118 : /* On windows 64, prefer SEH exceptions over anything else. */
2119 9287242 : if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
2120 : return UI_SEH;
2121 :
2122 9287242 : if (DWARF2_UNWIND_INFO)
2123 9287242 : return UI_DWARF2;
2124 :
2125 : return UI_SJLJ;
2126 : }
2127 :
2128 : #undef TARGET_EXCEPT_UNWIND_INFO
2129 : #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2130 :
2131 : #undef TARGET_DEFAULT_TARGET_FLAGS
2132 : #define TARGET_DEFAULT_TARGET_FLAGS \
2133 : (TARGET_DEFAULT \
2134 : | TARGET_SUBTARGET_DEFAULT \
2135 : | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2136 :
2137 : #undef TARGET_HANDLE_OPTION
2138 : #define TARGET_HANDLE_OPTION ix86_handle_option
2139 :
2140 : #undef TARGET_OPTION_OPTIMIZATION_TABLE
2141 : #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2142 : #undef TARGET_OPTION_INIT_STRUCT
2143 : #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2144 :
2145 : #undef TARGET_SUPPORTS_SPLIT_STACK
2146 : #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2147 :
2148 : /* This table must be in sync with enum processor_type in i386.h. */
2149 : const char *const processor_names[] =
2150 : {
2151 : "generic",
2152 : "i386",
2153 : "i486",
2154 : "pentium",
2155 : "lakemont",
2156 : "pentiumpro",
2157 : "pentium4",
2158 : "nocona",
2159 : "core2",
2160 : "nehalem",
2161 : "sandybridge",
2162 : "haswell",
2163 : "bonnell",
2164 : "silvermont",
2165 : "goldmont",
2166 : "goldmont-plus",
2167 : "tremont",
2168 : "sierraforest",
2169 : "grandridge",
2170 : "clearwaterforest",
2171 : "skylake",
2172 : "skylake-avx512",
2173 : "cannonlake",
2174 : "icelake-client",
2175 : "icelake-server",
2176 : "cascadelake",
2177 : "tigerlake",
2178 : "cooperlake",
2179 : "sapphirerapids",
2180 : "alderlake",
2181 : "rocketlake",
2182 : "graniterapids",
2183 : "graniterapids-d",
2184 : "arrowlake",
2185 : "arrowlake-s",
2186 : "pantherlake",
2187 : "diamondrapids",
2188 : "novalake",
2189 : "intel",
2190 : "lujiazui",
2191 : "yongfeng",
2192 : "shijidadao",
2193 : "geode",
2194 : "k6",
2195 : "athlon",
2196 : "k8",
2197 : "amdfam10",
2198 : "bdver1",
2199 : "bdver2",
2200 : "bdver3",
2201 : "bdver4",
2202 : "btver1",
2203 : "btver2",
2204 : "znver1",
2205 : "znver2",
2206 : "znver3",
2207 : "znver4",
2208 : "znver5",
2209 : "znver6",
2210 : "c86-4g-m4",
2211 : "c86-4g-m6",
2212 : "c86-4g-m7",
2213 : "c86-4g-m8"
2214 : };
2215 :
2216 : /* Guarantee that the array is aligned with enum processor_type. */
2217 : STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2218 :
2219 : const pta processor_alias_table[] =
2220 : {
2221 : {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2222 : {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2223 : {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2224 : {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2225 : {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2226 : 0, P_NONE},
2227 : {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2228 : {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2229 : {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2230 : 0, P_NONE},
2231 : {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2232 : {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2233 : 0, P_NONE},
2234 : {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2235 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2236 : {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2237 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2238 : {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2239 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2240 : {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2241 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2242 : {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2243 : {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2244 : {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2245 : 0, P_NONE},
2246 : {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2247 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2248 : {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2249 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2250 : {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2251 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2252 : {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2253 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2254 : {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2255 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2256 : {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2257 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2258 : {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2259 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2260 : | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2261 : {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2262 : M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2263 : {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2264 : M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2265 : {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2266 : M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2267 : {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2268 : M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2269 : {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2270 : PTA_SANDYBRIDGE,
2271 : M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2272 : {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2273 : PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2274 : {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2275 : PTA_IVYBRIDGE,
2276 : M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2277 : {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2278 : PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2279 : {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2280 : M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2281 : {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2282 : 0, P_PROC_DYNAMIC},
2283 : {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2284 : M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2285 : {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2286 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2287 : {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2288 : PTA_SKYLAKE_AVX512,
2289 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2290 : {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2291 : M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2292 : {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2293 : PTA_ICELAKE_CLIENT,
2294 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2295 : {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2296 : PTA_ROCKETLAKE,
2297 : M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2298 : {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2299 : PTA_ICELAKE_SERVER,
2300 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2301 : {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2302 : PTA_CASCADELAKE,
2303 : M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2304 : {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2305 : M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2306 : {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2307 : M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2308 : {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2309 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2310 : {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2311 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2312 : {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2313 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2314 : {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2315 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2316 : {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2317 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2318 : {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2319 : M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1},
2320 : {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2321 : PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2322 : P_PROC_AVX10_1},
2323 : {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2324 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2325 : {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2326 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2327 : {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2328 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2329 : {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2330 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2331 : {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS,
2332 : M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_2},
2333 : {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2334 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2335 : {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
2336 : M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
2337 : {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2338 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2339 : {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2340 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2341 : {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2342 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2343 : {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2344 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2345 : {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2346 : M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2347 : {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2348 : M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2349 : {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2350 : M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2351 : {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2352 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2353 : {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2354 : M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2355 : {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2356 : M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2357 : {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2358 : PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2359 : {"intel", PROCESSOR_INTEL, CPU_HASWELL, PTA_HASWELL,
2360 : M_VENDOR (VENDOR_INTEL), P_NONE},
2361 : {"geode", PROCESSOR_GEODE, CPU_GEODE,
2362 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2363 : {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2364 : {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2365 : {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2366 : {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2367 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2368 : {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2369 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2370 : {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2371 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2372 : {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2373 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2374 : {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2375 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2376 : {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2377 : {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2378 : 0, P_NONE},
2379 : {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2380 : 0, P_NONE},
2381 : {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2382 : 0, P_NONE},
2383 : {"eden-x2", PROCESSOR_K8, CPU_K8,
2384 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2385 : 0, P_NONE},
2386 : {"nano", PROCESSOR_K8, CPU_K8,
2387 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2388 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2389 : {"nano-1000", PROCESSOR_K8, CPU_K8,
2390 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2391 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2392 : {"nano-2000", PROCESSOR_K8, CPU_K8,
2393 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2394 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2395 : {"nano-3000", PROCESSOR_K8, CPU_K8,
2396 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2397 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2398 : {"nano-x2", PROCESSOR_K8, CPU_K8,
2399 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2400 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2401 : {"eden-x4", PROCESSOR_K8, CPU_K8,
2402 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2403 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2404 : {"nano-x4", PROCESSOR_K8, CPU_K8,
2405 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2406 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2407 : {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2408 : PTA_LUJIAZUI,
2409 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2410 : {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2411 : PTA_YONGFENG,
2412 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2413 : {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2414 : PTA_YONGFENG,
2415 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2416 : {"k8", PROCESSOR_K8, CPU_K8,
2417 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2418 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2419 : {"k8-sse3", PROCESSOR_K8, CPU_K8,
2420 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2421 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2422 : {"opteron", PROCESSOR_K8, CPU_K8,
2423 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2424 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2425 : {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2426 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2427 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2428 : {"athlon64", PROCESSOR_K8, CPU_K8,
2429 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2430 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2431 : {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2432 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2433 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2434 : {"athlon-fx", PROCESSOR_K8, CPU_K8,
2435 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2436 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2437 : {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2438 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2439 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2440 : 0, P_PROC_DYNAMIC},
2441 : {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2442 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2443 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2444 : M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2445 : {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2446 : PTA_BDVER1,
2447 : M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2448 : {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2449 : PTA_BDVER2,
2450 : M_CPU_SUBTYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2451 : {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2452 : PTA_BDVER3,
2453 : M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2454 : {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2455 : PTA_BDVER4,
2456 : M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2457 : {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2458 : PTA_ZNVER1,
2459 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2460 : {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2461 : PTA_ZNVER2,
2462 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2463 : {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2464 : PTA_ZNVER3,
2465 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2466 : {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2467 : PTA_ZNVER4,
2468 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2469 : {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2470 : PTA_ZNVER5,
2471 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2472 : {"znver6", PROCESSOR_ZNVER6, CPU_ZNVER5,
2473 : PTA_ZNVER6,
2474 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER6), P_PROC_AVX512F},
2475 : {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2476 : PTA_BTVER1,
2477 : M_CPU_TYPE (AMD_BTVER1), P_PROC_SSE4_A},
2478 : {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2479 : PTA_BTVER2,
2480 : M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2481 : {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
2482 : PTA_C86_4G_M4,
2483 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
2484 : {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
2485 : PTA_C86_4G_M6,
2486 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
2487 : {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
2488 : PTA_C86_4G_M7,
2489 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
2490 : {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8,
2491 : PTA_C86_4G_M8,
2492 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F},
2493 :
2494 : {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2495 : PTA_64BIT
2496 : | PTA_HLE /* flags are only used for -march switch. */,
2497 : 0, P_NONE},
2498 :
2499 : {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2500 : M_VENDOR (VENDOR_AMD), P_NONE},
2501 : {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2502 : M_CPU_TYPE (AMDFAM10H), P_NONE},
2503 : {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2504 : M_CPU_TYPE (AMDFAM15H), P_NONE},
2505 : {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2506 : M_CPU_TYPE (AMDFAM17H), P_NONE},
2507 : {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2508 : M_CPU_TYPE (AMDFAM19H), P_NONE},
2509 : {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2510 : M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
2511 : {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2512 : M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
2513 : {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2514 : M_VENDOR (VENDOR_HYGON), P_NONE},
2515 : {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2516 : M_CPU_TYPE (HYGONFAM18H), P_NONE},
2517 : };
2518 :
2519 : /* NB: processor_alias_table stops at the "generic" entry. */
2520 : unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
2521 : unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2522 :
2523 : /* Provide valid option values for -march and -mtune options. */
2524 :
2525 : vec<const char *>
2526 160173 : ix86_get_valid_option_values (int option_code,
2527 : const char *prefix ATTRIBUTE_UNUSED)
2528 : {
2529 160173 : vec<const char *> v;
2530 160173 : v.create (0);
2531 160173 : opt_code opt = (opt_code) option_code;
2532 :
2533 160173 : switch (opt)
2534 : {
2535 : case OPT_march_:
2536 73689 : for (unsigned i = 0; i < pta_size; i++)
2537 : {
2538 73080 : const char *name = processor_alias_table[i].name;
2539 73080 : gcc_checking_assert (name != NULL);
2540 73080 : v.safe_push (name);
2541 : }
2542 : #ifdef HAVE_LOCAL_CPU_DETECT
2543 : /* Add also "native" as possible value. */
2544 609 : v.safe_push ("native");
2545 : #endif
2546 :
2547 609 : break;
2548 : case OPT_mtune_:
2549 38976 : for (unsigned i = 0; i < PROCESSOR_max; i++)
2550 : {
2551 38367 : const char *name = processor_names[i];
2552 38367 : gcc_checking_assert (name != NULL);
2553 38367 : v.safe_push (name);
2554 : }
2555 : break;
2556 : default:
2557 : break;
2558 : }
2559 :
2560 160173 : return v;
2561 : }
2562 :
2563 : #undef TARGET_GET_VALID_OPTION_VALUES
2564 : #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2565 :
2566 : struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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