Line data Source code
1 : /* IA-32 common hooks.
2 : Copyright (C) 1988-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify
7 : it under the terms of the GNU General Public License as published by
8 : the Free Software Foundation; either version 3, or (at your option)
9 : any later version.
10 :
11 : GCC is distributed in the hope that it will be useful,
12 : but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : GNU General Public License for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "diagnostic-core.h"
24 : #include "tm.h"
25 : #include "memmodel.h"
26 : #include "tm_p.h"
27 : #include "common/common-target.h"
28 : #include "common/common-target-def.h"
29 : #include "opts.h"
30 : #include "flags.h"
31 :
32 : /* Define a set of ISAs which are available when a given ISA is
33 : enabled. MMX and SSE ISAs are handled separately. */
34 :
35 : #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 : #define OPTION_MASK_ISA_3DNOW_SET \
37 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 : #define OPTION_MASK_ISA_3DNOW_A_SET \
39 : (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 :
41 : #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 : #define OPTION_MASK_ISA_SSE2_SET \
43 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 : #define OPTION_MASK_ISA_SSE3_SET \
45 : (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 : #define OPTION_MASK_ISA_SSSE3_SET \
47 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 : #define OPTION_MASK_ISA_SSE4_1_SET \
49 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 : #define OPTION_MASK_ISA_SSE4_2_SET \
51 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 : #define OPTION_MASK_ISA_AVX_SET \
53 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 : | OPTION_MASK_ISA_XSAVE_SET)
55 : #define OPTION_MASK_ISA_FMA_SET \
56 : (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 : #define OPTION_MASK_ISA_AVX2_SET \
58 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 : #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 : #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 : #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 : (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 : #define OPTION_MASK_ISA_AVX512F_SET \
64 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 : #define OPTION_MASK_ISA_AVX512CD_SET \
66 : (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 : #define OPTION_MASK_ISA_AVX512DQ_SET \
68 : (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 : #define OPTION_MASK_ISA_AVX512BW_SET \
70 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 : #define OPTION_MASK_ISA_AVX512VL_SET \
72 : (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 : #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 : (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 : #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 : #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 : (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 : #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 : (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 : #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 : #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 : #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 : (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 : #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 : (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 : #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 : (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 : #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 : #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 : #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 : #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 : #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 : #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 : #define OPTION_MASK_ISA_XSAVES_SET \
96 : (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 : #define OPTION_MASK_ISA_XSAVEC_SET \
98 : (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 : #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 : #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 : #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 : #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 : #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 : #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 : #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 : #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 : #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 : #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 : #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 : #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 : #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 : #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 : #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 : #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 : #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
121 : #define OPTION_MASK_ISA_AVX10_1_SET \
122 : (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
123 : | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
124 : | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
125 : | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
126 : | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
127 : | OPTION_MASK_ISA_AVX512BITALG_SET)
128 : #define OPTION_MASK_ISA2_AVX10_1_SET \
129 : (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
130 : | OPTION_MASK_ISA2_AVX10_1)
131 : #define OPTION_MASK_ISA2_AVX10_2_SET \
132 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
133 : #define OPTION_MASK_ISA2_AMX_AVX512_SET \
134 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
135 : #define OPTION_MASK_ISA2_AMX_TF32_SET \
136 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_TF32)
137 : #define OPTION_MASK_ISA2_AMX_FP8_SET \
138 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
139 : #define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
140 : #define OPTION_MASK_ISA2_AMX_MOVRS_SET \
141 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS)
142 : #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
143 :
144 : /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
145 : as -msse4.2. */
146 : #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
147 :
148 : #define OPTION_MASK_ISA_SSE4A_SET \
149 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
150 : #define OPTION_MASK_ISA_FMA4_SET \
151 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
152 : | OPTION_MASK_ISA_AVX_SET)
153 : #define OPTION_MASK_ISA_XOP_SET \
154 : (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
155 : #define OPTION_MASK_ISA_LWP_SET \
156 : OPTION_MASK_ISA_LWP
157 :
158 : /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
159 : #define OPTION_MASK_ISA_AES_SET \
160 : (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
161 : #define OPTION_MASK_ISA_SHA_SET \
162 : (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
163 : #define OPTION_MASK_ISA_PCLMUL_SET \
164 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
165 :
166 : #define OPTION_MASK_ISA_ABM_SET \
167 : (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
168 :
169 : #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
170 : #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
171 : #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
172 : #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
173 : #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
174 : #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
175 : #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
176 : #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
177 : #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
178 : #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
179 : #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
180 : #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
181 :
182 : #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
183 : #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
184 : #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
185 : #define OPTION_MASK_ISA_F16C_SET \
186 : (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
187 : #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
188 : #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
189 : #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
190 : #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
191 : #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
192 : #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
193 : #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
194 : #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
195 : #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
196 : (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
197 : | OPTION_MASK_ISA_AVX_SET)
198 : #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
199 : #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
200 : #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
201 : #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
202 : #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
203 : #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
204 : #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
205 : #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
206 : #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
207 : #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
208 : #define OPTION_MASK_ISA2_WIDEKL_SET \
209 : (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
210 :
211 : /* Define a set of ISAs which aren't available when a given ISA is
212 : disabled. MMX and SSE ISAs are handled separately. */
213 :
214 : #define OPTION_MASK_ISA_MMX_UNSET \
215 : (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
216 : #define OPTION_MASK_ISA_3DNOW_UNSET \
217 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
218 : #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
219 :
220 : #define OPTION_MASK_ISA_SSE_UNSET \
221 : (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
222 : #define OPTION_MASK_ISA_SSE2_UNSET \
223 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
224 : #define OPTION_MASK_ISA_SSE3_UNSET \
225 : (OPTION_MASK_ISA_SSE3 \
226 : | OPTION_MASK_ISA_SSSE3_UNSET \
227 : | OPTION_MASK_ISA_SSE4A_UNSET )
228 : #define OPTION_MASK_ISA_SSSE3_UNSET \
229 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
230 : #define OPTION_MASK_ISA_SSE4_1_UNSET \
231 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
232 : #define OPTION_MASK_ISA_SSE4_2_UNSET \
233 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
234 : #define OPTION_MASK_ISA_AVX_UNSET \
235 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
236 : | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
237 : | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
238 : #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
239 : #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
240 : #define OPTION_MASK_ISA_XSAVE_UNSET \
241 : (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
242 : | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
243 : | OPTION_MASK_ISA_AVX_UNSET)
244 : #define OPTION_MASK_ISA2_XSAVE_UNSET \
245 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
246 : #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
247 : #define OPTION_MASK_ISA_AVX2_UNSET \
248 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
249 : #define OPTION_MASK_ISA2_AVX2_UNSET \
250 : (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
251 : | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
252 : | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
253 : #define OPTION_MASK_ISA_AVX512F_UNSET \
254 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
255 : | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
256 : | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
257 : | OPTION_MASK_ISA_AVX512VNNI_UNSET \
258 : | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
259 : #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
260 : #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
261 : #define OPTION_MASK_ISA_AVX512BW_UNSET \
262 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
263 : | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
264 : #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
265 : #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
266 : #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
267 : #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
268 : #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
269 : #define OPTION_MASK_ISA2_AVX512FP16_UNSET \
270 : (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
271 : #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
272 : #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
273 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
274 : #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
275 : #define OPTION_MASK_ISA2_AVX512BF16_UNSET \
276 : (OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
277 : #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
278 : #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
279 : #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
280 : #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
281 : #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
282 : #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
283 : #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
284 : #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
285 : #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
286 : #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
287 : #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
288 : #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
289 : #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
290 : #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
291 : #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
292 : #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
293 : #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
294 : #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
295 : #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
296 : #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
297 : #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
298 : #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
299 : #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
300 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
301 : #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
302 : #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
303 : (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
304 : | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
305 : | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
306 : | OPTION_MASK_ISA2_AMX_TF32_UNSET | OPTION_MASK_ISA2_AMX_FP8_UNSET \
307 : | OPTION_MASK_ISA2_AMX_MOVRS_UNSET)
308 : #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
309 : #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
310 : #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
311 : #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
312 : #define OPTION_MASK_ISA2_KL_UNSET \
313 : (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
314 : #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
315 : #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
316 : #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
317 : #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
318 : #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
319 : #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
320 : #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
321 : #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
322 : #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
323 : #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
324 : #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
325 : #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
326 : #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
327 : #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
328 : #define OPTION_MASK_ISA2_AVX10_1_UNSET \
329 : (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET)
330 : #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
331 : #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
332 : #define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32
333 : #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
334 : #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
335 : #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
336 : #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
337 :
338 : /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
339 : as -mno-sse4.1. */
340 : #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
341 :
342 : #define OPTION_MASK_ISA_SSE4A_UNSET \
343 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
344 :
345 : #define OPTION_MASK_ISA_FMA4_UNSET \
346 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
347 : #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
348 : #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
349 :
350 : #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
351 : #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
352 : #define OPTION_MASK_ISA_PCLMUL_UNSET \
353 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
354 : #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
355 : #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
356 : #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
357 : #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
358 : #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
359 : #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
360 : #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
361 : #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
362 : #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
363 : #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
364 : #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
365 : #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
366 : #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
367 :
368 : #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
369 : #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
370 : #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
371 : #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
372 :
373 : #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
374 : (OPTION_MASK_ISA_MMX_UNSET \
375 : | OPTION_MASK_ISA_SSE_UNSET)
376 :
377 : #define OPTION_MASK_ISA2_AVX512F_UNSET \
378 : (OPTION_MASK_ISA2_AVX512BW_UNSET \
379 : | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
380 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
381 : | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
382 : #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
383 : OPTION_MASK_ISA2_SSE_UNSET
384 : #define OPTION_MASK_ISA2_AVX_UNSET \
385 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
386 : | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
387 : | OPTION_MASK_ISA2_SM4_UNSET)
388 : #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
389 : #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
390 : #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
391 : #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
392 : #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
393 : #define OPTION_MASK_ISA2_SSE2_UNSET \
394 : (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
395 : #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
396 :
397 : #define OPTION_MASK_ISA2_AVX512BW_UNSET \
398 : (OPTION_MASK_ISA2_AVX512BF16_UNSET \
399 : | OPTION_MASK_ISA2_AVX512FP16_UNSET \
400 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
401 : | OPTION_MASK_ISA2_AVX512BMM_UNSET)
402 : #define OPTION_MASK_ISA2_AVX512CD_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
403 : #define OPTION_MASK_ISA2_AVX512DQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
404 : #define OPTION_MASK_ISA2_AVX512VL_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
405 : #define OPTION_MASK_ISA2_AVX512IFMA_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
406 : #define OPTION_MASK_ISA2_AVX512VNNI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
407 : #define OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
408 : #define OPTION_MASK_ISA2_AVX512VBMI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
409 : #define OPTION_MASK_ISA2_AVX512VBMI2_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
410 : #define OPTION_MASK_ISA2_AVX512BITALG_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
411 :
412 : /* Set 1 << value as value of -malign-FLAG option. */
413 :
414 : static void
415 1 : set_malign_value (const char **flag, unsigned value)
416 : {
417 1 : char *r = XNEWVEC (char, 6);
418 1 : sprintf (r, "%d", 1 << value);
419 1 : *flag = r;
420 1 : }
421 :
422 : /* Implement TARGET_HANDLE_OPTION. */
423 :
424 : bool
425 67715059 : ix86_handle_option (struct gcc_options *opts,
426 : struct gcc_options *opts_set ATTRIBUTE_UNUSED,
427 : const struct cl_decoded_option *decoded,
428 : location_t loc)
429 : {
430 67715059 : size_t code = decoded->opt_index;
431 67715059 : int value = decoded->value;
432 :
433 67715059 : switch (code)
434 : {
435 1972489 : case OPT_mgeneral_regs_only:
436 1972489 : if (value)
437 : {
438 1972489 : HOST_WIDE_INT general_regs_only_flags = 0;
439 1972489 : HOST_WIDE_INT general_regs_only_flags2 = 0;
440 :
441 : /* NB: Enable the GPR only instructions which are enabled
442 : implicitly by SSE ISAs unless they have been disabled
443 : explicitly. */
444 1972489 : if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
445 : {
446 6476 : if (!TARGET_EXPLICIT_CRC32_P (opts))
447 4565 : general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
448 6476 : if (!TARGET_EXPLICIT_POPCNT_P (opts))
449 4547 : general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
450 : }
451 1972489 : if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
452 : {
453 6884 : if (!TARGET_EXPLICIT_MWAIT_P (opts))
454 1972489 : general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
455 : }
456 :
457 : /* Disable MMX, SSE and x87 instructions if only
458 : general registers are allowed. */
459 1972489 : opts->x_ix86_isa_flags
460 1972489 : &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
461 1972489 : opts->x_ix86_isa_flags2
462 1972489 : &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
463 1972489 : opts->x_ix86_isa_flags |= general_regs_only_flags;
464 1972489 : opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
465 1972489 : opts->x_ix86_isa_flags_explicit
466 1972489 : |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
467 : | general_regs_only_flags);
468 1972489 : opts->x_ix86_isa_flags2_explicit
469 1972489 : |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
470 : | general_regs_only_flags2);
471 :
472 1972489 : opts->x_target_flags &= ~MASK_80387;
473 : }
474 : else
475 0 : gcc_unreachable ();
476 1972489 : return true;
477 :
478 3462 : case OPT_mmmx:
479 3462 : if (value)
480 : {
481 1645 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
482 1645 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
483 : }
484 : else
485 : {
486 1817 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
487 1817 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
488 : }
489 : return true;
490 :
491 83533 : case OPT_m3dnow:
492 83533 : if (value)
493 : {
494 83520 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
495 83520 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
496 : }
497 : else
498 : {
499 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
500 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
501 : }
502 : return true;
503 :
504 6006 : case OPT_m3dnowa:
505 6006 : if (value)
506 : {
507 6005 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
508 6005 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
509 : }
510 : else
511 : {
512 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
513 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
514 : }
515 : return true;
516 :
517 33767 : case OPT_msse:
518 33767 : if (value)
519 : {
520 33668 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
521 33668 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
522 : }
523 : else
524 : {
525 99 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
526 99 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
527 99 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
528 99 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
529 : }
530 : return true;
531 :
532 86749 : case OPT_msse2:
533 86749 : if (value)
534 : {
535 86634 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
536 86634 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
537 : }
538 : else
539 : {
540 115 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
541 115 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
542 115 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
543 115 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
544 : }
545 : return true;
546 :
547 24621 : case OPT_msse3:
548 24621 : if (value)
549 : {
550 24538 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
551 24538 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
552 : }
553 : else
554 : {
555 83 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
556 83 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
557 83 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
558 83 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
559 : }
560 : return true;
561 :
562 46053 : case OPT_mssse3:
563 46053 : if (value)
564 : {
565 46045 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
566 46045 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
567 : }
568 : else
569 : {
570 8 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
571 8 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
572 8 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
573 8 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
574 : }
575 : return true;
576 :
577 79022 : case OPT_msse4_1:
578 79022 : if (value)
579 : {
580 78996 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
581 78996 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
582 : }
583 : else
584 : {
585 26 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
586 26 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
587 26 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
588 26 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
589 : }
590 : return true;
591 :
592 29480 : case OPT_msse4_2:
593 29480 : if (value)
594 : {
595 29467 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
596 29467 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
597 : }
598 : else
599 : {
600 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
601 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
602 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
603 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
604 : }
605 : return true;
606 :
607 299134 : case OPT_mavx:
608 299134 : if (value)
609 : {
610 297517 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
611 297517 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
612 : }
613 : else
614 : {
615 1617 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
616 1617 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
617 1617 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
618 1617 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
619 : }
620 : return true;
621 :
622 613108 : case OPT_mavx2:
623 613108 : if (value)
624 : {
625 613034 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
626 613034 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
627 : }
628 : else
629 : {
630 74 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
631 74 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
632 74 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
633 74 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
634 : }
635 : return true;
636 :
637 5018995 : case OPT_mavx512f:
638 5018995 : if (value)
639 : {
640 5018882 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
641 5018882 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
642 : }
643 : else
644 : {
645 113 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
646 113 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
647 113 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
648 113 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
649 : }
650 : return true;
651 :
652 415426 : case OPT_mavx512cd:
653 415426 : if (value)
654 : {
655 415402 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
656 415402 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
657 : }
658 : else
659 : {
660 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
661 24 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
662 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512CD_UNSET;
663 24 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512CD_UNSET;
664 : }
665 : return true;
666 :
667 61955 : case OPT_mrdpid:
668 61955 : if (value)
669 : {
670 61954 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
671 61954 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
672 : }
673 : else
674 : {
675 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
676 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
677 : }
678 : return true;
679 :
680 362459 : case OPT_mgfni:
681 362459 : if (value)
682 : {
683 362446 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
684 362446 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
685 : }
686 : else
687 : {
688 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
689 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
690 : }
691 : return true;
692 :
693 123857 : case OPT_mshstk:
694 123857 : if (value)
695 : {
696 123845 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
697 123845 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
698 : }
699 : else
700 : {
701 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
702 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
703 : }
704 : return true;
705 :
706 90216 : case OPT_mvaes:
707 90216 : if (value)
708 : {
709 90204 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
710 90204 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
711 90204 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
712 90204 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
713 : }
714 : else
715 : {
716 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
717 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
718 : }
719 : return true;
720 :
721 74350 : case OPT_mvpclmulqdq:
722 74350 : if (value)
723 : {
724 74338 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
725 74338 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
726 : }
727 : else
728 : {
729 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
730 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
731 : }
732 : return true;
733 :
734 25354 : case OPT_mmovdiri:
735 25354 : if (value)
736 : {
737 25343 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
738 25343 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
739 : }
740 : else
741 : {
742 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
743 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
744 : }
745 : return true;
746 :
747 15368 : case OPT_mmovdir64b:
748 15368 : if (value)
749 : {
750 15357 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
751 15357 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
752 : }
753 : else
754 : {
755 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
756 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
757 : }
758 : return true;
759 :
760 15364 : case OPT_mcldemote:
761 15364 : if (value)
762 : {
763 15353 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
764 15353 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
765 : }
766 : else
767 : {
768 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
769 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
770 : }
771 : return true;
772 :
773 35539 : case OPT_mwaitpkg:
774 35539 : if (value)
775 : {
776 35528 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
777 35528 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
778 : }
779 : else
780 : {
781 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
782 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
783 : }
784 : return true;
785 :
786 71396 : case OPT_menqcmd:
787 71396 : if (value)
788 : {
789 71384 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
790 71384 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
791 : }
792 : else
793 : {
794 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
795 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
796 : }
797 : return true;
798 :
799 145553 : case OPT_mkl:
800 145553 : if (value)
801 : {
802 145541 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
803 145541 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
804 :
805 : /* The Keylocker instructions need XMM registers from SSE2. */
806 145541 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
807 145541 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
808 : }
809 : else
810 : {
811 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
812 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
813 : }
814 : return true;
815 :
816 154197 : case OPT_mwidekl:
817 154197 : if (value)
818 : {
819 154185 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
820 154185 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
821 :
822 : /* The Widekl instructions need XMM registers from SSE2. */
823 154185 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
824 154185 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
825 : }
826 : else
827 : {
828 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
829 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
830 : }
831 : return true;
832 :
833 87516 : case OPT_mserialize:
834 87516 : if (value)
835 : {
836 87503 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
837 87503 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
838 : }
839 : else
840 : {
841 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
842 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
843 : }
844 : return true;
845 :
846 46418 : case OPT_muintr:
847 46418 : if (value)
848 : {
849 46406 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
850 46406 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
851 : }
852 : else
853 : {
854 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
855 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
856 : }
857 : return true;
858 :
859 16903 : case OPT_mhreset:
860 16903 : if (value)
861 : {
862 16891 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
863 16891 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
864 : }
865 : else
866 : {
867 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
868 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
869 : }
870 : return true;
871 :
872 1436857 : case OPT_mavx512vbmi2:
873 1436857 : if (value)
874 : {
875 1436846 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
876 1436846 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
877 : }
878 : else
879 : {
880 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
881 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
882 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
883 11 : opts->x_ix86_isa_flags2_explicit
884 11 : |= OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
885 : }
886 : return true;
887 :
888 7943245 : case OPT_mavx512fp16:
889 7943245 : if (value)
890 : {
891 7943230 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
892 7943230 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
893 7943230 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
894 7943230 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
895 : }
896 : else
897 : {
898 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
899 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
900 : }
901 : return true;
902 :
903 282081 : case OPT_mavx512vnni:
904 282081 : if (value)
905 : {
906 282069 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
907 282069 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
908 : }
909 : else
910 : {
911 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
912 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
913 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VNNI_UNSET;
914 12 : opts->x_ix86_isa_flags2_explicit
915 12 : |= OPTION_MASK_ISA2_AVX512VNNI_UNSET;
916 : }
917 : return true;
918 :
919 184929 : case OPT_mavx512vpopcntdq:
920 184929 : if (value)
921 : {
922 184905 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
923 184905 : opts->x_ix86_isa_flags_explicit
924 184905 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
925 : }
926 : else
927 : {
928 24 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
929 24 : opts->x_ix86_isa_flags_explicit
930 24 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
931 24 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
932 24 : opts->x_ix86_isa_flags2_explicit
933 24 : |= OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
934 : }
935 : return true;
936 :
937 243052 : case OPT_mavx512bitalg:
938 243052 : if (value)
939 : {
940 243041 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
941 243041 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
942 : }
943 : else
944 : {
945 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
946 11 : opts->x_ix86_isa_flags_explicit
947 11 : |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
948 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BITALG_UNSET;
949 11 : opts->x_ix86_isa_flags2_explicit
950 11 : |= OPTION_MASK_ISA2_AVX512BITALG_UNSET;
951 : }
952 : return true;
953 :
954 418352 : case OPT_mavx512bf16:
955 418352 : if (value)
956 : {
957 418338 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
958 418338 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
959 418338 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
960 418338 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
961 : }
962 : else
963 : {
964 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
965 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
966 : }
967 : return true;
968 :
969 140444 : case OPT_mavx512bmm:
970 140444 : if (value)
971 : {
972 140433 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BMM_SET;
973 140433 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_SET;
974 140433 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
975 140433 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
976 : }
977 : else
978 : {
979 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BMM_UNSET;
980 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_UNSET;
981 : }
982 : return true;
983 :
984 155382 : case OPT_mavxvnni:
985 155382 : if (value)
986 : {
987 155368 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
988 155368 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
989 155368 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
990 155368 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
991 : }
992 : else
993 : {
994 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
995 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
996 : }
997 : return true;
998 :
999 111018 : case OPT_msgx:
1000 111018 : if (value)
1001 : {
1002 111006 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
1003 111006 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
1004 : }
1005 : else
1006 : {
1007 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
1008 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
1009 : }
1010 : return true;
1011 :
1012 71027 : case OPT_mpconfig:
1013 71027 : if (value)
1014 : {
1015 71016 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
1016 71016 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
1017 : }
1018 : else
1019 : {
1020 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
1021 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
1022 : }
1023 : return true;
1024 :
1025 61324 : case OPT_mwbnoinvd:
1026 61324 : if (value)
1027 : {
1028 61324 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1029 61324 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1030 : }
1031 : else
1032 : {
1033 0 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1034 0 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1035 : }
1036 : return true;
1037 :
1038 3606314 : case OPT_mavx512dq:
1039 3606314 : if (value)
1040 : {
1041 3606281 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1042 3606281 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1043 : }
1044 : else
1045 : {
1046 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1047 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1048 33 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512DQ_UNSET;
1049 33 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512DQ_UNSET;
1050 : }
1051 : return true;
1052 :
1053 6868738 : case OPT_mavx512bw:
1054 6868738 : if (value)
1055 : {
1056 6868682 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1057 6868682 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1058 : }
1059 : else
1060 : {
1061 56 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1062 56 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1063 56 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1064 56 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1065 : }
1066 : return true;
1067 :
1068 20511104 : case OPT_mavx512vl:
1069 20511104 : if (value)
1070 : {
1071 20511044 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1072 20511044 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1073 : }
1074 : else
1075 : {
1076 60 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1077 60 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1078 60 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VL_UNSET;
1079 60 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VL_UNSET;
1080 : }
1081 : return true;
1082 :
1083 146117 : case OPT_mavx512ifma:
1084 146117 : if (value)
1085 : {
1086 146105 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1087 146105 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1088 : }
1089 : else
1090 : {
1091 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1092 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1093 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1094 12 : opts->x_ix86_isa_flags2_explicit
1095 12 : |= OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1096 : }
1097 : return true;
1098 :
1099 301414 : case OPT_mavx512vbmi:
1100 301414 : if (value)
1101 : {
1102 301402 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1103 301402 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1104 : }
1105 : else
1106 : {
1107 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1108 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1109 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1110 12 : opts->x_ix86_isa_flags2_explicit
1111 12 : |= OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1112 : }
1113 : return true;
1114 :
1115 140900 : case OPT_mavx512vp2intersect:
1116 140900 : if (value)
1117 : {
1118 140888 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1119 140888 : opts->x_ix86_isa_flags2_explicit |=
1120 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1121 140888 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1122 140888 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1123 : }
1124 : else
1125 : {
1126 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1127 12 : opts->x_ix86_isa_flags2_explicit |=
1128 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1129 : }
1130 : return true;
1131 :
1132 97576 : case OPT_mtsxldtrk:
1133 97576 : if (value)
1134 : {
1135 97564 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1136 97564 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1137 : }
1138 : else
1139 : {
1140 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1141 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1142 : }
1143 : return true;
1144 :
1145 105017 : case OPT_mamx_tile:
1146 105017 : if (value)
1147 : {
1148 105005 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1149 105005 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1150 105005 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1151 105005 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1152 : }
1153 : else
1154 : {
1155 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1156 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1157 : }
1158 : return true;
1159 :
1160 75880 : case OPT_mamx_int8:
1161 75880 : if (value)
1162 : {
1163 75868 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1164 75868 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1165 : }
1166 : else
1167 : {
1168 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1169 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1170 : }
1171 : return true;
1172 :
1173 75882 : case OPT_mamx_bf16:
1174 75882 : if (value)
1175 : {
1176 75870 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1177 75870 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1178 : }
1179 : else
1180 : {
1181 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1182 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1183 : }
1184 : return true;
1185 :
1186 115744 : case OPT_mavxifma:
1187 115744 : if (value)
1188 : {
1189 115732 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1190 115732 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1191 115732 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1192 115732 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1193 : }
1194 : else
1195 : {
1196 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1197 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1198 : }
1199 : return true;
1200 :
1201 195395 : case OPT_mavxvnniint8:
1202 195395 : if (value)
1203 : {
1204 195382 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1205 195382 : opts->x_ix86_isa_flags2_explicit |=
1206 : OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1207 195382 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1208 195382 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1209 : }
1210 : else
1211 : {
1212 13 : opts->x_ix86_isa_flags2 &=
1213 : ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1214 13 : opts->x_ix86_isa_flags2_explicit |=
1215 : OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1216 : }
1217 : return true;
1218 :
1219 215310 : case OPT_mavxneconvert:
1220 215310 : if (value)
1221 : {
1222 215296 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1223 215296 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1224 215296 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1225 215296 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1226 : }
1227 : else
1228 : {
1229 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1230 14 : opts->x_ix86_isa_flags2_explicit
1231 14 : |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1232 : }
1233 : return true;
1234 :
1235 70679 : case OPT_mcmpccxadd:
1236 70679 : if (value)
1237 : {
1238 70667 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1239 70667 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1240 : }
1241 : else
1242 : {
1243 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1244 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1245 : }
1246 : return true;
1247 :
1248 70711 : case OPT_mamx_fp16:
1249 70711 : if (value)
1250 : {
1251 70699 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1252 70699 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1253 : }
1254 : else
1255 : {
1256 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1257 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1258 : }
1259 : return true;
1260 :
1261 70683 : case OPT_mprefetchi:
1262 70683 : if (value)
1263 : {
1264 70671 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1265 70671 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1266 : }
1267 : else
1268 : {
1269 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1270 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1271 : }
1272 : return true;
1273 :
1274 157679 : case OPT_mraoint:
1275 157679 : if (value)
1276 : {
1277 157667 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1278 157667 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1279 : }
1280 : else
1281 : {
1282 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1283 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1284 : }
1285 : return true;
1286 :
1287 75890 : case OPT_mamx_complex:
1288 75890 : if (value)
1289 : {
1290 75878 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1291 75878 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1292 : }
1293 : else
1294 : {
1295 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1296 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1297 : }
1298 : return true;
1299 :
1300 195371 : case OPT_mavxvnniint16:
1301 195371 : if (value)
1302 : {
1303 195358 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1304 195358 : opts->x_ix86_isa_flags2_explicit |=
1305 : OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1306 195358 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1307 195358 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1308 : }
1309 : else
1310 : {
1311 13 : opts->x_ix86_isa_flags2 &=
1312 : ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1313 13 : opts->x_ix86_isa_flags2_explicit |=
1314 : OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1315 : }
1316 : return true;
1317 :
1318 105377 : case OPT_msm3:
1319 105377 : if (value)
1320 : {
1321 105365 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1322 105365 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1323 105365 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1324 105365 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1325 : }
1326 : else
1327 : {
1328 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1329 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1330 : }
1331 : return true;
1332 :
1333 105797 : case OPT_msha512:
1334 105797 : if (value)
1335 : {
1336 105785 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1337 105785 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1338 105785 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1339 105785 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1340 : }
1341 : else
1342 : {
1343 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1344 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1345 : }
1346 : return true;
1347 :
1348 140863 : case OPT_msm4:
1349 140863 : if (value)
1350 : {
1351 140851 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1352 140851 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1353 140851 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1354 140851 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1355 : }
1356 : else
1357 : {
1358 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1359 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1360 : }
1361 : return true;
1362 :
1363 114 : case OPT_mapxf:
1364 114 : if (value)
1365 : {
1366 80 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1367 80 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1368 80 : opts->x_ix86_apx_features = apx_all;
1369 : }
1370 : else
1371 : {
1372 34 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1373 34 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1374 34 : opts->x_ix86_apx_features = apx_none;
1375 : }
1376 : return true;
1377 :
1378 27113 : case OPT_musermsr:
1379 27113 : if (value)
1380 : {
1381 27101 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1382 27101 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1383 : }
1384 : else
1385 : {
1386 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1387 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1388 : }
1389 : return true;
1390 :
1391 27 : case OPT_mavx10_1:
1392 27 : if (value)
1393 : {
1394 15 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
1395 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
1396 15 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1397 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1398 : }
1399 : else
1400 : {
1401 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
1402 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
1403 : }
1404 : return true;
1405 :
1406 7607125 : case OPT_mavx10_2:
1407 7607125 : if (value)
1408 : {
1409 7607111 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
1410 7607111 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
1411 7607111 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1412 7607111 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1413 : }
1414 : else
1415 : {
1416 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET;
1417 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET;
1418 : }
1419 : return true;
1420 :
1421 75894 : case OPT_mamx_avx512:
1422 75894 : if (value)
1423 : {
1424 75878 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1425 75878 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1426 75878 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
1427 75878 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
1428 : }
1429 : else
1430 : {
1431 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1432 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1433 : }
1434 : return true;
1435 :
1436 75890 : case OPT_mamx_tf32:
1437 75890 : if (value)
1438 : {
1439 75878 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TF32_SET;
1440 75878 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TF32_SET;
1441 : }
1442 : else
1443 : {
1444 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TF32_UNSET;
1445 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TF32_UNSET;
1446 : }
1447 : return true;
1448 :
1449 70712 : case OPT_mamx_fp8:
1450 70712 : if (value)
1451 : {
1452 70700 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP8_SET;
1453 70700 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_SET;
1454 : }
1455 : else
1456 : {
1457 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP8_UNSET;
1458 12 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_UNSET;
1459 : }
1460 : return true;
1461 :
1462 486297 : case OPT_mmovrs:
1463 486297 : if (value)
1464 : {
1465 486284 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
1466 486284 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
1467 : }
1468 : else
1469 : {
1470 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
1471 13 : opts->x_ix86_isa_flags2_explicit |=
1472 : OPTION_MASK_ISA2_MOVRS_UNSET;
1473 : }
1474 : return true;
1475 :
1476 75804 : case OPT_mamx_movrs:
1477 75804 : if (value)
1478 : {
1479 75792 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1480 75792 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1481 : }
1482 : else
1483 : {
1484 12 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1485 12 : opts->x_ix86_isa_flags2_explicit |=
1486 : OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1487 : }
1488 : return true;
1489 :
1490 357624 : case OPT_mfma:
1491 357624 : if (value)
1492 : {
1493 357612 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1494 357612 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1495 : }
1496 : else
1497 : {
1498 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1499 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1500 : }
1501 : return true;
1502 :
1503 121659 : case OPT_mrtm:
1504 121659 : if (value)
1505 : {
1506 121646 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1507 121646 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1508 : }
1509 : else
1510 : {
1511 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1512 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1513 : }
1514 : return true;
1515 :
1516 195 : case OPT_msse4:
1517 195 : if (value)
1518 : {
1519 151 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1520 151 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1521 : }
1522 : else
1523 : {
1524 44 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1525 44 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1526 44 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1527 44 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1528 : }
1529 : return true;
1530 :
1531 77355 : case OPT_msse4a:
1532 77355 : if (value)
1533 : {
1534 77353 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1535 77353 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1536 : }
1537 : else
1538 : {
1539 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1540 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1541 : }
1542 : return true;
1543 :
1544 91955 : case OPT_mfma4:
1545 91955 : if (value)
1546 : {
1547 91924 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1548 91924 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1549 : }
1550 : else
1551 : {
1552 31 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1553 31 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1554 : }
1555 : return true;
1556 :
1557 181296 : case OPT_mxop:
1558 181296 : if (value)
1559 : {
1560 181267 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1561 181267 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1562 : }
1563 : else
1564 : {
1565 29 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1566 29 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1567 : }
1568 : return true;
1569 :
1570 124821 : case OPT_mlwp:
1571 124821 : if (value)
1572 : {
1573 124808 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1574 124808 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1575 : }
1576 : else
1577 : {
1578 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1579 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1580 : }
1581 : return true;
1582 :
1583 58479 : case OPT_mabm:
1584 58479 : if (value)
1585 : {
1586 58475 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1587 58475 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1588 : }
1589 : else
1590 : {
1591 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1592 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1593 : }
1594 : return true;
1595 :
1596 316197 : case OPT_mbmi:
1597 316197 : if (value)
1598 : {
1599 316196 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1600 316196 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1601 : }
1602 : else
1603 : {
1604 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1605 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1606 : }
1607 : return true;
1608 :
1609 133817 : case OPT_mbmi2:
1610 133817 : if (value)
1611 : {
1612 133812 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1613 133812 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1614 : }
1615 : else
1616 : {
1617 5 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1618 5 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1619 : }
1620 : return true;
1621 :
1622 114502 : case OPT_mlzcnt:
1623 114502 : if (value)
1624 : {
1625 114496 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1626 114496 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1627 : }
1628 : else
1629 : {
1630 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1631 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1632 : }
1633 : return true;
1634 :
1635 265867 : case OPT_mtbm:
1636 265867 : if (value)
1637 : {
1638 265854 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1639 265854 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1640 : }
1641 : else
1642 : {
1643 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1644 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1645 : }
1646 : return true;
1647 :
1648 64585 : case OPT_mpopcnt:
1649 64585 : if (value)
1650 : {
1651 64569 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1652 64569 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1653 : }
1654 : else
1655 : {
1656 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1657 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1658 : }
1659 : return true;
1660 :
1661 17 : case OPT_msahf:
1662 17 : if (value)
1663 : {
1664 15 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1665 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1666 : }
1667 : else
1668 : {
1669 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1670 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1671 : }
1672 : return true;
1673 :
1674 67 : case OPT_mcx16:
1675 67 : if (value)
1676 : {
1677 65 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1678 65 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1679 : }
1680 : else
1681 : {
1682 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1683 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1684 : }
1685 : return true;
1686 :
1687 30 : case OPT_mmovbe:
1688 30 : if (value)
1689 : {
1690 25 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1691 25 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1692 : }
1693 : else
1694 : {
1695 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1696 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1697 : }
1698 : return true;
1699 :
1700 11206 : case OPT_mcrc32:
1701 11206 : if (value)
1702 : {
1703 11202 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1704 11202 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1705 : }
1706 : else
1707 : {
1708 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1709 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1710 : }
1711 : return true;
1712 :
1713 83752 : case OPT_maes:
1714 83752 : if (value)
1715 : {
1716 83750 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1717 83750 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1718 : }
1719 : else
1720 : {
1721 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1722 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1723 : }
1724 : return true;
1725 :
1726 144868 : case OPT_msha:
1727 144868 : if (value)
1728 : {
1729 144867 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1730 144867 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1731 : }
1732 : else
1733 : {
1734 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1735 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1736 : }
1737 : return true;
1738 :
1739 73770 : case OPT_mpclmul:
1740 73770 : if (value)
1741 : {
1742 73769 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1743 73769 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1744 : }
1745 : else
1746 : {
1747 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1748 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1749 : }
1750 : return true;
1751 :
1752 156463 : case OPT_mfsgsbase:
1753 156463 : if (value)
1754 : {
1755 156462 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1756 156462 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1757 : }
1758 : else
1759 : {
1760 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1761 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1762 : }
1763 : return true;
1764 :
1765 112417 : case OPT_mrdrnd:
1766 112417 : if (value)
1767 : {
1768 112416 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1769 112416 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1770 : }
1771 : else
1772 : {
1773 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1774 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1775 : }
1776 : return true;
1777 :
1778 25363 : case OPT_mptwrite:
1779 25363 : if (value)
1780 : {
1781 25352 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1782 25352 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1783 : }
1784 : else
1785 : {
1786 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1787 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1788 : }
1789 : return true;
1790 :
1791 132146 : case OPT_mf16c:
1792 132146 : if (value)
1793 : {
1794 132145 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1795 132145 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1796 : }
1797 : else
1798 : {
1799 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1800 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1801 : }
1802 : return true;
1803 :
1804 60647 : case OPT_mfxsr:
1805 60647 : if (value)
1806 : {
1807 60645 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1808 60645 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1809 : }
1810 : else
1811 : {
1812 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1813 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1814 : }
1815 : return true;
1816 :
1817 6926 : case OPT_mxsave:
1818 6926 : if (value)
1819 : {
1820 6920 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1821 6920 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1822 : }
1823 : else
1824 : {
1825 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1826 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1827 6 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1828 6 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1829 : }
1830 : return true;
1831 :
1832 85737 : case OPT_mxsaveopt:
1833 85737 : if (value)
1834 : {
1835 85736 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1836 85736 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1837 : }
1838 : else
1839 : {
1840 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1841 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1842 : }
1843 : return true;
1844 :
1845 71852 : case OPT_mxsavec:
1846 71852 : if (value)
1847 : {
1848 71850 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1849 71850 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1850 : }
1851 : else
1852 : {
1853 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1854 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1855 : }
1856 : return true;
1857 :
1858 91815 : case OPT_mxsaves:
1859 91815 : if (value)
1860 : {
1861 91813 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1862 91813 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1863 : }
1864 : else
1865 : {
1866 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1867 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1868 : }
1869 : return true;
1870 :
1871 95823 : case OPT_mrdseed:
1872 95823 : if (value)
1873 : {
1874 95821 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1875 95821 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1876 : }
1877 : else
1878 : {
1879 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1880 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1881 : }
1882 : return true;
1883 :
1884 59106 : case OPT_mprfchw:
1885 59106 : if (value)
1886 : {
1887 59104 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1888 59104 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1889 : }
1890 : else
1891 : {
1892 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1893 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1894 : }
1895 : return true;
1896 :
1897 60637 : case OPT_madx:
1898 60637 : if (value)
1899 : {
1900 60633 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1901 60633 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1902 : }
1903 : else
1904 : {
1905 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1906 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1907 : }
1908 : return true;
1909 :
1910 61917 : case OPT_mclflushopt:
1911 61917 : if (value)
1912 : {
1913 61915 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1914 61915 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1915 : }
1916 : else
1917 : {
1918 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1919 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1920 : }
1921 : return true;
1922 :
1923 61936 : case OPT_mclwb:
1924 61936 : if (value)
1925 : {
1926 61934 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1927 61934 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1928 : }
1929 : else
1930 : {
1931 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1932 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1933 : }
1934 : return true;
1935 :
1936 71445 : case OPT_mmwaitx:
1937 71445 : if (value)
1938 : {
1939 71443 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1940 71443 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1941 : }
1942 : else
1943 : {
1944 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1945 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1946 : }
1947 : return true;
1948 :
1949 25685 : case OPT_mmwait:
1950 25685 : if (value)
1951 : {
1952 25684 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1953 25684 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1954 : }
1955 : else
1956 : {
1957 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1958 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1959 : }
1960 : return true;
1961 :
1962 61363 : case OPT_mclzero:
1963 61363 : if (value)
1964 : {
1965 61361 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1966 61361 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1967 : }
1968 : else
1969 : {
1970 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1971 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1972 : }
1973 : return true;
1974 :
1975 71958 : case OPT_mpku:
1976 71958 : if (value)
1977 : {
1978 71945 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1979 71945 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1980 : }
1981 : else
1982 : {
1983 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1984 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1985 : }
1986 : return true;
1987 :
1988 :
1989 1 : case OPT_malign_loops_:
1990 1 : warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1991 : "use %<-falign-loops%>");
1992 1 : if (value > MAX_CODE_ALIGN)
1993 0 : error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1994 : value, MAX_CODE_ALIGN);
1995 : else
1996 1 : set_malign_value (&opts->x_str_align_loops, value);
1997 : return true;
1998 :
1999 0 : case OPT_malign_jumps_:
2000 0 : warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
2001 : "use %<-falign-jumps%>");
2002 0 : if (value > MAX_CODE_ALIGN)
2003 0 : error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
2004 : value, MAX_CODE_ALIGN);
2005 : else
2006 0 : set_malign_value (&opts->x_str_align_jumps, value);
2007 : return true;
2008 :
2009 0 : case OPT_malign_functions_:
2010 0 : warning_at (loc, 0,
2011 : "%<-malign-functions%> is obsolete, "
2012 : "use %<-falign-functions%>");
2013 0 : if (value > MAX_CODE_ALIGN)
2014 0 : error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
2015 : value, MAX_CODE_ALIGN);
2016 : else
2017 0 : set_malign_value (&opts->x_str_align_functions, value);
2018 : return true;
2019 :
2020 20 : case OPT_mbranch_cost_:
2021 20 : if (value > 5)
2022 : {
2023 0 : error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
2024 0 : opts->x_ix86_branch_cost = 5;
2025 : }
2026 : return true;
2027 :
2028 : default:
2029 : return true;
2030 : }
2031 : }
2032 :
2033 : static const struct default_options ix86_option_optimization_table[] =
2034 : {
2035 : /* Enable redundant extension instructions removal at -O2 and higher. */
2036 : { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
2037 : /* Enable function splitting at -O2 and higher. */
2038 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
2039 : /* The STC algorithm produces the smallest code at -Os, for x86. */
2040 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
2041 : REORDER_BLOCKS_ALGORITHM_STC },
2042 :
2043 : /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2044 : loop unrolling at -O2. */
2045 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
2046 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
2047 : /* Turns off -frename-registers and -fweb which are enabled by
2048 : funroll-loops. */
2049 : { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
2050 : { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
2051 : /* Turn off -fschedule-insns by default. It tends to make the
2052 : problem with not enough registers even worse. */
2053 : { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
2054 :
2055 : #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2056 : SUBTARGET_OPTIMIZATION_OPTIONS,
2057 : #endif
2058 : { OPT_LEVELS_NONE, 0, NULL, 0 }
2059 : };
2060 :
2061 : /* Implement TARGET_OPTION_INIT_STRUCT. */
2062 :
2063 : static void
2064 48364164 : ix86_option_init_struct (struct gcc_options *opts)
2065 : {
2066 48364164 : if (TARGET_MACHO)
2067 : /* The Darwin libraries never set errno, so we might as well
2068 : avoid calling them when that's the only reason we would. */
2069 : opts->x_flag_errno_math = 0;
2070 :
2071 48364164 : opts->x_flag_pcc_struct_return = 2;
2072 48364164 : opts->x_flag_asynchronous_unwind_tables = 2;
2073 48364164 : }
2074 :
2075 : /* On the x86 -fsplit-stack and -fstack-protector both use the same
2076 : field in the TCB, so they cannot be used together. */
2077 :
2078 : static bool
2079 6365 : ix86_supports_split_stack (bool report,
2080 : struct gcc_options *opts ATTRIBUTE_UNUSED)
2081 : {
2082 : #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2083 6365 : if (!OPTION_GLIBC_P (opts))
2084 : #endif
2085 : {
2086 0 : if (report)
2087 0 : error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2088 0 : return false;
2089 : }
2090 :
2091 : bool ret = true;
2092 :
2093 : #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2094 : if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
2095 : {
2096 : if (report)
2097 : error ("%<-fsplit-stack%> requires "
2098 : "assembler support for CFI directives");
2099 : ret = false;
2100 : }
2101 : #endif
2102 :
2103 : return ret;
2104 : }
2105 :
2106 : /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2107 :
2108 : static enum unwind_info_type
2109 9047017 : i386_except_unwind_info (struct gcc_options *opts)
2110 : {
2111 : /* Honor the --enable-sjlj-exceptions configure switch. */
2112 : #ifdef CONFIG_SJLJ_EXCEPTIONS
2113 : if (CONFIG_SJLJ_EXCEPTIONS)
2114 : return UI_SJLJ;
2115 : #endif
2116 :
2117 : /* On windows 64, prefer SEH exceptions over anything else. */
2118 9047017 : if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
2119 : return UI_SEH;
2120 :
2121 9047017 : if (DWARF2_UNWIND_INFO)
2122 9047017 : return UI_DWARF2;
2123 :
2124 : return UI_SJLJ;
2125 : }
2126 :
2127 : #undef TARGET_EXCEPT_UNWIND_INFO
2128 : #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2129 :
2130 : #undef TARGET_DEFAULT_TARGET_FLAGS
2131 : #define TARGET_DEFAULT_TARGET_FLAGS \
2132 : (TARGET_DEFAULT \
2133 : | TARGET_SUBTARGET_DEFAULT \
2134 : | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2135 :
2136 : #undef TARGET_HANDLE_OPTION
2137 : #define TARGET_HANDLE_OPTION ix86_handle_option
2138 :
2139 : #undef TARGET_OPTION_OPTIMIZATION_TABLE
2140 : #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2141 : #undef TARGET_OPTION_INIT_STRUCT
2142 : #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2143 :
2144 : #undef TARGET_SUPPORTS_SPLIT_STACK
2145 : #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2146 :
2147 : /* This table must be in sync with enum processor_type in i386.h. */
2148 : const char *const processor_names[] =
2149 : {
2150 : "generic",
2151 : "i386",
2152 : "i486",
2153 : "pentium",
2154 : "lakemont",
2155 : "pentiumpro",
2156 : "pentium4",
2157 : "nocona",
2158 : "core2",
2159 : "nehalem",
2160 : "sandybridge",
2161 : "haswell",
2162 : "bonnell",
2163 : "silvermont",
2164 : "goldmont",
2165 : "goldmont-plus",
2166 : "tremont",
2167 : "sierraforest",
2168 : "grandridge",
2169 : "clearwaterforest",
2170 : "skylake",
2171 : "skylake-avx512",
2172 : "cannonlake",
2173 : "icelake-client",
2174 : "icelake-server",
2175 : "cascadelake",
2176 : "tigerlake",
2177 : "cooperlake",
2178 : "sapphirerapids",
2179 : "alderlake",
2180 : "rocketlake",
2181 : "graniterapids",
2182 : "graniterapids-d",
2183 : "arrowlake",
2184 : "arrowlake-s",
2185 : "pantherlake",
2186 : "diamondrapids",
2187 : "novalake",
2188 : "intel",
2189 : "lujiazui",
2190 : "yongfeng",
2191 : "shijidadao",
2192 : "geode",
2193 : "k6",
2194 : "athlon",
2195 : "k8",
2196 : "amdfam10",
2197 : "bdver1",
2198 : "bdver2",
2199 : "bdver3",
2200 : "bdver4",
2201 : "btver1",
2202 : "btver2",
2203 : "znver1",
2204 : "znver2",
2205 : "znver3",
2206 : "znver4",
2207 : "znver5",
2208 : "znver6",
2209 : "c86-4g-m4",
2210 : "c86-4g-m6",
2211 : "c86-4g-m7"
2212 : };
2213 :
2214 : /* Guarantee that the array is aligned with enum processor_type. */
2215 : STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2216 :
2217 : const pta processor_alias_table[] =
2218 : {
2219 : {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2220 : {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2221 : {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2222 : {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2223 : {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2224 : 0, P_NONE},
2225 : {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2226 : {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2227 : {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2228 : 0, P_NONE},
2229 : {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2230 : {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2231 : 0, P_NONE},
2232 : {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2233 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2234 : {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2235 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2236 : {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2237 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2238 : {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2239 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2240 : {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2241 : {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2242 : {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2243 : 0, P_NONE},
2244 : {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2245 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2246 : {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2247 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2248 : {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2249 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2250 : {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2251 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2252 : {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2253 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2254 : {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2255 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2256 : {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2257 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2258 : | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2259 : {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2260 : M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2261 : {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2262 : M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2263 : {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2264 : M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2265 : {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2266 : M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2267 : {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2268 : PTA_SANDYBRIDGE,
2269 : M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2270 : {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2271 : PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2272 : {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2273 : PTA_IVYBRIDGE,
2274 : M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2275 : {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2276 : PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2277 : {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2278 : M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2279 : {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2280 : 0, P_PROC_DYNAMIC},
2281 : {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2282 : M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2283 : {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2284 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2285 : {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2286 : PTA_SKYLAKE_AVX512,
2287 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2288 : {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2289 : M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2290 : {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2291 : PTA_ICELAKE_CLIENT,
2292 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2293 : {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2294 : PTA_ROCKETLAKE,
2295 : M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2296 : {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2297 : PTA_ICELAKE_SERVER,
2298 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2299 : {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2300 : PTA_CASCADELAKE,
2301 : M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2302 : {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2303 : M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2304 : {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2305 : M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2306 : {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2307 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2308 : {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2309 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2310 : {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2311 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2312 : {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2313 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2314 : {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2315 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2316 : {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2317 : M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1},
2318 : {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2319 : PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2320 : P_PROC_AVX10_1},
2321 : {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2322 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2323 : {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2324 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2325 : {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2326 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2327 : {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2328 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2329 : {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS,
2330 : M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_1},
2331 : {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2332 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2333 : {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
2334 : M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_1},
2335 : {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2336 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2337 : {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2338 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2339 : {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2340 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2341 : {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2342 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2343 : {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2344 : M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2345 : {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2346 : M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2347 : {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2348 : M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2349 : {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2350 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2351 : {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2352 : M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2353 : {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2354 : M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2355 : {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2356 : PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2357 : {"intel", PROCESSOR_INTEL, CPU_HASWELL, PTA_HASWELL,
2358 : M_VENDOR (VENDOR_INTEL), P_NONE},
2359 : {"geode", PROCESSOR_GEODE, CPU_GEODE,
2360 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2361 : {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2362 : {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2363 : {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2364 : {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2365 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2366 : {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2367 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2368 : {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2369 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2370 : {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2371 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2372 : {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2373 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2374 : {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2375 : {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2376 : 0, P_NONE},
2377 : {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2378 : 0, P_NONE},
2379 : {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2380 : 0, P_NONE},
2381 : {"eden-x2", PROCESSOR_K8, CPU_K8,
2382 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2383 : 0, P_NONE},
2384 : {"nano", PROCESSOR_K8, CPU_K8,
2385 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2386 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2387 : {"nano-1000", PROCESSOR_K8, CPU_K8,
2388 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2389 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2390 : {"nano-2000", PROCESSOR_K8, CPU_K8,
2391 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2392 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2393 : {"nano-3000", PROCESSOR_K8, CPU_K8,
2394 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2395 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2396 : {"nano-x2", PROCESSOR_K8, CPU_K8,
2397 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2398 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2399 : {"eden-x4", PROCESSOR_K8, CPU_K8,
2400 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2401 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2402 : {"nano-x4", PROCESSOR_K8, CPU_K8,
2403 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2404 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2405 : {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2406 : PTA_LUJIAZUI,
2407 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2408 : {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2409 : PTA_YONGFENG,
2410 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2411 : {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2412 : PTA_YONGFENG,
2413 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2414 : {"k8", PROCESSOR_K8, CPU_K8,
2415 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2416 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2417 : {"k8-sse3", PROCESSOR_K8, CPU_K8,
2418 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2419 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2420 : {"opteron", PROCESSOR_K8, CPU_K8,
2421 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2422 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2423 : {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2424 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2425 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2426 : {"athlon64", PROCESSOR_K8, CPU_K8,
2427 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2428 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2429 : {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2430 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2431 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2432 : {"athlon-fx", PROCESSOR_K8, CPU_K8,
2433 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2434 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2435 : {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2436 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2437 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2438 : 0, P_PROC_DYNAMIC},
2439 : {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2440 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2441 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2442 : M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2443 : {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2444 : PTA_BDVER1,
2445 : M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2446 : {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2447 : PTA_BDVER2,
2448 : M_CPU_SUBTYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2449 : {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2450 : PTA_BDVER3,
2451 : M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2452 : {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2453 : PTA_BDVER4,
2454 : M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2455 : {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2456 : PTA_ZNVER1,
2457 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2458 : {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2459 : PTA_ZNVER2,
2460 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2461 : {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2462 : PTA_ZNVER3,
2463 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2464 : {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2465 : PTA_ZNVER4,
2466 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2467 : {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2468 : PTA_ZNVER5,
2469 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2470 : {"znver6", PROCESSOR_ZNVER6, CPU_ZNVER5,
2471 : PTA_ZNVER6,
2472 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER6), P_PROC_AVX512F},
2473 : {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2474 : PTA_BTVER1,
2475 : M_CPU_TYPE (AMD_BTVER1), P_PROC_SSE4_A},
2476 : {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2477 : PTA_BTVER2,
2478 : M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2479 : {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
2480 : PTA_C86_4G_M4,
2481 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
2482 : {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
2483 : PTA_C86_4G_M6,
2484 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
2485 : {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
2486 : PTA_C86_4G_M7,
2487 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
2488 :
2489 : {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2490 : PTA_64BIT
2491 : | PTA_HLE /* flags are only used for -march switch. */,
2492 : 0, P_NONE},
2493 :
2494 : {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2495 : M_VENDOR (VENDOR_AMD), P_NONE},
2496 : {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2497 : M_CPU_TYPE (AMDFAM10H), P_NONE},
2498 : {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2499 : M_CPU_TYPE (AMDFAM15H), P_NONE},
2500 : {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2501 : M_CPU_TYPE (AMDFAM17H), P_NONE},
2502 : {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2503 : M_CPU_TYPE (AMDFAM19H), P_NONE},
2504 : {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2505 : M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
2506 : {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2507 : M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
2508 : {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2509 : M_VENDOR (VENDOR_HYGON), P_NONE},
2510 : {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2511 : M_CPU_TYPE (HYGONFAM18H), P_NONE},
2512 : };
2513 :
2514 : /* NB: processor_alias_table stops at the "generic" entry. */
2515 : unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
2516 : unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2517 :
2518 : /* Provide valid option values for -march and -mtune options. */
2519 :
2520 : vec<const char *>
2521 156777 : ix86_get_valid_option_values (int option_code,
2522 : const char *prefix ATTRIBUTE_UNUSED)
2523 : {
2524 156777 : vec<const char *> v;
2525 156777 : v.create (0);
2526 156777 : opt_code opt = (opt_code) option_code;
2527 :
2528 156777 : switch (opt)
2529 : {
2530 : case OPT_march_:
2531 71520 : for (unsigned i = 0; i < pta_size; i++)
2532 : {
2533 70924 : const char *name = processor_alias_table[i].name;
2534 70924 : gcc_checking_assert (name != NULL);
2535 70924 : v.safe_push (name);
2536 : }
2537 : #ifdef HAVE_LOCAL_CPU_DETECT
2538 : /* Add also "native" as possible value. */
2539 596 : v.safe_push ("native");
2540 : #endif
2541 :
2542 596 : break;
2543 : case OPT_mtune_:
2544 37548 : for (unsigned i = 0; i < PROCESSOR_max; i++)
2545 : {
2546 36952 : const char *name = processor_names[i];
2547 36952 : gcc_checking_assert (name != NULL);
2548 36952 : v.safe_push (name);
2549 : }
2550 : break;
2551 : default:
2552 : break;
2553 : }
2554 :
2555 156777 : return v;
2556 : }
2557 :
2558 : #undef TARGET_GET_VALID_OPTION_VALUES
2559 : #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2560 :
2561 : struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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