Line data Source code
1 : /* IA-32 common hooks.
2 : Copyright (C) 1988-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify
7 : it under the terms of the GNU General Public License as published by
8 : the Free Software Foundation; either version 3, or (at your option)
9 : any later version.
10 :
11 : GCC is distributed in the hope that it will be useful,
12 : but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : GNU General Public License for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "diagnostic-core.h"
24 : #include "tm.h"
25 : #include "memmodel.h"
26 : #include "tm_p.h"
27 : #include "common/common-target.h"
28 : #include "common/common-target-def.h"
29 : #include "opts.h"
30 : #include "flags.h"
31 :
32 : /* Define a set of ISAs which are available when a given ISA is
33 : enabled. MMX and SSE ISAs are handled separately. */
34 :
35 : #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 : #define OPTION_MASK_ISA_3DNOW_SET \
37 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 : #define OPTION_MASK_ISA_3DNOW_A_SET \
39 : (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 :
41 : #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 : #define OPTION_MASK_ISA_SSE2_SET \
43 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 : #define OPTION_MASK_ISA_SSE3_SET \
45 : (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 : #define OPTION_MASK_ISA_SSSE3_SET \
47 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 : #define OPTION_MASK_ISA_SSE4_1_SET \
49 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 : #define OPTION_MASK_ISA_SSE4_2_SET \
51 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 : #define OPTION_MASK_ISA_AVX_SET \
53 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 : | OPTION_MASK_ISA_XSAVE_SET)
55 : #define OPTION_MASK_ISA_FMA_SET \
56 : (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 : #define OPTION_MASK_ISA_AVX2_SET \
58 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 : #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 : #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 : #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 : (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 : #define OPTION_MASK_ISA_AVX512F_SET \
64 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 : #define OPTION_MASK_ISA_AVX512CD_SET \
66 : (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 : #define OPTION_MASK_ISA_AVX512DQ_SET \
68 : (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
69 : #define OPTION_MASK_ISA_AVX512BW_SET \
70 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
71 : #define OPTION_MASK_ISA_AVX512VL_SET \
72 : (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
73 : #define OPTION_MASK_ISA_AVX512IFMA_SET \
74 : (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
75 : #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA
76 : #define OPTION_MASK_ISA_AVX512VBMI_SET \
77 : (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
78 : #define OPTION_MASK_ISA_AVX512VBMI2_SET \
79 : (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET)
80 : #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
81 : #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
82 : #define OPTION_MASK_ISA_AVX512VNNI_SET \
83 : (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
84 : #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
85 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
86 : (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
87 : #define OPTION_MASK_ISA_AVX512BITALG_SET \
88 : (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET)
89 : #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
90 : #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
91 : #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
92 : #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
93 : #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
94 : #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
95 : #define OPTION_MASK_ISA_XSAVES_SET \
96 : (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
97 : #define OPTION_MASK_ISA_XSAVEC_SET \
98 : (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
99 : #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
100 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
101 : #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
102 : #define OPTION_MASK_ISA2_AMX_INT8_SET \
103 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8)
104 : #define OPTION_MASK_ISA2_AMX_BF16_SET \
105 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16)
106 : #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8
107 : #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT
108 : #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD
109 : #define OPTION_MASK_ISA2_AMX_FP16_SET \
110 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16)
111 : #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI
112 : #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
113 : #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
114 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX)
115 : #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
116 : #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
117 : #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
118 : #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4
119 : #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
120 : #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
121 : #define OPTION_MASK_ISA_AVX10_1_SET \
122 : (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
123 : | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
124 : | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
125 : | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
126 : | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
127 : | OPTION_MASK_ISA_AVX512BITALG_SET)
128 : #define OPTION_MASK_ISA2_AVX10_1_SET \
129 : (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
130 : | OPTION_MASK_ISA2_AVX10_1)
131 : #define OPTION_MASK_ISA2_AVX10_2_SET \
132 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
133 : #define OPTION_MASK_ISA2_AMX_AVX512_SET \
134 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_AVX512)
135 : #define OPTION_MASK_ISA2_AMX_FP8_SET \
136 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
137 : #define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
138 : #define OPTION_MASK_ISA2_AMX_MOVRS_SET \
139 : (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_MOVRS)
140 : #define OPTION_MASK_ISA2_AVX512BMM_SET OPTION_MASK_ISA2_AVX512BMM
141 : #define OPTION_MASK_ISA2_AVX10V2AUX_SET \
142 : (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V2AUX)
143 : #define OPTION_MASK_ISA2_ACEV1_SET \
144 : (OPTION_MASK_ISA2_AVX10V2AUX_SET | OPTION_MASK_ISA2_ACEV1)
145 :
146 : /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
147 : as -msse4.2. */
148 : #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
149 :
150 : #define OPTION_MASK_ISA_SSE4A_SET \
151 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
152 : #define OPTION_MASK_ISA_FMA4_SET \
153 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
154 : | OPTION_MASK_ISA_AVX_SET)
155 : #define OPTION_MASK_ISA_XOP_SET \
156 : (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
157 : #define OPTION_MASK_ISA_LWP_SET \
158 : OPTION_MASK_ISA_LWP
159 :
160 : /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
161 : #define OPTION_MASK_ISA_AES_SET \
162 : (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
163 : #define OPTION_MASK_ISA_SHA_SET \
164 : (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
165 : #define OPTION_MASK_ISA_PCLMUL_SET \
166 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
167 :
168 : #define OPTION_MASK_ISA_ABM_SET \
169 : (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET)
170 :
171 : #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
172 : #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
173 : #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
174 : #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
175 : #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
176 : #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
177 : #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
178 : #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
179 : #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
180 : #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
181 : #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
182 : #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
183 :
184 : #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
185 : #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
186 : #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
187 : #define OPTION_MASK_ISA_F16C_SET \
188 : (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
189 : #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
190 : #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
191 : #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
192 : #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
193 : #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
194 : #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
195 : #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
196 : #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
197 : #define OPTION_MASK_ISA_VPCLMULQDQ_SET \
198 : (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \
199 : | OPTION_MASK_ISA_AVX_SET)
200 : #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
201 : #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
202 : #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
203 : #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
204 : #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
205 : #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
206 : #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
207 : #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
208 : #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
209 : #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
210 : #define OPTION_MASK_ISA2_WIDEKL_SET \
211 : (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
212 :
213 : /* Define a set of ISAs which aren't available when a given ISA is
214 : disabled. MMX and SSE ISAs are handled separately. */
215 :
216 : #define OPTION_MASK_ISA_MMX_UNSET \
217 : (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
218 : #define OPTION_MASK_ISA_3DNOW_UNSET \
219 : (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
220 : #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
221 :
222 : #define OPTION_MASK_ISA_SSE_UNSET \
223 : (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
224 : #define OPTION_MASK_ISA_SSE2_UNSET \
225 : (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET \
226 : | OPTION_MASK_ISA_AES_UNSET | OPTION_MASK_ISA_SHA_UNSET \
227 : | OPTION_MASK_ISA_PCLMUL_UNSET)
228 : #define OPTION_MASK_ISA_SSE3_UNSET \
229 : (OPTION_MASK_ISA_SSE3 \
230 : | OPTION_MASK_ISA_SSSE3_UNSET \
231 : | OPTION_MASK_ISA_SSE4A_UNSET )
232 : #define OPTION_MASK_ISA_SSSE3_UNSET \
233 : (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
234 : #define OPTION_MASK_ISA_SSE4_1_UNSET \
235 : (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
236 : #define OPTION_MASK_ISA_SSE4_2_UNSET \
237 : (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
238 : #define OPTION_MASK_ISA_AVX_UNSET \
239 : (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
240 : | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
241 : | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
242 : #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
243 : #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
244 : #define OPTION_MASK_ISA_XSAVE_UNSET \
245 : (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
246 : | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
247 : | OPTION_MASK_ISA_AVX_UNSET)
248 : #define OPTION_MASK_ISA2_XSAVE_UNSET \
249 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
250 : #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
251 : #define OPTION_MASK_ISA_AVX2_UNSET \
252 : (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
253 : #define OPTION_MASK_ISA2_AVX2_UNSET \
254 : (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
255 : | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
256 : | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
257 : #define OPTION_MASK_ISA_AVX512F_UNSET \
258 : (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
259 : | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
260 : | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
261 : | OPTION_MASK_ISA_AVX512VNNI_UNSET \
262 : | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET)
263 : #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
264 : #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
265 : #define OPTION_MASK_ISA_AVX512BW_UNSET \
266 : (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \
267 : | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET)
268 : #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
269 : #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
270 : #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA
271 : #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
272 : #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
273 : #define OPTION_MASK_ISA2_AVX512FP16_UNSET \
274 : (OPTION_MASK_ISA2_AVX512FP16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
275 : #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
276 : #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
277 : #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
278 : #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
279 : #define OPTION_MASK_ISA2_AVX512BF16_UNSET \
280 : (OPTION_MASK_ISA2_AVX512BF16 | OPTION_MASK_ISA2_AVX10_1_UNSET)
281 : #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
282 : #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
283 : #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
284 : #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
285 : #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
286 : #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
287 : #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
288 : #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
289 : #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
290 : #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
291 : #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
292 : #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
293 : #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
294 : #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
295 : #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
296 : #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
297 : #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
298 : #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
299 : #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
300 : #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
301 : #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
302 : #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
303 : #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
304 : #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
305 : #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
306 : #define OPTION_MASK_ISA2_AMX_TILE_UNSET \
307 : (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \
308 : | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \
309 : | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET | OPTION_MASK_ISA2_AMX_AVX512_UNSET \
310 : | OPTION_MASK_ISA2_AMX_FP8_UNSET | OPTION_MASK_ISA2_AMX_MOVRS_UNSET)
311 : #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
312 : #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
313 : #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
314 : #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
315 : #define OPTION_MASK_ISA2_KL_UNSET \
316 : (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
317 : #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
318 : #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8
319 : #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT
320 : #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD
321 : #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16
322 : #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
323 : #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
324 : #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
325 : #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
326 : #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
327 : #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
328 : #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4
329 : #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
330 : #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
331 : #define OPTION_MASK_ISA2_AVX10_1_UNSET \
332 : (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
333 : | OPTION_MASK_ISA2_AVX10V2AUX_UNSET)
334 : #define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
335 : #define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
336 : #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
337 : #define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
338 : #define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
339 : #define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
340 : #define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \
341 : (OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET)
342 : #define OPTION_MASK_ISA2_ACEV1_UNSET OPTION_MASK_ISA2_ACEV1
343 :
344 : /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
345 : as -mno-sse4.1. */
346 : #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
347 :
348 : #define OPTION_MASK_ISA_SSE4A_UNSET \
349 : (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
350 :
351 : #define OPTION_MASK_ISA_FMA4_UNSET \
352 : (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
353 : #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
354 : #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
355 :
356 : #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
357 : #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
358 : #define OPTION_MASK_ISA_PCLMUL_UNSET \
359 : (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET)
360 : #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
361 : #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
362 : #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
363 : #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
364 : #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
365 : #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
366 : #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
367 : #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
368 : #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
369 : #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
370 : #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
371 : #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
372 : #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
373 :
374 : #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
375 : #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
376 : #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
377 : #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
378 :
379 : #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
380 : (OPTION_MASK_ISA_MMX_UNSET \
381 : | OPTION_MASK_ISA_SSE_UNSET)
382 :
383 : #define OPTION_MASK_ISA2_AVX512F_UNSET \
384 : (OPTION_MASK_ISA2_AVX512BW_UNSET \
385 : | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
386 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
387 : | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
388 : #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
389 : OPTION_MASK_ISA2_SSE_UNSET
390 : #define OPTION_MASK_ISA2_AVX_UNSET \
391 : (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
392 : | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \
393 : | OPTION_MASK_ISA2_SM4_UNSET)
394 : #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
395 : #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
396 : #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
397 : #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
398 : #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
399 : #define OPTION_MASK_ISA2_SSE2_UNSET \
400 : (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
401 : #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
402 :
403 : #define OPTION_MASK_ISA2_AVX512BW_UNSET \
404 : (OPTION_MASK_ISA2_AVX512BF16_UNSET \
405 : | OPTION_MASK_ISA2_AVX512FP16_UNSET \
406 : | OPTION_MASK_ISA2_AVX10_1_UNSET \
407 : | OPTION_MASK_ISA2_AVX512BMM_UNSET)
408 : #define OPTION_MASK_ISA2_AVX512CD_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
409 : #define OPTION_MASK_ISA2_AVX512DQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
410 : #define OPTION_MASK_ISA2_AVX512VL_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
411 : #define OPTION_MASK_ISA2_AVX512IFMA_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
412 : #define OPTION_MASK_ISA2_AVX512VNNI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
413 : #define OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
414 : #define OPTION_MASK_ISA2_AVX512VBMI_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
415 : #define OPTION_MASK_ISA2_AVX512VBMI2_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
416 : #define OPTION_MASK_ISA2_AVX512BITALG_UNSET OPTION_MASK_ISA2_AVX10_1_UNSET
417 :
418 : /* Set 1 << value as value of -malign-FLAG option. */
419 :
420 : static void
421 1 : set_malign_value (const char **flag, unsigned value)
422 : {
423 1 : char *r = XNEWVEC (char, 6);
424 1 : sprintf (r, "%d", 1 << value);
425 1 : *flag = r;
426 1 : }
427 :
428 : /* Implement TARGET_HANDLE_OPTION. */
429 :
430 : bool
431 70137070 : ix86_handle_option (struct gcc_options *opts,
432 : struct gcc_options *opts_set ATTRIBUTE_UNUSED,
433 : const struct cl_decoded_option *decoded,
434 : location_t loc)
435 : {
436 70137070 : size_t code = decoded->opt_index;
437 70137070 : int value = decoded->value;
438 :
439 70137070 : switch (code)
440 : {
441 1983961 : case OPT_mgeneral_regs_only:
442 1983961 : if (value)
443 : {
444 1983961 : HOST_WIDE_INT general_regs_only_flags = 0;
445 1983961 : HOST_WIDE_INT general_regs_only_flags2 = 0;
446 :
447 : /* NB: Enable the GPR only instructions which are enabled
448 : implicitly by SSE ISAs unless they have been disabled
449 : explicitly. */
450 1983961 : if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
451 : {
452 6506 : if (!TARGET_EXPLICIT_CRC32_P (opts))
453 4595 : general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
454 6506 : if (!TARGET_EXPLICIT_POPCNT_P (opts))
455 4577 : general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
456 : }
457 1983961 : if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
458 : {
459 6916 : if (!TARGET_EXPLICIT_MWAIT_P (opts))
460 1983961 : general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
461 : }
462 :
463 : /* Disable MMX, SSE and x87 instructions if only
464 : general registers are allowed. */
465 1983961 : opts->x_ix86_isa_flags
466 1983961 : &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
467 1983961 : opts->x_ix86_isa_flags2
468 1983961 : &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
469 1983961 : opts->x_ix86_isa_flags |= general_regs_only_flags;
470 1983961 : opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
471 1983961 : opts->x_ix86_isa_flags_explicit
472 1983961 : |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
473 : | general_regs_only_flags);
474 1983961 : opts->x_ix86_isa_flags2_explicit
475 1983961 : |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
476 : | general_regs_only_flags2);
477 :
478 1983961 : opts->x_target_flags &= ~MASK_80387;
479 : }
480 : else
481 0 : gcc_unreachable ();
482 1983961 : return true;
483 :
484 3468 : case OPT_mmmx:
485 3468 : if (value)
486 : {
487 1648 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
488 1648 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
489 : }
490 : else
491 : {
492 1820 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
493 1820 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
494 : }
495 : return true;
496 :
497 85435 : case OPT_m3dnow:
498 85435 : if (value)
499 : {
500 85419 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
501 85419 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
502 : }
503 : else
504 : {
505 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
506 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
507 : }
508 : return true;
509 :
510 6073 : case OPT_m3dnowa:
511 6073 : if (value)
512 : {
513 6072 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
514 6072 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
515 : }
516 : else
517 : {
518 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
519 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
520 : }
521 : return true;
522 :
523 34134 : case OPT_msse:
524 34134 : if (value)
525 : {
526 34026 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
527 34026 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
528 : }
529 : else
530 : {
531 108 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
532 108 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
533 108 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
534 108 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
535 : }
536 : return true;
537 :
538 87688 : case OPT_msse2:
539 87688 : if (value)
540 : {
541 87565 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
542 87565 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
543 : }
544 : else
545 : {
546 123 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
547 123 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
548 123 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
549 123 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
550 : }
551 : return true;
552 :
553 24958 : case OPT_msse3:
554 24958 : if (value)
555 : {
556 24873 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
557 24873 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
558 : }
559 : else
560 : {
561 85 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
562 85 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
563 85 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
564 85 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
565 : }
566 : return true;
567 :
568 46280 : case OPT_mssse3:
569 46280 : if (value)
570 : {
571 46269 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
572 46269 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
573 : }
574 : else
575 : {
576 11 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
577 11 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
578 11 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
579 11 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
580 : }
581 : return true;
582 :
583 79286 : case OPT_msse4_1:
584 79286 : if (value)
585 : {
586 79254 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
587 79254 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
588 : }
589 : else
590 : {
591 32 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
592 32 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
593 32 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
594 32 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
595 : }
596 : return true;
597 :
598 29942 : case OPT_msse4_2:
599 29942 : if (value)
600 : {
601 29927 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
602 29927 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
603 : }
604 : else
605 : {
606 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
607 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
608 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
609 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
610 : }
611 : return true;
612 :
613 301219 : case OPT_mavx:
614 301219 : if (value)
615 : {
616 299565 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
617 299565 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
618 : }
619 : else
620 : {
621 1654 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
622 1654 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
623 1654 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
624 1654 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
625 : }
626 : return true;
627 :
628 615494 : case OPT_mavx2:
629 615494 : if (value)
630 : {
631 615413 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
632 615413 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
633 : }
634 : else
635 : {
636 81 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
637 81 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
638 81 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
639 81 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
640 : }
641 : return true;
642 :
643 5031040 : case OPT_mavx512f:
644 5031040 : if (value)
645 : {
646 5030889 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
647 5030889 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
648 : }
649 : else
650 : {
651 151 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
652 151 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
653 151 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
654 151 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
655 : }
656 : return true;
657 :
658 416372 : case OPT_mavx512cd:
659 416372 : if (value)
660 : {
661 416346 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
662 416346 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
663 : }
664 : else
665 : {
666 26 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
667 26 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
668 26 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512CD_UNSET;
669 26 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512CD_UNSET;
670 : }
671 : return true;
672 :
673 63319 : case OPT_mrdpid:
674 63319 : if (value)
675 : {
676 63318 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
677 63318 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
678 : }
679 : else
680 : {
681 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
682 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
683 : }
684 : return true;
685 :
686 366199 : case OPT_mgfni:
687 366199 : if (value)
688 : {
689 366180 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
690 366180 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
691 : }
692 : else
693 : {
694 19 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
695 19 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
696 : }
697 : return true;
698 :
699 125370 : case OPT_mshstk:
700 125370 : if (value)
701 : {
702 125356 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
703 125356 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
704 : }
705 : else
706 : {
707 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
708 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
709 : }
710 : return true;
711 :
712 90720 : case OPT_mvaes:
713 90720 : if (value)
714 : {
715 90706 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
716 90706 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
717 90706 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
718 90706 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
719 : }
720 : else
721 : {
722 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
723 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
724 : }
725 : return true;
726 :
727 75735 : case OPT_mvpclmulqdq:
728 75735 : if (value)
729 : {
730 75721 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
731 75721 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
732 : }
733 : else
734 : {
735 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
736 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
737 : }
738 : return true;
739 :
740 25500 : case OPT_mmovdiri:
741 25500 : if (value)
742 : {
743 25487 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
744 25487 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
745 : }
746 : else
747 : {
748 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
749 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
750 : }
751 : return true;
752 :
753 15456 : case OPT_mmovdir64b:
754 15456 : if (value)
755 : {
756 15443 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
757 15443 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
758 : }
759 : else
760 : {
761 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
762 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
763 : }
764 : return true;
765 :
766 15452 : case OPT_mcldemote:
767 15452 : if (value)
768 : {
769 15439 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
770 15439 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
771 : }
772 : else
773 : {
774 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
775 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
776 : }
777 : return true;
778 :
779 35743 : case OPT_mwaitpkg:
780 35743 : if (value)
781 : {
782 35730 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
783 35730 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
784 : }
785 : else
786 : {
787 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
788 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
789 : }
790 : return true;
791 :
792 72754 : case OPT_menqcmd:
793 72754 : if (value)
794 : {
795 72740 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
796 72740 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
797 : }
798 : else
799 : {
800 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
801 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
802 : }
803 : return true;
804 :
805 147994 : case OPT_mkl:
806 147994 : if (value)
807 : {
808 147980 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
809 147980 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
810 :
811 : /* The Keylocker instructions need XMM registers from SSE2. */
812 147980 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
813 147980 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
814 : }
815 : else
816 : {
817 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
818 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
819 : }
820 : return true;
821 :
822 156710 : case OPT_mwidekl:
823 156710 : if (value)
824 : {
825 156696 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
826 156696 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
827 :
828 : /* The Widekl instructions need XMM registers from SSE2. */
829 156696 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
830 156696 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
831 : }
832 : else
833 : {
834 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
835 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
836 : }
837 : return true;
838 :
839 89624 : case OPT_mserialize:
840 89624 : if (value)
841 : {
842 89609 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
843 89609 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
844 : }
845 : else
846 : {
847 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
848 15 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
849 : }
850 : return true;
851 :
852 46680 : case OPT_muintr:
853 46680 : if (value)
854 : {
855 46666 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
856 46666 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
857 : }
858 : else
859 : {
860 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
861 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
862 : }
863 : return true;
864 :
865 16991 : case OPT_mhreset:
866 16991 : if (value)
867 : {
868 16977 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
869 16977 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
870 : }
871 : else
872 : {
873 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
874 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
875 : }
876 : return true;
877 :
878 1441106 : case OPT_mavx512vbmi2:
879 1441106 : if (value)
880 : {
881 1441093 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
882 1441093 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
883 : }
884 : else
885 : {
886 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
887 13 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
888 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
889 13 : opts->x_ix86_isa_flags2_explicit
890 13 : |= OPTION_MASK_ISA2_AVX512VBMI2_UNSET;
891 : }
892 : return true;
893 :
894 7966502 : case OPT_mavx512fp16:
895 7966502 : if (value)
896 : {
897 7966482 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
898 7966482 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
899 7966482 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
900 7966482 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
901 : }
902 : else
903 : {
904 20 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
905 20 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
906 : }
907 : return true;
908 :
909 282837 : case OPT_mavx512vnni:
910 282837 : if (value)
911 : {
912 282823 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
913 282823 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
914 : }
915 : else
916 : {
917 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
918 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
919 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VNNI_UNSET;
920 14 : opts->x_ix86_isa_flags2_explicit
921 14 : |= OPTION_MASK_ISA2_AVX512VNNI_UNSET;
922 : }
923 : return true;
924 :
925 185423 : case OPT_mavx512vpopcntdq:
926 185423 : if (value)
927 : {
928 185397 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
929 185397 : opts->x_ix86_isa_flags_explicit
930 185397 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
931 : }
932 : else
933 : {
934 26 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
935 26 : opts->x_ix86_isa_flags_explicit
936 26 : |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
937 26 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
938 26 : opts->x_ix86_isa_flags2_explicit
939 26 : |= OPTION_MASK_ISA2_AVX512VPOPCNTDQ_UNSET;
940 : }
941 : return true;
942 :
943 243702 : case OPT_mavx512bitalg:
944 243702 : if (value)
945 : {
946 243689 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
947 243689 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
948 : }
949 : else
950 : {
951 13 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
952 13 : opts->x_ix86_isa_flags_explicit
953 13 : |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
954 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BITALG_UNSET;
955 13 : opts->x_ix86_isa_flags2_explicit
956 13 : |= OPTION_MASK_ISA2_AVX512BITALG_UNSET;
957 : }
958 : return true;
959 :
960 419455 : case OPT_mavx512bf16:
961 419455 : if (value)
962 : {
963 419430 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
964 419430 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
965 419430 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
966 419430 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
967 : }
968 : else
969 : {
970 25 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
971 25 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
972 : }
973 : return true;
974 :
975 141228 : case OPT_mavx512bmm:
976 141228 : if (value)
977 : {
978 141215 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BMM_SET;
979 141215 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_SET;
980 141215 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
981 141215 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
982 : }
983 : else
984 : {
985 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BMM_UNSET;
986 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BMM_UNSET;
987 : }
988 : return true;
989 :
990 157879 : case OPT_mavxvnni:
991 157879 : if (value)
992 : {
993 157863 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
994 157863 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
995 157863 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
996 157863 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
997 : }
998 : else
999 : {
1000 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
1001 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
1002 : }
1003 : return true;
1004 :
1005 112684 : case OPT_msgx:
1006 112684 : if (value)
1007 : {
1008 112670 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
1009 112670 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
1010 : }
1011 : else
1012 : {
1013 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
1014 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
1015 : }
1016 : return true;
1017 :
1018 72389 : case OPT_mpconfig:
1019 72389 : if (value)
1020 : {
1021 72376 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
1022 72376 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
1023 : }
1024 : else
1025 : {
1026 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
1027 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
1028 : }
1029 : return true;
1030 :
1031 62624 : case OPT_mwbnoinvd:
1032 62624 : if (value)
1033 : {
1034 62624 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
1035 62624 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
1036 : }
1037 : else
1038 : {
1039 0 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
1040 0 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
1041 : }
1042 : return true;
1043 :
1044 3614110 : case OPT_mavx512dq:
1045 3614110 : if (value)
1046 : {
1047 3614075 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1048 3614075 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1049 : }
1050 : else
1051 : {
1052 35 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
1053 35 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1054 35 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512DQ_UNSET;
1055 35 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512DQ_UNSET;
1056 : }
1057 : return true;
1058 :
1059 6884236 : case OPT_mavx512bw:
1060 6884236 : if (value)
1061 : {
1062 6884175 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1063 6884175 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1064 : }
1065 : else
1066 : {
1067 61 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1068 61 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1069 61 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1070 61 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1071 : }
1072 : return true;
1073 :
1074 20555966 : case OPT_mavx512vl:
1075 20555966 : if (value)
1076 : {
1077 20555902 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1078 20555902 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1079 : }
1080 : else
1081 : {
1082 64 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1083 64 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1084 64 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VL_UNSET;
1085 64 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512VL_UNSET;
1086 : }
1087 : return true;
1088 :
1089 146508 : case OPT_mavx512ifma:
1090 146508 : if (value)
1091 : {
1092 146494 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1093 146494 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1094 : }
1095 : else
1096 : {
1097 14 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1098 14 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1099 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1100 14 : opts->x_ix86_isa_flags2_explicit
1101 14 : |= OPTION_MASK_ISA2_AVX512IFMA_UNSET;
1102 : }
1103 : return true;
1104 :
1105 302224 : case OPT_mavx512vbmi:
1106 302224 : if (value)
1107 : {
1108 302204 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1109 302204 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1110 : }
1111 : else
1112 : {
1113 20 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1114 20 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1115 20 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1116 20 : opts->x_ix86_isa_flags2_explicit
1117 20 : |= OPTION_MASK_ISA2_AVX512VBMI_UNSET;
1118 : }
1119 : return true;
1120 :
1121 143313 : case OPT_mavx512vp2intersect:
1122 143313 : if (value)
1123 : {
1124 143299 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1125 143299 : opts->x_ix86_isa_flags2_explicit |=
1126 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1127 143299 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1128 143299 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1129 : }
1130 : else
1131 : {
1132 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1133 14 : opts->x_ix86_isa_flags2_explicit |=
1134 : OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1135 : }
1136 : return true;
1137 :
1138 99742 : case OPT_mtsxldtrk:
1139 99742 : if (value)
1140 : {
1141 99728 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1142 99728 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1143 : }
1144 : else
1145 : {
1146 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1147 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1148 : }
1149 : return true;
1150 :
1151 107276 : case OPT_mamx_tile:
1152 107276 : if (value)
1153 : {
1154 107262 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1155 107262 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1156 107262 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1157 107262 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1158 : }
1159 : else
1160 : {
1161 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1162 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1163 : }
1164 : return true;
1165 :
1166 77928 : case OPT_mamx_int8:
1167 77928 : if (value)
1168 : {
1169 77914 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1170 77914 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1171 : }
1172 : else
1173 : {
1174 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1175 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1176 : }
1177 : return true;
1178 :
1179 77931 : case OPT_mamx_bf16:
1180 77931 : if (value)
1181 : {
1182 77917 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1183 77917 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1184 : }
1185 : else
1186 : {
1187 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1188 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1189 : }
1190 : return true;
1191 :
1192 118017 : case OPT_mavxifma:
1193 118017 : if (value)
1194 : {
1195 118003 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET;
1196 118003 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET;
1197 118003 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1198 118003 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1199 : }
1200 : else
1201 : {
1202 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET;
1203 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET;
1204 : }
1205 : return true;
1206 :
1207 198093 : case OPT_mavxvnniint8:
1208 198093 : if (value)
1209 : {
1210 198078 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1211 198078 : opts->x_ix86_isa_flags2_explicit |=
1212 : OPTION_MASK_ISA2_AVXVNNIINT8_SET;
1213 198078 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1214 198078 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1215 : }
1216 : else
1217 : {
1218 15 : opts->x_ix86_isa_flags2 &=
1219 : ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1220 15 : opts->x_ix86_isa_flags2_explicit |=
1221 : OPTION_MASK_ISA2_AVXVNNIINT8_UNSET;
1222 : }
1223 : return true;
1224 :
1225 218154 : case OPT_mavxneconvert:
1226 218154 : if (value)
1227 : {
1228 218129 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1229 218129 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET;
1230 218129 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1231 218129 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1232 : }
1233 : else
1234 : {
1235 25 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1236 25 : opts->x_ix86_isa_flags2_explicit
1237 25 : |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET;
1238 : }
1239 : return true;
1240 :
1241 72037 : case OPT_mcmpccxadd:
1242 72037 : if (value)
1243 : {
1244 72023 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1245 72023 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET;
1246 : }
1247 : else
1248 : {
1249 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1250 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET;
1251 : }
1252 : return true;
1253 :
1254 72733 : case OPT_mamx_fp16:
1255 72733 : if (value)
1256 : {
1257 72719 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET;
1258 72719 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET;
1259 : }
1260 : else
1261 : {
1262 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET;
1263 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET;
1264 : }
1265 : return true;
1266 :
1267 72041 : case OPT_mprefetchi:
1268 72041 : if (value)
1269 : {
1270 72027 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET;
1271 72027 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET;
1272 : }
1273 : else
1274 : {
1275 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET;
1276 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET;
1277 : }
1278 : return true;
1279 :
1280 160193 : case OPT_mraoint:
1281 160193 : if (value)
1282 : {
1283 160179 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET;
1284 160179 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET;
1285 : }
1286 : else
1287 : {
1288 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET;
1289 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET;
1290 : }
1291 : return true;
1292 :
1293 77939 : case OPT_mamx_complex:
1294 77939 : if (value)
1295 : {
1296 77925 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1297 77925 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET;
1298 : }
1299 : else
1300 : {
1301 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1302 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET;
1303 : }
1304 : return true;
1305 :
1306 198093 : case OPT_mavxvnniint16:
1307 198093 : if (value)
1308 : {
1309 198078 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1310 198078 : opts->x_ix86_isa_flags2_explicit |=
1311 : OPTION_MASK_ISA2_AVXVNNIINT16_SET;
1312 198078 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
1313 198078 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
1314 : }
1315 : else
1316 : {
1317 15 : opts->x_ix86_isa_flags2 &=
1318 : ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1319 15 : opts->x_ix86_isa_flags2_explicit |=
1320 : OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
1321 : }
1322 : return true;
1323 :
1324 107596 : case OPT_msm3:
1325 107596 : if (value)
1326 : {
1327 107582 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET;
1328 107582 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET;
1329 107582 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1330 107582 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1331 : }
1332 : else
1333 : {
1334 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET;
1335 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET;
1336 : }
1337 : return true;
1338 :
1339 108014 : case OPT_msha512:
1340 108014 : if (value)
1341 : {
1342 108000 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
1343 108000 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
1344 108000 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1345 108000 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1346 : }
1347 : else
1348 : {
1349 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
1350 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
1351 : }
1352 : return true;
1353 :
1354 143274 : case OPT_msm4:
1355 143274 : if (value)
1356 : {
1357 143260 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET;
1358 143260 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET;
1359 143260 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
1360 143260 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
1361 : }
1362 : else
1363 : {
1364 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET;
1365 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET;
1366 : }
1367 : return true;
1368 :
1369 124 : case OPT_mapxf:
1370 124 : if (value)
1371 : {
1372 88 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET;
1373 88 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET;
1374 88 : opts->x_ix86_apx_features = apx_all;
1375 : }
1376 : else
1377 : {
1378 36 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET;
1379 36 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET;
1380 36 : opts->x_ix86_apx_features = apx_none;
1381 : }
1382 : return true;
1383 :
1384 27259 : case OPT_musermsr:
1385 27259 : if (value)
1386 : {
1387 27245 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET;
1388 27245 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET;
1389 : }
1390 : else
1391 : {
1392 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET;
1393 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET;
1394 : }
1395 : return true;
1396 :
1397 31 : case OPT_mavx10_1:
1398 31 : if (value)
1399 : {
1400 17 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
1401 17 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
1402 17 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1403 17 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1404 : }
1405 : else
1406 : {
1407 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
1408 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
1409 : }
1410 : return true;
1411 :
1412 7728145 : case OPT_mavx10_2:
1413 7728145 : if (value)
1414 : {
1415 7728129 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
1416 7728129 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
1417 7728129 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1418 7728129 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1419 : }
1420 : else
1421 : {
1422 16 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_UNSET;
1423 16 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_UNSET;
1424 : }
1425 : return true;
1426 :
1427 1754549 : case OPT_mavx10v2aux:
1428 1754549 : if (value)
1429 : {
1430 1754535 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1431 1754535 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_SET;
1432 1754535 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1433 1754535 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1434 : }
1435 : else
1436 : {
1437 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1438 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10V2AUX_UNSET;
1439 : }
1440 : return true;
1441 :
1442 77943 : case OPT_mamx_avx512:
1443 77943 : if (value)
1444 : {
1445 77925 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1446 77925 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
1447 77925 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
1448 77925 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
1449 : }
1450 : else
1451 : {
1452 18 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1453 18 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_UNSET;
1454 : }
1455 : return true;
1456 :
1457 72735 : case OPT_mamx_fp8:
1458 72735 : if (value)
1459 : {
1460 72721 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP8_SET;
1461 72721 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_SET;
1462 : }
1463 : else
1464 : {
1465 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP8_UNSET;
1466 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP8_UNSET;
1467 : }
1468 : return true;
1469 :
1470 490669 : case OPT_mmovrs:
1471 490669 : if (value)
1472 : {
1473 490654 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
1474 490654 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
1475 : }
1476 : else
1477 : {
1478 15 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
1479 15 : opts->x_ix86_isa_flags2_explicit |=
1480 : OPTION_MASK_ISA2_MOVRS_UNSET;
1481 : }
1482 : return true;
1483 :
1484 77853 : case OPT_mamx_movrs:
1485 77853 : if (value)
1486 : {
1487 77839 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1488 77839 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_MOVRS_SET;
1489 : }
1490 : else
1491 : {
1492 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1493 14 : opts->x_ix86_isa_flags2_explicit |=
1494 : OPTION_MASK_ISA2_AMX_MOVRS_UNSET;
1495 : }
1496 : return true;
1497 :
1498 328390 : case OPT_macev1:
1499 328390 : if (value)
1500 : {
1501 328376 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ACEV1_SET;
1502 328376 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACEV1_SET;
1503 328376 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
1504 328376 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
1505 : }
1506 : else
1507 : {
1508 14 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ACEV1_UNSET;
1509 14 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ACEV1_UNSET;
1510 : }
1511 : return true;
1512 :
1513 360527 : case OPT_mfma:
1514 360527 : if (value)
1515 : {
1516 360515 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1517 360515 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1518 : }
1519 : else
1520 : {
1521 12 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1522 12 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1523 : }
1524 : return true;
1525 :
1526 123969 : case OPT_mrtm:
1527 123969 : if (value)
1528 : {
1529 123954 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1530 123954 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1531 : }
1532 : else
1533 : {
1534 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1535 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1536 : }
1537 : return true;
1538 :
1539 214 : case OPT_msse4:
1540 214 : if (value)
1541 : {
1542 165 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1543 165 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1544 : }
1545 : else
1546 : {
1547 49 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1548 49 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1549 49 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1550 49 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1551 : }
1552 : return true;
1553 :
1554 79457 : case OPT_msse4a:
1555 79457 : if (value)
1556 : {
1557 79455 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1558 79455 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1559 : }
1560 : else
1561 : {
1562 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1563 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1564 : }
1565 : return true;
1566 :
1567 94030 : case OPT_mfma4:
1568 94030 : if (value)
1569 : {
1570 93997 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1571 93997 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1572 : }
1573 : else
1574 : {
1575 33 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1576 33 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1577 : }
1578 : return true;
1579 :
1580 184428 : case OPT_mxop:
1581 184428 : if (value)
1582 : {
1583 184393 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1584 184393 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1585 : }
1586 : else
1587 : {
1588 35 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1589 35 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1590 : }
1591 : return true;
1592 :
1593 126879 : case OPT_mlwp:
1594 126879 : if (value)
1595 : {
1596 126864 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1597 126864 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1598 : }
1599 : else
1600 : {
1601 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1602 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1603 : }
1604 : return true;
1605 :
1606 60097 : case OPT_mabm:
1607 60097 : if (value)
1608 : {
1609 60093 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1610 60093 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1611 : }
1612 : else
1613 : {
1614 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1615 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1616 : }
1617 : return true;
1618 :
1619 319289 : case OPT_mbmi:
1620 319289 : if (value)
1621 : {
1622 319287 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1623 319287 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1624 : }
1625 : else
1626 : {
1627 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1628 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1629 : }
1630 : return true;
1631 :
1632 135921 : case OPT_mbmi2:
1633 135921 : if (value)
1634 : {
1635 135915 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1636 135915 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1637 : }
1638 : else
1639 : {
1640 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1641 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1642 : }
1643 : return true;
1644 :
1645 116473 : case OPT_mlzcnt:
1646 116473 : if (value)
1647 : {
1648 116466 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1649 116466 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1650 : }
1651 : else
1652 : {
1653 7 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1654 7 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1655 : }
1656 : return true;
1657 :
1658 268737 : case OPT_mtbm:
1659 268737 : if (value)
1660 : {
1661 268722 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1662 268722 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1663 : }
1664 : else
1665 : {
1666 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1667 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1668 : }
1669 : return true;
1670 :
1671 66265 : case OPT_mpopcnt:
1672 66265 : if (value)
1673 : {
1674 66249 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1675 66249 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1676 : }
1677 : else
1678 : {
1679 16 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1680 16 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1681 : }
1682 : return true;
1683 :
1684 19 : case OPT_msahf:
1685 19 : if (value)
1686 : {
1687 17 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1688 17 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1689 : }
1690 : else
1691 : {
1692 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1693 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1694 : }
1695 : return true;
1696 :
1697 72 : case OPT_mcx16:
1698 72 : if (value)
1699 : {
1700 67 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1701 67 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1702 : }
1703 : else
1704 : {
1705 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1706 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1707 : }
1708 : return true;
1709 :
1710 32 : case OPT_mmovbe:
1711 32 : if (value)
1712 : {
1713 27 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1714 27 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1715 : }
1716 : else
1717 : {
1718 5 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1719 5 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1720 : }
1721 : return true;
1722 :
1723 11191 : case OPT_mcrc32:
1724 11191 : if (value)
1725 : {
1726 11187 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1727 11187 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1728 : }
1729 : else
1730 : {
1731 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1732 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1733 : }
1734 : return true;
1735 :
1736 85573 : case OPT_maes:
1737 85573 : if (value)
1738 : {
1739 85571 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1740 85571 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1741 : }
1742 : else
1743 : {
1744 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1745 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1746 : }
1747 : return true;
1748 :
1749 147312 : case OPT_msha:
1750 147312 : if (value)
1751 : {
1752 147311 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1753 147311 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1754 : }
1755 : else
1756 : {
1757 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1758 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1759 : }
1760 : return true;
1761 :
1762 75566 : case OPT_mpclmul:
1763 75566 : if (value)
1764 : {
1765 75565 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1766 75565 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1767 : }
1768 : else
1769 : {
1770 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1771 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1772 : }
1773 : return true;
1774 :
1775 158977 : case OPT_mfsgsbase:
1776 158977 : if (value)
1777 : {
1778 158976 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1779 158976 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1780 : }
1781 : else
1782 : {
1783 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1784 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1785 : }
1786 : return true;
1787 :
1788 114670 : case OPT_mrdrnd:
1789 114670 : if (value)
1790 : {
1791 114669 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1792 114669 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1793 : }
1794 : else
1795 : {
1796 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1797 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1798 : }
1799 : return true;
1800 :
1801 25506 : case OPT_mptwrite:
1802 25506 : if (value)
1803 : {
1804 25493 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1805 25493 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1806 : }
1807 : else
1808 : {
1809 13 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1810 13 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1811 : }
1812 : return true;
1813 :
1814 134504 : case OPT_mf16c:
1815 134504 : if (value)
1816 : {
1817 134500 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1818 134500 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1819 : }
1820 : else
1821 : {
1822 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1823 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1824 : }
1825 : return true;
1826 :
1827 62329 : case OPT_mfxsr:
1828 62329 : if (value)
1829 : {
1830 62327 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1831 62327 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1832 : }
1833 : else
1834 : {
1835 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1836 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1837 : }
1838 : return true;
1839 :
1840 6968 : case OPT_mxsave:
1841 6968 : if (value)
1842 : {
1843 6962 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1844 6962 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1845 : }
1846 : else
1847 : {
1848 6 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1849 6 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1850 6 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1851 6 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1852 : }
1853 : return true;
1854 :
1855 87563 : case OPT_mxsaveopt:
1856 87563 : if (value)
1857 : {
1858 87562 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1859 87562 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1860 : }
1861 : else
1862 : {
1863 1 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1864 1 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1865 : }
1866 : return true;
1867 :
1868 73274 : case OPT_mxsavec:
1869 73274 : if (value)
1870 : {
1871 73272 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1872 73272 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1873 : }
1874 : else
1875 : {
1876 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1877 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1878 : }
1879 : return true;
1880 :
1881 93353 : case OPT_mxsaves:
1882 93353 : if (value)
1883 : {
1884 93351 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1885 93351 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1886 : }
1887 : else
1888 : {
1889 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1890 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1891 : }
1892 : return true;
1893 :
1894 97708 : case OPT_mrdseed:
1895 97708 : if (value)
1896 : {
1897 97706 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1898 97706 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1899 : }
1900 : else
1901 : {
1902 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1903 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1904 : }
1905 : return true;
1906 :
1907 60789 : case OPT_mprfchw:
1908 60789 : if (value)
1909 : {
1910 60787 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1911 60787 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1912 : }
1913 : else
1914 : {
1915 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1916 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1917 : }
1918 : return true;
1919 :
1920 62320 : case OPT_madx:
1921 62320 : if (value)
1922 : {
1923 62316 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1924 62316 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1925 : }
1926 : else
1927 : {
1928 4 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1929 4 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1930 : }
1931 : return true;
1932 :
1933 63281 : case OPT_mclflushopt:
1934 63281 : if (value)
1935 : {
1936 63279 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1937 63279 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1938 : }
1939 : else
1940 : {
1941 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1942 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1943 : }
1944 : return true;
1945 :
1946 63300 : case OPT_mclwb:
1947 63300 : if (value)
1948 : {
1949 63298 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1950 63298 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1951 : }
1952 : else
1953 : {
1954 2 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1955 2 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1956 : }
1957 : return true;
1958 :
1959 72803 : case OPT_mmwaitx:
1960 72803 : if (value)
1961 : {
1962 72801 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1963 72801 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1964 : }
1965 : else
1966 : {
1967 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1968 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1969 : }
1970 : return true;
1971 :
1972 25829 : case OPT_mmwait:
1973 25829 : if (value)
1974 : {
1975 25828 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1976 25828 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1977 : }
1978 : else
1979 : {
1980 1 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1981 1 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1982 : }
1983 : return true;
1984 :
1985 62663 : case OPT_mclzero:
1986 62663 : if (value)
1987 : {
1988 62661 : opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1989 62661 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1990 : }
1991 : else
1992 : {
1993 2 : opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1994 2 : opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1995 : }
1996 : return true;
1997 :
1998 73380 : case OPT_mpku:
1999 73380 : if (value)
2000 : {
2001 73365 : opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
2002 73365 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
2003 : }
2004 : else
2005 : {
2006 15 : opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
2007 15 : opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
2008 : }
2009 : return true;
2010 :
2011 :
2012 1 : case OPT_malign_loops_:
2013 1 : warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
2014 : "use %<-falign-loops%>");
2015 1 : if (value > MAX_CODE_ALIGN)
2016 0 : error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
2017 : value, MAX_CODE_ALIGN);
2018 : else
2019 1 : set_malign_value (&opts->x_str_align_loops, value);
2020 : return true;
2021 :
2022 0 : case OPT_malign_jumps_:
2023 0 : warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
2024 : "use %<-falign-jumps%>");
2025 0 : if (value > MAX_CODE_ALIGN)
2026 0 : error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
2027 : value, MAX_CODE_ALIGN);
2028 : else
2029 0 : set_malign_value (&opts->x_str_align_jumps, value);
2030 : return true;
2031 :
2032 0 : case OPT_malign_functions_:
2033 0 : warning_at (loc, 0,
2034 : "%<-malign-functions%> is obsolete, "
2035 : "use %<-falign-functions%>");
2036 0 : if (value > MAX_CODE_ALIGN)
2037 0 : error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
2038 : value, MAX_CODE_ALIGN);
2039 : else
2040 0 : set_malign_value (&opts->x_str_align_functions, value);
2041 : return true;
2042 :
2043 20 : case OPT_mbranch_cost_:
2044 20 : if (value > 5)
2045 : {
2046 0 : error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
2047 0 : opts->x_ix86_branch_cost = 5;
2048 : }
2049 : return true;
2050 :
2051 : default:
2052 : return true;
2053 : }
2054 : }
2055 :
2056 : static const struct default_options ix86_option_optimization_table[] =
2057 : {
2058 : /* Enable redundant extension instructions removal at -O2 and higher. */
2059 : { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
2060 : /* Enable function splitting at -O2 and higher. */
2061 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
2062 : /* The STC algorithm produces the smallest code at -Os, for x86. */
2063 : { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
2064 : REORDER_BLOCKS_ALGORITHM_STC },
2065 :
2066 : /* Turn on -funroll-loops with -munroll-only-small-loops to enable small
2067 : loop unrolling at -O2. */
2068 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_funroll_loops, NULL, 1 },
2069 : { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 },
2070 : /* Turns off -frename-registers and -fweb which are enabled by
2071 : funroll-loops. */
2072 : { OPT_LEVELS_ALL, OPT_frename_registers, NULL, 0 },
2073 : { OPT_LEVELS_ALL, OPT_fweb, NULL, 0 },
2074 : /* Turn off -fschedule-insns by default. It tends to make the
2075 : problem with not enough registers even worse. */
2076 : { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
2077 :
2078 : #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2079 : SUBTARGET_OPTIMIZATION_OPTIONS,
2080 : #endif
2081 : { OPT_LEVELS_NONE, 0, NULL, 0 }
2082 : };
2083 :
2084 : /* Implement TARGET_OPTION_INIT_STRUCT. */
2085 :
2086 : static void
2087 50533236 : ix86_option_init_struct (struct gcc_options *opts)
2088 : {
2089 50533236 : if (TARGET_MACHO)
2090 : /* The Darwin libraries never set errno, so we might as well
2091 : avoid calling them when that's the only reason we would. */
2092 : opts->x_flag_errno_math = 0;
2093 :
2094 50533236 : opts->x_flag_pcc_struct_return = 2;
2095 50533236 : opts->x_flag_asynchronous_unwind_tables = 2;
2096 50533236 : }
2097 :
2098 : /* On the x86 -fsplit-stack and -fstack-protector both use the same
2099 : field in the TCB, so they cannot be used together. */
2100 :
2101 : static bool
2102 6365 : ix86_supports_split_stack (bool report,
2103 : struct gcc_options *opts ATTRIBUTE_UNUSED)
2104 : {
2105 : #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
2106 6365 : if (!OPTION_GLIBC_P (opts))
2107 : #endif
2108 : {
2109 0 : if (report)
2110 0 : error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
2111 : return false;
2112 : }
2113 :
2114 : bool ret = true;
2115 :
2116 : #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
2117 : if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
2118 : {
2119 : if (report)
2120 : error ("%<-fsplit-stack%> requires "
2121 : "assembler support for CFI directives");
2122 : ret = false;
2123 : }
2124 : #endif
2125 :
2126 : return ret;
2127 : }
2128 :
2129 : /* Implement TARGET_EXCEPT_UNWIND_INFO. */
2130 :
2131 : static enum unwind_info_type
2132 9336001 : i386_except_unwind_info (struct gcc_options *opts)
2133 : {
2134 : /* Honor the --enable-sjlj-exceptions configure switch. */
2135 : #ifdef CONFIG_SJLJ_EXCEPTIONS
2136 : if (CONFIG_SJLJ_EXCEPTIONS)
2137 : return UI_SJLJ;
2138 : #endif
2139 :
2140 : /* On windows 64, prefer SEH exceptions over anything else. */
2141 9336001 : if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
2142 : return UI_SEH;
2143 :
2144 9336001 : if (DWARF2_UNWIND_INFO)
2145 9336001 : return UI_DWARF2;
2146 :
2147 : return UI_SJLJ;
2148 : }
2149 :
2150 : #undef TARGET_EXCEPT_UNWIND_INFO
2151 : #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
2152 :
2153 : #undef TARGET_DEFAULT_TARGET_FLAGS
2154 : #define TARGET_DEFAULT_TARGET_FLAGS \
2155 : (TARGET_DEFAULT \
2156 : | TARGET_SUBTARGET_DEFAULT \
2157 : | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
2158 :
2159 : #undef TARGET_HANDLE_OPTION
2160 : #define TARGET_HANDLE_OPTION ix86_handle_option
2161 :
2162 : #undef TARGET_OPTION_OPTIMIZATION_TABLE
2163 : #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
2164 : #undef TARGET_OPTION_INIT_STRUCT
2165 : #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
2166 :
2167 : #undef TARGET_SUPPORTS_SPLIT_STACK
2168 : #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
2169 :
2170 : /* This table must be in sync with enum processor_type in i386.h. */
2171 : const char *const processor_names[] =
2172 : {
2173 : "generic",
2174 : "i386",
2175 : "i486",
2176 : "pentium",
2177 : "lakemont",
2178 : "pentiumpro",
2179 : "pentium4",
2180 : "nocona",
2181 : "core2",
2182 : "nehalem",
2183 : "sandybridge",
2184 : "haswell",
2185 : "bonnell",
2186 : "silvermont",
2187 : "goldmont",
2188 : "goldmont-plus",
2189 : "tremont",
2190 : "sierraforest",
2191 : "grandridge",
2192 : "clearwaterforest",
2193 : "skylake",
2194 : "skylake-avx512",
2195 : "cannonlake",
2196 : "icelake-client",
2197 : "icelake-server",
2198 : "cascadelake",
2199 : "tigerlake",
2200 : "cooperlake",
2201 : "sapphirerapids",
2202 : "alderlake",
2203 : "rocketlake",
2204 : "graniterapids",
2205 : "graniterapids-d",
2206 : "arrowlake",
2207 : "arrowlake-s",
2208 : "pantherlake",
2209 : "diamondrapids",
2210 : "novalake",
2211 : "intel",
2212 : "lujiazui",
2213 : "yongfeng",
2214 : "shijidadao",
2215 : "geode",
2216 : "k6",
2217 : "athlon",
2218 : "k8",
2219 : "amdfam10",
2220 : "bdver1",
2221 : "bdver2",
2222 : "bdver3",
2223 : "bdver4",
2224 : "btver1",
2225 : "btver2",
2226 : "znver1",
2227 : "znver2",
2228 : "znver3",
2229 : "znver4",
2230 : "znver5",
2231 : "znver6",
2232 : "c86-4g-m4",
2233 : "c86-4g-m6",
2234 : "c86-4g-m7",
2235 : "c86-4g-m8"
2236 : };
2237 :
2238 : /* Guarantee that the array is aligned with enum processor_type. */
2239 : STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
2240 :
2241 : const pta processor_alias_table[] =
2242 : {
2243 : {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
2244 : {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
2245 : {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2246 : {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
2247 : {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
2248 : 0, P_NONE},
2249 : {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
2250 : {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
2251 : {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2252 : 0, P_NONE},
2253 : {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2254 : {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
2255 : 0, P_NONE},
2256 : {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2257 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2258 : {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2259 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2260 : {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2261 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2262 : {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2263 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2264 : {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2265 : {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
2266 : {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
2267 : 0, P_NONE},
2268 : {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2269 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2270 : {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2271 : PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
2272 : {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2273 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2274 : {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2275 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2276 : {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2277 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
2278 : {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2279 : PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
2280 : {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2281 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2282 : | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2283 : {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
2284 : M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
2285 : {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2286 : M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
2287 : {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
2288 : M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
2289 : {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
2290 : M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
2291 : {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2292 : PTA_SANDYBRIDGE,
2293 : M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
2294 : {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2295 : PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
2296 : {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2297 : PTA_IVYBRIDGE,
2298 : M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
2299 : {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
2300 : PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
2301 : {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2302 : M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
2303 : {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
2304 : 0, P_PROC_DYNAMIC},
2305 : {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
2306 : M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
2307 : {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
2308 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
2309 : {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
2310 : PTA_SKYLAKE_AVX512,
2311 : M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
2312 : {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
2313 : M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
2314 : {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
2315 : PTA_ICELAKE_CLIENT,
2316 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
2317 : {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
2318 : PTA_ROCKETLAKE,
2319 : M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
2320 : {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
2321 : PTA_ICELAKE_SERVER,
2322 : M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
2323 : {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
2324 : PTA_CASCADELAKE,
2325 : M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
2326 : {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
2327 : M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
2328 : {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
2329 : M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
2330 : {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2331 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2332 : {"emeraldrapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
2333 : M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
2334 : {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2335 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2336 : {"raptorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2337 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2338 : {"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2339 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2340 : {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
2341 : M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX10_1},
2342 : {"graniterapids-d", PROCESSOR_GRANITERAPIDS_D, CPU_HASWELL,
2343 : PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D),
2344 : P_PROC_AVX10_1},
2345 : {"arrowlake", PROCESSOR_ARROWLAKE, CPU_HASWELL, PTA_ARROWLAKE,
2346 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), P_PROC_AVX2},
2347 : {"arrowlake-s", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2348 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2349 : {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S,
2350 : M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2},
2351 : {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2352 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2353 : {"diamondrapids", PROCESSOR_DIAMONDRAPIDS, CPU_HASWELL, PTA_DIAMONDRAPIDS,
2354 : M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_2},
2355 : {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
2356 : M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
2357 : {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
2358 : M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
2359 : {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2360 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2361 : {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
2362 : M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
2363 : {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2364 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2365 : {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
2366 : M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
2367 : {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
2368 : M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
2369 : {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
2370 : M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
2371 : {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
2372 : M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
2373 : {"gracemont", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
2374 : M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
2375 : {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST,
2376 : M_CPU_TYPE (INTEL_SIERRAFOREST), P_PROC_AVX2},
2377 : {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE,
2378 : M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2},
2379 : {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL,
2380 : PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2},
2381 : {"intel", PROCESSOR_INTEL, CPU_HASWELL, PTA_HASWELL,
2382 : M_VENDOR (VENDOR_INTEL), P_NONE},
2383 : {"geode", PROCESSOR_GEODE, CPU_GEODE,
2384 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2385 : {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
2386 : {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2387 : {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
2388 : {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2389 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2390 : {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2391 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
2392 : {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2393 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2394 : {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2395 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2396 : {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2397 : PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
2398 : {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
2399 : {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
2400 : 0, P_NONE},
2401 : {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
2402 : 0, P_NONE},
2403 : {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
2404 : 0, P_NONE},
2405 : {"eden-x2", PROCESSOR_K8, CPU_K8,
2406 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
2407 : 0, P_NONE},
2408 : {"nano", PROCESSOR_K8, CPU_K8,
2409 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2410 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2411 : {"nano-1000", PROCESSOR_K8, CPU_K8,
2412 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2413 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2414 : {"nano-2000", PROCESSOR_K8, CPU_K8,
2415 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2416 : | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
2417 : {"nano-3000", PROCESSOR_K8, CPU_K8,
2418 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2419 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2420 : {"nano-x2", PROCESSOR_K8, CPU_K8,
2421 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2422 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2423 : {"eden-x4", PROCESSOR_K8, CPU_K8,
2424 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2425 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2426 : {"nano-x4", PROCESSOR_K8, CPU_K8,
2427 : PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2428 : | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
2429 : {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
2430 : PTA_LUJIAZUI,
2431 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_PROC_BMI},
2432 : {"yongfeng", PROCESSOR_YONGFENG, CPU_YONGFENG,
2433 : PTA_YONGFENG,
2434 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), P_PROC_AVX2},
2435 : {"shijidadao", PROCESSOR_SHIJIDADAO, CPU_YONGFENG,
2436 : PTA_YONGFENG,
2437 : M_CPU_SUBTYPE (ZHAOXIN_FAM7H_SHIJIDADAO), P_PROC_AVX2},
2438 : {"k8", PROCESSOR_K8, CPU_K8,
2439 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2440 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2441 : {"k8-sse3", PROCESSOR_K8, CPU_K8,
2442 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2443 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2444 : {"opteron", PROCESSOR_K8, CPU_K8,
2445 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2446 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2447 : {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2448 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2449 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2450 : {"athlon64", PROCESSOR_K8, CPU_K8,
2451 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2452 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2453 : {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2454 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2455 : | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2456 : {"athlon-fx", PROCESSOR_K8, CPU_K8,
2457 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2458 : | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2459 : {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2460 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2461 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2462 : 0, P_PROC_DYNAMIC},
2463 : {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2464 : PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2465 : | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2466 : M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2467 : {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2468 : PTA_BDVER1,
2469 : M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2470 : {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2471 : PTA_BDVER2,
2472 : M_CPU_SUBTYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2473 : {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2474 : PTA_BDVER3,
2475 : M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2476 : {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2477 : PTA_BDVER4,
2478 : M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2479 : {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2480 : PTA_ZNVER1,
2481 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2482 : {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2483 : PTA_ZNVER2,
2484 : M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2485 : {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2486 : PTA_ZNVER3,
2487 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2488 : {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2489 : PTA_ZNVER4,
2490 : M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2491 : {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
2492 : PTA_ZNVER5,
2493 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
2494 : {"znver6", PROCESSOR_ZNVER6, CPU_ZNVER5,
2495 : PTA_ZNVER6,
2496 : M_CPU_SUBTYPE (AMDFAM1AH_ZNVER6), P_PROC_AVX512F},
2497 : {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2498 : PTA_BTVER1,
2499 : M_CPU_TYPE (AMD_BTVER1), P_PROC_SSE4_A},
2500 : {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2501 : PTA_BTVER2,
2502 : M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2503 : {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
2504 : PTA_C86_4G_M4,
2505 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
2506 : {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
2507 : PTA_C86_4G_M6,
2508 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
2509 : {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
2510 : PTA_C86_4G_M7,
2511 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
2512 : {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8,
2513 : PTA_C86_4G_M8,
2514 : M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F},
2515 :
2516 : {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2517 : PTA_64BIT
2518 : | PTA_HLE /* flags are only used for -march switch. */,
2519 : 0, P_NONE},
2520 :
2521 : {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2522 : M_VENDOR (VENDOR_AMD), P_NONE},
2523 : {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2524 : M_CPU_TYPE (AMDFAM10H), P_NONE},
2525 : {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2526 : M_CPU_TYPE (AMDFAM15H), P_NONE},
2527 : {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2528 : M_CPU_TYPE (AMDFAM17H), P_NONE},
2529 : {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2530 : M_CPU_TYPE (AMDFAM19H), P_NONE},
2531 : {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2532 : M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
2533 : {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2534 : M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
2535 : {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2536 : M_VENDOR (VENDOR_HYGON), P_NONE},
2537 : {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2538 : M_CPU_TYPE (HYGONFAM18H), P_NONE},
2539 : };
2540 :
2541 : /* NB: processor_alias_table stops at the "generic" entry. */
2542 : unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
2543 : unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2544 :
2545 : /* Provide valid option values for -march and -mtune options. */
2546 :
2547 : vec<const char *>
2548 154416 : ix86_get_valid_option_values (int option_code,
2549 : const char *prefix ATTRIBUTE_UNUSED)
2550 : {
2551 154416 : vec<const char *> v;
2552 154416 : v.create (0);
2553 154416 : opt_code opt = (opt_code) option_code;
2554 :
2555 154416 : switch (opt)
2556 : {
2557 : case OPT_march_:
2558 70301 : for (unsigned i = 0; i < pta_size; i++)
2559 : {
2560 69720 : const char *name = processor_alias_table[i].name;
2561 69720 : gcc_checking_assert (name != NULL);
2562 69720 : v.safe_push (name);
2563 : }
2564 : #ifdef HAVE_LOCAL_CPU_DETECT
2565 : /* Add also "native" as possible value. */
2566 581 : v.safe_push ("native");
2567 : #endif
2568 :
2569 581 : break;
2570 : case OPT_mtune_:
2571 37184 : for (unsigned i = 0; i < PROCESSOR_max; i++)
2572 : {
2573 36603 : const char *name = processor_names[i];
2574 36603 : gcc_checking_assert (name != NULL);
2575 36603 : v.safe_push (name);
2576 : }
2577 : break;
2578 : default:
2579 : break;
2580 : }
2581 :
2582 154416 : return v;
2583 : }
2584 :
2585 : #undef TARGET_GET_VALID_OPTION_VALUES
2586 : #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2587 :
2588 : struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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