Line data Source code
1 : /* Get CPU type and Features for x86 processors.
2 : Copyright (C) 2012-2026 Free Software Foundation, Inc.
3 : Contributed by Sriraman Tallam (tmsriram@google.com)
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : Under Section 7 of GPL version 3, you are granted additional
18 : permissions described in the GCC Runtime Library Exception, version
19 : 3.1, as published by the Free Software Foundation.
20 :
21 : You should have received a copy of the GNU General Public License and
22 : a copy of the GCC Runtime Library Exception along with this program;
23 : see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 : <http://www.gnu.org/licenses/>. */
25 :
26 : /* Processor Vendor and Models. */
27 :
28 : enum processor_vendor
29 : {
30 : VENDOR_INTEL = 1,
31 : VENDOR_AMD,
32 : VENDOR_ZHAOXIN,
33 : VENDOR_HYGON,
34 : VENDOR_OTHER,
35 : VENDOR_CENTAUR,
36 : VENDOR_CYRIX,
37 : VENDOR_NSC,
38 :
39 : /* Maximum values must be at the end of this enum. */
40 : VENDOR_MAX,
41 : BUILTIN_VENDOR_MAX = VENDOR_OTHER
42 : };
43 :
44 : /* Any new types or subtypes have to be inserted at the end. */
45 :
46 : enum processor_types
47 : {
48 : INTEL_BONNELL = 1,
49 : INTEL_CORE2,
50 : INTEL_COREI7,
51 : AMDFAM10H,
52 : AMDFAM15H,
53 : INTEL_SILVERMONT,
54 : AMD_BTVER1 = 8,
55 : AMD_BTVER2,
56 : AMDFAM17H,
57 : INTEL_GOLDMONT = 12,
58 : INTEL_GOLDMONT_PLUS,
59 : INTEL_TREMONT,
60 : AMDFAM19H,
61 : ZHAOXIN_FAM7H,
62 : INTEL_SIERRAFOREST,
63 : INTEL_GRANDRIDGE,
64 : INTEL_CLEARWATERFOREST,
65 : AMDFAM1AH,
66 : HYGONFAM18H,
67 : CPU_TYPE_MAX,
68 : BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
69 : };
70 :
71 : enum processor_subtypes
72 : {
73 : INTEL_COREI7_NEHALEM = 1,
74 : INTEL_COREI7_WESTMERE,
75 : INTEL_COREI7_SANDYBRIDGE,
76 : AMDFAM10H_BARCELONA,
77 : AMDFAM10H_SHANGHAI,
78 : AMDFAM10H_ISTANBUL,
79 : AMDFAM15H_BDVER1,
80 : AMDFAM15H_BDVER2,
81 : AMDFAM15H_BDVER3,
82 : AMDFAM15H_BDVER4,
83 : AMDFAM17H_ZNVER1,
84 : INTEL_COREI7_IVYBRIDGE,
85 : INTEL_COREI7_HASWELL,
86 : INTEL_COREI7_BROADWELL,
87 : INTEL_COREI7_SKYLAKE,
88 : INTEL_COREI7_SKYLAKE_AVX512,
89 : INTEL_COREI7_CANNONLAKE,
90 : INTEL_COREI7_ICELAKE_CLIENT,
91 : INTEL_COREI7_ICELAKE_SERVER,
92 : AMDFAM17H_ZNVER2,
93 : INTEL_COREI7_CASCADELAKE,
94 : INTEL_COREI7_TIGERLAKE,
95 : INTEL_COREI7_COOPERLAKE,
96 : INTEL_COREI7_SAPPHIRERAPIDS,
97 : INTEL_COREI7_ALDERLAKE,
98 : AMDFAM19H_ZNVER3,
99 : INTEL_COREI7_ROCKETLAKE,
100 : ZHAOXIN_FAM7H_LUJIAZUI,
101 : AMDFAM19H_ZNVER4,
102 : INTEL_COREI7_GRANITERAPIDS,
103 : INTEL_COREI7_GRANITERAPIDS_D,
104 : INTEL_COREI7_ARROWLAKE,
105 : INTEL_COREI7_ARROWLAKE_S,
106 : INTEL_COREI7_PANTHERLAKE,
107 : ZHAOXIN_FAM7H_YONGFENG,
108 : AMDFAM1AH_ZNVER5,
109 : ZHAOXIN_FAM7H_SHIJIDADAO,
110 : INTEL_COREI7_DIAMONDRAPIDS,
111 : INTEL_COREI7_NOVALAKE,
112 : AMDFAM1AH_ZNVER6,
113 : HYGONFAM18H_C86_4G_M4,
114 : HYGONFAM18H_C86_4G_M6,
115 : HYGONFAM18H_C86_4G_M7,
116 : HYGONFAM18H_C86_4G_M8,
117 : CPU_SUBTYPE_MAX
118 : };
119 :
120 : /* Priority of i386 features, greater value is higher priority. This is
121 : used to decide the order in which function dispatch must happen. For
122 : instance, a version specialized for SSE4.2 should be checked for dispatch
123 : before a version for SSE3. */
124 : enum feature_priority
125 : {
126 : P_NONE = 0,
127 : P_MMX,
128 : P_SSE,
129 : P_SSE2,
130 : P_X86_64_BASELINE,
131 : P_SSE3,
132 : P_SSSE3,
133 : P_PROC_SSSE3,
134 : P_SSE4_A,
135 : P_PROC_SSE4_A,
136 : P_SSE4_1,
137 : P_SSE4_2,
138 : P_PROC_SSE4_2,
139 : P_POPCNT,
140 : P_X86_64_V2,
141 : P_AES,
142 : P_PCLMUL,
143 : P_AVX,
144 : P_PROC_AVX,
145 : P_BMI,
146 : P_PROC_BMI,
147 : P_FMA4,
148 : P_XOP,
149 : P_PROC_XOP,
150 : P_FMA,
151 : P_PROC_FMA,
152 : P_BMI2,
153 : P_AVX2,
154 : P_PROC_AVX2,
155 : P_X86_64_V3,
156 : P_AVX512F,
157 : P_PROC_AVX512F,
158 : P_X86_64_V4,
159 : P_AVX10_1 = 34,
160 : P_PROC_AVX10_1,
161 : P_AVX10_2,
162 : P_APX_F,
163 : P_PROC_AVX10_2,
164 : P_PROC_DYNAMIC
165 : };
166 :
167 : /* ISA Features supported. New features have to be inserted at the end. */
168 :
169 : enum processor_features
170 : {
171 : FEATURE_CMOV = 0,
172 : FEATURE_MMX,
173 : FEATURE_POPCNT,
174 : FEATURE_SSE,
175 : FEATURE_SSE2,
176 : FEATURE_SSE3,
177 : FEATURE_SSSE3,
178 : FEATURE_SSE4_1,
179 : FEATURE_SSE4_2,
180 : FEATURE_AVX,
181 : FEATURE_AVX2,
182 : FEATURE_SSE4_A,
183 : FEATURE_FMA4,
184 : FEATURE_XOP,
185 : FEATURE_FMA,
186 : FEATURE_AVX512F,
187 : FEATURE_BMI,
188 : FEATURE_BMI2,
189 : FEATURE_AES,
190 : FEATURE_PCLMUL,
191 : FEATURE_AVX512VL,
192 : FEATURE_AVX512BW,
193 : FEATURE_AVX512DQ,
194 : FEATURE_AVX512CD,
195 : FEATURE_AVX512VBMI = 26,
196 : FEATURE_AVX512IFMA,
197 : FEATURE_AVX512VPOPCNTDQ = 30,
198 : FEATURE_AVX512VBMI2,
199 : FEATURE_GFNI,
200 : FEATURE_VPCLMULQDQ,
201 : FEATURE_AVX512VNNI,
202 : FEATURE_AVX512BITALG,
203 : FEATURE_AVX512BF16,
204 : FEATURE_AVX512VP2INTERSECT,
205 : FEATURE_3DNOW,
206 : FEATURE_3DNOWP,
207 : FEATURE_ADX,
208 : FEATURE_ABM,
209 : FEATURE_CLDEMOTE,
210 : FEATURE_CLFLUSHOPT,
211 : FEATURE_CLWB,
212 : FEATURE_CLZERO,
213 : FEATURE_CMPXCHG16B,
214 : FEATURE_CMPXCHG8B,
215 : FEATURE_ENQCMD,
216 : FEATURE_F16C,
217 : FEATURE_FSGSBASE,
218 : FEATURE_FXSAVE,
219 : FEATURE_HLE,
220 : FEATURE_IBT,
221 : FEATURE_LAHF_LM,
222 : FEATURE_LM,
223 : FEATURE_LWP,
224 : FEATURE_LZCNT,
225 : FEATURE_MOVBE,
226 : FEATURE_MOVDIR64B,
227 : FEATURE_MOVDIRI,
228 : FEATURE_MWAITX,
229 : FEATURE_OSXSAVE,
230 : FEATURE_PCONFIG,
231 : FEATURE_PKU,
232 : FEATURE_PRFCHW = 66,
233 : FEATURE_PTWRITE,
234 : FEATURE_RDPID,
235 : FEATURE_RDRND,
236 : FEATURE_RDSEED,
237 : FEATURE_RTM,
238 : FEATURE_SERIALIZE,
239 : FEATURE_SGX,
240 : FEATURE_SHA,
241 : FEATURE_SHSTK,
242 : FEATURE_TBM,
243 : FEATURE_TSXLDTRK,
244 : FEATURE_VAES,
245 : FEATURE_WAITPKG,
246 : FEATURE_WBNOINVD,
247 : FEATURE_XSAVE,
248 : FEATURE_XSAVEC,
249 : FEATURE_XSAVEOPT,
250 : FEATURE_XSAVES,
251 : FEATURE_AMX_TILE,
252 : FEATURE_AMX_INT8,
253 : FEATURE_AMX_BF16,
254 : FEATURE_UINTR,
255 : FEATURE_HRESET,
256 : FEATURE_KL,
257 : FEATURE_AESKLE,
258 : FEATURE_WIDEKL,
259 : FEATURE_AVXVNNI,
260 : FEATURE_AVX512FP16,
261 : FEATURE_X86_64_BASELINE,
262 : FEATURE_X86_64_V2,
263 : FEATURE_X86_64_V3,
264 : FEATURE_X86_64_V4,
265 : FEATURE_AVXIFMA,
266 : FEATURE_AVXVNNIINT8,
267 : FEATURE_AVXNECONVERT,
268 : FEATURE_CMPCCXADD,
269 : FEATURE_AMX_FP16,
270 : FEATURE_PREFETCHI,
271 : FEATURE_RAOINT,
272 : FEATURE_AMX_COMPLEX,
273 : FEATURE_AVXVNNIINT16,
274 : FEATURE_SM3,
275 : FEATURE_SHA512,
276 : FEATURE_SM4,
277 : FEATURE_APX_F,
278 : FEATURE_USER_MSR,
279 : FEATURE_AVX10_1 = 114,
280 : FEATURE_AVX10_2 = 116,
281 : FEATURE_AMX_AVX512,
282 : FEATURE_AMX_FP8 = 120,
283 : FEATURE_MOVRS,
284 : FEATURE_AMX_MOVRS,
285 : FEATURE_AVX512BMM,
286 : FEATURE_AVX10V2AUX,
287 : FEATURE_ACEV1,
288 : CPU_FEATURE_MAX
289 : };
290 :
291 : /* Size of __cpu_features2 array in libgcc/config/i386/cpuinfo.c. */
292 : #define SIZE_OF_CPU_FEATURES ((CPU_FEATURE_MAX - 1) / 32)
293 :
294 : /* These are the values for vendor types, cpu types and subtypes. Cpu
295 : types and subtypes should be subtracted by the corresponding start
296 : value. */
297 :
298 : #define M_CPU_TYPE_START (BUILTIN_VENDOR_MAX)
299 : #define M_CPU_SUBTYPE_START \
300 : (M_CPU_TYPE_START + int (BUILTIN_CPU_TYPE_MAX))
301 : #define M_VENDOR(a) (a)
302 : #define M_CPU_TYPE(a) (M_CPU_TYPE_START + int (a))
303 : #define M_CPU_SUBTYPE(a) (M_CPU_SUBTYPE_START + a)
304 :
305 : #ifdef __cplusplus
306 : /* Extract processor VENDOR, TYPE and SUBTYPE from MODEL. */
307 :
308 : static inline void
309 50722604 : ix86_decode_cpu_info (int model, processor_vendor &vendor,
310 : processor_types &type,
311 : processor_subtypes &subtype)
312 : {
313 50722604 : if (model > M_CPU_SUBTYPE_START)
314 : {
315 323305 : subtype = (processor_subtypes) (model - M_CPU_SUBTYPE_START);
316 323305 : if (subtype <= INTEL_COREI7_SANDYBRIDGE
317 : || (subtype >= INTEL_COREI7_IVYBRIDGE
318 322965 : && subtype <= INTEL_COREI7_ICELAKE_SERVER)
319 : || (subtype >= INTEL_COREI7_CASCADELAKE
320 : && subtype <= INTEL_COREI7_ALDERLAKE)
321 : || subtype == INTEL_COREI7_ROCKETLAKE
322 : || (subtype >= INTEL_COREI7_GRANITERAPIDS
323 : && subtype <= INTEL_COREI7_PANTHERLAKE)
324 : || subtype == INTEL_COREI7_DIAMONDRAPIDS
325 : || subtype == INTEL_COREI7_NOVALAKE)
326 : {
327 317607 : vendor = VENDOR_INTEL;
328 317607 : type = INTEL_COREI7;
329 : }
330 : else if (subtype >= AMDFAM10H_BARCELONA
331 : && subtype <= AMDFAM10H_ISTANBUL)
332 : {
333 3 : vendor = VENDOR_AMD;
334 3 : type = AMDFAM10H;
335 : }
336 : else if (subtype >= AMDFAM15H_BDVER1
337 : && subtype <= AMDFAM15H_BDVER4)
338 : {
339 681 : vendor = VENDOR_AMD;
340 681 : type = AMDFAM15H;
341 : }
342 : else if (subtype == AMDFAM17H_ZNVER1
343 : || subtype == AMDFAM17H_ZNVER2)
344 : {
345 139 : vendor = VENDOR_AMD;
346 139 : type = AMDFAM17H;
347 : }
348 : else if (subtype == AMDFAM19H_ZNVER3
349 : || subtype == AMDFAM19H_ZNVER4)
350 : {
351 4587 : vendor = VENDOR_AMD;
352 4587 : type = AMDFAM19H;
353 : }
354 : else if (subtype == AMDFAM1AH_ZNVER5
355 : || subtype == AMDFAM1AH_ZNVER6)
356 : {
357 109 : vendor = VENDOR_AMD;
358 109 : type = AMDFAM1AH;
359 : }
360 : else if (subtype == ZHAOXIN_FAM7H_LUJIAZUI
361 : || subtype == ZHAOXIN_FAM7H_YONGFENG
362 : || subtype == ZHAOXIN_FAM7H_SHIJIDADAO)
363 : {
364 68 : vendor = VENDOR_ZHAOXIN;
365 68 : type = ZHAOXIN_FAM7H;
366 : }
367 : else if (subtype >= HYGONFAM18H_C86_4G_M4
368 : && subtype <= HYGONFAM18H_C86_4G_M8)
369 : {
370 111 : vendor = VENDOR_HYGON;
371 111 : type = HYGONFAM18H;
372 : }
373 : else
374 : {
375 : /* Set VENDOR to VENDOR_OTHER and TYPE to CPU_TYPE_MAX for
376 : unsupported SUBTYPE. */
377 0 : vendor = VENDOR_OTHER;
378 0 : type = CPU_TYPE_MAX;
379 : }
380 : }
381 50399299 : else if (model > M_CPU_TYPE_START)
382 : {
383 56550 : type = (processor_types) (model - M_CPU_TYPE_START);
384 56550 : if ((type >= INTEL_BONNELL && type <= INTEL_COREI7)
385 : || type == INTEL_SILVERMONT
386 : || (type >= INTEL_GOLDMONT && type <= INTEL_TREMONT)
387 : || (type >= INTEL_SIERRAFOREST
388 : && type <= INTEL_CLEARWATERFOREST))
389 : {
390 56407 : vendor = VENDOR_INTEL;
391 56407 : subtype = CPU_SUBTYPE_MAX;
392 : }
393 : else if (type == AMDFAM10H
394 : || type == AMDFAM15H
395 : || (type >= AMD_BTVER1 && type <= AMDFAM17H)
396 : || type == AMDFAM19H
397 : || type == AMDFAM1AH)
398 : {
399 143 : vendor = VENDOR_AMD;
400 143 : subtype = CPU_SUBTYPE_MAX;
401 : }
402 : else if (type == ZHAOXIN_FAM7H)
403 : {
404 0 : vendor = VENDOR_ZHAOXIN;
405 0 : subtype = CPU_SUBTYPE_MAX;
406 : }
407 : else if (type == HYGONFAM18H)
408 : {
409 0 : vendor = VENDOR_HYGON;
410 0 : subtype = CPU_SUBTYPE_MAX;
411 : }
412 : else
413 : {
414 : /* Set VENDOR to VENDOR_OTHER and SUBTYPE to CPU_SUBTYPE_MAX
415 : for unsupported TYPE. */
416 0 : vendor = VENDOR_OTHER;
417 0 : subtype = CPU_SUBTYPE_MAX;
418 : }
419 : }
420 : else
421 : {
422 50342749 : vendor = (processor_vendor) model;
423 : /* Set TYPE to CPU_TYPE_MAX and SUBTYPE to CPU_SUBTYPE_MAX for
424 : unknown TYPE and SUBTYPE. */
425 50342749 : type = CPU_TYPE_MAX;
426 50342749 : subtype = CPU_SUBTYPE_MAX;
427 : }
428 50722604 : }
429 : #endif
|
