Line data Source code
1 : /* Copyright (C) 1988-2026 Free Software Foundation, Inc.
2 :
3 : This file is part of GCC.
4 :
5 : GCC is free software; you can redistribute it and/or modify
6 : it under the terms of the GNU General Public License as published by
7 : the Free Software Foundation; either version 3, or (at your option)
8 : any later version.
9 :
10 : GCC is distributed in the hope that it will be useful,
11 : but WITHOUT ANY WARRANTY; without even the implied warranty of
12 : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 : GNU General Public License for more details.
14 :
15 : You should have received a copy of the GNU General Public License
16 : along with GCC; see the file COPYING3. If not see
17 : <http://www.gnu.org/licenses/>. */
18 :
19 : #define IN_TARGET_CODE 1
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "rtl.h"
26 : #include "tree.h"
27 : #include "memmodel.h"
28 : #include "gimple.h"
29 : #include "cfghooks.h"
30 : #include "cfgloop.h"
31 : #include "df.h"
32 : #include "tm_p.h"
33 : #include "stringpool.h"
34 : #include "expmed.h"
35 : #include "optabs.h"
36 : #include "regs.h"
37 : #include "emit-rtl.h"
38 : #include "recog.h"
39 : #include "cgraph.h"
40 : #include "diagnostic.h"
41 : #include "cfgbuild.h"
42 : #include "alias.h"
43 : #include "fold-const.h"
44 : #include "attribs.h"
45 : #include "calls.h"
46 : #include "stor-layout.h"
47 : #include "varasm.h"
48 : #include "output.h"
49 : #include "insn-attr.h"
50 : #include "flags.h"
51 : #include "except.h"
52 : #include "explow.h"
53 : #include "expr.h"
54 : #include "cfgrtl.h"
55 : #include "common/common-target.h"
56 : #include "langhooks.h"
57 : #include "reload.h"
58 : #include "gimplify.h"
59 : #include "dwarf2.h"
60 : #include "tm-constrs.h"
61 : #include "cselib.h"
62 : #include "sched-int.h"
63 : #include "opts.h"
64 : #include "tree-pass.h"
65 : #include "context.h"
66 : #include "pass_manager.h"
67 : #include "target-globals.h"
68 : #include "gimple-iterator.h"
69 : #include "shrink-wrap.h"
70 : #include "builtins.h"
71 : #include "rtl-iter.h"
72 : #include "tree-iterator.h"
73 : #include "dbgcnt.h"
74 : #include "case-cfn-macros.h"
75 : #include "dojump.h"
76 : #include "fold-const-call.h"
77 : #include "tree-vrp.h"
78 : #include "tree-ssanames.h"
79 : #include "selftest.h"
80 : #include "selftest-rtl.h"
81 : #include "print-rtl.h"
82 : #include "intl.h"
83 : #include "ifcvt.h"
84 : #include "symbol-summary.h"
85 : #include "sreal.h"
86 : #include "ipa-cp.h"
87 : #include "ipa-prop.h"
88 : #include "ipa-fnsummary.h"
89 : #include "wide-int-bitmask.h"
90 : #include "tree-vector-builder.h"
91 : #include "debug.h"
92 : #include "dwarf2out.h"
93 : #include "function-abi.h"
94 : #include "i386-builtins.h"
95 : #include "i386-features.h"
96 : #include "i386-expand.h"
97 :
98 : const char * const xlogue_layout::STUB_BASE_NAMES[XLOGUE_STUB_COUNT] = {
99 : "savms64",
100 : "resms64",
101 : "resms64x",
102 : "savms64f",
103 : "resms64f",
104 : "resms64fx"
105 : };
106 :
107 : const unsigned xlogue_layout::REG_ORDER[xlogue_layout::MAX_REGS] = {
108 : /* The below offset values are where each register is stored for the layout
109 : relative to incoming stack pointer. The value of each m_regs[].offset will
110 : be relative to the incoming base pointer (rax or rsi) used by the stub.
111 :
112 : s_instances: 0 1 2 3
113 : Offset: realigned or aligned + 8
114 : Register aligned aligned + 8 aligned w/HFP w/HFP */
115 : XMM15_REG, /* 0x10 0x18 0x10 0x18 */
116 : XMM14_REG, /* 0x20 0x28 0x20 0x28 */
117 : XMM13_REG, /* 0x30 0x38 0x30 0x38 */
118 : XMM12_REG, /* 0x40 0x48 0x40 0x48 */
119 : XMM11_REG, /* 0x50 0x58 0x50 0x58 */
120 : XMM10_REG, /* 0x60 0x68 0x60 0x68 */
121 : XMM9_REG, /* 0x70 0x78 0x70 0x78 */
122 : XMM8_REG, /* 0x80 0x88 0x80 0x88 */
123 : XMM7_REG, /* 0x90 0x98 0x90 0x98 */
124 : XMM6_REG, /* 0xa0 0xa8 0xa0 0xa8 */
125 : SI_REG, /* 0xa8 0xb0 0xa8 0xb0 */
126 : DI_REG, /* 0xb0 0xb8 0xb0 0xb8 */
127 : BX_REG, /* 0xb8 0xc0 0xb8 0xc0 */
128 : BP_REG, /* 0xc0 0xc8 N/A N/A */
129 : R12_REG, /* 0xc8 0xd0 0xc0 0xc8 */
130 : R13_REG, /* 0xd0 0xd8 0xc8 0xd0 */
131 : R14_REG, /* 0xd8 0xe0 0xd0 0xd8 */
132 : R15_REG, /* 0xe0 0xe8 0xd8 0xe0 */
133 : };
134 :
135 : /* Instantiate static const values. */
136 : const HOST_WIDE_INT xlogue_layout::STUB_INDEX_OFFSET;
137 : const unsigned xlogue_layout::MIN_REGS;
138 : const unsigned xlogue_layout::MAX_REGS;
139 : const unsigned xlogue_layout::MAX_EXTRA_REGS;
140 : const unsigned xlogue_layout::VARIANT_COUNT;
141 : const unsigned xlogue_layout::STUB_NAME_MAX_LEN;
142 :
143 : /* Initialize xlogue_layout::s_stub_names to zero. */
144 : char xlogue_layout::s_stub_names[2][XLOGUE_STUB_COUNT][VARIANT_COUNT]
145 : [STUB_NAME_MAX_LEN];
146 :
147 : /* Instantiates all xlogue_layout instances. */
148 : const xlogue_layout xlogue_layout::s_instances[XLOGUE_SET_COUNT] = {
149 : xlogue_layout (0, false),
150 : xlogue_layout (8, false),
151 : xlogue_layout (0, true),
152 : xlogue_layout (8, true)
153 : };
154 :
155 : /* Return an appropriate const instance of xlogue_layout based upon values
156 : in cfun->machine and crtl. */
157 : const class xlogue_layout &
158 49891 : xlogue_layout::get_instance ()
159 : {
160 49891 : enum xlogue_stub_sets stub_set;
161 49891 : bool aligned_plus_8 = cfun->machine->call_ms2sysv_pad_in;
162 :
163 49891 : if (stack_realign_fp)
164 : stub_set = XLOGUE_SET_HFP_ALIGNED_OR_REALIGN;
165 40910 : else if (frame_pointer_needed)
166 25246 : stub_set = aligned_plus_8
167 31552 : ? XLOGUE_SET_HFP_ALIGNED_PLUS_8
168 : : XLOGUE_SET_HFP_ALIGNED_OR_REALIGN;
169 : else
170 9358 : stub_set = aligned_plus_8 ? XLOGUE_SET_ALIGNED_PLUS_8 : XLOGUE_SET_ALIGNED;
171 :
172 49891 : return s_instances[stub_set];
173 : }
174 :
175 : /* Determine how many clobbered registers can be saved by the stub.
176 : Returns the count of registers the stub will save and restore. */
177 : unsigned
178 35225 : xlogue_layout::count_stub_managed_regs ()
179 : {
180 35225 : bool hfp = frame_pointer_needed || stack_realign_fp;
181 35225 : unsigned i, count;
182 35225 : unsigned regno;
183 :
184 93950 : for (count = i = MIN_REGS; i < MAX_REGS; ++i)
185 : {
186 92750 : regno = REG_ORDER[i];
187 92750 : if (regno == BP_REG && hfp)
188 17880 : continue;
189 74870 : if (!ix86_save_reg (regno, false, false))
190 : break;
191 40845 : ++count;
192 : }
193 35225 : return count;
194 : }
195 :
196 : /* Determine if register REGNO is a stub managed register given the
197 : total COUNT of stub managed registers. */
198 : bool
199 2642240 : xlogue_layout::is_stub_managed_reg (unsigned regno, unsigned count)
200 : {
201 2642240 : bool hfp = frame_pointer_needed || stack_realign_fp;
202 2642240 : unsigned i;
203 :
204 34418160 : for (i = 0; i < count; ++i)
205 : {
206 32275013 : gcc_assert (i < MAX_REGS);
207 32275013 : if (REG_ORDER[i] == BP_REG && hfp)
208 510254 : ++count;
209 31764759 : else if (REG_ORDER[i] == regno)
210 : return true;
211 : }
212 : return false;
213 : }
214 :
215 : /* Constructor for xlogue_layout. */
216 1172300 : xlogue_layout::xlogue_layout (HOST_WIDE_INT stack_align_off_in, bool hfp)
217 1172300 : : m_hfp (hfp) , m_nregs (hfp ? 17 : 18),
218 1172300 : m_stack_align_off_in (stack_align_off_in)
219 : {
220 1172300 : HOST_WIDE_INT offset = stack_align_off_in;
221 1172300 : unsigned i, j;
222 :
223 22273700 : for (i = j = 0; i < MAX_REGS; ++i)
224 : {
225 21101400 : unsigned regno = REG_ORDER[i];
226 :
227 21101400 : if (regno == BP_REG && hfp)
228 586150 : continue;
229 20515250 : if (SSE_REGNO_P (regno))
230 : {
231 11723000 : offset += 16;
232 : /* Verify that SSE regs are always aligned. */
233 11723000 : gcc_assert (!((stack_align_off_in + offset) & 15));
234 : }
235 : else
236 8792250 : offset += 8;
237 :
238 20515250 : m_regs[j].regno = regno;
239 20515250 : m_regs[j++].offset = offset - STUB_INDEX_OFFSET;
240 : }
241 1172300 : gcc_assert (j == m_nregs);
242 1172300 : }
243 :
244 : const char *
245 14666 : xlogue_layout::get_stub_name (enum xlogue_stub stub,
246 : unsigned n_extra_regs)
247 : {
248 14666 : const int have_avx = TARGET_AVX;
249 14666 : char *name = s_stub_names[!!have_avx][stub][n_extra_regs];
250 :
251 : /* Lazy init */
252 14666 : if (!*name)
253 : {
254 362 : int res = snprintf (name, STUB_NAME_MAX_LEN, "__%s_%s_%u",
255 : (have_avx ? "avx" : "sse"),
256 181 : STUB_BASE_NAMES[stub],
257 : MIN_REGS + n_extra_regs);
258 181 : gcc_checking_assert (res < (int)STUB_NAME_MAX_LEN);
259 : }
260 :
261 14666 : return name;
262 : }
263 :
264 : /* Return rtx of a symbol ref for the entry point (based upon
265 : cfun->machine->call_ms2sysv_extra_regs) of the specified stub. */
266 : rtx
267 14666 : xlogue_layout::get_stub_rtx (enum xlogue_stub stub)
268 : {
269 14666 : const unsigned n_extra_regs = cfun->machine->call_ms2sysv_extra_regs;
270 14666 : gcc_checking_assert (n_extra_regs <= MAX_EXTRA_REGS);
271 14666 : gcc_assert (stub < XLOGUE_STUB_COUNT);
272 14666 : gcc_assert (crtl->stack_realign_finalized);
273 :
274 14666 : return gen_rtx_SYMBOL_REF (Pmode, get_stub_name (stub, n_extra_regs));
275 : }
276 :
277 : unsigned scalar_chain::max_id = 0;
278 :
279 : namespace {
280 :
281 : /* Initialize new chain. */
282 :
283 6608140 : scalar_chain::scalar_chain (enum machine_mode smode_, enum machine_mode vmode_)
284 : {
285 6608140 : smode = smode_;
286 6608140 : vmode = vmode_;
287 :
288 6608140 : chain_id = ++max_id;
289 :
290 6608140 : if (dump_file)
291 136 : fprintf (dump_file, "Created a new instruction chain #%d\n", chain_id);
292 :
293 6608140 : bitmap_obstack_initialize (NULL);
294 6608140 : insns = BITMAP_ALLOC (NULL);
295 6608140 : defs = BITMAP_ALLOC (NULL);
296 6608140 : defs_conv = BITMAP_ALLOC (NULL);
297 6608140 : insns_conv = BITMAP_ALLOC (NULL);
298 6608140 : queue = NULL;
299 :
300 6608140 : cost_sse_integer = 0;
301 6608140 : weighted_cost_sse_integer = 0 ;
302 6608140 : max_visits = x86_stv_max_visits;
303 6608140 : }
304 :
305 : /* Free chain's data. */
306 :
307 6608140 : scalar_chain::~scalar_chain ()
308 : {
309 6608140 : BITMAP_FREE (insns);
310 6608140 : BITMAP_FREE (defs);
311 6608140 : BITMAP_FREE (defs_conv);
312 6608140 : BITMAP_FREE (insns_conv);
313 6608140 : bitmap_obstack_release (NULL);
314 6608140 : }
315 :
316 : /* Add instruction into chains' queue. */
317 :
318 : void
319 8558670 : scalar_chain::add_to_queue (unsigned insn_uid)
320 : {
321 8558670 : if (!bitmap_set_bit (queue, insn_uid))
322 : return;
323 :
324 6405273 : if (dump_file)
325 141 : fprintf (dump_file, " Adding insn %d into chain's #%d queue\n",
326 : insn_uid, chain_id);
327 : }
328 :
329 : /* For DImode conversion, mark register defined by DEF as requiring
330 : conversion. */
331 :
332 : void
333 9722264 : scalar_chain::mark_dual_mode_def (df_ref def)
334 : {
335 9722264 : gcc_assert (DF_REF_REG_DEF_P (def));
336 :
337 : /* Record the def/insn pair so we can later efficiently iterate over
338 : the defs to convert on insns not in the chain. */
339 9722264 : bool reg_new = bitmap_set_bit (defs_conv, DF_REF_REGNO (def));
340 9722264 : basic_block bb = BLOCK_FOR_INSN (DF_REF_INSN (def));
341 9722264 : profile_count entry_count = ENTRY_BLOCK_PTR_FOR_FN (cfun)->count;
342 9722264 : bool speed_p = optimize_bb_for_speed_p (bb);
343 9722264 : int cost = 0;
344 :
345 9722264 : if (!bitmap_bit_p (insns, DF_REF_INSN_UID (def)))
346 : {
347 2936821 : if (!bitmap_set_bit (insns_conv, DF_REF_INSN_UID (def))
348 2936821 : && !reg_new)
349 1507011 : return;
350 :
351 : /* Cost integer to sse moves. */
352 2580553 : if (speed_p)
353 2278916 : cost = COSTS_N_INSNS (ix86_cost->integer_to_sse) / 2;
354 301637 : else if (TARGET_64BIT || smode == SImode)
355 : cost = COSTS_N_BYTES (4);
356 : /* vmovd (4 bytes) + vpinsrd (6 bytes). */
357 18773 : else if (TARGET_SSE4_1)
358 : cost = COSTS_N_BYTES (10);
359 : /* movd (4 bytes) + movd (4 bytes) + unpckldq (4 bytes). */
360 : else
361 8215253 : cost = COSTS_N_BYTES (12);
362 : }
363 : else
364 : {
365 6785443 : if (!reg_new)
366 : return;
367 :
368 : /* Cost sse to integer moves. */
369 5634700 : if (speed_p)
370 5051846 : cost = COSTS_N_INSNS (ix86_cost->sse_to_integer) / 2;
371 582854 : else if (TARGET_64BIT || smode == SImode)
372 : cost = COSTS_N_BYTES (4);
373 : /* vmovd (4 bytes) + vpextrd (6 bytes). */
374 2927 : else if (TARGET_SSE4_1)
375 : cost = COSTS_N_BYTES (10);
376 : /* movd (4 bytes) + psrlq (5 bytes) + movd (4 bytes). */
377 : else
378 8215253 : cost = COSTS_N_BYTES (13);
379 : }
380 :
381 8215253 : if (speed_p)
382 7330762 : weighted_cost_sse_integer += bb->count.to_sreal_scale (entry_count) * cost;
383 :
384 8215253 : cost_sse_integer += cost;
385 :
386 8215253 : if (dump_file)
387 240 : fprintf (dump_file,
388 : " Mark r%d def in insn %d as requiring both modes in chain #%d\n",
389 240 : DF_REF_REGNO (def), DF_REF_INSN_UID (def), chain_id);
390 : }
391 :
392 : /* Check REF's chain to add new insns into a queue
393 : and find registers requiring conversion. Return true if OK, false
394 : if the analysis was aborted. */
395 :
396 : bool
397 18340912 : scalar_chain::analyze_register_chain (bitmap candidates, df_ref ref,
398 : bitmap disallowed)
399 : {
400 18340912 : df_link *chain;
401 18340912 : bool mark_def = false;
402 :
403 18340912 : gcc_checking_assert (bitmap_bit_p (insns, DF_REF_INSN_UID (ref)));
404 :
405 63862534 : for (chain = DF_REF_CHAIN (ref); chain; chain = chain->next)
406 : {
407 45525987 : unsigned uid = DF_REF_INSN_UID (chain->ref);
408 :
409 45525987 : if (!NONDEBUG_INSN_P (DF_REF_INSN (chain->ref)))
410 8291877 : continue;
411 :
412 37234110 : if (--max_visits == 0)
413 : return false;
414 :
415 37233543 : if (!DF_REF_REG_MEM_P (chain->ref))
416 : {
417 31187357 : if (bitmap_bit_p (insns, uid))
418 9878944 : continue;
419 :
420 21308413 : if (bitmap_bit_p (candidates, uid))
421 : {
422 8558670 : add_to_queue (uid);
423 8558670 : continue;
424 : }
425 :
426 : /* If we run into parts of an aborted chain discovery abort. */
427 12749743 : if (bitmap_bit_p (disallowed, uid))
428 : return false;
429 : }
430 :
431 18792131 : if (DF_REF_REG_DEF_P (chain->ref))
432 : {
433 2936821 : if (dump_file)
434 125 : fprintf (dump_file, " r%d def in insn %d isn't convertible\n",
435 : DF_REF_REGNO (chain->ref), uid);
436 2936821 : mark_dual_mode_def (chain->ref);
437 : }
438 : else
439 : {
440 15855310 : if (dump_file)
441 524 : fprintf (dump_file, " r%d use in insn %d isn't convertible\n",
442 : DF_REF_REGNO (chain->ref), uid);
443 : mark_def = true;
444 : }
445 : }
446 :
447 18336547 : if (mark_def)
448 6785443 : mark_dual_mode_def (ref);
449 :
450 : return true;
451 : }
452 :
453 : /* Check whether X is a convertible *concatditi_? variant. X is known
454 : to be any_or_plus:TI, i.e. PLUS:TI, IOR:TI or XOR:TI. */
455 :
456 : static bool
457 31182 : timode_concatdi_p (rtx x)
458 : {
459 31182 : rtx op0 = XEXP (x, 0);
460 31182 : rtx op1 = XEXP (x, 1);
461 :
462 31182 : if (GET_CODE (op1) == ASHIFT)
463 953 : std::swap (op0, op1);
464 :
465 31182 : return GET_CODE (op0) == ASHIFT
466 21865 : && GET_CODE (XEXP (op0, 0)) == ZERO_EXTEND
467 21865 : && GET_MODE (XEXP (XEXP (op0, 0), 0)) == DImode
468 21865 : && REG_P (XEXP (XEXP (op0, 0), 0))
469 21714 : && CONST_INT_P (XEXP (op0, 1))
470 21714 : && INTVAL (XEXP (op0, 1)) == 64
471 21714 : && GET_CODE (op1) == ZERO_EXTEND
472 20761 : && GET_MODE (XEXP (op1, 0)) == DImode
473 51943 : && REG_P (XEXP (op1, 0));
474 : }
475 :
476 :
477 : /* Add instruction into a chain. Return true if OK, false if the search
478 : was aborted. */
479 :
480 : bool
481 13008531 : scalar_chain::add_insn (bitmap candidates, unsigned int insn_uid,
482 : bitmap disallowed)
483 : {
484 13008531 : if (!bitmap_set_bit (insns, insn_uid))
485 : return true;
486 :
487 13008531 : if (dump_file)
488 277 : fprintf (dump_file, " Adding insn %d to chain #%d\n", insn_uid, chain_id);
489 :
490 13008531 : rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
491 13008531 : rtx def_set = single_set (insn);
492 13008531 : if (def_set && REG_P (SET_DEST (def_set))
493 23022644 : && !HARD_REGISTER_P (SET_DEST (def_set)))
494 9988734 : bitmap_set_bit (defs, REGNO (SET_DEST (def_set)));
495 :
496 : /* ??? The following is quadratic since analyze_register_chain
497 : iterates over all refs to look for dual-mode regs. Instead this
498 : should be done separately for all regs mentioned in the chain once. */
499 13008531 : df_ref ref;
500 26562211 : for (ref = DF_INSN_UID_DEFS (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
501 13555292 : if (!HARD_REGISTER_P (DF_REF_REG (ref)))
502 9988734 : if (!analyze_register_chain (candidates, ref, disallowed))
503 : return false;
504 :
505 : /* The operand(s) of VEC_SELECT, ZERO_EXTEND and similar ops don't need
506 : to be converted/convertible. */
507 13006919 : if (def_set)
508 13006919 : switch (GET_CODE (SET_SRC (def_set)))
509 : {
510 3887559 : case REG:
511 3887559 : if (HARD_REGISTER_P (SET_SRC (def_set)))
512 : return true;
513 : break;
514 : case VEC_SELECT:
515 : return true;
516 9832 : case ZERO_EXTEND:
517 9832 : if (GET_MODE (XEXP (SET_SRC (def_set), 0)) == DImode)
518 : return true;
519 : break;
520 2426127 : case PLUS:
521 2426127 : case IOR:
522 2426127 : case XOR:
523 2426127 : if (smode == TImode && timode_concatdi_p (SET_SRC (def_set)))
524 : return true;
525 : break;
526 : default:
527 : break;
528 : }
529 :
530 28441379 : for (ref = DF_INSN_UID_USES (insn_uid); ref; ref = DF_REF_NEXT_LOC (ref))
531 15512286 : if (DF_REF_TYPE (ref) == DF_REF_REG_USE
532 8352181 : && !SUBREG_P (DF_REF_REG (ref)))
533 8352178 : if (!analyze_register_chain (candidates, ref, disallowed))
534 : return false;
535 :
536 : return true;
537 : }
538 :
539 : /* Build new chain starting from insn INSN_UID recursively
540 : adding all dependent uses and definitions. Return true if OK, false
541 : if the chain discovery was aborted. */
542 :
543 : bool
544 6608140 : scalar_chain::build (bitmap candidates, unsigned insn_uid, bitmap disallowed)
545 : {
546 6608140 : queue = BITMAP_ALLOC (NULL);
547 6608140 : bitmap_set_bit (queue, insn_uid);
548 :
549 6608140 : if (dump_file)
550 136 : fprintf (dump_file, "Building chain #%d...\n", chain_id);
551 :
552 19612306 : while (!bitmap_empty_p (queue))
553 : {
554 13008531 : insn_uid = bitmap_first_set_bit (queue);
555 13008531 : bitmap_clear_bit (queue, insn_uid);
556 13008531 : bitmap_clear_bit (candidates, insn_uid);
557 13008531 : if (!add_insn (candidates, insn_uid, disallowed))
558 : {
559 : /* If we aborted the search put sofar found insn on the set of
560 : disallowed insns so that further searches reaching them also
561 : abort and thus we abort the whole but yet undiscovered chain. */
562 4365 : bitmap_ior_into (disallowed, insns);
563 4365 : if (dump_file)
564 0 : fprintf (dump_file, "Aborted chain #%d discovery\n", chain_id);
565 4365 : BITMAP_FREE (queue);
566 4365 : return false;
567 : }
568 : }
569 :
570 6603775 : if (dump_file)
571 : {
572 136 : fprintf (dump_file, "Collected chain #%d...\n", chain_id);
573 136 : fprintf (dump_file, " insns: ");
574 136 : dump_bitmap (dump_file, insns);
575 136 : if (!bitmap_empty_p (defs_conv))
576 : {
577 136 : bitmap_iterator bi;
578 136 : unsigned id;
579 136 : const char *comma = "";
580 136 : fprintf (dump_file, " defs to convert: ");
581 366 : EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, id, bi)
582 : {
583 230 : fprintf (dump_file, "%sr%d", comma, id);
584 230 : comma = ", ";
585 : }
586 136 : fprintf (dump_file, "\n");
587 : }
588 : }
589 :
590 6603775 : BITMAP_FREE (queue);
591 :
592 6603775 : return true;
593 : }
594 :
595 : /* Return a cost of building a vector constant
596 : instead of using a scalar one. */
597 :
598 : int
599 2701498 : general_scalar_chain::vector_const_cost (rtx exp, basic_block bb)
600 : {
601 2701498 : gcc_assert (CONST_INT_P (exp));
602 :
603 2701498 : if (standard_sse_constant_p (exp, vmode))
604 611038 : return ix86_cost->sse_op;
605 2090460 : if (optimize_bb_for_size_p (bb))
606 : return COSTS_N_BYTES (8);
607 : /* We have separate costs for SImode and DImode, use SImode costs
608 : for smaller modes. */
609 2461557 : return COSTS_N_INSNS (ix86_cost->sse_load[smode == DImode ? 1 : 0]) / 2;
610 : }
611 :
612 : /* Return true if it's cost profitable for chain conversion. */
613 :
614 : bool
615 6076514 : general_scalar_chain::compute_convert_gain ()
616 : {
617 6076514 : bitmap_iterator bi;
618 6076514 : unsigned insn_uid;
619 6076514 : int gain = 0;
620 6076514 : sreal weighted_gain = 0;
621 :
622 6076514 : if (dump_file)
623 136 : fprintf (dump_file, "Computing gain for chain #%d...\n", chain_id);
624 :
625 : /* SSE costs distinguish between SImode and DImode loads/stores, for
626 : int costs factor in the number of GPRs involved. When supporting
627 : smaller modes than SImode the int load/store costs need to be
628 : adjusted as well. */
629 6076514 : unsigned sse_cost_idx = smode == DImode ? 1 : 0;
630 6076514 : int m = smode == DImode ? (TARGET_64BIT ? 1 : 2) : 1;
631 :
632 18013900 : EXECUTE_IF_SET_IN_BITMAP (insns, 0, insn_uid, bi)
633 : {
634 11937386 : rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
635 11937386 : rtx def_set = single_set (insn);
636 11937386 : rtx src = SET_SRC (def_set);
637 11937386 : rtx dst = SET_DEST (def_set);
638 11937386 : basic_block bb = BLOCK_FOR_INSN (insn);
639 11937386 : int igain = 0;
640 11937386 : profile_count entry_count = ENTRY_BLOCK_PTR_FOR_FN (cfun)->count;
641 11937386 : bool speed_p = optimize_bb_for_speed_p (bb);
642 11937386 : sreal bb_freq = bb->count.to_sreal_scale (entry_count);
643 :
644 11937386 : if (REG_P (src) && REG_P (dst))
645 : {
646 953743 : if (!speed_p)
647 : /* reg-reg move is 2 bytes, while SSE 3. */
648 203281 : igain += COSTS_N_BYTES (2 * m - 3);
649 : else
650 : /* Move costs are normalized to reg-reg move having cost 2. */
651 750462 : igain += COSTS_N_INSNS (2 * m - ix86_cost->xmm_move) / 2;
652 : }
653 10983643 : else if (REG_P (src) && MEM_P (dst))
654 : {
655 2384133 : if (!speed_p)
656 : /* Integer load/store is 3+ bytes and SSE 4+. */
657 201961 : igain += COSTS_N_BYTES (3 * m - 4);
658 : else
659 2182172 : igain
660 2182172 : += COSTS_N_INSNS (m * ix86_cost->int_store[2]
661 : - ix86_cost->sse_store[sse_cost_idx]) / 2;
662 : }
663 8599510 : else if (MEM_P (src) && REG_P (dst))
664 : {
665 3853221 : if (!speed_p)
666 362704 : igain += COSTS_N_BYTES (3 * m - 4);
667 : else
668 3490517 : igain += COSTS_N_INSNS (m * ix86_cost->int_load[2]
669 : - ix86_cost->sse_load[sse_cost_idx]) / 2;
670 : }
671 : else
672 : {
673 : /* For operations on memory operands, include the overhead
674 : of explicit load and store instructions. */
675 4746289 : if (MEM_P (dst))
676 : {
677 71886 : if (!speed_p)
678 : /* ??? This probably should account size difference
679 : of SSE and integer load rather than full SSE load. */
680 : igain -= COSTS_N_BYTES (8);
681 : else
682 : {
683 62195 : int cost = (m * (ix86_cost->int_load[2]
684 62195 : + ix86_cost->int_store[2])
685 62195 : - (ix86_cost->sse_load[sse_cost_idx] +
686 62195 : ix86_cost->sse_store[sse_cost_idx]));
687 62195 : igain += COSTS_N_INSNS (cost) / 2;
688 : }
689 : }
690 :
691 4746289 : switch (GET_CODE (src))
692 : {
693 490732 : case ASHIFT:
694 490732 : case ASHIFTRT:
695 490732 : case LSHIFTRT:
696 490732 : if (m == 2)
697 : {
698 17991 : if (INTVAL (XEXP (src, 1)) >= 32)
699 12399 : igain += ix86_cost->add;
700 : /* Gain for extend highpart case. */
701 5592 : else if (GET_CODE (XEXP (src, 0)) == ASHIFT)
702 0 : igain += ix86_cost->shift_const - ix86_cost->sse_op;
703 : else
704 5592 : igain += ix86_cost->shift_const;
705 : }
706 :
707 490732 : igain += ix86_cost->shift_const - ix86_cost->sse_op;
708 :
709 490732 : if (CONST_INT_P (XEXP (src, 0)))
710 0 : igain -= vector_const_cost (XEXP (src, 0), bb);
711 : break;
712 :
713 3935 : case ROTATE:
714 3935 : case ROTATERT:
715 3935 : igain += m * ix86_cost->shift_const;
716 3935 : if (TARGET_AVX512VL)
717 204 : igain -= ix86_cost->sse_op;
718 3731 : else if (smode == DImode)
719 : {
720 791 : int bits = INTVAL (XEXP (src, 1));
721 791 : if ((bits & 0x0f) == 0)
722 186 : igain -= ix86_cost->sse_op;
723 605 : else if ((bits & 0x07) == 0)
724 31 : igain -= 2 * ix86_cost->sse_op;
725 : else
726 574 : igain -= 3 * ix86_cost->sse_op;
727 : }
728 2940 : else if (INTVAL (XEXP (src, 1)) == 16)
729 139 : igain -= ix86_cost->sse_op;
730 : else
731 2801 : igain -= 2 * ix86_cost->sse_op;
732 : break;
733 :
734 2923901 : case AND:
735 2923901 : case IOR:
736 2923901 : case XOR:
737 2923901 : case PLUS:
738 2923901 : case MINUS:
739 2923901 : igain += m * ix86_cost->add - ix86_cost->sse_op;
740 : /* Additional gain for andnot for targets without BMI. */
741 2923901 : if (GET_CODE (XEXP (src, 0)) == NOT
742 3143 : && !TARGET_BMI)
743 3134 : igain += m * ix86_cost->add;
744 :
745 2923901 : if (CONST_INT_P (XEXP (src, 0)))
746 0 : igain -= vector_const_cost (XEXP (src, 0), bb);
747 2923901 : if (CONST_INT_P (XEXP (src, 1)))
748 1730626 : igain -= vector_const_cost (XEXP (src, 1), bb);
749 2923901 : if (MEM_P (XEXP (src, 1)))
750 : {
751 100768 : if (!speed_p)
752 23496 : igain -= COSTS_N_BYTES (m == 2 ? 3 : 5);
753 : else
754 89015 : igain += COSTS_N_INSNS
755 : (m * ix86_cost->int_load[2]
756 : - ix86_cost->sse_load[sse_cost_idx]) / 2;
757 : }
758 : break;
759 :
760 59044 : case NEG:
761 59044 : case NOT:
762 59044 : igain -= ix86_cost->sse_op + COSTS_N_INSNS (1);
763 :
764 59044 : if (GET_CODE (XEXP (src, 0)) != ABS)
765 : {
766 59044 : igain += m * ix86_cost->add;
767 59044 : break;
768 : }
769 : /* FALLTHRU */
770 :
771 976 : case ABS:
772 976 : case SMAX:
773 976 : case SMIN:
774 976 : case UMAX:
775 976 : case UMIN:
776 : /* We do not have any conditional move cost, estimate it as a
777 : reg-reg move. Comparisons are costed as adds. */
778 976 : igain += m * (COSTS_N_INSNS (2) + ix86_cost->add);
779 : /* Integer SSE ops are all costed the same. */
780 976 : igain -= ix86_cost->sse_op;
781 976 : break;
782 :
783 0 : case COMPARE:
784 0 : if (XEXP (src, 1) != const0_rtx)
785 : {
786 : /* cmp vs. pxor;pshufd;ptest. */
787 0 : igain += COSTS_N_INSNS (m - 3);
788 : }
789 0 : else if (GET_CODE (XEXP (src, 0)) != AND)
790 : {
791 : /* test vs. pshufd;ptest. */
792 0 : igain += COSTS_N_INSNS (m - 2);
793 : }
794 0 : else if (GET_CODE (XEXP (XEXP (src, 0), 0)) != NOT)
795 : {
796 : /* and;test vs. pshufd;ptest. */
797 0 : igain += COSTS_N_INSNS (2 * m - 2);
798 : }
799 0 : else if (TARGET_BMI)
800 : {
801 : /* andn;test vs. pandn;pshufd;ptest. */
802 0 : igain += COSTS_N_INSNS (2 * m - 3);
803 : }
804 : else
805 : {
806 : /* not;and;test vs. pandn;pshufd;ptest. */
807 0 : igain += COSTS_N_INSNS (3 * m - 3);
808 : }
809 : break;
810 :
811 1212703 : case CONST_INT:
812 1212703 : if (REG_P (dst))
813 : {
814 1212703 : if (!speed_p)
815 : {
816 : /* xor (2 bytes) vs. xorps (3 bytes). */
817 241831 : if (src == const0_rtx)
818 127080 : igain -= COSTS_N_BYTES (1);
819 : /* movdi_internal vs. movv2di_internal. */
820 : /* => mov (5 bytes) vs. movaps (7 bytes). */
821 114751 : else if (x86_64_immediate_operand (src, SImode))
822 102508 : igain -= COSTS_N_BYTES (2);
823 : else
824 : /* ??? Larger immediate constants are placed in the
825 : constant pool, where the size benefit/impact of
826 : STV conversion is affected by whether and how
827 : often each constant pool entry is shared/reused.
828 : The value below is empirically derived from the
829 : CSiBE benchmark (and the optimal value may drift
830 : over time). */
831 : igain += COSTS_N_BYTES (0);
832 : }
833 : else
834 : {
835 : /* DImode can be immediate for TARGET_64BIT
836 : and SImode always. */
837 970872 : igain += m * COSTS_N_INSNS (1);
838 970872 : igain -= vector_const_cost (src, bb);
839 : }
840 : }
841 0 : else if (MEM_P (dst))
842 : {
843 0 : igain += (m * ix86_cost->int_store[2]
844 0 : - ix86_cost->sse_store[sse_cost_idx]);
845 0 : igain -= vector_const_cost (src, bb);
846 : }
847 : break;
848 :
849 45435 : case VEC_SELECT:
850 45435 : if (XVECEXP (XEXP (src, 1), 0, 0) == const0_rtx)
851 : {
852 : // movd (4 bytes) replaced with movdqa (4 bytes).
853 33139 : if (!!speed_p)
854 30455 : igain += COSTS_N_INSNS (ix86_cost->sse_to_integer
855 : - ix86_cost->xmm_move) / 2;
856 : }
857 : else
858 : {
859 : // pshufd; movd replaced with pshufd.
860 12296 : if (!speed_p)
861 1620 : igain += COSTS_N_BYTES (4);
862 : else
863 10676 : igain += ix86_cost->sse_to_integer;
864 : }
865 : break;
866 :
867 9563 : case ZERO_EXTEND:
868 : /* mov eax (6 bytes) vs movd xmm0 (8 bytes). */
869 : /* mov eax; xor edx,edx (7 bytes). */
870 9563 : if (speed_p)
871 8699 : igain += COSTS_N_INSNS (ix86_cost->int_load[2]
872 : - ix86_cost->sse_load[0]) / 2;
873 : else
874 910 : igain += COSTS_N_BYTES (TARGET_64BIT ? -2 : -1);
875 : break;
876 :
877 0 : default:
878 0 : gcc_unreachable ();
879 : }
880 : }
881 :
882 11934702 : if (speed_p)
883 10614322 : weighted_gain += bb_freq * igain;
884 11937386 : gain += igain;
885 :
886 11937386 : if (igain != 0 && dump_file)
887 : {
888 93 : fprintf (dump_file, " Instruction gain %d with bb_freq %.2f for",
889 : igain, bb_freq.to_double ());
890 93 : dump_insn_slim (dump_file, insn);
891 : }
892 : }
893 :
894 6076514 : if (dump_file)
895 : {
896 136 : fprintf (dump_file, " Instruction conversion gain: %d, \n",
897 : gain);
898 136 : fprintf (dump_file, " Registers conversion cost: %d\n",
899 : cost_sse_integer);
900 136 : fprintf (dump_file, " Weighted instruction conversion gain: %.2f, \n",
901 : weighted_gain.to_double ());
902 136 : fprintf (dump_file, " Weighted registers conversion cost: %.2f\n",
903 : weighted_cost_sse_integer.to_double ());
904 : }
905 :
906 6076514 : if (weighted_gain != weighted_cost_sse_integer)
907 4898531 : return weighted_gain > weighted_cost_sse_integer;
908 : else
909 1177983 : return gain > cost_sse_integer;;
910 : }
911 :
912 : /* Insert generated conversion instruction sequence INSNS
913 : after instruction AFTER. New BB may be required in case
914 : instruction has EH region attached. */
915 :
916 : void
917 33556 : scalar_chain::emit_conversion_insns (rtx insns, rtx_insn *after)
918 : {
919 33556 : if (!control_flow_insn_p (after))
920 : {
921 33345 : emit_insn_after (insns, after);
922 33345 : return;
923 : }
924 :
925 211 : basic_block bb = BLOCK_FOR_INSN (after);
926 211 : edge e = find_fallthru_edge (bb->succs);
927 211 : gcc_assert (e);
928 :
929 211 : basic_block new_bb = split_edge (e);
930 211 : emit_insn_after (insns, BB_HEAD (new_bb));
931 : }
932 :
933 : } // anon namespace
934 :
935 : /* Generate the canonical SET_SRC to move GPR to a VMODE vector register,
936 : zeroing the upper parts. */
937 :
938 : static rtx
939 176162 : gen_gpr_to_xmm_move_src (enum machine_mode vmode, rtx gpr)
940 : {
941 352324 : switch (GET_MODE_NUNITS (vmode))
942 : {
943 71 : case 1:
944 71 : return gen_rtx_SUBREG (vmode, gpr, 0);
945 175608 : case 2:
946 351216 : return gen_rtx_VEC_CONCAT (vmode, gpr,
947 : CONST0_RTX (GET_MODE_INNER (vmode)));
948 483 : default:
949 483 : return gen_rtx_VEC_MERGE (vmode, gen_rtx_VEC_DUPLICATE (vmode, gpr),
950 : CONST0_RTX (vmode), GEN_INT (HOST_WIDE_INT_1U));
951 : }
952 : }
953 :
954 : /* Make vector copies for all register REGNO definitions
955 : and replace its uses in a chain. */
956 :
957 : void
958 9096 : scalar_chain::make_vector_copies (rtx_insn *insn, rtx reg)
959 : {
960 9096 : rtx vreg = *defs_map.get (reg);
961 :
962 9096 : start_sequence ();
963 9096 : if (!TARGET_INTER_UNIT_MOVES_TO_VEC)
964 : {
965 0 : rtx tmp = assign_386_stack_local (smode, SLOT_STV_TEMP);
966 0 : if (smode == DImode && !TARGET_64BIT)
967 : {
968 0 : emit_move_insn (adjust_address (tmp, SImode, 0),
969 : gen_rtx_SUBREG (SImode, reg, 0));
970 0 : emit_move_insn (adjust_address (tmp, SImode, 4),
971 : gen_rtx_SUBREG (SImode, reg, 4));
972 : }
973 : else
974 0 : emit_move_insn (copy_rtx (tmp), reg);
975 0 : emit_insn (gen_rtx_SET (gen_rtx_SUBREG (vmode, vreg, 0),
976 : gen_gpr_to_xmm_move_src (vmode, tmp)));
977 : }
978 9096 : else if (!TARGET_64BIT && smode == DImode)
979 : {
980 8917 : if (TARGET_SSE4_1)
981 : {
982 356 : emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, vreg, 0),
983 : CONST0_RTX (V4SImode),
984 : gen_rtx_SUBREG (SImode, reg, 0)));
985 356 : emit_insn (gen_sse4_1_pinsrd (gen_rtx_SUBREG (V4SImode, vreg, 0),
986 : gen_rtx_SUBREG (V4SImode, vreg, 0),
987 : gen_rtx_SUBREG (SImode, reg, 4),
988 : GEN_INT (2)));
989 : }
990 : else
991 : {
992 8561 : rtx tmp = gen_reg_rtx (DImode);
993 8561 : emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, vreg, 0),
994 : CONST0_RTX (V4SImode),
995 : gen_rtx_SUBREG (SImode, reg, 0)));
996 8561 : emit_insn (gen_sse2_loadld (gen_rtx_SUBREG (V4SImode, tmp, 0),
997 : CONST0_RTX (V4SImode),
998 : gen_rtx_SUBREG (SImode, reg, 4)));
999 8561 : emit_insn (gen_vec_interleave_lowv4si
1000 : (gen_rtx_SUBREG (V4SImode, vreg, 0),
1001 : gen_rtx_SUBREG (V4SImode, vreg, 0),
1002 : gen_rtx_SUBREG (V4SImode, tmp, 0)));
1003 : }
1004 : }
1005 : else
1006 179 : emit_insn (gen_rtx_SET (gen_rtx_SUBREG (vmode, vreg, 0),
1007 : gen_gpr_to_xmm_move_src (vmode, reg)));
1008 9096 : rtx_insn *seq = end_sequence ();
1009 9096 : emit_conversion_insns (seq, insn);
1010 :
1011 9096 : if (dump_file)
1012 0 : fprintf (dump_file,
1013 : " Copied r%d to a vector register r%d for insn %d\n",
1014 0 : REGNO (reg), REGNO (vreg), INSN_UID (insn));
1015 9096 : }
1016 :
1017 : /* Copy the definition SRC of INSN inside the chain to DST for
1018 : scalar uses outside of the chain. */
1019 :
1020 : void
1021 23675 : scalar_chain::convert_reg (rtx_insn *insn, rtx dst, rtx src)
1022 : {
1023 23675 : start_sequence ();
1024 23675 : if (!TARGET_INTER_UNIT_MOVES_FROM_VEC)
1025 : {
1026 0 : rtx tmp = assign_386_stack_local (smode, SLOT_STV_TEMP);
1027 0 : emit_move_insn (tmp, src);
1028 0 : if (!TARGET_64BIT && smode == DImode)
1029 : {
1030 0 : emit_move_insn (gen_rtx_SUBREG (SImode, dst, 0),
1031 : adjust_address (tmp, SImode, 0));
1032 0 : emit_move_insn (gen_rtx_SUBREG (SImode, dst, 4),
1033 : adjust_address (tmp, SImode, 4));
1034 : }
1035 : else
1036 0 : emit_move_insn (dst, copy_rtx (tmp));
1037 : }
1038 23675 : else if (!TARGET_64BIT && smode == DImode)
1039 : {
1040 22569 : if (TARGET_SSE4_1)
1041 : {
1042 0 : rtx tmp = gen_rtx_PARALLEL (VOIDmode,
1043 : gen_rtvec (1, const0_rtx));
1044 0 : emit_insn
1045 0 : (gen_rtx_SET
1046 : (gen_rtx_SUBREG (SImode, dst, 0),
1047 : gen_rtx_VEC_SELECT (SImode,
1048 : gen_rtx_SUBREG (V4SImode, src, 0),
1049 : tmp)));
1050 :
1051 0 : tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const1_rtx));
1052 0 : emit_insn
1053 0 : (gen_rtx_SET
1054 : (gen_rtx_SUBREG (SImode, dst, 4),
1055 : gen_rtx_VEC_SELECT (SImode,
1056 : gen_rtx_SUBREG (V4SImode, src, 0),
1057 : tmp)));
1058 : }
1059 : else
1060 : {
1061 22569 : rtx vcopy = gen_reg_rtx (V2DImode);
1062 22569 : emit_move_insn (vcopy, gen_rtx_SUBREG (V2DImode, src, 0));
1063 22569 : emit_move_insn (gen_rtx_SUBREG (SImode, dst, 0),
1064 : gen_rtx_SUBREG (SImode, vcopy, 0));
1065 22569 : emit_move_insn (vcopy,
1066 : gen_rtx_LSHIFTRT (V2DImode,
1067 : vcopy, GEN_INT (32)));
1068 22569 : emit_move_insn (gen_rtx_SUBREG (SImode, dst, 4),
1069 : gen_rtx_SUBREG (SImode, vcopy, 0));
1070 : }
1071 : }
1072 : else
1073 1106 : emit_move_insn (dst, src);
1074 :
1075 23675 : rtx_insn *seq = end_sequence ();
1076 23675 : emit_conversion_insns (seq, insn);
1077 :
1078 23675 : if (dump_file)
1079 0 : fprintf (dump_file,
1080 : " Copied r%d to a scalar register r%d for insn %d\n",
1081 0 : REGNO (src), REGNO (dst), INSN_UID (insn));
1082 23675 : }
1083 :
1084 : /* Helper function to convert immediate constant X to vmode. */
1085 : static rtx
1086 37898 : smode_convert_cst (rtx x, enum machine_mode vmode)
1087 : {
1088 : /* Prefer all ones vector in case of -1. */
1089 37898 : if (constm1_operand (x, GET_MODE (x)))
1090 635 : return CONSTM1_RTX (vmode);
1091 :
1092 37263 : unsigned n = GET_MODE_NUNITS (vmode);
1093 37263 : rtx *v = XALLOCAVEC (rtx, n);
1094 37263 : v[0] = x;
1095 43494 : for (unsigned i = 1; i < n; ++i)
1096 6231 : v[i] = const0_rtx;
1097 37263 : return gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (n, v));
1098 : }
1099 :
1100 : /* Convert operand OP in INSN. We should handle
1101 : memory operands and uninitialized registers.
1102 : All other register uses are converted during
1103 : registers conversion. */
1104 :
1105 : void
1106 243581 : scalar_chain::convert_op (rtx *op, rtx_insn *insn)
1107 : {
1108 243581 : rtx tmp;
1109 :
1110 243581 : if (GET_MODE (*op) == V1TImode)
1111 : return;
1112 :
1113 243326 : *op = copy_rtx_if_shared (*op);
1114 :
1115 243326 : if (GET_CODE (*op) == NOT
1116 243326 : || GET_CODE (*op) == ASHIFT)
1117 : {
1118 2890 : convert_op (&XEXP (*op, 0), insn);
1119 2890 : PUT_MODE (*op, vmode);
1120 : }
1121 : else if (MEM_P (*op))
1122 : {
1123 175983 : rtx_insn *movabs = NULL;
1124 :
1125 : /* Emit MOVABS to load from a 64-bit absolute address to a GPR. */
1126 175983 : if (!memory_operand (*op, GET_MODE (*op)))
1127 : {
1128 0 : tmp = gen_reg_rtx (GET_MODE (*op));
1129 0 : movabs = emit_insn_before (gen_rtx_SET (tmp, *op), insn);
1130 :
1131 0 : *op = tmp;
1132 : }
1133 :
1134 175983 : tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (GET_MODE (*op)), 0);
1135 :
1136 175983 : rtx_insn *eh_insn
1137 175983 : = emit_insn_before (gen_rtx_SET (copy_rtx (tmp),
1138 : gen_gpr_to_xmm_move_src (vmode, *op)),
1139 175983 : insn);
1140 :
1141 175983 : if (cfun->can_throw_non_call_exceptions)
1142 : {
1143 : /* Handle REG_EH_REGION note. */
1144 168517 : rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
1145 168517 : if (note)
1146 : {
1147 3587 : if (movabs)
1148 0 : eh_insn = movabs;
1149 3587 : control_flow_insns.safe_push (eh_insn);
1150 3587 : add_reg_note (eh_insn, REG_EH_REGION, XEXP (note, 0));
1151 : }
1152 : }
1153 :
1154 175983 : *op = tmp;
1155 :
1156 175983 : if (dump_file)
1157 0 : fprintf (dump_file, " Preloading operand for insn %d into r%d\n",
1158 0 : INSN_UID (insn), reg_or_subregno (tmp));
1159 : }
1160 : else if (REG_P (*op))
1161 57807 : *op = gen_rtx_SUBREG (vmode, *op, 0);
1162 : else if (CONST_SCALAR_INT_P (*op))
1163 : {
1164 6643 : rtx vec_cst = smode_convert_cst (*op, vmode);
1165 :
1166 6643 : if (!standard_sse_constant_p (vec_cst, vmode))
1167 : {
1168 2661 : start_sequence ();
1169 2661 : vec_cst = validize_mem (force_const_mem (vmode, vec_cst));
1170 2661 : rtx_insn *seq = end_sequence ();
1171 2661 : emit_insn_before (seq, insn);
1172 : }
1173 :
1174 6643 : tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (smode), 0);
1175 :
1176 6643 : emit_insn_before (gen_move_insn (copy_rtx (tmp), vec_cst), insn);
1177 6643 : *op = tmp;
1178 : }
1179 : else
1180 : {
1181 0 : gcc_assert (SUBREG_P (*op));
1182 3 : if (GET_MODE (*op) != vmode)
1183 : {
1184 3 : rtx inner = SUBREG_REG (*op);
1185 3 : poly_uint64 byte = SUBREG_BYTE (*op);
1186 3 : if (targetm.modes_tieable_p (vmode, GET_MODE (inner))
1187 3 : && validate_subreg (vmode, GET_MODE (inner), inner, byte))
1188 3 : *op = gen_lowpart (vmode, *op);
1189 : else
1190 : {
1191 0 : tmp = gen_reg_rtx (GET_MODE (*op));
1192 0 : emit_insn_before (gen_rtx_SET (tmp, *op), insn);
1193 0 : *op = gen_rtx_SUBREG (vmode, tmp, 0);
1194 : }
1195 : }
1196 : }
1197 : }
1198 :
1199 : /* Convert CCZmode COMPARE to vector mode. */
1200 :
1201 : rtx
1202 12 : scalar_chain::convert_compare (rtx op1, rtx op2, rtx_insn *insn)
1203 : {
1204 12 : rtx src, tmp;
1205 :
1206 : /* Handle any REG_EQUAL notes. */
1207 12 : tmp = find_reg_equal_equiv_note (insn);
1208 12 : if (tmp)
1209 : {
1210 1 : if (GET_CODE (XEXP (tmp, 0)) == COMPARE
1211 1 : && GET_MODE (XEXP (tmp, 0)) == CCZmode
1212 1 : && REG_P (XEXP (XEXP (tmp, 0), 0)))
1213 : {
1214 1 : rtx *op = &XEXP (XEXP (tmp, 0), 1);
1215 1 : if (CONST_SCALAR_INT_P (*op))
1216 : {
1217 1 : if (constm1_operand (*op, GET_MODE (*op)))
1218 0 : *op = CONSTM1_RTX (vmode);
1219 : else
1220 : {
1221 1 : unsigned n = GET_MODE_NUNITS (vmode);
1222 1 : rtx *v = XALLOCAVEC (rtx, n);
1223 1 : v[0] = *op;
1224 1 : for (unsigned i = 1; i < n; ++i)
1225 0 : v[i] = const0_rtx;
1226 1 : *op = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (n, v));
1227 : }
1228 : tmp = NULL_RTX;
1229 : }
1230 0 : else if (REG_P (*op))
1231 : tmp = NULL_RTX;
1232 : }
1233 :
1234 1 : if (tmp)
1235 0 : remove_note (insn, tmp);
1236 : }
1237 :
1238 : /* Comparison against anything other than zero, requires an XOR. */
1239 12 : if (op2 != const0_rtx)
1240 : {
1241 6 : convert_op (&op1, insn);
1242 6 : convert_op (&op2, insn);
1243 : /* If both operands are MEMs, explicitly load the OP1 into TMP. */
1244 6 : if (MEM_P (op1) && MEM_P (op2))
1245 : {
1246 0 : tmp = gen_reg_rtx (vmode);
1247 0 : emit_insn_before (gen_rtx_SET (tmp, op1), insn);
1248 0 : src = tmp;
1249 : }
1250 : else
1251 : src = op1;
1252 6 : src = gen_rtx_XOR (vmode, src, op2);
1253 : }
1254 6 : else if (GET_CODE (op1) == AND
1255 0 : && GET_CODE (XEXP (op1, 0)) == NOT)
1256 : {
1257 0 : rtx op11 = XEXP (XEXP (op1, 0), 0);
1258 0 : rtx op12 = XEXP (op1, 1);
1259 0 : convert_op (&op11, insn);
1260 0 : convert_op (&op12, insn);
1261 0 : if (!REG_P (op11))
1262 : {
1263 0 : tmp = gen_reg_rtx (vmode);
1264 0 : emit_insn_before (gen_rtx_SET (tmp, op11), insn);
1265 0 : op11 = tmp;
1266 : }
1267 0 : src = gen_rtx_AND (vmode, gen_rtx_NOT (vmode, op11), op12);
1268 0 : }
1269 6 : else if (GET_CODE (op1) == AND)
1270 : {
1271 0 : rtx op11 = XEXP (op1, 0);
1272 0 : rtx op12 = XEXP (op1, 1);
1273 0 : convert_op (&op11, insn);
1274 0 : convert_op (&op12, insn);
1275 0 : if (!REG_P (op11))
1276 : {
1277 0 : tmp = gen_reg_rtx (vmode);
1278 0 : emit_insn_before (gen_rtx_SET (tmp, op11), insn);
1279 0 : op11 = tmp;
1280 : }
1281 0 : return gen_rtx_UNSPEC (CCZmode, gen_rtvec (2, op11, op12),
1282 : UNSPEC_PTEST);
1283 : }
1284 : else
1285 : {
1286 6 : convert_op (&op1, insn);
1287 6 : src = op1;
1288 : }
1289 :
1290 12 : if (!REG_P (src))
1291 : {
1292 8 : tmp = gen_reg_rtx (vmode);
1293 8 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
1294 8 : src = tmp;
1295 : }
1296 :
1297 12 : if (vmode == V2DImode)
1298 : {
1299 0 : tmp = gen_reg_rtx (vmode);
1300 0 : emit_insn_before (gen_vec_interleave_lowv2di (tmp, src, src), insn);
1301 0 : src = tmp;
1302 : }
1303 12 : else if (vmode == V4SImode)
1304 : {
1305 0 : tmp = gen_reg_rtx (vmode);
1306 0 : emit_insn_before (gen_sse2_pshufd (tmp, src, const0_rtx), insn);
1307 0 : src = tmp;
1308 : }
1309 :
1310 12 : return gen_rtx_UNSPEC (CCZmode, gen_rtvec (2, src, src), UNSPEC_PTEST);
1311 : }
1312 :
1313 : /* Helper function for converting INSN to vector mode. */
1314 :
1315 : void
1316 1372553 : scalar_chain::convert_insn_common (rtx_insn *insn)
1317 : {
1318 : /* Generate copies for out-of-chain uses of defs and adjust debug uses. */
1319 2096182 : for (df_ref ref = DF_INSN_DEFS (insn); ref; ref = DF_REF_NEXT_LOC (ref))
1320 723629 : if (bitmap_bit_p (defs_conv, DF_REF_REGNO (ref)))
1321 : {
1322 25152 : df_link *use;
1323 50302 : for (use = DF_REF_CHAIN (ref); use; use = use->next)
1324 48825 : if (NONDEBUG_INSN_P (DF_REF_INSN (use->ref))
1325 48825 : && (DF_REF_REG_MEM_P (use->ref)
1326 42228 : || !bitmap_bit_p (insns, DF_REF_INSN_UID (use->ref))))
1327 : break;
1328 25152 : if (use)
1329 23675 : convert_reg (insn, DF_REF_REG (ref),
1330 23675 : *defs_map.get (regno_reg_rtx [DF_REF_REGNO (ref)]));
1331 1477 : else if (MAY_HAVE_DEBUG_BIND_INSNS)
1332 : {
1333 : /* If we generated a scalar copy we can leave debug-insns
1334 : as-is, if not, we have to adjust them. */
1335 1367 : auto_vec<rtx_insn *, 5> to_reset_debug_insns;
1336 4205 : for (use = DF_REF_CHAIN (ref); use; use = use->next)
1337 2838 : if (DEBUG_INSN_P (DF_REF_INSN (use->ref)))
1338 : {
1339 872 : rtx_insn *debug_insn = DF_REF_INSN (use->ref);
1340 : /* If there's a reaching definition outside of the
1341 : chain we have to reset. */
1342 872 : df_link *def;
1343 3063 : for (def = DF_REF_CHAIN (use->ref); def; def = def->next)
1344 2364 : if (!bitmap_bit_p (insns, DF_REF_INSN_UID (def->ref)))
1345 : break;
1346 872 : if (def)
1347 173 : to_reset_debug_insns.safe_push (debug_insn);
1348 : else
1349 : {
1350 699 : *DF_REF_REAL_LOC (use->ref)
1351 699 : = *defs_map.get (regno_reg_rtx [DF_REF_REGNO (ref)]);
1352 699 : df_insn_rescan (debug_insn);
1353 : }
1354 : }
1355 : /* Have to do the reset outside of the DF_CHAIN walk to not
1356 : disrupt it. */
1357 2907 : while (!to_reset_debug_insns.is_empty ())
1358 : {
1359 173 : rtx_insn *debug_insn = to_reset_debug_insns.pop ();
1360 173 : INSN_VAR_LOCATION_LOC (debug_insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1361 173 : df_insn_rescan_debug_internal (debug_insn);
1362 : }
1363 1367 : }
1364 : }
1365 :
1366 : /* Replace uses in this insn with the defs we use in the chain. */
1367 3419004 : for (df_ref ref = DF_INSN_USES (insn); ref; ref = DF_REF_NEXT_LOC (ref))
1368 2046451 : if (!DF_REF_REG_MEM_P (ref))
1369 731671 : if (rtx *vreg = defs_map.get (regno_reg_rtx[DF_REF_REGNO (ref)]))
1370 : {
1371 : /* Also update a corresponding REG_DEAD note. */
1372 36131 : rtx note = find_reg_note (insn, REG_DEAD, DF_REF_REG (ref));
1373 36131 : if (note)
1374 23001 : XEXP (note, 0) = *vreg;
1375 36131 : *DF_REF_REAL_LOC (ref) = *vreg;
1376 : }
1377 1372553 : }
1378 :
1379 : /* Convert INSN which is an SImode or DImode rotation by a constant
1380 : to vector mode. CODE is either ROTATE or ROTATERT with operands
1381 : OP0 and OP1. Returns the SET_SRC of the last instruction in the
1382 : resulting sequence, which is emitted before INSN. */
1383 :
1384 : rtx
1385 92 : general_scalar_chain::convert_rotate (enum rtx_code code, rtx op0, rtx op1,
1386 : rtx_insn *insn)
1387 : {
1388 92 : int bits = INTVAL (op1);
1389 92 : rtx pat, result;
1390 :
1391 92 : convert_op (&op0, insn);
1392 92 : if (bits == 0)
1393 0 : return op0;
1394 :
1395 92 : if (smode == DImode)
1396 : {
1397 92 : if (code == ROTATE)
1398 45 : bits = 64 - bits;
1399 92 : if (bits == 32)
1400 : {
1401 0 : rtx tmp1 = gen_reg_rtx (V4SImode);
1402 0 : pat = gen_sse2_pshufd (tmp1, gen_lowpart (V4SImode, op0),
1403 : GEN_INT (225));
1404 0 : emit_insn_before (pat, insn);
1405 0 : result = gen_lowpart (V2DImode, tmp1);
1406 : }
1407 92 : else if (TARGET_AVX512VL)
1408 0 : result = simplify_gen_binary (code, V2DImode, op0, op1);
1409 92 : else if (bits == 16 || bits == 48)
1410 : {
1411 0 : rtx tmp1 = gen_reg_rtx (V8HImode);
1412 0 : pat = gen_sse2_pshuflw (tmp1, gen_lowpart (V8HImode, op0),
1413 : GEN_INT (bits == 16 ? 57 : 147));
1414 0 : emit_insn_before (pat, insn);
1415 0 : result = gen_lowpart (V2DImode, tmp1);
1416 : }
1417 92 : else if ((bits & 0x07) == 0)
1418 : {
1419 0 : rtx tmp1 = gen_reg_rtx (V4SImode);
1420 0 : pat = gen_sse2_pshufd (tmp1, gen_lowpart (V4SImode, op0),
1421 : GEN_INT (68));
1422 0 : emit_insn_before (pat, insn);
1423 0 : rtx tmp2 = gen_reg_rtx (V1TImode);
1424 0 : pat = gen_sse2_lshrv1ti3 (tmp2, gen_lowpart (V1TImode, tmp1),
1425 : GEN_INT (bits));
1426 0 : emit_insn_before (pat, insn);
1427 0 : result = gen_lowpart (V2DImode, tmp2);
1428 : }
1429 : else
1430 : {
1431 92 : rtx tmp1 = gen_reg_rtx (V4SImode);
1432 92 : pat = gen_sse2_pshufd (tmp1, gen_lowpart (V4SImode, op0),
1433 : GEN_INT (20));
1434 92 : emit_insn_before (pat, insn);
1435 92 : rtx tmp2 = gen_reg_rtx (V2DImode);
1436 92 : pat = gen_lshrv2di3 (tmp2, gen_lowpart (V2DImode, tmp1),
1437 : GEN_INT (bits & 31));
1438 92 : emit_insn_before (pat, insn);
1439 92 : rtx tmp3 = gen_reg_rtx (V4SImode);
1440 139 : pat = gen_sse2_pshufd (tmp3, gen_lowpart (V4SImode, tmp2),
1441 : GEN_INT (bits > 32 ? 34 : 136));
1442 92 : emit_insn_before (pat, insn);
1443 92 : result = gen_lowpart (V2DImode, tmp3);
1444 : }
1445 : }
1446 0 : else if (bits == 16)
1447 : {
1448 0 : rtx tmp1 = gen_reg_rtx (V8HImode);
1449 0 : pat = gen_sse2_pshuflw (tmp1, gen_lowpart (V8HImode, op0), GEN_INT (225));
1450 0 : emit_insn_before (pat, insn);
1451 0 : result = gen_lowpart (V4SImode, tmp1);
1452 : }
1453 0 : else if (TARGET_AVX512VL)
1454 0 : result = simplify_gen_binary (code, V4SImode, op0, op1);
1455 : else
1456 : {
1457 0 : if (code == ROTATE)
1458 0 : bits = 32 - bits;
1459 :
1460 0 : rtx tmp1 = gen_reg_rtx (V4SImode);
1461 0 : emit_insn_before (gen_sse2_pshufd (tmp1, op0, GEN_INT (224)), insn);
1462 0 : rtx tmp2 = gen_reg_rtx (V2DImode);
1463 0 : pat = gen_lshrv2di3 (tmp2, gen_lowpart (V2DImode, tmp1),
1464 : GEN_INT (bits));
1465 0 : emit_insn_before (pat, insn);
1466 0 : result = gen_lowpart (V4SImode, tmp2);
1467 : }
1468 :
1469 : return result;
1470 : }
1471 :
1472 : /* Convert INSN to vector mode. */
1473 :
1474 : void
1475 413046 : general_scalar_chain::convert_insn (rtx_insn *insn)
1476 : {
1477 413046 : rtx def_set = single_set (insn);
1478 413046 : rtx src = SET_SRC (def_set);
1479 413046 : rtx dst = SET_DEST (def_set);
1480 413046 : rtx subreg;
1481 :
1482 413046 : if (MEM_P (dst) && !REG_P (src))
1483 : {
1484 : /* There are no scalar integer instructions and therefore
1485 : temporary register usage is required. */
1486 785 : rtx tmp = gen_reg_rtx (smode);
1487 785 : emit_conversion_insns (gen_move_insn (dst, tmp), insn);
1488 785 : dst = gen_rtx_SUBREG (vmode, tmp, 0);
1489 785 : }
1490 412261 : else if (REG_P (dst) && GET_MODE (dst) == smode)
1491 : {
1492 : /* Replace the definition with a SUBREG to the definition we
1493 : use inside the chain. */
1494 217191 : rtx *vdef = defs_map.get (dst);
1495 217191 : if (vdef)
1496 25152 : dst = *vdef;
1497 217191 : dst = gen_rtx_SUBREG (vmode, dst, 0);
1498 : /* IRA doesn't like to have REG_EQUAL/EQUIV notes when the SET_DEST
1499 : is a non-REG_P. So kill those off. */
1500 217191 : rtx note = find_reg_equal_equiv_note (insn);
1501 217191 : if (note)
1502 9695 : remove_note (insn, note);
1503 : }
1504 :
1505 413046 : switch (GET_CODE (src))
1506 : {
1507 26709 : case PLUS:
1508 26709 : case MINUS:
1509 26709 : case IOR:
1510 26709 : case XOR:
1511 26709 : case AND:
1512 26709 : case SMAX:
1513 26709 : case SMIN:
1514 26709 : case UMAX:
1515 26709 : case UMIN:
1516 26709 : convert_op (&XEXP (src, 1), insn);
1517 : /* FALLTHRU */
1518 :
1519 33380 : case ABS:
1520 33380 : case ASHIFT:
1521 33380 : case ASHIFTRT:
1522 33380 : case LSHIFTRT:
1523 33380 : convert_op (&XEXP (src, 0), insn);
1524 33380 : PUT_MODE (src, vmode);
1525 33380 : break;
1526 :
1527 92 : case ROTATE:
1528 92 : case ROTATERT:
1529 92 : src = convert_rotate (GET_CODE (src), XEXP (src, 0), XEXP (src, 1),
1530 : insn);
1531 92 : break;
1532 :
1533 402 : case NEG:
1534 402 : src = XEXP (src, 0);
1535 :
1536 402 : if (GET_CODE (src) == ABS)
1537 : {
1538 0 : src = XEXP (src, 0);
1539 0 : convert_op (&src, insn);
1540 0 : subreg = gen_reg_rtx (vmode);
1541 0 : emit_insn_before (gen_rtx_SET (subreg,
1542 : gen_rtx_ABS (vmode, src)), insn);
1543 0 : src = subreg;
1544 : }
1545 : else
1546 402 : convert_op (&src, insn);
1547 :
1548 402 : subreg = gen_reg_rtx (vmode);
1549 402 : emit_insn_before (gen_move_insn (subreg, CONST0_RTX (vmode)), insn);
1550 402 : src = gen_rtx_MINUS (vmode, subreg, src);
1551 402 : break;
1552 :
1553 225 : case NOT:
1554 225 : src = XEXP (src, 0);
1555 225 : convert_op (&src, insn);
1556 225 : subreg = gen_reg_rtx (vmode);
1557 225 : emit_insn_before (gen_move_insn (subreg, CONSTM1_RTX (vmode)), insn);
1558 225 : src = gen_rtx_XOR (vmode, src, subreg);
1559 225 : break;
1560 :
1561 173934 : case MEM:
1562 173934 : if (!REG_P (dst))
1563 173934 : convert_op (&src, insn);
1564 : break;
1565 :
1566 196716 : case REG:
1567 196716 : if (!MEM_P (dst))
1568 1646 : convert_op (&src, insn);
1569 : break;
1570 :
1571 0 : case SUBREG:
1572 0 : gcc_assert (GET_MODE (src) == vmode);
1573 : break;
1574 :
1575 0 : case COMPARE:
1576 0 : dst = gen_rtx_REG (CCZmode, FLAGS_REG);
1577 0 : src = convert_compare (XEXP (src, 0), XEXP (src, 1), insn);
1578 0 : break;
1579 :
1580 3946 : case CONST_INT:
1581 3946 : convert_op (&src, insn);
1582 3946 : break;
1583 :
1584 4014 : case VEC_SELECT:
1585 4014 : if (XVECEXP (XEXP (src, 1), 0, 0) == const0_rtx)
1586 2152 : src = XEXP (src, 0);
1587 1862 : else if (smode == DImode)
1588 : {
1589 1487 : rtx tmp = gen_lowpart (V1TImode, XEXP (src, 0));
1590 1487 : dst = gen_lowpart (V1TImode, dst);
1591 1487 : src = gen_rtx_LSHIFTRT (V1TImode, tmp, GEN_INT (64));
1592 : }
1593 : else
1594 : {
1595 375 : rtx tmp = XVECEXP (XEXP (src, 1), 0, 0);
1596 375 : rtvec vec = gen_rtvec (4, tmp, tmp, tmp, tmp);
1597 375 : rtx par = gen_rtx_PARALLEL (VOIDmode, vec);
1598 375 : src = gen_rtx_VEC_SELECT (vmode, XEXP (src, 0), par);
1599 : }
1600 : break;
1601 :
1602 337 : case ZERO_EXTEND:
1603 : /* *zero_extendsidi2 becomes *vec_setv2di_0_zero_extendsi_1. */
1604 337 : src = gen_rtx_VEC_CONCAT (V2DImode, src, const0_rtx);
1605 337 : break;
1606 :
1607 0 : default:
1608 0 : gcc_unreachable ();
1609 : }
1610 :
1611 413046 : SET_SRC (def_set) = src;
1612 413046 : SET_DEST (def_set) = dst;
1613 :
1614 : /* Drop possible dead definitions. */
1615 413046 : PATTERN (insn) = def_set;
1616 :
1617 413046 : INSN_CODE (insn) = -1;
1618 413046 : int patt = recog_memoized (insn);
1619 413046 : if (patt == -1)
1620 0 : fatal_insn_not_found (insn);
1621 413046 : df_insn_rescan (insn);
1622 413046 : }
1623 :
1624 : /* Helper function to compute gain for loading an immediate constant.
1625 : Typically, two movabsq for TImode vs. vmovdqa for V1TImode, but
1626 : with numerous special cases. */
1627 :
1628 : static int
1629 35 : timode_immed_const_gain (rtx cst, basic_block bb)
1630 : {
1631 : /* movabsq vs. movabsq+vmovq+vunpacklqdq. */
1632 35 : if (CONST_WIDE_INT_P (cst)
1633 23 : && CONST_WIDE_INT_NUNITS (cst) == 2
1634 58 : && CONST_WIDE_INT_ELT (cst, 0) == CONST_WIDE_INT_ELT (cst, 1))
1635 0 : return optimize_bb_for_size_p (bb) ? -COSTS_N_BYTES (9)
1636 : : -COSTS_N_INSNS (2);
1637 : /* 2x movabsq ~ vmovdqa. */
1638 : return 0;
1639 : }
1640 :
1641 : /* Return true it's cost profitable for for chain conversion. */
1642 :
1643 : bool
1644 527261 : timode_scalar_chain::compute_convert_gain ()
1645 : {
1646 : /* Assume that if we have to move TImode values between units,
1647 : then transforming this chain isn't worth it. */
1648 527261 : if (cost_sse_integer)
1649 : return false;
1650 :
1651 527261 : bitmap_iterator bi;
1652 527261 : unsigned insn_uid;
1653 :
1654 : /* Split ties to prefer V1TImode when not optimizing for size. */
1655 527261 : int gain = optimize_size ? 0 : 1;
1656 527261 : sreal weighted_gain = 0;
1657 :
1658 527261 : if (dump_file)
1659 0 : fprintf (dump_file, "Computing gain for chain #%d...\n", chain_id);
1660 :
1661 1576504 : EXECUTE_IF_SET_IN_BITMAP (insns, 0, insn_uid, bi)
1662 : {
1663 1049243 : rtx_insn *insn = DF_INSN_UID_GET (insn_uid)->insn;
1664 1049243 : rtx def_set = single_set (insn);
1665 1049243 : rtx src = SET_SRC (def_set);
1666 1049243 : rtx dst = SET_DEST (def_set);
1667 1049243 : HOST_WIDE_INT op1val;
1668 1049243 : basic_block bb = BLOCK_FOR_INSN (insn);
1669 1049243 : int scost, vcost;
1670 1049243 : int igain = 0;
1671 1049243 : profile_count entry_count = ENTRY_BLOCK_PTR_FOR_FN (cfun)->count;
1672 1049243 : bool speed_p = optimize_bb_for_speed_p (bb);
1673 1049243 : sreal bb_freq = bb->count.to_sreal_scale (entry_count);
1674 :
1675 1049243 : switch (GET_CODE (src))
1676 : {
1677 546222 : case REG:
1678 546222 : if (GENERAL_REGNO_P (REGNO (src)))
1679 : {
1680 24974 : if (TARGET_SSE4_1)
1681 : /* movq + pinsrq */
1682 27 : igain = speed_p ? -ix86_cost->integer_to_sse
1683 : - COSTS_N_INSNS (1)
1684 : : -COSTS_N_BYTES (11);
1685 : else
1686 : /* movq + movq + punpcklqdq */
1687 24947 : igain = speed_p ? -ix86_cost->integer_to_sse
1688 : - COSTS_N_INSNS (2)
1689 : : -COSTS_N_BYTES (14);
1690 : }
1691 521248 : else if (GENERAL_REG_P (dst))
1692 : {
1693 24986 : if (TARGET_SSE4_1)
1694 : /* pextrq + movq */
1695 27 : igain = speed_p ? -ix86_cost->sse_to_integer
1696 : - COSTS_N_INSNS (1)
1697 : : -COSTS_N_BYTES (11);
1698 : else
1699 : /* movhlps + movq + movq */
1700 24959 : igain = speed_p ? -ix86_cost->sse_to_integer
1701 : - COSTS_N_INSNS (2)
1702 : : -COSTS_N_BYTES (13);
1703 : }
1704 496262 : else if (!speed_p)
1705 15607 : igain = MEM_P (dst) ? COSTS_N_BYTES (6) : COSTS_N_BYTES (3);
1706 : else
1707 : igain = COSTS_N_INSNS (1);
1708 : break;
1709 :
1710 455151 : case MEM:
1711 455151 : igain = !speed_p ? COSTS_N_BYTES (7) : COSTS_N_INSNS (1);
1712 : break;
1713 :
1714 10939 : case CONST_INT:
1715 10939 : if (MEM_P (dst)
1716 10939 : && standard_sse_constant_p (src, V1TImode))
1717 10471 : igain = !speed_p ? COSTS_N_BYTES (11) : 1;
1718 : break;
1719 :
1720 31620 : case CONST_WIDE_INT:
1721 : /* 2 x mov vs. vmovdqa. */
1722 31620 : if (MEM_P (dst))
1723 31068 : igain = !speed_p ? COSTS_N_BYTES (3) : COSTS_N_INSNS (1);
1724 : break;
1725 :
1726 78 : case NOT:
1727 78 : if (MEM_P (dst))
1728 68210 : igain = -COSTS_N_INSNS (1);
1729 : break;
1730 :
1731 68 : case AND:
1732 68 : if (!MEM_P (dst))
1733 : {
1734 57 : igain = COSTS_N_INSNS (1);
1735 57 : if (MEM_P (XEXP (src, 0)) || MEM_P (XEXP (src, 1)))
1736 : /* One less load. */
1737 20 : igain += COSTS_N_INSNS (1);
1738 : }
1739 68 : if (CONST_SCALAR_INT_P (XEXP (src, 1)))
1740 26 : igain += timode_immed_const_gain (XEXP (src, 1), bb);
1741 : break;
1742 :
1743 4524 : case XOR:
1744 4524 : case IOR:
1745 4524 : if (timode_concatdi_p (src))
1746 : {
1747 : /* vmovq;vpinsrq (11 bytes). */
1748 4377 : igain = speed_p ? -ix86_cost->integer_to_sse - COSTS_N_INSNS (1)
1749 : : -COSTS_N_BYTES (11);
1750 : break;
1751 : }
1752 147 : if (!MEM_P (dst))
1753 : {
1754 139 : igain = COSTS_N_INSNS (1);
1755 139 : if (MEM_P (XEXP (src, 0)) || MEM_P (XEXP (src, 1)))
1756 : /* One less load. */
1757 48 : igain += COSTS_N_INSNS (1);
1758 : }
1759 147 : if (CONST_SCALAR_INT_P (XEXP (src, 1)))
1760 9 : igain += timode_immed_const_gain (XEXP (src, 1), bb);
1761 : break;
1762 :
1763 0 : case PLUS:
1764 0 : if (timode_concatdi_p (src))
1765 : /* vmovq;vpinsrq (11 bytes). */
1766 0 : igain = speed_p ? -ix86_cost->integer_to_sse - COSTS_N_INSNS (1)
1767 : : -COSTS_N_BYTES (11);
1768 : break;
1769 :
1770 224 : case ASHIFT:
1771 224 : case LSHIFTRT:
1772 : /* See ix86_expand_v1ti_shift. */
1773 224 : op1val = INTVAL (XEXP (src, 1));
1774 224 : if (!speed_p)
1775 : {
1776 21 : if (op1val == 64 || op1val == 65)
1777 : scost = COSTS_N_BYTES (5);
1778 13 : else if (op1val >= 66)
1779 : scost = COSTS_N_BYTES (6);
1780 13 : else if (op1val == 1)
1781 : scost = COSTS_N_BYTES (8);
1782 : else
1783 : scost = COSTS_N_BYTES (9);
1784 :
1785 19 : if ((op1val & 7) == 0)
1786 : vcost = COSTS_N_BYTES (5);
1787 13 : else if (op1val > 64)
1788 : vcost = COSTS_N_BYTES (10);
1789 : else
1790 13 : vcost = TARGET_AVX ? COSTS_N_BYTES (19) : COSTS_N_BYTES (23);
1791 : }
1792 : else
1793 : {
1794 203 : scost = COSTS_N_INSNS (2);
1795 203 : if ((op1val & 7) == 0)
1796 : vcost = COSTS_N_INSNS (1);
1797 133 : else if (op1val > 64)
1798 : vcost = COSTS_N_INSNS (2);
1799 : else
1800 133 : vcost = TARGET_AVX ? COSTS_N_INSNS (4) : COSTS_N_INSNS (5);
1801 : }
1802 224 : igain = scost - vcost;
1803 224 : break;
1804 :
1805 123 : case ASHIFTRT:
1806 : /* See ix86_expand_v1ti_ashiftrt. */
1807 123 : op1val = INTVAL (XEXP (src, 1));
1808 123 : if (!speed_p)
1809 : {
1810 9 : if (op1val == 64 || op1val == 127)
1811 : scost = COSTS_N_BYTES (7);
1812 9 : else if (op1val == 1)
1813 : scost = COSTS_N_BYTES (8);
1814 8 : else if (op1val == 65)
1815 : scost = COSTS_N_BYTES (10);
1816 8 : else if (op1val >= 66)
1817 : scost = COSTS_N_BYTES (11);
1818 : else
1819 : scost = COSTS_N_BYTES (9);
1820 :
1821 0 : if (op1val == 127)
1822 : vcost = COSTS_N_BYTES (10);
1823 9 : else if (op1val == 64)
1824 : vcost = COSTS_N_BYTES (14);
1825 9 : else if (op1val == 96)
1826 : vcost = COSTS_N_BYTES (18);
1827 9 : else if (op1val >= 111)
1828 : vcost = COSTS_N_BYTES (15);
1829 9 : else if (TARGET_AVX2 && op1val == 32)
1830 : vcost = COSTS_N_BYTES (16);
1831 9 : else if (TARGET_SSE4_1 && op1val == 32)
1832 : vcost = COSTS_N_BYTES (20);
1833 9 : else if (op1val >= 96)
1834 : vcost = COSTS_N_BYTES (23);
1835 9 : else if ((op1val & 7) == 0)
1836 : vcost = COSTS_N_BYTES (28);
1837 9 : else if (TARGET_AVX2 && op1val < 32)
1838 : vcost = COSTS_N_BYTES (30);
1839 9 : else if (op1val == 1 || op1val >= 64)
1840 : vcost = COSTS_N_BYTES (42);
1841 : else
1842 8 : vcost = COSTS_N_BYTES (47);
1843 : }
1844 : else
1845 : {
1846 114 : if (op1val >= 65 && op1val <= 126)
1847 : scost = COSTS_N_INSNS (3);
1848 : else
1849 114 : scost = COSTS_N_INSNS (2);
1850 :
1851 114 : if (op1val == 127)
1852 : vcost = COSTS_N_INSNS (2);
1853 113 : else if (op1val == 64)
1854 : vcost = COSTS_N_INSNS (3);
1855 113 : else if (op1val == 96)
1856 : vcost = COSTS_N_INSNS (3);
1857 113 : else if (op1val >= 111)
1858 : vcost = COSTS_N_INSNS (3);
1859 113 : else if (TARGET_SSE4_1 && op1val == 32)
1860 : vcost = COSTS_N_INSNS (3);
1861 113 : else if (TARGET_SSE4_1
1862 0 : && (op1val == 8 || op1val == 16 || op1val == 24))
1863 : vcost = COSTS_N_INSNS (3);
1864 113 : else if (op1val >= 96)
1865 : vcost = COSTS_N_INSNS (4);
1866 113 : else if (TARGET_SSE4_1 && (op1val == 28 || op1val == 80))
1867 : vcost = COSTS_N_INSNS (4);
1868 113 : else if ((op1val & 7) == 0)
1869 : vcost = COSTS_N_INSNS (5);
1870 113 : else if (TARGET_AVX2 && op1val < 32)
1871 : vcost = COSTS_N_INSNS (6);
1872 113 : else if (TARGET_SSE4_1 && op1val < 15)
1873 : vcost = COSTS_N_INSNS (6);
1874 113 : else if (op1val == 1 || op1val >= 64)
1875 : vcost = COSTS_N_INSNS (8);
1876 : else
1877 16 : vcost = COSTS_N_INSNS (9);
1878 : }
1879 123 : igain = scost - vcost;
1880 123 : break;
1881 :
1882 6 : case ROTATE:
1883 6 : case ROTATERT:
1884 : /* See ix86_expand_v1ti_rotate. */
1885 6 : op1val = INTVAL (XEXP (src, 1));
1886 6 : if (!speed_p)
1887 : {
1888 0 : scost = COSTS_N_BYTES (13);
1889 0 : if ((op1val & 31) == 0)
1890 : vcost = COSTS_N_BYTES (5);
1891 0 : else if ((op1val & 7) == 0)
1892 0 : vcost = TARGET_AVX ? COSTS_N_BYTES (13) : COSTS_N_BYTES (18);
1893 0 : else if (op1val > 32 && op1val < 96)
1894 : vcost = COSTS_N_BYTES (24);
1895 : else
1896 0 : vcost = COSTS_N_BYTES (19);
1897 : }
1898 : else
1899 : {
1900 6 : scost = COSTS_N_INSNS (3);
1901 6 : if ((op1val & 31) == 0)
1902 : vcost = COSTS_N_INSNS (1);
1903 4 : else if ((op1val & 7) == 0)
1904 1 : vcost = TARGET_AVX ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4);
1905 3 : else if (op1val > 32 && op1val < 96)
1906 : vcost = COSTS_N_INSNS (5);
1907 : else
1908 3 : vcost = COSTS_N_INSNS (4);
1909 : }
1910 6 : igain = scost - vcost;
1911 6 : break;
1912 :
1913 19 : case COMPARE:
1914 19 : if (XEXP (src, 1) == const0_rtx)
1915 : {
1916 8 : if (GET_CODE (XEXP (src, 0)) == AND)
1917 : /* and;and;or (9 bytes) vs. ptest (5 bytes). */
1918 : igain = !speed_p ? COSTS_N_BYTES (4) : COSTS_N_INSNS (2);
1919 : /* or (3 bytes) vs. ptest (5 bytes). */
1920 8 : else if (!speed_p)
1921 0 : igain = -COSTS_N_BYTES (2);
1922 : }
1923 11 : else if (XEXP (src, 1) == const1_rtx)
1924 : /* and;cmp -1 (7 bytes) vs. pcmpeqd;pxor;ptest (13 bytes). */
1925 0 : igain = !speed_p ? -COSTS_N_BYTES (6) : -COSTS_N_INSNS (1);
1926 : break;
1927 :
1928 269 : case ZERO_EXTEND:
1929 269 : if (GET_MODE (XEXP (src, 0)) == DImode)
1930 : /* xor (2 bytes) vs. vmovq (5 bytes). */
1931 269 : igain = speed_p ? COSTS_N_INSNS (1) - ix86_cost->sse_to_integer
1932 : : -COSTS_N_BYTES (3);
1933 : break;
1934 :
1935 : default:
1936 : break;
1937 : }
1938 :
1939 2064667 : gain += igain;
1940 1049235 : if (speed_p)
1941 1015432 : weighted_gain += bb_freq * igain;
1942 :
1943 1049243 : if (igain != 0 && dump_file)
1944 : {
1945 0 : fprintf (dump_file, " Instruction gain %d with bb_freq %.2f for ",
1946 : igain, bb_freq.to_double ());
1947 0 : dump_insn_slim (dump_file, insn);
1948 : }
1949 : }
1950 :
1951 527261 : if (dump_file)
1952 0 : fprintf (dump_file, " Total gain: %d, weighted gain %.2f\n",
1953 : gain, weighted_gain.to_double ());
1954 :
1955 527261 : if (weighted_gain > (sreal) 0)
1956 : return true;
1957 : else
1958 56012 : return gain > 0;
1959 : }
1960 :
1961 : /* Fix uses of converted REG in debug insns. */
1962 :
1963 : void
1964 444657 : timode_scalar_chain::fix_debug_reg_uses (rtx reg)
1965 : {
1966 444657 : if (!flag_var_tracking)
1967 : return;
1968 :
1969 390487 : df_ref ref, next;
1970 799930 : for (ref = DF_REG_USE_CHAIN (REGNO (reg)); ref; ref = next)
1971 : {
1972 409443 : rtx_insn *insn = DF_REF_INSN (ref);
1973 : /* Make sure the next ref is for a different instruction,
1974 : so that we're not affected by the rescan. */
1975 409443 : next = DF_REF_NEXT_REG (ref);
1976 409443 : while (next && DF_REF_INSN (next) == insn)
1977 0 : next = DF_REF_NEXT_REG (next);
1978 :
1979 409443 : if (DEBUG_INSN_P (insn))
1980 : {
1981 : /* It may be a debug insn with a TImode variable in
1982 : register. */
1983 : bool changed = false;
1984 246 : for (; ref != next; ref = DF_REF_NEXT_REG (ref))
1985 : {
1986 123 : rtx *loc = DF_REF_LOC (ref);
1987 123 : if (REG_P (*loc) && GET_MODE (*loc) == V1TImode)
1988 : {
1989 114 : *loc = gen_rtx_SUBREG (TImode, *loc, 0);
1990 114 : changed = true;
1991 : }
1992 : }
1993 123 : if (changed)
1994 114 : df_insn_rescan (insn);
1995 : }
1996 : }
1997 : }
1998 :
1999 : /* Convert SRC, a *concatditi3 pattern, into a vec_concatv2di instruction.
2000 : Insert this before INSN, and return the result as a V1TImode subreg. */
2001 :
2002 : static rtx
2003 283 : timode_convert_concatdi (rtx src, rtx_insn *insn)
2004 : {
2005 283 : rtx hi, lo;
2006 283 : rtx tmp = gen_reg_rtx (V2DImode);
2007 283 : if (GET_CODE (XEXP (src, 0)) == ASHIFT)
2008 : {
2009 283 : hi = XEXP (XEXP (XEXP (src, 0), 0), 0);
2010 283 : lo = XEXP (XEXP (src, 1), 0);
2011 : }
2012 : else
2013 : {
2014 0 : hi = XEXP (XEXP (XEXP (src, 1), 0), 0);
2015 0 : lo = XEXP (XEXP (src, 0), 0);
2016 : }
2017 283 : emit_insn_before (gen_vec_concatv2di (tmp, lo, hi), insn);
2018 283 : return gen_rtx_SUBREG (V1TImode, tmp, 0);
2019 : }
2020 :
2021 : /* Convert INSN from TImode to V1T1mode. */
2022 :
2023 : void
2024 959507 : timode_scalar_chain::convert_insn (rtx_insn *insn)
2025 : {
2026 959507 : rtx def_set = single_set (insn);
2027 959507 : rtx src = SET_SRC (def_set);
2028 959507 : rtx dst = SET_DEST (def_set);
2029 959507 : rtx tmp;
2030 :
2031 959507 : switch (GET_CODE (dst))
2032 : {
2033 445183 : case REG:
2034 445183 : if (GET_MODE (dst) == TImode)
2035 : {
2036 444566 : if (!HARD_REGISTER_NUM_P (REGNO (dst)))
2037 : {
2038 444052 : PUT_MODE (dst, V1TImode);
2039 444052 : fix_debug_reg_uses (dst);
2040 : }
2041 514 : else if (!GENERAL_REGNO_P (REGNO (dst)))
2042 359 : dst = gen_raw_REG (V1TImode, REGNO (dst));
2043 : }
2044 445183 : if (GET_MODE (dst) == V1TImode)
2045 : {
2046 : /* It might potentially be helpful to convert REG_EQUAL notes,
2047 : but for now we just remove them. */
2048 445016 : rtx note = find_reg_equal_equiv_note (insn);
2049 445016 : if (note)
2050 483 : remove_note (insn, note);
2051 : }
2052 : break;
2053 514324 : case MEM:
2054 514324 : PUT_MODE (dst, V1TImode);
2055 514324 : break;
2056 :
2057 0 : default:
2058 0 : gcc_unreachable ();
2059 : }
2060 :
2061 959507 : switch (GET_CODE (src))
2062 : {
2063 473632 : case REG:
2064 473632 : if (GET_MODE (src) == TImode)
2065 : {
2066 831 : if (GENERAL_REGNO_P (REGNO (src)))
2067 : {
2068 221 : rtx lo = gen_reg_rtx (DImode);
2069 221 : rtx hi = gen_reg_rtx (DImode);
2070 221 : emit_insn_before (gen_rtx_SET (lo, gen_lowpart (DImode, src)),
2071 : insn);
2072 221 : emit_insn_before (gen_rtx_SET (hi, gen_highpart (DImode, src)),
2073 : insn);
2074 221 : src = gen_reg_rtx (V2DImode);
2075 221 : emit_insn_before (gen_vec_concatv2di (src, lo, hi), insn);
2076 221 : src = gen_lowpart (V1TImode, src);
2077 : }
2078 610 : else if (!HARD_REGISTER_NUM_P (REGNO (src)))
2079 : {
2080 605 : PUT_MODE (src, V1TImode);
2081 605 : fix_debug_reg_uses (src);
2082 : }
2083 : else
2084 5 : src = gen_raw_REG (V1TImode, REGNO (src));
2085 : }
2086 473632 : if (GENERAL_REG_P (dst))
2087 : {
2088 155 : rtx tmp = gen_reg_rtx (V2DImode);
2089 155 : src = gen_lowpart (V2DImode, src);
2090 155 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2091 : /* Extracting hi before lo helps register allocation. */
2092 155 : rtx hi = gen_reg_rtx (DImode);
2093 155 : rtx lo = gen_reg_rtx (DImode);
2094 155 : emit_insn_before (gen_vec_extractv2didi (hi, tmp, const1_rtx), insn);
2095 155 : emit_insn_before (gen_vec_extractv2didi (lo, tmp, const0_rtx), insn);
2096 :
2097 : /* Construct *concatditi3 pattern from lo and hi. */
2098 155 : hi = gen_rtx_ZERO_EXTEND (TImode, hi);
2099 155 : hi = gen_rtx_ASHIFT (TImode, hi, GEN_INT (64));
2100 155 : lo = gen_rtx_ZERO_EXTEND (TImode, lo);
2101 155 : src = gen_rtx_PLUS (TImode, hi, lo);
2102 : }
2103 : break;
2104 :
2105 442889 : case MEM:
2106 442889 : PUT_MODE (src, V1TImode);
2107 442889 : break;
2108 :
2109 31449 : case CONST_WIDE_INT:
2110 31449 : if (NONDEBUG_INSN_P (insn))
2111 : {
2112 : /* Since there are no instructions to store 128-bit constant,
2113 : temporary register usage is required. */
2114 31449 : bool use_move;
2115 31449 : start_sequence ();
2116 31449 : tmp = ix86_convert_const_wide_int_to_broadcast (TImode, src);
2117 31449 : if (tmp)
2118 : {
2119 194 : src = lowpart_subreg (V1TImode, tmp, TImode);
2120 194 : use_move = true;
2121 : }
2122 : else
2123 : {
2124 31255 : src = smode_convert_cst (src, V1TImode);
2125 31255 : src = validize_mem (force_const_mem (V1TImode, src));
2126 31255 : use_move = MEM_P (dst);
2127 : }
2128 31449 : rtx_insn *seq = end_sequence ();
2129 31449 : if (seq)
2130 195 : emit_insn_before (seq, insn);
2131 31449 : if (use_move)
2132 : {
2133 31069 : tmp = gen_reg_rtx (V1TImode);
2134 31069 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2135 31069 : src = tmp;
2136 : }
2137 : }
2138 : break;
2139 :
2140 10939 : case CONST_INT:
2141 10939 : switch (standard_sse_constant_p (src, TImode))
2142 : {
2143 10716 : case 1:
2144 10716 : src = CONST0_RTX (GET_MODE (dst));
2145 10716 : break;
2146 223 : case 2:
2147 223 : src = CONSTM1_RTX (GET_MODE (dst));
2148 223 : break;
2149 0 : default:
2150 0 : gcc_unreachable ();
2151 : }
2152 10939 : if (MEM_P (dst))
2153 : {
2154 10471 : tmp = gen_reg_rtx (V1TImode);
2155 10471 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2156 10471 : src = tmp;
2157 : }
2158 : break;
2159 :
2160 41 : case AND:
2161 41 : if (GET_CODE (XEXP (src, 0)) == NOT)
2162 : {
2163 0 : convert_op (&XEXP (XEXP (src, 0), 0), insn);
2164 0 : convert_op (&XEXP (src, 1), insn);
2165 0 : PUT_MODE (XEXP (src, 0), V1TImode);
2166 0 : PUT_MODE (src, V1TImode);
2167 0 : break;
2168 : }
2169 41 : convert_op (&XEXP (src, 0), insn);
2170 41 : convert_op (&XEXP (src, 1), insn);
2171 41 : PUT_MODE (src, V1TImode);
2172 41 : if (MEM_P (dst))
2173 : {
2174 10 : tmp = gen_reg_rtx (V1TImode);
2175 10 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2176 10 : src = tmp;
2177 : }
2178 : break;
2179 :
2180 381 : case XOR:
2181 381 : case IOR:
2182 381 : if (timode_concatdi_p (src))
2183 : {
2184 283 : src = timode_convert_concatdi (src, insn);
2185 283 : break;
2186 : }
2187 98 : convert_op (&XEXP (src, 0), insn);
2188 98 : convert_op (&XEXP (src, 1), insn);
2189 98 : PUT_MODE (src, V1TImode);
2190 98 : if (MEM_P (dst))
2191 : {
2192 8 : tmp = gen_reg_rtx (V1TImode);
2193 8 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2194 8 : src = tmp;
2195 : }
2196 : break;
2197 :
2198 3 : case NOT:
2199 3 : src = XEXP (src, 0);
2200 3 : convert_op (&src, insn);
2201 3 : tmp = gen_reg_rtx (V1TImode);
2202 3 : emit_insn_before (gen_move_insn (tmp, CONSTM1_RTX (V1TImode)), insn);
2203 3 : src = gen_rtx_XOR (V1TImode, src, tmp);
2204 3 : if (MEM_P (dst))
2205 : {
2206 0 : tmp = gen_reg_rtx (V1TImode);
2207 0 : emit_insn_before (gen_rtx_SET (tmp, src), insn);
2208 0 : src = tmp;
2209 : }
2210 : break;
2211 :
2212 12 : case COMPARE:
2213 12 : dst = gen_rtx_REG (CCZmode, FLAGS_REG);
2214 12 : src = convert_compare (XEXP (src, 0), XEXP (src, 1), insn);
2215 12 : break;
2216 :
2217 58 : case ASHIFT:
2218 58 : case LSHIFTRT:
2219 58 : case ASHIFTRT:
2220 58 : case ROTATERT:
2221 58 : case ROTATE:
2222 58 : convert_op (&XEXP (src, 0), insn);
2223 58 : PUT_MODE (src, V1TImode);
2224 58 : break;
2225 :
2226 103 : case ZERO_EXTEND:
2227 103 : if (GET_MODE (XEXP (src, 0)) == DImode)
2228 : {
2229 : /* Convert to *vec_concatv2di_0. */
2230 103 : rtx tmp = gen_reg_rtx (V2DImode);
2231 103 : rtx pat = gen_rtx_VEC_CONCAT (V2DImode, XEXP (src, 0), const0_rtx);
2232 103 : emit_insn_before (gen_move_insn (tmp, pat), insn);
2233 103 : src = gen_rtx_SUBREG (vmode, tmp, 0);
2234 : }
2235 : else
2236 0 : gcc_unreachable ();
2237 103 : break;
2238 :
2239 0 : case PLUS:
2240 0 : if (timode_concatdi_p (src))
2241 0 : src = timode_convert_concatdi (src, insn);
2242 : else
2243 0 : gcc_unreachable ();
2244 0 : break;
2245 :
2246 0 : default:
2247 0 : gcc_unreachable ();
2248 : }
2249 :
2250 959507 : SET_SRC (def_set) = src;
2251 959507 : SET_DEST (def_set) = dst;
2252 :
2253 : /* Drop possible dead definitions. */
2254 959507 : PATTERN (insn) = def_set;
2255 :
2256 959507 : INSN_CODE (insn) = -1;
2257 959507 : recog_memoized (insn);
2258 959507 : df_insn_rescan (insn);
2259 959507 : }
2260 :
2261 : /* Generate copies from defs used by the chain but not defined therein.
2262 : Also populates defs_map which is used later by convert_insn. */
2263 :
2264 : void
2265 659197 : scalar_chain::convert_registers ()
2266 : {
2267 659197 : bitmap_iterator bi;
2268 659197 : unsigned id;
2269 686484 : EXECUTE_IF_SET_IN_BITMAP (defs_conv, 0, id, bi)
2270 : {
2271 27287 : rtx chain_reg = gen_reg_rtx (smode);
2272 27287 : defs_map.put (regno_reg_rtx[id], chain_reg);
2273 : }
2274 668293 : EXECUTE_IF_SET_IN_BITMAP (insns_conv, 0, id, bi)
2275 21910 : for (df_ref ref = DF_INSN_UID_DEFS (id); ref; ref = DF_REF_NEXT_LOC (ref))
2276 12814 : if (bitmap_bit_p (defs_conv, DF_REF_REGNO (ref)))
2277 9096 : make_vector_copies (DF_REF_INSN (ref), DF_REF_REAL_REG (ref));
2278 659197 : }
2279 :
2280 : /* Convert whole chain creating required register
2281 : conversions and copies. */
2282 :
2283 : int
2284 659197 : scalar_chain::convert ()
2285 : {
2286 659197 : bitmap_iterator bi;
2287 659197 : unsigned id;
2288 659197 : int converted_insns = 0;
2289 :
2290 659197 : if (!dbg_cnt (stv_conversion))
2291 : return 0;
2292 :
2293 659197 : if (dump_file)
2294 0 : fprintf (dump_file, "Converting chain #%d...\n", chain_id);
2295 :
2296 659197 : convert_registers ();
2297 :
2298 2031750 : EXECUTE_IF_SET_IN_BITMAP (insns, 0, id, bi)
2299 : {
2300 1372553 : rtx_insn *insn = DF_INSN_UID_GET (id)->insn;
2301 1372553 : convert_insn_common (insn);
2302 1372553 : convert_insn (insn);
2303 1372553 : converted_insns++;
2304 : }
2305 :
2306 : return converted_insns;
2307 : }
2308 :
2309 : /* Return the SET expression if INSN doesn't reference hard register.
2310 : Return NULL if INSN uses or defines a hard register, excluding
2311 : pseudo register pushes, hard register uses in a memory address,
2312 : clobbers and flags definitions. */
2313 :
2314 : static rtx
2315 357352849 : pseudo_reg_set (rtx_insn *insn)
2316 : {
2317 357352849 : rtx set = single_set (insn);
2318 357352849 : if (!set)
2319 : return NULL;
2320 :
2321 : /* Check pseudo register push first. */
2322 138878447 : machine_mode mode = TARGET_64BIT ? TImode : DImode;
2323 138878447 : if (REG_P (SET_SRC (set))
2324 39383200 : && !HARD_REGISTER_P (SET_SRC (set))
2325 169668837 : && push_operand (SET_DEST (set), mode))
2326 : return set;
2327 :
2328 138626589 : df_ref ref;
2329 224770651 : FOR_EACH_INSN_DEF (ref, insn)
2330 124110181 : if (HARD_REGISTER_P (DF_REF_REAL_REG (ref))
2331 66796885 : && !DF_REF_FLAGS_IS_SET (ref, DF_REF_MUST_CLOBBER)
2332 175871042 : && DF_REF_REGNO (ref) != FLAGS_REG)
2333 : return NULL;
2334 :
2335 192567781 : FOR_EACH_INSN_USE (ref, insn)
2336 117995498 : if (!DF_REF_REG_MEM_P (ref) && HARD_REGISTER_P (DF_REF_REAL_REG (ref)))
2337 : return NULL;
2338 :
2339 : return set;
2340 : }
2341 :
2342 : /* Return true if the register REG is defined in a single DEF chain.
2343 : If it is defined in more than one DEF chains, we may not be able
2344 : to convert it in all chains. */
2345 :
2346 : static bool
2347 1299313 : single_def_chain_p (rtx reg)
2348 : {
2349 1299313 : df_ref ref = DF_REG_DEF_CHAIN (REGNO (reg));
2350 1299313 : if (!ref)
2351 : return false;
2352 1299282 : return DF_REF_NEXT_REG (ref) == nullptr;
2353 : }
2354 :
2355 : /* Check if comparison INSN may be transformed into vector comparison.
2356 : Currently we transform equality/inequality checks which look like:
2357 : (set (reg:CCZ 17 flags) (compare:CCZ (reg:TI x) (reg:TI y))) */
2358 :
2359 : static bool
2360 13160296 : convertible_comparison_p (rtx_insn *insn, enum machine_mode mode)
2361 : {
2362 14576216 : if (mode != (TARGET_64BIT ? TImode : DImode))
2363 : return false;
2364 :
2365 4826210 : if (!TARGET_SSE4_1)
2366 : return false;
2367 :
2368 166001 : rtx def_set = single_set (insn);
2369 :
2370 166001 : gcc_assert (def_set);
2371 :
2372 166001 : rtx src = SET_SRC (def_set);
2373 166001 : rtx dst = SET_DEST (def_set);
2374 :
2375 166001 : gcc_assert (GET_CODE (src) == COMPARE);
2376 :
2377 166001 : if (!REG_P (dst)
2378 166001 : || REGNO (dst) != FLAGS_REG
2379 332002 : || GET_MODE (dst) != CCZmode)
2380 : return false;
2381 :
2382 115830 : rtx op1 = XEXP (src, 0);
2383 115830 : rtx op2 = XEXP (src, 1);
2384 :
2385 : /* *cmp<dwi>_doubleword. */
2386 115830 : if (general_operand (op1, mode)
2387 115830 : && general_operand (op2, mode))
2388 : return true;
2389 :
2390 : /* *testti_doubleword. */
2391 115774 : if (op2 == const0_rtx
2392 39755 : && GET_CODE (op1) == AND
2393 142 : && REG_P (XEXP (op1, 0)))
2394 : {
2395 142 : rtx op12 = XEXP (op1, 1);
2396 142 : return GET_MODE (XEXP (op1, 0)) == TImode
2397 142 : && (CONST_SCALAR_INT_P (op12)
2398 0 : || ((REG_P (op12) || MEM_P (op12))
2399 0 : && GET_MODE (op12) == TImode));
2400 : }
2401 :
2402 : /* *test<dwi>_not_doubleword. */
2403 115632 : if (op2 == const0_rtx
2404 39613 : && GET_CODE (op1) == AND
2405 0 : && GET_CODE (XEXP (op1, 0)) == NOT)
2406 : {
2407 0 : rtx op11 = XEXP (XEXP (op1, 0), 0);
2408 0 : rtx op12 = XEXP (op1, 1);
2409 0 : return (REG_P (op11) || MEM_P (op11))
2410 0 : && (REG_P (op12) || MEM_P (op12))
2411 0 : && GET_MODE (op11) == mode
2412 0 : && GET_MODE (op12) == mode;
2413 : }
2414 :
2415 : return false;
2416 : }
2417 :
2418 : /* The general version of scalar_to_vector_candidate_p. */
2419 :
2420 : static bool
2421 249381201 : general_scalar_to_vector_candidate_p (rtx_insn *insn, enum machine_mode mode)
2422 : {
2423 249381201 : rtx def_set = pseudo_reg_set (insn);
2424 :
2425 249381201 : if (!def_set)
2426 : return false;
2427 :
2428 50576381 : rtx src = SET_SRC (def_set);
2429 50576381 : rtx dst = SET_DEST (def_set);
2430 :
2431 50576381 : if (GET_CODE (src) == COMPARE)
2432 9042046 : return convertible_comparison_p (insn, mode);
2433 :
2434 : /* We are interested in "mode" only. */
2435 41534335 : if ((GET_MODE (src) != mode
2436 28312612 : && !CONST_INT_P (src))
2437 18520901 : || GET_MODE (dst) != mode)
2438 : return false;
2439 :
2440 15547921 : if (!REG_P (dst) && !MEM_P (dst))
2441 : return false;
2442 :
2443 15287177 : switch (GET_CODE (src))
2444 : {
2445 549120 : case ASHIFT:
2446 549120 : case LSHIFTRT:
2447 549120 : case ASHIFTRT:
2448 549120 : case ROTATE:
2449 549120 : case ROTATERT:
2450 549120 : if (!CONST_INT_P (XEXP (src, 1))
2451 1060684 : || !IN_RANGE (INTVAL (XEXP (src, 1)), 0, GET_MODE_BITSIZE (mode)-1))
2452 : return false;
2453 :
2454 : /* Check for extend highpart case. */
2455 511564 : if (mode != DImode
2456 376139 : || GET_CODE (src) != ASHIFTRT
2457 89556 : || GET_CODE (XEXP (src, 0)) != ASHIFT)
2458 : break;
2459 :
2460 3782561 : src = XEXP (src, 0);
2461 : break;
2462 :
2463 102071 : case SMAX:
2464 102071 : case SMIN:
2465 102071 : case UMAX:
2466 102071 : case UMIN:
2467 102071 : if ((mode == DImode && !TARGET_AVX512VL)
2468 18077 : || (mode == SImode && !TARGET_SSE4_1))
2469 : return false;
2470 : /* Fallthru. */
2471 :
2472 3301438 : case AND:
2473 3301438 : case IOR:
2474 3301438 : case XOR:
2475 3301438 : case PLUS:
2476 3301438 : case MINUS:
2477 3301438 : if (!REG_P (XEXP (src, 1))
2478 : && !MEM_P (XEXP (src, 1))
2479 : && !CONST_INT_P (XEXP (src, 1)))
2480 : return false;
2481 :
2482 3210001 : if (GET_MODE (XEXP (src, 1)) != mode
2483 1852631 : && !CONST_INT_P (XEXP (src, 1)))
2484 : return false;
2485 :
2486 : /* Check for andnot case. */
2487 3210001 : if (GET_CODE (src) != AND
2488 177187 : || GET_CODE (XEXP (src, 0)) != NOT)
2489 : break;
2490 :
2491 3782561 : src = XEXP (src, 0);
2492 : /* FALLTHRU */
2493 :
2494 : case NOT:
2495 : break;
2496 :
2497 32325 : case NEG:
2498 : /* Check for nabs case. */
2499 32325 : if (GET_CODE (XEXP (src, 0)) != ABS)
2500 : break;
2501 :
2502 : src = XEXP (src, 0);
2503 : /* FALLTHRU */
2504 :
2505 3869 : case ABS:
2506 3869 : if ((mode == DImode && !TARGET_AVX512VL)
2507 1459 : || (mode == SImode && !TARGET_SSSE3))
2508 : return false;
2509 : break;
2510 :
2511 : case REG:
2512 : return true;
2513 :
2514 6105012 : case MEM:
2515 6105012 : case CONST_INT:
2516 6105012 : return REG_P (dst);
2517 :
2518 66957 : case VEC_SELECT:
2519 : /* Excluding MEM_P (dst) avoids interfering with vpextr[dq]. */
2520 66957 : return REG_P (dst)
2521 56714 : && REG_P (XEXP (src, 0))
2522 66909 : && GET_MODE (XEXP (src, 0)) == (mode == DImode ? V2DImode
2523 : : V4SImode)
2524 45447 : && GET_CODE (XEXP (src, 1)) == PARALLEL
2525 45447 : && XVECLEN (XEXP (src, 1), 0) == 1
2526 112404 : && CONST_INT_P (XVECEXP (XEXP (src, 1), 0, 0));
2527 :
2528 321279 : case ZERO_EXTEND:
2529 : /* *zero_extendsidi2 becomes *vec_setv2di_0_zero_extendsi_1. */
2530 321279 : return mode == DImode
2531 228144 : && REG_P (dst)
2532 225398 : && GET_MODE (XEXP (src, 0)) == SImode
2533 510045 : && MEM_P (XEXP (src, 0));
2534 :
2535 : default:
2536 : return false;
2537 : }
2538 :
2539 3782561 : if (!REG_P (XEXP (src, 0))
2540 : && !MEM_P (XEXP (src, 0))
2541 : && !CONST_INT_P (XEXP (src, 0)))
2542 : return false;
2543 :
2544 3491725 : if (GET_MODE (XEXP (src, 0)) != mode
2545 0 : && !CONST_INT_P (XEXP (src, 0)))
2546 : return false;
2547 :
2548 : return true;
2549 : }
2550 :
2551 : /* Check for a suitable TImode memory operand. */
2552 :
2553 : static bool
2554 1635 : timode_mem_p (rtx x)
2555 : {
2556 1635 : return MEM_P (x)
2557 1635 : && (TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
2558 0 : || !misaligned_operand (x, TImode));
2559 : }
2560 :
2561 : /* The TImode version of scalar_to_vector_candidate_p. */
2562 :
2563 : static bool
2564 107971648 : timode_scalar_to_vector_candidate_p (rtx_insn *insn)
2565 : {
2566 107971648 : rtx def_set = pseudo_reg_set (insn);
2567 :
2568 : /* We allow two exceptions to the pseudo registers only rule.
2569 : Setting a hard register from a pseudo, and setting a pseudo
2570 : from a hard register. */
2571 107971648 : if (!def_set)
2572 : {
2573 83723888 : def_set = single_set (insn);
2574 83723888 : if (def_set)
2575 : {
2576 18514062 : rtx src = SET_SRC (def_set);
2577 18514062 : rtx dst = SET_DEST (def_set);
2578 18514062 : if (GET_MODE (dst) == TImode
2579 224249 : && REG_P (src) && REG_P (dst))
2580 : {
2581 102279 : if (HARD_REGISTER_P (dst)
2582 52967 : && !HARD_REGISTER_P (src)
2583 155246 : && single_def_chain_p (src))
2584 : return true;
2585 73084 : if (HARD_REGISTER_P (src)
2586 49312 : && !HARD_REGISTER_P (dst)
2587 122396 : && single_def_chain_p (dst))
2588 : return true;
2589 : }
2590 : }
2591 : return false;
2592 : }
2593 :
2594 24247760 : rtx src = SET_SRC (def_set);
2595 24247760 : rtx dst = SET_DEST (def_set);
2596 :
2597 24247760 : if (GET_CODE (src) == COMPARE)
2598 4118250 : return convertible_comparison_p (insn, TImode);
2599 :
2600 20129510 : if (GET_MODE (dst) != TImode
2601 1241748 : || (GET_MODE (src) != TImode
2602 60915 : && !CONST_SCALAR_INT_P (src)))
2603 : return false;
2604 :
2605 1241748 : if (!REG_P (dst) && !MEM_P (dst))
2606 : return false;
2607 :
2608 1240295 : if (MEM_P (dst)
2609 551785 : && misaligned_operand (dst, TImode)
2610 1569081 : && !TARGET_SSE_UNALIGNED_STORE_OPTIMAL)
2611 : return false;
2612 :
2613 1240290 : if (REG_P (dst) && !single_def_chain_p (dst))
2614 : return false;
2615 :
2616 1084796 : switch (GET_CODE (src))
2617 : {
2618 508524 : case REG:
2619 508524 : return single_def_chain_p (src);
2620 :
2621 : case CONST_WIDE_INT:
2622 : return true;
2623 :
2624 12924 : case CONST_INT:
2625 : /* ??? Verify performance impact before enabling CONST_INT for
2626 : __int128 store. */
2627 12924 : return standard_sse_constant_p (src, TImode);
2628 :
2629 465453 : case MEM:
2630 : /* Memory must be aligned or unaligned load is optimal. */
2631 465453 : return (REG_P (dst)
2632 465453 : && (!misaligned_operand (src, TImode)
2633 162697 : || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL));
2634 :
2635 3340 : case AND:
2636 3340 : if (!MEM_P (dst)
2637 3299 : && GET_CODE (XEXP (src, 0)) == NOT
2638 0 : && REG_P (XEXP (XEXP (src, 0), 0))
2639 3340 : && (REG_P (XEXP (src, 1))
2640 0 : || CONST_SCALAR_INT_P (XEXP (src, 1))
2641 0 : || timode_mem_p (XEXP (src, 1))))
2642 : return true;
2643 3340 : return (REG_P (XEXP (src, 0))
2644 46 : || timode_mem_p (XEXP (src, 0)))
2645 3386 : && (REG_P (XEXP (src, 1))
2646 1446 : || CONST_SCALAR_INT_P (XEXP (src, 1))
2647 45 : || timode_mem_p (XEXP (src, 1)));
2648 :
2649 14474 : case IOR:
2650 14474 : case XOR:
2651 14474 : if (timode_concatdi_p (src))
2652 : return true;
2653 2854 : return (REG_P (XEXP (src, 0))
2654 1461 : || timode_mem_p (XEXP (src, 0)))
2655 2871 : && (REG_P (XEXP (src, 1))
2656 307 : || CONST_SCALAR_INT_P (XEXP (src, 1))
2657 67 : || timode_mem_p (XEXP (src, 1)));
2658 :
2659 523 : case NOT:
2660 523 : return REG_P (XEXP (src, 0)) || timode_mem_p (XEXP (src, 0));
2661 :
2662 11852 : case ASHIFT:
2663 11852 : case LSHIFTRT:
2664 11852 : case ASHIFTRT:
2665 11852 : case ROTATERT:
2666 11852 : case ROTATE:
2667 : /* Handle shifts/rotates by integer constants between 0 and 127. */
2668 11852 : return REG_P (XEXP (src, 0))
2669 11816 : && CONST_INT_P (XEXP (src, 1))
2670 23308 : && (INTVAL (XEXP (src, 1)) & ~0x7f) == 0;
2671 :
2672 7279 : case PLUS:
2673 7279 : return timode_concatdi_p (src);
2674 :
2675 3909 : case ZERO_EXTEND:
2676 3909 : return REG_P (XEXP (src, 0))
2677 3909 : && GET_MODE (XEXP (src, 0)) == DImode;
2678 :
2679 : default:
2680 : return false;
2681 : }
2682 : }
2683 :
2684 : /* For a register REGNO, scan instructions for its defs and uses.
2685 : Put REGNO in REGS if a def or use isn't in CANDIDATES. */
2686 :
2687 : static void
2688 1277626 : timode_check_non_convertible_regs (bitmap candidates, bitmap regs,
2689 : unsigned int regno)
2690 : {
2691 : /* Do nothing if REGNO is already in REGS or is a hard reg. */
2692 1277626 : if (bitmap_bit_p (regs, regno)
2693 1277626 : || HARD_REGISTER_NUM_P (regno))
2694 : return;
2695 :
2696 1269449 : for (df_ref def = DF_REG_DEF_CHAIN (regno);
2697 2528132 : def;
2698 1258683 : def = DF_REF_NEXT_REG (def))
2699 : {
2700 1269429 : if (!bitmap_bit_p (candidates, DF_REF_INSN_UID (def)))
2701 : {
2702 10746 : if (dump_file)
2703 0 : fprintf (dump_file,
2704 : "r%d has non convertible def in insn %d\n",
2705 0 : regno, DF_REF_INSN_UID (def));
2706 :
2707 10746 : bitmap_set_bit (regs, regno);
2708 10746 : break;
2709 : }
2710 : }
2711 :
2712 1269449 : for (df_ref ref = DF_REG_USE_CHAIN (regno);
2713 2809612 : ref;
2714 1540163 : ref = DF_REF_NEXT_REG (ref))
2715 : {
2716 : /* Debug instructions are skipped. */
2717 1610694 : if (NONDEBUG_INSN_P (DF_REF_INSN (ref))
2718 1610694 : && !bitmap_bit_p (candidates, DF_REF_INSN_UID (ref)))
2719 : {
2720 70531 : if (dump_file)
2721 0 : fprintf (dump_file,
2722 : "r%d has non convertible use in insn %d\n",
2723 0 : regno, DF_REF_INSN_UID (ref));
2724 :
2725 70531 : bitmap_set_bit (regs, regno);
2726 70531 : break;
2727 : }
2728 : }
2729 : }
2730 :
2731 : /* For a given bitmap of insn UIDs scans all instructions and
2732 : remove insn from CANDIDATES in case it has both convertible
2733 : and not convertible definitions.
2734 :
2735 : All insns in a bitmap are conversion candidates according to
2736 : scalar_to_vector_candidate_p. Currently it implies all insns
2737 : are single_set. */
2738 :
2739 : static void
2740 850441 : timode_remove_non_convertible_regs (bitmap candidates)
2741 : {
2742 850441 : bitmap_iterator bi;
2743 850441 : unsigned id;
2744 850441 : bitmap regs = BITMAP_ALLOC (NULL);
2745 871898 : bool changed;
2746 :
2747 871898 : do {
2748 871898 : changed = false;
2749 2173861 : EXECUTE_IF_SET_IN_BITMAP (candidates, 0, id, bi)
2750 : {
2751 1301963 : rtx_insn *insn = DF_INSN_UID_GET (id)->insn;
2752 1301963 : df_ref ref;
2753 :
2754 2033706 : FOR_EACH_INSN_DEF (ref, insn)
2755 731743 : if (!DF_REF_REG_MEM_P (ref)
2756 731743 : && GET_MODE (DF_REF_REG (ref)) == TImode)
2757 641702 : timode_check_non_convertible_regs (candidates, regs,
2758 : DF_REF_REGNO (ref));
2759 :
2760 3207231 : FOR_EACH_INSN_USE (ref, insn)
2761 1905268 : if (DF_REF_TYPE (ref) == DF_REF_REG_USE
2762 772786 : && GET_MODE (DF_REF_REG (ref)) == TImode
2763 635929 : && !SUBREG_P (DF_REF_REG (ref)))
2764 635924 : timode_check_non_convertible_regs (candidates, regs,
2765 : DF_REF_REGNO (ref));
2766 : }
2767 :
2768 1050393 : EXECUTE_IF_SET_IN_BITMAP (regs, 0, id, bi)
2769 : {
2770 178495 : for (df_ref def = DF_REG_DEF_CHAIN (id);
2771 363379 : def;
2772 184884 : def = DF_REF_NEXT_REG (def))
2773 184884 : if (bitmap_bit_p (candidates, DF_REF_INSN_UID (def)))
2774 : {
2775 56708 : if (dump_file)
2776 0 : fprintf (dump_file, "Removing insn %d from candidates list\n",
2777 0 : DF_REF_INSN_UID (def));
2778 :
2779 56708 : bitmap_clear_bit (candidates, DF_REF_INSN_UID (def));
2780 56708 : changed = true;
2781 : }
2782 :
2783 178495 : for (df_ref ref = DF_REG_USE_CHAIN (id);
2784 528973 : ref;
2785 350478 : ref = DF_REF_NEXT_REG (ref))
2786 350478 : if (bitmap_bit_p (candidates, DF_REF_INSN_UID (ref)))
2787 : {
2788 16616 : if (dump_file)
2789 0 : fprintf (dump_file, "Removing insn %d from candidates list\n",
2790 0 : DF_REF_INSN_UID (ref));
2791 :
2792 16616 : bitmap_clear_bit (candidates, DF_REF_INSN_UID (ref));
2793 16616 : changed = true;
2794 : }
2795 : }
2796 : } while (changed);
2797 :
2798 850441 : BITMAP_FREE (regs);
2799 850441 : }
2800 :
2801 : /* Main STV pass function. Find and convert scalar
2802 : instructions into vector mode when profitable. */
2803 :
2804 : static unsigned int
2805 1827197 : convert_scalars_to_vector (bool timode_p)
2806 : {
2807 1827197 : basic_block bb;
2808 1827197 : int converted_insns = 0;
2809 1827197 : auto_vec<rtx_insn *> control_flow_insns;
2810 :
2811 1827197 : bitmap_obstack_initialize (NULL);
2812 1827197 : const machine_mode cand_mode[3] = { SImode, DImode, TImode };
2813 1827197 : const machine_mode cand_vmode[3] = { V4SImode, V2DImode, V1TImode };
2814 5481591 : bitmap_head candidates[3]; /* { SImode, DImode, TImode } */
2815 7308788 : for (unsigned i = 0; i < 3; ++i)
2816 5481591 : bitmap_initialize (&candidates[i], &bitmap_default_obstack);
2817 :
2818 1827197 : calculate_dominance_info (CDI_DOMINATORS);
2819 1827197 : df_set_flags (DF_DEFER_INSN_RESCAN | DF_RD_PRUNE_DEAD_DEFS);
2820 1827197 : df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN);
2821 1827197 : df_analyze ();
2822 :
2823 : /* Find all instructions we want to convert into vector mode. */
2824 1827197 : if (dump_file)
2825 44 : fprintf (dump_file, "Searching for mode conversion candidates...\n");
2826 :
2827 20231069 : FOR_EACH_BB_FN (bb, cfun)
2828 : {
2829 18403872 : rtx_insn *insn;
2830 252837785 : FOR_BB_INSNS (bb, insn)
2831 234433913 : if (timode_p
2832 234433913 : && timode_scalar_to_vector_candidate_p (insn))
2833 : {
2834 1122567 : if (dump_file)
2835 0 : fprintf (dump_file, " insn %d is marked as a TImode candidate\n",
2836 0 : INSN_UID (insn));
2837 :
2838 1122567 : bitmap_set_bit (&candidates[2], INSN_UID (insn));
2839 : }
2840 233311346 : else if (!timode_p)
2841 : {
2842 : /* Check {SI,DI}mode. */
2843 363884178 : for (unsigned i = 0; i <= 1; ++i)
2844 249381201 : if (general_scalar_to_vector_candidate_p (insn, cand_mode[i]))
2845 : {
2846 11959288 : if (dump_file)
2847 554 : fprintf (dump_file, " insn %d is marked as a %s candidate\n",
2848 277 : INSN_UID (insn), i == 0 ? "SImode" : "DImode");
2849 :
2850 11959288 : bitmap_set_bit (&candidates[i], INSN_UID (insn));
2851 11959288 : break;
2852 : }
2853 : }
2854 : }
2855 :
2856 1827197 : if (timode_p)
2857 850441 : timode_remove_non_convertible_regs (&candidates[2]);
2858 :
2859 5788137 : for (unsigned i = 0; i <= 2; ++i)
2860 4614048 : if (!bitmap_empty_p (&candidates[i]))
2861 : break;
2862 3960940 : else if (i == 2 && dump_file)
2863 23 : fprintf (dump_file, "There are no candidates for optimization.\n");
2864 :
2865 7308788 : for (unsigned i = 0; i <= 2; ++i)
2866 : {
2867 5481591 : auto_bitmap disallowed;
2868 5481591 : bitmap_tree_view (&candidates[i]);
2869 17571322 : while (!bitmap_empty_p (&candidates[i]))
2870 : {
2871 6608140 : unsigned uid = bitmap_first_set_bit (&candidates[i]);
2872 6608140 : scalar_chain *chain;
2873 :
2874 6608140 : if (cand_mode[i] == TImode)
2875 527261 : chain = new timode_scalar_chain;
2876 : else
2877 6080879 : chain = new general_scalar_chain (cand_mode[i], cand_vmode[i]);
2878 :
2879 : /* Find instructions chain we want to convert to vector mode.
2880 : Check all uses and definitions to estimate all required
2881 : conversions. */
2882 6608140 : if (chain->build (&candidates[i], uid, disallowed))
2883 : {
2884 6603775 : if (chain->compute_convert_gain ())
2885 659197 : converted_insns += chain->convert ();
2886 5944578 : else if (dump_file)
2887 136 : fprintf (dump_file, "Chain #%d conversion is not profitable\n",
2888 : chain->chain_id);
2889 : }
2890 :
2891 6608140 : rtx_insn* iter_insn;
2892 6608140 : unsigned int ii;
2893 6615284 : FOR_EACH_VEC_ELT (chain->control_flow_insns, ii, iter_insn)
2894 3587 : control_flow_insns.safe_push (iter_insn);
2895 :
2896 6608140 : delete chain;
2897 : }
2898 5481591 : }
2899 :
2900 1827197 : if (dump_file)
2901 44 : fprintf (dump_file, "Total insns converted: %d\n", converted_insns);
2902 :
2903 7308788 : for (unsigned i = 0; i <= 2; ++i)
2904 5481591 : bitmap_release (&candidates[i]);
2905 1827197 : bitmap_obstack_release (NULL);
2906 1827197 : df_process_deferred_rescans ();
2907 :
2908 : /* Conversion means we may have 128bit register spills/fills
2909 : which require aligned stack. */
2910 1827197 : if (converted_insns)
2911 : {
2912 107157 : if (crtl->stack_alignment_needed < 128)
2913 2479 : crtl->stack_alignment_needed = 128;
2914 107157 : if (crtl->stack_alignment_estimated < 128)
2915 223 : crtl->stack_alignment_estimated = 128;
2916 :
2917 107157 : crtl->stack_realign_needed
2918 107157 : = INCOMING_STACK_BOUNDARY < crtl->stack_alignment_estimated;
2919 107157 : crtl->stack_realign_tried = crtl->stack_realign_needed;
2920 :
2921 107157 : crtl->stack_realign_processed = true;
2922 :
2923 107157 : if (!crtl->drap_reg)
2924 : {
2925 106968 : rtx drap_rtx = targetm.calls.get_drap_rtx ();
2926 :
2927 : /* stack_realign_drap and drap_rtx must match. */
2928 106968 : gcc_assert ((stack_realign_drap != 0) == (drap_rtx != NULL));
2929 :
2930 : /* Do nothing if NULL is returned,
2931 : which means DRAP is not needed. */
2932 106968 : if (drap_rtx != NULL)
2933 : {
2934 0 : crtl->args.internal_arg_pointer = drap_rtx;
2935 :
2936 : /* Call fixup_tail_calls to clean up
2937 : REG_EQUIV note if DRAP is needed. */
2938 0 : fixup_tail_calls ();
2939 : }
2940 : }
2941 :
2942 : /* Fix up DECL_RTL/DECL_INCOMING_RTL of arguments. */
2943 107157 : if (TARGET_64BIT)
2944 68576 : for (tree parm = DECL_ARGUMENTS (current_function_decl);
2945 188155 : parm; parm = DECL_CHAIN (parm))
2946 : {
2947 119579 : if (TYPE_MODE (TREE_TYPE (parm)) != TImode)
2948 103400 : continue;
2949 16179 : if (DECL_RTL_SET_P (parm)
2950 32358 : && GET_MODE (DECL_RTL (parm)) == V1TImode)
2951 : {
2952 621 : rtx r = DECL_RTL (parm);
2953 621 : if (REG_P (r))
2954 621 : SET_DECL_RTL (parm, gen_rtx_SUBREG (TImode, r, 0));
2955 : }
2956 16179 : if (DECL_INCOMING_RTL (parm)
2957 16179 : && GET_MODE (DECL_INCOMING_RTL (parm)) == V1TImode)
2958 : {
2959 0 : rtx r = DECL_INCOMING_RTL (parm);
2960 0 : if (REG_P (r))
2961 0 : DECL_INCOMING_RTL (parm) = gen_rtx_SUBREG (TImode, r, 0);
2962 : }
2963 : }
2964 :
2965 1828332 : if (!control_flow_insns.is_empty ())
2966 : {
2967 1135 : free_dominance_info (CDI_DOMINATORS);
2968 :
2969 1135 : unsigned int i;
2970 1135 : rtx_insn* insn;
2971 5857 : FOR_EACH_VEC_ELT (control_flow_insns, i, insn)
2972 3587 : if (control_flow_insn_p (insn))
2973 : {
2974 : /* Split the block after insn. There will be a fallthru
2975 : edge, which is OK so we keep it. We have to create
2976 : the exception edges ourselves. */
2977 3587 : bb = BLOCK_FOR_INSN (insn);
2978 3587 : split_block (bb, insn);
2979 3587 : rtl_make_eh_edge (NULL, bb, BB_END (bb));
2980 : }
2981 : }
2982 : }
2983 :
2984 1827197 : return 0;
2985 1827197 : }
2986 :
2987 : static unsigned int
2988 76028 : rest_of_handle_insert_vzeroupper (void)
2989 : {
2990 : /* vzeroupper instructions are inserted immediately after reload and
2991 : postreload_cse to clean up after it a little bit to account for possible
2992 : spills from 256bit or 512bit registers. The pass reuses mode switching
2993 : infrastructure by re-running mode insertion pass, so disable entities
2994 : that have already been processed. */
2995 532196 : for (int i = 0; i < MAX_386_ENTITIES; i++)
2996 456168 : ix86_optimize_mode_switching[i] = 0;
2997 :
2998 76028 : ix86_optimize_mode_switching[AVX_U128] = 1;
2999 :
3000 : /* Call optimize_mode_switching. */
3001 76028 : g->get_passes ()->execute_pass_mode_switching ();
3002 :
3003 : /* LRA removes all REG_DEAD/REG_UNUSED notes and normally they
3004 : reappear in the IL only at the start of pass_rtl_dse2, which does
3005 : df_note_add_problem (); df_analyze ();
3006 : The vzeroupper is scheduled after postreload_cse pass and mode
3007 : switching computes the notes as well, the problem is that e.g.
3008 : pass_gcse2 doesn't maintain the notes, see PR113059 and
3009 : PR112760. Remove the notes now to restore status quo ante
3010 : until we figure out how to maintain the notes or what else
3011 : to do. */
3012 76028 : basic_block bb;
3013 76028 : rtx_insn *insn;
3014 408302 : FOR_EACH_BB_FN (bb, cfun)
3015 4271457 : FOR_BB_INSNS (bb, insn)
3016 3939183 : if (NONDEBUG_INSN_P (insn))
3017 : {
3018 2109325 : rtx *pnote = ®_NOTES (insn);
3019 3913365 : while (*pnote != 0)
3020 : {
3021 1804040 : if (REG_NOTE_KIND (*pnote) == REG_DEAD
3022 820228 : || REG_NOTE_KIND (*pnote) == REG_UNUSED)
3023 1294894 : *pnote = XEXP (*pnote, 1);
3024 : else
3025 509146 : pnote = &XEXP (*pnote, 1);
3026 : }
3027 : }
3028 :
3029 76028 : df_remove_problem (df_note);
3030 76028 : df_analyze ();
3031 76028 : return 0;
3032 : }
3033 :
3034 : namespace {
3035 :
3036 : const pass_data pass_data_insert_vzeroupper =
3037 : {
3038 : RTL_PASS, /* type */
3039 : "vzeroupper", /* name */
3040 : OPTGROUP_NONE, /* optinfo_flags */
3041 : TV_MACH_DEP, /* tv_id */
3042 : 0, /* properties_required */
3043 : 0, /* properties_provided */
3044 : 0, /* properties_destroyed */
3045 : 0, /* todo_flags_start */
3046 : TODO_df_finish, /* todo_flags_finish */
3047 : };
3048 :
3049 : class pass_insert_vzeroupper : public rtl_opt_pass
3050 : {
3051 : public:
3052 294245 : pass_insert_vzeroupper(gcc::context *ctxt)
3053 588490 : : rtl_opt_pass(pass_data_insert_vzeroupper, ctxt)
3054 : {}
3055 :
3056 : /* opt_pass methods: */
3057 1511981 : bool gate (function *) final override
3058 : {
3059 1511981 : return TARGET_AVX && TARGET_VZEROUPPER;
3060 : }
3061 :
3062 76028 : unsigned int execute (function *) final override
3063 : {
3064 76028 : return rest_of_handle_insert_vzeroupper ();
3065 : }
3066 :
3067 : }; // class pass_insert_vzeroupper
3068 :
3069 : const pass_data pass_data_stv =
3070 : {
3071 : RTL_PASS, /* type */
3072 : "stv", /* name */
3073 : OPTGROUP_NONE, /* optinfo_flags */
3074 : TV_MACH_DEP, /* tv_id */
3075 : 0, /* properties_required */
3076 : 0, /* properties_provided */
3077 : 0, /* properties_destroyed */
3078 : 0, /* todo_flags_start */
3079 : TODO_df_finish, /* todo_flags_finish */
3080 : };
3081 :
3082 : class pass_stv : public rtl_opt_pass
3083 : {
3084 : public:
3085 588490 : pass_stv (gcc::context *ctxt)
3086 : : rtl_opt_pass (pass_data_stv, ctxt),
3087 1176980 : timode_p (false)
3088 : {}
3089 :
3090 : /* opt_pass methods: */
3091 3023962 : bool gate (function *) final override
3092 : {
3093 1511981 : return ((!timode_p || TARGET_64BIT)
3094 4409307 : && TARGET_STV && TARGET_SSE2 && optimize > 1);
3095 : }
3096 :
3097 1827197 : unsigned int execute (function *) final override
3098 : {
3099 1827197 : return convert_scalars_to_vector (timode_p);
3100 : }
3101 :
3102 294245 : opt_pass *clone () final override
3103 : {
3104 294245 : return new pass_stv (m_ctxt);
3105 : }
3106 :
3107 588490 : void set_pass_param (unsigned int n, bool param) final override
3108 : {
3109 588490 : gcc_assert (n == 0);
3110 588490 : timode_p = param;
3111 588490 : }
3112 :
3113 : private:
3114 : bool timode_p;
3115 : }; // class pass_stv
3116 :
3117 : } // anon namespace
3118 :
3119 : rtl_opt_pass *
3120 294245 : make_pass_insert_vzeroupper (gcc::context *ctxt)
3121 : {
3122 294245 : return new pass_insert_vzeroupper (ctxt);
3123 : }
3124 :
3125 : rtl_opt_pass *
3126 294245 : make_pass_stv (gcc::context *ctxt)
3127 : {
3128 294245 : return new pass_stv (ctxt);
3129 : }
3130 :
3131 : /* Inserting ENDBR and pseudo patchable-area instructions. */
3132 :
3133 : static void
3134 206495 : rest_of_insert_endbr_and_patchable_area (bool need_endbr,
3135 : unsigned int patchable_area_size)
3136 : {
3137 206495 : rtx endbr;
3138 206495 : rtx_insn *insn;
3139 206495 : rtx_insn *endbr_insn = NULL;
3140 206495 : basic_block bb;
3141 :
3142 206495 : if (need_endbr)
3143 : {
3144 : /* Currently emit EB if it's a tracking function, i.e. 'nocf_check'
3145 : is absent among function attributes. Later an optimization will
3146 : be introduced to make analysis if an address of a static function
3147 : is taken. A static function whose address is not taken will get
3148 : a nocf_check attribute. This will allow to reduce the number of
3149 : EB. */
3150 206450 : if (!lookup_attribute ("nocf_check",
3151 206450 : TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl)))
3152 206432 : && (!flag_manual_endbr
3153 8 : || lookup_attribute ("cf_check",
3154 8 : DECL_ATTRIBUTES (cfun->decl)))
3155 412881 : && (!cgraph_node::get (cfun->decl)->only_called_directly_p ()
3156 29951 : || ix86_cmodel == CM_LARGE
3157 29950 : || ix86_cmodel == CM_LARGE_PIC
3158 29949 : || flag_force_indirect_call
3159 29949 : || (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3160 : && DECL_DLLIMPORT_P (cfun->decl))))
3161 : {
3162 176483 : if (crtl->profile && flag_fentry)
3163 : {
3164 : /* Queue ENDBR insertion to x86_function_profiler.
3165 : NB: Any patchable-area insn will be inserted after
3166 : ENDBR. */
3167 6 : cfun->machine->insn_queued_at_entrance = TYPE_ENDBR;
3168 : }
3169 : else
3170 : {
3171 176477 : endbr = gen_nop_endbr ();
3172 176477 : bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
3173 176477 : rtx_insn *insn = BB_HEAD (bb);
3174 176477 : endbr_insn = emit_insn_before (endbr, insn);
3175 : }
3176 : }
3177 : }
3178 :
3179 206495 : if (patchable_area_size)
3180 : {
3181 51 : if (crtl->profile && flag_fentry)
3182 : {
3183 : /* Queue patchable-area insertion to x86_function_profiler.
3184 : NB: If there is a queued ENDBR, x86_function_profiler
3185 : will also handle patchable-area. */
3186 2 : if (!cfun->machine->insn_queued_at_entrance)
3187 1 : cfun->machine->insn_queued_at_entrance = TYPE_PATCHABLE_AREA;
3188 : }
3189 : else
3190 : {
3191 49 : rtx patchable_area
3192 49 : = gen_patchable_area (GEN_INT (patchable_area_size),
3193 49 : GEN_INT (crtl->patch_area_entry == 0));
3194 49 : if (endbr_insn)
3195 3 : emit_insn_after (patchable_area, endbr_insn);
3196 : else
3197 : {
3198 46 : bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
3199 46 : insn = BB_HEAD (bb);
3200 46 : emit_insn_before (patchable_area, insn);
3201 : }
3202 : }
3203 : }
3204 :
3205 206495 : if (!need_endbr)
3206 : return;
3207 :
3208 206450 : bb = 0;
3209 4208429 : FOR_EACH_BB_FN (bb, cfun)
3210 : {
3211 79186911 : for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
3212 75184932 : insn = NEXT_INSN (insn))
3213 : {
3214 75184932 : if (CALL_P (insn))
3215 : {
3216 1496982 : need_endbr = find_reg_note (insn, REG_SETJMP, NULL) != NULL;
3217 1496982 : if (!need_endbr && !SIBLING_CALL_P (insn))
3218 : {
3219 1444388 : rtx call = get_call_rtx_from (insn);
3220 1444388 : rtx fnaddr = XEXP (call, 0);
3221 1444388 : tree fndecl = NULL_TREE;
3222 :
3223 : /* Also generate ENDBRANCH for non-tail call which
3224 : may return via indirect branch. */
3225 1444388 : if (SYMBOL_REF_P (XEXP (fnaddr, 0)))
3226 1384014 : fndecl = SYMBOL_REF_DECL (XEXP (fnaddr, 0));
3227 1384014 : if (fndecl == NULL_TREE)
3228 60742 : fndecl = MEM_EXPR (fnaddr);
3229 60742 : if (fndecl
3230 1441978 : && TREE_CODE (TREE_TYPE (fndecl)) != FUNCTION_TYPE
3231 608896 : && TREE_CODE (TREE_TYPE (fndecl)) != METHOD_TYPE)
3232 : fndecl = NULL_TREE;
3233 1444388 : if (fndecl && TYPE_ARG_TYPES (TREE_TYPE (fndecl)))
3234 : {
3235 1399534 : tree fntype = TREE_TYPE (fndecl);
3236 1399534 : if (lookup_attribute ("indirect_return",
3237 1399534 : TYPE_ATTRIBUTES (fntype)))
3238 : need_endbr = true;
3239 : }
3240 : }
3241 1496970 : if (!need_endbr)
3242 1496962 : continue;
3243 : /* Generate ENDBRANCH after CALL, which can return more than
3244 : twice, setjmp-like functions. */
3245 :
3246 20 : endbr = gen_nop_endbr ();
3247 20 : emit_insn_after_setloc (endbr, insn, INSN_LOCATION (insn));
3248 20 : continue;
3249 20 : }
3250 :
3251 73687950 : if (JUMP_P (insn) && flag_cet_switch)
3252 : {
3253 9 : rtx target = JUMP_LABEL (insn);
3254 9 : if (target == NULL_RTX || ANY_RETURN_P (target))
3255 5 : continue;
3256 :
3257 : /* Check the jump is a switch table. */
3258 4 : rtx_insn *label = as_a<rtx_insn *> (target);
3259 4 : rtx_insn *table = next_insn (label);
3260 4 : if (table == NULL_RTX || !JUMP_TABLE_DATA_P (table))
3261 2 : continue;
3262 :
3263 : /* For the indirect jump find out all places it jumps and insert
3264 : ENDBRANCH there. It should be done under a special flag to
3265 : control ENDBRANCH generation for switch stmts. */
3266 2 : edge_iterator ei;
3267 2 : edge e;
3268 2 : basic_block dest_blk;
3269 :
3270 24 : FOR_EACH_EDGE (e, ei, bb->succs)
3271 : {
3272 22 : rtx_insn *insn;
3273 :
3274 22 : dest_blk = e->dest;
3275 22 : insn = BB_HEAD (dest_blk);
3276 22 : gcc_assert (LABEL_P (insn));
3277 22 : endbr = gen_nop_endbr ();
3278 22 : emit_insn_after (endbr, insn);
3279 : }
3280 2 : continue;
3281 2 : }
3282 :
3283 73687941 : if (LABEL_P (insn) && LABEL_PRESERVE_P (insn))
3284 : {
3285 153675 : endbr = gen_nop_endbr ();
3286 153675 : emit_insn_after (endbr, insn);
3287 153675 : continue;
3288 : }
3289 : }
3290 : }
3291 :
3292 : return;
3293 : }
3294 :
3295 : namespace {
3296 :
3297 : const pass_data pass_data_insert_endbr_and_patchable_area =
3298 : {
3299 : RTL_PASS, /* type. */
3300 : "endbr_and_patchable_area", /* name. */
3301 : OPTGROUP_NONE, /* optinfo_flags. */
3302 : TV_MACH_DEP, /* tv_id. */
3303 : 0, /* properties_required. */
3304 : 0, /* properties_provided. */
3305 : 0, /* properties_destroyed. */
3306 : 0, /* todo_flags_start. */
3307 : 0, /* todo_flags_finish. */
3308 : };
3309 :
3310 : class pass_insert_endbr_and_patchable_area : public rtl_opt_pass
3311 : {
3312 : public:
3313 294245 : pass_insert_endbr_and_patchable_area (gcc::context *ctxt)
3314 588490 : : rtl_opt_pass (pass_data_insert_endbr_and_patchable_area, ctxt)
3315 : {}
3316 :
3317 : /* opt_pass methods: */
3318 1511981 : bool gate (function *) final override
3319 : {
3320 1511981 : need_endbr = (flag_cf_protection & CF_BRANCH) != 0;
3321 1511981 : patchable_area_size = crtl->patch_area_size - crtl->patch_area_entry;
3322 1511981 : return need_endbr || patchable_area_size;
3323 : }
3324 :
3325 206495 : unsigned int execute (function *) final override
3326 : {
3327 206495 : timevar_push (TV_MACH_DEP);
3328 206495 : rest_of_insert_endbr_and_patchable_area (need_endbr,
3329 : patchable_area_size);
3330 206495 : timevar_pop (TV_MACH_DEP);
3331 206495 : return 0;
3332 : }
3333 :
3334 : private:
3335 : bool need_endbr;
3336 : unsigned int patchable_area_size;
3337 : }; // class pass_insert_endbr_and_patchable_area
3338 :
3339 : } // anon namespace
3340 :
3341 : rtl_opt_pass *
3342 294245 : make_pass_insert_endbr_and_patchable_area (gcc::context *ctxt)
3343 : {
3344 294245 : return new pass_insert_endbr_and_patchable_area (ctxt);
3345 : }
3346 :
3347 : bool
3348 6174612 : ix86_rpad_gate ()
3349 : {
3350 6174612 : return (TARGET_AVX
3351 389855 : && TARGET_SSE_PARTIAL_REG_DEPENDENCY
3352 291950 : && TARGET_SSE_MATH
3353 291656 : && optimize
3354 6461060 : && optimize_function_for_speed_p (cfun));
3355 : }
3356 :
3357 : enum x86_cse_kind
3358 : {
3359 : X86_CSE_CONST0_VECTOR,
3360 : X86_CSE_CONSTM1_VECTOR,
3361 : X86_CSE_CONST_VECTOR,
3362 : X86_CSE_VEC_DUP,
3363 : X86_CSE_TLS_GD,
3364 : X86_CSE_TLS_LD_BASE,
3365 : X86_CSE_TLSDESC
3366 : };
3367 :
3368 159271 : struct redundant_pattern
3369 : {
3370 : /* Bitmap of basic blocks with broadcast instructions. */
3371 : auto_bitmap bbs;
3372 : /* Bitmap of broadcast instructions. */
3373 : auto_bitmap insns;
3374 : /* The broadcast inner scalar. */
3375 : rtx val;
3376 : /* The actual redundant source value for UNSPEC_TLSDESC. */
3377 : rtx tlsdesc_val;
3378 : /* The inner scalar mode. */
3379 : machine_mode mode;
3380 : /* The destination mode which can be changed to the integer mode of
3381 : the same time. */
3382 : machine_mode dest_mode;
3383 : /* The instruction which sets the inner scalar. Nullptr if the inner
3384 : scalar is applied to the whole function, instead of within the same
3385 : block. */
3386 : rtx_insn *def_insn;
3387 : /* The widest broadcast source. */
3388 : rtx broadcast_source;
3389 : /* The widest broadcast register. */
3390 : rtx broadcast_reg;
3391 : /* The basic block of the broadcast instruction. */
3392 : basic_block bb;
3393 : /* The number of broadcast instructions with the same inner scalar. */
3394 : unsigned HOST_WIDE_INT count;
3395 : /* The threshold of broadcast instructions with the same inner
3396 : scalar. */
3397 : unsigned int threshold;
3398 : /* The widest broadcast size in bytes. */
3399 : unsigned int size;
3400 : /* Load kind. */
3401 : x86_cse_kind kind;
3402 : };
3403 :
3404 : /* Generate a vector set, DEST = SRC, at entry of the nearest dominator
3405 : for basic block map BBS, which is in the fake loop that contains the
3406 : whole function, so that there is only a single vector set in the
3407 : whole function. If not nullptr, LOAD is a pointer to the load. */
3408 :
3409 : static void
3410 45090 : ix86_place_single_vector_set (rtx dest, rtx src, bitmap bbs,
3411 : redundant_pattern *load = nullptr)
3412 : {
3413 45090 : basic_block bb = nearest_common_dominator_for_set (CDI_DOMINATORS, bbs);
3414 : /* For X86_CSE_VEC_DUP and X86_CSE_CONST_VECTOR, don't place the vector
3415 : set outside of the loop to avoid extra spills. */
3416 45090 : if (!load
3417 44066 : || (load->kind != X86_CSE_VEC_DUP
3418 44066 : && load->kind != X86_CSE_CONST_VECTOR))
3419 : {
3420 25025 : while (bb->loop_father->latch
3421 25025 : != EXIT_BLOCK_PTR_FOR_FN (cfun))
3422 1452 : bb = get_immediate_dominator (CDI_DOMINATORS,
3423 : bb->loop_father->header);
3424 : }
3425 :
3426 45090 : if (CONST_INT_P (src))
3427 11144 : dest = gen_rtx_SUBREG (load->dest_mode, dest, 0);
3428 33946 : else if (CONST_VECTOR_P (src))
3429 : {
3430 : /* The only possible CONST_VECTORs of SRC are CONST0_RTX and
3431 : CONSTM1_RTX. Otherwise,
3432 :
3433 : rtx set = gen_rtx_SET (dest, src);
3434 :
3435 : won't be a valid instruction. CONST0_RTX always works. It
3436 : can comes from:
3437 :
3438 : 1. remove_partial_avx_dependency with LOAD == NULL.
3439 : 2. X86_CSE_VEC_DUP with
3440 :
3441 : (insn 48 58 16 3 (set (reg:V4HI 123)
3442 : (const_vector:V4HI [
3443 : (const_int 0 [0]) repeated x4
3444 : ])) 2065 {*movv4hi_internal} (nil))
3445 :
3446 : 3. X86_CSE_CONST0_VECTOR.
3447 : */
3448 23573 : machine_mode mode = GET_MODE (dest);
3449 23573 : if (!(src == CONST0_RTX (mode)
3450 1668 : || (src == CONSTM1_RTX (mode)
3451 1668 : && load->kind == X86_CSE_CONSTM1_VECTOR)))
3452 0 : gcc_unreachable ();
3453 : }
3454 45090 : rtx set = gen_rtx_SET (dest, src);
3455 :
3456 45090 : rtx_insn *insn = BB_HEAD (bb);
3457 180559 : while (insn && !NONDEBUG_INSN_P (insn))
3458 : {
3459 135473 : if (insn == BB_END (bb))
3460 : {
3461 : insn = NULL;
3462 : break;
3463 : }
3464 135469 : insn = NEXT_INSN (insn);
3465 : }
3466 :
3467 45090 : rtx_insn *set_insn;
3468 45090 : if (insn == BB_HEAD (bb))
3469 : {
3470 0 : set_insn = emit_insn_before (set, insn);
3471 0 : if (dump_file)
3472 : {
3473 0 : fprintf (dump_file, "\nPlace:\n\n");
3474 0 : print_rtl_single (dump_file, set_insn);
3475 0 : fprintf (dump_file, "\nbefore:\n\n");
3476 0 : print_rtl_single (dump_file, insn);
3477 0 : fprintf (dump_file, "\n");
3478 : }
3479 : }
3480 : else
3481 : {
3482 45090 : rtx_insn *after = insn ? PREV_INSN (insn) : BB_END (bb);
3483 45090 : set_insn = emit_insn_after (set, after);
3484 45090 : if (dump_file)
3485 : {
3486 0 : fprintf (dump_file, "\nPlace:\n\n");
3487 0 : print_rtl_single (dump_file, set_insn);
3488 0 : fprintf (dump_file, "\nafter:\n\n");
3489 0 : print_rtl_single (dump_file, after);
3490 0 : fprintf (dump_file, "\n");
3491 : }
3492 : }
3493 :
3494 45090 : if (load && load->kind == X86_CSE_VEC_DUP)
3495 : {
3496 : /* Get the source from LOAD as (reg:SI 99) in
3497 :
3498 : (vec_duplicate:V4SI (reg:SI 99))
3499 :
3500 : */
3501 10373 : rtx inner_scalar = load->val;
3502 : /* Set the source in (vec_duplicate:V4SI (reg:SI 99)). */
3503 10373 : rtx reg = XEXP (src, 0);
3504 10373 : machine_mode reg_mode = GET_MODE (reg);
3505 10373 : if (reg_mode != GET_MODE (inner_scalar))
3506 : {
3507 10033 : if (REG_P (inner_scalar) || MEM_P (inner_scalar))
3508 0 : inner_scalar = gen_rtx_SUBREG (reg_mode, inner_scalar, 0);
3509 10033 : else if (!SCALAR_INT_MODE_P (reg_mode))
3510 : {
3511 : /* For non-int load with integer constant, generate
3512 :
3513 : (set (subreg:SI (reg/v:SF 105 [ f ]) 0)
3514 : (const_int 1313486336 [0x4e4a3600]))
3515 :
3516 : */
3517 1 : gcc_assert (CONST_INT_P (inner_scalar));
3518 1 : unsigned int bits = GET_MODE_BITSIZE (reg_mode);
3519 1 : machine_mode mode = int_mode_for_size (bits, 0).require ();
3520 1 : reg = gen_rtx_SUBREG (mode, reg, 0);
3521 : }
3522 : }
3523 10373 : rtx set = gen_rtx_SET (reg, inner_scalar);
3524 10373 : insn = emit_insn_before (set, set_insn);
3525 10373 : if (dump_file)
3526 : {
3527 0 : fprintf (dump_file, "\nAdd:\n\n");
3528 0 : print_rtl_single (dump_file, insn);
3529 0 : fprintf (dump_file, "\nbefore:\n\n");
3530 0 : print_rtl_single (dump_file, set_insn);
3531 0 : fprintf (dump_file, "\n");
3532 : }
3533 : }
3534 45090 : }
3535 :
3536 : /* At entry of the nearest common dominator for basic blocks with
3537 : conversions/rcp/sqrt/rsqrt/round, generate a single
3538 : vxorps %xmmN, %xmmN, %xmmN
3539 : for all
3540 : vcvtss2sd op, %xmmN, %xmmX
3541 : vcvtsd2ss op, %xmmN, %xmmX
3542 : vcvtsi2ss op, %xmmN, %xmmX
3543 : vcvtsi2sd op, %xmmN, %xmmX
3544 :
3545 : NB: We want to generate only a single vxorps to cover the whole
3546 : function. The LCM algorithm isn't appropriate here since it may
3547 : place a vxorps inside the loop. */
3548 :
3549 : static unsigned int
3550 33661 : remove_partial_avx_dependency (void)
3551 : {
3552 33661 : timevar_push (TV_MACH_DEP);
3553 :
3554 33661 : bitmap_obstack_initialize (NULL);
3555 33661 : bitmap convert_bbs = BITMAP_ALLOC (NULL);
3556 :
3557 33661 : basic_block bb;
3558 33661 : rtx_insn *insn, *set_insn;
3559 33661 : rtx set;
3560 33661 : rtx v4sf_const0 = NULL_RTX;
3561 :
3562 33661 : auto_vec<rtx_insn *> control_flow_insns;
3563 :
3564 : /* We create invalid RTL initially so defer rescans. */
3565 33661 : df_set_flags (DF_DEFER_INSN_RESCAN);
3566 :
3567 311455 : FOR_EACH_BB_FN (bb, cfun)
3568 : {
3569 3489202 : FOR_BB_INSNS (bb, insn)
3570 : {
3571 3211408 : if (!NONDEBUG_INSN_P (insn))
3572 1426202 : continue;
3573 :
3574 1785206 : set = single_set (insn);
3575 1785206 : if (!set)
3576 71515 : continue;
3577 :
3578 1713691 : if (get_attr_avx_partial_xmm_update (insn)
3579 : != AVX_PARTIAL_XMM_UPDATE_TRUE)
3580 1710506 : continue;
3581 :
3582 : /* Convert PARTIAL_XMM_UPDATE_TRUE insns, DF -> SF, SF -> DF,
3583 : SI -> SF, SI -> DF, DI -> SF, DI -> DF, sqrt, rsqrt, rcp,
3584 : round, to vec_dup and vec_merge with subreg. */
3585 3185 : rtx src = SET_SRC (set);
3586 3185 : rtx dest = SET_DEST (set);
3587 3185 : machine_mode dest_mode = GET_MODE (dest);
3588 3185 : bool convert_p = false;
3589 3185 : switch (GET_CODE (src))
3590 : {
3591 3120 : case FLOAT:
3592 3120 : case FLOAT_EXTEND:
3593 3120 : case FLOAT_TRUNCATE:
3594 3120 : case UNSIGNED_FLOAT:
3595 3120 : convert_p = true;
3596 3120 : break;
3597 : default:
3598 : break;
3599 : }
3600 :
3601 : /* Only handle conversion here. */
3602 3120 : machine_mode src_mode
3603 3120 : = convert_p ? GET_MODE (XEXP (src, 0)) : VOIDmode;
3604 3120 : switch (src_mode)
3605 : {
3606 153 : case E_SFmode:
3607 153 : case E_DFmode:
3608 153 : if (TARGET_USE_VECTOR_FP_CONVERTS
3609 147 : || !TARGET_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY)
3610 8 : continue;
3611 : break;
3612 2967 : case E_SImode:
3613 2967 : case E_DImode:
3614 2967 : if (TARGET_USE_VECTOR_CONVERTS
3615 2955 : || !TARGET_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY)
3616 14 : continue;
3617 : break;
3618 65 : case E_VOIDmode:
3619 65 : gcc_assert (!convert_p);
3620 : break;
3621 0 : default:
3622 0 : gcc_unreachable ();
3623 : }
3624 :
3625 3163 : if (!v4sf_const0)
3626 1024 : v4sf_const0 = gen_reg_rtx (V4SFmode);
3627 :
3628 3163 : rtx zero;
3629 3163 : machine_mode dest_vecmode;
3630 3163 : switch (dest_mode)
3631 : {
3632 50 : case E_HFmode:
3633 50 : dest_vecmode = V8HFmode;
3634 50 : zero = gen_rtx_SUBREG (V8HFmode, v4sf_const0, 0);
3635 50 : break;
3636 : case E_SFmode:
3637 : dest_vecmode = V4SFmode;
3638 : zero = v4sf_const0;
3639 : break;
3640 1185 : case E_DFmode:
3641 1185 : dest_vecmode = V2DFmode;
3642 1185 : zero = gen_rtx_SUBREG (V2DFmode, v4sf_const0, 0);
3643 1185 : break;
3644 0 : default:
3645 0 : gcc_unreachable ();
3646 : }
3647 :
3648 : /* Change source to vector mode. */
3649 3163 : src = gen_rtx_VEC_DUPLICATE (dest_vecmode, src);
3650 3163 : src = gen_rtx_VEC_MERGE (dest_vecmode, src, zero,
3651 : GEN_INT (HOST_WIDE_INT_1U));
3652 : /* Change destination to vector mode. */
3653 3163 : rtx vec = gen_reg_rtx (dest_vecmode);
3654 : /* Generate an XMM vector SET. */
3655 3163 : set = gen_rtx_SET (vec, src);
3656 3163 : set_insn = emit_insn_before (set, insn);
3657 :
3658 3163 : if (cfun->can_throw_non_call_exceptions)
3659 : {
3660 : /* Handle REG_EH_REGION note. */
3661 0 : rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3662 0 : if (note)
3663 : {
3664 0 : control_flow_insns.safe_push (set_insn);
3665 0 : add_reg_note (set_insn, REG_EH_REGION, XEXP (note, 0));
3666 : }
3667 : }
3668 :
3669 3163 : src = gen_rtx_SUBREG (dest_mode, vec, 0);
3670 3163 : set = gen_rtx_SET (dest, src);
3671 :
3672 : /* Drop possible dead definitions. */
3673 3163 : PATTERN (insn) = set;
3674 :
3675 3163 : INSN_CODE (insn) = -1;
3676 3163 : recog_memoized (insn);
3677 3163 : df_insn_rescan (insn);
3678 3163 : bitmap_set_bit (convert_bbs, bb->index);
3679 : }
3680 : }
3681 :
3682 33661 : if (v4sf_const0)
3683 : {
3684 : /* (Re-)discover loops so that bb->loop_father can be used in the
3685 : analysis below. */
3686 1024 : calculate_dominance_info (CDI_DOMINATORS);
3687 1024 : loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
3688 :
3689 1024 : ix86_place_single_vector_set (v4sf_const0,
3690 : CONST0_RTX (V4SFmode),
3691 : convert_bbs);
3692 :
3693 1024 : loop_optimizer_finalize ();
3694 :
3695 33661 : if (!control_flow_insns.is_empty ())
3696 : {
3697 0 : free_dominance_info (CDI_DOMINATORS);
3698 :
3699 0 : unsigned int i;
3700 0 : FOR_EACH_VEC_ELT (control_flow_insns, i, insn)
3701 0 : if (control_flow_insn_p (insn))
3702 : {
3703 : /* Split the block after insn. There will be a fallthru
3704 : edge, which is OK so we keep it. We have to create
3705 : the exception edges ourselves. */
3706 0 : bb = BLOCK_FOR_INSN (insn);
3707 0 : split_block (bb, insn);
3708 0 : rtl_make_eh_edge (NULL, bb, BB_END (bb));
3709 : }
3710 : }
3711 : }
3712 :
3713 33661 : df_process_deferred_rescans ();
3714 33661 : df_clear_flags (DF_DEFER_INSN_RESCAN);
3715 33661 : bitmap_obstack_release (NULL);
3716 33661 : BITMAP_FREE (convert_bbs);
3717 :
3718 33661 : timevar_pop (TV_MACH_DEP);
3719 33661 : return 0;
3720 33661 : }
3721 :
3722 : namespace {
3723 :
3724 : const pass_data pass_data_remove_partial_avx_dependency =
3725 : {
3726 : RTL_PASS, /* type */
3727 : "rpad", /* name */
3728 : OPTGROUP_NONE, /* optinfo_flags */
3729 : TV_MACH_DEP, /* tv_id */
3730 : 0, /* properties_required */
3731 : 0, /* properties_provided */
3732 : 0, /* properties_destroyed */
3733 : 0, /* todo_flags_start */
3734 : 0, /* todo_flags_finish */
3735 : };
3736 :
3737 : class pass_remove_partial_avx_dependency : public rtl_opt_pass
3738 : {
3739 : public:
3740 294245 : pass_remove_partial_avx_dependency (gcc::context *ctxt)
3741 588490 : : rtl_opt_pass (pass_data_remove_partial_avx_dependency, ctxt)
3742 : {}
3743 :
3744 : /* opt_pass methods: */
3745 1511981 : bool gate (function *) final override
3746 : {
3747 1511981 : return ix86_rpad_gate ();
3748 : }
3749 :
3750 33661 : unsigned int execute (function *) final override
3751 : {
3752 33661 : return remove_partial_avx_dependency ();
3753 : }
3754 : }; // class pass_rpad
3755 :
3756 : } // anon namespace
3757 :
3758 : rtl_opt_pass *
3759 294245 : make_pass_remove_partial_avx_dependency (gcc::context *ctxt)
3760 : {
3761 294245 : return new pass_remove_partial_avx_dependency (ctxt);
3762 : }
3763 :
3764 : /* Return a machine mode suitable for vector SIZE with SMODE inner
3765 : mode. */
3766 :
3767 : static machine_mode
3768 66092 : ix86_get_vector_cse_mode (unsigned int size, machine_mode smode)
3769 : {
3770 : /* Use the inner scalar mode of vector broadcast source in:
3771 :
3772 : (set (reg:V8DF 394)
3773 : (vec_duplicate:V8DF (reg:V2DF 190 [ alpha ])))
3774 :
3775 : to compute the vector mode for broadcast from vector source.
3776 : */
3777 66092 : if (VECTOR_MODE_P (smode))
3778 31677 : smode = GET_MODE_INNER (smode);
3779 66092 : scalar_mode s_mode = as_a <scalar_mode> (smode);
3780 132184 : poly_uint64 nunits = size / GET_MODE_SIZE (smode);
3781 66092 : machine_mode mode = mode_for_vector (s_mode, nunits).require ();
3782 66092 : return mode;
3783 : }
3784 :
3785 : /* Replace the source operand of instructions in VECTOR_INSNS with
3786 : VECTOR_CONST in VECTOR_MODE. */
3787 :
3788 : static void
3789 65404 : replace_vector_const (machine_mode vector_mode, rtx vector_const,
3790 : auto_bitmap &vector_insns,
3791 : machine_mode scalar_mode)
3792 : {
3793 65404 : bitmap_iterator bi;
3794 65404 : unsigned int id;
3795 :
3796 230268 : EXECUTE_IF_SET_IN_BITMAP (vector_insns, 0, id, bi)
3797 : {
3798 164864 : rtx_insn *insn = DF_INSN_UID_GET (id)->insn;
3799 :
3800 : /* Get the single SET instruction. */
3801 164864 : rtx set = single_set (insn);
3802 164864 : rtx src = SET_SRC (set);
3803 164864 : rtx dest = SET_DEST (set);
3804 164864 : machine_mode mode = GET_MODE (dest);
3805 :
3806 164864 : rtx replace;
3807 : /* Replace the source operand with VECTOR_CONST. */
3808 164864 : if (SUBREG_P (src)
3809 164864 : || mode == vector_mode
3810 62205 : || CONST_INT_P (vector_const))
3811 : replace = vector_const;
3812 : else
3813 : {
3814 62198 : unsigned int size = GET_MODE_SIZE (mode);
3815 62198 : if (size < ix86_regmode_natural_size (mode))
3816 : {
3817 : /* If the mode size is smaller than its natural size,
3818 : first insert an extra move with a QI vector SUBREG
3819 : of the same size to avoid validate_subreg failure. */
3820 688 : machine_mode vmode
3821 688 : = ix86_get_vector_cse_mode (size, scalar_mode);
3822 688 : rtx vreg;
3823 688 : if (mode == vmode)
3824 : vreg = vector_const;
3825 : else
3826 : {
3827 146 : vreg = gen_reg_rtx (vmode);
3828 146 : rtx vsubreg = gen_rtx_SUBREG (vmode, vector_const, 0);
3829 146 : rtx pat = gen_rtx_SET (vreg, vsubreg);
3830 146 : rtx_insn *vinsn = emit_insn_before (pat, insn);
3831 146 : if (dump_file)
3832 : {
3833 0 : fprintf (dump_file, "\nInsert an extra move:\n\n");
3834 0 : print_rtl_single (dump_file, vinsn);
3835 0 : fprintf (dump_file, "\nbefore:\n\n");
3836 0 : print_rtl_single (dump_file, insn);
3837 0 : fprintf (dump_file, "\n");
3838 : }
3839 : }
3840 688 : replace = gen_rtx_SUBREG (mode, vreg, 0);
3841 : }
3842 : else
3843 61510 : replace = gen_rtx_SUBREG (mode, vector_const, 0);
3844 : }
3845 :
3846 164864 : if (dump_file)
3847 : {
3848 0 : fprintf (dump_file, "\nReplace:\n\n");
3849 0 : print_rtl_single (dump_file, insn);
3850 : }
3851 164864 : SET_SRC (set) = replace;
3852 164864 : if (CONST_INT_P (replace))
3853 : {
3854 23636 : dest = gen_lowpart (scalar_mode, dest);
3855 23636 : SET_DEST (set) = dest;
3856 : }
3857 : /* Drop possible dead definitions. */
3858 164864 : PATTERN (insn) = set;
3859 164864 : INSN_CODE (insn) = -1;
3860 164864 : recog_memoized (insn);
3861 164864 : if (dump_file)
3862 : {
3863 0 : fprintf (dump_file, "\nwith:\n\n");
3864 0 : print_rtl_single (dump_file, insn);
3865 0 : fprintf (dump_file, "\n");
3866 : }
3867 164864 : df_insn_rescan (insn);
3868 : }
3869 65404 : }
3870 :
3871 : /* Return the inner scalar if OP is a broadcast, else return nullptr. */
3872 :
3873 : static rtx
3874 2228085 : ix86_broadcast_inner (rtx op, machine_mode mode,
3875 : machine_mode *scalar_mode_p,
3876 : x86_cse_kind *kind_p, rtx_insn **insn_p)
3877 : {
3878 2228085 : switch (standard_sse_constant_p (op, mode))
3879 : {
3880 119811 : case 1:
3881 119811 : *scalar_mode_p = QImode;
3882 119811 : *kind_p = X86_CSE_CONST0_VECTOR;
3883 119811 : *insn_p = nullptr;
3884 119811 : return const0_rtx;
3885 12682 : case 2:
3886 12682 : *scalar_mode_p = QImode;
3887 12682 : *kind_p = X86_CSE_CONSTM1_VECTOR;
3888 12682 : *insn_p = nullptr;
3889 12682 : return constm1_rtx;
3890 2095592 : default:
3891 2095592 : break;
3892 : }
3893 :
3894 2095592 : mode = GET_MODE (op);
3895 2095592 : int nunits = GET_MODE_NUNITS (mode);
3896 2095592 : if (nunits < 2)
3897 : return nullptr;
3898 :
3899 1587531 : bool const_vector_p = CONST_VECTOR_P (op);
3900 1587531 : bool duplicated = GET_CODE (op) == VEC_DUPLICATE;
3901 1587531 : rtx orig_op = op;
3902 1587531 : if (!const_vector_p)
3903 : {
3904 : /* Check CONST_VECTOR in REG_EQUAL note. */
3905 1587511 : rtx equal = find_reg_equal_equiv_note (*insn_p);
3906 1587511 : if (equal)
3907 : {
3908 379821 : equal = XEXP (equal, 0);
3909 379821 : const_vector_p = CONST_VECTOR_P (equal);
3910 : /* Use CONST_VECTOR in REG_EQUAL note. */
3911 379821 : if (const_vector_p)
3912 : {
3913 : /* Handle REG_EQUAL note in:
3914 :
3915 : (insn 7 5 12 2 (set (subreg:V8SI (reg:V4DI 100) 0)
3916 : (vec_duplicate:V8SI (reg:SI 102)))
3917 : (expr_list:REG_DEAD (reg:SI 102)
3918 : (expr_list:REG_EQUAL (const_vector:V4DI [
3919 : (const_int -1 [0xffffffffffffffff]) repeated x4]) (nil))))
3920 :
3921 : NB: Don't treat it as CONST_VECTOR since EQUAL isn't
3922 : supported by ISAs as in gcc.target/i386/pr40957.c. */
3923 268784 : if (GET_MODE (equal) != mode)
3924 : const_vector_p = false;
3925 : else
3926 1587531 : op = equal;
3927 : }
3928 : }
3929 : }
3930 :
3931 1587531 : machine_mode inner_mode = GET_MODE_INNER (mode);
3932 :
3933 1587531 : if (const_vector_p)
3934 : {
3935 537534 : bool int_load_p = GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
3936 268767 : *kind_p = X86_CSE_CONST_VECTOR;
3937 268767 : if (int_load_p)
3938 : {
3939 : /* This CONST_VECTOR load can be converted to constant
3940 : integer load. */
3941 35399 : *scalar_mode_p = mode;
3942 35399 : *insn_p = nullptr;
3943 35399 : return op;
3944 : }
3945 :
3946 : /* This CONST_VECTOR is wider than the integer register. */
3947 233368 : rtx first = XVECEXP (op, 0, 0);
3948 :
3949 233368 : if (duplicated)
3950 : {
3951 : /* Check if CONST_VECTOR in REG_EQUAL note is duplicated in
3952 :
3953 : (insn 10 7 12 2 (set (reg:V8SI 128)
3954 : (vec_duplicate:V8SI (vec_select:V2SI (reg:V4SI 180)
3955 : (parallel [(const_int 0 [0])
3956 : (const_int 1 [0x1])]))))
3957 : (expr_list:REG_EQUAL (const_vector:V8SI [
3958 : (const_int 0 [0])
3959 : (const_int 34 [0x22])
3960 : (const_int 0 [0])
3961 : (const_int 34 [0x22])
3962 : (const_int 0 [0])
3963 : (const_int 34 [0x22])
3964 : (const_int 0 [0])
3965 : (const_int 34 [0x22])])(nil)))
3966 :
3967 : */
3968 :
3969 216070 : bool duplicated_const_vector = true;
3970 216070 : for (int i = 1; i < nunits; ++i)
3971 : {
3972 141555 : rtx tmp = XVECEXP (op, 0, i);
3973 141555 : if (!rtx_equal_p (tmp, first))
3974 : {
3975 : duplicated_const_vector = false;
3976 : break;
3977 : }
3978 : }
3979 :
3980 74531 : if (duplicated_const_vector)
3981 : {
3982 74515 : bool const_double_p = CONST_DOUBLE_P (first);
3983 : /* Force the floating point constant to memory. */
3984 74515 : if (const_double_p)
3985 5806 : first = validize_mem (force_const_mem (inner_mode, first));
3986 :
3987 74515 : if (const_double_p || CONST_INT_P (first))
3988 : {
3989 : /* Handle
3990 :
3991 : (insn 7 6 8 2 (set (reg:V4SF 99)
3992 : (vec_duplicate:V4SF (mem/u/c:SF (symbol_ref/u:DI ("*.LC2") [flags 0x2]) [0 S4 A32])))
3993 : (expr_list:REG_EQUAL (const_vector:V4SF [
3994 : (const_double:SF 3.4e+1 [0x0.88p+6]) repeated x4]) (nil)))
3995 :
3996 : and
3997 :
3998 : (insn 14 15 16 3 (set (reg:V4SI 116)
3999 : (vec_duplicate:V4SI (reg:SI 117)))
4000 : (expr_list:REG_EQUAL (const_vector:V4SI [
4001 : (const_int 34 [0x22]) repeated x4]) (nil)))
4002 :
4003 : */
4004 74515 : *kind_p = X86_CSE_VEC_DUP;
4005 74515 : *insn_p = nullptr;
4006 74515 : *scalar_mode_p = inner_mode;
4007 74515 : return first;
4008 : }
4009 : }
4010 :
4011 : op = orig_op;
4012 : }
4013 : else
4014 : {
4015 : /* Only native CONST_VECTOR is allowed. */
4016 158837 : if (orig_op != op)
4017 : return nullptr;
4018 :
4019 : /* Check if VEC_DUPLICATE can be used. */
4020 48 : for (int i = 1; i < nunits; ++i)
4021 : {
4022 48 : rtx tmp = XVECEXP (op, 0, i);
4023 : /* Vector duplicate value. */
4024 48 : if (!rtx_equal_p (tmp, first))
4025 : return nullptr;
4026 : }
4027 :
4028 : /* Use the inner mode to handle
4029 : (const_vector:V2QI [(const_int 0 [0]) repeated x2])
4030 : */
4031 0 : *scalar_mode_p = inner_mode;
4032 0 : *insn_p = nullptr;
4033 0 : return first;
4034 : }
4035 : }
4036 :
4037 1318780 : if (!duplicated)
4038 : return nullptr;
4039 :
4040 23368 : *kind_p = X86_CSE_VEC_DUP;
4041 :
4042 : /* Only
4043 :
4044 : (vec_duplicate:V4SI (reg:SI 99))
4045 : (vec_duplicate:V2DF (mem/u/c:DF (symbol_ref/u:DI ("*.LC1") [flags 0x2]) [0 S8 A64]))
4046 :
4047 : are supported. Set OP to the broadcast source by default. */
4048 23368 : op = XEXP (op, 0);
4049 23368 : rtx reg = op;
4050 23368 : if (SUBREG_P (op)
4051 402 : && SUBREG_BYTE (op) == 0
4052 23770 : && !paradoxical_subreg_p (op))
4053 402 : reg = SUBREG_REG (op);
4054 23368 : if (!REG_P (reg))
4055 : {
4056 2347 : if (MEM_P (op)
4057 2078 : && SYMBOL_REF_P (XEXP (op, 0))
4058 2622 : && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
4059 : {
4060 : /* Handle constant broadcast from memory. */
4061 11 : *scalar_mode_p = inner_mode;
4062 11 : *insn_p = nullptr;
4063 11 : return op;
4064 : }
4065 : return nullptr;
4066 : }
4067 :
4068 21021 : machine_mode orig_mode = mode;
4069 21021 : mode = GET_MODE (op);
4070 :
4071 : /* Only single def chain is supported. */
4072 21021 : df_ref ref = DF_REG_DEF_CHAIN (REGNO (reg));
4073 21021 : if (!ref
4074 21021 : || DF_REF_IS_ARTIFICIAL (ref)
4075 21021 : || DF_REF_NEXT_REG (ref) != nullptr)
4076 : return nullptr;
4077 :
4078 15382 : rtx_insn *insn = DF_REF_INSN (ref);
4079 :
4080 : /* Skip JUMP which happens with asm goto. */
4081 15382 : if (JUMP_P (insn))
4082 : return nullptr;
4083 :
4084 15380 : rtx set = single_set (insn);
4085 15380 : if (!set)
4086 : return nullptr;
4087 :
4088 15342 : rtx src = SET_SRC (set);
4089 :
4090 15342 : if (CONST_INT_P (src))
4091 : {
4092 : /* Handle sequences like
4093 :
4094 : (set (subreg:SI (reg/v:SF 105 [ f ]) 0)
4095 : (const_int 0 [0]))
4096 : (set (reg:V4SF 110)
4097 : (vec_duplicate:V4SF (reg/v:SF 105 [ f ])))
4098 :
4099 : and
4100 :
4101 : (set (reg:SI 99)
4102 : (const_int 34 [0x22]))
4103 : (set (reg:V4SI 98)
4104 : (vec_duplicate:V4SI (reg:SI 99)))
4105 :
4106 : Set *INSN_P to nullptr and return SET_SRC if SET_SRC is an
4107 : integer constant. */
4108 243 : op = src;
4109 243 : if (SCALAR_INT_MODE_P (mode) && mode != GET_MODE (reg))
4110 0 : op = gen_int_mode (INTVAL (src), mode);
4111 243 : if (op == const0_rtx)
4112 : {
4113 4 : if (standard_sse_constant_p (CONST0_RTX (orig_mode),
4114 : orig_mode) == 1)
4115 : {
4116 4 : *scalar_mode_p = QImode;
4117 4 : *kind_p = X86_CSE_CONST0_VECTOR;
4118 4 : *insn_p = nullptr;
4119 4 : return const0_rtx;
4120 : }
4121 0 : op = CONST0_RTX (mode);
4122 : }
4123 239 : else if (op == constm1_rtx
4124 239 : && standard_sse_constant_p (CONSTM1_RTX (orig_mode),
4125 : orig_mode) == 2)
4126 : {
4127 0 : *scalar_mode_p = QImode;
4128 0 : *kind_p = X86_CSE_CONSTM1_VECTOR;
4129 0 : *insn_p = nullptr;
4130 0 : return constm1_rtx;
4131 : }
4132 :
4133 : /* Check if we can convert:
4134 :
4135 : (insn 14 465 412 3 (set (reg:SI 507 [ j_lsm.26 ])
4136 : (const_int 2 [0x2])) "foo.c":10:12 discrim 2 100 {*movsi_internal} (nil))
4137 : ...
4138 : (insn 518 507 434 16 (set (reg:V2SI 493)
4139 : (vec_duplicate:V2SI (reg:SI 507 [ j_lsm.26 ]))) 2395 {*vec_dupv2si} (nil))
4140 :
4141 : to constant integer load:
4142 :
4143 : (insn 566 55 56 6 (set (subreg:DI (reg:V2SI 517) 0)
4144 : (const_int 8589934594 [0x200000002])) -1 (nil))
4145 : ...
4146 : (insn 518 507 434 16 (set (reg:V2SI 493)
4147 : (reg:V2SI 517)) 2066 {*movv2si_internal} (nil))
4148 :
4149 : */
4150 478 : if (GET_MODE_SIZE (orig_mode) <= UNITS_PER_WORD)
4151 17 : *kind_p = X86_CSE_CONST_VECTOR;
4152 :
4153 239 : *insn_p = nullptr;
4154 : }
4155 : else
4156 : {
4157 : /* Handle sequences like
4158 :
4159 : (set (reg:QI 105 [ c ])
4160 : (reg:QI 5 di [ c ]))
4161 : (set (reg:V64QI 102 [ _1 ])
4162 : (vec_duplicate:V64QI (reg:QI 105 [ c ])))
4163 :
4164 : (set (reg/v:SI 116 [ argc ])
4165 : (mem/c:SI (reg:SI 135) [2 argc+0 S4 A32]))
4166 : (set (reg:V4SI 119 [ _45 ])
4167 : (vec_duplicate:V4SI (reg/v:SI 116 [ argc ])))
4168 :
4169 : (set (reg:SI 98 [ _1 ])
4170 : (sign_extend:SI (reg:QI 106 [ c ])))
4171 : (set (reg:V16SI 103 [ _2 ])
4172 : (vec_duplicate:V16SI (reg:SI 98 [ _1 ])))
4173 :
4174 : (set (reg:SI 102 [ cost ])
4175 : (mem/c:SI (symbol_ref:DI ("cost") [flags 0x40])))
4176 : (set (reg:V4HI 103 [ _16 ])
4177 : (vec_duplicate:V4HI (subreg:HI (reg:SI 102 [ cost ]) 0)))
4178 :
4179 : (set (subreg:SI (reg/v:HI 107 [ cr_val ]) 0)
4180 : (ashift:SI (reg:SI 158)
4181 : (subreg:QI (reg:SI 156 [ _2 ]) 0)))
4182 : (set (reg:V16HI 183 [ _61 ])
4183 : (vec_duplicate:V16HI (reg/v:HI 107 [ cr_val ])))
4184 :
4185 : Set *INSN_P to INSN and return the broadcast source otherwise. */
4186 15099 : *insn_p = insn;
4187 : }
4188 :
4189 15338 : *scalar_mode_p = mode;
4190 15338 : return op;
4191 : }
4192 :
4193 : /* Replace CALL instruction in TLS_CALL_INSNS with SET from SRC and
4194 : put the updated instruction in UPDATED_TLS_INSNS. */
4195 :
4196 : static void
4197 320 : replace_tls_call (rtx src, auto_bitmap &tls_call_insns,
4198 : auto_bitmap &updated_tls_insns)
4199 : {
4200 320 : bitmap_iterator bi;
4201 320 : unsigned int id;
4202 :
4203 1754 : EXECUTE_IF_SET_IN_BITMAP (tls_call_insns, 0, id, bi)
4204 : {
4205 1434 : rtx_insn *insn = DF_INSN_UID_GET (id)->insn;
4206 :
4207 : /* If this isn't a CALL, only GNU2 TLS implicit CALL patterns are
4208 : allowed. */
4209 1434 : if (!CALL_P (insn))
4210 : {
4211 47 : attr_tls64 tls64 = get_attr_tls64 (insn);
4212 47 : if (tls64 != TLS64_CALL && tls64 != TLS64_COMBINE)
4213 0 : gcc_unreachable ();
4214 : }
4215 :
4216 1434 : rtx pat = PATTERN (insn);
4217 1434 : gcc_assert (GET_CODE (pat) == PARALLEL);
4218 1434 : rtx set = XVECEXP (pat, 0, 0);
4219 1434 : gcc_assert (GET_CODE (set) == SET);
4220 1434 : rtx dest = SET_DEST (set);
4221 :
4222 1434 : set = gen_rtx_SET (dest, src);
4223 1434 : rtx_insn *set_insn = emit_insn_after (set, insn);
4224 1434 : if (recog_memoized (set_insn) < 0)
4225 0 : gcc_unreachable ();
4226 :
4227 : /* Put SET_INSN in UPDATED_TLS_INSNS. */
4228 1434 : bitmap_set_bit (updated_tls_insns, INSN_UID (set_insn));
4229 :
4230 1434 : if (dump_file)
4231 : {
4232 0 : fprintf (dump_file, "\nReplace:\n\n");
4233 0 : print_rtl_single (dump_file, insn);
4234 0 : fprintf (dump_file, "\nwith:\n\n");
4235 0 : print_rtl_single (dump_file, set_insn);
4236 0 : fprintf (dump_file, "\n");
4237 : }
4238 :
4239 : /* Delete the CALL insn. */
4240 1434 : delete_insn (insn);
4241 :
4242 1434 : df_insn_rescan (set_insn);
4243 : }
4244 320 : }
4245 :
4246 : /* Return the basic block which dominates all basic blocks which set
4247 : hard register REGNO used in basic block BB. */
4248 :
4249 : static basic_block
4250 2 : ix86_get_dominator_for_reg (unsigned int regno, basic_block bb)
4251 : {
4252 2 : basic_block set_bb;
4253 2 : auto_bitmap set_bbs;
4254 :
4255 : /* Get all BBs which set REGNO and dominate the current BB from all
4256 : DEFs of REGNO. */
4257 2 : for (df_ref def = DF_REG_DEF_CHAIN (regno);
4258 18 : def;
4259 16 : def = DF_REF_NEXT_REG (def))
4260 16 : if (!DF_REF_IS_ARTIFICIAL (def)
4261 16 : && !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)
4262 6 : && !DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
4263 : {
4264 4 : set_bb = DF_REF_BB (def);
4265 4 : if (dominated_by_p (CDI_DOMINATORS, bb, set_bb))
4266 2 : bitmap_set_bit (set_bbs, set_bb->index);
4267 : }
4268 :
4269 2 : bb = nearest_common_dominator_for_set (CDI_DOMINATORS, set_bbs);
4270 2 : return bb;
4271 2 : }
4272 :
4273 : /* Mark FLAGS register as live in DATA, a bitmap of live caller-saved
4274 : registers, if DEST is FLAGS register. */
4275 :
4276 : static void
4277 388 : ix86_check_flags_reg (rtx dest, const_rtx x, void *data)
4278 : {
4279 388 : if (GET_CODE (x) == CLOBBER)
4280 : return;
4281 :
4282 381 : auto_bitmap *live_caller_saved_regs = (auto_bitmap *) data;
4283 381 : if (REG_P (dest) && REGNO (dest) == FLAGS_REG)
4284 0 : bitmap_set_bit (*live_caller_saved_regs, FLAGS_REG);
4285 : }
4286 :
4287 : /* Emit a TLS_SET instruction of KIND in basic block BB. Store the
4288 : insertion point in *BEFORE_P for emit_insn_before or in *AFTER_P
4289 : for emit_insn_after. UPDATED_GNU_TLS_INSNS contains instructions
4290 : which replace the GNU TLS instructions. UPDATED_GNU2_TLS_INSNS
4291 : contains instructions which replace the GNU2 TLS instructions. */
4292 :
4293 : static rtx_insn *
4294 320 : ix86_emit_tls_call (rtx tls_set, x86_cse_kind kind, basic_block bb,
4295 : rtx_insn **before_p, rtx_insn **after_p,
4296 : auto_bitmap &updated_gnu_tls_insns,
4297 : auto_bitmap &updated_gnu2_tls_insns)
4298 : {
4299 322 : rtx_insn *tls_insn;
4300 :
4301 322 : do
4302 : {
4303 322 : rtx_insn *insn = BB_HEAD (bb);
4304 1283 : while (insn && !NONDEBUG_INSN_P (insn))
4305 : {
4306 965 : if (insn == BB_END (bb))
4307 : {
4308 : /* This must be the beginning basic block:
4309 :
4310 : (note 4 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
4311 : (note 2 4 26 2 NOTE_INSN_FUNCTION_BEG)
4312 :
4313 : or a basic block with only a label:
4314 :
4315 : (code_label 78 11 77 3 14 (nil) [1 uses])
4316 : (note 77 78 54 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
4317 :
4318 : or a basic block with only a debug marker:
4319 :
4320 : (note 3 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
4321 : (note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
4322 : (debug_insn 5 2 16 2 (debug_marker) "x.c":6:3 -1 (nil))
4323 :
4324 : or a basic block with only deleted instructions:
4325 :
4326 : (code_label 348 23 349 45 3 (nil) [0 uses])
4327 : (note 349 348 436 45 [bb 45] NOTE_INSN_BASIC_BLOCK)
4328 : (note 436 349 362 45 NOTE_INSN_DELETED)
4329 :
4330 : */
4331 4 : gcc_assert (DEBUG_INSN_P (insn)
4332 : || (NOTE_P (insn)
4333 : && ((NOTE_KIND (insn)
4334 : == NOTE_INSN_FUNCTION_BEG)
4335 : || (NOTE_KIND (insn)
4336 : == NOTE_INSN_DELETED)
4337 : || (NOTE_KIND (insn)
4338 : == NOTE_INSN_BASIC_BLOCK))));
4339 : insn = NULL;
4340 : break;
4341 : }
4342 961 : insn = NEXT_INSN (insn);
4343 : }
4344 :
4345 : /* TLS_GD and TLS_LD_BASE instructions are normal functions which
4346 : clobber caller-saved registers. TLSDESC instructions only
4347 : clobber FLAGS. If any registers clobbered by TLS instructions
4348 : are live in this basic block, we must insert TLS instructions
4349 : after all live registers clobbered are dead. */
4350 :
4351 322 : auto_bitmap live_caller_saved_regs;
4352 644 : bitmap in = df_live ? DF_LIVE_IN (bb) : DF_LR_IN (bb);
4353 :
4354 322 : if (bitmap_bit_p (in, FLAGS_REG))
4355 4 : bitmap_set_bit (live_caller_saved_regs, FLAGS_REG);
4356 :
4357 322 : unsigned int i;
4358 :
4359 : /* Get all live caller-saved registers for TLS_GD and TLS_LD_BASE
4360 : instructions. */
4361 322 : if (kind != X86_CSE_TLSDESC)
4362 : {
4363 300 : const predefined_function_abi &tls_abi
4364 300 : = ix86_tls_get_addr_abi ();
4365 28800 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4366 28200 : if (tls_abi.clobbers_full_reg_p (i)
4367 25503 : && !fixed_regs[i]
4368 40548 : && bitmap_bit_p (in, i))
4369 350 : bitmap_set_bit (live_caller_saved_regs, i);
4370 300 : if (df_live && crtl->drap_reg)
4371 : {
4372 : /* DRAP has no reaching definition at this point, so df_live drops
4373 : it above. Its hard register can also go dead mid-function once
4374 : copied elsewhere (e.g. right after the prologue), so query
4375 : DF_LR_IN per-block rather than treating it as live whenever
4376 : crtl->drap_reg is set. */
4377 1 : i = REGNO (crtl->drap_reg);
4378 2 : if (bitmap_bit_p (DF_LR_IN (bb), i))
4379 1 : bitmap_set_bit (live_caller_saved_regs, i);
4380 : }
4381 : }
4382 :
4383 322 : if (bitmap_empty_p (live_caller_saved_regs))
4384 : {
4385 82 : if (insn == BB_HEAD (bb))
4386 : {
4387 0 : *before_p = insn;
4388 0 : tls_insn = emit_insn_before (tls_set, insn);
4389 : }
4390 : else
4391 : {
4392 : /* Emit the TLS call after NOTE_INSN_FUNCTION_BEG in the
4393 : beginning basic block:
4394 :
4395 : (note 4 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
4396 : (note 2 4 26 2 NOTE_INSN_FUNCTION_BEG)
4397 :
4398 : or after NOTE_INSN_BASIC_BLOCK in a basic block with
4399 : only a label:
4400 :
4401 : (code_label 78 11 77 3 14 (nil) [1 uses])
4402 : (note 77 78 54 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
4403 :
4404 : or after debug marker in a basic block with only a
4405 : debug marker:
4406 :
4407 : (note 3 0 2 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
4408 : (note 2 3 5 2 NOTE_INSN_FUNCTION_BEG)
4409 : (debug_insn 5 2 16 2 (debug_marker) "x.c":6:3 -1 (nil))
4410 :
4411 : */
4412 82 : insn = insn ? PREV_INSN (insn) : BB_END (bb);
4413 82 : *after_p = insn;
4414 82 : tls_insn = emit_insn_after (tls_set, insn);
4415 : }
4416 : return tls_insn;
4417 : }
4418 :
4419 240 : bool repeat = false;
4420 :
4421 : /* Search for REG_DEAD notes in this basic block. */
4422 675 : FOR_BB_INSNS (bb, insn)
4423 : {
4424 675 : if (!NONDEBUG_INSN_P (insn))
4425 290 : continue;
4426 :
4427 : /* NB: Conditional jump is the only instruction which reads
4428 : flags register and changes control flow. We can never
4429 : place the TLS call after unconditional jump. */
4430 385 : if (JUMP_P (insn))
4431 : {
4432 : /* This must be a conditional jump. */
4433 2 : rtx label = JUMP_LABEL (insn);
4434 2 : if (label == nullptr
4435 2 : || ANY_RETURN_P (label)
4436 2 : || !(LABEL_P (label) || SYMBOL_REF_P (label)))
4437 0 : gcc_unreachable ();
4438 :
4439 : /* Place the call before all FLAGS_REG setting BBs since
4440 : we can't place a call before nor after a conditional
4441 : jump. */
4442 2 : bb = ix86_get_dominator_for_reg (FLAGS_REG, bb);
4443 :
4444 : /* Start over again. */
4445 2 : repeat = true;
4446 2 : break;
4447 : }
4448 :
4449 383 : if (bitmap_bit_p (updated_gnu_tls_insns, INSN_UID (insn)))
4450 : {
4451 : /* Insert the __tls_get_addr call before INSN which
4452 : replaces a __tls_get_addr call. */
4453 1 : *before_p = insn;
4454 1 : tls_insn = emit_insn_before (tls_set, insn);
4455 1 : return tls_insn;
4456 : }
4457 :
4458 382 : if (bitmap_bit_p (updated_gnu2_tls_insns, INSN_UID (insn)))
4459 : {
4460 : /* Mark FLAGS register as dead since FLAGS register
4461 : would be clobbered by the GNU2 TLS instruction. */
4462 1 : bitmap_clear_bit (live_caller_saved_regs, FLAGS_REG);
4463 1 : continue;
4464 : }
4465 :
4466 : /* Check if FLAGS register is live. */
4467 381 : note_stores (insn, ix86_check_flags_reg,
4468 : &live_caller_saved_regs);
4469 :
4470 381 : rtx link;
4471 522 : for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
4472 378 : if ((REG_NOTE_KIND (link) == REG_DEAD
4473 9 : || (REG_NOTE_KIND (link) == REG_UNUSED
4474 7 : && REGNO (XEXP (link, 0)) == FLAGS_REG))
4475 385 : && REG_P (XEXP (link, 0)))
4476 : {
4477 : /* Mark the live caller-saved register as dead. */
4478 757 : for (i = REGNO (XEXP (link, 0));
4479 757 : i < END_REGNO (XEXP (link, 0));
4480 : i++)
4481 381 : if (i < FIRST_PSEUDO_REGISTER)
4482 358 : bitmap_clear_bit (live_caller_saved_regs, i);
4483 :
4484 376 : if (bitmap_empty_p (live_caller_saved_regs))
4485 : {
4486 237 : *after_p = insn;
4487 237 : tls_insn = emit_insn_after (tls_set, insn);
4488 237 : return tls_insn;
4489 : }
4490 : }
4491 : }
4492 :
4493 : /* NB: Start over again for conditional jump. */
4494 2 : if (repeat)
4495 2 : continue;
4496 :
4497 0 : gcc_assert (!bitmap_empty_p (live_caller_saved_regs));
4498 :
4499 : /* If any live caller-saved registers aren't dead at the end of
4500 : this basic block, get the basic block which dominates all
4501 : basic blocks which set the remaining live registers. */
4502 0 : auto_bitmap set_bbs;
4503 0 : bitmap_iterator bi;
4504 0 : unsigned int id;
4505 0 : EXECUTE_IF_SET_IN_BITMAP (live_caller_saved_regs, 0, id, bi)
4506 : {
4507 0 : basic_block set_bb = ix86_get_dominator_for_reg (id, bb);
4508 0 : bitmap_set_bit (set_bbs, set_bb->index);
4509 : }
4510 0 : bb = nearest_common_dominator_for_set (CDI_DOMINATORS, set_bbs);
4511 2 : }
4512 : while (true);
4513 : }
4514 :
4515 : /* Generate a TLS call of KIND with VAL and copy the call result to DEST,
4516 : at entry of the nearest dominator for basic block map BBS, which is in
4517 : the fake loop that contains the whole function, so that there is only
4518 : a single TLS CALL of KIND with VAL in the whole function.
4519 : UPDATED_GNU_TLS_INSNS contains instructions which replace the GNU TLS
4520 : instructions. UPDATED_GNU2_TLS_INSNS contains instructions which
4521 : replace the GNU2 TLS instructions. If TLSDESC_SET isn't nullptr,
4522 : insert it before the TLS call. */
4523 :
4524 : static void
4525 320 : ix86_place_single_tls_call (rtx dest, rtx val, x86_cse_kind kind,
4526 : auto_bitmap &bbs,
4527 : auto_bitmap &updated_gnu_tls_insns,
4528 : auto_bitmap &updated_gnu2_tls_insns,
4529 : rtx tlsdesc_set = nullptr)
4530 : {
4531 320 : basic_block bb = nearest_common_dominator_for_set (CDI_DOMINATORS, bbs);
4532 320 : while (bb->loop_father->latch
4533 330 : != EXIT_BLOCK_PTR_FOR_FN (cfun))
4534 10 : bb = get_immediate_dominator (CDI_DOMINATORS,
4535 : bb->loop_father->header);
4536 :
4537 320 : rtx rax = nullptr, rdi;
4538 320 : rtx eqv = nullptr;
4539 320 : rtx caddr;
4540 320 : rtx set;
4541 320 : rtx clob;
4542 320 : rtx symbol;
4543 320 : rtx tls;
4544 :
4545 320 : switch (kind)
4546 : {
4547 265 : case X86_CSE_TLS_GD:
4548 265 : rax = gen_rtx_REG (Pmode, AX_REG);
4549 265 : rdi = gen_rtx_REG (Pmode, DI_REG);
4550 265 : caddr = ix86_tls_get_addr ();
4551 :
4552 265 : symbol = XVECEXP (val, 0, 0);
4553 265 : tls = gen_tls_global_dynamic_64 (Pmode, rax, symbol, caddr, rdi);
4554 265 : CALL_INSN_ABI_ID (tls) = ix86_tls_get_addr_abi ().id ();
4555 :
4556 265 : if (GET_MODE (symbol) != Pmode)
4557 0 : symbol = gen_rtx_ZERO_EXTEND (Pmode, symbol);
4558 : eqv = symbol;
4559 : break;
4560 :
4561 34 : case X86_CSE_TLS_LD_BASE:
4562 34 : rax = gen_rtx_REG (Pmode, AX_REG);
4563 34 : rdi = gen_rtx_REG (Pmode, DI_REG);
4564 34 : caddr = ix86_tls_get_addr ();
4565 :
4566 34 : tls = gen_tls_local_dynamic_base_64 (Pmode, rax, caddr, rdi);
4567 34 : CALL_INSN_ABI_ID (tls) = ix86_tls_get_addr_abi ().id ();
4568 :
4569 : /* Attach a unique REG_EQUAL to DEST, to allow the RTL optimizers
4570 : to share the LD_BASE result with other LD model accesses. */
4571 34 : eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
4572 : UNSPEC_TLS_LD_BASE);
4573 :
4574 34 : break;
4575 :
4576 21 : case X86_CSE_TLSDESC:
4577 21 : set = gen_rtx_SET (dest, val);
4578 21 : clob = gen_rtx_CLOBBER (VOIDmode,
4579 : gen_rtx_REG (CCmode, FLAGS_REG));
4580 21 : tls = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clob));
4581 21 : break;
4582 :
4583 0 : default:
4584 0 : gcc_unreachable ();
4585 : }
4586 :
4587 : /* Emit the TLS CALL insn. */
4588 320 : rtx_insn *before = nullptr;
4589 320 : rtx_insn *after = nullptr;
4590 320 : rtx_insn *tls_insn = ix86_emit_tls_call (tls, kind, bb, &before,
4591 : &after,
4592 : updated_gnu_tls_insns,
4593 : updated_gnu2_tls_insns);
4594 :
4595 320 : rtx_insn *tlsdesc_insn = nullptr;
4596 320 : if (tlsdesc_set)
4597 : {
4598 16 : rtx dest = copy_rtx (SET_DEST (tlsdesc_set));
4599 16 : rtx src = copy_rtx (SET_SRC (tlsdesc_set));
4600 16 : tlsdesc_set = gen_rtx_SET (dest, src);
4601 16 : tlsdesc_insn = emit_insn_before (tlsdesc_set, tls_insn);
4602 : }
4603 :
4604 320 : if (kind != X86_CSE_TLSDESC)
4605 : {
4606 299 : RTL_CONST_CALL_P (tls_insn) = 1;
4607 :
4608 : /* Indicate that this function can't jump to non-local gotos. */
4609 299 : make_reg_eh_region_note_nothrow_nononlocal (tls_insn);
4610 : }
4611 :
4612 320 : if (recog_memoized (tls_insn) < 0)
4613 0 : gcc_unreachable ();
4614 :
4615 320 : if (dump_file)
4616 : {
4617 0 : if (after)
4618 : {
4619 0 : fprintf (dump_file, "\nPlace:\n\n");
4620 0 : if (tlsdesc_insn)
4621 0 : print_rtl_single (dump_file, tlsdesc_insn);
4622 0 : print_rtl_single (dump_file, tls_insn);
4623 0 : fprintf (dump_file, "\nafter:\n\n");
4624 0 : print_rtl_single (dump_file, after);
4625 0 : fprintf (dump_file, "\n");
4626 : }
4627 : else
4628 : {
4629 0 : fprintf (dump_file, "\nPlace:\n\n");
4630 0 : if (tlsdesc_insn)
4631 0 : print_rtl_single (dump_file, tlsdesc_insn);
4632 0 : print_rtl_single (dump_file, tls_insn);
4633 0 : fprintf (dump_file, "\nbefore:\n\n");
4634 0 : print_rtl_single (dump_file, before);
4635 0 : fprintf (dump_file, "\n");
4636 : }
4637 : }
4638 :
4639 320 : if (kind != X86_CSE_TLSDESC)
4640 : {
4641 : /* Copy RAX to DEST. */
4642 299 : set = gen_rtx_SET (dest, rax);
4643 299 : rtx_insn *set_insn = emit_insn_after (set, tls_insn);
4644 299 : set_dst_reg_note (set_insn, REG_EQUAL, copy_rtx (eqv), dest);
4645 299 : if (dump_file)
4646 : {
4647 0 : fprintf (dump_file, "\nPlace:\n\n");
4648 0 : print_rtl_single (dump_file, set_insn);
4649 0 : fprintf (dump_file, "\nafter:\n\n");
4650 0 : print_rtl_single (dump_file, tls_insn);
4651 0 : fprintf (dump_file, "\n");
4652 : }
4653 : }
4654 320 : }
4655 :
4656 : namespace {
4657 :
4658 : const pass_data pass_data_x86_cse =
4659 : {
4660 : RTL_PASS, /* type */
4661 : "x86_cse", /* name */
4662 : OPTGROUP_NONE, /* optinfo_flags */
4663 : TV_MACH_DEP, /* tv_id */
4664 : 0, /* properties_required */
4665 : 0, /* properties_provided */
4666 : 0, /* properties_destroyed */
4667 : 0, /* todo_flags_start */
4668 : 0, /* todo_flags_finish */
4669 : };
4670 :
4671 : class pass_x86_cse : public rtl_opt_pass
4672 : {
4673 : public:
4674 294245 : pass_x86_cse (gcc::context *ctxt)
4675 588490 : : rtl_opt_pass (pass_data_x86_cse, ctxt)
4676 : {}
4677 :
4678 : /* opt_pass methods: */
4679 1511981 : bool gate (function *fun) final override
4680 : {
4681 1511981 : return optimize && optimize_function_for_speed_p (fun);
4682 : }
4683 :
4684 998114 : unsigned int execute (function *) final override
4685 : {
4686 998114 : return x86_cse ();
4687 : }
4688 :
4689 : private:
4690 : /* The redundant source value. */
4691 : rtx val;
4692 : /* The actual redundant source value for UNSPEC_TLSDESC. */
4693 : rtx tlsdesc_val;
4694 : /* The instruction which defines the redundant value. */
4695 : rtx_insn *def_insn;
4696 : /* Mode of the destination of the candidate redundant instruction. */
4697 : machine_mode mode;
4698 : /* Mode of the source of the candidate redundant instruction. */
4699 : machine_mode scalar_mode;
4700 : /* The classification of the candidate redundant instruction. */
4701 : x86_cse_kind kind;
4702 :
4703 : unsigned int x86_cse (void);
4704 : bool candidate_gnu_tls_p (rtx_insn *, attr_tls64);
4705 : bool candidate_gnu2_tls_p (rtx, attr_tls64);
4706 : bool candidate_vector_p (rtx, rtx_insn *);
4707 : rtx_insn *tls_set_insn_from_symbol (const_rtx, const_rtx);
4708 : }; // class pass_x86_cse
4709 :
4710 : /* Return the instruction which sets REG from TLS_SYMBOL. */
4711 :
4712 : rtx_insn *
4713 42 : pass_x86_cse::tls_set_insn_from_symbol (const_rtx reg,
4714 : const_rtx tls_symbol)
4715 : {
4716 42 : rtx_insn *set_insn = nullptr;
4717 42 : for (df_ref ref = DF_REG_DEF_CHAIN (REGNO (reg));
4718 111 : ref;
4719 69 : ref = DF_REF_NEXT_REG (ref))
4720 : {
4721 69 : if (DF_REF_IS_ARTIFICIAL (ref))
4722 : return nullptr;
4723 :
4724 69 : set_insn = DF_REF_INSN (ref);
4725 69 : if (get_attr_tls64 (set_insn) != TLS64_LEA)
4726 : return nullptr;
4727 :
4728 69 : rtx tls_set = PATTERN (set_insn);
4729 69 : rtx tls_src = XVECEXP (SET_SRC (tls_set), 0, 0);
4730 69 : if (!rtx_equal_p (tls_symbol, tls_src))
4731 : return nullptr;
4732 : }
4733 :
4734 : return set_insn;
4735 : }
4736 :
4737 : /* Return true and output def_insn, val, mode, scalar_mode and kind if
4738 : INSN is UNSPEC_TLS_GD or UNSPEC_TLS_LD_BASE. */
4739 :
4740 : bool
4741 2199 : pass_x86_cse::candidate_gnu_tls_p (rtx_insn *insn, attr_tls64 tls64)
4742 : {
4743 2199 : if (!TARGET_64BIT || !cfun->machine->tls_descriptor_call_multiple_p)
4744 : return false;
4745 :
4746 : /* Record the redundant TLS CALLs for 64-bit:
4747 :
4748 : (parallel [
4749 : (set (reg:DI 0 ax)
4750 : (call:DI (mem:QI (symbol_ref:DI ("__tls_get_addr")))
4751 : (const_int 0 [0])))
4752 : (unspec:DI [(symbol_ref:DI ("foo") [flags 0x50])
4753 : (reg/f:DI 7 sp)] UNSPEC_TLS_GD)
4754 : (clobber (reg:DI 5 di))])
4755 :
4756 :
4757 : and
4758 :
4759 : (parallel [
4760 : (set (reg:DI 0 ax)
4761 : (call:DI (mem:QI (symbol_ref:DI ("__tls_get_addr")))
4762 : (const_int 0 [0])))
4763 : (unspec:DI [(reg/f:DI 7 sp)] UNSPEC_TLS_LD_BASE)])
4764 :
4765 : */
4766 :
4767 2031 : rtx pat = PATTERN (insn);
4768 2031 : rtx set = XVECEXP (pat, 0, 0);
4769 2031 : gcc_assert (GET_CODE (set) == SET);
4770 2031 : rtx dest = SET_DEST (set);
4771 2031 : scalar_mode = mode = GET_MODE (dest);
4772 2031 : val = XVECEXP (pat, 0, 1);
4773 2031 : gcc_assert (GET_CODE (val) == UNSPEC);
4774 :
4775 2031 : if (tls64 == TLS64_GD)
4776 : kind = X86_CSE_TLS_GD;
4777 : else
4778 109 : kind = X86_CSE_TLS_LD_BASE;
4779 :
4780 2031 : def_insn = nullptr;
4781 2031 : return true;
4782 : }
4783 :
4784 : /* Return true and output def_insn, val, mode, scalar_mode and kind if
4785 : SET is UNSPEC_TLSDESC. */
4786 :
4787 : bool
4788 56 : pass_x86_cse::candidate_gnu2_tls_p (rtx set, attr_tls64 tls64)
4789 : {
4790 56 : if (!TARGET_64BIT || !cfun->machine->tls_descriptor_call_multiple_p)
4791 : return false;
4792 :
4793 54 : rtx tls_symbol;
4794 54 : rtx_insn *set_insn;
4795 54 : rtx src = SET_SRC (set);
4796 54 : val = src;
4797 54 : tlsdesc_val = src;
4798 54 : kind = X86_CSE_TLSDESC;
4799 :
4800 54 : if (tls64 == TLS64_COMBINE)
4801 : {
4802 : /* Record 64-bit TLS64_COMBINE:
4803 :
4804 : (set (reg/f:DI 104)
4805 : (plus:DI (unspec:DI [
4806 : (symbol_ref:DI ("_TLS_MODULE_BASE_") [flags 0x10])
4807 : (reg:DI 114)
4808 : (reg/f:DI 7 sp)] UNSPEC_TLSDESC)
4809 : (const:DI (unspec:DI [
4810 : (symbol_ref:DI ("e") [flags 0x1a])
4811 : ] UNSPEC_DTPOFF))))
4812 :
4813 : (set (reg/f:DI 104)
4814 : (plus:DI (unspec:DI [
4815 : (symbol_ref:DI ("_TLS_MODULE_BASE_") [flags 0x10])
4816 : (unspec:DI [
4817 : (symbol_ref:DI ("_TLS_MODULE_BASE_") [flags 0x10])
4818 : ] UNSPEC_TLSDESC)
4819 : (reg/f:DI 7 sp)] UNSPEC_TLSDESC)
4820 : (const:DI (unspec:DI [
4821 : (symbol_ref:DI ("e") [flags 0x1a])
4822 : ] UNSPEC_DTPOFF))))
4823 : */
4824 :
4825 12 : scalar_mode = mode = GET_MODE (src);
4826 :
4827 : /* Since the first operand of PLUS in the source TLS_COMBINE
4828 : pattern is unused, use the second operand of PLUS:
4829 :
4830 : (const:DI (unspec:DI [
4831 : (symbol_ref:DI ("e") [flags 0x1a])
4832 : ] UNSPEC_DTPOFF))
4833 :
4834 : as VAL to check if 2 TLS_COMBINE patterns have the same
4835 : source. */
4836 12 : val = XEXP (src, 1);
4837 12 : gcc_assert (GET_CODE (val) == CONST
4838 : && GET_CODE (XEXP (val, 0)) == UNSPEC
4839 : && XINT (XEXP (val, 0), 1) == UNSPEC_DTPOFF
4840 : && SYMBOL_REF_P (XVECEXP (XEXP (val, 0), 0, 0)));
4841 12 : def_insn = nullptr;
4842 12 : return true;
4843 : }
4844 :
4845 : /* Record 64-bit TLS_CALL:
4846 :
4847 : (set (reg:DI 101)
4848 : (unspec:DI [(symbol_ref:DI ("foo") [flags 0x50])
4849 : (reg:DI 112)
4850 : (reg/f:DI 7 sp)] UNSPEC_TLSDESC))
4851 :
4852 : */
4853 :
4854 42 : gcc_assert (GET_CODE (src) == UNSPEC);
4855 42 : tls_symbol = XVECEXP (src, 0, 0);
4856 42 : src = XVECEXP (src, 0, 1);
4857 42 : scalar_mode = mode = GET_MODE (src);
4858 42 : gcc_assert (REG_P (src));
4859 :
4860 : /* All definitions of reg:DI 129 in
4861 :
4862 : (set (reg:DI 110)
4863 : (unspec:DI [(symbol_ref:DI ("foo"))
4864 : (reg:DI 129)
4865 : (reg/f:DI 7 sp)] UNSPEC_TLSDESC))
4866 :
4867 : should have the same source as in
4868 :
4869 : (set (reg:DI 129)
4870 : (unspec:DI [(symbol_ref:DI ("foo"))] UNSPEC_TLSDESC))
4871 :
4872 : */
4873 :
4874 42 : set_insn = tls_set_insn_from_symbol (src, tls_symbol);
4875 42 : if (!set_insn)
4876 : return false;
4877 :
4878 : /* Use TLS_SYMBOL as VAL to check if 2 patterns have the same source. */
4879 42 : val = tls_symbol;
4880 42 : def_insn = set_insn;
4881 42 : return true;
4882 : }
4883 :
4884 : /* Return true and output def_insn, val, mode, scalar_mode and kind if
4885 : INSN is a vector broadcast instruction. */
4886 :
4887 : bool
4888 51352364 : pass_x86_cse::candidate_vector_p (rtx set, rtx_insn *insn)
4889 : {
4890 51352364 : rtx src = SET_SRC (set);
4891 51352364 : rtx dest = SET_DEST (set);
4892 51352364 : mode = GET_MODE (dest);
4893 : /* Skip non-vector instruction. */
4894 51352364 : if (!VECTOR_MODE_P (mode))
4895 : return false;
4896 :
4897 : /* Skip non-vector load instruction. */
4898 3714587 : if (!REG_P (dest) && !SUBREG_P (dest))
4899 : return false;
4900 :
4901 2228085 : def_insn = insn;
4902 2228085 : val = ix86_broadcast_inner (src, mode, &scalar_mode, &kind,
4903 : &def_insn);
4904 2228085 : return val ? true : false;
4905 : }
4906 :
4907 : /* At entry of the nearest common dominator for basic blocks with
4908 :
4909 : 1. Vector CONST0_RTX patterns.
4910 : 2. Vector CONSTM1_RTX patterns.
4911 : 3. Vector broadcast patterns.
4912 : 4. UNSPEC_TLS_GD patterns.
4913 : 5. UNSPEC_TLS_LD_BASE patterns.
4914 : 6. UNSPEC_TLSDESC patterns.
4915 :
4916 : generate a single pattern whose destination is used to replace the
4917 : source in all identical patterns.
4918 :
4919 : NB: We want to generate a pattern, which is executed only once, to
4920 : cover the whole function. The LCM algorithm isn't appropriate here
4921 : since it may place a pattern inside the loop. */
4922 :
4923 : unsigned int
4924 998114 : pass_x86_cse::x86_cse (void)
4925 : {
4926 998114 : timevar_push (TV_MACH_DEP);
4927 :
4928 998114 : auto_vec<redundant_pattern *> loads;
4929 998114 : redundant_pattern *load;
4930 998114 : basic_block bb;
4931 998114 : rtx_insn *insn;
4932 998114 : unsigned int i;
4933 998114 : auto_bitmap updated_gnu_tls_insns;
4934 998114 : auto_bitmap updated_gnu2_tls_insns;
4935 998114 : auto_bitmap call_bbs;
4936 :
4937 998114 : df_set_flags (DF_DEFER_INSN_RESCAN);
4938 :
4939 998114 : bool recursive_call_p = cfun->machine->recursive_function;
4940 :
4941 11209492 : FOR_EACH_BB_FN (bb, cfun)
4942 : {
4943 138799185 : FOR_BB_INSNS (bb, insn)
4944 : {
4945 128587807 : if (!NONDEBUG_INSN_P (insn))
4946 73475784 : continue;
4947 :
4948 55112023 : bool matched = false;
4949 : /* Remove redundant patterns if there are more than 2 of
4950 : them. */
4951 55112023 : unsigned int threshold = 2;
4952 :
4953 55112023 : bool call_p = CALL_P (insn);
4954 55112023 : rtx set = single_set (insn);
4955 55112023 : if (!set && !call_p)
4956 1110824 : continue;
4957 :
4958 54001199 : tlsdesc_val = nullptr;
4959 :
4960 54001199 : attr_tls64 tls64 = get_attr_tls64 (insn);
4961 :
4962 : /* NB: TLS calls preserve all registers. */
4963 54001199 : if (call_p && tls64 == TLS64_NONE)
4964 4566515 : bitmap_set_bit (call_bbs, BLOCK_FOR_INSN (insn)->index);
4965 :
4966 54001199 : switch (tls64)
4967 : {
4968 2199 : case TLS64_GD:
4969 2199 : case TLS64_LD_BASE:
4970 : /* Verify UNSPEC_TLS_GD and UNSPEC_TLS_LD_BASE. */
4971 2199 : if (candidate_gnu_tls_p (insn, tls64))
4972 : break;
4973 168 : continue;
4974 :
4975 56 : case TLS64_CALL:
4976 56 : case TLS64_COMBINE:
4977 : /* Verify UNSPEC_TLSDESC. */
4978 56 : if (candidate_gnu2_tls_p (set, tls64))
4979 : break;
4980 2 : continue;
4981 :
4982 36 : case TLS64_LEA:
4983 : /* Skip TLS64_LEA. */
4984 36 : continue;
4985 :
4986 53998908 : case TLS64_NONE:
4987 53998908 : if (!set)
4988 2646544 : continue;
4989 :
4990 : /* Check for vector broadcast. */
4991 51352364 : if (candidate_vector_p (set, insn))
4992 : break;
4993 51094604 : continue;
4994 : }
4995 :
4996 : /* Check if there is a matching redundant load. */
4997 674334 : FOR_EACH_VEC_ELT (loads, i, load)
4998 452849 : if (load->val
4999 452849 : && load->kind == kind
5000 299826 : && load->mode == scalar_mode
5001 264428 : && (load->bb == bb
5002 203129 : || (kind != X86_CSE_VEC_DUP
5003 203129 : && kind != X86_CSE_CONST_VECTOR)
5004 : /* Non all 0s/1s vector load must be in the same
5005 : basic block if it is in a recursive call. */
5006 139435 : || !recursive_call_p)
5007 715012 : && rtx_equal_p (load->val, val))
5008 : {
5009 : /* Record instruction. */
5010 100574 : bitmap_set_bit (load->insns, INSN_UID (insn));
5011 :
5012 : /* Record the maximum vector size. */
5013 100574 : if (kind <= X86_CSE_VEC_DUP
5014 200034 : && load->size < GET_MODE_SIZE (mode))
5015 836 : load->size = GET_MODE_SIZE (mode);
5016 :
5017 : /* Record the basic block. */
5018 100574 : bitmap_set_bit (load->bbs, bb->index);
5019 :
5020 : /* Increment the count. */
5021 100574 : load->count++;
5022 :
5023 100574 : matched = true;
5024 100574 : break;
5025 : }
5026 :
5027 259845 : if (matched)
5028 100574 : continue;
5029 :
5030 : /* We see this instruction the first time. Record the
5031 : redundant source value, its mode, the destination size,
5032 : instruction which defines the redundant source value,
5033 : instruction basic block and the instruction kind. */
5034 159271 : load = new redundant_pattern;
5035 :
5036 : /* Convert CONST_VECTOR load no larger than integer register
5037 : to constant integer load even if there is no redundant
5038 : CONST_VECTOR load. */
5039 159271 : if (CONST_VECTOR_P (val))
5040 31676 : threshold = 1;
5041 :
5042 159271 : load->val = copy_rtx (val);
5043 159271 : if (tlsdesc_val)
5044 28 : load->tlsdesc_val = copy_rtx (tlsdesc_val);
5045 : else
5046 : load->tlsdesc_val = nullptr;
5047 159271 : load->mode = scalar_mode;
5048 159271 : load->dest_mode = mode;
5049 159271 : load->size = GET_MODE_SIZE (mode);
5050 159271 : load->def_insn = def_insn;
5051 159271 : load->count = 1;
5052 159271 : load->threshold = threshold;
5053 159271 : load->bb = BLOCK_FOR_INSN (insn);
5054 159271 : load->kind = kind;
5055 :
5056 159271 : bitmap_set_bit (load->insns, INSN_UID (insn));
5057 159271 : bitmap_set_bit (load->bbs, bb->index);
5058 :
5059 159271 : loads.safe_push (load);
5060 : }
5061 : }
5062 :
5063 : bool replaced = false;
5064 1254442 : FOR_EACH_VEC_ELT (loads, i, load)
5065 159271 : if (load->count >= load->threshold)
5066 : {
5067 65724 : machine_mode mode;
5068 65724 : rtx reg, broadcast_reg;
5069 65724 : rtx broadcast_source = nullptr;
5070 65724 : replaced = true;
5071 65724 : switch (load->kind)
5072 : {
5073 320 : case X86_CSE_TLS_GD:
5074 320 : case X86_CSE_TLS_LD_BASE:
5075 320 : case X86_CSE_TLSDESC:
5076 320 : broadcast_reg = gen_reg_rtx (load->mode);
5077 320 : replace_tls_call (broadcast_reg, load->insns,
5078 320 : (load->kind == X86_CSE_TLSDESC
5079 : ? updated_gnu2_tls_insns
5080 : : updated_gnu_tls_insns));
5081 320 : load->broadcast_reg = broadcast_reg;
5082 320 : break;
5083 :
5084 11176 : case X86_CSE_VEC_DUP:
5085 11176 : if (CONST_INT_P (load->val)
5086 10033 : && (load->val == CONST0_RTX (load->mode)
5087 10057 : || load->size <= UNITS_PER_WORD))
5088 : {
5089 : /* Generate CONST_VECTOR load. */
5090 31679 : case X86_CSE_CONST_VECTOR:
5091 31679 : mode = ix86_get_vector_cse_mode (load->size,
5092 : load->mode);
5093 :
5094 31679 : if (CONST_VECTOR_P (load->val))
5095 : broadcast_source = load->val;
5096 3 : else if (load->val == CONST0_RTX (load->mode))
5097 0 : broadcast_source = CONST0_RTX (mode);
5098 3 : else if (load->val == CONSTM1_RTX (load->mode))
5099 0 : broadcast_source = CONSTM1_RTX (mode);
5100 : else
5101 : {
5102 3 : int nunits = GET_MODE_NUNITS (mode);
5103 3 : rtvec v = rtvec_alloc (nunits);
5104 12 : for (int j = 0; j < nunits ; j++)
5105 6 : RTVEC_ELT (v, j) = load->val;
5106 3 : if (CONST_INT_P (load->val)
5107 3 : && GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
5108 : {
5109 1 : gcc_assert (load->size <= UNITS_PER_WORD);
5110 1 : machine_mode imode = GET_MODE_INNER (mode);
5111 1 : class scalar_mode i_mode
5112 1 : = int_mode_for_mode (imode).require ();
5113 1 : mode = mode_for_vector (i_mode,
5114 1 : nunits).require ();
5115 : }
5116 :
5117 3 : broadcast_source = gen_rtx_CONST_VECTOR (mode, v);
5118 : }
5119 :
5120 : /* NB: Zero CONST_VECTOR load works for MMX and XMM
5121 : registers. */
5122 33089 : if (load->size <= UNITS_PER_WORD)
5123 : {
5124 : /* Convert CONST_VECTOR load no larger than integer
5125 : register:
5126 :
5127 : (set (reg:V2SI 106)
5128 : (const_vector:V2SI [(const_int 1 [1]) repeated x2]))
5129 :
5130 : to constant integer load:
5131 :
5132 : (set (subreg:DI (reg:V2SI 106 [ _20 ]) 0)
5133 : (const_int 4294967297 [0x100000001]))
5134 : */
5135 31679 : machine_mode int_mode
5136 31679 : = int_mode_for_mode (mode).require ();
5137 31679 : load->dest_mode = int_mode;
5138 31679 : broadcast_source = simplify_subreg (int_mode,
5139 : broadcast_source,
5140 : mode, 0);
5141 31679 : gcc_assert (broadcast_source != nullptr);
5142 :
5143 31679 : bool keep_const_int_load = false;
5144 31679 : if (!bitmap_empty_p (call_bbs))
5145 : {
5146 28365 : bitmap_iterator bi;
5147 28365 : unsigned int id;
5148 37335 : EXECUTE_IF_SET_IN_BITMAP (load->bbs, 0, id, bi)
5149 29505 : if (bitmap_bit_p (call_bbs, id))
5150 : {
5151 : /* NB: Constant integer load is faster
5152 : than save and restore an integer
5153 : register when crossing a function call.
5154 : */
5155 : keep_const_int_load = true;
5156 : break;
5157 : }
5158 : }
5159 :
5160 28365 : if (keep_const_int_load)
5161 : {
5162 : /* Keep constant integer load. */
5163 20535 : replace_vector_const (mode, broadcast_source,
5164 20535 : load->insns, int_mode);
5165 20535 : load->broadcast_source = nullptr;
5166 20535 : load->broadcast_reg = nullptr;
5167 : }
5168 : else
5169 : {
5170 11144 : broadcast_reg = gen_reg_rtx (mode);
5171 11144 : reg = gen_reg_rtx (load->mode);
5172 11144 : replace_vector_const (mode, broadcast_reg,
5173 11144 : load->insns, load->mode);
5174 11144 : load->broadcast_source = broadcast_source;
5175 11144 : load->broadcast_reg = broadcast_reg;
5176 : }
5177 : break;
5178 : }
5179 : }
5180 : /* FALLTHRU */
5181 :
5182 33725 : case X86_CSE_CONST0_VECTOR:
5183 33725 : case X86_CSE_CONSTM1_VECTOR:
5184 33725 : mode = ix86_get_vector_cse_mode (load->size, load->mode);
5185 33725 : broadcast_reg = gen_reg_rtx (mode);
5186 33725 : if (load->def_insn)
5187 : {
5188 : /* Replace redundant vector loads with a single vector
5189 : load in the same basic block. */
5190 803 : reg = load->val;
5191 803 : if (load->mode != GET_MODE (reg))
5192 0 : reg = gen_rtx_SUBREG (load->mode, reg, 0);
5193 803 : broadcast_source = gen_rtx_VEC_DUPLICATE (mode, reg);
5194 : }
5195 : else
5196 : /* This is a constant integer/double vector. If the
5197 : inner scalar is 0 or -1, set vector to CONST0_RTX
5198 : or CONSTM1_RTX directly. */
5199 32922 : switch (load->kind)
5200 : {
5201 20881 : case X86_CSE_CONST0_VECTOR:
5202 20881 : broadcast_source = CONST0_RTX (mode);
5203 20881 : break;
5204 1668 : case X86_CSE_CONSTM1_VECTOR:
5205 1668 : broadcast_source = CONSTM1_RTX (mode);
5206 1668 : break;
5207 10373 : case X86_CSE_CONST_VECTOR:
5208 10373 : case X86_CSE_VEC_DUP:
5209 10373 : if (!broadcast_source)
5210 : {
5211 10373 : reg = gen_reg_rtx (load->mode);
5212 10373 : broadcast_source = gen_rtx_VEC_DUPLICATE (mode,
5213 : reg);
5214 : }
5215 : break;
5216 0 : default:
5217 0 : gcc_unreachable ();
5218 : }
5219 33725 : replace_vector_const (mode, broadcast_reg, load->insns,
5220 : load->mode);
5221 33725 : load->broadcast_source = broadcast_source;
5222 33725 : load->broadcast_reg = broadcast_reg;
5223 33725 : break;
5224 : }
5225 : }
5226 :
5227 998114 : if (replaced)
5228 : {
5229 42942 : auto_vec<rtx_insn *> control_flow_insns;
5230 :
5231 : /* (Re-)discover loops so that bb->loop_father can be used in the
5232 : analysis below. */
5233 42942 : calculate_dominance_info (CDI_DOMINATORS);
5234 42942 : loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
5235 :
5236 215953 : FOR_EACH_VEC_ELT (loads, i, load)
5237 87127 : if (load->count >= load->threshold)
5238 : {
5239 65724 : rtx set;
5240 65724 : if (load->def_insn)
5241 819 : switch (load->kind)
5242 : {
5243 16 : case X86_CSE_TLSDESC:
5244 16 : ix86_place_single_tls_call (load->broadcast_reg,
5245 : load->tlsdesc_val,
5246 : load->kind,
5247 16 : load->bbs,
5248 : updated_gnu_tls_insns,
5249 : updated_gnu2_tls_insns,
5250 16 : PATTERN (load->def_insn));
5251 16 : break;
5252 803 : case X86_CSE_VEC_DUP:
5253 : /* Insert a broadcast after the original scalar
5254 : definition. */
5255 803 : set = gen_rtx_SET (load->broadcast_reg,
5256 : load->broadcast_source);
5257 803 : insn = emit_insn_after (set, load->def_insn);
5258 :
5259 803 : if (cfun->can_throw_non_call_exceptions)
5260 : {
5261 : /* Handle REG_EH_REGION note in DEF_INSN. */
5262 4 : rtx note = find_reg_note (load->def_insn,
5263 : REG_EH_REGION, nullptr);
5264 4 : if (note)
5265 : {
5266 1 : control_flow_insns.safe_push (load->def_insn);
5267 1 : add_reg_note (insn, REG_EH_REGION,
5268 : XEXP (note, 0));
5269 : }
5270 : }
5271 :
5272 803 : if (dump_file)
5273 : {
5274 0 : fprintf (dump_file, "\nAdd:\n\n");
5275 0 : print_rtl_single (dump_file, insn);
5276 0 : fprintf (dump_file, "\nafter:\n\n");
5277 0 : print_rtl_single (dump_file, load->def_insn);
5278 0 : fprintf (dump_file, "\n");
5279 : }
5280 : break;
5281 0 : default:
5282 0 : gcc_unreachable ();
5283 : }
5284 : else
5285 64905 : switch (load->kind)
5286 : {
5287 304 : case X86_CSE_TLS_GD:
5288 304 : case X86_CSE_TLS_LD_BASE:
5289 304 : case X86_CSE_TLSDESC:
5290 304 : ix86_place_single_tls_call (load->broadcast_reg,
5291 : (load->kind == X86_CSE_TLSDESC
5292 : ? load->tlsdesc_val
5293 : : load->val),
5294 : load->kind,
5295 304 : load->bbs,
5296 : updated_gnu_tls_insns,
5297 : updated_gnu2_tls_insns);
5298 304 : break;
5299 42052 : case X86_CSE_CONST_VECTOR:
5300 42052 : case X86_CSE_VEC_DUP:
5301 : /* Keep redundant constant integer load. */
5302 42052 : if (!load->broadcast_reg)
5303 : break;
5304 : /* FALLTHRU */
5305 44066 : case X86_CSE_CONST0_VECTOR:
5306 44066 : case X86_CSE_CONSTM1_VECTOR:
5307 44066 : ix86_place_single_vector_set (load->broadcast_reg,
5308 : load->broadcast_source,
5309 : load->bbs,
5310 : load);
5311 44066 : break;
5312 : }
5313 : }
5314 :
5315 42942 : loop_optimizer_finalize ();
5316 :
5317 42943 : if (!control_flow_insns.is_empty ())
5318 : {
5319 1 : free_dominance_info (CDI_DOMINATORS);
5320 :
5321 3 : FOR_EACH_VEC_ELT (control_flow_insns, i, insn)
5322 1 : if (control_flow_insn_p (insn))
5323 : {
5324 : /* Split the block after insn. There will be a fallthru
5325 : edge, which is OK so we keep it. We have to create
5326 : the exception edges ourselves. */
5327 1 : bb = BLOCK_FOR_INSN (insn);
5328 1 : split_block (bb, insn);
5329 1 : rtl_make_eh_edge (NULL, bb, BB_END (bb));
5330 : }
5331 : }
5332 :
5333 42942 : df_process_deferred_rescans ();
5334 42942 : }
5335 :
5336 1254442 : FOR_EACH_VEC_ELT (loads, i, load)
5337 318542 : delete load;
5338 :
5339 998114 : df_clear_flags (DF_DEFER_INSN_RESCAN);
5340 :
5341 998114 : timevar_pop (TV_MACH_DEP);
5342 998114 : return 0;
5343 998114 : }
5344 :
5345 : } // anon namespace
5346 :
5347 : rtl_opt_pass *
5348 294245 : make_pass_x86_cse (gcc::context *ctxt)
5349 : {
5350 294245 : return new pass_x86_cse (ctxt);
5351 : }
5352 :
5353 : /* Convert legacy instructions that clobbers EFLAGS to APX_NF
5354 : instructions when there are no flag set between a flag
5355 : producer and user. */
5356 :
5357 : static unsigned int
5358 382 : ix86_apx_nf_convert (void)
5359 : {
5360 382 : timevar_push (TV_MACH_DEP);
5361 :
5362 382 : basic_block bb;
5363 382 : rtx_insn *insn;
5364 382 : hash_map <rtx_insn *, rtx> converting_map;
5365 382 : auto_vec <rtx_insn *> current_convert_list;
5366 :
5367 382 : bool converting_seq = false;
5368 382 : rtx cc = gen_rtx_REG (CCmode, FLAGS_REG);
5369 :
5370 838 : FOR_EACH_BB_FN (bb, cfun)
5371 : {
5372 : /* Reset conversion for each bb. */
5373 456 : converting_seq = false;
5374 5340 : FOR_BB_INSNS (bb, insn)
5375 : {
5376 4884 : if (!NONDEBUG_INSN_P (insn))
5377 4267 : continue;
5378 :
5379 3885 : if (recog_memoized (insn) < 0)
5380 345 : continue;
5381 :
5382 : /* Convert candidate insns after cstore, which should
5383 : satisfy the two conditions:
5384 : 1. Is not flag user or producer, only clobbers
5385 : FLAGS_REG.
5386 : 2. Have corresponding nf pattern. */
5387 :
5388 3540 : rtx pat = PATTERN (insn);
5389 :
5390 : /* Starting conversion at first cstorecc. */
5391 3540 : rtx set = NULL_RTX;
5392 3540 : if (!converting_seq
5393 2949 : && (set = single_set (insn))
5394 2873 : && ix86_comparison_operator (SET_SRC (set), VOIDmode)
5395 131 : && reg_overlap_mentioned_p (cc, SET_SRC (set))
5396 3668 : && !reg_overlap_mentioned_p (cc, SET_DEST (set)))
5397 : {
5398 128 : converting_seq = true;
5399 128 : current_convert_list.truncate (0);
5400 : }
5401 : /* Terminate at the next explicit flag set. */
5402 3412 : else if (reg_set_p (cc, pat)
5403 3412 : && GET_CODE (set_of (cc, pat)) != CLOBBER)
5404 : converting_seq = false;
5405 :
5406 3301 : if (!converting_seq)
5407 2923 : continue;
5408 :
5409 617 : if (get_attr_has_nf (insn)
5410 617 : && GET_CODE (pat) == PARALLEL)
5411 : {
5412 : /* Record the insn to candidate map. */
5413 74 : current_convert_list.safe_push (insn);
5414 74 : converting_map.put (insn, pat);
5415 : }
5416 : /* If the insn clobbers flags but has no nf_attr,
5417 : revoke all previous candidates. */
5418 543 : else if (!get_attr_has_nf (insn)
5419 542 : && reg_set_p (cc, pat)
5420 546 : && GET_CODE (set_of (cc, pat)) == CLOBBER)
5421 : {
5422 3 : for (auto item : current_convert_list)
5423 0 : converting_map.remove (item);
5424 3 : converting_seq = false;
5425 : }
5426 : }
5427 : }
5428 :
5429 382 : if (!converting_map.is_empty ())
5430 : {
5431 88 : for (auto iter = converting_map.begin ();
5432 102 : iter != converting_map.end (); ++iter)
5433 : {
5434 74 : rtx_insn *replace = (*iter).first;
5435 74 : rtx pat = (*iter).second;
5436 74 : int i, n = 0, len = XVECLEN (pat, 0);
5437 74 : rtx *new_elems = XALLOCAVEC (rtx, len);
5438 74 : rtx new_pat;
5439 222 : for (i = 0; i < len; i++)
5440 : {
5441 148 : rtx temp = XVECEXP (pat, 0, i);
5442 222 : if (! (GET_CODE (temp) == CLOBBER
5443 74 : && reg_overlap_mentioned_p (cc,
5444 74 : XEXP (temp, 0))))
5445 : {
5446 74 : new_elems[n] = temp;
5447 74 : n++;
5448 : }
5449 : }
5450 :
5451 74 : if (n == 1)
5452 74 : new_pat = new_elems[0];
5453 : else
5454 0 : new_pat =
5455 0 : gen_rtx_PARALLEL (VOIDmode,
5456 : gen_rtvec_v (n,
5457 : new_elems));
5458 :
5459 74 : PATTERN (replace) = new_pat;
5460 74 : INSN_CODE (replace) = -1;
5461 74 : recog_memoized (replace);
5462 74 : df_insn_rescan (replace);
5463 : }
5464 : }
5465 :
5466 382 : timevar_pop (TV_MACH_DEP);
5467 382 : return 0;
5468 382 : }
5469 :
5470 :
5471 : namespace {
5472 :
5473 : const pass_data pass_data_apx_nf_convert =
5474 : {
5475 : RTL_PASS, /* type */
5476 : "apx_nfcvt", /* name */
5477 : OPTGROUP_NONE, /* optinfo_flags */
5478 : TV_MACH_DEP, /* tv_id */
5479 : 0, /* properties_required */
5480 : 0, /* properties_provided */
5481 : 0, /* properties_destroyed */
5482 : 0, /* todo_flags_start */
5483 : 0, /* todo_flags_finish */
5484 : };
5485 :
5486 : class pass_apx_nf_convert : public rtl_opt_pass
5487 : {
5488 : public:
5489 294245 : pass_apx_nf_convert (gcc::context *ctxt)
5490 588490 : : rtl_opt_pass (pass_data_apx_nf_convert, ctxt)
5491 : {}
5492 :
5493 : /* opt_pass methods: */
5494 1511981 : bool gate (function *) final override
5495 : {
5496 1511981 : return (TARGET_APX_NF
5497 478 : && optimize
5498 1512447 : && optimize_function_for_speed_p (cfun));
5499 : }
5500 :
5501 382 : unsigned int execute (function *) final override
5502 : {
5503 382 : return ix86_apx_nf_convert ();
5504 : }
5505 : }; // class pass_apx_nf_convert
5506 :
5507 : } // anon namespace
5508 :
5509 : rtl_opt_pass *
5510 294245 : make_pass_apx_nf_convert (gcc::context *ctxt)
5511 : {
5512 294245 : return new pass_apx_nf_convert (ctxt);
5513 : }
5514 :
5515 : /* When a hot loop can be fit into one cacheline,
5516 : force align the loop without considering the max skip. */
5517 : static void
5518 997632 : ix86_align_loops ()
5519 : {
5520 997632 : basic_block bb;
5521 :
5522 : /* Don't do this when we don't know cache line size. */
5523 997632 : if (ix86_cost->prefetch_block == 0)
5524 9 : return;
5525 :
5526 997623 : loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
5527 997623 : profile_count count_threshold = cfun->cfg->count_max / param_align_threshold;
5528 11664340 : FOR_EACH_BB_FN (bb, cfun)
5529 : {
5530 10666717 : rtx_insn *label = BB_HEAD (bb);
5531 10666717 : bool has_fallthru = 0;
5532 10666717 : edge e;
5533 10666717 : edge_iterator ei;
5534 :
5535 10666717 : if (!LABEL_P (label))
5536 5427478 : continue;
5537 :
5538 5244053 : profile_count fallthru_count = profile_count::zero ();
5539 5244053 : profile_count branch_count = profile_count::zero ();
5540 :
5541 15236632 : FOR_EACH_EDGE (e, ei, bb->preds)
5542 : {
5543 9992579 : if (e->flags & EDGE_FALLTHRU)
5544 2532215 : has_fallthru = 1, fallthru_count += e->count ();
5545 : else
5546 7460364 : branch_count += e->count ();
5547 : }
5548 :
5549 5244053 : if (!fallthru_count.initialized_p () || !branch_count.initialized_p ())
5550 4814 : continue;
5551 :
5552 5239239 : if (bb->loop_father
5553 5239239 : && bb->loop_father->latch != EXIT_BLOCK_PTR_FOR_FN (cfun)
5554 6608582 : && (has_fallthru
5555 1369343 : ? (!(single_succ_p (bb)
5556 150627 : && single_succ (bb) == EXIT_BLOCK_PTR_FOR_FN (cfun))
5557 943069 : && optimize_bb_for_speed_p (bb)
5558 861459 : && branch_count + fallthru_count > count_threshold
5559 739060 : && (branch_count > fallthru_count * param_align_loop_iterations))
5560 : /* In case there'no fallthru for the loop.
5561 : Nops inserted won't be executed. */
5562 426274 : : (branch_count > count_threshold
5563 139642 : || (bb->count > bb->prev_bb->count * 10
5564 12757 : && (bb->prev_bb->count
5565 5251996 : <= ENTRY_BLOCK_PTR_FOR_FN (cfun)->count / 2)))))
5566 : {
5567 561328 : rtx_insn* insn, *end_insn;
5568 561328 : HOST_WIDE_INT size = 0;
5569 561328 : bool padding_p = true;
5570 561328 : basic_block tbb = bb;
5571 561328 : unsigned cond_branch_num = 0;
5572 561328 : bool detect_tight_loop_p = false;
5573 :
5574 879566 : for (unsigned int i = 0; i != bb->loop_father->num_nodes;
5575 318238 : i++, tbb = tbb->next_bb)
5576 : {
5577 : /* Only handle continuous cfg layout. */
5578 879566 : if (bb->loop_father != tbb->loop_father)
5579 : {
5580 : padding_p = false;
5581 : break;
5582 : }
5583 :
5584 10639793 : FOR_BB_INSNS (tbb, insn)
5585 : {
5586 9966444 : if (!NONDEBUG_INSN_P (insn))
5587 5842329 : continue;
5588 4124115 : size += ix86_min_insn_size (insn);
5589 :
5590 : /* We don't know size of inline asm.
5591 : Don't align loop for call. */
5592 4124115 : if (asm_noperands (PATTERN (insn)) >= 0
5593 4124115 : || CALL_P (insn))
5594 : {
5595 : size = -1;
5596 : break;
5597 : }
5598 : }
5599 :
5600 832382 : if (size == -1 || size > ix86_cost->prefetch_block)
5601 : {
5602 : padding_p = false;
5603 : break;
5604 : }
5605 :
5606 1487691 : FOR_EACH_EDGE (e, ei, tbb->succs)
5607 : {
5608 : /* It could be part of the loop. */
5609 1026218 : if (e->dest == bb)
5610 : {
5611 : detect_tight_loop_p = true;
5612 : break;
5613 : }
5614 : }
5615 :
5616 647427 : if (detect_tight_loop_p)
5617 : break;
5618 :
5619 461473 : end_insn = BB_END (tbb);
5620 461473 : if (JUMP_P (end_insn))
5621 : {
5622 : /* For decoded icache:
5623 : 1. Up to two branches are allowed per Way.
5624 : 2. A non-conditional branch is the last micro-op in a Way.
5625 : */
5626 373118 : if (onlyjump_p (end_insn)
5627 373118 : && (any_uncondjump_p (end_insn)
5628 310189 : || single_succ_p (tbb)))
5629 : {
5630 : padding_p = false;
5631 : break;
5632 : }
5633 310189 : else if (++cond_branch_num >= 2)
5634 : {
5635 : padding_p = false;
5636 : break;
5637 : }
5638 : }
5639 :
5640 : }
5641 :
5642 561328 : if (padding_p && detect_tight_loop_p)
5643 : {
5644 371908 : emit_insn_before (gen_max_skip_align (GEN_INT (ceil_log2 (size)),
5645 : GEN_INT (0)), label);
5646 : /* End of function. */
5647 185954 : if (!tbb || tbb == EXIT_BLOCK_PTR_FOR_FN (cfun))
5648 : break;
5649 : /* Skip bb which already fits into one cacheline. */
5650 : bb = tbb;
5651 : }
5652 : }
5653 : }
5654 :
5655 997623 : loop_optimizer_finalize ();
5656 997623 : free_dominance_info (CDI_DOMINATORS);
5657 : }
5658 :
5659 : namespace {
5660 :
5661 : const pass_data pass_data_align_tight_loops =
5662 : {
5663 : RTL_PASS, /* type */
5664 : "align_tight_loops", /* name */
5665 : OPTGROUP_NONE, /* optinfo_flags */
5666 : TV_MACH_DEP, /* tv_id */
5667 : 0, /* properties_required */
5668 : 0, /* properties_provided */
5669 : 0, /* properties_destroyed */
5670 : 0, /* todo_flags_start */
5671 : 0, /* todo_flags_finish */
5672 : };
5673 :
5674 : class pass_align_tight_loops : public rtl_opt_pass
5675 : {
5676 : public:
5677 294245 : pass_align_tight_loops (gcc::context *ctxt)
5678 588490 : : rtl_opt_pass (pass_data_align_tight_loops, ctxt)
5679 : {}
5680 :
5681 : /* opt_pass methods: */
5682 1511981 : bool gate (function *) final override
5683 : {
5684 1511981 : return TARGET_ALIGN_TIGHT_LOOPS
5685 1511492 : && optimize
5686 2575244 : && optimize_function_for_speed_p (cfun);
5687 : }
5688 :
5689 997632 : unsigned int execute (function *) final override
5690 : {
5691 997632 : timevar_push (TV_MACH_DEP);
5692 : #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
5693 997632 : ix86_align_loops ();
5694 : #endif
5695 997632 : timevar_pop (TV_MACH_DEP);
5696 997632 : return 0;
5697 : }
5698 : }; // class pass_align_tight_loops
5699 :
5700 : } // anon namespace
5701 :
5702 : rtl_opt_pass *
5703 294245 : make_pass_align_tight_loops (gcc::context *ctxt)
5704 : {
5705 294245 : return new pass_align_tight_loops (ctxt);
5706 : }
5707 :
5708 : /* This compares the priority of target features in function DECL1
5709 : and DECL2. It returns positive value if DECL1 is higher priority,
5710 : negative value if DECL2 is higher priority and 0 if they are the
5711 : same. */
5712 :
5713 : int
5714 5829 : ix86_compare_version_priority (tree decl1, tree decl2)
5715 : {
5716 5829 : unsigned int priority1 = get_builtin_code_for_version (decl1, NULL);
5717 5829 : unsigned int priority2 = get_builtin_code_for_version (decl2, NULL);
5718 :
5719 5829 : return (int)priority1 - (int)priority2;
5720 : }
5721 :
5722 : /* V1 and V2 point to function versions with different priorities
5723 : based on the target ISA. This function compares their priorities. */
5724 :
5725 : static int
5726 6882 : feature_compare (const void *v1, const void *v2)
5727 : {
5728 6882 : typedef struct _function_version_info
5729 : {
5730 : tree version_decl;
5731 : tree predicate_chain;
5732 : unsigned int dispatch_priority;
5733 : } function_version_info;
5734 :
5735 6882 : const function_version_info c1 = *(const function_version_info *)v1;
5736 6882 : const function_version_info c2 = *(const function_version_info *)v2;
5737 6882 : return (c2.dispatch_priority - c1.dispatch_priority);
5738 : }
5739 :
5740 : /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
5741 : to return a pointer to VERSION_DECL if the outcome of the expression
5742 : formed by PREDICATE_CHAIN is true. This function will be called during
5743 : version dispatch to decide which function version to execute. It returns
5744 : the basic block at the end, to which more conditions can be added. */
5745 :
5746 : static basic_block
5747 846 : add_condition_to_bb (tree function_decl, tree version_decl,
5748 : tree predicate_chain, basic_block new_bb)
5749 : {
5750 846 : gimple *return_stmt;
5751 846 : tree convert_expr, result_var;
5752 846 : gimple *convert_stmt;
5753 846 : gimple *call_cond_stmt;
5754 846 : gimple *if_else_stmt;
5755 :
5756 846 : basic_block bb1, bb2, bb3;
5757 846 : edge e12, e23;
5758 :
5759 846 : tree cond_var, and_expr_var = NULL_TREE;
5760 846 : gimple_seq gseq;
5761 :
5762 846 : tree predicate_decl, predicate_arg;
5763 :
5764 846 : push_cfun (DECL_STRUCT_FUNCTION (function_decl));
5765 :
5766 846 : gcc_assert (new_bb != NULL);
5767 846 : gseq = bb_seq (new_bb);
5768 :
5769 :
5770 846 : convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
5771 : build_fold_addr_expr (version_decl));
5772 846 : result_var = create_tmp_var (ptr_type_node);
5773 846 : convert_stmt = gimple_build_assign (result_var, convert_expr);
5774 846 : return_stmt = gimple_build_return (result_var);
5775 :
5776 846 : if (predicate_chain == NULL_TREE)
5777 : {
5778 203 : gimple_seq_add_stmt (&gseq, convert_stmt);
5779 203 : gimple_seq_add_stmt (&gseq, return_stmt);
5780 203 : set_bb_seq (new_bb, gseq);
5781 203 : gimple_set_bb (convert_stmt, new_bb);
5782 203 : gimple_set_bb (return_stmt, new_bb);
5783 203 : pop_cfun ();
5784 203 : return new_bb;
5785 : }
5786 :
5787 1325 : while (predicate_chain != NULL)
5788 : {
5789 682 : cond_var = create_tmp_var (integer_type_node);
5790 682 : predicate_decl = TREE_PURPOSE (predicate_chain);
5791 682 : predicate_arg = TREE_VALUE (predicate_chain);
5792 682 : call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
5793 682 : gimple_call_set_lhs (call_cond_stmt, cond_var);
5794 :
5795 682 : gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
5796 682 : gimple_set_bb (call_cond_stmt, new_bb);
5797 682 : gimple_seq_add_stmt (&gseq, call_cond_stmt);
5798 :
5799 682 : predicate_chain = TREE_CHAIN (predicate_chain);
5800 :
5801 682 : if (and_expr_var == NULL)
5802 : and_expr_var = cond_var;
5803 : else
5804 : {
5805 39 : gimple *assign_stmt;
5806 : /* Use MIN_EXPR to check if any integer is zero?.
5807 : and_expr_var = min_expr <cond_var, and_expr_var> */
5808 39 : assign_stmt = gimple_build_assign (and_expr_var,
5809 : build2 (MIN_EXPR, integer_type_node,
5810 : cond_var, and_expr_var));
5811 :
5812 39 : gimple_set_block (assign_stmt, DECL_INITIAL (function_decl));
5813 39 : gimple_set_bb (assign_stmt, new_bb);
5814 39 : gimple_seq_add_stmt (&gseq, assign_stmt);
5815 : }
5816 : }
5817 :
5818 643 : if_else_stmt = gimple_build_cond (GT_EXPR, and_expr_var,
5819 : integer_zero_node,
5820 : NULL_TREE, NULL_TREE);
5821 643 : gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
5822 643 : gimple_set_bb (if_else_stmt, new_bb);
5823 643 : gimple_seq_add_stmt (&gseq, if_else_stmt);
5824 :
5825 643 : gimple_seq_add_stmt (&gseq, convert_stmt);
5826 643 : gimple_seq_add_stmt (&gseq, return_stmt);
5827 643 : set_bb_seq (new_bb, gseq);
5828 :
5829 643 : bb1 = new_bb;
5830 643 : e12 = split_block (bb1, if_else_stmt);
5831 643 : bb2 = e12->dest;
5832 643 : e12->flags &= ~EDGE_FALLTHRU;
5833 643 : e12->flags |= EDGE_TRUE_VALUE;
5834 :
5835 643 : e23 = split_block (bb2, return_stmt);
5836 :
5837 643 : gimple_set_bb (convert_stmt, bb2);
5838 643 : gimple_set_bb (return_stmt, bb2);
5839 :
5840 643 : bb3 = e23->dest;
5841 643 : make_edge (bb1, bb3, EDGE_FALSE_VALUE);
5842 :
5843 643 : remove_edge (e23);
5844 643 : make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
5845 :
5846 643 : pop_cfun ();
5847 :
5848 643 : return bb3;
5849 : }
5850 :
5851 : /* This function generates the dispatch function for
5852 : multi-versioned functions. DISPATCH_DECL is the function which will
5853 : contain the dispatch logic. FNDECLS are the function choices for
5854 : dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
5855 : in DISPATCH_DECL in which the dispatch code is generated. */
5856 :
5857 : static int
5858 203 : dispatch_function_versions (tree dispatch_decl,
5859 : void *fndecls_p,
5860 : basic_block *empty_bb)
5861 : {
5862 203 : tree default_decl;
5863 203 : gimple *ifunc_cpu_init_stmt;
5864 203 : gimple_seq gseq;
5865 203 : int ix;
5866 203 : tree ele;
5867 203 : vec<tree> *fndecls;
5868 203 : unsigned int num_versions = 0;
5869 203 : unsigned int actual_versions = 0;
5870 203 : unsigned int i;
5871 :
5872 203 : struct _function_version_info
5873 : {
5874 : tree version_decl;
5875 : tree predicate_chain;
5876 : unsigned int dispatch_priority;
5877 : }*function_version_info;
5878 :
5879 203 : gcc_assert (dispatch_decl != NULL
5880 : && fndecls_p != NULL
5881 : && empty_bb != NULL);
5882 :
5883 : /*fndecls_p is actually a vector. */
5884 203 : fndecls = static_cast<vec<tree> *> (fndecls_p);
5885 :
5886 : /* At least one more version other than the default. */
5887 203 : num_versions = fndecls->length ();
5888 203 : gcc_assert (num_versions >= 2);
5889 :
5890 203 : function_version_info = (struct _function_version_info *)
5891 203 : XNEWVEC (struct _function_version_info, (num_versions - 1));
5892 :
5893 : /* The first version in the vector is the default decl. */
5894 203 : default_decl = (*fndecls)[0];
5895 :
5896 203 : push_cfun (DECL_STRUCT_FUNCTION (dispatch_decl));
5897 :
5898 203 : gseq = bb_seq (*empty_bb);
5899 : /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
5900 : constructors, so explicitly call __builtin_cpu_init here. */
5901 203 : ifunc_cpu_init_stmt
5902 203 : = gimple_build_call_vec (get_ix86_builtin (IX86_BUILTIN_CPU_INIT), vNULL);
5903 203 : gimple_seq_add_stmt (&gseq, ifunc_cpu_init_stmt);
5904 203 : gimple_set_bb (ifunc_cpu_init_stmt, *empty_bb);
5905 203 : set_bb_seq (*empty_bb, gseq);
5906 :
5907 203 : pop_cfun ();
5908 :
5909 :
5910 1206 : for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
5911 : {
5912 800 : tree version_decl = ele;
5913 800 : tree predicate_chain = NULL_TREE;
5914 800 : unsigned int priority;
5915 : /* Get attribute string, parse it and find the right predicate decl.
5916 : The predicate function could be a lengthy combination of many
5917 : features, like arch-type and various isa-variants. */
5918 800 : priority = get_builtin_code_for_version (version_decl,
5919 : &predicate_chain);
5920 :
5921 800 : if (predicate_chain == NULL_TREE)
5922 157 : continue;
5923 :
5924 643 : function_version_info [actual_versions].version_decl = version_decl;
5925 643 : function_version_info [actual_versions].predicate_chain
5926 643 : = predicate_chain;
5927 643 : function_version_info [actual_versions].dispatch_priority = priority;
5928 643 : actual_versions++;
5929 : }
5930 :
5931 : /* Sort the versions according to descending order of dispatch priority. The
5932 : priority is based on the ISA. This is not a perfect solution. There
5933 : could still be ambiguity. If more than one function version is suitable
5934 : to execute, which one should be dispatched? In future, allow the user
5935 : to specify a dispatch priority next to the version. */
5936 203 : qsort (function_version_info, actual_versions,
5937 : sizeof (struct _function_version_info), feature_compare);
5938 :
5939 1049 : for (i = 0; i < actual_versions; ++i)
5940 643 : *empty_bb = add_condition_to_bb (dispatch_decl,
5941 : function_version_info[i].version_decl,
5942 643 : function_version_info[i].predicate_chain,
5943 : *empty_bb);
5944 :
5945 : /* dispatch default version at the end. */
5946 203 : *empty_bb = add_condition_to_bb (dispatch_decl, default_decl,
5947 : NULL, *empty_bb);
5948 :
5949 203 : free (function_version_info);
5950 203 : return 0;
5951 : }
5952 :
5953 : /* This function changes the assembler name for functions that are
5954 : versions. If DECL is a function version and has a "target"
5955 : attribute, it appends the attribute string to its assembler name. */
5956 :
5957 : static tree
5958 1125 : ix86_mangle_function_version_assembler_name (tree decl, tree id)
5959 : {
5960 1125 : tree version_attr;
5961 1125 : char *attr_str;
5962 :
5963 1125 : if (DECL_DECLARED_INLINE_P (decl)
5964 1174 : && lookup_attribute ("gnu_inline",
5965 49 : DECL_ATTRIBUTES (decl)))
5966 0 : error_at (DECL_SOURCE_LOCATION (decl),
5967 : "function versions cannot be marked as %<gnu_inline%>,"
5968 : " bodies have to be generated");
5969 :
5970 1125 : if (DECL_VIRTUAL_P (decl)
5971 2250 : || DECL_VINDEX (decl))
5972 0 : sorry ("virtual function multiversioning not supported");
5973 :
5974 1125 : version_attr = lookup_attribute ("target", DECL_ATTRIBUTES (decl));
5975 :
5976 : /* target attribute string cannot be NULL. */
5977 1125 : gcc_assert (version_attr != NULL_TREE);
5978 :
5979 1125 : attr_str = sorted_attr_string (TREE_VALUE (version_attr));
5980 :
5981 : /* Allow assembler name to be modified if already set. */
5982 1125 : if (DECL_ASSEMBLER_NAME_SET_P (decl))
5983 1110 : SET_DECL_RTL (decl, NULL);
5984 :
5985 1125 : tree ret = clone_identifier (id, attr_str, true);
5986 :
5987 1125 : XDELETEVEC (attr_str);
5988 :
5989 1125 : return ret;
5990 : }
5991 :
5992 : tree
5993 503001985 : ix86_mangle_decl_assembler_name (tree decl, tree id)
5994 : {
5995 : /* For function version, add the target suffix to the assembler name. */
5996 503001985 : if (TREE_CODE (decl) == FUNCTION_DECL)
5997 : {
5998 466209373 : cgraph_node *node = cgraph_node::get (decl);
5999 : /* Mangle all versions when annotated with target_clones, but only
6000 : non-default versions when annotated with target attributes. */
6001 466209373 : if (DECL_FUNCTION_VERSIONED (decl)
6002 466209373 : && (node->is_target_clone
6003 1092 : || !is_function_default_version (node->decl)))
6004 1125 : id = ix86_mangle_function_version_assembler_name (decl, id);
6005 : /* Mangle the dispatched symbol but only in the case of target clones. */
6006 466208248 : else if (node && node->dispatcher_function && !node->is_target_clone)
6007 117 : id = clone_identifier (id, "ifunc");
6008 68112265 : else if (node && node->dispatcher_resolver_function)
6009 203 : id = clone_identifier (id, "resolver");
6010 : }
6011 : #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
6012 : id = SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME (decl, id);
6013 : #endif
6014 :
6015 503001985 : return id;
6016 : }
6017 :
6018 : /* Make a dispatcher declaration for the multi-versioned function DECL.
6019 : Calls to DECL function will be replaced with calls to the dispatcher
6020 : by the front-end. Returns the decl of the dispatcher function. */
6021 :
6022 : tree
6023 329 : ix86_get_function_versions_dispatcher (void *decl)
6024 : {
6025 329 : tree fn = (tree) decl;
6026 329 : struct cgraph_node *node = NULL;
6027 329 : struct cgraph_node *default_node = NULL;
6028 329 : struct cgraph_function_version_info *node_v = NULL;
6029 :
6030 329 : tree dispatch_decl = NULL;
6031 :
6032 329 : struct cgraph_function_version_info *default_version_info = NULL;
6033 :
6034 658 : gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
6035 :
6036 329 : node = cgraph_node::get (fn);
6037 329 : gcc_assert (node != NULL);
6038 :
6039 329 : node_v = node->function_version ();
6040 329 : gcc_assert (node_v != NULL);
6041 :
6042 329 : if (node_v->dispatcher_resolver != NULL)
6043 : return node_v->dispatcher_resolver;
6044 :
6045 : /* The default node is always the beginning of the chain. */
6046 : default_version_info = node_v;
6047 680 : while (default_version_info->prev != NULL)
6048 : default_version_info = default_version_info->prev;
6049 215 : default_node = default_version_info->this_node;
6050 :
6051 : /* If there is no default node, just return NULL. */
6052 215 : if (!is_function_default_version (default_node->decl))
6053 : return NULL;
6054 :
6055 : #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
6056 206 : if (targetm.has_ifunc_p ())
6057 : {
6058 206 : struct cgraph_function_version_info *it_v = NULL;
6059 :
6060 : /* Right now, the dispatching is done via ifunc. */
6061 206 : dispatch_decl = make_dispatcher_decl (default_node->decl);
6062 :
6063 : /* Set the dispatcher for all the versions. */
6064 206 : it_v = default_version_info;
6065 1421 : while (it_v != NULL)
6066 : {
6067 1009 : it_v->dispatcher_resolver = dispatch_decl;
6068 1009 : it_v = it_v->next;
6069 : }
6070 : }
6071 : else
6072 : #endif
6073 : {
6074 0 : error_at (DECL_SOURCE_LOCATION (default_node->decl),
6075 : "multiversioning needs %<ifunc%> which is not supported "
6076 : "on this target");
6077 : }
6078 :
6079 : return dispatch_decl;
6080 : }
6081 :
6082 : /* Make the resolver function decl to dispatch the versions of
6083 : a multi-versioned function, DEFAULT_DECL. IFUNC_ALIAS_DECL is
6084 : ifunc alias that will point to the created resolver. Create an
6085 : empty basic block in the resolver and store the pointer in
6086 : EMPTY_BB. Return the decl of the resolver function. */
6087 :
6088 : static tree
6089 203 : make_resolver_func (const tree default_decl,
6090 : const tree ifunc_alias_decl,
6091 : basic_block *empty_bb)
6092 : {
6093 203 : tree decl, type, t;
6094 :
6095 : /* The resolver function should return a (void *). */
6096 203 : type = build_function_type_list (ptr_type_node, NULL_TREE);
6097 :
6098 203 : cgraph_node *node = cgraph_node::get (default_decl);
6099 203 : gcc_assert (node && node->function_version ());
6100 :
6101 203 : decl = build_fn_decl (IDENTIFIER_POINTER (DECL_NAME (default_decl)), type);
6102 :
6103 : /* Set the assembler name to prevent cgraph_node attempting to mangle. */
6104 203 : SET_DECL_ASSEMBLER_NAME (decl, DECL_ASSEMBLER_NAME (default_decl));
6105 :
6106 203 : cgraph_node *resolver_node = cgraph_node::get_create (decl);
6107 203 : resolver_node->dispatcher_resolver_function = true;
6108 :
6109 203 : if (node->is_target_clone)
6110 89 : resolver_node->is_target_clone = true;
6111 :
6112 203 : tree id = ix86_mangle_decl_assembler_name
6113 203 : (decl, node->function_version ()->assembler_name);
6114 203 : symtab->change_decl_assembler_name (decl, id);
6115 :
6116 203 : DECL_NAME (decl) = DECL_NAME (default_decl);
6117 203 : TREE_USED (decl) = 1;
6118 203 : DECL_ARTIFICIAL (decl) = 1;
6119 203 : DECL_IGNORED_P (decl) = 1;
6120 203 : TREE_PUBLIC (decl) = 0;
6121 203 : DECL_UNINLINABLE (decl) = 1;
6122 :
6123 : /* Resolver is not external, body is generated. */
6124 203 : DECL_EXTERNAL (decl) = 0;
6125 203 : DECL_EXTERNAL (ifunc_alias_decl) = 0;
6126 :
6127 203 : DECL_CONTEXT (decl) = NULL_TREE;
6128 203 : DECL_INITIAL (decl) = make_node (BLOCK);
6129 203 : DECL_STATIC_CONSTRUCTOR (decl) = 0;
6130 :
6131 203 : if (DECL_COMDAT_GROUP (default_decl)
6132 203 : || TREE_PUBLIC (default_decl))
6133 : {
6134 : /* In this case, each translation unit with a call to this
6135 : versioned function will put out a resolver. Ensure it
6136 : is comdat to keep just one copy. */
6137 178 : DECL_COMDAT (decl) = 1;
6138 178 : make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
6139 : }
6140 : else
6141 25 : TREE_PUBLIC (ifunc_alias_decl) = 0;
6142 :
6143 : /* Build result decl and add to function_decl. */
6144 203 : t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
6145 203 : DECL_CONTEXT (t) = decl;
6146 203 : DECL_ARTIFICIAL (t) = 1;
6147 203 : DECL_IGNORED_P (t) = 1;
6148 203 : DECL_RESULT (decl) = t;
6149 :
6150 203 : gimplify_function_tree (decl);
6151 203 : push_cfun (DECL_STRUCT_FUNCTION (decl));
6152 203 : *empty_bb = init_lowered_empty_function (decl, false,
6153 : profile_count::uninitialized ());
6154 :
6155 203 : cgraph_node::add_new_function (decl, true);
6156 203 : symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
6157 :
6158 203 : pop_cfun ();
6159 :
6160 203 : gcc_assert (ifunc_alias_decl != NULL);
6161 : /* Mark ifunc_alias_decl as "ifunc" with resolver as resolver_name. */
6162 203 : DECL_ATTRIBUTES (ifunc_alias_decl)
6163 203 : = make_attribute ("ifunc", IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)),
6164 203 : DECL_ATTRIBUTES (ifunc_alias_decl));
6165 :
6166 : /* Create the alias for dispatch to resolver here. */
6167 203 : cgraph_node::create_same_body_alias (ifunc_alias_decl, decl);
6168 203 : return decl;
6169 : }
6170 :
6171 : /* Generate the dispatching code body to dispatch multi-versioned function
6172 : DECL. The target hook is called to process the "target" attributes and
6173 : provide the code to dispatch the right function at run-time. NODE points
6174 : to the dispatcher decl whose body will be created. */
6175 :
6176 : tree
6177 203 : ix86_generate_version_dispatcher_body (void *node_p)
6178 : {
6179 203 : tree resolver_decl;
6180 203 : basic_block empty_bb;
6181 203 : tree default_ver_decl;
6182 203 : struct cgraph_node *versn;
6183 203 : struct cgraph_node *node;
6184 :
6185 203 : struct cgraph_function_version_info *node_version_info = NULL;
6186 203 : struct cgraph_function_version_info *versn_info = NULL;
6187 :
6188 203 : node = (cgraph_node *)node_p;
6189 :
6190 203 : node_version_info = node->function_version ();
6191 203 : gcc_assert (node->dispatcher_function
6192 : && node_version_info != NULL);
6193 :
6194 203 : if (node_version_info->dispatcher_resolver)
6195 : return node_version_info->dispatcher_resolver;
6196 :
6197 : /* The first version in the chain corresponds to the default version. */
6198 203 : default_ver_decl = node_version_info->next->this_node->decl;
6199 :
6200 : /* node is going to be an alias, so remove the finalized bit. */
6201 203 : node->definition = false;
6202 :
6203 203 : resolver_decl = make_resolver_func (default_ver_decl,
6204 : node->decl, &empty_bb);
6205 :
6206 203 : node_version_info->dispatcher_resolver = resolver_decl;
6207 :
6208 203 : push_cfun (DECL_STRUCT_FUNCTION (resolver_decl));
6209 :
6210 203 : auto_vec<tree, 2> fn_ver_vec;
6211 :
6212 1206 : for (versn_info = node_version_info->next; versn_info;
6213 1003 : versn_info = versn_info->next)
6214 : {
6215 1003 : versn = versn_info->this_node;
6216 : /* Check for virtual functions here again, as by this time it should
6217 : have been determined if this function needs a vtable index or
6218 : not. This happens for methods in derived classes that override
6219 : virtual methods in base classes but are not explicitly marked as
6220 : virtual. */
6221 1003 : if (DECL_VIRTUAL_P (versn->decl))
6222 0 : sorry ("virtual function multiversioning not supported");
6223 :
6224 1003 : fn_ver_vec.safe_push (versn->decl);
6225 : }
6226 :
6227 203 : dispatch_function_versions (resolver_decl, &fn_ver_vec, &empty_bb);
6228 203 : cgraph_edge::rebuild_edges ();
6229 203 : pop_cfun ();
6230 203 : return resolver_decl;
6231 203 : }
6232 :
6233 :
|
