Line data Source code
1 : ;; GCC machine description for MMX and 3dNOW! instructions
2 : ;; Copyright (C) 2005-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; The MMX and 3dNOW! patterns are in the same file because they use
21 : ;; the same register file, and 3dNOW! adds a number of extensions to
22 : ;; the base integer MMX isa.
23 :
24 : ;; Note! Except for the basic move instructions, *all* of these
25 : ;; patterns are outside the normal optabs namespace. This is because
26 : ;; use of these registers requires the insertion of emms or femms
27 : ;; instructions to return to normal fpu mode. The compiler doesn't
28 : ;; know how to do that itself, which means it's up to the user. Which
29 : ;; means that we should never use any of these patterns except at the
30 : ;; direction of the user via a builtin.
31 :
32 : (define_c_enum "unspec" [
33 : UNSPEC_3DNOW
34 :
35 : UNSPEC_MOVNTQ
36 : UNSPEC_PFRCP
37 : UNSPEC_PFRCPIT1
38 : UNSPEC_PFRCPIT2
39 : UNSPEC_PFRSQRT
40 : UNSPEC_PFRSQIT1
41 : ])
42 :
43 : (define_c_enum "unspecv" [
44 : UNSPECV_EMMS
45 : UNSPECV_FEMMS
46 : ])
47 :
48 : ;; 8 byte integral modes handled by MMX (and by extension, SSE)
49 : (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
50 283 : (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")])
51 56 :
52 : ;; All 8-byte vector modes handled by MMX
53 : (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF V4HF V4BF])
54 14574 : (define_mode_iterator MMXMODE124 [V8QI V4HI V2SI V2SF])
55 14574 :
56 14574 : ;; Mix-n-match
57 : (define_mode_iterator MMXMODE12 [V8QI V4HI])
58 14574 : (define_mode_iterator MMXMODE14 [V8QI V2SI])
59 : (define_mode_iterator MMXMODE24 [V4HI V2SI])
60 : (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
61 :
62 : ;; All 4-byte integer/float16 vector modes
63 : (define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF])
64 :
65 : (define_mode_iterator V2FI_32 [V2HF V2BF V2HI])
66 : (define_mode_iterator V4FI_64 [V4HF V4BF V4HI])
67 : (define_mode_iterator V4F_64 [V4HF V4BF])
68 : (define_mode_iterator V2F_32 [V2HF V2BF])
69 : ;; 4-byte integer vector modes
70 : (define_mode_iterator VI_32 [V4QI V2HI])
71 :
72 : ;; 8-byte and 4-byte HImode vector modes
73 110 : (define_mode_iterator VI2_32_64 [(V4HI "TARGET_MMX_WITH_SSE") V2HI])
74 7 :
75 82 : ;; 8-byte, 4-byte and 2-byte QImode vector modes
76 5 : (define_mode_iterator VI1_16_32_64 [(V8QI "TARGET_MMX_WITH_SSE") V4QI V2QI])
77 23 :
78 12 : ;; 4-byte and 2-byte integer vector modes
79 22 : (define_mode_iterator VI_16_32 [V4QI V2QI V2HI])
80 22 :
81 45 : ;; 4-byte and 2-byte QImode vector modes
82 6 : (define_mode_iterator VI1_16_32 [V4QI V2QI])
83 6 :
84 17 : ;; All 2-byte, 4-byte and 8-byte vector modes.
85 : (define_mode_iterator V_16_32_64
86 : [V2QI V4QI V2HI V1SI V2HF V2BF
87 3718 : (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT")
88 2294 : (V4HF "TARGET_64BIT") (V4BF "TARGET_64BIT")
89 52440 : (V2SI "TARGET_64BIT") (V2SF "TARGET_64BIT")
90 18517 : (V1DI "TARGET_64BIT")])
91 31455330 :
92 32172479 : ;; V2S* modes
93 49888640 : (define_mode_iterator V2FI [V2SF V2SI])
94 77199009 :
95 58706321 : (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI])
96 37001288 :
97 13778684 : (define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI])
98 :
99 : (define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI])
100 :
101 : ;; Mapping from integer vector mode to mnemonic suffix
102 : (define_mode_attr mmxvecsize
103 : [(V8QI "b") (V4QI "b") (V2QI "b")
104 : (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
105 :
106 : ;; Mapping to same size integral mode.
107 : (define_mode_attr mmxinsnmode
108 : [(V8QI "DI") (V4QI "SI") (V2QI "HI")
109 : (V4HI "DI") (V2HI "SI")
110 : (V2SI "DI")
111 : (V1DI "DI") (V1SI "SI")
112 : (V4HF "DI") (V2HF "SI")
113 : (V4BF "DI") (V2BF "SI")
114 : (V2SF "DI")])
115 :
116 : (define_mode_attr mmxdoublemode
117 : [(V8QI "V8HI") (V4HI "V4SI")])
118 :
119 : (define_mode_attr mmxhalfmode
120 : [(V4HI "V4QI") (V2HI "V2QI")])
121 :
122 : (define_mode_attr mmxbytemode
123 : [(V4HI "V8QI") (V2HI "V4QI")])
124 :
125 : (define_mode_attr mmxhalfmodelower
126 : [(V4HI "v4qi") (V2HI "v2qi")])
127 :
128 : ;; Mapping of vector float modes to an integer mode of the same size
129 : (define_mode_attr mmxintvecmode
130 : [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
131 : (V4HF "V4HI") (V2HF "V2HI") (V4BF "V4HI") (V2BF "V2HI")])
132 :
133 : (define_mode_attr mmxintvecmodelower
134 : [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")
135 : (V4HF "v4hi") (V2HF "v2hi")])
136 :
137 : ;; Mapping of vector modes to a vector mode of double size
138 : (define_mode_attr mmxdoublevecmode
139 : [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")
140 : (V2HI "V4HI") (V2HF "V4HF") (V2BF "V4BF")])
141 :
142 : ;; Mapping of vector modes back to the scalar modes
143 : (define_mode_attr mmxscalarmode
144 : [(V2SI "SI") (V2SF "SF")
145 : (V4HF "HF") (V4BF "BF")
146 : (V2HF "HF") (V2BF "BF")
147 : (V4HI "HI") (V2HI "HI")
148 : (V8QI "QI")])
149 :
150 : (define_mode_attr mmxscalarmodelower
151 : [(V2SI "si") (V2SF "sf")
152 : (V4HF "hf") (V4BF "bf")
153 : (V2HF "hf") (V2BF "bf")
154 : (V4HI "hi") (V2HI "hi")
155 : (V8QI "qi")])
156 :
157 : (define_mode_attr mmxscalarsize
158 : [(V1DI "64")
159 : (V2SI "32") (V2SF "32")
160 : (V4HF "16") (V4BF "16")
161 : (V2HF "16") (V2BF "16")
162 : (V4HI "16") (V2HI "16")
163 : (V8QI "8")])
164 :
165 : (define_mode_attr Yv_Yw
166 : [(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")])
167 :
168 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
169 : ;;
170 : ;; Move patterns
171 : ;;
172 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
173 :
174 : ;; All of these patterns are enabled for MMX as well as 3dNOW.
175 : ;; This is essential for maintaining stable calling conventions.
176 :
177 : (define_expand "mov<mode>"
178 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
179 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"))]
180 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
181 483527 : {
182 483527 : ix86_expand_vector_move (<MODE>mode, operands);
183 483527 : DONE;
184 : })
185 :
186 : (define_insn "*mov<mode>_internal"
187 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
188 : "=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!y,v,v,v,m,r,v,!y,*x")
189 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"
190 : "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))]
191 72203973 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
192 71869849 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))
193 71523265 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
194 218790 : {
195 28035442 : switch (get_attr_type (insn))
196 859330 : {
197 27819301 : case TYPE_MULTI:
198 : return "#";
199 384 :
200 52938 : case TYPE_IMOV:
201 53322 : if (get_attr_mode (insn) == MODE_SI)
202 : return "mov{l}\t{%1, %k0|%k0, %1}";
203 : else
204 52860 : return "mov{q}\t{%1, %0|%0, %1}";
205 :
206 0 : case TYPE_MMX:
207 0 : return "pxor\t%0, %0";
208 :
209 547 : case TYPE_MMXMOV:
210 : /* Handle broken assemblers that require movd instead of movq. */
211 547 : if (!HAVE_AS_IX86_INTERUNIT_MOVQ
212 : && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
213 : return "movd\t{%1, %0|%0, %1}";
214 547 : return "movq\t{%1, %0|%0, %1}";
215 :
216 147 : case TYPE_SSECVT:
217 147 : if (SSE_REG_P (operands[0]))
218 : return "movq2dq\t{%1, %0|%0, %1}";
219 : else
220 41 : return "movdq2q\t{%1, %0|%0, %1}";
221 :
222 1757 : case TYPE_SSELOG1:
223 1757 : return standard_sse_constant_opcode (insn, operands);
224 :
225 163401 : case TYPE_SSEMOV:
226 163401 : return ix86_output_ssemov (insn, operands);
227 :
228 0 : default:
229 0 : gcc_unreachable ();
230 : }
231 : }
232 : [(set (attr "isa")
233 : (cond [(eq_attr "alternative" "0,1")
234 : (const_string "nox64")
235 222807 : (eq_attr "alternative" "2,3,4,9,10")
236 : (const_string "x64")
237 : (eq_attr "alternative" "15,16")
238 : (const_string "x64_sse2")
239 : (eq_attr "alternative" "17,18")
240 : (const_string "sse2")
241 : ]
242 : (const_string "*")))
243 : (set (attr "type")
244 : (cond [(eq_attr "alternative" "0,1")
245 : (const_string "multi")
246 : (eq_attr "alternative" "2,3,4")
247 : (const_string "imov")
248 : (eq_attr "alternative" "5")
249 : (const_string "mmx")
250 : (eq_attr "alternative" "6,7,8,9,10")
251 : (const_string "mmxmov")
252 : (eq_attr "alternative" "11")
253 : (const_string "sselog1")
254 : (eq_attr "alternative" "17,18")
255 : (const_string "ssecvt")
256 : ]
257 : (const_string "ssemov")))
258 : (set (attr "prefix_rex")
259 : (if_then_else (eq_attr "alternative" "9,10,15,16")
260 : (const_string "1")
261 : (const_string "*")))
262 : (set (attr "prefix")
263 : (if_then_else (eq_attr "type" "sselog1,ssemov")
264 : (const_string "maybe_vex")
265 : (const_string "orig")))
266 : (set (attr "prefix_data16")
267 : (if_then_else
268 : (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
269 : (const_string "1")
270 : (const_string "*")))
271 : (set (attr "mode")
272 : (cond [(eq_attr "alternative" "2")
273 : (const_string "SI")
274 : (eq_attr "alternative" "11,12")
275 : (cond [(match_test "<MODE>mode == V2SFmode
276 : || <MODE>mode == V4HFmode
277 : || <MODE>mode == V4BFmode")
278 : (const_string "V4SF")
279 : (ior (not (match_test "TARGET_SSE2"))
280 : (match_test "optimize_function_for_size_p (cfun)"))
281 48516 : (const_string "V4SF")
282 : ]
283 : (const_string "TI"))
284 :
285 : (and (eq_attr "alternative" "13")
286 1735977 : (ior (ior (and (match_test "<MODE>mode == V2SFmode")
287 : (not (match_test "TARGET_MMX_WITH_SSE")))
288 : (not (match_test "TARGET_SSE2")))
289 : (match_test "<MODE>mode == V4HFmode
290 : || <MODE>mode == V4BFmode")))
291 : (const_string "V2SF")
292 :
293 : (and (eq_attr "alternative" "14")
294 5460877 : (ior (ior (match_test "<MODE>mode == V2SFmode")
295 : (not (match_test "TARGET_SSE2")))
296 : (match_test "<MODE>mode == V4HFmode
297 : || <MODE>mode == V4BFmode")))
298 : (const_string "V2SF")
299 5753225 : ]
300 5753225 : (const_string "DI")))
301 5753225 : (set (attr "preferred_for_speed")
302 : (cond [(eq_attr "alternative" "9,15")
303 17936 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
304 : (eq_attr "alternative" "10,16")
305 5604218 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
306 : ]
307 306173 : (symbol_ref "true")))])
308 :
309 : (define_split
310 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
311 : (match_operand:MMXMODE 1 "nonimmediate_gr_operand"))]
312 197143 : "!TARGET_64BIT && reload_completed"
313 66351 : [(const_int 0)]
314 791505 : "ix86_split_long_move (operands); DONE;")
315 36587 :
316 725154 : (define_split
317 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
318 : (match_operand:MMXMODE 1 "const0_operand"))]
319 34024 : "!TARGET_64BIT && reload_completed"
320 17308 : [(const_int 0)]
321 64789 : "ix86_split_long_move (operands); DONE;")
322 42135 :
323 73277 : (define_expand "movmisalign<mode>"
324 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
325 5316 : (match_operand:MMXMODE 1 "nonimmediate_operand"))]
326 17207 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
327 128455 : {
328 135115 : ix86_expand_vector_move (<MODE>mode, operands);
329 123139 : DONE;
330 17207 : })
331 :
332 145578 : (define_expand "mov<mode>"
333 : [(set (match_operand:V_32 0 "nonimmediate_operand")
334 145578 : (match_operand:V_32 1 "nonimm_or_0_operand"))]
335 145578 : ""
336 160899 : {
337 43076 : ix86_expand_vector_move (<MODE>mode, operands);
338 43076 : DONE;
339 : })
340 :
341 : (define_insn "*mov<mode>_internal"
342 15150 : [(set (match_operand:V_32 0 "nonimmediate_operand"
343 0 : "=r ,m ,v,v,v,m,r,v")
344 15150 : (match_operand:V_32 1 "nonimm_or_0_operand"
345 15150 : "rmC,rC,C,v,m,v,v,r"))]
346 9966994 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
347 40171896 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
348 17530 : {
349 18638043 : switch (get_attr_type (insn))
350 3 : {
351 18620513 : case TYPE_IMOV:
352 0 : return "mov{l}\t{%1, %0|%0, %1}";
353 :
354 165 : case TYPE_SSELOG1:
355 165 : return standard_sse_constant_opcode (insn, operands);
356 0 :
357 7219 : case TYPE_SSEMOV:
358 7219 : return ix86_output_ssemov (insn, operands);
359 :
360 0 : default:
361 0 : gcc_unreachable ();
362 : }
363 : }
364 : [(set (attr "isa")
365 : (cond [(eq_attr "alternative" "6,7")
366 : (const_string "sse2")
367 5111 : ]
368 : (const_string "*")))
369 : (set (attr "type")
370 : (cond [(eq_attr "alternative" "2")
371 : (const_string "sselog1")
372 : (eq_attr "alternative" "3,4,5,6,7")
373 : (const_string "ssemov")
374 : ]
375 : (const_string "imov")))
376 : (set (attr "prefix")
377 : (if_then_else (eq_attr "type" "sselog1,ssemov")
378 : (const_string "maybe_vex")
379 : (const_string "orig")))
380 : (set (attr "prefix_data16")
381 : (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
382 : (const_string "1")
383 : (const_string "*")))
384 : (set (attr "mode")
385 : (cond [(eq_attr "alternative" "2,3")
386 : (cond [(match_test "<MODE>mode == V2HFmode
387 132165 : || <MODE>mode == V2BFmode")
388 : (const_string "V4SF")
389 : (match_test "TARGET_AVX")
390 : (const_string "TI")
391 26537 : (ior (not (match_test "TARGET_SSE2"))
392 9777 : (match_test "optimize_function_for_size_p (cfun)"))
393 : (const_string "V4SF")
394 : ]
395 : (const_string "TI"))
396 :
397 : (and (eq_attr "alternative" "4,5")
398 : (ior (match_test "<MODE>mode == V2HFmode
399 : || <MODE>mode == V2BFmode")
400 : (not (match_test "TARGET_SSE2"))))
401 : (const_string "SF")
402 : ]
403 : (const_string "SI")))
404 : (set (attr "preferred_for_speed")
405 : (cond [(eq_attr "alternative" "6")
406 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
407 : (eq_attr "alternative" "7")
408 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
409 : ]
410 : (symbol_ref "true")))])
411 :
412 : ;; For TARGET_64BIT we always round up to 8 bytes.
413 : (define_insn "*push<mode>2_rex64"
414 : [(set (match_operand:V_32 0 "push_operand" "=X,X")
415 : (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))]
416 3 : "TARGET_64BIT"
417 : "@
418 18620510 : push{q}\t%q1
419 18620510 : #"
420 : [(set_attr "type" "push,multi")
421 : (set_attr "mode" "DI")])
422 :
423 58899259 : (define_split
424 58899259 : [(set (match_operand:V_32 0 "push_operand")
425 40372247 : (match_operand:V_32 1 "sse_reg_operand"))]
426 90891172 : "TARGET_64BIT && TARGET_SSE && reload_completed"
427 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
428 : (set (match_dup 0) (match_dup 1))]
429 0 : {
430 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<V_32:MODE>mode)));
431 : /* Preserve memory attributes. */
432 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
433 : })
434 :
435 : (define_expand "movmisalign<mode>"
436 0 : [(set (match_operand:V_32 0 "nonimmediate_operand")
437 : (match_operand:V_32 1 "nonimmediate_operand"))]
438 : ""
439 8504 : {
440 8504 : ix86_expand_vector_move (<MODE>mode, operands);
441 8504 : DONE;
442 : })
443 :
444 : (define_expand "movv2qi"
445 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
446 53294 : (match_operand:V2QI 1 "nonimm_or_0_operand"))]
447 2791 : ""
448 98084 : {
449 56085 : ix86_expand_vector_move (V2QImode, operands);
450 53294 : DONE;
451 2791 : })
452 :
453 : (define_insn "*movv2qi_internal"
454 : [(set (match_operand:V2QI 0 "nonimmediate_operand"
455 2302 : "=r,r,r,m ,v,v,v,jm,m,r,v")
456 : (match_operand:V2QI 1 "nonimm_or_0_operand"
457 2302 : "r ,C,m,rC,C,v,m,x,v,v,r"))]
458 8285212 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
459 8270785 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
460 9777 : {
461 3804473 : switch (get_attr_type (insn))
462 3794696 : {
463 6324 : case TYPE_IMOV:
464 3786346 : if (get_attr_mode (insn) == MODE_SI)
465 3780022 : return "mov{l}\t{%k1, %k0|%k0, %k1}";
466 0 : else
467 6140 : return "mov{w}\t{%1, %0|%0, %1}";
468 0 :
469 4262942 : case TYPE_IMOVX:
470 4262942 : /* movzwl is faster than movw on p2 due to partial word stalls,
471 1768178 : though not as fast as an aligned movl. */
472 4364608 : return "movz{wl|x}\t{%1, %k0|%k0, %1}";
473 :
474 403 : case TYPE_SSELOG1:
475 403 : if (satisfies_constraint_C (operands[1]))
476 46 : return standard_sse_constant_opcode (insn, operands);
477 :
478 357 : if (SSE_REG_P (operands[0]))
479 : return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
480 : else
481 25 : return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
482 :
483 388 : case TYPE_SSEMOV:
484 388 : return ix86_output_ssemov (insn, operands);
485 :
486 0 : default:
487 0 : gcc_unreachable ();
488 : }
489 : }
490 : [(set (attr "isa")
491 : (cond [(eq_attr "alternative" "6,9,10")
492 : (const_string "sse2")
493 0 : (eq_attr "alternative" "7")
494 : (const_string "sse4_noavx")
495 : (eq_attr "alternative" "8")
496 : (const_string "avx")
497 : ]
498 : (const_string "*")))
499 : (set (attr "addr")
500 : (if_then_else (eq_attr "alternative" "7")
501 : (const_string "gpr16")
502 : (const_string "*")))
503 : (set (attr "type")
504 : (cond [(eq_attr "alternative" "6,7,8")
505 : (if_then_else (match_test "TARGET_AVX512FP16")
506 : (const_string "ssemov")
507 : (const_string "sselog1"))
508 : (eq_attr "alternative" "4")
509 : (const_string "sselog1")
510 : (eq_attr "alternative" "5,9,10")
511 : (const_string "ssemov")
512 : (match_test "optimize_function_for_size_p (cfun)")
513 : (const_string "imov")
514 : (and (eq_attr "alternative" "0")
515 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
516 0 : (not (match_test "TARGET_HIMODE_MATH"))))
517 : (const_string "imov")
518 : (and (eq_attr "alternative" "1,2")
519 : (match_operand:V2QI 1 "aligned_operand"))
520 24180033 : (const_string "imov")
521 108077686 : (and (match_test "TARGET_MOVX")
522 : (eq_attr "alternative" "0,2"))
523 : (const_string "imovx")
524 18704751 : ]
525 27046667 : (const_string "imov")))
526 27046667 : (set (attr "prefix")
527 27103921 : (cond [(eq_attr "alternative" "4,5,6,7,8,9,10")
528 : (const_string "maybe_evex")
529 0 : ]
530 134050725 : (const_string "orig")))
531 122913346 : (set (attr "mode")
532 95949349 : (cond [(eq_attr "alternative" "6,7,8")
533 77280 : (if_then_else (match_test "TARGET_AVX512FP16")
534 60495 : (const_string "HI")
535 8744481 : (const_string "TI"))
536 95362827 : (eq_attr "alternative" "9,10")
537 16785 : (if_then_else (match_test "TARGET_AVX512FP16")
538 38040881 : (const_string "HI")
539 38040881 : (const_string "SI"))
540 95346488 : (eq_attr "alternative" "4")
541 38040881 : (cond [(match_test "TARGET_AVX")
542 37665 : (const_string "TI")
543 38040881 : (ior (not (match_test "TARGET_SSE2"))
544 129243470 : (match_test "optimize_function_for_size_p (cfun)"))
545 : (const_string "V4SF")
546 5101586 : ]
547 5101586 : (const_string "TI"))
548 5101586 : (eq_attr "alternative" "5")
549 : (cond [(match_test "TARGET_AVX512FP16")
550 : (const_string "HF")
551 : (match_test "TARGET_AVX")
552 : (const_string "TI")
553 76 : (ior (not (match_test "TARGET_SSE2"))
554 76 : (match_test "optimize_function_for_size_p (cfun)"))
555 76 : (const_string "V4SF")
556 : ]
557 26509471 : (const_string "TI"))
558 26509471 : (eq_attr "type" "imovx")
559 26509471 : (const_string "SI")
560 : (and (eq_attr "alternative" "1,2")
561 : (match_operand:V2QI 1 "aligned_operand"))
562 : (const_string "SI")
563 25933592 : (and (eq_attr "alternative" "0")
564 16974 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
565 16974 : (not (match_test "TARGET_HIMODE_MATH"))))
566 16974 : (const_string "SI")
567 25950566 : ]
568 : (const_string "HI")))
569 : (set (attr "preferred_for_speed")
570 : (cond [(eq_attr "alternative" "9")
571 24963252 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
572 : (eq_attr "alternative" "10")
573 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
574 : ]
575 : (symbol_ref "true")))])
576 9826 :
577 9826 : (define_split
578 9826 : [(set (match_operand:V_16_32_64 0 "general_reg_operand")
579 : (match_operand:V_16_32_64 1 "memory_operand"))]
580 26822411 : "reload_completed
581 26829272 : && SYMBOL_REF_P (XEXP (operands[1], 0))
582 26819614 : && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
583 2792 : [(set (match_dup 0) (match_dup 1))]
584 56501 : {
585 56501 : rtx op1 = avoid_constant_pool_reference (operands[1]);
586 26575616 :
587 73355 : if (!CONST_VECTOR_P (op1))
588 22985 : FAIL;
589 41275 :
590 24954511 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
591 14602 :
592 38229 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
593 38229 : operands[1] = GEN_INT (val);
594 21124372 : })
595 :
596 : ;; 16-bit, 32-bit and 64-bit constant vector stores. After reload,
597 23627 : ;; convert them to immediate integer stores.
598 : (define_insn_and_split "*mov<mode>_imm"
599 : [(set (match_operand:V_16_32_64 0 "memory_operand" "=m")
600 23627 : (match_operand:V_16_32_64 1 "x86_64_const_vector_operand" "i"))]
601 : ""
602 : "#"
603 1554954 : "&& reload_completed"
604 1559497 : [(set (match_dup 0) (match_dup 1))]
605 1559497 : {
606 1607236 : rtx op1 = operands[1];
607 129500 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
608 146900 :
609 124047 : operands[0] = adjust_address (operands[0], <mmxinsnmode>mode, 0);
610 1783142 : operands[1] = GEN_INT (val);
611 : })
612 9384817 :
613 9384817 : ;; We always round up to UNITS_PER_WORD bytes.
614 10594519 : (define_insn "*pushv2qi2"
615 : [(set (match_operand:V2QI 0 "push_operand" "=X,X")
616 773170 : (match_operand:V2QI 1 "nonmemory_no_elim_operand" "rC,v"))]
617 30339 : ""
618 422433 : "* return TARGET_64BIT ? \"push{q}\t%q1\" : \"push{l}\t%k1\";
619 422433 : #"
620 422433 : [(set_attr "isa" "*,sse4")
621 : (set_attr "type" "push,multi")
622 62787 : (set (attr "mode")
623 42841 : (cond [(eq_attr "alternative" "0")
624 1108297 : (if_then_else (match_test "TARGET_64BIT")
625 1109441 : (const_string "DI")
626 1107889 : (const_string "SI"))
627 42841 : (eq_attr "alternative" "1")
628 41697 : (if_then_else (match_test "TARGET_AVX512FP16")
629 41697 : (const_string "HI")
630 92696 : (const_string "TI"))
631 92696 : ]
632 92696 : (const_string "HI")))])
633 51524 :
634 : (define_split
635 327 : [(set (match_operand:V2QI 0 "push_operand")
636 327 : (match_operand:V2QI 1 "sse_reg_operand"))]
637 0 : "TARGET_SSE4_1 && reload_completed"
638 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
639 : (set (match_dup 0) (match_dup 1))]
640 0 : {
641 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (V2QImode)));
642 0 : /* Preserve memory attributes. */
643 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
644 0 : })
645 :
646 : (define_expand "movmisalignv2qi"
647 0 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
648 : (match_operand:V2QI 1 "nonimmediate_operand"))]
649 : ""
650 5551 : {
651 5551 : ix86_expand_vector_move (V2QImode, operands);
652 5551 : DONE;
653 80280 : })
654 80280 :
655 80280 : (define_insn "sse_movntq"
656 : [(set (match_operand:DI 0 "memory_operand" "=m,m")
657 3284 : (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
658 0 : UNSPEC_MOVNTQ))]
659 83317 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
660 3284 : && (TARGET_SSE || TARGET_3DNOW_A)"
661 3284 : "@
662 0 : movntq\t{%1, %0|%0, %1}
663 79971 : movnti\t{%1, %0|%0, %1}"
664 1024 : [(set_attr "isa" "*,x64")
665 1024 : (set_attr "mmx_isa" "native,*")
666 26 : (set_attr "type" "mmxmov,ssemov")
667 291 : (set_attr "mode" "DI")])
668 317 :
669 0 : (define_expand "movq_<mode>_to_sse"
670 26 : [(set (match_operand:<mmxdoublevecmode> 0 "register_operand")
671 : (vec_concat:<mmxdoublevecmode>
672 95715 : (match_operand:V24FI 1 "nonimmediate_operand")
673 95715 : (match_dup 2)))]
674 95715 : "TARGET_SSE2"
675 15503 : {
676 15503 : if (<MODE>mode != V2SImode
677 15121 : && !flag_trapping_math)
678 1014 : {
679 9897 : rtx op1 = force_reg (<MODE>mode, operands[1]);
680 9897 : emit_move_insn (operands[0], lowpart_subreg (<mmxdoublevecmode>mode,
681 : op1, <MODE>mode));
682 9897 : DONE;
683 : }
684 :
685 5606 : operands[2] = CONST0_RTX (<MODE>mode);
686 : })
687 :
688 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
689 : ;;
690 5606 : ;; Parallel single-precision floating point arithmetic
691 995451 : ;;
692 995451 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
693 995451 :
694 1001057 : (define_expand "<code>v2sf2"
695 : [(set (match_operand:V2SF 0 "register_operand")
696 : (absneg:V2SF
697 : (match_operand:V2SF 1 "register_operand")))]
698 953803 : "TARGET_MMX_WITH_SSE"
699 432 : "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
700 :
701 396 : (define_insn_and_split "*mmx_<code>v2sf2"
702 954199 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
703 367 : (absneg:V2SF
704 : (match_operand:V2SF 1 "register_operand" "0,x,x")))
705 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
706 954211 : "TARGET_MMX_WITH_SSE"
707 29 : "#"
708 72 : "&& reload_completed"
709 : [(set (match_dup 0)
710 41 : (<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
711 1980 : {
712 62 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
713 1947 : std::swap (operands[1], operands[2]);
714 1956 : }
715 6984 : [(set_attr "isa" "noavx,noavx,avx")])
716 5050 :
717 5064 : (define_insn_and_split "*mmx_nabsv2sf2"
718 5028 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
719 5028 : (neg:V2SF
720 : (abs:V2SF
721 36 : (match_operand:V2SF 1 "register_operand" "0,x,x"))))
722 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
723 0 : "TARGET_MMX_WITH_SSE"
724 : "#"
725 0 : "&& reload_completed"
726 151 : [(set (match_dup 0)
727 0 : (ior:V2SF (match_dup 1) (match_dup 2)))]
728 2756 : {
729 2756 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
730 2756 : std::swap (operands[1], operands[2]);
731 2605 : }
732 2605 : [(set_attr "isa" "noavx,noavx,avx")])
733 2605 :
734 2605 : (define_expand "<insn>v2sf3"
735 2605 : [(set (match_operand:V2SF 0 "register_operand")
736 2605 : (plusminusmult:V2SF
737 2605 : (match_operand:V2SF 1 "nonimmediate_operand")
738 0 : (match_operand:V2SF 2 "nonimmediate_operand")))]
739 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
740 5552 : {
741 5552 : rtx op2 = gen_reg_rtx (V4SFmode);
742 5552 : rtx op1 = gen_reg_rtx (V4SFmode);
743 5611 : rtx op0 = gen_reg_rtx (V4SFmode);
744 :
745 5611 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
746 6679 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
747 1127 :
748 6620 : emit_insn (gen_<insn>v4sf3 (op0, op1, op2));
749 :
750 5552 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
751 5552 : DONE;
752 1051 : })
753 :
754 : (define_expand "mmx_addv2sf3"
755 : [(parallel
756 1051 : [(set (match_operand:V2SF 0 "register_operand")
757 : (plus:V2SF
758 : (match_operand:V2SF 1 "nonimmediate_operand")
759 : (match_operand:V2SF 2 "nonimmediate_operand")))
760 1051 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
761 : "TARGET_3DNOW"
762 18 : "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
763 :
764 : (define_insn "*mmx_addv2sf3"
765 42 : [(set (match_operand:V2SF 0 "register_operand" "=y")
766 18 : (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
767 42 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
768 42 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
769 161649 : "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
770 161548 : "pfadd\t{%2, %0|%0, %2}"
771 161553 : [(set_attr "type" "mmxadd")
772 161535 : (set_attr "prefix_extra" "1")
773 296 : (set_attr "mode" "V2SF")])
774 296 :
775 : (define_expand "mmx_subv2sf3"
776 74 : [(parallel
777 103 : [(set (match_operand:V2SF 0 "register_operand")
778 74 : (minus:V2SF (match_operand:V2SF 1 "register_operand")
779 75 : (match_operand:V2SF 2 "nonimmediate_operand")))
780 0 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
781 215723 : "TARGET_3DNOW")
782 215663 :
783 215648 : (define_expand "mmx_subrv2sf3"
784 15 : [(parallel
785 15 : [(set (match_operand:V2SF 0 "register_operand")
786 15 : (minus:V2SF (match_operand:V2SF 2 "register_operand")
787 : (match_operand:V2SF 1 "nonimmediate_operand")))
788 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
789 : "TARGET_3DNOW")
790 :
791 : (define_insn "*mmx_subv2sf3"
792 698938 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
793 698938 : (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
794 698938 : (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))
795 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
796 0 : "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
797 : "@
798 97433 : pfsub\t{%2, %0|%0, %2}
799 : pfsubr\t{%1, %0|%0, %1}"
800 : [(set_attr "type" "mmxadd")
801 : (set_attr "prefix_extra" "1")
802 55000 : (set_attr "mode" "V2SF")])
803 :
804 48 : (define_expand "mmx_mulv2sf3"
805 48 : [(parallel
806 48 : [(set (match_operand:V2SF 0 "register_operand")
807 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
808 : (match_operand:V2SF 2 "nonimmediate_operand")))
809 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
810 48 : "TARGET_3DNOW"
811 34808 : "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
812 34832 :
813 34832 : (define_insn "*mmx_mulv2sf3"
814 : [(set (match_operand:V2SF 0 "register_operand" "=y")
815 15 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
816 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
817 29972 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
818 78 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
819 9 : "pfmul\t{%2, %0|%0, %2}"
820 15 : [(set_attr "type" "mmxmul")
821 29972 : (set_attr "prefix_extra" "1")
822 : (set_attr "mode" "V2SF")])
823 :
824 : (define_expand "divv2sf3"
825 : [(set (match_operand:V2SF 0 "register_operand")
826 380745 : (div:V2SF (match_operand:V2SF 1 "register_operand")
827 380744 : (match_operand:V2SF 2 "register_operand")))]
828 1 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
829 68 : {
830 642854 : rtx op2 = gen_reg_rtx (V4SFmode);
831 642853 : rtx op1 = gen_reg_rtx (V4SFmode);
832 540216 : rtx op0 = gen_reg_rtx (V4SFmode);
833 :
834 68 : rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
835 : force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
836 68 : emit_insn (gen_rtx_SET (op2, tmp));
837 68 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
838 :
839 68 : emit_insn (gen_divv4sf3 (op0, op1, op2));
840 :
841 68 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
842 68 : DONE;
843 : })
844 :
845 : (define_expand "<code>v2sf3"
846 : [(set (match_operand:V2SF 0 "register_operand")
847 : (smaxmin:V2SF
848 : (match_operand:V2SF 1 "register_operand")
849 : (match_operand:V2SF 2 "register_operand")))]
850 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
851 142 : {
852 142 : rtx op2 = gen_reg_rtx (V4SFmode);
853 142 : rtx op1 = gen_reg_rtx (V4SFmode);
854 142 : rtx op0 = gen_reg_rtx (V4SFmode);
855 :
856 144 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
857 1892090 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
858 1891950 :
859 1892092 : emit_insn (gen_<code>v4sf3 (op0, op1, op2));
860 2 :
861 142 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
862 142 : DONE;
863 : })
864 :
865 : (define_expand "mmx_<code>v2sf3"
866 : [(parallel
867 : [(set (match_operand:V2SF 0 "register_operand")
868 281745 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
869 281745 : (match_operand:V2SF 2 "nonimmediate_operand")))
870 281745 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
871 : "TARGET_3DNOW"
872 28 : {
873 28 : if (!flag_finite_math_only || flag_signed_zeros)
874 : {
875 28 : operands[1] = force_reg (V2SFmode, operands[1]);
876 287 : emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
877 : (operands[0], operands[1], operands[2]));
878 287 : DONE;
879 259 : }
880 259 : else
881 0 : ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
882 : })
883 :
884 : ;; These versions of the min/max patterns are intentionally ignorant of
885 : ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
886 0 : ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
887 : ;; are undefined in this condition, we're certain this is correct.
888 :
889 : (define_insn "*mmx_<code>v2sf3"
890 : [(set (match_operand:V2SF 0 "register_operand" "=y")
891 0 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
892 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
893 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
894 0 : "TARGET_3DNOW && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
895 : "pf<maxmin_float>\t{%2, %0|%0, %2}"
896 8 : [(set_attr "type" "mmxadd")
897 : (set_attr "prefix_extra" "1")
898 8 : (set_attr "mode" "V2SF")])
899 8 :
900 8 : ;; These versions of the min/max patterns implement exactly the operations
901 : ;; min = (op1 < op2 ? op1 : op2)
902 : ;; max = (!(op1 < op2) ? op1 : op2)
903 429196 : ;; Their operands are not commutative, and thus they may be used in the
904 429196 : ;; presence of -0.0 and NaN.
905 :
906 236920 : (define_insn "mmx_ieee_<ieee_maxmin>v2sf3"
907 236920 : [(set (match_operand:V2SF 0 "register_operand" "=y")
908 : (unspec:V2SF
909 : [(match_operand:V2SF 1 "register_operand" "0")
910 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
911 : IEEE_MAXMIN))
912 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
913 63 : "TARGET_3DNOW"
914 : "pf<ieee_maxmin>\t{%2, %0|%0, %2}"
915 : [(set_attr "type" "mmxadd")
916 : (set_attr "prefix_extra" "1")
917 7811 : (set_attr "mode" "V2SF")])
918 332 :
919 7811 : (define_insn "mmx_rcpv2sf2"
920 : [(set (match_operand:V2SF 0 "register_operand" "=y")
921 7479 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
922 7479 : UNSPEC_PFRCP))]
923 7550 : "TARGET_3DNOW"
924 7479 : "pfrcp\t{%1, %0|%0, %1}"
925 7479 : [(set_attr "type" "mmx")
926 : (set_attr "prefix_extra" "1")
927 7557 : (set_attr "mode" "V2SF")])
928 7557 :
929 : (define_insn "mmx_rcpit1v2sf3"
930 7352 : [(set (match_operand:V2SF 0 "register_operand" "=y")
931 7352 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
932 7352 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
933 7274 : UNSPEC_PFRCPIT1))]
934 7425 : "TARGET_3DNOW"
935 7345 : "pfrcpit1\t{%2, %0|%0, %2}"
936 7345 : [(set_attr "type" "mmx")
937 71 : (set_attr "prefix_extra" "1")
938 7368 : (set_attr "mode" "V2SF")])
939 7368 :
940 7274 : (define_insn "mmx_rcpit2v2sf3"
941 7368 : [(set (match_operand:V2SF 0 "register_operand" "=y")
942 7274 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
943 7274 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
944 7274 : UNSPEC_PFRCPIT2))]
945 7354 : "TARGET_3DNOW"
946 : "pfrcpit2\t{%2, %0|%0, %2}"
947 6477 : [(set_attr "type" "mmx")
948 : (set_attr "prefix_extra" "1")
949 872 : (set_attr "mode" "V2SF")])
950 872 :
951 778 : (define_expand "sqrtv2sf2"
952 94 : [(set (match_operand:V2SF 0 "register_operand")
953 778 : (sqrt:V2SF (match_operand:V2SF 1 "nonimmediate_operand")))]
954 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
955 8 : {
956 8 : rtx op1 = gen_reg_rtx (V4SFmode);
957 8 : rtx op0 = gen_reg_rtx (V4SFmode);
958 :
959 8 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
960 0 :
961 8 : emit_insn (gen_sqrtv4sf2 (op0, op1));
962 :
963 8 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
964 8 : DONE;
965 : })
966 :
967 : (define_insn "mmx_rsqrtv2sf2"
968 : [(set (match_operand:V2SF 0 "register_operand" "=y")
969 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
970 : UNSPEC_PFRSQRT))]
971 71 : "TARGET_3DNOW"
972 : "pfrsqrt\t{%1, %0|%0, %1}"
973 : [(set_attr "type" "mmx")
974 : (set_attr "prefix_extra" "1")
975 2016 : (set_attr "mode" "V2SF")])
976 2016 :
977 122 : (define_insn "mmx_rsqit1v2sf3"
978 210 : [(set (match_operand:V2SF 0 "register_operand" "=y")
979 332 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
980 332 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
981 122 : UNSPEC_PFRSQIT1))]
982 289 : "TARGET_3DNOW"
983 209 : "pfrsqit1\t{%2, %0|%0, %2}"
984 209 : [(set_attr "type" "mmx")
985 : (set_attr "prefix_extra" "1")
986 116102 : (set_attr "mode" "V2SF")])
987 116102 :
988 146 : (define_expand "mmx_haddv2sf3"
989 4950 : [(set (match_operand:V2SF 0 "register_operand")
990 28 : (vec_concat:V2SF
991 : (plus:SF
992 : (vec_select:SF
993 : (match_operand:V2SF 1 "register_operand")
994 : (parallel [(const_int 0)]))
995 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
996 : (plus:SF
997 : (vec_select:SF
998 : (match_operand:V2SF 2 "nonimmediate_operand")
999 : (parallel [(const_int 0)]))
1000 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1001 : "TARGET_3DNOW")
1002 :
1003 : (define_insn "*mmx_haddv2sf3"
1004 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1005 : (vec_concat:V2SF
1006 : (plus:SF
1007 : (vec_select:SF
1008 : (match_operand:V2SF 1 "register_operand" "0")
1009 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1010 : (vec_select:SF (match_dup 1)
1011 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))
1012 : (plus:SF
1013 : (vec_select:SF
1014 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1015 : (parallel [(match_operand:SI 5 "const_0_to_1_operand")]))
1016 : (vec_select:SF (match_dup 2)
1017 : (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))]
1018 79 : "TARGET_3DNOW
1019 79 : && INTVAL (operands[3]) != INTVAL (operands[4])
1020 79 : && INTVAL (operands[5]) != INTVAL (operands[6])"
1021 0 : "pfacc\t{%2, %0|%0, %2}"
1022 : [(set_attr "type" "mmxadd")
1023 : (set_attr "prefix_extra" "1")
1024 1681 : (set_attr "mode" "V2SF")])
1025 1681 :
1026 : (define_insn_and_split "*mmx_haddv2sf3_low"
1027 173 : [(set (match_operand:SF 0 "register_operand")
1028 1854 : (plus:SF
1029 1508 : (vec_select:SF
1030 173 : (match_operand:V2SF 1 "nonimmediate_operand")
1031 173 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))
1032 173 : (vec_select:SF
1033 173 : (match_dup 1)
1034 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
1035 162 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1036 162 : && INTVAL (operands[2]) != INTVAL (operands[3])
1037 3 : && ix86_pre_reload_split ()"
1038 177 : "#"
1039 159 : "&& 1"
1040 217 : [(const_int 0)]
1041 101 : {
1042 259 : rtx op1 = gen_reg_rtx (V4SFmode);
1043 724 : rtx op0 = gen_reg_rtx (V4SFmode);
1044 803 :
1045 200 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1046 30 :
1047 46 : emit_insn (gen_sse3_haddv4sf3 (op0, op1, op1));
1048 80 :
1049 81 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1050 81 : DONE;
1051 80 : })
1052 :
1053 80 : (define_insn "mmx_hsubv2sf3"
1054 80 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1055 80 : (vec_concat:V2SF
1056 80 : (minus:SF
1057 : (vec_select:SF
1058 : (match_operand:V2SF 1 "register_operand" "0")
1059 : (parallel [(const_int 0)]))
1060 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1061 : (minus:SF
1062 724 : (vec_select:SF
1063 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1064 724 : (parallel [(const_int 0)]))
1065 724 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1066 804 : "TARGET_3DNOW_A"
1067 : "pfnacc\t{%2, %0|%0, %2}"
1068 : [(set_attr "type" "mmxadd")
1069 : (set_attr "prefix_extra" "1")
1070 79 : (set_attr "mode" "V2SF")])
1071 79 :
1072 79 : (define_insn_and_split "*mmx_hsubv2sf3_low"
1073 79 : [(set (match_operand:SF 0 "register_operand")
1074 : (minus:SF
1075 79 : (vec_select:SF
1076 79 : (match_operand:V2SF 1 "register_operand")
1077 79 : (parallel [(const_int 0)]))
1078 : (vec_select:SF
1079 79 : (match_dup 1)
1080 79 : (parallel [(const_int 1)]))))]
1081 82 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1082 3 : && ix86_pre_reload_split ()"
1083 79 : "#"
1084 79 : "&& 1"
1085 79 : [(const_int 0)]
1086 13 : {
1087 91 : rtx op1 = gen_reg_rtx (V4SFmode);
1088 390 : rtx op0 = gen_reg_rtx (V4SFmode);
1089 389 :
1090 12 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1091 109 :
1092 125 : emit_insn (gen_sse3_hsubv4sf3 (op0, op1, op1));
1093 79 :
1094 1 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1095 80 : DONE;
1096 79 : })
1097 79 :
1098 : (define_expand "mmx_haddsubv2sf3"
1099 79 : [(set (match_operand:V2SF 0 "register_operand")
1100 79 : (vec_concat:V2SF
1101 79 : (minus:SF
1102 : (vec_select:SF
1103 : (match_operand:V2SF 1 "register_operand")
1104 : (parallel [(const_int 0)]))
1105 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1106 : (plus:SF
1107 14 : (vec_select:SF
1108 : (match_operand:V2SF 2 "nonimmediate_operand")
1109 14 : (parallel [(const_int 0)]))
1110 14 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1111 14 : "TARGET_3DNOW_A")
1112 :
1113 : (define_insn "*mmx_haddsubv2sf3"
1114 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1115 : (vec_concat:V2SF
1116 : (minus:SF
1117 : (vec_select:SF
1118 : (match_operand:V2SF 1 "register_operand" "0")
1119 : (parallel [(const_int 0)]))
1120 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1121 : (plus:SF
1122 : (vec_select:SF
1123 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1124 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1125 : (vec_select:SF
1126 : (match_dup 2)
1127 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))))]
1128 79 : "TARGET_3DNOW_A
1129 79 : && INTVAL (operands[3]) != INTVAL (operands[4])"
1130 : "pfpnacc\t{%2, %0|%0, %2}"
1131 : [(set_attr "type" "mmxadd")
1132 : (set_attr "prefix_extra" "1")
1133 : (set_attr "mode" "V2SF")])
1134 :
1135 : (define_expand "vec_addsubv2sf3"
1136 : [(set (match_operand:V2SF 0 "register_operand")
1137 3191251 : (vec_merge:V2SF
1138 3191251 : (minus:V2SF
1139 3191251 : (match_operand:V2SF 1 "nonimmediate_operand")
1140 3191251 : (match_operand:V2SF 2 "nonimmediate_operand"))
1141 3191251 : (plus:V2SF (match_dup 1) (match_dup 2))
1142 3191251 : (const_int 1)))]
1143 3191251 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1144 257 : {
1145 96995 : rtx op2 = gen_reg_rtx (V4SFmode);
1146 96995 : rtx op1 = gen_reg_rtx (V4SFmode);
1147 92692 : rtx op0 = gen_reg_rtx (V4SFmode);
1148 189173 :
1149 8155 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1150 89097 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1151 :
1152 83266 : emit_insn (gen_vec_addsubv4sf3 (op0, op1, op2));
1153 :
1154 257 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1155 257 : DONE;
1156 : })
1157 :
1158 : (define_expand "vec_fmaddsubv2sf4"
1159 : [(match_operand:V2SF 0 "register_operand")
1160 : (match_operand:V2SF 1 "nonimmediate_operand")
1161 : (match_operand:V2SF 2 "nonimmediate_operand")
1162 : (match_operand:V2SF 3 "nonimmediate_operand")]
1163 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1164 : && TARGET_MMX_WITH_SSE
1165 : && ix86_partial_vec_fp_math"
1166 2 : {
1167 2 : rtx op3 = gen_reg_rtx (V4SFmode);
1168 2 : rtx op2 = gen_reg_rtx (V4SFmode);
1169 2 : rtx op1 = gen_reg_rtx (V4SFmode);
1170 4 : rtx op0 = gen_reg_rtx (V4SFmode);
1171 :
1172 4 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1173 4 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1174 4 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1175 :
1176 2 : emit_insn (gen_vec_fmaddsubv4sf4 (op0, op1, op2, op3));
1177 :
1178 2 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1179 2 : DONE;
1180 : })
1181 :
1182 : (define_expand "vec_fmsubaddv2sf4"
1183 : [(match_operand:V2SF 0 "register_operand")
1184 : (match_operand:V2SF 1 "nonimmediate_operand")
1185 : (match_operand:V2SF 2 "nonimmediate_operand")
1186 : (match_operand:V2SF 3 "nonimmediate_operand")]
1187 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1188 : && TARGET_MMX_WITH_SSE
1189 : && ix86_partial_vec_fp_math"
1190 2 : {
1191 2 : rtx op3 = gen_reg_rtx (V4SFmode);
1192 2 : rtx op2 = gen_reg_rtx (V4SFmode);
1193 381 : rtx op1 = gen_reg_rtx (V4SFmode);
1194 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1195 379 :
1196 381 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1197 381 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1198 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1199 :
1200 2 : emit_insn (gen_vec_fmsubaddv4sf4 (op0, op1, op2, op3));
1201 :
1202 2 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1203 2 : DONE;
1204 : })
1205 :
1206 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1207 : ;;
1208 : ;; Parallel single-precision floating point comparisons
1209 : ;;
1210 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1211 :
1212 : (define_expand "mmx_eqv2sf3"
1213 : [(parallel
1214 : [(set (match_operand:V2SI 0 "register_operand")
1215 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
1216 : (match_operand:V2SF 2 "nonimmediate_operand")))
1217 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
1218 230 : "TARGET_3DNOW"
1219 14 : "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
1220 230 :
1221 0 : (define_insn "*mmx_eqv2sf3"
1222 230 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1223 14 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
1224 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1225 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1226 70 : "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
1227 0 : "pfcmpeq\t{%2, %0|%0, %2}"
1228 14 : [(set_attr "type" "mmxcmp")
1229 : (set_attr "prefix_extra" "1")
1230 : (set_attr "mode" "V2SF")])
1231 :
1232 : (define_insn "mmx_gtv2sf3"
1233 154 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1234 : (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
1235 154 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1236 23435 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1237 224 : "TARGET_3DNOW"
1238 : "pfcmpgt\t{%2, %0|%0, %2}"
1239 : [(set_attr "type" "mmxcmp")
1240 23281 : (set_attr "prefix_extra" "1")
1241 64743 : (set_attr "mode" "V2SF")])
1242 64743 :
1243 64743 : (define_insn "mmx_gev2sf3"
1244 23281 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1245 23281 : (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
1246 23281 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1247 23281 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1248 70 : "TARGET_3DNOW"
1249 20517 : "pfcmpge\t{%2, %0|%0, %2}"
1250 20517 : [(set_attr "type" "mmxcmp")
1251 : (set_attr "prefix_extra" "1")
1252 20456 : (set_attr "mode" "V2SF")])
1253 20456 :
1254 : (define_expand "vec_cmpv2sfv2si"
1255 646345 : [(set (match_operand:V2SI 0 "register_operand")
1256 626687 : (match_operator:V2SI 1 ""
1257 0 : [(match_operand:V2SF 2 "nonimmediate_operand")
1258 11 : (match_operand:V2SF 3 "nonimmediate_operand")]))]
1259 11 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1260 122 : {
1261 122 : rtx ops[4];
1262 122 : ops[3] = gen_reg_rtx (V4SFmode);
1263 122 : ops[2] = gen_reg_rtx (V4SFmode);
1264 122 : ops[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), V4SImode, ops[2], ops[3]);
1265 122 : ops[0] = gen_reg_rtx (V4SImode);
1266 :
1267 122 : emit_insn (gen_movq_v2sf_to_sse (ops[3], operands[3]));
1268 122 : emit_insn (gen_movq_v2sf_to_sse (ops[2], operands[2]));
1269 :
1270 122 : bool ok = ix86_expand_fp_vec_cmp (ops);
1271 122 : gcc_assert (ok);
1272 :
1273 122 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, ops[0], V4SImode));
1274 122 : DONE;
1275 : })
1276 :
1277 : (define_insn "@sse4_1_insertps_<mode>"
1278 : [(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v")
1279 : (unspec:V2FI
1280 : [(match_operand:V2FI 2 "nonimmediate_operand" "Yrjm,*xjm,vm")
1281 : (match_operand:V2FI 1 "register_operand" "0,0,v")
1282 : (match_operand:SI 3 "const_0_to_255_operand")]
1283 : UNSPEC_INSERTPS))]
1284 6722 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1285 525 : {
1286 525 : if (MEM_P (operands[2]))
1287 : {
1288 4 : unsigned count_s = INTVAL (operands[3]) >> 6;
1289 125 : if (count_s)
1290 0 : operands[3] = GEN_INT (INTVAL (operands[3]) & 0x3f);
1291 125 : operands[2] = adjust_address_nv (operands[2],
1292 43108 : <mmxscalarmode>mode, count_s * 4);
1293 43229 : }
1294 43633 : switch (which_alternative)
1295 43108 : {
1296 43108 : case 0:
1297 43108 : case 1:
1298 43108 : return "insertps\t{%3, %2, %0|%0, %2, %3}";
1299 43633 : case 2:
1300 43633 : return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
1301 43108 : default:
1302 0 : gcc_unreachable ();
1303 40058 : }
1304 : }
1305 321 : [(set_attr "isa" "noavx,noavx,avx")
1306 321 : (set_attr "addr" "gpr16,gpr16,*")
1307 : (set_attr "type" "sselog")
1308 594 : (set_attr "prefix_data16" "1,1,*")
1309 : (set_attr "prefix_extra" "1")
1310 : (set_attr "length_immediate" "1")
1311 : (set_attr "prefix" "orig,orig,maybe_evex")
1312 : (set_attr "mode" "V4SF")])
1313 :
1314 : (define_insn "*mmx_blendps"
1315 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1316 : (vec_merge:V2SF
1317 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1318 : (match_operand:V2SF 1 "register_operand" "0,0,x")
1319 : (match_operand:SI 3 "const_0_to_3_operand")))]
1320 1977 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1321 : "@
1322 : blendps\t{%3, %2, %0|%0, %2, %3}
1323 : blendps\t{%3, %2, %0|%0, %2, %3}
1324 3 : vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1325 3 : [(set_attr "isa" "noavx,noavx,avx")
1326 : (set_attr "type" "ssemov")
1327 3 : (set_attr "length_immediate" "1")
1328 : (set_attr "prefix_data16" "1,1,*")
1329 : (set_attr "prefix_extra" "1")
1330 : (set_attr "prefix" "orig,orig,vex")
1331 : (set_attr "mode" "V4SF")])
1332 :
1333 : (define_insn "mmx_blendvps"
1334 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1335 : (unspec:V2SF
1336 : [(match_operand:V2SF 1 "register_operand" "0,0,x")
1337 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1338 : (match_operand:V2SF 3 "register_operand" "Yz,Yz,x")]
1339 : UNSPEC_BLENDV))]
1340 18 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1341 : "@
1342 : blendvps\t{%3, %2, %0|%0, %2, %3}
1343 : blendvps\t{%3, %2, %0|%0, %2, %3}
1344 3807 : vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1345 3807 : [(set_attr "isa" "noavx,noavx,avx")
1346 : (set_attr "type" "ssemov")
1347 3807 : (set_attr "length_immediate" "1")
1348 : (set_attr "prefix_data16" "1,1,*")
1349 : (set_attr "prefix_extra" "1")
1350 : (set_attr "prefix" "orig,orig,vex")
1351 : (set_attr "btver2_decode" "vector")
1352 : (set_attr "mode" "V4SF")])
1353 :
1354 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1355 : ;;
1356 : ;; Parallel single-precision floating point logical operations
1357 : ;;
1358 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1359 :
1360 : (define_insn "*mmx_andnotv2sf3"
1361 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1362 : (and:V2SF
1363 : (not:V2SF
1364 : (match_operand:V2SF 1 "register_operand" "0,x"))
1365 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1366 234 : "TARGET_MMX_WITH_SSE"
1367 : "@
1368 : andnps\t{%2, %0|%0, %2}
1369 : vandnps\t{%2, %1, %0|%0, %1, %2}"
1370 0 : [(set_attr "isa" "noavx,avx")
1371 0 : (set_attr "type" "sselog")
1372 : (set_attr "prefix" "orig,vex")
1373 0 : (set_attr "mode" "V4SF")])
1374 :
1375 : (define_insn "<code>v2sf3"
1376 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1377 : (any_logic:V2SF
1378 : (match_operand:V2SF 1 "register_operand" "%0,x")
1379 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1380 621 : "TARGET_MMX_WITH_SSE"
1381 : "@
1382 : <logic>ps\t{%2, %0|%0, %2}
1383 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
1384 2 : [(set_attr "isa" "noavx,avx")
1385 2 : (set_attr "type" "sselog")
1386 1 : (set_attr "prefix" "orig,vex")
1387 : (set_attr "mode" "V4SF")])
1388 1 :
1389 : (define_expand "copysignv2sf3"
1390 : [(set (match_dup 4)
1391 : (and:V2SF
1392 : (not:V2SF (match_dup 3))
1393 : (match_operand:V2SF 1 "register_operand")))
1394 : (set (match_dup 5)
1395 : (and:V2SF (match_dup 3)
1396 : (match_operand:V2SF 2 "register_operand")))
1397 : (set (match_operand:V2SF 0 "register_operand")
1398 : (ior:V2SF (match_dup 4) (match_dup 5)))]
1399 : "TARGET_MMX_WITH_SSE"
1400 7 : {
1401 7 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1402 :
1403 7 : operands[4] = gen_reg_rtx (V2SFmode);
1404 7 : operands[5] = gen_reg_rtx (V2SFmode);
1405 : })
1406 :
1407 : (define_expand "xorsignv2sf3"
1408 : [(set (match_dup 4)
1409 7 : (and:V2SF (match_dup 3)
1410 : (match_operand:V2SF 2 "register_operand")))
1411 : (set (match_operand:V2SF 0 "register_operand")
1412 : (xor:V2SF (match_dup 4)
1413 : (match_operand:V2SF 1 "register_operand")))]
1414 : "TARGET_MMX_WITH_SSE"
1415 8 : {
1416 1 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1417 :
1418 1 : operands[4] = gen_reg_rtx (V2SFmode);
1419 : })
1420 1 :
1421 : (define_expand "signbitv2sf2"
1422 1 : [(set (match_operand:V2SI 0 "register_operand")
1423 2 : (lshiftrt:V2SI
1424 1 : (subreg:V2SI
1425 : (match_operand:V2SF 1 "register_operand") 0)
1426 : (match_dup 2)))]
1427 : "TARGET_MMX_WITH_SSE"
1428 2 : {
1429 1 : operands[1] = force_reg (V2SFmode, operands[1]);
1430 1 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);
1431 : })
1432 :
1433 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1434 : ;;
1435 2 : ;; Parallel single-precision FMA multiply/accumulate instructions.
1436 1 : ;;
1437 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1438 :
1439 1 : (define_expand "fmav2sf4"
1440 : [(set (match_operand:V2SF 0 "register_operand")
1441 : (fma:V2SF
1442 : (match_operand:V2SF 1 "nonimmediate_operand")
1443 : (match_operand:V2SF 2 "nonimmediate_operand")
1444 73 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1445 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1446 73 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1447 797 : {
1448 797 : rtx op3 = gen_reg_rtx (V4SFmode);
1449 724 : rtx op2 = gen_reg_rtx (V4SFmode);
1450 724 : rtx op1 = gen_reg_rtx (V4SFmode);
1451 724 : rtx op0 = gen_reg_rtx (V4SFmode);
1452 :
1453 724 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1454 724 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1455 724 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1456 :
1457 724 : emit_insn (gen_fmav4sf4 (op0, op1, op2, op3));
1458 :
1459 724 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1460 724 : DONE;
1461 : })
1462 :
1463 : (define_expand "fmsv2sf4"
1464 : [(set (match_operand:V2SF 0 "register_operand")
1465 : (fma:V2SF
1466 : (match_operand:V2SF 1 "nonimmediate_operand")
1467 : (match_operand:V2SF 2 "nonimmediate_operand")
1468 : (neg:V2SF
1469 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1470 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1471 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1472 14 : {
1473 14 : rtx op3 = gen_reg_rtx (V4SFmode);
1474 31 : rtx op2 = gen_reg_rtx (V4SFmode);
1475 14 : rtx op1 = gen_reg_rtx (V4SFmode);
1476 31 : rtx op0 = gen_reg_rtx (V4SFmode);
1477 17 :
1478 31 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1479 14 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1480 14 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1481 :
1482 14 : emit_insn (gen_fmsv4sf4 (op0, op1, op2, op3));
1483 :
1484 14 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1485 14 : DONE;
1486 : })
1487 :
1488 : (define_expand "fnmav2sf4"
1489 : [(set (match_operand:V2SF 0 "register_operand")
1490 : (fma:V2SF
1491 : (neg:V2SF
1492 : (match_operand:V2SF 1 "nonimmediate_operand"))
1493 : (match_operand:V2SF 2 "nonimmediate_operand")
1494 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1495 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1496 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1497 154 : {
1498 154 : rtx op3 = gen_reg_rtx (V4SFmode);
1499 154 : rtx op2 = gen_reg_rtx (V4SFmode);
1500 656 : rtx op1 = gen_reg_rtx (V4SFmode);
1501 154 : rtx op0 = gen_reg_rtx (V4SFmode);
1502 502 :
1503 154 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1504 656 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1505 154 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1506 :
1507 154 : emit_insn (gen_fnmav4sf4 (op0, op1, op2, op3));
1508 :
1509 154 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1510 154 : DONE;
1511 : })
1512 :
1513 : (define_expand "fnmsv2sf4"
1514 : [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1515 : (fma:V2SF
1516 : (neg:V2SF
1517 : (match_operand:V2SF 1 "nonimmediate_operand"))
1518 : (match_operand:V2SF 2 "nonimmediate_operand")
1519 : (neg:V2SF
1520 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1521 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1522 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1523 2 : {
1524 3 : rtx op3 = gen_reg_rtx (V4SFmode);
1525 2 : rtx op2 = gen_reg_rtx (V4SFmode);
1526 3 : rtx op1 = gen_reg_rtx (V4SFmode);
1527 3 : rtx op0 = gen_reg_rtx (V4SFmode);
1528 1 :
1529 2 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1530 2 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1531 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1532 :
1533 2 : emit_insn (gen_fnmsv4sf4 (op0, op1, op2, op3));
1534 :
1535 2 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1536 2 : DONE;
1537 : })
1538 :
1539 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1540 : ;;
1541 : ;; Parallel single-precision floating point conversion operations
1542 : ;;
1543 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1544 :
1545 : (define_expand "fix_truncv2sfv2si2"
1546 : [(set (match_operand:V2SI 0 "register_operand")
1547 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1548 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1549 73 : {
1550 73 : rtx op1 = gen_reg_rtx (V4SFmode);
1551 74 : rtx op0 = gen_reg_rtx (V4SImode);
1552 :
1553 74 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1554 1 :
1555 74 : emit_insn (gen_fix_truncv4sfv4si2 (op0, op1));
1556 :
1557 73 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1558 73 : DONE;
1559 : })
1560 :
1561 : (define_expand "fixuns_truncv2sfv2si2"
1562 : [(set (match_operand:V2SI 0 "register_operand")
1563 : (unsigned_fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1564 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1565 1 : {
1566 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1567 1 : rtx op0 = gen_reg_rtx (V4SImode);
1568 :
1569 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1570 :
1571 1289 : emit_insn (gen_fixuns_truncv4sfv4si2 (op0, op1));
1572 :
1573 1289 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1574 1289 : DONE;
1575 1288 : })
1576 :
1577 : (define_insn "mmx_fix_truncv2sfv2si2"
1578 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1579 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))
1580 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1581 54 : "TARGET_3DNOW"
1582 : "pf2id\t{%1, %0|%0, %1}"
1583 : [(set_attr "type" "mmxcvt")
1584 : (set_attr "prefix_extra" "1")
1585 : (set_attr "mode" "V2SF")])
1586 :
1587 1905 : (define_expand "floatv2siv2sf2"
1588 : [(set (match_operand:V2SF 0 "register_operand")
1589 1905 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1590 1905 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1591 62513297 : {
1592 379 : rtx op1 = gen_reg_rtx (V4SImode);
1593 379 : rtx op0 = gen_reg_rtx (V4SFmode);
1594 :
1595 62511392 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1596 62511013 :
1597 62511392 : emit_insn (gen_floatv4siv4sf2 (op0, op1));
1598 62511013 :
1599 379 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1600 61396225 : DONE;
1601 61395846 : })
1602 61395846 :
1603 61395846 : (define_expand "floatunsv2siv2sf2"
1604 : [(set (match_operand:V2SF 0 "register_operand")
1605 61387792 : (unsigned_float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1606 61387792 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1607 61387793 : {
1608 1 : rtx op1 = gen_reg_rtx (V4SImode);
1609 61387793 : rtx op0 = gen_reg_rtx (V4SFmode);
1610 :
1611 38335460 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1612 38335459 :
1613 2 : emit_insn (gen_floatunsv4siv4sf2 (op0, op1));
1614 38332355 :
1615 38332357 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1616 38332357 : DONE;
1617 38332356 : })
1618 10007 :
1619 38322348 : (define_insn "mmx_floatv2siv2sf2"
1620 76269434 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1621 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))
1622 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1623 66 : "TARGET_3DNOW"
1624 : "pi2fd\t{%1, %0|%0, %1}"
1625 : [(set_attr "type" "mmxcvt")
1626 : (set_attr "prefix_extra" "1")
1627 : (set_attr "mode" "V2SF")])
1628 :
1629 1 : (define_insn "mmx_pf2iw"
1630 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1631 1 : (sign_extend:V2SI
1632 1 : (ss_truncate:V2HI
1633 92 : (fix:V2SI
1634 : (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
1635 70 : "TARGET_3DNOW_A"
1636 : "pf2iw\t{%1, %0|%0, %1}"
1637 91 : [(set_attr "type" "mmxcvt")
1638 91 : (set_attr "prefix_extra" "1")
1639 33010 : (set_attr "mode" "V2SF")])
1640 33010 :
1641 32919 : (define_insn "mmx_pi2fw"
1642 90 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1643 33009 : (float:V2SF
1644 32919 : (sign_extend:V2SI
1645 32969 : (truncate:V2HI
1646 50 : (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
1647 11049 : "TARGET_3DNOW_A"
1648 10983 : "pi2fw\t{%1, %0|%0, %1}"
1649 11755 : [(set_attr "type" "mmxcvt")
1650 50 : (set_attr "prefix_extra" "1")
1651 50 : (set_attr "mode" "V2SF")])
1652 :
1653 28 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1654 : ;;
1655 0 : ;; Parallel single-precision floating point element swizzling
1656 0 : ;;
1657 226479 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1658 :
1659 : (define_insn "mmx_pswapdv2sf2"
1660 : [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv")
1661 226479 : (vec_select:V2SF
1662 226479 : (match_operand:V2SF 1 "register_mmxmem_operand" "ym,0,Yv")
1663 226479 : (parallel [(const_int 1) (const_int 0)])))]
1664 233005 : "TARGET_3DNOW_A || TARGET_MMX_WITH_SSE"
1665 226479 : "@
1666 226479 : pswapd\t{%1, %0|%0, %1}
1667 : shufps\t{$0xe1, %1, %0|%0, %1, 0xe1}
1668 154306 : vshufps\t{$0xe1, %1, %1, %0|%0, %1, %1, 0xe1}"
1669 154306 : [(set_attr "isa" "*,sse_noavx,avx")
1670 154306 : (set_attr "mmx_isa" "native,*,*")
1671 149863 : (set_attr "type" "mmxcvt,ssemov,ssemov")
1672 149863 : (set_attr "prefix_extra" "1,*,*")
1673 149863 : (set_attr "mode" "V2SF,V4SF,V4SF")])
1674 :
1675 149862 : (define_insn "*mmx_movshdup"
1676 149862 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1677 149862 : (vec_select:V2SF
1678 149862 : (match_operand:V2SF 1 "register_operand" "v,0")
1679 149862 : (parallel [(const_int 1) (const_int 1)])))]
1680 4263 : "TARGET_MMX_WITH_SSE"
1681 3416 : "@
1682 3416 : %vmovshdup\t{%1, %0|%0, %1}
1683 3416 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}"
1684 3416 : [(set_attr "isa" "sse3,*")
1685 3416 : (set_attr "type" "sse,sseshuf1")
1686 6832 : (set_attr "length_immediate" "*,1")
1687 : (set_attr "prefix_rep" "1,*")
1688 : (set_attr "prefix" "maybe_vex,orig")
1689 : (set_attr "mode" "V4SF")])
1690 4993 :
1691 4993 : (define_insn "*mmx_movsldup"
1692 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1693 4556 : (vec_select:V2SF
1694 4556 : (match_operand:V2SF 1 "register_operand" "v,0")
1695 4525 : (parallel [(const_int 0) (const_int 0)])))]
1696 8892 : "TARGET_MMX_WITH_SSE"
1697 : "@
1698 : %vmovsldup\t{%1, %0|%0, %1}
1699 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1700 429 : [(set_attr "isa" "sse3,*")
1701 429 : (set_attr "type" "sse,sseshuf1")
1702 429 : (set_attr "length_immediate" "*,1")
1703 855 : (set_attr "prefix_rep" "1,*")
1704 : (set_attr "prefix" "maybe_vex,orig")
1705 : (set_attr "mode" "V4SF")])
1706 :
1707 : (define_insn_and_split "*vec_interleave_lowv2sf"
1708 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1709 : (vec_select:V2SF
1710 : (vec_concat:V4SF
1711 : (match_operand:V2SF 1 "register_operand" "0,v")
1712 : (match_operand:V2SF 2 "register_operand" "x,v"))
1713 : (parallel [(const_int 0) (const_int 2)])))]
1714 5610 : "TARGET_MMX_WITH_SSE"
1715 : "#"
1716 460 : "&& reload_completed"
1717 230 : [(const_int 0)]
1718 12426 : "ix86_split_mmx_punpck (operands, false); DONE;"
1719 12196 : [(set_attr "isa" "noavx,avx")
1720 644 : (set_attr "type" "sselog")
1721 644 : (set_attr "prefix" "orig,maybe_evex")
1722 : (set_attr "mode" "V4SF")])
1723 :
1724 : (define_insn_and_split "*vec_interleave_highv2sf"
1725 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1726 : (vec_select:V2SF
1727 : (vec_concat:V4SF
1728 : (match_operand:V2SF 1 "register_operand" "0,v")
1729 : (match_operand:V2SF 2 "register_operand" "x,v"))
1730 40 : (parallel [(const_int 1) (const_int 3)])))]
1731 2402 : "TARGET_MMX_WITH_SSE"
1732 40 : "#"
1733 242 : "&& reload_completed"
1734 161 : [(const_int 0)]
1735 6658 : "ix86_split_mmx_punpck (operands, true); DONE;"
1736 6537 : [(set_attr "isa" "noavx,avx")
1737 532 : (set_attr "type" "sselog")
1738 532 : (set_attr "prefix" "orig,vex")
1739 : (set_attr "mode" "V4SF")])
1740 :
1741 : (define_insn "*vec_dupv2sf"
1742 : [(set (match_operand:V2SF 0 "register_operand" "=y,Yv,x")
1743 : (vec_duplicate:V2SF
1744 : (match_operand:SF 1 "register_operand" "0,Yv,0")))]
1745 5194 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1746 419 : "@
1747 : punpckldq\t%0, %0
1748 1 : %vmovsldup\t{%1, %0|%0, %1}
1749 38 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1750 38 : [(set_attr "isa" "*,sse3,sse_noavx")
1751 32 : (set_attr "mmx_isa" "native,*,*")
1752 32 : (set_attr "type" "mmxcvt,sse,sseshuf1")
1753 69 : (set_attr "length_immediate" "*,*,1")
1754 : (set_attr "prefix_rep" "*,1,*")
1755 : (set_attr "prefix" "*,maybe_vex,orig")
1756 : (set_attr "mode" "DI,V4SF,V4SF")])
1757 :
1758 : (define_insn "*mmx_movss_<mode>"
1759 : [(set (match_operand:V2FI 0 "register_operand" "=x,v")
1760 : (vec_merge:V2FI
1761 : (match_operand:V2FI 2 "register_operand" " x,v")
1762 : (match_operand:V2FI 1 "register_operand" " 0,v")
1763 : (const_int 1)))]
1764 4265 : "TARGET_MMX_WITH_SSE"
1765 : "@
1766 : movss\t{%2, %0|%0, %2}
1767 : vmovss\t{%2, %1, %0|%0, %1, %2}"
1768 3220 : [(set_attr "isa" "noavx,avx")
1769 3220 : (set_attr "type" "ssemov")
1770 : (set_attr "prefix" "orig,maybe_evex")
1771 3220 : (set_attr "mode" "SF")])
1772 390434 :
1773 390434 : (define_insn "*mmx_concatv2sf"
1774 390434 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
1775 390434 : (vec_concat:V2SF
1776 390434 : (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
1777 390434 : (match_operand:SF 2 "nonimm_or_0_operand" "ym,C")))]
1778 473443 : "TARGET_MMX && !TARGET_SSE"
1779 390434 : "@
1780 83009 : punpckldq\t{%2, %0|%0, %2}
1781 379302 : movd\t{%1, %0|%0, %1}"
1782 : [(set_attr "type" "mmxcvt,mmxmov")
1783 272 : (set_attr "mode" "DI")])
1784 272 :
1785 : (define_expand "vec_setv2sf"
1786 : [(match_operand:V2SF 0 "register_operand")
1787 272 : (match_operand:SF 1 "register_operand")
1788 : (match_operand 2 "vec_setm_mmx_operand")]
1789 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1790 17 : {
1791 17 : if (CONST_INT_P (operands[2]))
1792 15 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
1793 15 : INTVAL (operands[2]));
1794 : else
1795 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
1796 17 : DONE;
1797 : })
1798 :
1799 : ;; Avoid combining registers from different units in a single alternative,
1800 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1801 : (define_insn_and_split "*vec_extractv2sf_0"
1802 : [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
1803 : (vec_select:SF
1804 : (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
1805 : (parallel [(const_int 0)])))]
1806 1560 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1807 11114 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1808 : "#"
1809 1510 : "&& reload_completed"
1810 502 : [(set (match_dup 0) (match_dup 1))]
1811 85086 : "operands[1] = gen_lowpart (SFmode, operands[1]);"
1812 84584 : [(set_attr "mmx_isa" "*,*,native,native,*,*")])
1813 14419 :
1814 14920 : ;; Avoid combining registers from different units in a single alternative,
1815 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1816 : (define_insn "*vec_extractv2sf_1"
1817 502 : [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,x,y,x,f,r")
1818 : (vec_select:SF
1819 : (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,0,o,o,o,o")
1820 : (parallel [(const_int 1)])))]
1821 5103 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1822 5105 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1823 : "@
1824 2 : punpckhdq\t%0, %0
1825 2 : %vmovshdup\t{%1, %0|%0, %1}
1826 13805 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
1827 13803 : #
1828 13630 : #
1829 27433 : #
1830 : #"
1831 13449 : [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
1832 : (set_attr "mmx_isa" "native,*,*,native,*,*,*")
1833 : (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
1834 : (set (attr "length_immediate")
1835 : (if_then_else (eq_attr "alternative" "2")
1836 : (const_string "1")
1837 : (const_string "*")))
1838 : (set (attr "prefix_rep")
1839 : (if_then_else (eq_attr "alternative" "1")
1840 : (const_string "1")
1841 : (const_string "*")))
1842 : (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
1843 : (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
1844 :
1845 : (define_split
1846 : [(set (match_operand:SF 0 "register_operand")
1847 : (vec_select:SF
1848 : (match_operand:V2SF 1 "memory_operand")
1849 : (parallel [(const_int 1)])))]
1850 46 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
1851 40 : [(set (match_dup 0) (match_dup 1))]
1852 40 : "operands[1] = adjust_address (operands[1], SFmode, 4);")
1853 :
1854 5459 : (define_expand "vec_extractv2sfsf"
1855 5499 : [(match_operand:SF 0 "register_operand")
1856 4143 : (match_operand:V2SF 1 "register_operand")
1857 4143 : (match_operand 2 "const_int_operand")]
1858 5499 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1859 1288 : {
1860 1288 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
1861 1288 : operands[1], INTVAL (operands[2]));
1862 1288 : DONE;
1863 1 : })
1864 :
1865 1 : (define_expand "vec_initv2sfsf"
1866 1 : [(match_operand:V2SF 0 "register_operand")
1867 1 : (match_operand 1)]
1868 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
1869 1905 : {
1870 1905 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
1871 : operands[1]);
1872 1905 : DONE;
1873 : })
1874 :
1875 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1876 : ;;
1877 1 : ;; Parallel single-precision floating point rounding operations.
1878 1 : ;;
1879 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1880 :
1881 : (define_expand "nearbyintv2sf2"
1882 : [(match_operand:V2SF 0 "register_operand")
1883 : (match_operand:V2SF 1 "nonimmediate_operand")]
1884 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1885 2 : {
1886 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1887 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1888 1 :
1889 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1890 :
1891 1 : emit_insn (gen_nearbyintv4sf2 (op0, op1));
1892 :
1893 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1894 1 : DONE;
1895 : })
1896 :
1897 : (define_expand "rintv2sf2"
1898 : [(match_operand:V2SF 0 "register_operand")
1899 : (match_operand:V2SF 1 "nonimmediate_operand")]
1900 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1901 1 : {
1902 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1903 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1904 :
1905 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1906 :
1907 100 : emit_insn (gen_rintv4sf2 (op0, op1));
1908 :
1909 100 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1910 100 : DONE;
1911 99 : })
1912 :
1913 : (define_expand "lrintv2sfv2si2"
1914 : [(match_operand:V2SI 0 "register_operand")
1915 : (match_operand:V2SF 1 "nonimmediate_operand")]
1916 : "TARGET_SSE4_1 && !flag_trapping_math
1917 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1918 1 : {
1919 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1920 1 : rtx op0 = gen_reg_rtx (V4SImode);
1921 :
1922 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1923 8 :
1924 1 : emit_insn (gen_lrintv4sfv4si2 (op0, op1));
1925 8 :
1926 9 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1927 9 : DONE;
1928 : })
1929 :
1930 : (define_expand "ceilv2sf2"
1931 : [(match_operand:V2SF 0 "register_operand")
1932 : (match_operand:V2SF 1 "nonimmediate_operand")]
1933 : "TARGET_SSE4_1 && !flag_trapping_math
1934 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1935 1 : {
1936 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1937 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1938 :
1939 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1940 0 :
1941 1 : emit_insn (gen_ceilv4sf2 (op0, op1));
1942 0 :
1943 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1944 1 : DONE;
1945 : })
1946 :
1947 : (define_expand "lceilv2sfv2si2"
1948 : [(match_operand:V2SI 0 "register_operand")
1949 : (match_operand:V2SF 1 "nonimmediate_operand")]
1950 : "TARGET_SSE4_1 && !flag_trapping_math
1951 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1952 1 : {
1953 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1954 1 : rtx op0 = gen_reg_rtx (V4SImode);
1955 :
1956 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1957 4 :
1958 1 : emit_insn (gen_lceilv4sfv4si2 (op0, op1));
1959 4 :
1960 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1961 5 : DONE;
1962 : })
1963 :
1964 : (define_expand "floorv2sf2"
1965 : [(match_operand:V2SF 0 "register_operand")
1966 : (match_operand:V2SF 1 "nonimmediate_operand")]
1967 : "TARGET_SSE4_1 && !flag_trapping_math
1968 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1969 2 : {
1970 2 : rtx op1 = gen_reg_rtx (V4SFmode);
1971 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1972 :
1973 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1974 5 :
1975 2 : emit_insn (gen_floorv4sf2 (op0, op1));
1976 5 :
1977 7 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1978 2 : DONE;
1979 : })
1980 :
1981 5 : (define_expand "lfloorv2sfv2si2"
1982 : [(match_operand:V2SI 0 "register_operand")
1983 : (match_operand:V2SF 1 "nonimmediate_operand")]
1984 : "TARGET_SSE4_1 && !flag_trapping_math
1985 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1986 6 : {
1987 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1988 6 : rtx op0 = gen_reg_rtx (V4SImode);
1989 5 :
1990 6 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1991 0 :
1992 1 : emit_insn (gen_lfloorv4sfv4si2 (op0, op1));
1993 0 :
1994 1 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1995 1 : DONE;
1996 : })
1997 :
1998 0 : (define_expand "btruncv2sf2"
1999 : [(match_operand:V2SF 0 "register_operand")
2000 : (match_operand:V2SF 1 "nonimmediate_operand")]
2001 : "TARGET_SSE4_1 && !flag_trapping_math
2002 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2003 5 : {
2004 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2005 5 : rtx op0 = gen_reg_rtx (V4SFmode);
2006 4 :
2007 5 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2008 0 :
2009 1 : emit_insn (gen_btruncv4sf2 (op0, op1));
2010 0 :
2011 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2012 1 : DONE;
2013 : })
2014 :
2015 0 : (define_expand "roundv2sf2"
2016 : [(match_operand:V2SF 0 "register_operand")
2017 : (match_operand:V2SF 1 "nonimmediate_operand")]
2018 : "TARGET_SSE4_1 && !flag_trapping_math
2019 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2020 2 : {
2021 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2022 2 : rtx op0 = gen_reg_rtx (V4SFmode);
2023 1 :
2024 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2025 6 :
2026 1 : emit_insn (gen_roundv4sf2 (op0, op1));
2027 6 :
2028 7 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2029 7 : DONE;
2030 : })
2031 :
2032 : (define_expand "lroundv2sfv2si2"
2033 : [(match_operand:V2SI 0 "register_operand")
2034 : (match_operand:V2SF 1 "nonimmediate_operand")]
2035 : "TARGET_SSE4_1 && !flag_trapping_math
2036 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2037 1 : {
2038 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2039 1 : rtx op0 = gen_reg_rtx (V4SImode);
2040 :
2041 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2042 4 :
2043 1 : emit_insn (gen_lroundv4sfv4si2 (op0, op1));
2044 4 :
2045 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
2046 5 : DONE;
2047 : })
2048 :
2049 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2050 : ;;
2051 : ;; Parallel half-precision floating point arithmetic
2052 : ;;
2053 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2054 :
2055 : (define_mode_iterator VHF_32_64 [V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2056 :
2057 : (define_mode_iterator VBF_32_64 [V2BF (V4BF "TARGET_MMX_WITH_SSE")])
2058 :
2059 4 : (define_expand "divv4hf3"
2060 : [(set (match_operand:V4HF 0 "register_operand")
2061 4 : (div:V4HF
2062 4 : (match_operand:V4HF 1 "nonimmediate_operand")
2063 4 : (match_operand:V4HF 2 "register_operand")))]
2064 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math
2065 : && TARGET_MMX_WITH_SSE"
2066 8 : {
2067 8 : rtx op2 = gen_reg_rtx (V8HFmode);
2068 8 : rtx op1 = gen_reg_rtx (V8HFmode);
2069 8 : rtx op0 = gen_reg_rtx (V8HFmode);
2070 :
2071 8 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2072 8 : rtx tmp = gen_rtx_VEC_CONCAT (V8HFmode, operands[2],
2073 : force_reg (V4HFmode, CONST1_RTX (V4HFmode)));
2074 8 : emit_insn (gen_rtx_SET (op2, tmp));
2075 8 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2076 8 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2077 8 : DONE;
2078 : })
2079 :
2080 : (define_mode_attr mov_to_sse_suffix
2081 : [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")])
2082 :
2083 : (define_mode_attr mmxxmmmode
2084 : [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")
2085 : (V4HF "V8HF") (V4HI "V8HI") (V4BF "V8BF")])
2086 :
2087 : (define_mode_attr mmxxmmmodelower
2088 : [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")
2089 : (V4HF "v8hf") (V4HI "v8hi") (V4BF "v8bf")])
2090 :
2091 2 : (define_expand "movd_<mode>_to_sse"
2092 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2093 2 : (vec_merge:<mmxxmmmode>
2094 2 : (vec_duplicate:<mmxxmmmode>
2095 2 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2096 : (match_dup 2)
2097 : (const_int 3)))]
2098 : "TARGET_SSE"
2099 103 : {
2100 103 : if (!flag_trapping_math)
2101 : {
2102 13 : rtx op1 = force_reg (<MODE>mode, operands[1]);
2103 13 : emit_move_insn (operands[0],
2104 : lowpart_subreg (<mmxxmmmode>mode, op1, <MODE>mode));
2105 13 : DONE;
2106 : }
2107 90 : operands[2] = CONST0_RTX (<mmxxmmmode>mode);
2108 : })
2109 :
2110 : (define_expand "movd_<mode>_to_sse_reg"
2111 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2112 90 : (vec_merge:<mmxxmmmode>
2113 : (vec_duplicate:<mmxxmmmode>
2114 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2115 : (match_operand:<mmxxmmmode> 2 "register_operand")
2116 90 : (const_int 3)))]
2117 : "TARGET_SSE")
2118 :
2119 : (define_expand "<insn><mode>3"
2120 : [(set (match_operand:VHF_32_64 0 "register_operand")
2121 8 : (plusminusmult:VHF_32_64
2122 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2123 8 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2124 8 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2125 31 : {
2126 29 : rtx op2 = gen_reg_rtx (V8HFmode);
2127 29 : rtx op1 = gen_reg_rtx (V8HFmode);
2128 29 : rtx op0 = gen_reg_rtx (V8HFmode);
2129 :
2130 29 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2131 29 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2132 29 : emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
2133 :
2134 29 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2135 29 : DONE;
2136 : })
2137 :
2138 : ;; VDIVNEPBF16 does not generate floating point exceptions.
2139 : (define_expand "<insn><mode>3"
2140 : [(set (match_operand:VBF_32_64 0 "register_operand")
2141 : (plusminusmultdiv:VBF_32_64
2142 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2143 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2144 : "TARGET_AVX10_2"
2145 10 : {
2146 15 : rtx op0 = gen_reg_rtx (V8BFmode);
2147 10 : rtx op1 = lowpart_subreg (V8BFmode,
2148 26 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2149 16 : rtx op2 = lowpart_subreg (V8BFmode,
2150 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2151 11 :
2152 21 : emit_insn (gen_<insn>v8bf3 (op0, op1, op2));
2153 11 :
2154 10 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2155 10 : DONE;
2156 : })
2157 :
2158 : (define_expand "divv2hf3"
2159 : [(set (match_operand:V2HF 0 "register_operand")
2160 : (div:V2HF
2161 : (match_operand:V2HF 1 "nonimmediate_operand")
2162 : (match_operand:V2HF 2 "nonimmediate_operand")))]
2163 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2164 5 : {
2165 5 : rtx op2 = gen_reg_rtx (V8HFmode);
2166 5 : rtx op1 = gen_reg_rtx (V8HFmode);
2167 5 : rtx op0 = gen_reg_rtx (V8HFmode);
2168 :
2169 13 : emit_insn (gen_movd_v2hf_to_sse_reg (op2, operands[2],
2170 : force_reg (V8HFmode, CONST1_RTX (V8HFmode))));
2171 13 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
2172 13 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2173 8 :
2174 5 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
2175 5 : DONE;
2176 : })
2177 :
2178 : (define_expand "<code><mode>3"
2179 : [(set (match_operand:VHF_32_64 0 "register_operand")
2180 : (smaxmin:VHF_32_64
2181 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2182 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2183 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2184 4 : {
2185 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2186 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2187 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2188 :
2189 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2190 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2191 0 :
2192 4 : emit_insn (gen_<code>v8hf3 (op0, op1, op2));
2193 0 :
2194 4 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2195 4 : DONE;
2196 : })
2197 :
2198 : (define_expand "<code><mode>3"
2199 : [(set (match_operand:VBF_32_64 0 "register_operand")
2200 : (smaxmin:VBF_32_64
2201 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2202 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2203 : "TARGET_AVX10_2"
2204 4 : {
2205 4 : rtx op0 = gen_reg_rtx (V8BFmode);
2206 4 : rtx op1 = lowpart_subreg (V8BFmode,
2207 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2208 4 : rtx op2 = lowpart_subreg (V8BFmode,
2209 3 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2210 :
2211 7 : emit_insn (gen_<code>v8bf3 (op0, op1, op2));
2212 3 :
2213 7 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2214 4 : DONE;
2215 : })
2216 :
2217 : (define_expand "sqrt<mode>2"
2218 : [(set (match_operand:VHF_32_64 0 "register_operand")
2219 : (sqrt:VHF_32_64
2220 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
2221 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2222 2 : {
2223 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2224 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2225 :
2226 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2227 2 : emit_insn (gen_sqrtv8hf2 (op0, op1));
2228 6 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2229 3 : DONE;
2230 4 : })
2231 5 :
2232 4 : (define_expand "sqrt<mode>2"
2233 1 : [(set (match_operand:VBF_32_64 0 "register_operand")
2234 : (sqrt:VBF_32_64 (match_operand:VBF_32_64 1 "vector_operand")))]
2235 : "TARGET_AVX10_2"
2236 0 : {
2237 0 : rtx op0 = gen_reg_rtx (V8BFmode);
2238 0 : rtx op1 = lowpart_subreg (V8BFmode,
2239 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2240 :
2241 0 : emit_insn (gen_sqrtv8bf2 (op0, op1));
2242 1 :
2243 1 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2244 1 : DONE;
2245 2 : })
2246 1 :
2247 1 : (define_mode_iterator VHBF_32_64
2248 16 : [V2BF (V4BF "TARGET_MMX_WITH_SSE")
2249 46 : V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2250 :
2251 : (define_expand "<code><mode>2"
2252 66 : [(set (match_operand:VHBF_32_64 0 "register_operand")
2253 3850 : (absneg:VHBF_32_64
2254 1890 : (match_operand:VHBF_32_64 1 "register_operand")))]
2255 2494 : "TARGET_SSE"
2256 590 : "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
2257 4037 :
2258 2 : (define_insn_and_split "*mmx_<code><mode>"
2259 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2260 2 : (absneg:VHBF_32_64
2261 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x")))
2262 2 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2263 34 : "TARGET_SSE"
2264 : "#"
2265 4 : "&& reload_completed"
2266 : [(set (match_dup 0)
2267 20 : (<absneg_op>:<MODE> (match_dup 1) (match_dup 2)))]
2268 32 : {
2269 27 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
2270 32 : std::swap (operands[1], operands[2]);
2271 7 : }
2272 2 : [(set_attr "isa" "noavx,noavx,avx")])
2273 5 :
2274 9 : (define_insn_and_split "*mmx_nabs<mode>2"
2275 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2276 : (neg:VHBF_32_64
2277 : (abs:VHBF_32_64
2278 9 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x"))))
2279 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2280 0 : "TARGET_SSE"
2281 : "#"
2282 0 : "&& reload_completed"
2283 70 : [(set (match_dup 0)
2284 0 : (ior:<MODE> (match_dup 1) (match_dup 2)))])
2285 70 :
2286 70 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2287 70 : ;;
2288 0 : ;; Parallel half-precision floating point comparisons
2289 0 : ;;
2290 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2291 :
2292 : (define_expand "vec_cmpv4hfqi"
2293 0 : [(set (match_operand:QI 0 "register_operand")
2294 : (match_operator:QI 1 ""
2295 : [(match_operand:V4HF 2 "nonimmediate_operand")
2296 : (match_operand:V4HF 3 "nonimmediate_operand")]))]
2297 : "TARGET_MMX_WITH_SSE && TARGET_AVX512FP16 && TARGET_AVX512VL
2298 22 : && ix86_partial_vec_fp_math"
2299 17 : {
2300 39 : rtx ops[4];
2301 39 : ops[3] = gen_reg_rtx (V8HFmode);
2302 39 : ops[2] = gen_reg_rtx (V8HFmode);
2303 :
2304 17 : emit_insn (gen_movq_v4hf_to_sse (ops[3], operands[3]));
2305 17 : emit_insn (gen_movq_v4hf_to_sse (ops[2], operands[2]));
2306 17 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2307 17 : DONE;
2308 : })
2309 :
2310 : (define_expand "vcond_mask_<mode>v4hi"
2311 : [(set (match_operand:V4F_64 0 "register_operand")
2312 : (vec_merge:V4F_64
2313 : (match_operand:V4F_64 1 "register_operand")
2314 : (match_operand:V4F_64 2 "register_operand")
2315 : (match_operand:V4HI 3 "register_operand")))]
2316 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
2317 18 : {
2318 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2319 : operands[1], operands[2]);
2320 18 : DONE;
2321 5 : })
2322 :
2323 5 : (define_expand "vcond_mask_<mode>qi"
2324 5 : [(set (match_operand:V4FI_64 0 "register_operand")
2325 5 : (vec_merge:V4FI_64
2326 : (match_operand:V4FI_64 1 "register_operand")
2327 : (match_operand:V4FI_64 2 "register_operand")
2328 : (match_operand:QI 3 "register_operand")))]
2329 : "TARGET_MMX_WITH_SSE && TARGET_AVX512BW && TARGET_AVX512VL"
2330 22 : {
2331 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2332 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2333 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2334 44 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2335 : operands[2], operands[3]));
2336 44 : emit_move_insn (operands[0],
2337 22 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2338 44 : DONE;
2339 : })
2340 :
2341 : (define_expand "vec_cmpv2hfqi"
2342 : [(set (match_operand:QI 0 "register_operand")
2343 : (match_operator:QI 1 ""
2344 : [(match_operand:V2HF 2 "nonimmediate_operand")
2345 : (match_operand:V2HF 3 "nonimmediate_operand")]))]
2346 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2347 : && ix86_partial_vec_fp_math"
2348 17 : {
2349 17 : rtx ops[4];
2350 17 : ops[3] = gen_reg_rtx (V8HFmode);
2351 17 : ops[2] = gen_reg_rtx (V8HFmode);
2352 3 :
2353 17 : emit_insn (gen_movd_v2hf_to_sse (ops[3], operands[3]));
2354 20 : emit_insn (gen_movd_v2hf_to_sse (ops[2], operands[2]));
2355 20 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2356 20 : DONE;
2357 : })
2358 :
2359 : (define_expand "vcond_mask_<mode>v2hi"
2360 : [(set (match_operand:V2F_32 0 "register_operand")
2361 : (vec_merge:V2F_32
2362 : (match_operand:V2F_32 1 "register_operand")
2363 : (match_operand:V2F_32 2 "register_operand")
2364 : (match_operand:V2HI 3 "register_operand")))]
2365 : "TARGET_SSE4_1"
2366 18 : {
2367 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2368 : operands[1], operands[2]);
2369 18 : DONE;
2370 1 : })
2371 :
2372 1 : (define_expand "vcond_mask_<mode>qi"
2373 1 : [(set (match_operand:V2FI_32 0 "register_operand")
2374 1 : (vec_merge:V2FI_32
2375 : (match_operand:V2FI_32 1 "register_operand")
2376 : (match_operand:V2FI_32 2 "register_operand")
2377 : (match_operand:QI 3 "register_operand")))]
2378 : "TARGET_AVX512BW && TARGET_AVX512VL"
2379 22 : {
2380 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2381 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2382 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2383 28 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2384 : operands[2], operands[3]));
2385 28 : emit_move_insn (operands[0],
2386 6 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2387 28 : DONE;
2388 : })
2389 :
2390 : ;;This instruction does not generate floating point exceptions
2391 : (define_expand "vec_cmp<mode>qi"
2392 : [(set (match_operand:QI 0 "register_operand")
2393 : (match_operator:QI 1 ""
2394 : [(match_operand:VBF_32_64 2 "register_operand")
2395 : (match_operand:VBF_32_64 3 "nonimmediate_operand")]))]
2396 : "TARGET_AVX10_2"
2397 10 : {
2398 10 : rtx op2 = lowpart_subreg (V8BFmode,
2399 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2400 10 : rtx op3 = lowpart_subreg (V8BFmode,
2401 2 : force_reg (<MODE>mode, operands[3]), <MODE>mode);
2402 :
2403 12 : emit_insn (gen_vec_cmpv8bfqi (operands[0], operands[1], op2, op3));
2404 12 : DONE;
2405 2 : })
2406 :
2407 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2408 : ;;
2409 : ;; Parallel half-precision floating point rounding operations.
2410 : ;;
2411 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2412 :
2413 : (define_expand "btrunc<mode>2"
2414 : [(match_operand:VHF_32_64 0 "register_operand")
2415 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2416 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2417 : && ix86_partial_vec_fp_math
2418 1 : && !flag_trapping_math"
2419 2 : {
2420 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2421 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2422 1 :
2423 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2424 2 : emit_insn (gen_btruncv8hf2 (op0, op1));
2425 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2426 :
2427 2 : DONE;
2428 : })
2429 :
2430 : (define_expand "nearbyint<mode>2"
2431 : [(match_operand:VHF_32_64 0 "register_operand")
2432 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2433 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2434 : && ix86_partial_vec_fp_math"
2435 2 : {
2436 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2437 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2438 :
2439 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2440 3 : emit_insn (gen_nearbyintv8hf2 (op0, op1));
2441 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2442 1 :
2443 3 : DONE;
2444 1 : })
2445 :
2446 : (define_expand "rint<mode>2"
2447 : [(match_operand:VHF_32_64 0 "register_operand")
2448 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2449 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2450 : && ix86_partial_vec_fp_math"
2451 2 : {
2452 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2453 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2454 :
2455 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2456 3 : emit_insn (gen_rintv8hf2 (op0, op1));
2457 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2458 1 :
2459 3 : DONE;
2460 1 : })
2461 :
2462 : (define_expand "lrint<mode><mmxintvecmodelower>2"
2463 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2464 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2465 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2466 : && ix86_partial_vec_fp_math"
2467 0 : {
2468 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2469 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2470 :
2471 0 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2472 0 : emit_insn (gen_lrintv8hfv8hi2 (op0, op1));
2473 0 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2474 0 :
2475 0 : DONE;
2476 0 : })
2477 :
2478 : (define_expand "floor<mode>2"
2479 : [(match_operand:VHF_32_64 0 "register_operand")
2480 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2481 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2482 : && ix86_partial_vec_fp_math
2483 : && !flag_trapping_math"
2484 2 : {
2485 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2486 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2487 :
2488 3 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2489 2 : emit_insn (gen_floorv8hf2 (op0, op1));
2490 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2491 1 :
2492 3 : DONE;
2493 : })
2494 :
2495 : (define_expand "lfloor<mode><mmxintvecmodelower>2"
2496 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2497 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2498 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2499 : && ix86_partial_vec_fp_math
2500 : && !flag_trapping_math"
2501 0 : {
2502 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2503 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2504 :
2505 1 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2506 0 : emit_insn (gen_lfloorv8hfv8hi2 (op0, op1));
2507 1 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2508 1 :
2509 1 : DONE;
2510 : })
2511 :
2512 : (define_expand "ceil<mode>2"
2513 : [(match_operand:VHF_32_64 0 "register_operand")
2514 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2515 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2516 : && ix86_partial_vec_fp_math
2517 : && !flag_trapping_math"
2518 2 : {
2519 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2520 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2521 :
2522 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2523 2 : emit_insn (gen_ceilv8hf2 (op0, op1));
2524 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2525 0 :
2526 2 : DONE;
2527 : })
2528 :
2529 : (define_expand "lceil<mode><mmxintvecmodelower>2"
2530 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2531 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2532 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2533 : && ix86_partial_vec_fp_math
2534 : && !flag_trapping_math"
2535 0 : {
2536 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2537 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2538 :
2539 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2540 0 : emit_insn (gen_lceilv8hfv8hi2 (op0, op1));
2541 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2542 2 :
2543 2 : DONE;
2544 : })
2545 :
2546 : (define_expand "round<mode>2"
2547 : [(match_operand:VHF_32_64 0 "register_operand")
2548 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2549 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2550 : && ix86_partial_vec_fp_math
2551 : && !flag_trapping_math"
2552 2 : {
2553 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2554 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2555 :
2556 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2557 2 : emit_insn (gen_roundv8hf2 (op0, op1));
2558 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2559 0 :
2560 2 : DONE;
2561 : })
2562 :
2563 : (define_expand "lround<mode><mmxintvecmodelower>2"
2564 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2565 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2566 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2567 : && ix86_partial_vec_fp_math
2568 : && !flag_trapping_math"
2569 0 : {
2570 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2571 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2572 :
2573 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2574 0 : emit_insn (gen_lroundv8hfv8hi2 (op0, op1));
2575 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2576 2 :
2577 2 : DONE;
2578 : })
2579 :
2580 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2581 : ;;
2582 : ;; Parallel half-precision floating point logical operations
2583 : ;;
2584 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2585 :
2586 : (define_insn "*mmx_andnot<mode>3"
2587 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2588 : (and:VHBF_32_64
2589 : (not:VHBF_32_64
2590 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x"))
2591 : (match_operand:VHBF_32_64 2 "register_operand" "x,x")))]
2592 2 : "TARGET_SSE"
2593 0 : "@
2594 0 : andnps\t{%2, %0|%0, %2}
2595 : vandnps\t{%2, %1, %0|%0, %1, %2}"
2596 2 : [(set_attr "isa" "noavx,avx")
2597 2 : (set_attr "type" "sselog")
2598 : (set_attr "prefix" "orig,vex")
2599 2 : (set_attr "mode" "V4SF")])
2600 :
2601 : (define_insn "<code><mode>3"
2602 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2603 : (any_logic:VHBF_32_64
2604 : (match_operand:VHBF_32_64 1 "register_operand" "%0,x")
2605 : (match_operand:VHBF_32_64 2 "register_operand" " x,x")))]
2606 41 : "TARGET_SSE"
2607 : "@
2608 : <logic>ps\t{%2, %0|%0, %2}
2609 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
2610 57 : [(set_attr "isa" "noavx,avx")
2611 57 : (set_attr "type" "sselog,sselog")
2612 44 : (set_attr "prefix" "orig,vex")
2613 : (set_attr "mode" "V4SF")])
2614 44 :
2615 : (define_expand "copysign<mode>3"
2616 : [(set (match_dup 4)
2617 : (and:VHBF_32_64
2618 : (not:VHBF_32_64 (match_dup 3))
2619 : (match_operand:VHBF_32_64 1 "register_operand")))
2620 : (set (match_dup 5)
2621 : (and:VHBF_32_64 (match_dup 3)
2622 : (match_operand:VHBF_32_64 2 "register_operand")))
2623 : (set (match_operand:VHBF_32_64 0 "register_operand")
2624 : (ior:VHBF_32_64 (match_dup 4) (match_dup 5)))]
2625 : "TARGET_SSE"
2626 2 : {
2627 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2628 :
2629 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2630 2 : operands[5] = gen_reg_rtx (<MODE>mode);
2631 : })
2632 :
2633 : (define_expand "xorsign<mode>3"
2634 : [(set (match_dup 4)
2635 2 : (and:VHBF_32_64 (match_dup 3)
2636 : (match_operand:VHBF_32_64 2 "register_operand")))
2637 : (set (match_operand:VHBF_32_64 0 "register_operand")
2638 : (xor:VHBF_32_64 (match_dup 4)
2639 : (match_operand:VHBF_32_64 1 "register_operand")))]
2640 : "TARGET_SSE"
2641 4 : {
2642 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2643 :
2644 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2645 : })
2646 2 :
2647 : (define_expand "signbit<mode>2"
2648 2 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
2649 4 : (lshiftrt:<mmxintvecmode>
2650 2 : (subreg:<mmxintvecmode>
2651 : (match_operand:VHBF_32_64 1 "register_operand") 0)
2652 : (match_dup 2)))]
2653 : "TARGET_SSE2"
2654 2 : {
2655 0 : operands[1] = force_reg (<MODE>mode, operands[1]);
2656 0 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);
2657 : })
2658 :
2659 4 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2660 : ;;
2661 4 : ;; Parallel half-precision FMA multiply/accumulate instructions.
2662 4 : ;;
2663 4 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2664 :
2665 0 : (define_expand "fma<mode>4"
2666 : [(set (match_operand:VHF_32_64 0 "register_operand")
2667 : (fma:VHF_32_64
2668 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2669 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2670 4 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2671 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2672 6 : {
2673 6 : rtx op3 = gen_reg_rtx (V8HFmode);
2674 6 : rtx op2 = gen_reg_rtx (V8HFmode);
2675 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2676 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2677 :
2678 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2679 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2680 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2681 :
2682 2 : emit_insn (gen_fmav8hf4 (op0, op1, op2, op3));
2683 :
2684 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2685 2 : DONE;
2686 : })
2687 :
2688 : (define_expand "fms<mode>4"
2689 : [(set (match_operand:VHF_32_64 0 "register_operand")
2690 : (fma:VHF_32_64
2691 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2692 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2693 : (neg:VHF_32_64
2694 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2695 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2696 2 : {
2697 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2698 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2699 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2700 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2701 2 :
2702 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2703 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2704 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2705 :
2706 2 : emit_insn (gen_fmsv8hf4 (op0, op1, op2, op3));
2707 :
2708 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2709 2 : DONE;
2710 : })
2711 :
2712 : (define_expand "fnma<mode>4"
2713 : [(set (match_operand:VHF_32_64 0 "register_operand")
2714 : (fma:VHF_32_64
2715 : (neg:VHF_32_64
2716 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2717 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2718 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2719 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2720 2 : {
2721 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2722 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2723 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2724 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2725 2 :
2726 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2727 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2728 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2729 :
2730 2 : emit_insn (gen_fnmav8hf4 (op0, op1, op2, op3));
2731 :
2732 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2733 2 : DONE;
2734 : })
2735 :
2736 : (define_expand "fnms<mode>4"
2737 : [(set (match_operand:VHF_32_64 0 "register_operand" "=v,v,x")
2738 : (fma:VHF_32_64
2739 : (neg:VHF_32_64
2740 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2741 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2742 : (neg:VHF_32_64
2743 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2744 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2745 2 : {
2746 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2747 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2748 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2749 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2750 2 :
2751 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2752 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2753 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2754 :
2755 2 : emit_insn (gen_fnmsv8hf4 (op0, op1, op2, op3));
2756 :
2757 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2758 2 : DONE;
2759 : })
2760 :
2761 : (define_expand "vec_fmaddsubv4hf4"
2762 : [(match_operand:V4HF 0 "register_operand")
2763 : (match_operand:V4HF 1 "nonimmediate_operand")
2764 : (match_operand:V4HF 2 "nonimmediate_operand")
2765 : (match_operand:V4HF 3 "nonimmediate_operand")]
2766 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2767 : && TARGET_MMX_WITH_SSE
2768 : && ix86_partial_vec_fp_math"
2769 1 : {
2770 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2771 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2772 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2773 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2774 :
2775 3 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2776 3 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2777 3 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2778 :
2779 1 : emit_insn (gen_vec_fmaddsubv8hf4 (op0, op1, op2, op3));
2780 :
2781 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2782 1 : DONE;
2783 : })
2784 :
2785 : (define_expand "vec_fmsubaddv4hf4"
2786 : [(match_operand:V4HF 0 "register_operand")
2787 : (match_operand:V4HF 1 "nonimmediate_operand")
2788 : (match_operand:V4HF 2 "nonimmediate_operand")
2789 : (match_operand:V4HF 3 "nonimmediate_operand")]
2790 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2791 : && ix86_partial_vec_fp_math
2792 : && TARGET_MMX_WITH_SSE"
2793 1 : {
2794 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2795 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2796 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2797 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2798 1 :
2799 2 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2800 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2801 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2802 :
2803 1 : emit_insn (gen_vec_fmsubaddv8hf4 (op0, op1, op2, op3));
2804 :
2805 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2806 1 : DONE;
2807 : })
2808 :
2809 : (define_expand "fma<mode>4"
2810 : [(set (match_operand:VBF_32_64 0 "register_operand")
2811 : (fma:VBF_32_64
2812 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2813 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2814 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2815 : "TARGET_AVX10_2"
2816 2 : {
2817 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2818 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2819 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2820 3 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2821 :
2822 3 : emit_insn (gen_fmav8bf4 (op0, op1, op2, op3));
2823 1 :
2824 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2825 2 : DONE;
2826 : })
2827 :
2828 : (define_expand "fms<mode>4"
2829 : [(set (match_operand:VBF_32_64 0 "register_operand")
2830 : (fma:VBF_32_64
2831 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2832 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2833 : (neg:VBF_32_64
2834 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2835 : "TARGET_AVX10_2"
2836 2 : {
2837 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2838 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2839 4 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2840 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2841 2 :
2842 4 : emit_insn (gen_fmsv8bf4 (op0, op1, op2, op3));
2843 2 :
2844 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2845 2 : DONE;
2846 : })
2847 :
2848 : (define_expand "fnma<mode>4"
2849 : [(set (match_operand:VBF_32_64 0 "register_operand")
2850 : (fma:VBF_32_64
2851 : (neg:VBF_32_64
2852 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2853 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2854 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2855 : "TARGET_AVX10_2"
2856 2 : {
2857 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2858 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2859 6 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2860 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2861 4 :
2862 6 : emit_insn (gen_fnmav8bf4 (op0, op1, op2, op3));
2863 4 :
2864 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2865 2 : DONE;
2866 : })
2867 :
2868 : (define_expand "fnms<mode>4"
2869 : [(set (match_operand:VBF_32_64 0 "register_operand")
2870 : (fma:VBF_32_64
2871 : (neg:VBF_32_64
2872 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2873 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2874 : (neg:VBF_32_64
2875 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2876 : "TARGET_AVX10_2"
2877 2 : {
2878 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2879 6 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2880 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2881 6 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2882 4 :
2883 6 : emit_insn (gen_fnmsv8bf4 (op0, op1, op2, op3));
2884 :
2885 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2886 2 : DONE;
2887 : })
2888 :
2889 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2890 : ;;
2891 : ;; Parallel half-precision floating point complex type operations
2892 : ;;
2893 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2894 :
2895 : (define_expand "cmlav4hf4"
2896 : [(match_operand:V4HF 0 "register_operand")
2897 : (match_operand:V4HF 1 "vector_operand")
2898 : (match_operand:V4HF 2 "vector_operand")
2899 : (match_operand:V4HF 3 "vector_operand")]
2900 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2901 2 : && TARGET_MMX_WITH_SSE"
2902 1 : {
2903 3 : rtx op3 = gen_reg_rtx (V8HFmode);
2904 3 : rtx op2 = gen_reg_rtx (V8HFmode);
2905 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2906 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2907 :
2908 1 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2909 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2910 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2911 :
2912 1 : emit_insn (gen_cmlav8hf4 (op0, op1, op2, op3));
2913 :
2914 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2915 1 : DONE;
2916 : })
2917 :
2918 : (define_expand "cmla_conjv4hf4"
2919 : [(match_operand:V4HF 0 "register_operand")
2920 : (match_operand:V4HF 1 "vector_operand")
2921 : (match_operand:V4HF 2 "vector_operand")
2922 : (match_operand:V4HF 3 "vector_operand")]
2923 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2924 : && TARGET_MMX_WITH_SSE"
2925 1 : {
2926 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2927 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2928 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2929 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2930 :
2931 4 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2932 4 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2933 4 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2934 :
2935 1 : emit_insn (gen_cmla_conjv8hf4 (op0, op1, op2, op3));
2936 :
2937 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2938 1 : DONE;
2939 : })
2940 :
2941 : (define_expand "cmulv4hf3"
2942 : [(match_operand:V4HF 0 "register_operand")
2943 : (match_operand:V4HF 1 "vector_operand")
2944 : (match_operand:V4HF 2 "vector_operand")]
2945 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2946 : && TARGET_MMX_WITH_SSE"
2947 1 : {
2948 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2949 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2950 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2951 :
2952 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2953 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2954 1 :
2955 2 : emit_insn (gen_cmulv8hf3 (op0, op1, op2));
2956 2 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2957 1 : DONE;
2958 : })
2959 :
2960 : (define_expand "cmul_conjv4hf3"
2961 : [(match_operand:V4HF 0 "register_operand")
2962 : (match_operand:V4HF 1 "vector_operand")
2963 : (match_operand:V4HF 2 "vector_operand")]
2964 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2965 : && TARGET_MMX_WITH_SSE"
2966 1 : {
2967 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2968 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2969 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2970 1 :
2971 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2972 2 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2973 1 :
2974 2 : emit_insn (gen_cmul_conjv8hf3 (op0, op1, op2));
2975 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2976 1 : DONE;
2977 : })
2978 :
2979 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2980 : ;;
2981 : ;; Parallel half-precision floating point conversion operations
2982 : ;;
2983 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2984 :
2985 : (define_expand "fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2"
2986 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
2987 : (any_fix:<mmxintvecmode>
2988 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
2989 1 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2990 8 : {
2991 9 : rtx op1 = gen_reg_rtx (V8HFmode);
2992 9 : rtx op0 = gen_reg_rtx (V8HImode);
2993 1 :
2994 8 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2995 :
2996 8 : emit_insn (gen_fix<fixunssuffix>_truncv8hfv8hi2 (op0, op1));
2997 :
2998 8 : emit_move_insn (operands[0],
2999 : lowpart_subreg (<mmxintvecmode>mode, op0, V8HImode));
3000 8 : DONE;
3001 : })
3002 :
3003 : (define_expand "fix<fixunssuffix>_truncv2hfv2si2"
3004 : [(set (match_operand:V2SI 0 "register_operand")
3005 : (any_fix:V2SI
3006 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3007 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3008 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3009 2 : {
3010 2 : rtx op1 = gen_reg_rtx (V8HFmode);
3011 2 : rtx op0 = gen_reg_rtx (V4SImode);
3012 :
3013 8 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3014 :
3015 8 : emit_insn (gen_avx512fp16_fix<fixunssuffix>_truncv4si2 (op0, op1));
3016 6 :
3017 8 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
3018 2 : DONE;
3019 : })
3020 :
3021 : (define_expand "float<floatunssuffix><mmxintvecmodelower><mode>2"
3022 : [(set (match_operand:VHF_32_64 0 "register_operand")
3023 : (any_float:VHF_32_64
3024 : (match_operand:<mmxintvecmode> 1 "nonimmediate_operand")))]
3025 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
3026 8 : {
3027 8 : rtx op1 = gen_reg_rtx (V8HImode);
3028 8 : rtx op0 = gen_reg_rtx (V8HFmode);
3029 :
3030 8 : rtx (*gen_movd_sse) (rtx, rtx)
3031 4 : = gen_mov<mov_to_sse_suffix>_<mmxintvecmodelower>_to_sse;
3032 8 : emit_insn (gen_movd_sse (op1, operands[1]));
3033 4 :
3034 12 : emit_insn (gen_float<floatunssuffix>v8hiv8hf2 (op0, op1));
3035 4 :
3036 8 : emit_move_insn (operands[0],
3037 : lowpart_subreg (<MODE>mode, op0, V8HFmode));
3038 8 : DONE;
3039 : })
3040 :
3041 : (define_expand "float<floatunssuffix>v2siv2hf2"
3042 : [(set (match_operand:V2HF 0 "register_operand")
3043 : (any_float:V2HF
3044 : (match_operand:V2SI 1 "nonimmediate_operand")))]
3045 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3046 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3047 2 : {
3048 2 : rtx op1 = gen_reg_rtx (V4SImode);
3049 2 : rtx op0 = gen_reg_rtx (V8HFmode);
3050 :
3051 5 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
3052 1 :
3053 5 : emit_insn (gen_avx512fp16_float<floatunssuffix>v4siv4hf2 (op0, op1));
3054 4 :
3055 5 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3056 3 : DONE;
3057 : })
3058 :
3059 : (define_expand "extendv2hfv2sf2"
3060 : [(set (match_operand:V2SF 0 "register_operand")
3061 : (float_extend:V2SF
3062 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3063 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3064 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3065 1 : {
3066 1 : rtx op1 = gen_reg_rtx (V8HFmode);
3067 1 : rtx op0 = gen_reg_rtx (V4SFmode);
3068 :
3069 76 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3070 :
3071 76 : emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1));
3072 75 :
3073 76 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3074 1 : DONE;
3075 : })
3076 :
3077 : (define_expand "truncv2sfv2hf2"
3078 : [(set (match_operand:V2HF 0 "register_operand")
3079 : (float_truncate:V2HF
3080 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3081 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3082 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3083 1 : {
3084 1 : rtx op1 = gen_reg_rtx (V4SFmode);
3085 1 : rtx op0 = gen_reg_rtx (V8HFmode);
3086 :
3087 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
3088 0 :
3089 1 : emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1));
3090 0 :
3091 1 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3092 1 : DONE;
3093 : })
3094 :
3095 : (define_expand "truncv2sfv2bf2"
3096 : [(set (match_operand:V2BF 0 "register_operand")
3097 : (float_truncate:V2BF
3098 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3099 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE
3100 : && !HONOR_NANS (BFmode) && !flag_rounding_math
3101 : && (flag_unsafe_math_optimizations
3102 : || TARGET_AVXNECONVERT
3103 : || (TARGET_AVX512BF16 && TARGET_AVX512VL))"
3104 2 : {
3105 35 : rtx op1 = gen_reg_rtx (V4SFmode);
3106 2 : rtx op0 = gen_reg_rtx (V4BFmode);
3107 33 :
3108 35 : emit_move_insn (op1, lowpart_subreg (V4SFmode,
3109 33 : force_reg (V2SFmode, operands[1]),
3110 : V2SFmode));
3111 2 : emit_insn (gen_truncv4sfv4bf2 (op0, op1));
3112 :
3113 2 : emit_move_insn (operands[0], lowpart_subreg (V2BFmode, op0, V4BFmode));
3114 2 : DONE;
3115 : })
3116 :
3117 : (define_expand "extendv2bfv2sf2"
3118 : [(set (match_operand:V2SF 0 "register_operand")
3119 : (float_extend:V2SF
3120 : (match_operand:V2BF 1 "nonimmediate_operand")))]
3121 : "TARGET_SSE2 && TARGET_MMX_WITH_SSE && !HONOR_NANS (BFmode)"
3122 2 : {
3123 2 : rtx op0 = gen_reg_rtx (V4SFmode);
3124 2 : rtx op1 = gen_reg_rtx (V4BFmode);
3125 :
3126 2 : emit_move_insn (op1, lowpart_subreg (V4BFmode,
3127 36 : force_reg (V2BFmode, operands[1]),
3128 : V2BFmode));
3129 38 : emit_insn (gen_extendv4bfv4sf2 (op0, op1));
3130 36 :
3131 38 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3132 2 : DONE;
3133 : })
3134 :
3135 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3136 : ;;
3137 : ;; Parallel integral arithmetic
3138 : ;;
3139 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3140 :
3141 : (define_expand "neg<mode>2"
3142 : [(set (match_operand:MMXMODEI 0 "register_operand")
3143 : (minus:MMXMODEI
3144 : (match_dup 2)
3145 40 : (match_operand:MMXMODEI 1 "register_operand")))]
3146 : "TARGET_MMX_WITH_SSE"
3147 116 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3148 40 :
3149 40 : (define_expand "neg<mode>2"
3150 : [(set (match_operand:VI_32 0 "register_operand")
3151 76 : (minus:VI_32
3152 : (match_dup 2)
3153 : (match_operand:VI_32 1 "register_operand")))]
3154 : "TARGET_SSE2"
3155 78 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3156 :
3157 : (define_insn "negv2qi2"
3158 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,&Yw")
3159 2 : (neg:V2QI
3160 99 : (match_operand:V2QI 1 "register_operand" "0,Yw")))
3161 : (clobber (reg:CC FLAGS_REG))]
3162 109 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3163 101 : "#"
3164 102 : [(set_attr "isa" "*,sse2")
3165 3 : (set_attr "type" "multi")
3166 : (set_attr "mode" "QI,TI")
3167 : (set (attr "enabled")
3168 46 : (cond [(and (eq_attr "alternative" "0")
3169 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3170 36924 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3171 36925 : (symbol_ref "false")
3172 47 : ]
3173 5801 : (const_string "*")))])
3174 5802 :
3175 1 : (define_split
3176 : [(set (match_operand:V2QI 0 "general_reg_operand")
3177 : (neg:V2QI
3178 : (match_operand:V2QI 1 "general_reg_operand")))
3179 : (clobber (reg:CC FLAGS_REG))]
3180 1 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3181 1 : && reload_completed"
3182 1 : [(parallel
3183 1 : [(set (strict_low_part (match_dup 0))
3184 0 : (neg:QI (match_dup 1)))
3185 1 : (clobber (reg:CC FLAGS_REG))])
3186 : (parallel
3187 : [(set (zero_extract:HI (match_dup 2) (const_int 8) (const_int 8))
3188 : (subreg:HI
3189 : (neg:QI
3190 : (subreg:QI
3191 : (zero_extract:HI (match_dup 3)
3192 : (const_int 8)
3193 : (const_int 8)) 0)) 0))
3194 : (clobber (reg:CC FLAGS_REG))])]
3195 1 : {
3196 1 : operands[3] = lowpart_subreg (HImode, operands[1], V2QImode);
3197 1 : operands[2] = lowpart_subreg (HImode, operands[0], V2QImode);
3198 1 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3199 1 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3200 : })
3201 :
3202 : (define_split
3203 1 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3204 : (neg:V2QI
3205 : (match_operand:V2QI 1 "sse_reg_operand")))
3206 : (clobber (reg:CC FLAGS_REG))]
3207 0 : "TARGET_SSE2 && reload_completed"
3208 1 : [(set (match_dup 0) (match_dup 2))
3209 0 : (set (match_dup 0)
3210 : (minus:V16QI (match_dup 0) (match_dup 1)))]
3211 3467 : {
3212 3468 : operands[2] = CONST0_RTX (V16QImode);
3213 0 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3214 52 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3215 104 : })
3216 :
3217 1050 : (define_expand "mmx_<insn><mode>3"
3218 0 : [(set (match_operand:MMXMODEI8 0 "register_operand")
3219 1050 : (plusminus:MMXMODEI8
3220 1050 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand")
3221 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))]
3222 0 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3223 254 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3224 1050 :
3225 : (define_expand "<insn><mode>3"
3226 : [(set (match_operand:MMXMODEI 0 "register_operand")
3227 6455 : (plusminus:MMXMODEI
3228 : (match_operand:MMXMODEI 1 "register_operand")
3229 6234 : (match_operand:MMXMODEI 2 "register_operand")))]
3230 6201 : "TARGET_MMX_WITH_SSE")
3231 287 :
3232 33 : (define_insn "*mmx_<insn><mode>3"
3233 33 : [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,<Yv_Yw>")
3234 6201 : (plusminus:MMXMODEI8
3235 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand"
3236 2275 : "<comm>0,0,<Yv_Yw>")
3237 224 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand"
3238 2275 : "ym,x,<Yv_Yw>")))]
3239 11483 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3240 105491 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3241 53301 : "@
3242 33 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3243 2308 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3244 145481 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3245 145481 : [(set_attr "isa" "*,sse2_noavx,avx")
3246 145481 : (set_attr "mmx_isa" "native,*,*")
3247 : (set_attr "type" "mmxadd,sseadd,sseadd")
3248 242442 : (set_attr "mode" "DI,TI,TI")])
3249 :
3250 142 : (define_insn "<insn><mode>3"
3251 142 : [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
3252 142 : (plusminus:VI_32
3253 : (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
3254 : (match_operand:VI_32 2 "register_operand" "x,Yw")))]
3255 10123 : "TARGET_SSE2"
3256 : "@
3257 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3258 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3259 12452 : [(set_attr "isa" "noavx,avx")
3260 1556 : (set_attr "type" "sseadd")
3261 10896 : (set_attr "mode" "TI")])
3262 1556 :
3263 12452 : (define_insn "<insn>v2qi3"
3264 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,x,Yw")
3265 1556 : (plusminus:V2QI
3266 : (match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
3267 : (match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
3268 : (clobber (reg:CC FLAGS_REG))]
3269 2220 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3270 : "#"
3271 549 : [(set_attr "isa" "*,sse2_noavx,avx")
3272 549 : (set_attr "type" "multi,sseadd,sseadd")
3273 : (set_attr "mode" "QI,TI,TI")
3274 : (set (attr "enabled")
3275 : (cond [(and (eq_attr "alternative" "0")
3276 7734185 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3277 8201 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3278 8230 : (symbol_ref "false")
3279 176 : ]
3280 120346 : (const_string "*")))])
3281 8071 :
3282 17 : (define_split
3283 8071 : [(set (match_operand:V2QI 0 "general_reg_operand")
3284 : (plusminus:V2QI
3285 1885 : (match_operand:V2QI 1 "general_reg_operand")
3286 1885 : (match_operand:V2QI 2 "general_reg_operand")))
3287 1885 : (clobber (reg:CC FLAGS_REG))]
3288 2028 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3289 194 : && reload_completed"
3290 3919 : [(parallel
3291 953 : [(set (strict_low_part (match_dup 0))
3292 45 : (plusminus:QI (match_dup 1) (match_dup 2)))
3293 45 : (clobber (reg:CC FLAGS_REG))])
3294 953 : (parallel
3295 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
3296 : (subreg:HI
3297 : (plusminus:QI
3298 : (subreg:QI
3299 : (zero_extract:HI (match_dup 4)
3300 : (const_int 8)
3301 : (const_int 8)) 0)
3302 : (subreg:QI
3303 : (zero_extract:HI (match_dup 5)
3304 : (const_int 8)
3305 : (const_int 8)) 0)) 0))
3306 : (clobber (reg:CC FLAGS_REG))])]
3307 179 : {
3308 179 : operands[5] = lowpart_subreg (HImode, operands[2], V2QImode);
3309 179 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
3310 179 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
3311 179 : operands[2] = lowpart_subreg (QImode, operands[2], V2QImode);
3312 179 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3313 179 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3314 : })
3315 :
3316 : (define_split
3317 179 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3318 : (plusminus:V2QI
3319 : (match_operand:V2QI 1 "sse_reg_operand")
3320 : (match_operand:V2QI 2 "sse_reg_operand")))
3321 : (clobber (reg:CC FLAGS_REG))]
3322 45 : "TARGET_SSE2 && reload_completed"
3323 908 : [(set (match_dup 0)
3324 45 : (plusminus:V16QI (match_dup 1) (match_dup 2)))]
3325 45 : {
3326 2903224 : operands[2] = lowpart_subreg (V16QImode, operands[2], V2QImode);
3327 1493792 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3328 1409656 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3329 1409611 : })
3330 74 :
3331 74 : (define_expand "mmx_<insn><mode>3"
3332 1038 : [(set (match_operand:MMXMODE12 0 "register_operand")
3333 21 : (sat_plusminus:MMXMODE12
3334 1067 : (match_operand:MMXMODE12 1 "register_mmxmem_operand")
3335 960 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))]
3336 1005 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3337 208 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3338 :
3339 : (define_expand "<insn><mode>3"
3340 : [(set (match_operand:MMXMODE12 0 "register_operand")
3341 278 : (sat_plusminus:MMXMODE12
3342 : (match_operand:MMXMODE12 1 "register_operand")
3343 2 : (match_operand:MMXMODE12 2 "register_operand")))]
3344 2 : "TARGET_MMX_WITH_SSE")
3345 276 :
3346 : (define_insn "*mmx_<insn><mode>3"
3347 : [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yw")
3348 2 : (sat_plusminus:MMXMODE12
3349 : (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yw")
3350 98 : (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yw")))]
3351 232 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3352 1820 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3353 449 : "@
3354 68 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3355 351 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3356 1350 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3357 1031 : [(set_attr "isa" "*,sse2_noavx,avx")
3358 26 : (set_attr "mmx_isa" "native,*,*")
3359 : (set_attr "type" "mmxadd,sseadd,sseadd")
3360 351 : (set_attr "mode" "DI,TI,TI")])
3361 :
3362 427 : (define_insn "<insn><mode>3"
3363 39 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
3364 427 : (sat_plusminus:VI_16_32
3365 492 : (match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
3366 465 : (match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
3367 210 : "TARGET_SSE2"
3368 26 : "@
3369 27 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3370 17 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3371 444 : [(set_attr "isa" "noavx,avx")
3372 444 : (set_attr "type" "sseadd")
3373 : (set_attr "mode" "TI")])
3374 34 :
3375 337 : (define_insn "mulv2si3"
3376 15564 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
3377 14106 : (mult:V2SI
3378 13771 : (match_operand:V2SI 1 "register_operand" "%0,0,v")
3379 1462 : (match_operand:V2SI 2 "register_operand" "Yr,*x,v")))]
3380 6344 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3381 : "@
3382 351220 : pmulld\t{%2, %0|%0, %2}
3383 350163 : pmulld\t{%2, %0|%0, %2}
3384 356920 : vpmulld\t{%2, %1, %0|%0, %1, %2}"
3385 7811 : [(set_attr "isa" "noavx,noavx,avx")
3386 : (set_attr "type" "sseimul")
3387 11430 : (set_attr "prefix_extra" "1")
3388 196 : (set_attr "prefix" "orig,orig,vex")
3389 536 : (set_attr "btver2_decode" "vector")
3390 0 : (set_attr "mode" "TI")])
3391 0 :
3392 0 : (define_expand "mmx_mulv4hi3"
3393 : [(set (match_operand:V4HI 0 "register_operand")
3394 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand")
3395 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3396 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3397 33 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3398 :
3399 : (define_expand "mulv4hi3"
3400 : [(set (match_operand:V4HI 0 "register_operand")
3401 33 : (mult:V4HI (match_operand:V4HI 1 "register_operand")
3402 : (match_operand:V4HI 2 "register_operand")))]
3403 : "TARGET_MMX_WITH_SSE")
3404 :
3405 33 : (define_insn "*mmx_mulv4hi3"
3406 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3407 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3408 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3409 4477 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3410 4499 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3411 2280 : "@
3412 22 : pmullw\t{%2, %0|%0, %2}
3413 22 : pmullw\t{%2, %0|%0, %2}
3414 10221 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3415 10199 : [(set_attr "isa" "*,sse2_noavx,avx")
3416 : (set_attr "mmx_isa" "native,*,*")
3417 10199 : (set_attr "type" "mmxmul,ssemul,ssemul")
3418 : (set_attr "mode" "DI,TI,TI")])
3419 :
3420 : (define_insn "mulv2hi3"
3421 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3422 : (mult:V2HI (match_operand:V2HI 1 "register_operand" "%0,Yw")
3423 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3424 8527 : "TARGET_SSE2"
3425 : "@
3426 : pmullw\t{%2, %0|%0, %2}
3427 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3428 : [(set_attr "isa" "noavx,avx")
3429 : (set_attr "type" "ssemul")
3430 : (set_attr "mode" "TI")])
3431 :
3432 397601 : (define_expand "mulv8qi3"
3433 397601 : [(set (match_operand:V8QI 0 "register_operand")
3434 397601 : (mult:V8QI (match_operand:V8QI 1 "register_operand")
3435 : (match_operand:V8QI 2 "register_operand")))]
3436 213284 : "TARGET_MMX_WITH_SSE"
3437 213643 : {
3438 359 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3439 39689 : DONE;
3440 39330 : })
3441 39330 :
3442 39330 : (define_expand "mulv4qi3"
3443 39330 : [(set (match_operand:V4QI 0 "register_operand")
3444 39330 : (mult:V4QI (match_operand:V4QI 1 "register_operand")
3445 : (match_operand:V4QI 2 "register_operand")))]
3446 21413 : "TARGET_SSE2"
3447 22351 : {
3448 22351 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3449 938 : DONE;
3450 : })
3451 41640 :
3452 : (define_expand "mmx_smulv4hi3_highpart"
3453 11 : [(set (match_operand:V4HI 0 "register_operand")
3454 : (truncate:V4HI
3455 11 : (lshiftrt:V4SI
3456 11 : (mult:V4SI
3457 : (sign_extend:V4SI
3458 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3459 : (sign_extend:V4SI
3460 11 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3461 : (const_int 16))))]
3462 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3463 56 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3464 :
3465 38 : (define_insn "*mmx_smulv4hi3_highpart"
3466 22 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3467 72 : (truncate:V4HI
3468 16 : (lshiftrt:V4SI
3469 : (mult:V4SI
3470 : (sign_extend:V4SI
3471 16 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3472 34 : (sign_extend:V4SI
3473 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3474 : (const_int 16))))]
3475 16 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3476 196 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3477 22 : "@
3478 : pmulhw\t{%2, %0|%0, %2}
3479 22 : pmulhw\t{%2, %0|%0, %2}
3480 27 : vpmulhw\t{%2, %1, %0|%0, %1, %2}"
3481 27 : [(set_attr "isa" "*,sse2_noavx,avx")
3482 : (set_attr "mmx_isa" "native,*,*")
3483 : (set_attr "type" "mmxmul,ssemul,ssemul")
3484 : (set_attr "mode" "DI,TI,TI")])
3485 :
3486 : (define_expand "mmx_umulv4hi3_highpart"
3487 : [(set (match_operand:V4HI 0 "register_operand")
3488 : (truncate:V4HI
3489 : (lshiftrt:V4SI
3490 : (mult:V4SI
3491 : (zero_extend:V4SI
3492 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3493 : (zero_extend:V4SI
3494 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3495 : (const_int 16))))]
3496 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3497 : && (TARGET_SSE || TARGET_3DNOW_A)"
3498 22 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3499 :
3500 : (define_insn "*mmx_umulv4hi3_highpart"
3501 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3502 22 : (truncate:V4HI
3503 : (lshiftrt:V4SI
3504 : (mult:V4SI
3505 : (zero_extend:V4SI
3506 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3507 22 : (zero_extend:V4SI
3508 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3509 : (const_int 16))))]
3510 17 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3511 241 : && (TARGET_SSE || TARGET_3DNOW_A)
3512 242 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3513 0 : "@
3514 1 : pmulhuw\t{%2, %0|%0, %2}
3515 1 : pmulhuw\t{%2, %0|%0, %2}
3516 5 : vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
3517 5 : [(set_attr "isa" "*,sse2_noavx,avx")
3518 : (set_attr "mmx_isa" "native,*,*")
3519 1 : (set_attr "type" "mmxmul,ssemul,ssemul")
3520 : (set_attr "mode" "DI,TI,TI")])
3521 :
3522 : (define_expand "<s>mulv4hi3_highpart"
3523 : [(set (match_operand:V4HI 0 "register_operand")
3524 17 : (truncate:V4HI
3525 : (lshiftrt:V4SI
3526 17 : (mult:V4SI
3527 17 : (any_extend:V4SI
3528 : (match_operand:V4HI 1 "register_operand"))
3529 : (any_extend:V4SI
3530 17 : (match_operand:V4HI 2 "register_operand")))
3531 : (const_int 16))))]
3532 : "TARGET_MMX_WITH_SSE")
3533 :
3534 : (define_insn "<s>mulv2hi3_highpart"
3535 515 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3536 : (truncate:V2HI
3537 515 : (lshiftrt:V2SI
3538 515 : (mult:V2SI
3539 : (any_extend:V2SI
3540 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
3541 : (any_extend:V2SI
3542 515 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
3543 : (const_int 16))))]
3544 10 : "TARGET_SSE2"
3545 : "@
3546 : pmulh<u>w\t{%2, %0|%0, %2}
3547 31 : vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
3548 : [(set_attr "isa" "noavx,avx")
3549 31 : (set_attr "type" "ssemul")
3550 31 : (set_attr "mode" "TI")])
3551 31 :
3552 3600 : (define_expand "mmx_pmaddwd"
3553 3600 : [(set (match_operand:V2SI 0 "register_operand")
3554 : (plus:V2SI
3555 : (mult:V2SI
3556 2436 : (sign_extend:V2SI
3557 482 : (vec_select:V2HI
3558 2195 : (match_operand:V4HI 1 "register_mmxmem_operand")
3559 : (parallel [(const_int 0) (const_int 2)])))
3560 94 : (sign_extend:V2SI
3561 94 : (vec_select:V2HI
3562 : (match_operand:V4HI 2 "register_mmxmem_operand")
3563 94 : (parallel [(const_int 0) (const_int 2)]))))
3564 94 : (mult:V2SI
3565 94 : (sign_extend:V2SI
3566 : (vec_select:V2HI (match_dup 1)
3567 94 : (parallel [(const_int 1) (const_int 3)])))
3568 94 : (sign_extend:V2SI
3569 94 : (vec_select:V2HI (match_dup 2)
3570 : (parallel [(const_int 1) (const_int 3)]))))))]
3571 94 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3572 128 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3573 94 :
3574 94 : (define_insn "*mmx_pmaddwd"
3575 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yw")
3576 128 : (plus:V2SI
3577 94 : (mult:V2SI
3578 94 : (sign_extend:V2SI
3579 : (vec_select:V2HI
3580 94 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3581 94 : (parallel [(const_int 0) (const_int 2)])))
3582 94 : (sign_extend:V2SI
3583 : (vec_select:V2HI
3584 94 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")
3585 94 : (parallel [(const_int 0) (const_int 2)]))))
3586 94 : (mult:V2SI
3587 34 : (sign_extend:V2SI
3588 94 : (vec_select:V2HI (match_dup 1)
3589 94 : (parallel [(const_int 1) (const_int 3)])))
3590 94 : (sign_extend:V2SI
3591 94 : (vec_select:V2HI (match_dup 2)
3592 348 : (parallel [(const_int 1) (const_int 3)]))))))]
3593 275 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3594 529 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3595 435 : "@
3596 7 : pmaddwd\t{%2, %0|%0, %2}
3597 87 : pmaddwd\t{%2, %0|%0, %2}
3598 87 : vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
3599 341 : [(set_attr "isa" "*,sse2_noavx,avx")
3600 : (set_attr "mmx_isa" "native,*,*")
3601 87 : (set_attr "type" "mmxmul,sseiadd,sseiadd")
3602 1618190 : (set_attr "mode" "DI,TI,TI")])
3603 1618190 :
3604 1618277 : (define_expand "mmx_pmulhrwv4hi3"
3605 1618115 : [(set (match_operand:V4HI 0 "register_operand")
3606 1618103 : (truncate:V4HI
3607 1618115 : (lshiftrt:V4SI
3608 1618103 : (plus:V4SI
3609 12 : (mult:V4SI
3610 1204510 : (sign_extend:V4SI
3611 1204510 : (match_operand:V4HI 1 "nonimmediate_operand"))
3612 1204510 : (sign_extend:V4SI
3613 1204510 : (match_operand:V4HI 2 "nonimmediate_operand")))
3614 1204510 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3615 : (const_int 32768) (const_int 32768)]))
3616 1071196 : (const_int 16))))]
3617 1071196 : "TARGET_3DNOW"
3618 1071210 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3619 1071196 :
3620 1071196 : (define_insn "*mmx_pmulhrwv4hi3"
3621 1071196 : [(set (match_operand:V4HI 0 "register_operand" "=y")
3622 1071210 : (truncate:V4HI
3623 1071196 : (lshiftrt:V4SI
3624 1071196 : (plus:V4SI
3625 1071196 : (mult:V4SI
3626 1071196 : (sign_extend:V4SI
3627 1071196 : (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
3628 1071196 : (sign_extend:V4SI
3629 1071196 : (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
3630 14 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3631 3964 : (const_int 32768) (const_int 32768)]))
3632 3964 : (const_int 16))))]
3633 87 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3634 3972 : "pmulhrw\t{%2, %0|%0, %2}"
3635 : [(set_attr "type" "mmxmul")
3636 327 : (set_attr "prefix_extra" "1")
3637 1528 : (set_attr "mode" "DI")])
3638 1855 :
3639 1528 : (define_expand "sse2_umulv1siv1di3"
3640 327 : [(set (match_operand:V1DI 0 "register_operand")
3641 1528 : (mult:V1DI
3642 1528 : (zero_extend:V1DI
3643 : (vec_select:V1SI
3644 1492 : (match_operand:V2SI 1 "register_mmxmem_operand")
3645 1492 : (parallel [(const_int 0)])))
3646 1492 : (zero_extend:V1DI
3647 : (vec_select:V1SI
3648 1492 : (match_operand:V2SI 2 "register_mmxmem_operand")
3649 1492 : (parallel [(const_int 0)])))))]
3650 1492 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
3651 1504 : "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
3652 1492 :
3653 : (define_insn "*sse2_umulv1siv1di3"
3654 419 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
3655 431 : (mult:V1DI
3656 : (zero_extend:V1DI
3657 277 : (vec_select:V1SI
3658 : (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
3659 : (parallel [(const_int 0)])))
3660 419 : (zero_extend:V1DI
3661 12 : (vec_select:V1SI
3662 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
3663 : (parallel [(const_int 0)])))))]
3664 65 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3665 65 : && TARGET_SSE2
3666 89 : && ix86_binary_operator_ok (MULT, V2SImode, operands)"
3667 1 : "@
3668 24 : pmuludq\t{%2, %0|%0, %2}
3669 24 : pmuludq\t{%2, %0|%0, %2}
3670 : vpmuludq\t{%2, %1, %0|%0, %1, %2}"
3671 : [(set_attr "isa" "*,sse2_noavx,avx")
3672 24 : (set_attr "mmx_isa" "native,*,*")
3673 : (set_attr "type" "mmxmul,ssemul,ssemul")
3674 91706 : (set_attr "mode" "DI,TI,TI")])
3675 91706 :
3676 91706 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3677 262 : ;;
3678 13131 : ;; Parallel integral shifts
3679 13393 : ;;
3680 13393 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3681 13131 :
3682 13131 : (define_insn "<code><mode>3"
3683 : [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
3684 1807 : (smaxmin:MMXMODE14
3685 1545 : (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
3686 : (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
3687 408 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3688 : "@
3689 1439 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3690 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3691 559 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3692 60 : [(set_attr "isa" "noavx,noavx,avx")
3693 20 : (set_attr "type" "sseiadd")
3694 : (set_attr "prefix_extra" "1")
3695 : (set_attr "prefix" "orig,orig,vex")
3696 : (set_attr "mode" "TI")])
3697 :
3698 : (define_expand "mmx_<code>v4hi3"
3699 : [(set (match_operand:V4HI 0 "register_operand")
3700 : (smaxmin:V4HI
3701 : (match_operand:V4HI 1 "register_mmxmem_operand")
3702 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3703 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3704 : && (TARGET_SSE || TARGET_3DNOW_A)"
3705 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
3706 :
3707 : (define_insn "*mmx_<code>v4hi3"
3708 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3709 44 : (smaxmin:V4HI
3710 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3711 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3712 109 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3713 543 : && (TARGET_SSE || TARGET_3DNOW_A)
3714 998 : && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
3715 : "@
3716 : p<maxmin_int>w\t{%2, %0|%0, %2}
3717 : p<maxmin_int>w\t{%2, %0|%0, %2}
3718 169 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3719 285 : [(set_attr "isa" "*,sse2_noavx,avx")
3720 63 : (set_attr "mmx_isa" "native,*,*")
3721 242 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3722 0 : (set_attr "mode" "DI,TI,TI")])
3723 179 :
3724 : (define_expand "<code>v4hi3"
3725 63 : [(set (match_operand:V4HI 0 "register_operand")
3726 : (smaxmin:V4HI
3727 : (match_operand:V4HI 1 "register_operand")
3728 : (match_operand:V4HI 2 "register_operand")))]
3729 : "TARGET_MMX_WITH_SSE")
3730 306 :
3731 : (define_insn "<code><mode>3"
3732 306 : [(set (match_operand:VI1_16_32 0 "register_operand" "=Yr,*x,Yv")
3733 306 : (smaxmin:VI1_16_32
3734 : (match_operand:VI1_16_32 1 "register_operand" "%0,0,Yv")
3735 : (match_operand:VI1_16_32 2 "register_operand" "Yr,*x,Yv")))]
3736 106 : "TARGET_SSE4_1"
3737 306 : "@
3738 : p<maxmin_int>b\t{%2, %0|%0, %2}
3739 : p<maxmin_int>b\t{%2, %0|%0, %2}
3740 183 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3741 10 : [(set_attr "isa" "noavx,noavx,avx")
3742 18 : (set_attr "type" "sseiadd")
3743 : (set_attr "prefix_extra" "1")
3744 18 : (set_attr "prefix" "orig,orig,vex")
3745 18 : (set_attr "mode" "TI")])
3746 18 :
3747 : (define_insn "<code>v2hi3"
3748 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3749 : (smaxmin:V2HI
3750 : (match_operand:V2HI 1 "register_operand" "%0,Yw")
3751 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3752 173 : "TARGET_SSE2"
3753 : "@
3754 : p<maxmin_int>w\t{%2, %0|%0, %2}
3755 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3756 : [(set_attr "isa" "noavx,avx")
3757 : (set_attr "type" "sseiadd")
3758 : (set_attr "mode" "TI")])
3759 :
3760 : (define_insn "<code><mode>3"
3761 197076 : [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
3762 197076 : (umaxmin:MMXMODE24
3763 107869 : (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
3764 1647 : (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
3765 1873 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3766 : "@
3767 104793 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3768 104793 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3769 105073 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3770 280 : [(set_attr "isa" "noavx,noavx,avx")
3771 : (set_attr "type" "sseiadd")
3772 : (set_attr "prefix_extra" "1")
3773 223073 : (set_attr "prefix" "orig,orig,vex")
3774 223073 : (set_attr "mode" "TI")])
3775 223073 :
3776 : (define_expand "mmx_<code>v8qi3"
3777 : [(set (match_operand:V8QI 0 "register_operand")
3778 : (umaxmin:V8QI
3779 4186712 : (match_operand:V8QI 1 "register_mmxmem_operand")
3780 4186712 : (match_operand:V8QI 2 "register_mmxmem_operand")))]
3781 4186712 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3782 : && (TARGET_SSE || TARGET_3DNOW_A)"
3783 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
3784 :
3785 1107838 : (define_insn "*mmx_<code>v8qi3"
3786 1107838 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
3787 1107882 : (umaxmin:V8QI
3788 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
3789 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3790 280 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3791 4107232 : && (TARGET_SSE || TARGET_3DNOW_A)
3792 4107188 : && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
3793 4106908 : "@
3794 : p<maxmin_int>b\t{%2, %0|%0, %2}
3795 : p<maxmin_int>b\t{%2, %0|%0, %2}
3796 294 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3797 1468723 : [(set_attr "isa" "*,sse2_noavx,avx")
3798 1468601 : (set_attr "mmx_isa" "native,*,*")
3799 1468601 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3800 0 : (set_attr "mode" "DI,TI,TI")])
3801 0 :
3802 : (define_expand "<code>v8qi3"
3803 2441 : [(set (match_operand:V8QI 0 "register_operand")
3804 2355 : (umaxmin:V8QI
3805 2355 : (match_operand:V8QI 1 "register_operand")
3806 : (match_operand:V8QI 2 "register_operand")))]
3807 : "TARGET_MMX_WITH_SSE")
3808 :
3809 1217 : (define_insn "<code><mode>3"
3810 1217 : [(set (match_operand:VI1_16_32 0 "register_operand" "=x,Yw")
3811 1217 : (umaxmin:VI1_16_32
3812 1217 : (match_operand:VI1_16_32 1 "register_operand" "%0,Yw")
3813 0 : (match_operand:VI1_16_32 2 "register_operand" "x,Yw")))]
3814 409 : "TARGET_SSE2"
3815 201 : "@
3816 : p<maxmin_int>b\t{%2, %0|%0, %2}
3817 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3818 38 : [(set_attr "isa" "noavx,avx")
3819 28 : (set_attr "type" "sseiadd")
3820 : (set_attr "mode" "TI")])
3821 :
3822 : (define_insn "<code>v2hi3"
3823 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yv")
3824 : (umaxmin:V2HI
3825 : (match_operand:V2HI 1 "register_operand" "%0,0,Yv")
3826 : (match_operand:V2HI 2 "register_operand" "Yr,*x,Yv")))]
3827 10 : "TARGET_SSE4_1"
3828 : "@
3829 : p<maxmin_int>w\t{%2, %0|%0, %2}
3830 : p<maxmin_int>w\t{%2, %0|%0, %2}
3831 0 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3832 0 : [(set_attr "isa" "noavx,noavx,avx")
3833 0 : (set_attr "type" "sseiadd")
3834 0 : (set_attr "prefix_extra" "1")
3835 0 : (set_attr "prefix" "orig,orig,vex")
3836 : (set_attr "mode" "TI")])
3837 :
3838 : (define_insn "ssse3_abs<mode>2"
3839 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
3840 : (abs:MMXMODEI
3841 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))]
3842 106 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
3843 65 : "@
3844 : pabs<mmxvecsize>\t{%1, %0|%0, %1}
3845 : %vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3846 400 : [(set_attr "mmx_isa" "native,*")
3847 400 : (set_attr "type" "sselog1")
3848 390 : (set_attr "prefix_rep" "0")
3849 390 : (set_attr "prefix_extra" "1")
3850 687 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3851 : (set_attr "mode" "DI,TI")])
3852 :
3853 : (define_expand "abs<mode>2"
3854 : [(set (match_operand:MMXMODEI 0 "register_operand")
3855 : (abs:MMXMODEI
3856 : (match_operand:MMXMODEI 1 "register_operand")))]
3857 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
3858 :
3859 : (define_insn "abs<mode>2"
3860 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yv")
3861 : (abs:VI_16_32
3862 : (match_operand:VI_16_32 1 "register_operand" "Yv")))]
3863 36 : "TARGET_SSSE3"
3864 48 : "%vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3865 : [(set_attr "type" "sselog1")
3866 : (set_attr "prefix_rep" "0")
3867 32 : (set_attr "prefix_extra" "1")
3868 32 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3869 20 : (set_attr "mode" "TI")])
3870 20 :
3871 42 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3872 : ;;
3873 1793059 : ;; Parallel integral shifts
3874 : ;;
3875 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3876 :
3877 1793059 : (define_insn "mmx_ashr<mode>3"
3878 1793059 : [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,<Yv_Yw>")
3879 1793059 : (ashiftrt:MMXMODE24
3880 1793059 : (match_operand:MMXMODE24 1 "register_operand" "0,0,<Yv_Yw>")
3881 1793059 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3882 1795263 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3883 : "@
3884 1528 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3885 1528 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3886 3922 : vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3887 5450 : [(set_attr "isa" "*,sse2_noavx,avx")
3888 1528 : (set_attr "mmx_isa" "native,*,*")
3889 : (set_attr "type" "mmxshft,sseishft,sseishft")
3890 4675 : (set (attr "length_immediate")
3891 753 : (if_then_else (match_operand 2 "const_int_operand")
3892 753 : (const_string "1")
3893 1262 : (const_string "0")))
3894 244 : (set_attr "mode" "DI,TI,TI")])
3895 509 :
3896 509 : (define_insn_and_split "*mmx_ashr<mode>3_1"
3897 509 : [(set (match_operand:MMXMODE24 0 "register_operand")
3898 509 : (lt:MMXMODE24
3899 509 : (match_operand:MMXMODE24 1 "register_operand")
3900 : (match_operand:MMXMODE24 2 "const0_operand")))]
3901 5834 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3902 : "#"
3903 102 : "&& 1"
3904 608 : [(set (match_dup 0) (ashiftrt:MMXMODE24 (match_dup 1) (match_dup 3)))]
3905 2328 : "operands[3] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3906 1540 :
3907 191 : (define_expand "ashr<mode>3"
3908 685 : [(set (match_operand:MMXMODE24 0 "register_operand")
3909 : (ashiftrt:MMXMODE24
3910 : (match_operand:MMXMODE24 1 "register_operand")
3911 : (match_operand:DI 2 "nonmemory_operand")))]
3912 506 : "TARGET_MMX_WITH_SSE")
3913 :
3914 : (define_insn "mmx_<insn><mode>3"
3915 : [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,<Yv_Yw>")
3916 : (any_lshift:MMXMODE248
3917 22 : (match_operand:MMXMODE248 1 "register_operand" "0,0,<Yv_Yw>")
3918 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3919 6023 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3920 22 : "@
3921 22 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3922 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3923 45067 : vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3924 45067 : [(set_attr "isa" "*,sse2_noavx,avx")
3925 : (set_attr "mmx_isa" "native,*,*")
3926 : (set_attr "type" "mmxshft,sseishft,sseishft")
3927 45067 : (set (attr "length_immediate")
3928 : (if_then_else (match_operand 2 "const_int_operand")
3929 : (const_string "1")
3930 : (const_string "0")))
3931 : (set_attr "mode" "DI,TI,TI")])
3932 :
3933 : (define_split
3934 : [(set (match_operand:MMXMODE248 0 "register_operand")
3935 : (and:MMXMODE248
3936 : (lt:MMXMODE248
3937 : (match_operand:MMXMODE248 1 "register_operand")
3938 : (match_operand:MMXMODE248 2 "const0_operand"))
3939 : (match_operand:MMXMODE248 3 "const1_operand")))]
3940 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3941 26 : [(set (match_dup 0) (lshiftrt:MMXMODE248 (match_dup 1) (match_dup 4)))]
3942 0 : "operands[4] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3943 :
3944 26 : (define_expand "<insn><mode>3"
3945 26 : [(set (match_operand:MMXMODE24 0 "register_operand")
3946 : (any_lshift:MMXMODE24
3947 26 : (match_operand:MMXMODE24 1 "register_operand")
3948 : (match_operand:DI 2 "nonmemory_operand")))]
3949 0 : "TARGET_MMX_WITH_SSE")
3950 :
3951 : (define_insn "mmx_<insn>v1si3"
3952 : [(set (match_operand:V1SI 0 "register_operand" "=x,Yw")
3953 : (any_lshift:V1SI
3954 11 : (match_operand:V1SI 1 "register_operand" "0,Yw")
3955 45 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3956 3630 : "TARGET_SSE2"
3957 56 : "@
3958 11 : p<vshift>d\t{%2, %0|%0, %2}
3959 45 : vp<vshift>d\t{%2, %1, %0|%0, %1, %2}"
3960 846 : [(set_attr "isa" "noavx,avx")
3961 846 : (set_attr "type" "sseishft")
3962 : (set (attr "length_immediate")
3963 : (if_then_else (match_operand 2 "const_int_operand")
3964 846 : (const_string "1")
3965 : (const_string "0")))
3966 : (set_attr "mode" "TI")])
3967 :
3968 : (define_insn "<insn>v2hi3"
3969 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3970 : (any_shift:V2HI
3971 : (match_operand:V2HI 1 "register_operand" "0,Yw")
3972 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3973 946 : "TARGET_SSE2"
3974 : "@
3975 : p<vshift>w\t{%2, %0|%0, %2}
3976 : vp<vshift>w\t{%2, %1, %0|%0, %1, %2}"
3977 253 : [(set_attr "isa" "noavx,avx")
3978 253 : (set_attr "type" "sseishft")
3979 253 : (set (attr "length_immediate")
3980 : (if_then_else (match_operand 2 "const_int_operand")
3981 : (const_string "1")
3982 253 : (const_string "0")))
3983 : (set_attr "mode" "TI")])
3984 :
3985 : (define_insn_and_split "*mmx_ashrv2hi3_1"
3986 : [(set (match_operand:V2HI 0 "register_operand")
3987 : (lt:V2HI
3988 : (match_operand:V2HI 1 "register_operand")
3989 : (match_operand:V2HI 2 "const0_operand")))]
3990 150 : "TARGET_SSE2 && ix86_pre_reload_split ()"
3991 : "#"
3992 : "&& 1"
3993 12 : [(set (match_dup 0) (ashiftrt:V2HI (match_dup 1) (match_dup 3)))]
3994 12 : "operands[3] = gen_int_mode (15, DImode);")
3995 :
3996 : (define_split
3997 12 : [(set (match_operand:V2HI 0 "register_operand")
3998 : (and:V2HI
3999 533189 : (lt:V2HI
4000 533189 : (match_operand:V2HI 1 "register_operand")
4001 1000073 : (match_operand:V2HI 2 "const0_operand"))
4002 1000061 : (match_operand:V2HI 3 "const1_operand")))]
4003 1000061 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4004 533189 : [(set (match_dup 0) (lshiftrt:V2HI (match_dup 1) (match_dup 4)))]
4005 0 : "operands[4] = gen_int_mode (15, DImode);")
4006 5105 :
4007 1051659 : (define_expand "<insn>v8qi3"
4008 1046549 : [(set (match_operand:V8QI 0 "register_operand")
4009 1051659 : (any_shift:V8QI (match_operand:V8QI 1 "register_operand")
4010 0 : (match_operand:DI 2 "nonmemory_operand")))]
4011 245780 : "TARGET_MMX_WITH_SSE"
4012 245844 : {
4013 482885 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4014 482816 : operands[1], operands[2]);
4015 482885 : DONE;
4016 : })
4017 3 :
4018 : (define_expand "<insn>v4qi3"
4019 1472101 : [(set (match_operand:V4QI 0 "register_operand")
4020 1472101 : (any_shift:V4QI (match_operand:V4QI 1 "register_operand")
4021 1472101 : (match_operand:DI 2 "nonmemory_operand")))]
4022 : "TARGET_SSE2"
4023 33 : {
4024 33 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4025 738699 : operands[1], operands[2]);
4026 738732 : DONE;
4027 738699 : })
4028 738699 :
4029 7 : (define_insn_and_split "<insn>v2qi3"
4030 0 : [(set (match_operand:V2QI 0 "register_operand" "=Q")
4031 7 : (any_shift:V2QI
4032 7 : (match_operand:V2QI 1 "register_operand" "0")
4033 7 : (match_operand:QI 2 "nonmemory_operand" "cI")))
4034 : (clobber (reg:CC FLAGS_REG))]
4035 637 : "!TARGET_PARTIAL_REG_STALL || optimize_size"
4036 54 : "#"
4037 299 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
4038 299 : && reload_completed"
4039 50 : [(parallel
4040 53 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
4041 : (subreg:HI
4042 162286 : (any_shift:QI
4043 162286 : (subreg:QI
4044 134 : (zero_extract:HI (match_dup 4)
4045 69349 : (const_int 8)
4046 128260 : (const_int 8)) 0)
4047 128260 : (match_dup 2)) 0))
4048 128157 : (clobber (reg:CC FLAGS_REG))])
4049 59 : (parallel
4050 69 : [(set (strict_low_part (match_dup 0))
4051 20 : (any_shift:QI (match_dup 1) (match_dup 2)))
4052 : (clobber (reg:CC FLAGS_REG))])]
4053 50 : {
4054 50 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
4055 50 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
4056 50 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
4057 50 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
4058 : }
4059 : [(set_attr "type" "multi")
4060 : (set_attr "mode" "QI")])
4061 50 :
4062 : (define_expand "v<insn>v8qi3"
4063 : [(set (match_operand:V8QI 0 "register_operand")
4064 : (any_shift:V8QI
4065 : (match_operand:V8QI 1 "register_operand")
4066 : (match_operand:V8QI 2 "register_operand")))]
4067 : "TARGET_AVX512BW && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
4068 9 : {
4069 9 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4070 50 : operands[1], operands[2]);
4071 9 : DONE;
4072 : })
4073 :
4074 : (define_expand "v<insn>v4qi3"
4075 3 : [(set (match_operand:V4QI 0 "register_operand")
4076 : (any_shift:V4QI
4077 3 : (match_operand:V4QI 1 "register_operand")
4078 3 : (match_operand:V4QI 2 "register_operand")))]
4079 3 : "TARGET_AVX512BW && TARGET_AVX512VL"
4080 4 : {
4081 4 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4082 : operands[1], operands[2]);
4083 4 : DONE;
4084 : })
4085 5 :
4086 : (define_expand "vec_shl_<mode>"
4087 5 : [(set (match_operand:V248FI 0 "register_operand")
4088 5 : (ashift:V1DI
4089 5 : (match_operand:V248FI 1 "nonimmediate_operand")
4090 : (match_operand:DI 2 "nonmemory_operand")))]
4091 : "TARGET_MMX_WITH_SSE"
4092 7 : {
4093 8 : rtx op0 = gen_reg_rtx (V1DImode);
4094 7 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4095 :
4096 7 : emit_insn (gen_mmx_ashlv1di3
4097 9 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4098 7 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4099 9 : DONE;
4100 3 : })
4101 3 :
4102 : (define_expand "vec_shl_<mode>"
4103 : [(set (match_operand:V24FI_32 0 "register_operand")
4104 : (ashift:V1SI
4105 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4106 : (match_operand:DI 2 "nonmemory_operand")))]
4107 : "TARGET_SSE2"
4108 4 : {
4109 4 : rtx op0 = gen_reg_rtx (V1SImode);
4110 4 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4111 :
4112 4 : emit_insn (gen_mmx_ashlv1si3
4113 1172 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4114 4 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4115 1172 : DONE;
4116 1168 : })
4117 1168 :
4118 : (define_expand "vec_shr_<mode>"
4119 : [(set (match_operand:V248FI 0 "register_operand")
4120 : (lshiftrt:V1DI
4121 : (match_operand:V248FI 1 "nonimmediate_operand")
4122 : (match_operand:DI 2 "nonmemory_operand")))]
4123 : "TARGET_MMX_WITH_SSE"
4124 1168 : {
4125 1168 : rtx op0 = gen_reg_rtx (V1DImode);
4126 1168 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4127 :
4128 1168 : emit_insn (gen_mmx_lshrv1di3
4129 1397 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4130 1168 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4131 1397 : DONE;
4132 229 : })
4133 229 :
4134 : (define_expand "vec_shr_<mode>"
4135 : [(set (match_operand:V24FI_32 0 "register_operand")
4136 : (lshiftrt:V1SI
4137 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4138 : (match_operand:DI 2 "nonmemory_operand")))]
4139 : "TARGET_SSE2"
4140 229 : {
4141 229 : rtx op0 = gen_reg_rtx (V1SImode);
4142 229 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4143 :
4144 229 : emit_insn (gen_mmx_lshrv1si3
4145 1060 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4146 229 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4147 1060 : DONE;
4148 831 : })
4149 831 :
4150 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4151 : ;;
4152 : ;; Parallel integral comparisons
4153 : ;;
4154 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4155 :
4156 : (define_expand "mmx_eq<mode>3"
4157 : [(set (match_operand:MMXMODEI 0 "register_operand")
4158 : (eq:MMXMODEI
4159 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4160 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4161 172 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4162 105 : "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
4163 172 :
4164 172 : (define_insn "*mmx_eq<mode>3"
4165 172 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4166 105 : (eq:MMXMODEI
4167 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x")
4168 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4169 2473 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4170 10833 : && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
4171 10187 : "@
4172 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4173 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4174 17195 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4175 17379 : [(set_attr "isa" "*,sse2_noavx,avx")
4176 : (set_attr "mmx_isa" "native,*,*")
4177 25668 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4178 184 : (set_attr "mode" "DI,TI,TI")])
4179 184 :
4180 : (define_insn "*eq<mode>3"
4181 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4182 : (eq:VI_16_32
4183 : (match_operand:VI_16_32 1 "register_operand" "%0,x")
4184 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4185 710 : "TARGET_SSE2"
4186 : "@
4187 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4188 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4189 2108 : [(set_attr "isa" "noavx,avx")
4190 2108 : (set_attr "type" "ssecmp")
4191 : (set_attr "mode" "TI")])
4192 2108 :
4193 : (define_insn "mmx_gt<mode>3"
4194 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4195 : (gt:MMXMODEI
4196 : (match_operand:MMXMODEI 1 "register_operand" "0,0,x")
4197 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4198 2789 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4199 3871779 : "@
4200 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4201 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4202 12292 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4203 3884071 : [(set_attr "isa" "*,sse2_noavx,avx")
4204 3871779 : (set_attr "mmx_isa" "native,*,*")
4205 3884071 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4206 3871779 : (set_attr "mode" "DI,TI,TI")])
4207 3871779 :
4208 3871779 : (define_insn "*gt<mode>3"
4209 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4210 3871685 : (gt:VI_16_32
4211 3871685 : (match_operand:VI_16_32 1 "register_operand" "0,x")
4212 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4213 3833983 : "TARGET_SSE2"
4214 3833613 : "@
4215 3833613 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4216 3833613 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4217 3835170 : [(set_attr "isa" "noavx,avx")
4218 1557 : (set_attr "type" "ssecmp")
4219 4868 : (set_attr "mode" "TI")])
4220 6425 :
4221 4868 : (define_insn "*xop_maskcmp<mode>3"
4222 462 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4223 4406 : (match_operator:MMXMODEI 1 "ix86_comparison_int_operator"
4224 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4225 4552420 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4226 4552549 : "TARGET_XOP"
4227 4552420 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4228 4552420 : [(set_attr "type" "sse4arg")
4229 4552420 : (set_attr "mode" "TI")])
4230 4552420 :
4231 16574 : (define_insn "*xop_maskcmp<mode>3"
4232 6476 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4233 23050 : (match_operator:VI_16_32 1 "ix86_comparison_int_operator"
4234 : [(match_operand:VI_16_32 2 "register_operand" "x")
4235 6476 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4236 0 : "TARGET_XOP"
4237 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4238 : [(set_attr "type" "sse4arg")
4239 : (set_attr "mode" "TI")])
4240 2375 :
4241 2375 : (define_insn "*xop_maskcmp_uns<mode>3"
4242 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4243 2375 : (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator"
4244 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4245 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4246 3892206 : "TARGET_XOP"
4247 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4248 : [(set_attr "type" "sse4arg")
4249 : (set_attr "mode" "TI")])
4250 3903182 :
4251 3903182 : (define_insn "*xop_maskcmp_uns<mode>3"
4252 3892206 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4253 3903182 : (match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
4254 3892206 : [(match_operand:VI_16_32 2 "register_operand" "x")
4255 3892206 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4256 0 : "TARGET_XOP"
4257 3354605 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4258 3354605 : [(set_attr "type" "sse4arg")
4259 3354605 : (set_attr "mode" "TI")])
4260 3356388 :
4261 3356388 : (define_expand "vec_cmp<mode><mode>"
4262 3354605 : [(set (match_operand:MMXMODEI 0 "register_operand")
4263 3356388 : (match_operator:MMXMODEI 1 ""
4264 3354605 : [(match_operand:MMXMODEI 2 "register_operand")
4265 3354605 : (match_operand:MMXMODEI 3 "register_operand")]))]
4266 3354605 : "TARGET_MMX_WITH_SSE"
4267 3355331 : {
4268 3355331 : bool ok = ix86_expand_int_vec_cmp (operands);
4269 3355331 : gcc_assert (ok);
4270 6216197 : DONE;
4271 3354605 : })
4272 3354605 :
4273 : (define_expand "vec_cmp<mode><mode>"
4274 6164788 : [(set (match_operand:VI_16_32 0 "register_operand")
4275 6044374 : (match_operator:VI_16_32 1 ""
4276 2961749 : [(match_operand:VI_16_32 2 "register_operand")
4277 6265463 : (match_operand:VI_16_32 3 "register_operand")]))]
4278 2860866 : "TARGET_SSE2"
4279 1541 : {
4280 2862357 : bool ok = ix86_expand_int_vec_cmp (operands);
4281 2860928 : gcc_assert (ok);
4282 2861245 : DONE;
4283 2861133 : })
4284 2861229 :
4285 317 : (define_expand "vec_cmpu<mode><mode>"
4286 19410 : [(set (match_operand:MMXMODEI 0 "register_operand")
4287 19410 : (match_operator:MMXMODEI 1 ""
4288 19410 : [(match_operand:MMXMODEI 2 "register_operand")
4289 28276 : (match_operand:MMXMODEI 3 "register_operand")]))]
4290 30 : "TARGET_MMX_WITH_SSE"
4291 227 : {
4292 227 : bool ok = ix86_expand_int_vec_cmp (operands);
4293 197 : gcc_assert (ok);
4294 227 : DONE;
4295 : })
4296 347 :
4297 2 : (define_expand "vec_cmpu<mode><mode>"
4298 345 : [(set (match_operand:VI_16_32 0 "register_operand")
4299 345 : (match_operator:VI_16_32 1 ""
4300 345 : [(match_operand:VI_16_32 2 "register_operand")
4301 : (match_operand:VI_16_32 3 "register_operand")]))]
4302 : "TARGET_SSE2"
4303 109 : {
4304 109 : bool ok = ix86_expand_int_vec_cmp (operands);
4305 109 : gcc_assert (ok);
4306 109 : DONE;
4307 : })
4308 118 :
4309 : (define_expand "vcond_mask_<mode><mmxintvecmodelower>"
4310 118 : [(set (match_operand:MMXMODE124 0 "register_operand")
4311 118 : (vec_merge:MMXMODE124
4312 118 : (match_operand:MMXMODE124 1 "register_operand")
4313 : (match_operand:MMXMODE124 2 "register_operand")
4314 : (match_operand:<mmxintvecmode> 3 "register_operand")))]
4315 : "TARGET_MMX_WITH_SSE"
4316 379 : {
4317 379 : ix86_expand_sse_movcc (operands[0], operands[3],
4318 : operands[1], operands[2]);
4319 379 : DONE;
4320 : })
4321 9 :
4322 : (define_expand "vcond_mask_<mode><mode>"
4323 9 : [(set (match_operand:VI_16_32 0 "register_operand")
4324 0 : (vec_merge:VI_16_32
4325 9 : (match_operand:VI_16_32 1 "register_operand")
4326 : (match_operand:VI_16_32 2 "register_operand")
4327 : (match_operand:VI_16_32 3 "register_operand")))]
4328 : "TARGET_SSE2"
4329 118 : {
4330 118 : ix86_expand_sse_movcc (operands[0], operands[3],
4331 : operands[1], operands[2]);
4332 118 : DONE;
4333 : })
4334 33 :
4335 : (define_insn "mmx_pblendvb_v8qi"
4336 33 : [(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x")
4337 0 : (unspec:V8QI
4338 33 : [(match_operand:V8QI 1 "register_operand" "0,0,x")
4339 : (match_operand:V8QI 2 "register_operand" "Yr,*x,x")
4340 : (match_operand:V8QI 3 "register_operand" "Yz,Yz,x")]
4341 : UNSPEC_BLENDV))]
4342 1792 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4343 : "@
4344 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4345 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4346 3503 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4347 3465 : [(set_attr "isa" "noavx,noavx,avx")
4348 38 : (set_attr "type" "ssemov")
4349 3503 : (set_attr "prefix_extra" "1")
4350 38 : (set_attr "length_immediate" "1")
4351 : (set_attr "prefix" "orig,orig,vex")
4352 : (set_attr "btver2_decode" "vector")
4353 : (set_attr "mode" "TI")])
4354 :
4355 : (define_insn_and_split "*mmx_pblendvb_v8qi_1"
4356 : [(set (match_operand:V8QI 0 "register_operand")
4357 : (unspec:V8QI
4358 : [(match_operand:V8QI 1 "register_operand")
4359 : (match_operand:V8QI 2 "register_operand")
4360 : (eq:V8QI
4361 : (eq:V8QI
4362 : (match_operand:V8QI 3 "register_operand")
4363 : (match_operand:V8QI 4 "nonmemory_operand"))
4364 : (match_operand:V8QI 5 "const0_operand"))]
4365 : UNSPEC_BLENDV))]
4366 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4367 0 : "#"
4368 : "&& 1"
4369 0 : [(set (match_dup 6)
4370 0 : (eq:V8QI (match_dup 3) (match_dup 7)))
4371 6 : (set (match_dup 0)
4372 6 : (unspec:V8QI
4373 6 : [(match_dup 2)
4374 : (match_dup 1)
4375 : (match_dup 6)]
4376 : UNSPEC_BLENDV))]
4377 0 : {
4378 0 : operands[6] = gen_reg_rtx (V8QImode);
4379 0 : operands[7] = force_reg (V8QImode, operands[4]);
4380 : })
4381 :
4382 : (define_insn_and_split "*mmx_pblendvb_v8qi_2"
4383 0 : [(set (match_operand:V8QI 0 "register_operand")
4384 : (unspec:V8QI
4385 : [(match_operand:V8QI 1 "register_operand")
4386 : (match_operand:V8QI 2 "register_operand")
4387 : (subreg:V8QI
4388 0 : (eq:MMXMODE24
4389 : (eq:MMXMODE24
4390 : (match_operand:MMXMODE24 3 "register_operand")
4391 : (match_operand:MMXMODE24 4 "nonmemory_operand"))
4392 : (match_operand:MMXMODE24 5 "const0_operand")) 0)]
4393 : UNSPEC_BLENDV))]
4394 28 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4395 0 : "#"
4396 1 : "&& 1"
4397 0 : [(set (match_dup 6)
4398 10 : (eq:MMXMODE24 (match_dup 3) (match_dup 8)))
4399 30 : (set (match_dup 0)
4400 15 : (unspec:V8QI
4401 15 : [(match_dup 2)
4402 : (match_dup 1)
4403 : (match_dup 7)]
4404 : UNSPEC_BLENDV))]
4405 9 : {
4406 9 : operands[6] = gen_reg_rtx (<MODE>mode);
4407 9 : operands[7] = lowpart_subreg (V8QImode, operands[6], <MODE>mode);
4408 9 : operands[8] = force_reg (<MODE>mode, operands[4]);
4409 : })
4410 :
4411 : (define_insn "mmx_pblendvb_<mode>"
4412 9 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yr,*x,x")
4413 : (unspec:VI_16_32
4414 : [(match_operand:VI_16_32 1 "register_operand" "0,0,x")
4415 : (match_operand:VI_16_32 2 "register_operand" "Yr,*x,x")
4416 : (match_operand:VI_16_32 3 "register_operand" "Yz,Yz,x")]
4417 9 : UNSPEC_BLENDV))]
4418 1921 : "TARGET_SSE4_1"
4419 : "@
4420 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4421 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4422 1007 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4423 1012 : [(set_attr "isa" "noavx,noavx,avx")
4424 : (set_attr "type" "ssemov")
4425 1012 : (set_attr "prefix_extra" "1")
4426 0 : (set_attr "length_immediate" "1")
4427 5 : (set_attr "prefix" "orig,orig,vex")
4428 : (set_attr "btver2_decode" "vector")
4429 : (set_attr "mode" "TI")])
4430 :
4431 : (define_insn_and_split "*mmx_pblendvb_<mode>_1"
4432 : [(set (match_operand:VI_16_32 0 "register_operand")
4433 : (unspec:VI_16_32
4434 : [(match_operand:VI_16_32 1 "register_operand")
4435 : (match_operand:VI_16_32 2 "register_operand")
4436 : (eq:VI_16_32
4437 : (eq:VI_16_32
4438 : (match_operand:VI_16_32 3 "register_operand")
4439 : (match_operand:VI_16_32 4 "nonmemory_operand"))
4440 : (match_operand:VI_16_32 5 "const0_operand"))]
4441 : UNSPEC_BLENDV))]
4442 36 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4443 0 : "#"
4444 : "&& 1"
4445 0 : [(set (match_dup 6)
4446 18 : (eq:VI_16_32 (match_dup 3) (match_dup 7)))
4447 24 : (set (match_dup 0)
4448 12 : (unspec:VI_16_32
4449 24 : [(match_dup 2)
4450 : (match_dup 1)
4451 : (match_dup 6)]
4452 5624 : UNSPEC_BLENDV))]
4453 5642 : {
4454 8457 : operands[6] = gen_reg_rtx (<MODE>mode);
4455 8466 : operands[7] = force_reg (<MODE>mode, operands[4]);
4456 18 : })
4457 8439 :
4458 8439 : (define_insn_and_split "*mmx_pblendvb_v4qi_2"
4459 8457 : [(set (match_operand:V4QI 0 "register_operand")
4460 8439 : (unspec:V4QI
4461 8439 : [(match_operand:V4QI 1 "register_operand")
4462 8439 : (match_operand:V4QI 2 "register_operand")
4463 8439 : (subreg:V4QI
4464 18 : (eq:V2HI
4465 8439 : (eq:V2HI
4466 : (match_operand:V2HI 3 "register_operand")
4467 7006 : (match_operand:V2HI 4 "nonmemory_operand"))
4468 7006 : (match_operand:V2HI 5 "const0_operand")) 0)]
4469 5 : UNSPEC_BLENDV))]
4470 7054 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4471 5 : "#"
4472 8 : "&& 1"
4473 0 : [(set (match_dup 6)
4474 18 : (eq:V2HI (match_dup 3) (match_dup 8)))
4475 : (set (match_dup 0)
4476 5 : (unspec:V4QI
4477 : [(match_dup 2)
4478 784 : (match_dup 1)
4479 784 : (match_dup 7)]
4480 : UNSPEC_BLENDV))]
4481 15 : {
4482 15 : operands[6] = gen_reg_rtx (V2HImode);
4483 15 : operands[7] = lowpart_subreg (V4QImode, operands[6], V2HImode);
4484 28348 : operands[8] = force_reg (V2HImode, operands[4]);
4485 28333 : })
4486 0 :
4487 800 : ;; XOP parallel XMM conditional moves
4488 821 : (define_insn "*xop_pcmov_<mode>"
4489 : [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
4490 : (if_then_else:MMXMODE124
4491 : (match_operand:MMXMODE124 3 "register_operand" "x")
4492 : (match_operand:MMXMODE124 1 "register_operand" "x")
4493 15 : (match_operand:MMXMODE124 2 "register_operand" "x")))]
4494 174 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4495 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4496 : [(set_attr "type" "sse4arg")
4497 : (set_attr "mode" "TI")])
4498 390 :
4499 381 : (define_insn "*xop_pcmov_<mode>"
4500 9 : [(set (match_operand:V4F_64 0 "register_operand" "=x")
4501 393 : (if_then_else:V4F_64
4502 : (match_operand:V4F_64 3 "register_operand" "x")
4503 : (match_operand:V4F_64 1 "register_operand" "x")
4504 : (match_operand:V4F_64 2 "register_operand" "x")))]
4505 18 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4506 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4507 : [(set_attr "type" "sse4arg")
4508 : (set_attr "mode" "TI")])
4509 3 :
4510 3 : (define_insn "*xop_pcmov_<mode>"
4511 1 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4512 3 : (if_then_else:VI_16_32
4513 1 : (match_operand:VI_16_32 3 "register_operand" "x")
4514 0 : (match_operand:VI_16_32 1 "register_operand" "x")
4515 1 : (match_operand:VI_16_32 2 "register_operand" "x")))]
4516 0 : "TARGET_XOP"
4517 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4518 : [(set_attr "type" "sse4arg")
4519 : (set_attr "mode" "TI")])
4520 243 :
4521 243 : (define_insn "*xop_pcmov_<mode>"
4522 : [(set (match_operand:V2F_32 0 "register_operand" "=x")
4523 243 : (if_then_else:V2F_32
4524 : (match_operand:V2F_32 3 "register_operand" "x")
4525 : (match_operand:V2F_32 1 "register_operand" "x")
4526 : (match_operand:V2F_32 2 "register_operand" "x")))]
4527 3 : "TARGET_XOP"
4528 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4529 : [(set_attr "type" "sse4arg")
4530 : (set_attr "mode" "TI")])
4531 3 :
4532 3 : ;; XOP permute instructions
4533 : (define_insn "mmx_ppermv64"
4534 3 : [(set (match_operand:V8QI 0 "register_operand" "=x")
4535 318 : (unspec:V8QI
4536 318 : [(match_operand:V8QI 1 "register_operand" "x")
4537 : (match_operand:V8QI 2 "register_operand" "x")
4538 311 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4539 311 : UNSPEC_XOP_PERMUTE))]
4540 546 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4541 311 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4542 311 : [(set_attr "type" "sse4arg")
4543 : (set_attr "mode" "TI")])
4544 307 :
4545 307 : (define_insn "mmx_ppermv32"
4546 307 : [(set (match_operand:V4QI 0 "register_operand" "=x")
4547 307 : (unspec:V4QI
4548 307 : [(match_operand:V4QI 1 "register_operand" "x")
4549 : (match_operand:V4QI 2 "register_operand" "x")
4550 306 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4551 306 : UNSPEC_XOP_PERMUTE))]
4552 306 : "TARGET_XOP"
4553 306 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4554 : [(set_attr "type" "sse4arg")
4555 302 : (set_attr "mode" "TI")])
4556 :
4557 80 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4558 80 : ;;
4559 : ;; Parallel integral logical operations
4560 14199 : ;;
4561 14279 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4562 :
4563 10 : (define_expand "one_cmpl<mode>2"
4564 10 : [(set (match_operand:MMXMODEI 0 "register_operand")
4565 10 : (xor:MMXMODEI
4566 : (match_operand:MMXMODEI 1 "register_operand")
4567 10 : (match_dup 2)))]
4568 10 : "TARGET_MMX_WITH_SSE"
4569 48 : "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
4570 :
4571 10 : (define_insn "one_cmpl<mode>2"
4572 10 : [(set (match_operand:VI_16_32 0 "register_operand" "=?r,&x,&v")
4573 48 : (not:VI_16_32
4574 10 : (match_operand:VI_16_32 1 "register_operand" "0,x,v")))]
4575 10 : ""
4576 : "#"
4577 38 : [(set_attr "isa" "*,sse2,avx512vl")
4578 0 : (set_attr "type" "negnot,sselog1,sselog1")
4579 0 : (set_attr "mode" "SI,TI,TI")])
4580 :
4581 : (define_split
4582 2 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4583 1 : (not:VI_16_32
4584 2 : (match_operand:VI_16_32 1 "general_reg_operand")))]
4585 4 : "reload_completed"
4586 3 : [(set (match_dup 0)
4587 376777 : (not:SI (match_dup 1)))]
4588 9 : {
4589 11 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4590 376781 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4591 : })
4592 :
4593 : (define_split
4594 3 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4595 0 : (not:VI_16_32
4596 : (match_operand:VI_16_32 1 "sse_reg_operand")))]
4597 10 : "TARGET_SSE2 && reload_completed"
4598 7 : [(set (match_dup 0) (match_dup 2))
4599 376755 : (set (match_dup 0)
4600 40 : (xor:V16QI
4601 40 : (match_dup 0) (match_dup 1)))]
4602 376802 : {
4603 31 : operands[2] = CONSTM1_RTX (V16QImode);
4604 7 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4605 31 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4606 0 : })
4607 24 :
4608 : (define_expand "andn<mode>3"
4609 7 : [(set (match_operand:MMXMODEI 0 "register_operand")
4610 : (and:MMXMODEI
4611 : (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand"))
4612 : (match_operand:MMXMODEI 1 "register_operand")))]
4613 7 : "TARGET_MMX_WITH_SSE")
4614 :
4615 : (define_insn "mmx_andnot<mode>3"
4616 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4617 : (and:MMXMODEI
4618 0 : (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
4619 36 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4620 265 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4621 36 : "@
4622 0 : pandn\t{%2, %0|%0, %2}
4623 36 : pandn\t{%2, %0|%0, %2}
4624 3496 : vpandn\t{%2, %1, %0|%0, %1, %2}
4625 3355 : vpandnd\t{%2, %1, %0|%0, %1, %2}"
4626 141 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4627 3355 : (set_attr "mmx_isa" "native,*,*,*")
4628 126 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4629 15 : (set_attr "mode" "DI,TI,TI,TI")])
4630 15 :
4631 : (define_insn "*andnot<mode>3"
4632 97 : [(set (match_operand:VI_16_32 0 "register_operand" "=?&r,?r,x,x,v")
4633 97 : (and:VI_16_32
4634 97 : (not:VI_16_32
4635 : (match_operand:VI_16_32 1 "register_operand" "0,r,0,x,v"))
4636 84 : (match_operand:VI_16_32 2 "register_operand" "r,r,x,x,v")))
4637 13 : (clobber (reg:CC FLAGS_REG))]
4638 13 : ""
4639 : "#"
4640 124 : [(set_attr "isa" "*,bmi,sse2_noavx,avx,avx512vl")
4641 124 : (set_attr "type" "alu,bitmanip,sselog,sselog,sselog")
4642 124 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4643 :
4644 99 : (define_split
4645 25 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4646 25 : (and:VI_16_32
4647 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4648 0 : (match_operand:VI_16_32 2 "general_reg_operand")))
4649 0 : (clobber (reg:CC FLAGS_REG))]
4650 1 : "TARGET_BMI && reload_completed"
4651 0 : [(parallel
4652 3 : [(set (match_dup 0)
4653 : (and:SI (not:SI (match_dup 1)) (match_dup 2)))
4654 : (clobber (reg:CC FLAGS_REG))])]
4655 0 : {
4656 0 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4657 0 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4658 0 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4659 : })
4660 :
4661 : (define_split
4662 0 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4663 : (and:VI_16_32
4664 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4665 : (match_operand:VI_16_32 2 "general_reg_operand")))
4666 : (clobber (reg:CC FLAGS_REG))]
4667 3 : "!TARGET_BMI && reload_completed"
4668 3 : [(set (match_dup 0)
4669 : (not:SI (match_dup 1)))
4670 120 : (parallel
4671 58 : [(set (match_dup 0)
4672 58 : (and:SI (match_dup 0) (match_dup 2)))
4673 120 : (clobber (reg:CC FLAGS_REG))])]
4674 3 : {
4675 3 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4676 3 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4677 3 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4678 : })
4679 :
4680 : (define_split
4681 3 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4682 : (and:VI_16_32
4683 : (not:VI_16_32 (match_operand:VI_16_32 1 "sse_reg_operand"))
4684 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4685 : (clobber (reg:CC FLAGS_REG))]
4686 61 : "TARGET_SSE2 && reload_completed"
4687 62 : [(set (match_dup 0)
4688 58 : (and:V16QI (not:V16QI (match_dup 1)) (match_dup 2)))]
4689 58 : {
4690 2047 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4691 2121 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4692 134 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4693 1987 : })
4694 150 :
4695 76 : (define_expand "mmx_<code><mode>3"
4696 136 : [(set (match_operand:MMXMODEI 0 "register_operand")
4697 : (any_logic:MMXMODEI
4698 2 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4699 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4700 58 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4701 109 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4702 :
4703 : (define_expand "<code><mode>3"
4704 : [(set (match_operand:MMXMODEI 0 "register_operand")
4705 413 : (any_logic:MMXMODEI
4706 : (match_operand:MMXMODEI 1 "register_operand")
4707 304 : (match_operand:MMXMODEI 2 "register_operand")))]
4708 304 : "TARGET_MMX_WITH_SSE")
4709 109 :
4710 : (define_insn "*mmx_<code><mode>3"
4711 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4712 269 : (any_logic:MMXMODEI
4713 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
4714 2044 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4715 1808 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4716 31858 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4717 10471 : "@
4718 149 : p<logic>\t{%2, %0|%0, %2}
4719 842 : p<logic>\t{%2, %0|%0, %2}
4720 34355 : vp<logic>\t{%2, %1, %0|%0, %1, %2}
4721 35408 : vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
4722 24728 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4723 : (set_attr "mmx_isa" "native,*,*,*")
4724 43624 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4725 : (set_attr "mode" "DI,TI,TI,TI")])
4726 92 :
4727 5 : (define_expand "<code><mode>3"
4728 92 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand")
4729 198 : (any_logic:VI_16_32
4730 92 : (match_operand:VI_16_32 1 "nonimmediate_operand")
4731 106 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand")))]
4732 101 : ""
4733 342 : "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
4734 :
4735 : (define_insn "*<code><mode>3"
4736 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v")
4737 : (any_logic:VI_16_32
4738 : (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v")
4739 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand" "r,i,x,x,v")))
4740 : (clobber (reg:CC FLAGS_REG))]
4741 3618 : "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4742 220 : "#"
4743 920 : [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl")
4744 920 : (set_attr "type" "alu,alu,sselog,sselog,sselog")
4745 5595 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4746 5935 :
4747 1353 : (define_split
4748 1575 : [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand")
4749 479 : (any_logic:VI_16_32
4750 11925 : (match_operand:VI_16_32 1 "nonimmediate_gr_operand")
4751 92 : (match_operand:VI_16_32 2 "reg_or_const_vector_operand")))
4752 4146 : (clobber (reg:CC FLAGS_REG))]
4753 4168 : "reload_completed"
4754 55 : [(parallel
4755 905 : [(set (match_dup 0)
4756 307 : (any_logic:<mmxinsnmode> (match_dup 1) (match_dup 2)))
4757 307 : (clobber (reg:CC FLAGS_REG))])]
4758 960 : {
4759 55 : if (!register_operand (operands[2], <MODE>mode))
4760 : {
4761 9 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2],
4762 : <MODE>mode);
4763 9 : operands[2] = GEN_INT (val);
4764 : }
4765 : else
4766 46 : operands[2] = lowpart_subreg (<mmxinsnmode>mode, operands[2], <MODE>mode);
4767 55 : operands[1] = lowpart_subreg (<mmxinsnmode>mode, operands[1], <MODE>mode);
4768 55 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
4769 : })
4770 :
4771 : (define_split
4772 55 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4773 : (any_logic:VI_16_32
4774 : (match_operand:VI_16_32 1 "sse_reg_operand")
4775 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4776 55 : (clobber (reg:CC FLAGS_REG))]
4777 307 : "TARGET_SSE2 && reload_completed"
4778 598 : [(set (match_dup 0)
4779 307 : (any_logic:V16QI (match_dup 1) (match_dup 2)))]
4780 307 : {
4781 848 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4782 1480 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4783 356 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4784 911 : })
4785 529 :
4786 863 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4787 307 : ;;
4788 : ;; Parallel integral element swizzling
4789 : ;;
4790 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4791 307 :
4792 : (define_insn_and_split "mmx_packsswb"
4793 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4794 : (vec_concat:V8QI
4795 : (ss_truncate:V4QI
4796 : (match_operand:V4HI 1 "register_operand" "0,0,Yw"))
4797 4756 : (ss_truncate:V4QI
4798 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4799 5101 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4800 0 : "@
4801 4756 : packsswb\t{%2, %0|%0, %2}
4802 : #
4803 286 : #"
4804 98 : "&& reload_completed
4805 46 : && SSE_REGNO_P (REGNO (operands[0]))"
4806 : [(const_int 0)]
4807 92 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4808 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4809 112 : (set_attr "type" "mmxshft,sselog,sselog")
4810 224 : (set_attr "mode" "DI,TI,TI")])
4811 :
4812 : ;; This instruction does unsigned saturation of signed source
4813 : ;; and is different from generic us_truncate RTX.
4814 : (define_insn_and_split "mmx_packuswb"
4815 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4816 : (unspec:V8QI
4817 : [(match_operand:V4HI 1 "register_operand" "0,0,Yw")
4818 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")]
4819 480 : UNSPEC_US_TRUNCATE))]
4820 6150 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4821 480 : "@
4822 0 : packuswb\t{%2, %0|%0, %2}
4823 480 : #
4824 1041 : #"
4825 2213 : "&& reload_completed
4826 586 : && SSE_REGNO_P (REGNO (operands[0]))"
4827 : [(const_int 0)]
4828 1172 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4829 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4830 180 : (set_attr "type" "mmxshft,sselog,sselog")
4831 360 : (set_attr "mode" "DI,TI,TI")])
4832 :
4833 : (define_insn_and_split "mmx_packssdw"
4834 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4835 : (vec_concat:V4HI
4836 : (ss_truncate:V2HI
4837 : (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
4838 : (ss_truncate:V2HI
4839 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4840 770 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4841 : "@
4842 366 : packssdw\t{%2, %0|%0, %2}
4843 0 : #
4844 366 : #"
4845 112 : "&& reload_completed
4846 56 : && SSE_REGNO_P (REGNO (operands[0]))"
4847 : [(const_int 0)]
4848 112 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4849 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4850 : (set_attr "type" "mmxshft,sselog,sselog")
4851 : (set_attr "mode" "DI,TI,TI")])
4852 :
4853 : (define_insn_and_split "mmx_packusdw"
4854 13394 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
4855 : (unspec:V4HI
4856 482816 : [(match_operand:V2SI 1 "register_operand" "0,0,Yw")
4857 : (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")]
4858 496210 : UNSPEC_US_TRUNCATE))]
4859 498492 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4860 496210 : "#"
4861 496410 : "&& reload_completed"
4862 496230 : [(const_int 0)]
4863 496410 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4864 13394 : [(set_attr "isa" "noavx,noavx,avx")
4865 315629 : (set_attr "type" "sselog")
4866 315629 : (set_attr "mode" "TI")])
4867 379332 :
4868 365938 : (define_insn_and_split "mmx_punpckhbw"
4869 458961 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4870 458961 : (vec_select:V8QI
4871 458961 : (vec_concat:V16QI
4872 450301 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4873 374555 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4874 156708 : (parallel [(const_int 4) (const_int 12)
4875 382662 : (const_int 5) (const_int 13)
4876 48594 : (const_int 6) (const_int 14)
4877 6400 : (const_int 7) (const_int 15)])))]
4878 1714 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4879 7974 : "@
4880 7968 : punpckhbw\t{%2, %0|%0, %2}
4881 1612 : #
4882 12223 : #"
4883 3694 : "&& reload_completed
4884 435 : && SSE_REGNO_P (REGNO (operands[0]))"
4885 : [(const_int 0)]
4886 1066 : "ix86_split_mmx_punpck (operands, true); DONE;"
4887 392 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4888 960 : (set_attr "type" "mmxcvt,sselog,sselog")
4889 1920 : (set_attr "mode" "DI,TI,TI")])
4890 :
4891 : (define_insn_and_split "mmx_punpckhbw_low"
4892 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4893 : (vec_select:V4QI
4894 : (vec_concat:V8QI
4895 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4896 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4897 18 : (parallel [(const_int 2) (const_int 6)
4898 : (const_int 3) (const_int 7)])))]
4899 3689 : "TARGET_SSE2"
4900 18 : "#"
4901 496 : "&& reload_completed"
4902 : [(const_int 0)]
4903 13633 : "ix86_split_mmx_punpck (operands, true); DONE;"
4904 131 : [(set_attr "isa" "noavx,avx")
4905 2838 : (set_attr "type" "sselog")
4906 5676 : (set_attr "mode" "TI")])
4907 :
4908 : (define_insn_and_split "mmx_punpcklbw"
4909 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4910 : (vec_select:V8QI
4911 : (vec_concat:V16QI
4912 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4913 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4914 21 : (parallel [(const_int 0) (const_int 8)
4915 : (const_int 1) (const_int 9)
4916 21 : (const_int 2) (const_int 10)
4917 21 : (const_int 3) (const_int 11)])))]
4918 7561 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4919 : "@
4920 : punpcklbw\t{%2, %0|%0, %k2}
4921 : #
4922 3193 : #"
4923 4153 : "&& reload_completed
4924 480 : && SSE_REGNO_P (REGNO (operands[0]))"
4925 : [(const_int 0)]
4926 960 : "ix86_split_mmx_punpck (operands, false); DONE;"
4927 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4928 478 : (set_attr "type" "mmxcvt,sselog,sselog")
4929 478 : (set_attr "mode" "DI,TI,TI")])
4930 :
4931 : (define_insn_and_split "mmx_punpcklbw_low"
4932 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4933 : (vec_select:V4QI
4934 : (vec_concat:V8QI
4935 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4936 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4937 33 : (parallel [(const_int 0) (const_int 4)
4938 : (const_int 1) (const_int 5)])))]
4939 4991 : "TARGET_SSE2"
4940 33 : "#"
4941 765 : "&& reload_completed"
4942 : [(const_int 0)]
4943 17856 : "ix86_split_mmx_punpck (operands, false); DONE;"
4944 184 : [(set_attr "isa" "noavx,avx")
4945 3790 : (set_attr "type" "sselog")
4946 7580 : (set_attr "mode" "TI")])
4947 :
4948 : (define_insn_and_split "mmx_punpckhwd"
4949 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4950 : (vec_select:V4HI
4951 : (vec_concat:V8HI
4952 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
4953 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
4954 5 : (parallel [(const_int 2) (const_int 6)
4955 : (const_int 3) (const_int 7)])))]
4956 16129 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4957 5 : "@
4958 5 : punpckhwd\t{%2, %0|%0, %2}
4959 : #
4960 4226 : #"
4961 7064 : "&& reload_completed
4962 1419 : && SSE_REGNO_P (REGNO (operands[0]))"
4963 : [(const_int 0)]
4964 2838 : "ix86_split_mmx_punpck (operands, true); DONE;"
4965 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4966 732 : (set_attr "type" "mmxcvt,sselog,sselog")
4967 732 : (set_attr "mode" "DI,TI,TI")])
4968 :
4969 : (define_insn_and_split "mmx_punpcklwd"
4970 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4971 : (vec_select:V4HI
4972 : (vec_concat:V8HI
4973 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
4974 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
4975 29 : (parallel [(const_int 0) (const_int 4)
4976 : (const_int 1) (const_int 5)])))]
4977 21127 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4978 29 : "@
4979 29 : punpcklwd\t{%2, %0|%0, %k2}
4980 : #
4981 : #"
4982 3790 : "&& reload_completed
4983 1895 : && SSE_REGNO_P (REGNO (operands[0]))"
4984 : [(const_int 0)]
4985 8246 : "ix86_split_mmx_punpck (operands, false); DONE;"
4986 4456 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4987 4465 : (set_attr "type" "mmxcvt,sselog,sselog")
4988 : (set_attr "mode" "DI,TI,TI")])
4989 :
4990 : (define_insn_and_split "mmx_punpckhdq"
4991 493082 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
4992 493082 : (vec_select:V2SI
4993 493082 : (vec_concat:V4SI
4994 493082 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
4995 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
4996 315349 : (parallel [(const_int 1)
4997 315318 : (const_int 3)])))]
4998 322418 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4999 31 : "@
5000 31 : punpckhdq\t{%2, %0|%0, %2}
5001 : #
5002 35962 : #"
5003 532 : "&& reload_completed
5004 36228 : && SSE_REGNO_P (REGNO (operands[0]))"
5005 266 : [(const_int 0)]
5006 219387 : "ix86_split_mmx_punpck (operands, true); DONE;"
5007 219121 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5008 214495 : (set_attr "type" "mmxcvt,sselog,sselog")
5009 81 : (set_attr "mode" "DI,TI,TI")])
5010 81 :
5011 10835 : (define_insn_and_split "mmx_punpckldq"
5012 56242 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
5013 56242 : (vec_select:V2SI
5014 56242 : (vec_concat:V4SI
5015 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
5016 0 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
5017 14 : (parallel [(const_int 0)
5018 : (const_int 2)])))]
5019 12854 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5020 14 : "@
5021 14 : punpckldq\t{%2, %0|%0, %k2}
5022 : #
5023 2160 : #"
5024 2804 : "&& reload_completed
5025 322 : && SSE_REGNO_P (REGNO (operands[0]))"
5026 322 : [(const_int 0)]
5027 322 : "ix86_split_mmx_punpck (operands, false); DONE;"
5028 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5029 242 : (set_attr "type" "mmxcvt,sselog,sselog")
5030 242 : (set_attr "mode" "DI,TI,TI")])
5031 :
5032 : (define_insn "sse4_1_<code>v4qiv4hi2"
5033 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
5034 : (any_extend:V4HI
5035 : (vec_select:V4QI
5036 : (match_operand:V8QI 1 "register_operand" "Yr,*x,Yw")
5037 : (parallel [(const_int 0) (const_int 1)
5038 9 : (const_int 2) (const_int 3)]))))]
5039 2388 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5040 9 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5041 9 : [(set_attr "isa" "noavx,noavx,avx")
5042 9 : (set_attr "type" "ssemov")
5043 12114 : (set_attr "prefix_extra" "1")
5044 12114 : (set_attr "prefix" "orig,orig,maybe_evex")
5045 : (set_attr "mode" "TI")])
5046 2429 :
5047 2429 : (define_expand "<insn>v4qiv4hi2"
5048 : [(set (match_operand:V4HI 0 "register_operand")
5049 : (any_extend:V4HI
5050 : (match_operand:V4QI 1 "register_operand")))]
5051 : "TARGET_MMX_WITH_SSE"
5052 45 : {
5053 45 : if (!TARGET_SSE4_1)
5054 : {
5055 30 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5056 30 : DONE;
5057 : }
5058 :
5059 15 : rtx op1 = force_reg (V4QImode, operands[1]);
5060 15 : op1 = lowpart_subreg (V8QImode, op1, V4QImode);
5061 15 : emit_insn (gen_sse4_1_<code>v4qiv4hi2 (operands[0], op1));
5062 15 : DONE;
5063 : })
5064 :
5065 : (define_insn "sse4_1_<code>v2hiv2si2"
5066 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5067 : (any_extend:V2SI
5068 : (vec_select:V2HI
5069 : (match_operand:V4HI 1 "register_operand" "Yr,*x,v")
5070 : (parallel [(const_int 0) (const_int 1)]))))]
5071 4858 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5072 : "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
5073 : [(set_attr "isa" "noavx,noavx,avx")
5074 : (set_attr "type" "ssemov")
5075 538 : (set_attr "prefix_extra" "1")
5076 282 : (set_attr "prefix" "orig,orig,maybe_evex")
5077 256 : (set_attr "mode" "TI")])
5078 256 :
5079 256 : (define_expand "<insn>v2hiv2si2"
5080 : [(set (match_operand:V2SI 0 "register_operand")
5081 : (any_extend:V2SI
5082 : (match_operand:V2HI 1 "register_operand")))]
5083 : "TARGET_MMX_WITH_SSE"
5084 39 : {
5085 39 : if (!TARGET_SSE4_1)
5086 : {
5087 30 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5088 30 : DONE;
5089 : }
5090 :
5091 9 : rtx op1 = force_reg (V2HImode, operands[1]);
5092 9 : op1 = lowpart_subreg (V4HImode, op1, V2HImode);
5093 9 : emit_insn (gen_sse4_1_<code>v2hiv2si2 (operands[0], op1));
5094 9 : DONE;
5095 : })
5096 :
5097 : (define_insn "sse4_1_<code>v2qiv2si2"
5098 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5099 : (any_extend:V2SI
5100 : (vec_select:V2QI
5101 : (match_operand:V4QI 1 "register_operand" "Yr,*x,v")
5102 : (parallel [(const_int 0) (const_int 1)]))))]
5103 564 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5104 : "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
5105 : [(set_attr "isa" "noavx,noavx,avx")
5106 : (set_attr "type" "ssemov")
5107 708 : (set_attr "prefix_extra" "1")
5108 112 : (set_attr "prefix" "orig,orig,maybe_evex")
5109 596 : (set_attr "mode" "TI")])
5110 596 :
5111 596 : (define_expand "<insn>v2qiv2si2"
5112 : [(set (match_operand:V2SI 0 "register_operand")
5113 : (any_extend:V2SI
5114 : (match_operand:V2QI 1 "register_operand")))]
5115 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5116 38 : {
5117 38 : rtx op1 = force_reg (V2QImode, operands[1]);
5118 38 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5119 38 : emit_insn (gen_sse4_1_<code>v2qiv2si2 (operands[0], op1));
5120 38 : DONE;
5121 : })
5122 :
5123 : (define_insn "sse4_1_<code>v2qiv2hi2"
5124 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yw")
5125 : (any_extend:V2HI
5126 : (vec_select:V2QI
5127 : (match_operand:V4QI 1 "register_operand" "Yr,*x,Yw")
5128 : (parallel [(const_int 0) (const_int 1)]))))]
5129 112 : "TARGET_SSE4_1"
5130 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5131 : [(set_attr "isa" "noavx,noavx,avx")
5132 : (set_attr "type" "ssemov")
5133 576 : (set_attr "prefix_extra" "1")
5134 : (set_attr "prefix" "orig,orig,maybe_evex")
5135 576 : (set_attr "mode" "TI")])
5136 576 :
5137 109714 : (define_expand "<insn>v2qiv2hi2"
5138 109138 : [(set (match_operand:V2HI 0 "register_operand")
5139 3 : (any_extend:V2HI
5140 109141 : (match_operand:V2QI 1 "register_operand")))]
5141 : "TARGET_SSE2"
5142 63 : {
5143 63 : if (!TARGET_SSE4_1)
5144 3 : {
5145 54 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5146 54 : DONE;
5147 31073 : }
5148 :
5149 6 : rtx op1 = force_reg (V2QImode, operands[1]);
5150 6 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5151 31079 : emit_insn (gen_sse4_1_<code>v2qiv2hi2 (operands[0], op1));
5152 31079 : DONE;
5153 31073 : })
5154 31073 :
5155 31073 : (define_expand "trunc<mode><mmxhalfmodelower>2"
5156 31073 : [(set (match_operand:<mmxhalfmode> 0 "register_operand")
5157 : (truncate:<mmxhalfmode>
5158 19713 : (match_operand:VI2_32_64 1 "register_operand")))]
5159 19713 : "TARGET_AVX2"
5160 19736 : {
5161 23 : if (TARGET_AVX512VL && TARGET_AVX512BW)
5162 5626 : emit_insn (gen_avx512vl_trunc<mode><mmxhalfmodelower>2 (operands[0], operands[1]));
5163 5605 : else
5164 2 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <mmxbytemode>mode);
5165 3131 : DONE;
5166 2508 : })
5167 3020 :
5168 2216 : (define_insn "avx512vl_trunc<mode><mmxhalfmodelower>2"
5169 4724 : [(set (match_operand:<mmxhalfmode> 0 "register_operand" "=v")
5170 : (truncate:<mmxhalfmode>
5171 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
5172 175 : "TARGET_AVX512VL && TARGET_AVX512BW"
5173 : "vpmovwb\t{%1, %0|%0, %1}"
5174 : [(set_attr "type" "ssemov")
5175 : (set_attr "prefix" "evex")
5176 73 : (set_attr "mode" "TI")])
5177 73 :
5178 264 : (define_mode_iterator V2QI_V2HI [V2QI V2HI])
5179 : (define_mode_attr v2qi_quad_v2hi_double
5180 191 : [(V2QI "V8QI") (V2HI "V4HI")])
5181 191 : (define_expand "truncv2si<mode>2"
5182 191 : [(set (match_operand:V2QI_V2HI 0 "register_operand")
5183 : (truncate:V2QI_V2HI
5184 : (match_operand:V2SI 1 "register_operand")))]
5185 : "TARGET_AVX2 && TARGET_MMX_WITH_SSE"
5186 47 : {
5187 47 : if (TARGET_AVX512VL)
5188 15 : emit_insn (gen_avx512vl_truncv2si<mode>2 (operands[0], operands[1]));
5189 : else
5190 32 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <v2qi_quad_v2hi_double>mode);
5191 47 : DONE;
5192 : })
5193 :
5194 : (define_insn "avx512vl_truncv2si<mode>2"
5195 : [(set (match_operand:V2QI_V2HI 0 "register_operand" "=v")
5196 : (truncate:V2QI_V2HI
5197 : (match_operand:V2SI 1 "register_operand" "v")))]
5198 115 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
5199 : "vpmovd<mmxvecsize>\t{%1, %0|%0, %1}"
5200 40 : [(set_attr "type" "ssemov")
5201 15 : (set_attr "prefix" "evex")
5202 40 : (set_attr "mode" "TI")])
5203 :
5204 289 : ;; Pack/unpack vector modes
5205 : (define_mode_attr mmxpackmode
5206 343 : [(V4HI "V8QI") (V2SI "V4HI")])
5207 309 :
5208 343 : (define_expand "vec_pack_trunc_<mode>"
5209 : [(match_operand:<mmxpackmode> 0 "register_operand")
5210 : (match_operand:MMXMODE24 1 "register_operand")
5211 : (match_operand:MMXMODE24 2 "register_operand")]
5212 : "TARGET_MMX_WITH_SSE"
5213 785 : {
5214 785 : rtx op1 = gen_lowpart (<mmxpackmode>mode, operands[1]);
5215 785 : rtx op2 = gen_lowpart (<mmxpackmode>mode, operands[2]);
5216 785 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5217 785 : DONE;
5218 : })
5219 :
5220 : (define_expand "vec_pack_trunc_v2hi"
5221 : [(match_operand:V4QI 0 "register_operand")
5222 : (match_operand:V2HI 1 "register_operand")
5223 : (match_operand:V2HI 2 "register_operand")]
5224 : "TARGET_SSE2"
5225 24 : {
5226 24 : rtx op1 = gen_lowpart (V4QImode, operands[1]);
5227 24 : rtx op2 = gen_lowpart (V4QImode, operands[2]);
5228 24 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5229 24 : DONE;
5230 10 : })
5231 3 :
5232 10 : (define_mode_attr mmxunpackmode
5233 13 : [(V8QI "V4HI") (V4HI "V2SI")])
5234 10 :
5235 3 : (define_expand "vec_unpacks_lo_<mode>"
5236 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5237 : (match_operand:MMXMODE12 1 "register_operand")]
5238 : "TARGET_MMX_WITH_SSE"
5239 596 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5240 :
5241 : (define_expand "vec_unpacks_hi_<mode>"
5242 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5243 0 : (match_operand:MMXMODE12 1 "register_operand")]
5244 : "TARGET_MMX_WITH_SSE"
5245 600 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5246 0 :
5247 0 : (define_expand "vec_unpacku_lo_<mode>"
5248 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5249 : (match_operand:MMXMODE12 1 "register_operand")]
5250 : "TARGET_MMX_WITH_SSE"
5251 894 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5252 :
5253 448 : (define_expand "vec_unpacku_hi_<mode>"
5254 448 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5255 448 : (match_operand:MMXMODE12 1 "register_operand")]
5256 : "TARGET_MMX_WITH_SSE"
5257 448 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5258 :
5259 0 : (define_expand "vec_unpacks_lo_v4qi"
5260 0 : [(match_operand:V2HI 0 "register_operand")
5261 0 : (match_operand:V4QI 1 "register_operand")]
5262 : "TARGET_SSE2"
5263 75 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5264 0 :
5265 75 : (define_expand "vec_unpacks_hi_v4qi"
5266 75 : [(match_operand:V2HI 0 "register_operand")
5267 75 : (match_operand:V4QI 1 "register_operand")]
5268 0 : "TARGET_SSE2"
5269 189 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5270 55 :
5271 189 : (define_expand "vec_unpacku_lo_v4qi"
5272 244 : [(match_operand:V2HI 0 "register_operand")
5273 189 : (match_operand:V4QI 1 "register_operand")]
5274 55 : "TARGET_SSE2"
5275 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5276 1777 :
5277 : (define_expand "vec_unpacku_hi_v4qi"
5278 1777 : [(match_operand:V2HI 0 "register_operand")
5279 0 : (match_operand:V4QI 1 "register_operand")]
5280 1777 : "TARGET_SSE2"
5281 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5282 199 :
5283 : (define_insn "*mmx_pinsrd"
5284 199 : [(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
5285 0 : (vec_merge:V2SI
5286 199 : (vec_duplicate:V2SI
5287 : (match_operand:SI 2 "nonimmediate_operand" "jrjm,rm"))
5288 40 : (match_operand:V2SI 1 "register_operand" "0,Yv")
5289 : (match_operand:SI 3 "const_int_operand")))]
5290 240 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5291 200 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5292 240 : < GET_MODE_NUNITS (V2SImode))"
5293 26 : {
5294 52 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5295 26 : switch (which_alternative)
5296 21 : {
5297 21 : case 1:
5298 0 : return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5299 0 : case 0:
5300 21 : return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
5301 0 : default:
5302 0 : gcc_unreachable ();
5303 : }
5304 : }
5305 : [(set_attr "isa" "noavx,avx")
5306 : (set_attr "addr" "gpr16,*")
5307 : (set_attr "prefix_extra" "1")
5308 0 : (set_attr "type" "sselog")
5309 : (set_attr "length_immediate" "1")
5310 : (set_attr "prefix" "orig,vex")
5311 : (set_attr "mode" "TI")])
5312 :
5313 : (define_insn "*mmx_pinsrw"
5314 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,x,YW,&x")
5315 : (vec_merge:V4FI_64
5316 : (vec_duplicate:V4FI_64
5317 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,rm,x"))
5318 : (match_operand:V4FI_64 1 "register_operand" "0,0,YW,x")
5319 : (match_operand:SI 3 "const_int_operand")))]
5320 63 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5321 366 : && (TARGET_SSE || TARGET_3DNOW_A)
5322 366 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5323 15 : < GET_MODE_NUNITS (V4HImode))"
5324 39 : {
5325 39 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5326 39 : switch (which_alternative)
5327 693 : {
5328 693 : case 3:
5329 : return "#";
5330 16 : case 2:
5331 1060 : if (MEM_P (operands[2]))
5332 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5333 : else
5334 16 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5335 23 : case 1:
5336 23 : case 0:
5337 23 : if (MEM_P (operands[2]))
5338 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
5339 : else
5340 13 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
5341 0 : default:
5342 0 : gcc_unreachable ();
5343 : }
5344 : }
5345 : [(set_attr "isa" "*,sse2_noavx,avx,sse4")
5346 : (set_attr "mmx_isa" "native,*,*,*")
5347 : (set_attr "type" "mmxcvt,sselog,sselog,sselog")
5348 44 : (set_attr "length_immediate" "1")
5349 : (set_attr "mode" "DI,TI,TI,TI")])
5350 :
5351 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
5352 : (define_split
5353 : [(set (match_operand:V4FI_64 0 "sse_reg_operand")
5354 : (vec_merge:V4FI_64
5355 : (vec_duplicate:V4FI_64
5356 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
5357 : (match_operand:V4FI_64 1 "sse_reg_operand")
5358 : (match_operand:SI 3 "const_int_operand")))]
5359 3 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 && reload_completed
5360 3 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5361 3 : < GET_MODE_NUNITS (<MODE>mode))"
5362 : [(set (match_dup 0)
5363 3 : (vec_duplicate:V4FI_64 (match_dup 2)))
5364 : (set (match_dup 0)
5365 115 : (vec_merge:V4FI_64 (match_dup 1) (match_dup 0) (match_dup 3)))]
5366 118 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0xf);")
5367 :
5368 : (define_insn "*mmx_pinsrb"
5369 118 : [(set (match_operand:V8QI 0 "register_operand" "=x,YW")
5370 : (vec_merge:V8QI
5371 : (vec_duplicate:V8QI
5372 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
5373 : (match_operand:V8QI 1 "register_operand" "0,YW")
5374 3 : (match_operand:SI 3 "const_int_operand")))]
5375 74 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5376 74 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5377 74 : < GET_MODE_NUNITS (V8QImode))"
5378 5 : {
5379 26573 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5380 5 : switch (which_alternative)
5381 26570 : {
5382 26575 : case 1:
5383 26568 : if (MEM_P (operands[2]))
5384 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5385 7 : else
5386 5 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5387 0 : case 0:
5388 0 : if (MEM_P (operands[2]))
5389 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
5390 : else
5391 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
5392 0 : default:
5393 0 : gcc_unreachable ();
5394 : }
5395 : }
5396 : [(set_attr "isa" "noavx,avx")
5397 : (set_attr "type" "sselog")
5398 : (set_attr "addr" "gpr16,*")
5399 : (set_attr "prefix_extra" "1")
5400 : (set_attr "length_immediate" "1")
5401 : (set_attr "prefix" "orig,vex")
5402 : (set_attr "mode" "TI")])
5403 :
5404 : (define_insn "*mmx_pextrw"
5405 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,jm,m")
5406 16 : (vec_select:HI
5407 : (match_operand:V4HI 1 "register_operand" "y,YW,YW,YW")
5408 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5409 2252 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5410 2252 : && (TARGET_SSE || TARGET_3DNOW_A)"
5411 : "@
5412 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5413 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
5414 541 : pextrw\t{%2, %1, %0|%0, %1, %2}
5415 541 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
5416 529 : [(set_attr "isa" "*,sse2,sse4_noavx,avx")
5417 541 : (set_attr "addr" "*,*,gpr16,*")
5418 : (set_attr "mmx_isa" "native,*,*,*")
5419 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
5420 : (set_attr "length_immediate" "1")
5421 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
5422 : (set_attr "mode" "DI,TI,TI,TI")])
5423 :
5424 : (define_insn "*mmx_pextrw<mode>"
5425 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,?r,jm,m,x,Yw")
5426 : (vec_select:<mmxscalarmode>
5427 : (match_operand:V4F_64 1 "register_operand" "y,YW,YW,YW,0,YW")
5428 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5429 98 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5430 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5431 26 : {
5432 16 : switch (which_alternative)
5433 : {
5434 26 : case 0:
5435 26 : case 1:
5436 24 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
5437 30 : case 2:
5438 4 : case 3:
5439 4 : return "%vpextrw\t{%2, %1, %0|%0, %1, %2}";
5440 4 : case 4:
5441 4 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5442 4 : return "psrldq\t{%2, %0|%0, %2}";
5443 8 : case 5:
5444 8 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5445 8 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
5446 :
5447 0 : default:
5448 0 : gcc_unreachable ();
5449 : }
5450 : }
5451 : [(set_attr "isa" "*,sse2,sse4_noavx,avx,noavx,avx")
5452 : (set_attr "addr" "*,*,gpr16,*,*,*")
5453 : (set_attr "mmx_isa" "native,*,*,*,*,*")
5454 0 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
5455 : (set_attr "length_immediate" "1")
5456 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
5457 : (set_attr "mode" "DI,TI,TI,TI,TI,TI")])
5458 :
5459 : (define_insn "*mmx_pextrw_zext"
5460 : [(set (match_operand:SWI48 0 "register_operand" "=r,r")
5461 : (zero_extend:SWI48
5462 : (vec_select:HI
5463 : (match_operand:V4HI 1 "register_operand" "y,YW")
5464 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
5465 7047 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5466 7047 : && (TARGET_SSE || TARGET_3DNOW_A)"
5467 : "@
5468 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5469 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
5470 4888 : [(set_attr "isa" "*,sse2")
5471 4888 : (set_attr "mmx_isa" "native,*")
5472 : (set_attr "type" "mmxcvt,sselog1")
5473 : (set_attr "length_immediate" "1")
5474 : (set_attr "prefix" "orig,maybe_vex")
5475 : (set_attr "mode" "DI,TI")])
5476 :
5477 : (define_insn "*mmx_pextrb"
5478 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
5479 : (vec_select:QI
5480 : (match_operand:V8QI 1 "register_operand" "YW,YW,YW,YW")
5481 0 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))]
5482 3248 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5483 : "@
5484 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
5485 : pextrb\t{%2, %1, %0|%0, %1, %2}
5486 152 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
5487 152 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
5488 109 : [(set_attr "isa" "noavx,noavx,avx,avx")
5489 152 : (set_attr "addr" "*,gpr16,*,*")
5490 : (set_attr "type" "sselog1")
5491 : (set_attr "prefix_extra" "1")
5492 : (set_attr "length_immediate" "1")
5493 : (set_attr "prefix" "maybe_vex")
5494 : (set_attr "mode" "TI")])
5495 :
5496 : (define_insn "*mmx_pextrb_zext"
5497 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
5498 : (zero_extend:SWI248
5499 : (vec_select:QI
5500 : (match_operand:V8QI 1 "register_operand" "YW,YW")
5501 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))]
5502 4935 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5503 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
5504 : [(set_attr "isa" "noavx,avx")
5505 : (set_attr "type" "sselog1")
5506 386 : (set_attr "prefix_extra" "1")
5507 386 : (set_attr "length_immediate" "1")
5508 : (set_attr "prefix" "maybe_vex")
5509 : (set_attr "mode" "TI")])
5510 :
5511 : (define_insn "mmx_pshufbv8qi3"
5512 : [(set (match_operand:V8QI 0 "register_operand" "=x,Yw")
5513 : (unspec:V8QI
5514 : [(match_operand:V8QI 1 "register_operand" "0,Yw")
5515 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5516 : UNSPEC_PSHUFB))]
5517 2662 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
5518 281 : "@
5519 : pshufb\t{%2, %0|%0, %2}
5520 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5521 2949 : [(set_attr "isa" "noavx,avx")
5522 2949 : (set_attr "addr" "gpr16,*")
5523 2941 : (set_attr "type" "sselog1")
5524 2941 : (set_attr "prefix_extra" "1")
5525 2949 : (set_attr "prefix" "orig,maybe_evex")
5526 : (set_attr "btver2_decode" "vector")
5527 : (set_attr "mode" "TI")])
5528 :
5529 : (define_insn "mmx_pshufbv4qi3"
5530 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
5531 : (unspec:V4QI
5532 : [(match_operand:V4QI 1 "register_operand" "0,Yw")
5533 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5534 : UNSPEC_PSHUFB))]
5535 2743 : "TARGET_SSSE3"
5536 206 : "@
5537 : pshufb\t{%2, %0|%0, %2}
5538 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5539 : [(set_attr "isa" "noavx,avx")
5540 : (set_attr "addr" "gpr16,*")
5541 : (set_attr "type" "sselog1")
5542 : (set_attr "prefix_extra" "1")
5543 51448 : (set_attr "prefix" "orig,maybe_evex")
5544 51448 : (set_attr "btver2_decode" "vector")
5545 : (set_attr "mode" "TI")])
5546 11188 :
5547 11188 : (define_expand "mmx_pshufw"
5548 11188 : [(match_operand:V4HI 0 "register_operand")
5549 : (match_operand:V4HI 1 "register_mmxmem_operand")
5550 11104 : (match_operand:SI 2 "const_int_operand")]
5551 11104 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5552 11104 : && (TARGET_SSE || TARGET_3DNOW_A)"
5553 75 : {
5554 9458 : int mask = INTVAL (operands[2]);
5555 9458 : emit_insn (gen_mmx_pshufwv4hi_1 (operands[0], operands[1],
5556 9383 : GEN_INT ((mask >> 0) & 3),
5557 14907 : GEN_INT ((mask >> 2) & 3),
5558 75 : GEN_INT ((mask >> 4) & 3),
5559 75 : GEN_INT ((mask >> 6) & 3)));
5560 75 : DONE;
5561 : })
5562 :
5563 : (define_insn "mmx_pshufw<mode>_1"
5564 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,Yw")
5565 : (vec_select:V4FI_64
5566 : (match_operand:V4FI_64 1 "register_mmxmem_operand" "ym,Yw")
5567 : (parallel [(match_operand 2 "const_0_to_3_operand")
5568 : (match_operand 3 "const_0_to_3_operand")
5569 : (match_operand 4 "const_0_to_3_operand")
5570 : (match_operand 5 "const_0_to_3_operand")])))]
5571 417 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5572 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5573 6454 : {
5574 1156 : int mask = 0;
5575 1156 : mask |= INTVAL (operands[2]) << 0;
5576 13279 : mask |= INTVAL (operands[3]) << 2;
5577 13279 : mask |= INTVAL (operands[4]) << 4;
5578 10187 : mask |= INTVAL (operands[5]) << 6;
5579 9031 : operands[2] = GEN_INT (mask);
5580 19396 :
5581 1156 : switch (which_alternative)
5582 : {
5583 : case 0:
5584 : return "pshufw\t{%2, %1, %0|%0, %1, %2}";
5585 1156 : case 1:
5586 2827841 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
5587 0 : default:
5588 0 : gcc_unreachable ();
5589 : }
5590 2826685 : }
5591 2826685 : [(set_attr "isa" "*,sse2")
5592 2826685 : (set_attr "mmx_isa" "native,*")
5593 2826685 : (set_attr "type" "mmxcvt,sselog1")
5594 2828568 : (set_attr "length_immediate" "1")
5595 2826685 : (set_attr "mode" "DI,TI")])
5596 2826685 :
5597 2826685 : (define_insn "*mmx_pshufd_1"
5598 2826685 : [(set (match_operand:V2SI 0 "register_operand" "=Yv")
5599 2826685 : (vec_select:V2SI
5600 : (match_operand:V2SI 1 "register_operand" "Yv")
5601 380039 : (parallel [(match_operand 2 "const_0_to_1_operand")
5602 380039 : (match_operand 3 "const_0_to_1_operand")])))]
5603 9252 : "TARGET_MMX_WITH_SSE"
5604 965727 : {
5605 965727 : int mask = 0;
5606 965727 : mask |= INTVAL (operands[2]) << 0;
5607 965734 : mask |= INTVAL (operands[3]) << 2;
5608 734 : mask |= 2 << 4;
5609 734 : mask |= 3 << 6;
5610 965734 : operands[2] = GEN_INT (mask);
5611 7 :
5612 152649 : return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
5613 151922 : }
5614 151863 : [(set_attr "type" "sselog1")
5615 268390 : (set_attr "prefix_data16" "1")
5616 : (set_attr "length_immediate" "1")
5617 : (set_attr "mode" "TI")])
5618 :
5619 : (define_insn "*mmx_pblendw64"
5620 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yr,*x,x")
5621 : (vec_merge:V4FI_64
5622 : (match_operand:V4FI_64 2 "register_operand" "Yr,*x,x")
5623 : (match_operand:V4FI_64 1 "register_operand" "0,0,x")
5624 : (match_operand:SI 3 "const_0_to_15_operand")))]
5625 2909 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5626 : "@
5627 : pblendw\t{%3, %2, %0|%0, %2, %3}
5628 : pblendw\t{%3, %2, %0|%0, %2, %3}
5629 6114 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5630 6114 : [(set_attr "isa" "noavx,noavx,avx")
5631 : (set_attr "type" "ssemov")
5632 6114 : (set_attr "prefix_extra" "1")
5633 : (set_attr "length_immediate" "1")
5634 : (set_attr "prefix" "orig,orig,vex")
5635 : (set_attr "mode" "TI")])
5636 :
5637 : (define_insn "*mmx_pblendw32"
5638 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yr,*x,x")
5639 : (vec_merge:V2FI_32
5640 : (match_operand:V2FI_32 2 "register_operand" "Yr,*x,x")
5641 : (match_operand:V2FI_32 1 "register_operand" "0,0,x")
5642 : (match_operand:SI 3 "const_0_to_7_operand")))]
5643 1 : "TARGET_SSE4_1"
5644 : "@
5645 : pblendw\t{%3, %2, %0|%0, %2, %3}
5646 : pblendw\t{%3, %2, %0|%0, %2, %3}
5647 60 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5648 60 : [(set_attr "isa" "noavx,noavx,avx")
5649 : (set_attr "type" "ssemov")
5650 168718 : (set_attr "prefix_extra" "1")
5651 : (set_attr "length_immediate" "1")
5652 65004 : (set_attr "prefix" "orig,orig,vex")
5653 65004 : (set_attr "mode" "TI")])
5654 :
5655 2609 : ;; Optimize V2SImode load from memory, swapping the elements and
5656 2609 : ;; storing back into the memory into DImode rotate of the memory by 32.
5657 : (define_split
5658 2609 : [(set (match_operand:V2SI 0 "memory_operand")
5659 : (vec_select:V2SI (match_dup 0)
5660 : (parallel [(const_int 1) (const_int 0)])))]
5661 55 : "TARGET_64BIT && (TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())"
5662 55 : [(set (match_dup 0)
5663 : (rotate:DI (match_dup 0) (const_int 32)))]
5664 55 : "operands[0] = adjust_address (operands[0], DImode, 0);")
5665 :
5666 : (define_insn "mmx_pswapdv2si2"
5667 55 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5668 : (vec_select:V2SI
5669 436057 : (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")
5670 : (parallel [(const_int 1) (const_int 0)])))]
5671 258403 : "TARGET_3DNOW_A"
5672 410384 : "@
5673 193707 : pswapd\t{%1, %0|%0, %1}
5674 : %vpshufd\t{$0xe1, %1, %0|%0, %1, 0xe1}";
5675 1208669 : [(set_attr "isa" "*,sse2")
5676 1136429 : (set_attr "mmx_isa" "native,*")
5677 1136412 : (set_attr "type" "mmxcvt,sselog1")
5678 138658 : (set_attr "prefix_extra" "1,*")
5679 1103217 : (set_attr "length_immediate" "*,1")
5680 28258 : (set_attr "mode" "DI,TI")])
5681 818676 :
5682 790435 : (define_insn "*vec_dupv4hi"
5683 3 : [(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
5684 96956 : (vec_duplicate:V4HI
5685 96956 : (truncate:HI
5686 : (match_operand:SI 1 "register_operand" "0,Yw"))))]
5687 9689 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5688 9605 : && (TARGET_SSE || TARGET_3DNOW_A)"
5689 : "@
5690 : pshufw\t{$0, %0, %0|%0, %0, 0}
5691 : %vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5692 210 : [(set_attr "isa" "*,sse2")
5693 210 : (set_attr "mmx_isa" "native,*")
5694 210 : (set_attr "type" "mmxcvt,sselog1")
5695 210 : (set_attr "length_immediate" "1")
5696 : (set_attr "mode" "DI,TI")])
5697 :
5698 : (define_insn "*vec_dup<mode>"
5699 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yw")
5700 : (vec_duplicate:V4FI_64
5701 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
5702 32 : "TARGET_MMX_WITH_SSE"
5703 77 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5704 : [(set_attr "isa" "sse2")
5705 : (set_attr "type" "sselog1")
5706 14289 : (set_attr "length_immediate" "1")
5707 14289 : (set_attr "mode" "TI")])
5708 13335 :
5709 13335 : (define_insn "*vec_dupv2si"
5710 17773 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5711 : (vec_duplicate:V2SI
5712 : (match_operand:SI 1 "register_operand" "0,Yv")))]
5713 10183 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5714 888 : "@
5715 : punpckldq\t%0, %0
5716 : %vpshufd\t{$0xe0, %1, %0|%0, %1, 0xe0}"
5717 23 : [(set_attr "isa" "*,sse2")
5718 23 : (set_attr "mmx_isa" "native,*")
5719 18 : (set_attr "type" "mmxcvt,sselog1")
5720 18 : (set_attr "prefix_data16" "*,1")
5721 23 : (set_attr "length_immediate" "*,1")
5722 : (set_attr "mode" "DI,TI")])
5723 :
5724 : (define_insn "*mmx_concatv2si"
5725 : [(set (match_operand:V2SI 0 "register_operand" "=y,y")
5726 : (vec_concat:V2SI
5727 : (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
5728 : (match_operand:SI 2 "nonimm_or_0_operand" "ym,C")))]
5729 391074 : "TARGET_MMX && !TARGET_SSE"
5730 : "@
5731 391074 : punpckldq\t{%2, %0|%0, %2}
5732 : movd\t{%1, %0|%0, %1}"
5733 : [(set_attr "type" "mmxcvt,mmxmov")
5734 : (set_attr "mode" "DI")])
5735 :
5736 : (define_expand "vec_setv2si"
5737 : [(match_operand:V2SI 0 "register_operand")
5738 : (match_operand:SI 1 "register_operand")
5739 : (match_operand 2 "vec_setm_mmx_operand")]
5740 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5741 189 : {
5742 189 : if (CONST_INT_P (operands[2]))
5743 187 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5744 187 : INTVAL (operands[2]));
5745 : else
5746 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5747 189 : DONE;
5748 : })
5749 :
5750 : ;; Avoid combining registers from different units in a single alternative,
5751 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5752 : (define_insn_and_split "*vec_extractv2si_0"
5753 : [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r,r")
5754 : (vec_select:SI
5755 : (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m,x")
5756 : (parallel [(const_int 0)])))]
5757 23461 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5758 23461 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5759 : "#"
5760 3617 : "&& reload_completed"
5761 1777 : [(set (match_dup 0) (match_dup 1))]
5762 313091 : "operands[1] = gen_lowpart (SImode, operands[1]);"
5763 311314 : [(set_attr "isa" "*,*,*,*,*,sse2")
5764 423642 : (set_attr "mmx_isa" "*,*,native,native,*,*")
5765 114105 : (set (attr "preferred_for_speed")
5766 112328 : (cond [(eq_attr "alternative" "5")
5767 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5768 1777 : ]
5769 : (symbol_ref "true")))])
5770 :
5771 : (define_insn "*vec_extractv2si_0_zext_sse4"
5772 : [(set (match_operand:DI 0 "register_operand" "=r,x")
5773 7 : (zero_extend:DI
5774 : (vec_select:SI
5775 7 : (match_operand:V2SI 1 "register_operand" "x,x")
5776 7 : (parallel [(const_int 0)]))))]
5777 859 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE4_1"
5778 : "#"
5779 852 : [(set_attr "isa" "x64,*")
5780 : (set (attr "preferred_for_speed")
5781 : (cond [(eq_attr "alternative" "0")
5782 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5783 : ]
5784 : (symbol_ref "true")))])
5785 :
5786 : (define_insn "*vec_extractv2si_0_zext"
5787 : [(set (match_operand:DI 0 "register_operand" "=r")
5788 : (zero_extend:DI
5789 : (vec_select:SI
5790 : (match_operand:V2SI 1 "register_operand" "x")
5791 : (parallel [(const_int 0)]))))]
5792 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5793 852 : && TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC"
5794 : "#")
5795 :
5796 : (define_split
5797 : [(set (match_operand:DI 0 "register_operand")
5798 3114 : (zero_extend:DI
5799 3114 : (vec_select:SI
5800 : (match_operand:V2SI 1 "register_operand")
5801 2628 : (parallel [(const_int 0)]))))]
5802 398 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5803 398 : && TARGET_SSE2 && reload_completed"
5804 199 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5805 199 : "operands[1] = gen_lowpart (SImode, operands[1]);")
5806 :
5807 1360 : ;; Avoid combining registers from different units in a single alternative,
5808 1559 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5809 1360 : (define_insn "*vec_extractv2si_1"
5810 : [(set (match_operand:SI 0 "nonimmediate_operand" "=y,jrjm,rm,x,x,y,x,r")
5811 199 : (vec_select:SI
5812 : (match_operand:V2SI 1 "nonimmediate_operand" " 0,x, x ,x,0,o,o,o")
5813 : (parallel [(const_int 1)])))]
5814 14531 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5815 14531 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5816 0 : "@
5817 : punpckhdq\t%0, %0
5818 0 : pextrd\t{$1, %1, %0|%0, %1, 1}
5819 169103 : vpextrd\t{$1, %1, %0|%0, %1, 1}
5820 169103 : %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
5821 162875 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
5822 162875 : #
5823 329941 : #
5824 : #"
5825 : [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*")
5826 : (set (attr "addr")
5827 : (if_then_else (eq_attr "alternative" "1")
5828 : (const_string "gpr16")
5829 : (const_string "*")))
5830 : (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
5831 : (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
5832 : (set (attr "length_immediate")
5833 : (if_then_else (eq_attr "alternative" "1,2,3,4")
5834 : (const_string "1")
5835 : (const_string "*")))
5836 : (set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,orig,orig,orig,orig")
5837 : (set_attr "mode" "DI,TI,TI,TI,V4SF,SI,SI,SI")])
5838 :
5839 : (define_split
5840 : [(set (match_operand:SI 0 "register_operand")
5841 : (vec_select:SI
5842 : (match_operand:V2SI 1 "memory_operand")
5843 : (parallel [(const_int 1)])))]
5844 40 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
5845 40 : [(set (match_dup 0) (match_dup 1))]
5846 40 : "operands[1] = adjust_address (operands[1], SImode, 4);")
5847 :
5848 4192 : (define_insn "*vec_extractv2si_1_zext"
5849 4232 : [(set (match_operand:DI 0 "register_operand" "=jr,r")
5850 2979 : (zero_extend:DI
5851 2979 : (vec_select:SI
5852 4265 : (match_operand:V2SI 1 "register_operand" "x,x")
5853 : (parallel [(const_int 1)]))))]
5854 974 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5855 974 : && TARGET_64BIT && TARGET_SSE4_1"
5856 : "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
5857 826 : [(set_attr "isa" "noavx,avx")
5858 : (set_attr "type" "sselog1")
5859 826 : (set_attr "prefix_extra" "1")
5860 826 : (set_attr "length_immediate" "1")
5861 826 : (set_attr "prefix" "maybe_vex")
5862 4132 : (set_attr "mode" "TI")])
5863 4132 :
5864 : (define_insn_and_split "*vec_extractv2si_zext_mem"
5865 1457 : [(set (match_operand:DI 0 "register_operand" "=y,x,r")
5866 1457 : (zero_extend:DI
5867 2 : (vec_select:SI
5868 1459 : (match_operand:V2SI 1 "memory_operand" "o,o,o")
5869 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
5870 2 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_64BIT"
5871 1455 : "#"
5872 0 : "&& reload_completed"
5873 199 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5874 2648 : {
5875 2648 : operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
5876 740 : }
5877 3388 : [(set_attr "isa" "*,sse2,*")
5878 2648 : (set_attr "mmx_isa" "native,*,*")])
5879 740 :
5880 : (define_expand "vec_extractv2sisi"
5881 : [(match_operand:SI 0 "register_operand")
5882 0 : (match_operand:V2SI 1 "register_operand")
5883 : (match_operand 2 "const_int_operand")]
5884 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5885 8281 : {
5886 8281 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5887 11739 : operands[1], INTVAL (operands[2]));
5888 8281 : DONE;
5889 3458 : })
5890 3458 :
5891 3458 : (define_expand "vec_initv2sisi"
5892 : [(match_operand:V2SI 0 "register_operand")
5893 : (match_operand 1)]
5894 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5895 18280 : {
5896 34025 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5897 : operands[1]);
5898 18280 : DONE;
5899 : })
5900 :
5901 2 : (define_expand "vec_set<mode>"
5902 : [(match_operand:V4FI_64 0 "register_operand")
5903 2 : (match_operand:<mmxscalarmode> 1 "register_operand")
5904 2 : (match_operand 2 "vec_setm_mmx_operand")]
5905 2 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5906 9 : {
5907 9 : if (CONST_INT_P (operands[2]))
5908 10 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5909 6 : INTVAL (operands[2]));
5910 : else
5911 7 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5912 9 : DONE;
5913 4 : })
5914 4 :
5915 4 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
5916 : [(match_operand:<mmxscalarmode> 0 "register_operand")
5917 : (match_operand:V4FI_64 1 "register_operand")
5918 : (match_operand 2 "const_int_operand")]
5919 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5920 843 : {
5921 871 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5922 843 : operands[1], INTVAL (operands[2]));
5923 843 : DONE;
5924 : })
5925 976 :
5926 : (define_expand "vec_initv4hihi"
5927 976 : [(match_operand:V4HI 0 "register_operand")
5928 976 : (match_operand 1)]
5929 976 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5930 3458 : {
5931 3463 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5932 : operands[1]);
5933 3458 : DONE;
5934 : })
5935 :
5936 2 : (define_expand "vec_init<mode><mmxscalarmodelower>"
5937 0 : [(match_operand:V4F_64 0 "register_operand")
5938 2 : (match_operand 1)]
5939 2 : "TARGET_MMX_WITH_SSE"
5940 23 : {
5941 21 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5942 : operands[1]);
5943 21 : DONE;
5944 : })
5945 :
5946 : (define_expand "vec_setv8qi"
5947 1 : [(match_operand:V8QI 0 "register_operand")
5948 : (match_operand:QI 1 "register_operand")
5949 1 : (match_operand 2 "vec_setm_mmx_operand")]
5950 0 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5951 3 : {
5952 2 : if (CONST_INT_P (operands[2]))
5953 0 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5954 0 : INTVAL (operands[2]));
5955 : else
5956 27 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5957 2 : DONE;
5958 25 : })
5959 25 :
5960 25 : (define_expand "vec_extractv8qiqi"
5961 0 : [(match_operand:QI 0 "register_operand")
5962 : (match_operand:V8QI 1 "register_operand")
5963 : (match_operand 2 "const_int_operand")]
5964 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5965 627 : {
5966 627 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5967 627 : operands[1], INTVAL (operands[2]));
5968 627 : DONE;
5969 : })
5970 0 :
5971 : (define_expand "vec_initv8qiqi"
5972 0 : [(match_operand:V8QI 0 "register_operand")
5973 0 : (match_operand 1)]
5974 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5975 346 : {
5976 350 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5977 : operands[1]);
5978 346 : DONE;
5979 : })
5980 :
5981 376 : (define_insn "*pinsrw"
5982 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,YW,&x")
5983 376 : (vec_merge:V2FI_32
5984 376 : (vec_duplicate:V2FI_32
5985 376 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,x"))
5986 : (match_operand:V2FI_32 1 "register_operand" "0,YW,x")
5987 : (match_operand:SI 3 "const_int_operand")))]
5988 7 : "TARGET_SSE2
5989 670 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5990 7 : < GET_MODE_NUNITS (V2HImode))"
5991 63 : {
5992 61 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5993 63 : switch (which_alternative)
5994 1147 : {
5995 1147 : case 2:
5996 : return "#";
5997 1 : case 1:
5998 1809 : if (MEM_P (operands[2]))
5999 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6000 : else
6001 0 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6002 60 : case 0:
6003 60 : if (MEM_P (operands[2]))
6004 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
6005 : else
6006 41 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6007 0 : default:
6008 0 : gcc_unreachable ();
6009 : }
6010 : }
6011 : [(set_attr "isa" "noavx,avx,sse4")
6012 : (set_attr "type" "sselog")
6013 : (set_attr "length_immediate" "1")
6014 61 : (set_attr "mode" "TI")])
6015 :
6016 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
6017 : (define_split
6018 : [(set (match_operand:V2FI_32 0 "sse_reg_operand")
6019 : (vec_merge:V2FI_32
6020 : (vec_duplicate:V2FI_32
6021 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
6022 : (match_operand:V2FI_32 1 "sse_reg_operand")
6023 : (match_operand:SI 3 "const_int_operand")))]
6024 1 : "TARGET_SSE4_1 && reload_completed
6025 1 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6026 1 : < GET_MODE_NUNITS (<MODE>mode))"
6027 : [(set (match_dup 0)
6028 1 : (vec_duplicate:V2FI_32 (match_dup 2)))
6029 : (set (match_dup 0)
6030 232 : (vec_merge:V2FI_32 (match_dup 1) (match_dup 0) (match_dup 3)))]
6031 233 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0x3);")
6032 :
6033 :
6034 233 : (define_insn "*pinsrb"
6035 : [(set (match_operand:V4QI 0 "register_operand" "=x,YW")
6036 1554318 : (vec_merge:V4QI
6037 : (vec_duplicate:V4QI
6038 1554318 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
6039 1554319 : (match_operand:V4QI 1 "register_operand" "0,YW")
6040 1554318 : (match_operand:SI 3 "const_int_operand")))]
6041 1554318 : "TARGET_SSE4_1
6042 1554318 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6043 0 : < GET_MODE_NUNITS (V4QImode))"
6044 1091199 : {
6045 1091121 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6046 93 : switch (which_alternative)
6047 93 : {
6048 93 : case 1:
6049 0 : if (MEM_P (operands[2]))
6050 15 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6051 3277 : else
6052 3277 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6053 0 : case 0:
6054 95 : if (MEM_P (operands[2]))
6055 95 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
6056 : else
6057 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6058 0 : default:
6059 0 : gcc_unreachable ();
6060 0 : }
6061 0 : }
6062 : [(set_attr "isa" "noavx,avx")
6063 : (set_attr "addr" "gpr16,*")
6064 : (set_attr "type" "sselog")
6065 : (set_attr "prefix_extra" "1")
6066 : (set_attr "length_immediate" "1")
6067 : (set_attr "prefix" "orig,vex")
6068 : (set_attr "mode" "TI")])
6069 :
6070 : (define_insn "*pextrw"
6071 3 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,jm,m")
6072 : (vec_select:HI
6073 : (match_operand:V2HI 1 "register_operand" "YW,YW,YW")
6074 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6075 529 : "TARGET_SSE2"
6076 : "@
6077 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
6078 : pextrw\t{%2, %1, %0|%0, %1, %2}
6079 18993 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
6080 18993 : [(set_attr "isa" "*,sse4_noavx,avx")
6081 18820 : (set_attr "addr" "*,gpr16,*")
6082 37813 : (set_attr "type" "sselog1")
6083 : (set_attr "length_immediate" "1")
6084 : (set_attr "prefix" "maybe_vex")
6085 : (set_attr "mode" "TI")])
6086 :
6087 : (define_insn "*pextrw<mode>"
6088 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,jm,m,x,Yw")
6089 : (vec_select:<mmxscalarmode>
6090 : (match_operand:V2F_32 1 "register_operand" "YW,YW,YW,0,YW")
6091 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6092 24 : "TARGET_SSE2"
6093 5 : {
6094 3 : switch (which_alternative)
6095 : {
6096 4362 : case 0:
6097 4362 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
6098 4215 : case 1:
6099 8577 : return "pextrw\t{%2, %1, %0|%0, %1, %2}";
6100 0 : case 2:
6101 0 : return "vpextrw\t{%2, %1, %0|%0, %1, %2}";
6102 1 : case 3:
6103 1 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6104 1 : return "psrldq\t{%2, %0|%0, %2}";
6105 2 : case 4:
6106 2 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6107 2 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
6108 :
6109 0 : default:
6110 0 : gcc_unreachable ();
6111 : }
6112 : }
6113 : [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
6114 : (set_attr "addr" "*,gpr16,*,*,*")
6115 : (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
6116 0 : (set_attr "length_immediate" "1")
6117 : (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
6118 : (set_attr "mode" "TI")])
6119 :
6120 : (define_insn "*pextrw_zext"
6121 : [(set (match_operand:SWI48 0 "register_operand" "=r")
6122 : (zero_extend:SWI48
6123 0 : (vec_select:HI
6124 : (match_operand:V2HI 1 "register_operand" "YW")
6125 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
6126 4904 : "TARGET_SSE2"
6127 : "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
6128 : [(set_attr "type" "sselog1")
6129 : (set_attr "length_immediate" "1")
6130 46611 : (set_attr "prefix" "maybe_vex")
6131 46611 : (set_attr "mode" "TI")])
6132 :
6133 : (define_insn "*pextrb"
6134 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
6135 : (vec_select:QI
6136 : (match_operand:V4QI 1 "register_operand" "YW,YW,YW,YW")
6137 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
6138 109 : "TARGET_SSE4_1"
6139 : "@
6140 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
6141 : pextrb\t{%2, %1, %0|%0, %1, %2}
6142 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
6143 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
6144 : [(set_attr "isa" "noavx,noavx,avx,avx")
6145 : (set_attr "addr" "*,gpr16,*,*")
6146 6039 : (set_attr "type" "sselog1")
6147 6039 : (set_attr "prefix_extra" "1")
6148 3199 : (set_attr "length_immediate" "1")
6149 9238 : (set_attr "prefix" "maybe_vex")
6150 : (set_attr "mode" "TI")])
6151 :
6152 : (define_insn "*pextrb_zext"
6153 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
6154 : (zero_extend:SWI248
6155 : (vec_select:QI
6156 : (match_operand:V4QI 1 "register_operand" "YW,YW")
6157 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
6158 386 : "TARGET_SSE4_1"
6159 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
6160 : [(set_attr "isa" "noavx,avx")
6161 : (set_attr "type" "sselog1")
6162 17425 : (set_attr "prefix_extra" "1")
6163 17425 : (set_attr "length_immediate" "1")
6164 : (set_attr "prefix" "maybe_vex")
6165 : (set_attr "mode" "TI")])
6166 :
6167 : (define_expand "vec_set<mode>"
6168 : [(match_operand:V2FI_32 0 "register_operand")
6169 : (match_operand:<mmxscalarmode> 1 "register_operand")
6170 : (match_operand 2 "vec_setm_sse41_operand")]
6171 : "TARGET_SSE2"
6172 27 : {
6173 27 : if (CONST_INT_P (operands[2]))
6174 24 : ix86_expand_vector_set (false, operands[0], operands[1],
6175 24 : INTVAL (operands[2]));
6176 : else
6177 3 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6178 27 : DONE;
6179 : })
6180 :
6181 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
6182 : [(match_operand:<mmxscalarmode> 0 "register_operand")
6183 : (match_operand:V2FI_32 1 "register_operand")
6184 : (match_operand 2 "const_int_operand")]
6185 : "TARGET_SSE2"
6186 379 : {
6187 379 : ix86_expand_vector_extract (false, operands[0],
6188 379 : operands[1], INTVAL (operands[2]));
6189 379 : DONE;
6190 : })
6191 302 :
6192 : (define_expand "vec_setv4qi"
6193 302 : [(match_operand:V4QI 0 "register_operand")
6194 302 : (match_operand:QI 1 "register_operand")
6195 302 : (match_operand 2 "vec_setm_mmx_operand")]
6196 : "TARGET_SSE4_1"
6197 2 : {
6198 2 : if (CONST_INT_P (operands[2]))
6199 0 : ix86_expand_vector_set (false, operands[0], operands[1],
6200 0 : INTVAL (operands[2]));
6201 : else
6202 4263 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6203 182 : DONE;
6204 4261 : })
6205 4441 :
6206 4261 : (define_expand "vec_extractv4qiqi"
6207 180 : [(match_operand:QI 0 "register_operand")
6208 : (match_operand:V4QI 1 "register_operand")
6209 : (match_operand 2 "const_int_operand")]
6210 : "TARGET_SSE4_1"
6211 78 : {
6212 78 : ix86_expand_vector_extract (false, operands[0],
6213 78 : operands[1], INTVAL (operands[2]));
6214 78 : DONE;
6215 : })
6216 22 :
6217 : (define_insn_and_split "*punpckwd"
6218 22 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,Yw")
6219 22 : (vec_select:V2FI_32
6220 22 : (vec_concat:<mmxdoublevecmode>
6221 : (match_operand:V2FI_32 1 "register_operand" "0,Yw")
6222 : (match_operand:V2FI_32 2 "register_operand" "x,Yw"))
6223 : (parallel [(match_operand 3 "const_0_to_3_operand")
6224 : (match_operand 4 "const_0_to_3_operand")])))]
6225 0 : "TARGET_SSE2"
6226 : "#"
6227 363 : "&& reload_completed"
6228 : [(set (match_dup 5)
6229 2342 : (vec_select:<mmxxmmmode>
6230 2162 : (match_dup 5)
6231 723 : (parallel [(match_dup 3) (match_dup 4)
6232 360 : (const_int 2) (const_int 3)
6233 5847 : (const_int 4) (const_int 5)
6234 5847 : (const_int 6) (const_int 7)])))]
6235 1050 : {
6236 1060 : rtx dest = lowpart_subreg (<mmxxmmmode>mode, operands[0], <MODE>mode);
6237 180 : rtx op1 = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
6238 180 : rtx op2 = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
6239 :
6240 180 : emit_insn (gen_vec_interleave_low<mmxxmmmodelower> (dest, op1, op2));
6241 :
6242 180 : static const int map[4] = { 0, 2, 1, 3 };
6243 :
6244 180 : int sel0 = map[INTVAL (operands[3])];
6245 180 : int sel1 = map[INTVAL (operands[4])];
6246 :
6247 180 : if (sel0 == 0 && sel1 == 1)
6248 69 : DONE;
6249 :
6250 111 : operands[3] = GEN_INT (sel0);
6251 111 : operands[4] = GEN_INT (sel1);
6252 111 : operands[5] = dest;
6253 : }
6254 : [(set_attr "isa" "noavx,avx")
6255 : (set_attr "type" "sselog")
6256 111 : (set_attr "mode" "TI")])
6257 :
6258 : (define_insn "*pshufw<mode>_1"
6259 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6260 : (vec_select:V2FI_32
6261 : (match_operand:V2FI_32 1 "register_operand" "Yw")
6262 111 : (parallel [(match_operand 2 "const_0_to_1_operand")
6263 : (match_operand 3 "const_0_to_1_operand")])))]
6264 0 : "TARGET_SSE2"
6265 82 : {
6266 82 : int mask = 0;
6267 96 : mask |= INTVAL (operands[2]) << 0;
6268 1840 : mask |= INTVAL (operands[3]) << 2;
6269 1854 : mask |= 2 << 4;
6270 1692 : mask |= 3 << 6;
6271 1610 : operands[2] = GEN_INT (mask);
6272 3049 :
6273 152118 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
6274 27044 : }
6275 14419 : [(set_attr "type" "sselog1")
6276 1208 : (set_attr "length_immediate" "1")
6277 1208 : (set_attr "mode" "TI")])
6278 152160 :
6279 : (define_insn "*vec_dupv2hi"
6280 : [(set (match_operand:V2HI 0 "register_operand" "=Yw")
6281 : (vec_duplicate:V2HI
6282 : (truncate:HI
6283 : (match_operand:SI 1 "register_operand" "Yw"))))]
6284 210 : "TARGET_SSE2"
6285 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6286 : [(set_attr "type" "sselog1")
6287 : (set_attr "length_immediate" "1")
6288 : (set_attr "mode" "TI")])
6289 :
6290 : (define_insn "*vec_dup<mode>"
6291 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6292 : (vec_duplicate:V2FI_32
6293 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
6294 18 : "TARGET_SSE2"
6295 52 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6296 : [(set_attr "type" "sselog1")
6297 : (set_attr "length_immediate" "1")
6298 13313428 : (set_attr "mode" "TI")])
6299 839 :
6300 792 : (define_expand "vec_init<mode><mmxscalarmodelower>"
6301 792 : [(match_operand:V2FI_32 0 "register_operand")
6302 1631 : (match_operand 1)]
6303 992 : "TARGET_SSE2"
6304 13312891 : {
6305 13313940 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6306 13313581 : operands[1]);
6307 1294 : DONE;
6308 13312589 : })
6309 992 :
6310 13312589 : (define_expand "vec_initv4qiqi"
6311 782 : [(match_operand:V2HI 0 "register_operand")
6312 782 : (match_operand 1)]
6313 782 : "TARGET_SSE2"
6314 5869 : {
6315 7120407 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6316 7116168 : operands[1]);
6317 7120389 : DONE;
6318 7116168 : })
6319 :
6320 3147961 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6321 3147954 : ;;
6322 3115140 : ;; Miscellaneous
6323 6091315 : ;;
6324 7 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6325 :
6326 : (define_expand "mmx_uavg<mode>3"
6327 : [(set (match_operand:MMXMODE12 0 "register_operand")
6328 : (truncate:MMXMODE12
6329 : (lshiftrt:<mmxdoublemode>
6330 16 : (plus:<mmxdoublemode>
6331 : (plus:<mmxdoublemode>
6332 16 : (zero_extend:<mmxdoublemode>
6333 16 : (match_operand:MMXMODE12 1 "register_mmxmem_operand"))
6334 16 : (zero_extend:<mmxdoublemode>
6335 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))
6336 : (match_dup 3))
6337 : (const_int 1))))]
6338 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6339 : && (TARGET_SSE || TARGET_3DNOW)"
6340 62 : {
6341 62 : operands[3] = CONST1_RTX(<mmxdoublemode>mode);
6342 62 : ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
6343 : })
6344 :
6345 : (define_insn "*mmx_uavgv8qi3"
6346 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
6347 62 : (truncate:V8QI
6348 : (lshiftrt:V8HI
6349 : (plus:V8HI
6350 : (plus:V8HI
6351 : (zero_extend:V8HI
6352 62 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw"))
6353 : (zero_extend:V8HI
6354 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))
6355 : (const_vector:V8HI [(const_int 1) (const_int 1)
6356 : (const_int 1) (const_int 1)
6357 343 : (const_int 1) (const_int 1)
6358 : (const_int 1) (const_int 1)]))
6359 343 : (const_int 1))))]
6360 584 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6361 584 : && (TARGET_SSE || TARGET_3DNOW)
6362 241 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6363 220 : {
6364 42 : switch (which_alternative)
6365 : {
6366 165 : case 2:
6367 165 : return "vpavgb\t{%2, %1, %0|%0, %1, %2}";
6368 181 : case 1:
6369 16 : case 0:
6370 165 : /* These two instructions have the same operation, but their encoding
6371 165 : is different. Prefer the one that is de facto standard. */
6372 16 : if (TARGET_SSE || TARGET_3DNOW_A)
6373 165 : return "pavgb\t{%2, %0|%0, %2}";
6374 165 : else
6375 0 : return "pavgusb\t{%2, %0|%0, %2}";
6376 165 : default:
6377 165 : gcc_unreachable ();
6378 : }
6379 165 : }
6380 : [(set_attr "isa" "*,sse2_noavx,avx")
6381 145 : (set_attr "mmx_isa" "native,*,*")
6382 145 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6383 : (set (attr "prefix_extra")
6384 : (if_then_else
6385 204 : (not (ior (match_test "TARGET_SSE")
6386 145 : (match_test "TARGET_3DNOW_A")))
6387 : (const_string "1")
6388 0 : (const_string "*")))
6389 : (set_attr "mode" "DI,TI,TI")])
6390 :
6391 : (define_insn "*mmx_uavgv4hi3"
6392 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
6393 : (truncate:V4HI
6394 : (lshiftrt:V4SI
6395 160614 : (plus:V4SI
6396 160614 : (plus:V4SI
6397 160614 : (zero_extend:V4SI
6398 160614 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
6399 160614 : (zero_extend:V4SI
6400 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
6401 : (const_vector:V4SI [(const_int 1) (const_int 1)
6402 : (const_int 1) (const_int 1)]))
6403 : (const_int 1))))]
6404 133 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6405 133 : && (TARGET_SSE || TARGET_3DNOW_A)
6406 133 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6407 : "@
6408 152 : pavgw\t{%2, %0|%0, %2}
6409 152 : pavgw\t{%2, %0|%0, %2}
6410 172 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6411 172 : [(set_attr "isa" "*,sse2_noavx,avx")
6412 152 : (set_attr "mmx_isa" "native,*,*")
6413 152 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6414 20 : (set_attr "mode" "DI,TI,TI")])
6415 :
6416 10415 : (define_expand "uavg<mode>3_ceil"
6417 : [(set (match_operand:MMXMODE12 0 "register_operand")
6418 : (truncate:MMXMODE12
6419 : (lshiftrt:<mmxdoublemode>
6420 : (plus:<mmxdoublemode>
6421 : (plus:<mmxdoublemode>
6422 76 : (zero_extend:<mmxdoublemode>
6423 76 : (match_operand:MMXMODE12 1 "register_operand"))
6424 76 : (zero_extend:<mmxdoublemode>
6425 76 : (match_operand:MMXMODE12 2 "register_operand")))
6426 76 : (match_dup 3))
6427 : (const_int 1))))]
6428 : "TARGET_MMX_WITH_SSE"
6429 4 : "operands[3] = CONST1_RTX(<mmxdoublemode>mode);")
6430 :
6431 : (define_insn "uavgv4qi3_ceil"
6432 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
6433 4 : (truncate:V4QI
6434 : (lshiftrt:V4HI
6435 778824 : (plus:V4HI
6436 778824 : (plus:V4HI
6437 778824 : (zero_extend:V4HI
6438 4 : (match_operand:V4QI 1 "register_operand" "%0,Yw"))
6439 : (zero_extend:V4HI
6440 : (match_operand:V4QI 2 "register_operand" "x,Yw")))
6441 : (const_vector:V4HI [(const_int 1) (const_int 1)
6442 : (const_int 1) (const_int 1)]))
6443 30 : (const_int 1))))]
6444 5 : "TARGET_SSE2"
6445 30 : "@
6446 30 : pavgb\t{%2, %0|%0, %2}
6447 30 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6448 : [(set_attr "isa" "noavx,avx")
6449 : (set_attr "type" "sseiadd")
6450 : (set_attr "mode" "TI")])
6451 :
6452 222 : (define_insn "uavgv2qi3_ceil"
6453 222 : [(set (match_operand:V2QI 0 "register_operand" "=x,Yw")
6454 222 : (truncate:V2QI
6455 : (lshiftrt:V2HI
6456 222 : (plus:V2HI
6457 222 : (plus:V2HI
6458 : (zero_extend:V2HI
6459 222 : (match_operand:V2QI 1 "register_operand" "%0,Yw"))
6460 : (zero_extend:V2HI
6461 202 : (match_operand:V2QI 2 "register_operand" "x,Yw")))
6462 202 : (const_vector:V2HI [(const_int 1) (const_int 1)]))
6463 : (const_int 1))))]
6464 110 : "TARGET_SSE2"
6465 202 : "@
6466 : pavgb\t{%2, %0|%0, %2}
6467 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6468 20 : [(set_attr "isa" "noavx,avx")
6469 20 : (set_attr "type" "sseiadd")
6470 : (set_attr "mode" "TI")])
6471 :
6472 20 : (define_insn "uavgv2hi3_ceil"
6473 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
6474 : (truncate:V2HI
6475 : (lshiftrt:V2SI
6476 : (plus:V2SI
6477 : (plus:V2SI
6478 : (zero_extend:V2SI
6479 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
6480 : (zero_extend:V2SI
6481 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
6482 : (const_vector:V2SI [(const_int 1) (const_int 1)]))
6483 : (const_int 1))))]
6484 5 : "TARGET_SSE2"
6485 : "@
6486 : pavgw\t{%2, %0|%0, %2}
6487 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6488 : [(set_attr "isa" "noavx,avx")
6489 : (set_attr "type" "sseiadd")
6490 : (set_attr "mode" "TI")])
6491 :
6492 : (define_expand "mmx_psadbw"
6493 : [(set (match_operand:V1DI 0 "register_operand")
6494 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand")
6495 : (match_operand:V8QI 2 "register_mmxmem_operand")]
6496 517 : UNSPEC_PSADBW))]
6497 517 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)"
6498 880 : "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
6499 :
6500 512 : (define_insn "*mmx_psadbw"
6501 512 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yw")
6502 875 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
6503 512 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")]
6504 512 : UNSPEC_PSADBW))]
6505 5961 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)
6506 6324 : && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
6507 4451 : "@
6508 512 : psadbw\t{%2, %0|%0, %2}
6509 512 : psadbw\t{%2, %0|%0, %2}
6510 837 : vpsadbw\t{%2, %1, %0|%0, %1, %2}"
6511 1000 : [(set_attr "isa" "*,sse2_noavx,avx")
6512 163 : (set_attr "mmx_isa" "native,*,*")
6513 836 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6514 0 : (set_attr "mode" "DI,TI,TI")])
6515 359 :
6516 338 : (define_expand "reduc_<code>_scal_<mode>"
6517 137 : [(any_logic:MMXMODE12
6518 120 : (match_operand:<mmxscalarmode> 0 "register_operand")
6519 403 : (match_operand:MMXMODE12 1 "register_operand"))]
6520 : "TARGET_MMX_WITH_SSE"
6521 41 : {
6522 41 : rtx tmp = gen_reg_rtx (<MODE>mode);
6523 41 : ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
6524 41 : emit_insn (gen_vec_extract<mode><mmxscalarmodelower> (operands[0],
6525 : tmp, const0_rtx));
6526 41 : DONE;
6527 : })
6528 :
6529 : (define_expand "reduc_<code>_scal_v4qi"
6530 : [(any_logic:V4QI
6531 : (match_operand:QI 0 "register_operand")
6532 : (match_operand:V4QI 1 "register_operand"))]
6533 : "TARGET_SSE2"
6534 30 : {
6535 30 : rtx tmp = gen_reg_rtx (V4QImode);
6536 30 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6537 30 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6538 30 : DONE;
6539 255 : })
6540 :
6541 255 : (define_expand "reduc_plus_scal_v8qi"
6542 255 : [(plus:V8QI
6543 255 : (match_operand:QI 0 "register_operand")
6544 : (match_operand:V8QI 1 "register_operand"))]
6545 : "TARGET_MMX_WITH_SSE"
6546 335 : {
6547 335 : rtx tmp = gen_reg_rtx (V8QImode);
6548 335 : emit_move_insn (tmp, CONST0_RTX (V8QImode));
6549 335 : rtx tmp2 = gen_reg_rtx (V1DImode);
6550 335 : emit_insn (gen_mmx_psadbw (tmp2, operands[1], tmp));
6551 341 : tmp2 = gen_lowpart (V8QImode, tmp2);
6552 335 : emit_insn (gen_vec_extractv8qiqi (operands[0], tmp2, const0_rtx));
6553 341 : DONE;
6554 6 : })
6555 6 :
6556 : (define_expand "reduc_plus_scal_v4hi"
6557 : [(plus:V4HI
6558 : (match_operand:HI 0 "register_operand")
6559 : (match_operand:V4HI 1 "register_operand"))]
6560 : "TARGET_MMX_WITH_SSE"
6561 243 : {
6562 243 : rtx tmp = gen_reg_rtx (V4HImode);
6563 243 : ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
6564 243 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6565 243 : DONE;
6566 5 : })
6567 :
6568 5 : (define_expand "reduc_<code>_scal_v4hi"
6569 5 : [(smaxmin:V4HI
6570 5 : (match_operand:HI 0 "register_operand")
6571 : (match_operand:V4HI 1 "register_operand"))]
6572 : "TARGET_MMX_WITH_SSE"
6573 4 : {
6574 4 : rtx tmp = gen_reg_rtx (V4HImode);
6575 4 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6576 4 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6577 4 : DONE;
6578 314 : })
6579 :
6580 314 : (define_expand "reduc_<code>_scal_v4qi"
6581 314 : [(smaxmin:V4QI
6582 314 : (match_operand:QI 0 "register_operand")
6583 : (match_operand:V4QI 1 "register_operand"))]
6584 : "TARGET_SSE4_1"
6585 4 : {
6586 4 : rtx tmp = gen_reg_rtx (V4QImode);
6587 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6588 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6589 4 : DONE;
6590 14 : })
6591 :
6592 14 : (define_expand "reduc_<code>_scal_v4hi"
6593 14 : [(umaxmin:V4HI
6594 14 : (match_operand:HI 0 "register_operand")
6595 : (match_operand:V4HI 1 "register_operand"))]
6596 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6597 6 : {
6598 6 : rtx tmp = gen_reg_rtx (V4HImode);
6599 6 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6600 6 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6601 6 : DONE;
6602 10 : })
6603 :
6604 10 : (define_expand "reduc_<code>_scal_v4qi"
6605 10 : [(umaxmin:V4QI
6606 10 : (match_operand:QI 0 "register_operand")
6607 : (match_operand:V4QI 1 "register_operand"))]
6608 : "TARGET_SSE4_1"
6609 4 : {
6610 4 : rtx tmp = gen_reg_rtx (V4QImode);
6611 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6612 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6613 4 : DONE;
6614 45 : })
6615 :
6616 45 : (define_expand "reduc_plus_scal_v4qi"
6617 45 : [(plus:V4QI
6618 45 : (match_operand:QI 0 "register_operand")
6619 : (match_operand:V4QI 1 "register_operand"))]
6620 : "TARGET_SSE2"
6621 314 : {
6622 314 : rtx op1 = gen_reg_rtx (V16QImode);
6623 314 : emit_insn (gen_vec_setv4si_0 (lowpart_subreg (V4SImode, op1, V16QImode),
6624 : CONST0_RTX (V4SImode),
6625 : lowpart_subreg (SImode,
6626 1 : operands[1],
6627 22 : V4QImode)));
6628 315 : rtx tmp = gen_reg_rtx (V16QImode);
6629 337 : emit_move_insn (tmp, CONST0_RTX (V16QImode));
6630 314 : rtx tmp2 = gen_reg_rtx (V2DImode);
6631 336 : emit_insn (gen_sse2_psadbw (tmp2, op1, tmp));
6632 314 : tmp2 = gen_lowpart (V16QImode, tmp2);
6633 315 : emit_insn (gen_vec_extractv16qiqi (operands[0], tmp2, const0_rtx));
6634 314 : DONE;
6635 : })
6636 :
6637 : (define_expand "usadv8qi"
6638 15 : [(match_operand:V2SI 0 "register_operand")
6639 : (match_operand:V8QI 1 "register_operand")
6640 15 : (match_operand:V8QI 2 "register_operand")
6641 15 : (match_operand:V2SI 3 "register_operand")]
6642 : "TARGET_MMX_WITH_SSE"
6643 5 : {
6644 5 : rtx t1 = gen_reg_rtx (V1DImode);
6645 5 : rtx t2 = gen_reg_rtx (V2SImode);
6646 5 : emit_insn (gen_mmx_psadbw (t1, operands[1], operands[2]));
6647 18933 : convert_move (t2, t1, 0);
6648 5 : emit_insn (gen_addv2si3 (operands[0], t2, operands[3]));
6649 18933 : DONE;
6650 18928 : })
6651 18928 :
6652 : (define_expand "usdot_prodv2siv8qi"
6653 : [(match_operand:V2SI 0 "register_operand")
6654 : (match_operand:V8QI 1 "register_operand")
6655 : (match_operand:V8QI 2 "register_operand")
6656 : (match_operand:V2SI 3 "register_operand")]
6657 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6658 7 : {
6659 7 : operands[1] = force_reg (V8QImode, operands[1]);
6660 7 : operands[2] = force_reg (V8QImode, operands[2]);
6661 7 : operands[3] = force_reg (V2SImode, operands[3]);
6662 :
6663 112 : if ((TARGET_AVX512VNNI && TARGET_AVX512VL)
6664 5 : || TARGET_AVXVNNI)
6665 105 : {
6666 110 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6667 5 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6668 5 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6669 5 : rtx op0 = gen_reg_rtx (V4SImode);
6670 :
6671 5 : emit_insn (gen_usdot_prodv4siv16qi (op0, op1, op2, op3));
6672 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6673 5 : }
6674 : else
6675 : {
6676 2 : rtx op1 = gen_reg_rtx (V8HImode);
6677 2 : rtx op2 = gen_reg_rtx (V8HImode);
6678 2 : rtx op3 = gen_reg_rtx (V4SImode);
6679 2 : rtx op0 = gen_reg_rtx (V4SImode);
6680 2 : rtx op0_1 = gen_reg_rtx (V4SImode);
6681 :
6682 2 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6683 2 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6684 2 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6685 2 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6686 :
6687 : /* vec_perm (op0, 2, 3, 0, 1); */
6688 2 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6689 2 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6690 2 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6691 : lowpart_subreg (V2SImode, op0, V4SImode)));
6692 : }
6693 7 : DONE;
6694 : })
6695 :
6696 : (define_expand "sdot_prodv2siv8qi"
6697 : [(match_operand:V2SI 0 "register_operand")
6698 : (match_operand:V8QI 1 "register_operand")
6699 : (match_operand:V8QI 2 "register_operand")
6700 : (match_operand:V2SI 3 "register_operand")]
6701 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6702 7 : {
6703 7 : operands[1] = force_reg (V8QImode, operands[1]);
6704 7 : operands[2] = force_reg (V8QImode, operands[2]);
6705 7 : operands[3] = force_reg (V2SImode, operands[3]);
6706 :
6707 490562 : if (TARGET_AVXVNNIINT8)
6708 : {
6709 490560 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6710 490560 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6711 490560 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6712 5 : rtx op0 = gen_reg_rtx (V4SImode);
6713 :
6714 5 : emit_insn (gen_sdot_prodv4siv16qi (op0, op1, op2, op3));
6715 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6716 : }
6717 : else
6718 : {
6719 2 : rtx op1 = gen_reg_rtx (V8HImode);
6720 2 : rtx op2 = gen_reg_rtx (V8HImode);
6721 2 : rtx op3 = gen_reg_rtx (V4SImode);
6722 2 : rtx op0 = gen_reg_rtx (V4SImode);
6723 2 : rtx op0_1 = gen_reg_rtx (V4SImode);
6724 :
6725 2 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6726 2 : emit_insn (gen_extendv8qiv8hi2 (op1, operands[1]));
6727 2 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6728 2 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6729 :
6730 : /* vec_perm (op0, 2, 3, 0, 1); */
6731 2 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6732 2 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6733 2 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6734 : lowpart_subreg (V2SImode, op0, V4SImode)));
6735 : }
6736 7 : DONE;
6737 :
6738 : })
6739 :
6740 : (define_expand "udot_prodv2siv8qi"
6741 : [(match_operand:V2SI 0 "register_operand")
6742 : (match_operand:V8QI 1 "register_operand")
6743 : (match_operand:V8QI 2 "register_operand")
6744 : (match_operand:V2SI 3 "register_operand")]
6745 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6746 7 : {
6747 7 : operands[1] = force_reg (V8QImode, operands[1]);
6748 7 : operands[2] = force_reg (V8QImode, operands[2]);
6749 7 : operands[3] = force_reg (V2SImode, operands[3]);
6750 :
6751 205 : if (TARGET_AVXVNNIINT8)
6752 : {
6753 203 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6754 203 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6755 203 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6756 5 : rtx op0 = gen_reg_rtx (V4SImode);
6757 :
6758 5 : emit_insn (gen_udot_prodv4siv16qi (op0, op1, op2, op3));
6759 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6760 : }
6761 : else
6762 : {
6763 2 : rtx op1 = gen_reg_rtx (V8HImode);
6764 2 : rtx op2 = gen_reg_rtx (V8HImode);
6765 2 : rtx op3 = gen_reg_rtx (V4SImode);
6766 2 : rtx op0 = gen_reg_rtx (V4SImode);
6767 2 : rtx op0_1 = gen_reg_rtx (V4SImode);
6768 :
6769 2 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6770 2 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6771 2 : emit_insn (gen_zero_extendv8qiv8hi2 (op2, operands[2]));
6772 2 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6773 :
6774 : /* vec_perm (op0, 2, 3, 0, 1); */
6775 2 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6776 2 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6777 2 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6778 : lowpart_subreg (V2SImode, op0, V4SImode)));
6779 : }
6780 7 : DONE;
6781 :
6782 : })
6783 :
6784 : (define_expand "usdot_prodv2siv4hi"
6785 : [(match_operand:V2SI 0 "register_operand")
6786 : (match_operand:V4HI 1 "register_operand")
6787 : (match_operand:V4HI 2 "register_operand")
6788 : (match_operand:V2SI 3 "register_operand")]
6789 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6790 3 : {
6791 3 : operands[1] = force_reg (V4HImode, operands[1]);
6792 3 : operands[2] = force_reg (V4HImode, operands[2]);
6793 3 : operands[3] = force_reg (V2SImode, operands[3]);
6794 :
6795 16590 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6796 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6797 16590 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6798 16590 : rtx op0 = gen_reg_rtx (V4SImode);
6799 16587 :
6800 3 : emit_insn (gen_usdot_prodv4siv8hi (op0, op1, op2, op3));
6801 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6802 3 : DONE;
6803 : })
6804 :
6805 : (define_expand "udot_prodv2siv4hi"
6806 : [(match_operand:V2SI 0 "register_operand")
6807 : (match_operand:V4HI 1 "register_operand")
6808 : (match_operand:V4HI 2 "register_operand")
6809 : (match_operand:V2SI 3 "register_operand")]
6810 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6811 3 : {
6812 3 : operands[1] = force_reg (V4HImode, operands[1]);
6813 3 : operands[2] = force_reg (V4HImode, operands[2]);
6814 3 : operands[3] = force_reg (V2SImode, operands[3]);
6815 :
6816 9477 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6817 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6818 9477 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6819 9477 : rtx op0 = gen_reg_rtx (V4SImode);
6820 9474 :
6821 3 : emit_insn (gen_udot_prodv4siv8hi (op0, op1, op2, op3));
6822 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6823 3 : DONE;
6824 : })
6825 :
6826 : (define_expand "sdot_prodv2siv4hi"
6827 : [(match_operand:V2SI 0 "register_operand")
6828 : (match_operand:V4HI 1 "register_operand")
6829 : (match_operand:V4HI 2 "register_operand")
6830 : (match_operand:V2SI 3 "register_operand")]
6831 : "TARGET_MMX_WITH_SSE"
6832 42 : {
6833 42 : operands[1] = force_reg (V4HImode, operands[1]);
6834 42 : operands[2] = force_reg (V4HImode, operands[2]);
6835 42 : operands[3] = force_reg (V2SImode, operands[3]);
6836 :
6837 15889 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6838 42 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6839 15889 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6840 15889 : rtx op0 = gen_reg_rtx (V4SImode);
6841 15847 :
6842 42 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6843 42 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6844 42 : DONE;
6845 : })
6846 :
6847 : (define_insn_and_split "mmx_pmovmskb"
6848 : [(set (match_operand:SI 0 "register_operand" "=r,r,jr")
6849 : (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x,x")]
6850 : UNSPEC_MOVMSK))]
6851 111 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6852 111 : && (TARGET_SSE || TARGET_3DNOW_A)"
6853 : "@
6854 : pmovmskb\t{%1, %0|%0, %1}
6855 : #
6856 109 : #"
6857 153 : "TARGET_SSE2 && reload_completed
6858 115983 : && SSE_REGNO_P (REGNO (operands[1]))"
6859 22 : [(set (match_dup 0)
6860 119447 : (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
6861 119447 : (set (match_dup 0)
6862 115852 : (zero_extend:SI (match_dup 2)))]
6863 437 : {
6864 415 : /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
6865 44 : operands[1] = lowpart_subreg (V16QImode, operands[1],
6866 22 : GET_MODE (operands[1]));
6867 44 : operands[2] = lowpart_subreg (QImode, operands[0],
6868 22 : GET_MODE (operands[0]));
6869 0 : }
6870 0 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
6871 : (set_attr "type" "mmxcvt,ssemov,ssemov")
6872 22 : (set_attr "mode" "DI,TI,TI")])
6873 :
6874 : (define_expand "mmx_maskmovq"
6875 : [(set (match_operand:V8QI 0 "memory_operand")
6876 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
6877 22 : (match_operand:V8QI 2 "register_operand")
6878 : (match_dup 0)]
6879 : UNSPEC_MASKMOV))]
6880 : "TARGET_SSE || TARGET_3DNOW_A")
6881 :
6882 19772 : (define_insn "*mmx_maskmovq"
6883 : [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
6884 19772 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
6885 19772 : (match_operand:V8QI 2 "register_operand" "y")
6886 19772 : (mem:V8QI (match_dup 0))]
6887 : UNSPEC_MASKMOV))]
6888 9 : "TARGET_SSE || TARGET_3DNOW_A"
6889 : ;; @@@ check ordering of operands in intel/nonintel syntax
6890 : "maskmovq\t{%2, %1|%1, %2}"
6891 : [(set_attr "type" "mmxcvt")
6892 : (set_attr "znver1_decode" "vector")
6893 : (set_attr "mode" "DI")])
6894 :
6895 : (define_int_iterator EMMS
6896 104 : [(UNSPECV_EMMS "TARGET_MMX")
6897 15 : (UNSPECV_FEMMS "TARGET_3DNOW")])
6898 0 :
6899 0 : (define_int_attr emms
6900 15 : [(UNSPECV_EMMS "emms")
6901 15 : (UNSPECV_FEMMS "femms")])
6902 0 :
6903 94994 : (define_expand "mmx_<emms>"
6904 94994 : [(parallel
6905 94994 : [(unspec_volatile [(const_int 0)] EMMS)
6906 94994 : (clobber (reg:XF ST0_REG))
6907 1812895706 : (clobber (reg:XF ST1_REG))
6908 : (clobber (reg:XF ST2_REG))
6909 : (clobber (reg:XF ST3_REG))
6910 : (clobber (reg:XF ST4_REG))
6911 1812895706 : (clobber (reg:XF ST5_REG))
6912 1812895706 : (clobber (reg:XF ST6_REG))
6913 1812895706 : (clobber (reg:XF ST7_REG))
6914 1812895706 : (clobber (reg:DI MM0_REG))
6915 1812895706 : (clobber (reg:DI MM1_REG))
6916 1812895706 : (clobber (reg:DI MM2_REG))
6917 1812895706 : (clobber (reg:DI MM3_REG))
6918 1812895706 : (clobber (reg:DI MM4_REG))
6919 : (clobber (reg:DI MM5_REG))
6920 1545793868 : (clobber (reg:DI MM6_REG))
6921 1545793868 : (clobber (reg:DI MM7_REG))])]
6922 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
6923 136226534 : {
6924 136226534 : if (!TARGET_MMX)
6925 : {
6926 125990220 : emit_insn (gen_nop ());
6927 125990220 : DONE;
6928 125990219 : }
6929 : })
6930 :
6931 : (define_insn "*mmx_<emms>"
6932 8190323 : [(unspec_volatile [(const_int 0)] EMMS)
6933 8190442 : (clobber (reg:XF ST0_REG))
6934 8190323 : (clobber (reg:XF ST1_REG))
6935 : (clobber (reg:XF ST2_REG))
6936 : (clobber (reg:XF ST3_REG))
6937 : (clobber (reg:XF ST4_REG))
6938 561418 : (clobber (reg:XF ST5_REG))
6939 561418 : (clobber (reg:XF ST6_REG))
6940 561418 : (clobber (reg:XF ST7_REG))
6941 : (clobber (reg:DI MM0_REG))
6942 : (clobber (reg:DI MM1_REG))
6943 119 : (clobber (reg:DI MM2_REG))
6944 1295908 : (clobber (reg:DI MM3_REG))
6945 1295908 : (clobber (reg:DI MM4_REG))
6946 1295908 : (clobber (reg:DI MM5_REG))
6947 : (clobber (reg:DI MM6_REG))
6948 70779 : (clobber (reg:DI MM7_REG))]
6949 : ""
6950 141191 : "<emms>"
6951 141191 : [(set_attr "type" "mmx")
6952 141191 : (set_attr "modrm" "0")
6953 : (set_attr "memory" "none")])
6954 :
6955 : (define_insn "popcount<mode>2"
6956 74620 : [(set (match_operand:VI1_16_32_64 0 "register_operand" "=v")
6957 74620 : (popcount:VI1_16_32_64
6958 : (match_operand:VI1_16_32_64 1 "register_operand" "v")))]
6959 73823 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
6960 73827 : "vpopcntb\t{%1, %0|%0, %1}")
6961 :
6962 50640 : (define_insn "popcount<mode>2"
6963 50664 : [(set (match_operand:VI2_32_64 0 "register_operand" "=v")
6964 50664 : (popcount:VI2_32_64
6965 50652 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
6966 50662 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
6967 50686 : "vpopcntw\t{%1, %0|%0, %1}")
6968 :
6969 50640 : (define_insn "popcountv2si2"
6970 50652 : [(set (match_operand:V2SI 0 "register_operand" "=v")
6971 12 : (popcount:V2SI
6972 50646 : (match_operand:V2SI 1 "register_operand" "v")))]
6973 50656 : "TARGET_AVX512VPOPCNTDQ && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
6974 50663 : "vpopcntd\t{%1, %0|%0, %1}")
6975 50640 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
6976 : /* (content generated from coverage data) */
6977 : /* ... */
6978 : /* ... */
6979 : /* ... */
6980 : /* ... */
6981 : /* ... */
6982 : /* ... */
6983 3165092 : /* END: function "_Z8recog_61P7rtx_defP8rtx_insnPi" */
6984 : /* ... */
6985 : /* ... */
6986 : /* ... */
6987 3165092 : /* ... */
6988 3165092 : /* ... */
6989 3165092 : /* ... */
6990 3165092 : /* ... */
6991 3165092 : /* ... */
6992 3165092 : /* ... */
6993 3165092 : /* ... */
6994 3165092 : /* ... */
6995 3165092 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
6996 : /* (content generated from coverage data) */
6997 2110280 : /* ... */
6998 2110280 : /* ... */
6999 2110280 : /* ... */
7000 2110280 : /* ... */
7001 2110280 : /* ... */
7002 2110280 : /* ... */
7003 2110280 : /* ... */
7004 : /* ... */
7005 18134 : /* ... */
7006 18134 : /* ... */
7007 17458 : /* ... */
7008 17458 : /* ... */
7009 33239 : /* ... */
7010 5241 : /* ... */
7011 12893 : /* ... */
7012 : /* ... */
7013 : /* ... */
7014 : /* ... */
7015 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7016 : /* (content generated from coverage data) */
7017 : /* ... */
7018 : /* ... */
7019 : /* ... */
7020 : /* ... */
7021 : /* ... */
7022 : /* ... */
7023 : /* ... */
7024 : /* ... */
7025 : /* ... */
7026 : /* ... */
7027 : /* ... */
7028 : /* ... */
7029 : /* ... */
7030 : /* ... */
7031 : /* ... */
7032 : /* ... */
7033 : /* ... */
7034 : /* ... */
7035 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7036 : /* (content generated from coverage data) */
7037 : /* ... */
7038 : /* ... */
7039 : /* ... */
7040 : /* ... */
7041 : /* ... */
7042 : /* ... */
7043 : /* ... */
7044 : /* ... */
7045 : /* ... */
7046 : /* ... */
7047 : /* ... */
7048 : /* ... */
7049 : /* ... */
7050 : /* ... */
7051 : /* ... */
7052 : /* ... */
7053 : /* ... */
7054 : /* ... */
7055 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7056 : /* (content generated from coverage data) */
7057 : /* ... */
7058 : /* ... */
7059 : /* ... */
7060 : /* ... */
7061 : /* ... */
7062 : /* ... */
7063 : /* ... */
7064 : /* ... */
7065 : /* ... */
7066 : /* ... */
7067 : /* ... */
7068 : /* ... */
7069 : /* ... */
7070 : /* ... */
7071 : /* ... */
7072 : /* ... */
7073 : /* ... */
7074 : /* ... */
7075 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7076 : /* (content generated from coverage data) */
7077 : /* ... */
7078 : /* ... */
7079 : /* ... */
7080 : /* ... */
7081 : /* ... */
7082 : /* ... */
7083 : /* ... */
7084 : /* ... */
7085 : /* ... */
7086 : /* ... */
7087 : /* ... */
7088 : /* ... */
7089 : /* ... */
7090 : /* ... */
7091 : /* ... */
7092 : /* ... */
7093 : /* ... */
7094 : /* ... */
7095 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7096 : /* (content generated from coverage data) */
7097 : /* ... */
7098 : /* ... */
7099 : /* ... */
7100 : /* ... */
7101 : /* ... */
7102 : /* ... */
7103 : /* ... */
7104 : /* ... */
7105 : /* ... */
7106 : /* ... */
7107 : /* ... */
7108 : /* ... */
7109 : /* ... */
7110 : /* ... */
7111 : /* ... */
7112 : /* ... */
7113 : /* ... */
7114 : /* ... */
7115 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7116 : /* (content generated from coverage data) */
7117 : /* ... */
7118 : /* ... */
7119 : /* ... */
7120 : /* ... */
7121 : /* ... */
7122 : /* ... */
7123 : /* ... */
7124 : /* ... */
7125 : /* ... */
7126 : /* ... */
7127 : /* ... */
7128 : /* ... */
7129 : /* ... */
7130 : /* ... */
7131 : /* ... */
7132 : /* ... */
7133 : /* ... */
7134 : /* ... */
7135 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7136 : /* (content generated from coverage data) */
7137 : /* ... */
7138 : /* ... */
7139 : /* ... */
7140 : /* ... */
7141 : /* ... */
7142 : /* ... */
7143 : /* ... */
7144 : /* ... */
7145 : /* ... */
7146 : /* ... */
7147 : /* ... */
7148 : /* ... */
7149 : /* ... */
7150 : /* ... */
7151 : /* ... */
7152 : /* ... */
7153 : /* ... */
7154 : /* ... */
7155 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7156 : /* (content generated from coverage data) */
7157 : /* ... */
7158 : /* ... */
7159 : /* ... */
7160 : /* ... */
7161 : /* ... */
7162 : /* ... */
7163 : /* ... */
7164 : /* ... */
7165 : /* ... */
7166 : /* ... */
7167 : /* ... */
7168 : /* ... */
7169 : /* ... */
7170 : /* ... */
7171 : /* ... */
7172 : /* ... */
7173 : /* ... */
7174 : /* ... */
7175 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7176 : /* (content generated from coverage data) */
7177 : /* ... */
7178 : /* ... */
7179 : /* ... */
7180 : /* ... */
7181 : /* ... */
7182 : /* ... */
7183 : /* ... */
7184 : /* ... */
7185 : /* ... */
7186 : /* ... */
7187 : /* ... */
7188 : /* ... */
7189 : /* ... */
7190 : /* ... */
7191 : /* ... */
7192 : /* ... */
7193 : /* ... */
7194 : /* ... */
7195 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7196 : /* (content generated from coverage data) */
7197 : /* ... */
7198 : /* ... */
7199 : /* ... */
7200 : /* ... */
7201 : /* ... */
7202 : /* ... */
7203 : /* ... */
7204 : /* ... */
7205 : /* ... */
7206 : /* ... */
7207 : /* ... */
7208 : /* ... */
7209 : /* ... */
7210 : /* ... */
7211 : /* ... */
7212 : /* ... */
7213 : /* ... */
7214 : /* ... */
7215 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7216 : /* (content generated from coverage data) */
7217 : /* ... */
7218 : /* ... */
7219 : /* ... */
7220 : /* ... */
7221 : /* ... */
7222 : /* ... */
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7224 : /* ... */
7225 : /* ... */
7226 : /* ... */
7227 : /* ... */
7228 : /* ... */
7229 : /* ... */
7230 : /* ... */
7231 : /* ... */
7232 : /* ... */
7233 : /* ... */
7234 : /* ... */
7235 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7236 : /* (content generated from coverage data) */
7237 : /* ... */
7238 : /* ... */
7239 : /* ... */
7240 : /* ... */
7241 : /* ... */
7242 : /* ... */
7243 : /* ... */
7244 : /* ... */
7245 : /* ... */
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7248 : /* ... */
7249 : /* ... */
7250 : /* ... */
7251 : /* ... */
7252 : /* ... */
7253 : /* ... */
7254 : /* ... */
7255 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7256 : /* (content generated from coverage data) */
7257 : /* ... */
7258 : /* ... */
7259 : /* ... */
7260 : /* ... */
7261 : /* ... */
7262 : /* ... */
7263 : /* ... */
7264 : /* ... */
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7268 : /* ... */
7269 : /* ... */
7270 : /* ... */
7271 : /* ... */
7272 : /* ... */
7273 : /* ... */
7274 : /* ... */
7275 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7276 : /* (content generated from coverage data) */
7277 : /* ... */
7278 : /* ... */
7279 : /* ... */
7280 : /* ... */
7281 : /* ... */
7282 : /* ... */
7283 : /* ... */
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7285 : /* ... */
7286 : /* ... */
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7288 : /* ... */
7289 : /* ... */
7290 : /* ... */
7291 : /* ... */
7292 : /* ... */
7293 : /* ... */
7294 : /* ... */
7295 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7296 : /* (content generated from coverage data) */
7297 : /* ... */
7298 : /* ... */
7299 : /* ... */
7300 : /* ... */
7301 : /* ... */
7302 : /* ... */
7303 : /* ... */
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7309 : /* ... */
7310 : /* ... */
7311 : /* ... */
7312 : /* ... */
7313 : /* ... */
7314 : /* ... */
7315 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7316 : /* (content generated from coverage data) */
7317 : /* ... */
7318 : /* ... */
7319 : /* ... */
7320 : /* ... */
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7325 : /* ... */
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7328 : /* ... */
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7330 : /* ... */
7331 : /* ... */
7332 : /* ... */
7333 : /* ... */
7334 : /* ... */
7335 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7336 : /* (content generated from coverage data) */
7337 : /* ... */
7338 : /* ... */
7339 : /* ... */
7340 : /* ... */
7341 : /* ... */
7342 : /* ... */
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7344 : /* ... */
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7349 : /* ... */
7350 : /* ... */
7351 : /* ... */
7352 : /* ... */
7353 : /* ... */
7354 : /* ... */
7355 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7356 : /* (content generated from coverage data) */
7357 : /* ... */
7358 : /* ... */
7359 : /* ... */
7360 : /* ... */
7361 : /* ... */
7362 : /* ... */
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7364 : /* ... */
7365 : /* ... */
7366 : /* ... */
7367 : /* ... */
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7369 : /* ... */
7370 : /* ... */
7371 : /* ... */
7372 : /* ... */
7373 : /* ... */
7374 : /* ... */
7375 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7376 : /* (content generated from coverage data) */
7377 : /* ... */
7378 : /* ... */
7379 : /* ... */
7380 : /* ... */
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7384 : /* ... */
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7388 : /* ... */
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7390 : /* ... */
7391 : /* ... */
7392 : /* ... */
7393 : /* ... */
7394 : /* ... */
7395 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7396 : /* (content generated from coverage data) */
7397 : /* ... */
7398 : /* ... */
7399 : /* ... */
7400 : /* ... */
7401 : /* ... */
7402 : /* ... */
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7410 : /* ... */
7411 : /* ... */
7412 : /* ... */
7413 : /* ... */
7414 : /* ... */
7415 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7416 : /* (content generated from coverage data) */
7417 : /* ... */
7418 : /* ... */
7419 : /* ... */
7420 : /* ... */
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7430 : /* ... */
7431 : /* ... */
7432 : /* ... */
7433 : /* ... */
7434 : /* ... */
7435 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7436 : /* (content generated from coverage data) */
7437 : /* ... */
7438 : /* ... */
7439 : /* ... */
7440 : /* ... */
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7443 : /* ... */
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7450 : /* ... */
7451 : /* ... */
7452 : /* ... */
7453 : /* ... */
7454 : /* ... */
7455 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7456 : /* (content generated from coverage data) */
7457 : /* ... */
7458 : /* ... */
7459 : /* ... */
7460 : /* ... */
7461 : /* ... */
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7464 : /* ... */
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7467 : /* ... */
7468 : /* ... */
7469 : /* ... */
7470 : /* ... */
7471 : /* ... */
7472 : /* ... */
7473 : /* ... */
7474 : /* ... */
7475 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7476 : /* (content generated from coverage data) */
7477 : /* ... */
7478 : /* ... */
7479 : /* ... */
7480 : /* ... */
7481 : /* ... */
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7488 : /* ... */
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7490 : /* ... */
7491 : /* ... */
7492 : /* ... */
7493 : /* ... */
7494 : /* ... */
7495 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7496 : /* (content generated from coverage data) */
7497 : /* ... */
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7499 : /* ... */
7500 : /* ... */
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7508 : /* ... */
7509 : /* ... */
7510 : /* ... */
7511 : /* ... */
7512 : /* ... */
7513 : /* ... */
7514 : /* ... */
7515 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7516 : /* (content generated from coverage data) */
7517 : /* ... */
7518 : /* ... */
7519 : /* ... */
7520 : /* ... */
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7529 : /* ... */
7530 : /* ... */
7531 : /* ... */
7532 : /* ... */
7533 : /* ... */
7534 : /* ... */
7535 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7536 : /* (content generated from coverage data) */
7537 : /* ... */
7538 : /* ... */
7539 : /* ... */
7540 : /* ... */
7541 : /* ... */
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7548 : /* ... */
7549 : /* ... */
7550 : /* ... */
7551 : /* ... */
7552 : /* ... */
7553 : /* ... */
7554 : /* ... */
7555 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7556 : /* (content generated from coverage data) */
7557 : /* ... */
7558 : /* ... */
7559 : /* ... */
7560 : /* ... */
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7564 : /* ... */
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7568 : /* ... */
7569 : /* ... */
7570 : /* ... */
7571 : /* ... */
7572 : /* ... */
7573 : /* ... */
7574 : /* ... */
7575 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7576 : /* (content generated from coverage data) */
7577 : /* ... */
7578 : /* ... */
7579 : /* ... */
7580 : /* ... */
7581 : /* ... */
7582 : /* ... */
7583 : /* ... */
7584 : /* ... */
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7588 : /* ... */
7589 : /* ... */
7590 : /* ... */
7591 : /* ... */
7592 : /* ... */
7593 : /* ... */
7594 : /* ... */
7595 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7596 : /* (content generated from coverage data) */
7597 : /* ... */
7598 : /* ... */
7599 : /* ... */
7600 : /* ... */
7601 : /* ... */
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7609 : /* ... */
7610 : /* ... */
7611 : /* ... */
7612 : /* ... */
7613 : /* ... */
7614 : /* ... */
7615 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7616 : /* (content generated from coverage data) */
7617 : /* ... */
7618 : /* ... */
7619 : /* ... */
7620 : /* ... */
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7627 : /* ... */
7628 : /* ... */
7629 : /* ... */
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7631 : /* ... */
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7633 : /* ... */
7634 : /* ... */
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7636 : /* (content generated from coverage data) */
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7638 : /* ... */
7639 : /* ... */
7640 : /* ... */
7641 : /* ... */
7642 : /* ... */
7643 : /* ... */
7644 : /* ... */
7645 : /* ... */
7646 : /* ... */
7647 : /* ... */
7648 : /* ... */
7649 : /* ... */
7650 : /* ... */
7651 : /* ... */
7652 : /* ... */
7653 : /* ... */
7654 : /* ... */
7655 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
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7657 : /* ... */
7658 : /* ... */
7659 : /* ... */
7660 : /* ... */
7661 : /* ... */
7662 : /* ... */
7663 : /* ... */
7664 : /* ... */
7665 : /* ... */
7666 : /* ... */
7667 : /* ... */
7668 : /* ... */
7669 : /* ... */
7670 : /* ... */
7671 : /* ... */
7672 : /* ... */
7673 : /* ... */
7674 : /* ... */
7675 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7676 : /* (content generated from coverage data) */
7677 : /* ... */
7678 : /* ... */
7679 : /* ... */
7680 : /* ... */
7681 : /* ... */
7682 : /* ... */
7683 : /* ... */
7684 : /* ... */
7685 : /* ... */
7686 : /* ... */
7687 : /* ... */
7688 : /* ... */
7689 : /* ... */
7690 : /* ... */
7691 : /* ... */
7692 : /* ... */
7693 : /* ... */
7694 : /* ... */
7695 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7696 : /* (content generated from coverage data) */
7697 : /* ... */
7698 : /* ... */
7699 : /* ... */
7700 : /* ... */
7701 : /* ... */
7702 : /* ... */
7703 : /* ... */
7704 : /* ... */
7705 : /* ... */
7706 : /* ... */
7707 : /* ... */
7708 : /* ... */
7709 : /* ... */
7710 : /* ... */
7711 : /* ... */
7712 : /* ... */
7713 : /* ... */
7714 : /* ... */
7715 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7716 : /* (content generated from coverage data) */
7717 : /* ... */
7718 0 : /* ... */
7719 0 : /* ... */
7720 0 : /* ... */
7721 0 : /* ... */
7722 : /* ... */
7723 0 : /* ... */
7724 : /* ... */
7725 : /* ... */
7726 : /* ... */
7727 : /* ... */
7728 : /* ... */
7729 : /* ... */
7730 : /* ... */
7731 : /* ... */
7732 : /* ... */
7733 : /* ... */
7734 : /* ... */
7735 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7736 : /* (content generated from coverage data) */
7737 : /* ... */
7738 : /* ... */
7739 442050304 : /* END: function "_Z19get_attr_prefix_rexP8rtx_insn" */
7740 : /* ... */
7741 442050304 : /* ... */
7742 : /* ... */
7743 442050304 : /* ... */
7744 : /* ... */
7745 807603 : /* ... */
7746 807603 : /* ... */
7747 807603 : /* ... */
7748 807603 : /* ... */
7749 807603 : /* ... */
7750 : /* ... */
7751 : /* ... */
7752 : /* ... */
7753 : /* ... */
7754 : /* ... */
7755 786208 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
|
