Line data Source code
1 : ;; GCC machine description for MMX and 3dNOW! instructions
2 : ;; Copyright (C) 2005-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; The MMX and 3dNOW! patterns are in the same file because they use
21 : ;; the same register file, and 3dNOW! adds a number of extensions to
22 : ;; the base integer MMX isa.
23 :
24 : ;; Note! Except for the basic move instructions, *all* of these
25 : ;; patterns are outside the normal optabs namespace. This is because
26 : ;; use of these registers requires the insertion of emms or femms
27 : ;; instructions to return to normal fpu mode. The compiler doesn't
28 : ;; know how to do that itself, which means it's up to the user. Which
29 : ;; means that we should never use any of these patterns except at the
30 : ;; direction of the user via a builtin.
31 :
32 : (define_c_enum "unspec" [
33 : UNSPEC_3DNOW
34 :
35 : UNSPEC_MOVNTQ
36 : UNSPEC_PFRCP
37 : UNSPEC_PFRCPIT1
38 : UNSPEC_PFRCPIT2
39 : UNSPEC_PFRSQRT
40 : UNSPEC_PFRSQIT1
41 : ])
42 :
43 : (define_c_enum "unspecv" [
44 : UNSPECV_EMMS
45 : UNSPECV_FEMMS
46 : ])
47 :
48 : ;; 8 byte integral modes handled by MMX (and by extension, SSE)
49 : (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
50 284 : (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")])
51 56 :
52 : ;; All 8-byte vector modes handled by MMX
53 : (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF V4HF V4BF])
54 14777 : (define_mode_iterator MMXMODE124 [V8QI V4HI V2SI V2SF])
55 14777 :
56 14777 : ;; Mix-n-match
57 : (define_mode_iterator MMXMODE12 [V8QI V4HI])
58 14777 : (define_mode_iterator MMXMODE14 [V8QI V2SI])
59 : (define_mode_iterator MMXMODE24 [V4HI V2SI])
60 : (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
61 :
62 : ;; All 4-byte integer/float16 vector modes
63 : (define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF])
64 :
65 : (define_mode_iterator V2FI_32 [V2HF V2BF V2HI])
66 : (define_mode_iterator V4FI_64 [V4HF V4BF V4HI])
67 : (define_mode_iterator V4F_64 [V4HF V4BF])
68 : (define_mode_iterator V2F_32 [V2HF V2BF])
69 : ;; 4-byte integer vector modes
70 : (define_mode_iterator VI_32 [V4QI V2HI])
71 :
72 : ;; 8-byte and 4-byte HImode vector modes
73 110 : (define_mode_iterator VI2_32_64 [(V4HI "TARGET_MMX_WITH_SSE") V2HI])
74 7 :
75 74 : ;; 8-byte, 4-byte and 2-byte QImode vector modes
76 5 : (define_mode_iterator VI1_16_32_64 [(V8QI "TARGET_MMX_WITH_SSE") V4QI V2QI])
77 15 :
78 12 : ;; 4-byte and 2-byte integer vector modes
79 14 : (define_mode_iterator VI_16_32 [V4QI V2QI V2HI])
80 14 :
81 37 : ;; 4-byte and 2-byte QImode vector modes
82 6 : (define_mode_iterator VI1_16_32 [V4QI V2QI])
83 6 :
84 17 : ;; All 2-byte, 4-byte and 8-byte vector modes.
85 : (define_mode_iterator V_16_32_64
86 : [V2QI V4QI V2HI V1SI V2HF V2BF
87 1483 : (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT")
88 18 : (V4HF "TARGET_64BIT") (V4BF "TARGET_64BIT")
89 51718 : (V2SI "TARGET_64BIT") (V2SF "TARGET_64BIT")
90 157 : (V1DI "TARGET_64BIT")])
91 32136998 :
92 32852624 : ;; V2S* modes
93 51130944 : (define_mode_iterator V2FI [V2SF V2SI])
94 79285754 :
95 60556153 : (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI])
96 38176729 :
97 14219807 : (define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI])
98 :
99 : (define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI])
100 :
101 : ;; Mapping from integer vector mode to mnemonic suffix
102 : (define_mode_attr mmxvecsize
103 : [(V8QI "b") (V4QI "b") (V2QI "b")
104 : (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
105 :
106 : ;; Mapping to same size integral mode.
107 : (define_mode_attr mmxinsnmode
108 : [(V8QI "DI") (V4QI "SI") (V2QI "HI")
109 : (V4HI "DI") (V2HI "SI")
110 : (V2SI "DI")
111 : (V1DI "DI") (V1SI "SI")
112 : (V4HF "DI") (V2HF "SI")
113 : (V4BF "DI") (V2BF "SI")
114 : (V2SF "DI")])
115 :
116 : (define_mode_attr mmxdoublemode
117 : [(V8QI "V8HI") (V4HI "V4SI")])
118 :
119 : (define_mode_attr mmxhalfmode
120 : [(V4HI "V4QI") (V2HI "V2QI")])
121 :
122 : (define_mode_attr mmxbytemode
123 : [(V4HI "V8QI") (V2HI "V4QI")])
124 :
125 : (define_mode_attr mmxhalfmodelower
126 : [(V4HI "v4qi") (V2HI "v2qi")])
127 :
128 : ;; Mapping of vector float modes to an integer mode of the same size
129 : (define_mode_attr mmxintvecmode
130 : [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
131 : (V4HF "V4HI") (V2HF "V2HI") (V4BF "V4HI") (V2BF "V2HI")])
132 :
133 : (define_mode_attr mmxintvecmodelower
134 : [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")
135 : (V4HF "v4hi") (V2HF "v2hi")])
136 :
137 : ;; Mapping of vector modes to a vector mode of double size
138 : (define_mode_attr mmxdoublevecmode
139 : [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")
140 : (V2HI "V4HI") (V2HF "V4HF") (V2BF "V4BF")])
141 :
142 : ;; Mapping of vector modes back to the scalar modes
143 : (define_mode_attr mmxscalarmode
144 : [(V2SI "SI") (V2SF "SF")
145 : (V4HF "HF") (V4BF "BF")
146 : (V2HF "HF") (V2BF "BF")
147 : (V4HI "HI") (V2HI "HI")
148 : (V8QI "QI")])
149 :
150 : (define_mode_attr mmxscalarmodelower
151 : [(V2SI "si") (V2SF "sf")
152 : (V4HF "hf") (V4BF "bf")
153 : (V2HF "hf") (V2BF "bf")
154 : (V4HI "hi") (V2HI "hi")
155 : (V8QI "qi")])
156 :
157 : (define_mode_attr mmxscalarsize
158 : [(V1DI "64")
159 : (V2SI "32") (V2SF "32")
160 : (V4HF "16") (V4BF "16")
161 : (V2HF "16") (V2BF "16")
162 : (V4HI "16") (V2HI "16")
163 : (V8QI "8")])
164 :
165 : (define_mode_attr Yv_Yw
166 : [(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")])
167 :
168 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
169 : ;;
170 : ;; Move patterns
171 : ;;
172 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
173 :
174 : ;; All of these patterns are enabled for MMX as well as 3dNOW.
175 : ;; This is essential for maintaining stable calling conventions.
176 :
177 : (define_expand "mov<mode>"
178 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
179 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"))]
180 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
181 498516 : {
182 498516 : ix86_expand_vector_move (<MODE>mode, operands);
183 498516 : DONE;
184 : })
185 :
186 : (define_insn "*mov<mode>_internal"
187 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
188 : "=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!y,v,v,v,m,r,v,!y,*x")
189 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"
190 : "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))]
191 74178948 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
192 73842934 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))
193 73551597 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
194 232236 : {
195 28833234 : switch (get_attr_type (insn))
196 826391 : {
197 28601381 : case TYPE_MULTI:
198 : return "#";
199 383 :
200 58988 : case TYPE_IMOV:
201 59371 : if (get_attr_mode (insn) == MODE_SI)
202 : return "mov{l}\t{%1, %k0|%k0, %1}";
203 : else
204 58910 : return "mov{q}\t{%1, %0|%0, %1}";
205 :
206 0 : case TYPE_MMX:
207 0 : return "pxor\t%0, %0";
208 :
209 550 : case TYPE_MMXMOV:
210 : /* Handle broken assemblers that require movd instead of movq. */
211 550 : if (!HAVE_AS_IX86_INTERUNIT_MOVQ
212 : && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
213 : return "movd\t{%1, %0|%0, %1}";
214 550 : return "movq\t{%1, %0|%0, %1}";
215 :
216 146 : case TYPE_SSECVT:
217 146 : if (SSE_REG_P (operands[0]))
218 105 : return "movq2dq\t{%1, %0|%0, %1}";
219 : else
220 : return "movdq2q\t{%1, %0|%0, %1}";
221 :
222 1783 : case TYPE_SSELOG1:
223 1783 : return standard_sse_constant_opcode (insn, operands);
224 :
225 170769 : case TYPE_SSEMOV:
226 170769 : return ix86_output_ssemov (insn, operands);
227 :
228 0 : default:
229 0 : gcc_unreachable ();
230 : }
231 : }
232 : [(set (attr "isa")
233 : (cond [(eq_attr "alternative" "0,1")
234 : (const_string "nox64")
235 235053 : (eq_attr "alternative" "2,3,4,9,10")
236 : (const_string "x64")
237 : (eq_attr "alternative" "15,16")
238 : (const_string "x64_sse2")
239 : (eq_attr "alternative" "17,18")
240 : (const_string "sse2")
241 : ]
242 : (const_string "*")))
243 : (set (attr "type")
244 : (cond [(eq_attr "alternative" "0,1")
245 : (const_string "multi")
246 : (eq_attr "alternative" "2,3,4")
247 : (const_string "imov")
248 : (eq_attr "alternative" "5")
249 : (const_string "mmx")
250 : (eq_attr "alternative" "6,7,8,9,10")
251 : (const_string "mmxmov")
252 : (eq_attr "alternative" "11")
253 : (const_string "sselog1")
254 : (eq_attr "alternative" "17,18")
255 : (const_string "ssecvt")
256 : ]
257 : (const_string "ssemov")))
258 : (set (attr "prefix_rex")
259 : (if_then_else (eq_attr "alternative" "9,10,15,16")
260 : (const_string "1")
261 : (const_string "*")))
262 : (set (attr "prefix")
263 : (if_then_else (eq_attr "type" "sselog1,ssemov")
264 : (const_string "maybe_vex")
265 : (const_string "orig")))
266 : (set (attr "prefix_data16")
267 : (if_then_else
268 : (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
269 : (const_string "1")
270 : (const_string "*")))
271 : (set (attr "mode")
272 : (cond [(eq_attr "alternative" "2")
273 : (const_string "SI")
274 : (eq_attr "alternative" "11,12")
275 : (cond [(match_test "<MODE>mode == V2SFmode
276 : || <MODE>mode == V4HFmode
277 : || <MODE>mode == V4BFmode")
278 : (const_string "V4SF")
279 : (ior (not (match_test "TARGET_SSE2"))
280 : (match_test "optimize_function_for_size_p (cfun)"))
281 50987 : (const_string "V4SF")
282 : ]
283 : (const_string "TI"))
284 :
285 : (and (eq_attr "alternative" "13")
286 1886221 : (ior (ior (and (match_test "<MODE>mode == V2SFmode")
287 : (not (match_test "TARGET_MMX_WITH_SSE")))
288 : (not (match_test "TARGET_SSE2")))
289 : (match_test "<MODE>mode == V4HFmode
290 : || <MODE>mode == V4BFmode")))
291 : (const_string "V2SF")
292 :
293 : (and (eq_attr "alternative" "14")
294 6049533 : (ior (ior (match_test "<MODE>mode == V2SFmode")
295 : (not (match_test "TARGET_SSE2")))
296 : (match_test "<MODE>mode == V4HFmode
297 : || <MODE>mode == V4BFmode")))
298 : (const_string "V2SF")
299 6422744 : ]
300 6422744 : (const_string "DI")))
301 6422744 : (set (attr "preferred_for_speed")
302 : (cond [(eq_attr "alternative" "9,15")
303 18763 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
304 : (eq_attr "alternative" "10,16")
305 6282421 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
306 : ]
307 405638 : (symbol_ref "true")))])
308 :
309 : (define_split
310 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
311 : (match_operand:MMXMODE 1 "nonimmediate_gr_operand"))]
312 189554 : "!TARGET_64BIT && reload_completed"
313 66979 : [(const_int 0)]
314 792385 : "ix86_split_long_move (operands); DONE;")
315 21627 :
316 725406 : (define_split
317 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
318 : (match_operand:MMXMODE 1 "const0_operand"))]
319 34006 : "!TARGET_64BIT && reload_completed"
320 17312 : [(const_int 0)]
321 64407 : "ix86_split_long_move (operands); DONE;")
322 41677 :
323 47095 : (define_expand "movmisalign<mode>"
324 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
325 5487 : (match_operand:MMXMODE 1 "nonimmediate_operand"))]
326 17212 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
327 131473 : {
328 137282 : ix86_expand_vector_move (<MODE>mode, operands);
329 125986 : DONE;
330 17212 : })
331 :
332 149805 : (define_expand "mov<mode>"
333 : [(set (match_operand:V_32 0 "nonimmediate_operand")
334 149805 : (match_operand:V_32 1 "nonimm_or_0_operand"))]
335 149805 : ""
336 166297 : {
337 45798 : ix86_expand_vector_move (<MODE>mode, operands);
338 45798 : DONE;
339 : })
340 :
341 : (define_insn "*mov<mode>_internal"
342 16321 : [(set (match_operand:V_32 0 "nonimmediate_operand"
343 0 : "=r ,m ,v,v,v,m,r,v")
344 16321 : (match_operand:V_32 1 "nonimm_or_0_operand"
345 16321 : "rmC,rC,C,v,m,v,v,r"))]
346 10271444 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
347 41453179 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
348 17412 : {
349 19211941 : switch (get_attr_type (insn))
350 3 : {
351 19194529 : case TYPE_IMOV:
352 0 : return "mov{l}\t{%1, %0|%0, %1}";
353 :
354 208 : case TYPE_SSELOG1:
355 208 : return standard_sse_constant_opcode (insn, operands);
356 0 :
357 7598 : case TYPE_SSEMOV:
358 7598 : return ix86_output_ssemov (insn, operands);
359 :
360 0 : default:
361 0 : gcc_unreachable ();
362 : }
363 : }
364 : [(set (attr "isa")
365 : (cond [(eq_attr "alternative" "6,7")
366 : (const_string "sse2")
367 5610 : ]
368 : (const_string "*")))
369 : (set (attr "type")
370 : (cond [(eq_attr "alternative" "2")
371 : (const_string "sselog1")
372 : (eq_attr "alternative" "3,4,5,6,7")
373 : (const_string "ssemov")
374 : ]
375 : (const_string "imov")))
376 : (set (attr "prefix")
377 : (if_then_else (eq_attr "type" "sselog1,ssemov")
378 : (const_string "maybe_vex")
379 : (const_string "orig")))
380 : (set (attr "prefix_data16")
381 : (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
382 : (const_string "1")
383 : (const_string "*")))
384 : (set (attr "mode")
385 : (cond [(eq_attr "alternative" "2,3")
386 : (cond [(match_test "<MODE>mode == V2HFmode
387 133033 : || <MODE>mode == V2BFmode")
388 : (const_string "V4SF")
389 : (match_test "TARGET_AVX")
390 : (const_string "TI")
391 27966 : (ior (not (match_test "TARGET_SSE2"))
392 21969 : (match_test "optimize_function_for_size_p (cfun)"))
393 : (const_string "V4SF")
394 : ]
395 : (const_string "TI"))
396 :
397 : (and (eq_attr "alternative" "4,5")
398 : (ior (match_test "<MODE>mode == V2HFmode
399 : || <MODE>mode == V2BFmode")
400 : (not (match_test "TARGET_SSE2"))))
401 : (const_string "SF")
402 : ]
403 : (const_string "SI")))
404 : (set (attr "preferred_for_speed")
405 : (cond [(eq_attr "alternative" "6")
406 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
407 : (eq_attr "alternative" "7")
408 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
409 : ]
410 : (symbol_ref "true")))])
411 :
412 : ;; For TARGET_64BIT we always round up to 8 bytes.
413 : (define_insn "*push<mode>2_rex64"
414 : [(set (match_operand:V_32 0 "push_operand" "=X,X")
415 : (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))]
416 3 : "TARGET_64BIT"
417 : "@
418 19194526 : push{q}\t%q1
419 19194526 : #"
420 : [(set_attr "type" "push,multi")
421 : (set_attr "mode" "DI")])
422 :
423 60783946 : (define_split
424 60783946 : [(set (match_operand:V_32 0 "push_operand")
425 41685367 : (match_operand:V_32 1 "sse_reg_operand"))]
426 93807209 : "TARGET_64BIT && TARGET_SSE && reload_completed"
427 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
428 : (set (match_dup 0) (match_dup 1))]
429 0 : {
430 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<V_32:MODE>mode)));
431 : /* Preserve memory attributes. */
432 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
433 : })
434 :
435 : (define_expand "movmisalign<mode>"
436 0 : [(set (match_operand:V_32 0 "nonimmediate_operand")
437 : (match_operand:V_32 1 "nonimmediate_operand"))]
438 : ""
439 8668 : {
440 8668 : ix86_expand_vector_move (<MODE>mode, operands);
441 8668 : DONE;
442 : })
443 :
444 : (define_expand "movv2qi"
445 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
446 52847 : (match_operand:V2QI 1 "nonimm_or_0_operand"))]
447 111 : ""
448 97026 : {
449 52958 : ix86_expand_vector_move (V2QImode, operands);
450 52847 : DONE;
451 111 : })
452 :
453 : (define_insn "*movv2qi_internal"
454 : [(set (match_operand:V2QI 0 "nonimmediate_operand"
455 18 : "=r,r,r,m ,v,v,v,jm,m,r,v")
456 : (match_operand:V2QI 1 "nonimm_or_0_operand"
457 18 : "r ,C,m,rC,C,v,m,x,v,v,r"))]
458 8564994 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
459 8536061 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
460 21969 : {
461 3942370 : switch (get_attr_type (insn))
462 44511 : {
463 3937514 : case TYPE_IMOV:
464 17113 : if (get_attr_mode (insn) == MODE_SI)
465 : return "mov{l}\t{%k1, %k0|%k0, %k1}";
466 0 : else
467 16911 : return "mov{w}\t{%1, %0|%0, %1}";
468 0 :
469 : case TYPE_IMOVX:
470 : /* movzwl is faster than movw on p2 due to partial word stalls,
471 : though not as fast as an aligned movl. */
472 : return "movz{wl|x}\t{%1, %k0|%k0, %1}";
473 :
474 590 : case TYPE_SSELOG1:
475 590 : if (satisfies_constraint_C (operands[1]))
476 56 : return standard_sse_constant_opcode (insn, operands);
477 :
478 534 : if (SSE_REG_P (operands[0]))
479 509 : return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
480 : else
481 : return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
482 :
483 499 : case TYPE_SSEMOV:
484 499 : return ix86_output_ssemov (insn, operands);
485 :
486 0 : default:
487 0 : gcc_unreachable ();
488 : }
489 : }
490 : [(set (attr "isa")
491 : (cond [(eq_attr "alternative" "6,9,10")
492 : (const_string "sse2")
493 0 : (eq_attr "alternative" "7")
494 : (const_string "sse4_noavx")
495 : (eq_attr "alternative" "8")
496 : (const_string "avx")
497 : ]
498 : (const_string "*")))
499 : (set (attr "addr")
500 : (if_then_else (eq_attr "alternative" "7")
501 : (const_string "gpr16")
502 : (const_string "*")))
503 : (set (attr "type")
504 : (cond [(eq_attr "alternative" "6,7,8")
505 : (if_then_else (match_test "TARGET_AVX512FP16")
506 : (const_string "ssemov")
507 : (const_string "sselog1"))
508 : (eq_attr "alternative" "4")
509 : (const_string "sselog1")
510 : (eq_attr "alternative" "5,9,10")
511 : (const_string "ssemov")
512 : (match_test "optimize_function_for_size_p (cfun)")
513 : (const_string "imov")
514 : (and (eq_attr "alternative" "0")
515 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
516 0 : (not (match_test "TARGET_HIMODE_MATH"))))
517 : (const_string "imov")
518 : (and (eq_attr "alternative" "1,2")
519 : (match_operand:V2QI 1 "aligned_operand"))
520 24236672 : (const_string "imov")
521 107417021 : (and (match_test "TARGET_MOVX")
522 : (eq_attr "alternative" "0,2"))
523 : (const_string "imovx")
524 20445309 : ]
525 26410587 : (const_string "imov")))
526 26410587 : (set (attr "prefix")
527 26410587 : (cond [(eq_attr "alternative" "4,5,6,7,8,9,10")
528 : (const_string "maybe_evex")
529 0 : ]
530 132065965 : (const_string "orig")))
531 119845909 : (set (attr "mode")
532 93518002 : (cond [(eq_attr "alternative" "6,7,8")
533 77118 : (if_then_else (match_test "TARGET_AVX512FP16")
534 59666 : (const_string "HI")
535 8875581 : (const_string "TI"))
536 92923994 : (eq_attr "alternative" "9,10")
537 17452 : (if_then_else (match_test "TARGET_AVX512FP16")
538 38488297 : (const_string "HI")
539 38488297 : (const_string "SI"))
540 92907219 : (eq_attr "alternative" "4")
541 38488297 : (cond [(match_test "TARGET_AVX")
542 72311 : (const_string "TI")
543 38488297 : (ior (not (match_test "TARGET_SSE2"))
544 127655449 : (match_test "optimize_function_for_size_p (cfun)"))
545 : (const_string "V4SF")
546 5050876 : ]
547 5050876 : (const_string "TI"))
548 5050876 : (eq_attr "alternative" "5")
549 : (cond [(match_test "TARGET_AVX512FP16")
550 : (const_string "HF")
551 : (match_test "TARGET_AVX")
552 : (const_string "TI")
553 76 : (ior (not (match_test "TARGET_SSE2"))
554 76 : (match_test "optimize_function_for_size_p (cfun)"))
555 76 : (const_string "V4SF")
556 : ]
557 26854946 : (const_string "TI"))
558 26854946 : (eq_attr "type" "imovx")
559 26854946 : (const_string "SI")
560 : (and (eq_attr "alternative" "1,2")
561 : (match_operand:V2QI 1 "aligned_operand"))
562 : (const_string "SI")
563 26278872 : (and (eq_attr "alternative" "0")
564 33267 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
565 33267 : (not (match_test "TARGET_HIMODE_MATH"))))
566 33267 : (const_string "SI")
567 26312139 : ]
568 : (const_string "HI")))
569 : (set (attr "preferred_for_speed")
570 : (cond [(eq_attr "alternative" "9")
571 25268654 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
572 : (eq_attr "alternative" "10")
573 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
574 : ]
575 : (symbol_ref "true")))])
576 11830 :
577 11830 : (define_split
578 11830 : [(set (match_operand:V_16_32_64 0 "general_reg_operand")
579 : (match_operand:V_16_32_64 1 "memory_operand"))]
580 26530204 : "reload_completed
581 26537834 : && SYMBOL_REF_P (XEXP (operands[1], 0))
582 26522459 : && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
583 111 : [(set (match_dup 0) (match_dup 1))]
584 61172 : {
585 61172 : rtx op1 = avoid_constant_pool_reference (operands[1]);
586 26317818 :
587 77608 : if (!CONST_VECTOR_P (op1))
588 24881 : FAIL;
589 68546 :
590 24615067 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
591 42386 :
592 42689 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
593 42689 : operands[1] = GEN_INT (val);
594 20792877 : })
595 :
596 : ;; 16-bit, 32-bit and 64-bit constant vector stores. After reload,
597 303 : ;; convert them to immediate integer stores.
598 : (define_insn_and_split "*mov<mode>_imm"
599 : [(set (match_operand:V_16_32_64 0 "memory_operand" "=m")
600 303 : (match_operand:V_16_32_64 1 "x86_64_const_vector_operand" "i"))]
601 41608 : "!TARGET_LCP_STALL || <MODE>mode != V2QImode"
602 : "#"
603 5904891 : "&& reload_completed"
604 5885442 : [(set (match_dup 0) (match_dup 1))]
605 1965041 : {
606 1985742 : rtx op1 = operands[1];
607 110545 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
608 4507394 :
609 4502481 : operands[0] = adjust_address (operands[0], <mmxinsnmode>mode, 0);
610 3944301 : operands[1] = GEN_INT (val);
611 4500368 : })
612 9577062 :
613 9577062 : ;; We always round up to UNITS_PER_WORD bytes.
614 11100556 : (define_insn "*pushv2qi2"
615 : [(set (match_operand:V2QI 0 "push_operand" "=X,X")
616 889390 : (match_operand:V2QI 1 "nonmemory_no_elim_operand" "rC,v"))]
617 21362 : ""
618 454861 : "* return TARGET_64BIT ? \"push{q}\t%q1\" : \"push{l}\t%k1\";
619 454861 : #"
620 454861 : [(set_attr "isa" "*,sse4")
621 : (set_attr "type" "push,multi")
622 69843 : (set (attr "mode")
623 47758 : (cond [(eq_attr "alternative" "0")
624 1257549 : (if_then_else (match_test "TARGET_64BIT")
625 1258440 : (const_string "DI")
626 1257518 : (const_string "SI"))
627 47758 : (eq_attr "alternative" "1")
628 46867 : (if_then_else (match_test "TARGET_AVX512FP16")
629 46867 : (const_string "HI")
630 101826 : (const_string "TI"))
631 101826 : ]
632 101826 : (const_string "HI")))])
633 55417 :
634 : (define_split
635 354 : [(set (match_operand:V2QI 0 "push_operand")
636 354 : (match_operand:V2QI 1 "sse_reg_operand"))]
637 0 : "TARGET_SSE4_1 && reload_completed"
638 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
639 : (set (match_dup 0) (match_dup 1))]
640 0 : {
641 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (V2QImode)));
642 0 : /* Preserve memory attributes. */
643 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
644 0 : })
645 :
646 : (define_expand "movmisalignv2qi"
647 0 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
648 : (match_operand:V2QI 1 "nonimmediate_operand"))]
649 : ""
650 5698 : {
651 5698 : ix86_expand_vector_move (V2QImode, operands);
652 5698 : DONE;
653 19591 : })
654 19591 :
655 19591 : (define_insn "sse_movntq"
656 : [(set (match_operand:DI 0 "memory_operand" "=m,m")
657 3431 : (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
658 0 : UNSPEC_MOVNTQ))]
659 23084 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
660 3431 : && (TARGET_SSE || TARGET_3DNOW_A)"
661 3437 : "@
662 0 : movntq\t{%1, %0|%0, %1}
663 19591 : movnti\t{%1, %0|%0, %1}"
664 1023 : [(set_attr "isa" "*,x64")
665 1023 : (set_attr "mmx_isa" "native,*")
666 27 : (set_attr "type" "mmxmov,ssemov")
667 291 : (set_attr "c86_attr" "movnt")
668 318 : (set_attr "mode" "DI")])
669 0 :
670 27 : (define_expand "movq_<mode>_to_sse"
671 : [(set (match_operand:<mmxdoublevecmode> 0 "register_operand")
672 40491 : (vec_concat:<mmxdoublevecmode>
673 40491 : (match_operand:V24FI 1 "nonimmediate_operand")
674 40491 : (match_dup 2)))]
675 : "TARGET_SSE2"
676 17195 : {
677 17195 : if (<MODE>mode != V2SImode
678 17216 : && !flag_trapping_math)
679 : {
680 10420 : rtx op1 = force_reg (<MODE>mode, operands[1]);
681 10420 : emit_move_insn (operands[0], lowpart_subreg (<mmxdoublevecmode>mode,
682 0 : op1, <MODE>mode));
683 10420 : DONE;
684 : }
685 :
686 6775 : operands[2] = CONST0_RTX (<MODE>mode);
687 : })
688 :
689 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
690 : ;;
691 3478770 : ;; Parallel single-precision floating point arithmetic
692 3471995 : ;;
693 3471995 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
694 3471995 :
695 6775 : (define_expand "<code>v2sf2"
696 : [(set (match_operand:V2SF 0 "register_operand")
697 : (absneg:V2SF
698 3381346 : (match_operand:V2SF 1 "register_operand")))]
699 : "TARGET_MMX_WITH_SSE"
700 519 : "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
701 :
702 3381782 : (define_insn_and_split "*mmx_<code>v2sf2"
703 436 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
704 407 : (absneg:V2SF
705 : (match_operand:V2SF 1 "register_operand" "0,x,x")))
706 3381346 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
707 1204 : "TARGET_MMX_WITH_SSE"
708 29 : "#"
709 166 : "&& reload_completed"
710 : [(set (match_dup 0)
711 95 : (<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
712 2414 : {
713 115 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
714 2362 : std::swap (operands[1], operands[2]);
715 7562 : }
716 7562 : [(set_attr "isa" "noavx,noavx,avx")])
717 5243 :
718 5298 : (define_insn_and_split "*mmx_nabsv2sf2"
719 5215 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
720 : (neg:V2SF
721 : (abs:V2SF
722 83 : (match_operand:V2SF 1 "register_operand" "0,x,x"))))
723 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
724 0 : "TARGET_MMX_WITH_SSE"
725 0 : "#"
726 0 : "&& reload_completed"
727 304 : [(set (match_dup 0)
728 2578 : (ior:V2SF (match_dup 1) (match_dup 2)))]
729 2882 : {
730 2882 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
731 2882 : std::swap (operands[1], operands[2]);
732 2578 : }
733 2578 : [(set_attr "isa" "noavx,noavx,avx")])
734 2578 :
735 2578 : (define_expand "<insn>v2sf3"
736 2578 : [(set (match_operand:V2SF 0 "register_operand")
737 2578 : (plusminusmult:V2SF
738 : (match_operand:V2SF 1 "nonimmediate_operand")
739 0 : (match_operand:V2SF 2 "nonimmediate_operand")))]
740 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
741 6125 : {
742 6125 : rtx op2 = gen_reg_rtx (V4SFmode);
743 6125 : rtx op1 = gen_reg_rtx (V4SFmode);
744 6184 : rtx op0 = gen_reg_rtx (V4SFmode);
745 :
746 193892 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
747 193892 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
748 187767 :
749 193833 : emit_insn (gen_<insn>v4sf3 (op0, op1, op2));
750 187708 :
751 193833 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
752 193833 : DONE;
753 187708 : })
754 :
755 : (define_expand "mmx_addv2sf3"
756 : [(parallel
757 : [(set (match_operand:V2SF 0 "register_operand")
758 : (plus:V2SF
759 : (match_operand:V2SF 1 "nonimmediate_operand")
760 : (match_operand:V2SF 2 "nonimmediate_operand")))
761 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
762 1104 : "TARGET_3DNOW"
763 1121 : "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
764 1104 :
765 : (define_insn "*mmx_addv2sf3"
766 36 : [(set (match_operand:V2SF 0 "register_operand" "=y")
767 17 : (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
768 1123 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
769 36 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
770 100 : "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
771 12 : "pfadd\t{%2, %0|%0, %2}"
772 1104 : [(set_attr "type" "mmxadd")
773 : (set_attr "prefix_extra" "1")
774 296 : (set_attr "mode" "V2SF")])
775 296 :
776 1087 : (define_expand "mmx_subv2sf3"
777 74 : [(parallel
778 287 : [(set (match_operand:V2SF 0 "register_operand")
779 74 : (minus:V2SF (match_operand:V2SF 1 "register_operand")
780 259 : (match_operand:V2SF 2 "nonimmediate_operand")))
781 0 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
782 259 : "TARGET_3DNOW")
783 15 :
784 : (define_expand "mmx_subrv2sf3"
785 152279 : [(parallel
786 152279 : [(set (match_operand:V2SF 0 "register_operand")
787 152279 : (minus:V2SF (match_operand:V2SF 2 "register_operand")
788 152264 : (match_operand:V2SF 1 "nonimmediate_operand")))
789 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
790 : "TARGET_3DNOW")
791 :
792 : (define_insn "*mmx_subv2sf3"
793 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
794 : (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
795 : (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))
796 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
797 285269 : "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
798 285271 : "@
799 285269 : pfsub\t{%2, %0|%0, %2}
800 : pfsubr\t{%1, %0|%0, %1}"
801 : [(set_attr "type" "mmxadd")
802 : (set_attr "prefix_extra" "1")
803 : (set_attr "mode" "V2SF")])
804 :
805 51 : (define_expand "mmx_mulv2sf3"
806 51 : [(parallel
807 51 : [(set (match_operand:V2SF 0 "register_operand")
808 793991 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
809 793991 : (match_operand:V2SF 2 "nonimmediate_operand")))
810 793991 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
811 51 : "TARGET_3DNOW"
812 15 : "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
813 42 :
814 97705 : (define_insn "*mmx_mulv2sf3"
815 : [(set (match_operand:V2SF 0 "register_operand" "=y")
816 15 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
817 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
818 54219 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
819 78 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
820 9 : "pfmul\t{%2, %0|%0, %2}"
821 15 : [(set_attr "type" "mmxmul")
822 : (set_attr "prefix_extra" "1")
823 : (set_attr "mode" "V2SF")])
824 :
825 : (define_expand "divv2sf3"
826 : [(set (match_operand:V2SF 0 "register_operand")
827 424217 : (div:V2SF (match_operand:V2SF 1 "register_operand")
828 424216 : (match_operand:V2SF 2 "register_operand")))]
829 10351 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
830 228 : {
831 136454 : rtx op2 = gen_reg_rtx (V4SFmode);
832 136453 : rtx op1 = gen_reg_rtx (V4SFmode);
833 6304 : rtx op0 = gen_reg_rtx (V4SFmode);
834 :
835 228 : rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
836 : force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
837 6304 : emit_insn (gen_rtx_SET (op2, tmp));
838 228 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
839 :
840 228 : emit_insn (gen_divv4sf3 (op0, op1, op2));
841 :
842 228 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
843 228 : DONE;
844 : })
845 :
846 356255 : (define_expand "<code>v2sf3"
847 356255 : [(set (match_operand:V2SF 0 "register_operand")
848 356255 : (smaxmin:V2SF
849 : (match_operand:V2SF 1 "register_operand")
850 : (match_operand:V2SF 2 "register_operand")))]
851 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
852 135 : {
853 135 : rtx op2 = gen_reg_rtx (V4SFmode);
854 135 : rtx op1 = gen_reg_rtx (V4SFmode);
855 135 : rtx op0 = gen_reg_rtx (V4SFmode);
856 :
857 140 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
858 135 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
859 5 :
860 140 : emit_insn (gen_<code>v4sf3 (op0, op1, op2));
861 5 :
862 135 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
863 135 : DONE;
864 : })
865 :
866 : (define_expand "mmx_<code>v2sf3"
867 : [(parallel
868 : [(set (match_operand:V2SF 0 "register_operand")
869 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
870 : (match_operand:V2SF 2 "nonimmediate_operand")))
871 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
872 : "TARGET_3DNOW"
873 1803562 : {
874 1803562 : if (!flag_finite_math_only || flag_signed_zeros)
875 1803534 : {
876 28 : operands[1] = force_reg (V2SFmode, operands[1]);
877 278 : emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
878 : (operands[0], operands[1], operands[2]));
879 278 : DONE;
880 250 : }
881 250 : else
882 0 : ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
883 : })
884 355261 :
885 355261 : ;; These versions of the min/max patterns are intentionally ignorant of
886 355261 : ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
887 0 : ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
888 : ;; are undefined in this condition, we're certain this is correct.
889 :
890 : (define_insn "*mmx_<code>v2sf3"
891 : [(set (match_operand:V2SF 0 "register_operand" "=y")
892 0 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
893 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
894 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
895 0 : "TARGET_3DNOW && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
896 : "pf<maxmin_float>\t{%2, %0|%0, %2}"
897 12 : [(set_attr "type" "mmxadd")
898 : (set_attr "prefix_extra" "1")
899 12 : (set_attr "mode" "V2SF")])
900 12 :
901 12 : ;; These versions of the min/max patterns implement exactly the operations
902 : ;; min = (op1 < op2 ? op1 : op2)
903 : ;; max = (!(op1 < op2) ? op1 : op2)
904 479352 : ;; Their operands are not commutative, and thus they may be used in the
905 479352 : ;; presence of -0.0 and NaN.
906 :
907 276059 : (define_insn "mmx_ieee_<ieee_maxmin>v2sf3"
908 276059 : [(set (match_operand:V2SF 0 "register_operand" "=y")
909 : (unspec:V2SF
910 : [(match_operand:V2SF 1 "register_operand" "0")
911 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
912 : IEEE_MAXMIN))
913 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
914 63 : "TARGET_3DNOW"
915 : "pf<ieee_maxmin>\t{%2, %0|%0, %2}"
916 : [(set_attr "type" "mmxadd")
917 : (set_attr "prefix_extra" "1")
918 7805 : (set_attr "mode" "V2SF")])
919 326 :
920 7805 : (define_insn "mmx_rcpv2sf2"
921 : [(set (match_operand:V2SF 0 "register_operand" "=y")
922 7479 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
923 7479 : UNSPEC_PFRCP))]
924 7550 : "TARGET_3DNOW"
925 7479 : "pfrcp\t{%1, %0|%0, %1}"
926 7479 : [(set_attr "type" "mmx")
927 : (set_attr "prefix_extra" "1")
928 7557 : (set_attr "mode" "V2SF")])
929 7557 :
930 : (define_insn "mmx_rcpit1v2sf3"
931 7352 : [(set (match_operand:V2SF 0 "register_operand" "=y")
932 7352 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
933 7352 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
934 7274 : UNSPEC_PFRCPIT1))]
935 7425 : "TARGET_3DNOW"
936 7359 : "pfrcpit1\t{%2, %0|%0, %2}"
937 7345 : [(set_attr "type" "mmx")
938 71 : (set_attr "prefix_extra" "1")
939 7368 : (set_attr "mode" "V2SF")])
940 7368 :
941 7274 : (define_insn "mmx_rcpit2v2sf3"
942 7368 : [(set (match_operand:V2SF 0 "register_operand" "=y")
943 7274 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
944 7274 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
945 7274 : UNSPEC_PFRCPIT2))]
946 7354 : "TARGET_3DNOW"
947 14 : "pfrcpit2\t{%2, %0|%0, %2}"
948 6477 : [(set_attr "type" "mmx")
949 : (set_attr "prefix_extra" "1")
950 872 : (set_attr "mode" "V2SF")])
951 872 :
952 778 : (define_expand "sqrtv2sf2"
953 94 : [(set (match_operand:V2SF 0 "register_operand")
954 778 : (sqrt:V2SF (match_operand:V2SF 1 "nonimmediate_operand")))]
955 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
956 8 : {
957 8 : rtx op1 = gen_reg_rtx (V4SFmode);
958 8 : rtx op0 = gen_reg_rtx (V4SFmode);
959 :
960 8 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
961 0 :
962 8 : emit_insn (gen_sqrtv4sf2 (op0, op1));
963 :
964 8 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
965 8 : DONE;
966 : })
967 :
968 : (define_insn "mmx_rsqrtv2sf2"
969 : [(set (match_operand:V2SF 0 "register_operand" "=y")
970 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
971 : UNSPEC_PFRSQRT))]
972 71 : "TARGET_3DNOW"
973 0 : "pfrsqrt\t{%1, %0|%0, %1}"
974 : [(set_attr "type" "mmx")
975 : (set_attr "prefix_extra" "1")
976 2044 : (set_attr "mode" "V2SF")])
977 2044 :
978 175 : (define_insn "mmx_rsqit1v2sf3"
979 210 : [(set (match_operand:V2SF 0 "register_operand" "=y")
980 385 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
981 385 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
982 175 : UNSPEC_PFRSQIT1))]
983 289 : "TARGET_3DNOW"
984 223 : "pfrsqit1\t{%2, %0|%0, %2}"
985 209 : [(set_attr "type" "mmx")
986 : (set_attr "prefix_extra" "1")
987 118998 : (set_attr "mode" "V2SF")])
988 118998 :
989 146 : (define_expand "mmx_haddv2sf3"
990 4739 : [(set (match_operand:V2SF 0 "register_operand")
991 28 : (vec_concat:V2SF
992 : (plus:SF
993 : (vec_select:SF
994 : (match_operand:V2SF 1 "register_operand")
995 : (parallel [(const_int 0)]))
996 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
997 : (plus:SF
998 : (vec_select:SF
999 : (match_operand:V2SF 2 "nonimmediate_operand")
1000 : (parallel [(const_int 0)]))
1001 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1002 : "TARGET_3DNOW")
1003 :
1004 : (define_insn "*mmx_haddv2sf3"
1005 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1006 : (vec_concat:V2SF
1007 : (plus:SF
1008 : (vec_select:SF
1009 : (match_operand:V2SF 1 "register_operand" "0")
1010 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1011 : (vec_select:SF (match_dup 1)
1012 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))
1013 : (plus:SF
1014 : (vec_select:SF
1015 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1016 : (parallel [(match_operand:SI 5 "const_0_to_1_operand")]))
1017 : (vec_select:SF (match_dup 2)
1018 : (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))]
1019 79 : "TARGET_3DNOW
1020 79 : && INTVAL (operands[3]) != INTVAL (operands[4])
1021 79 : && INTVAL (operands[5]) != INTVAL (operands[6])"
1022 0 : "pfacc\t{%2, %0|%0, %2}"
1023 : [(set_attr "type" "mmxadd")
1024 : (set_attr "prefix_extra" "1")
1025 787 : (set_attr "mode" "V2SF")])
1026 787 :
1027 : (define_insn_and_split "*mmx_haddv2sf3_low"
1028 173 : [(set (match_operand:SF 0 "register_operand")
1029 960 : (plus:SF
1030 : (vec_select:SF
1031 173 : (match_operand:V2SF 1 "nonimmediate_operand")
1032 173 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))
1033 173 : (vec_select:SF
1034 173 : (match_dup 1)
1035 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
1036 986 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1037 531 : && INTVAL (operands[2]) != INTVAL (operands[3])
1038 372 : && ix86_pre_reload_split ()"
1039 604 : "#"
1040 159 : "&& 1"
1041 159 : [(const_int 0)]
1042 370 : {
1043 456 : rtx op1 = gen_reg_rtx (V4SFmode);
1044 936 : rtx op0 = gen_reg_rtx (V4SFmode);
1045 831 :
1046 397 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1047 30 :
1048 230 : emit_insn (gen_sse3_haddv4sf3 (op0, op1, op1));
1049 80 :
1050 265 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1051 265 : DONE;
1052 80 : })
1053 :
1054 80 : (define_insn "mmx_hsubv2sf3"
1055 80 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1056 80 : (vec_concat:V2SF
1057 80 : (minus:SF
1058 : (vec_select:SF
1059 : (match_operand:V2SF 1 "register_operand" "0")
1060 : (parallel [(const_int 0)]))
1061 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1062 : (minus:SF
1063 747 : (vec_select:SF
1064 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1065 747 : (parallel [(const_int 0)]))
1066 747 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1067 827 : "TARGET_3DNOW_A"
1068 0 : "pfnacc\t{%2, %0|%0, %2}"
1069 : [(set_attr "type" "mmxadd")
1070 : (set_attr "prefix_extra" "1")
1071 79 : (set_attr "mode" "V2SF")])
1072 79 :
1073 79 : (define_insn_and_split "*mmx_hsubv2sf3_low"
1074 79 : [(set (match_operand:SF 0 "register_operand")
1075 : (minus:SF
1076 79 : (vec_select:SF
1077 79 : (match_operand:V2SF 1 "register_operand")
1078 79 : (parallel [(const_int 0)]))
1079 : (vec_select:SF
1080 79 : (match_dup 1)
1081 79 : (parallel [(const_int 1)]))))]
1082 178 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1083 3 : && ix86_pre_reload_split ()"
1084 127 : "#"
1085 79 : "&& 1"
1086 79 : [(const_int 0)]
1087 19 : {
1088 97 : rtx op1 = gen_reg_rtx (V4SFmode);
1089 412 : rtx op0 = gen_reg_rtx (V4SFmode);
1090 411 :
1091 18 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1092 109 :
1093 125 : emit_insn (gen_sse3_hsubv4sf3 (op0, op1, op1));
1094 79 :
1095 1 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1096 80 : DONE;
1097 79 : })
1098 79 :
1099 : (define_expand "mmx_haddsubv2sf3"
1100 79 : [(set (match_operand:V2SF 0 "register_operand")
1101 79 : (vec_concat:V2SF
1102 79 : (minus:SF
1103 : (vec_select:SF
1104 : (match_operand:V2SF 1 "register_operand")
1105 : (parallel [(const_int 0)]))
1106 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1107 : (plus:SF
1108 13 : (vec_select:SF
1109 : (match_operand:V2SF 2 "nonimmediate_operand")
1110 13 : (parallel [(const_int 0)]))
1111 13 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1112 13 : "TARGET_3DNOW_A")
1113 :
1114 : (define_insn "*mmx_haddsubv2sf3"
1115 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1116 : (vec_concat:V2SF
1117 : (minus:SF
1118 : (vec_select:SF
1119 : (match_operand:V2SF 1 "register_operand" "0")
1120 : (parallel [(const_int 0)]))
1121 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1122 : (plus:SF
1123 : (vec_select:SF
1124 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1125 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1126 : (vec_select:SF
1127 : (match_dup 2)
1128 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))))]
1129 79 : "TARGET_3DNOW_A
1130 79 : && INTVAL (operands[3]) != INTVAL (operands[4])"
1131 0 : "pfpnacc\t{%2, %0|%0, %2}"
1132 : [(set_attr "type" "mmxadd")
1133 : (set_attr "prefix_extra" "1")
1134 : (set_attr "mode" "V2SF")])
1135 :
1136 : (define_expand "vec_addsubv2sf3"
1137 : [(set (match_operand:V2SF 0 "register_operand")
1138 2853239 : (vec_merge:V2SF
1139 2853239 : (minus:V2SF
1140 2853239 : (match_operand:V2SF 1 "nonimmediate_operand")
1141 2853239 : (match_operand:V2SF 2 "nonimmediate_operand"))
1142 2853239 : (plus:V2SF (match_dup 1) (match_dup 2))
1143 2853239 : (const_int 1)))]
1144 2853239 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1145 246 : {
1146 39818 : rtx op2 = gen_reg_rtx (V4SFmode);
1147 39818 : rtx op1 = gen_reg_rtx (V4SFmode);
1148 35128 : rtx op0 = gen_reg_rtx (V4SFmode);
1149 74454 :
1150 246 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1151 33023 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1152 :
1153 29027 : emit_insn (gen_vec_addsubv4sf3 (op0, op1, op2));
1154 :
1155 246 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1156 246 : DONE;
1157 : })
1158 :
1159 : (define_expand "vec_fmaddsubv2sf4"
1160 : [(match_operand:V2SF 0 "register_operand")
1161 : (match_operand:V2SF 1 "nonimmediate_operand")
1162 : (match_operand:V2SF 2 "nonimmediate_operand")
1163 : (match_operand:V2SF 3 "nonimmediate_operand")]
1164 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1165 : && TARGET_MMX_WITH_SSE
1166 : && ix86_partial_vec_fp_math"
1167 5 : {
1168 5 : rtx op3 = gen_reg_rtx (V4SFmode);
1169 5 : rtx op2 = gen_reg_rtx (V4SFmode);
1170 5 : rtx op1 = gen_reg_rtx (V4SFmode);
1171 7 : rtx op0 = gen_reg_rtx (V4SFmode);
1172 :
1173 7 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1174 7 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1175 7 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1176 :
1177 5 : emit_insn (gen_vec_fmaddsubv4sf4 (op0, op1, op2, op3));
1178 :
1179 5 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1180 5 : DONE;
1181 : })
1182 :
1183 : (define_expand "vec_fmsubaddv2sf4"
1184 : [(match_operand:V2SF 0 "register_operand")
1185 : (match_operand:V2SF 1 "nonimmediate_operand")
1186 : (match_operand:V2SF 2 "nonimmediate_operand")
1187 : (match_operand:V2SF 3 "nonimmediate_operand")]
1188 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1189 : && TARGET_MMX_WITH_SSE
1190 : && ix86_partial_vec_fp_math"
1191 4 : {
1192 4 : rtx op3 = gen_reg_rtx (V4SFmode);
1193 4 : rtx op2 = gen_reg_rtx (V4SFmode);
1194 418 : rtx op1 = gen_reg_rtx (V4SFmode);
1195 4 : rtx op0 = gen_reg_rtx (V4SFmode);
1196 414 :
1197 418 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1198 418 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1199 4 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1200 :
1201 4 : emit_insn (gen_vec_fmsubaddv4sf4 (op0, op1, op2, op3));
1202 :
1203 4 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1204 4 : DONE;
1205 : })
1206 :
1207 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1208 : ;;
1209 : ;; Parallel single-precision floating point comparisons
1210 : ;;
1211 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1212 :
1213 : (define_expand "mmx_eqv2sf3"
1214 : [(parallel
1215 : [(set (match_operand:V2SI 0 "register_operand")
1216 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
1217 : (match_operand:V2SF 2 "nonimmediate_operand")))
1218 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
1219 286 : "TARGET_3DNOW"
1220 14 : "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
1221 286 :
1222 0 : (define_insn "*mmx_eqv2sf3"
1223 286 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1224 14 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
1225 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1226 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1227 70 : "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
1228 0 : "pfcmpeq\t{%2, %0|%0, %2}"
1229 14 : [(set_attr "type" "mmxcmp")
1230 : (set_attr "prefix_extra" "1")
1231 : (set_attr "mode" "V2SF")])
1232 :
1233 : (define_insn "mmx_gtv2sf3"
1234 156 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1235 : (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
1236 156 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1237 52084 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1238 226 : "TARGET_3DNOW"
1239 : "pfcmpgt\t{%2, %0|%0, %2}"
1240 : [(set_attr "type" "mmxcmp")
1241 51928 : (set_attr "prefix_extra" "1")
1242 100008 : (set_attr "mode" "V2SF")])
1243 100008 :
1244 100008 : (define_insn "mmx_gev2sf3"
1245 51928 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1246 51928 : (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
1247 51928 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1248 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1249 27374 : "TARGET_3DNOW"
1250 27304 : "pfcmpge\t{%2, %0|%0, %2}"
1251 27304 : [(set_attr "type" "mmxcmp")
1252 27304 : (set_attr "prefix_extra" "1")
1253 27304 : (set_attr "mode" "V2SF")])
1254 27304 :
1255 : (define_expand "vec_cmpv2sfv2si"
1256 656337 : [(set (match_operand:V2SI 0 "register_operand")
1257 656337 : (match_operator:V2SI 1 ""
1258 : [(match_operand:V2SF 2 "nonimmediate_operand")
1259 25 : (match_operand:V2SF 3 "nonimmediate_operand")]))]
1260 25 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1261 186 : {
1262 186 : rtx ops[4];
1263 186 : ops[3] = gen_reg_rtx (V4SFmode);
1264 175 : ops[2] = gen_reg_rtx (V4SFmode);
1265 186 : ops[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), V4SImode, ops[2], ops[3]);
1266 186 : ops[0] = gen_reg_rtx (V4SImode);
1267 11 :
1268 197 : emit_insn (gen_movq_v2sf_to_sse (ops[3], operands[3]));
1269 175 : emit_insn (gen_movq_v2sf_to_sse (ops[2], operands[2]));
1270 11 :
1271 186 : bool ok = ix86_expand_fp_vec_cmp (ops);
1272 186 : gcc_assert (ok);
1273 11 :
1274 186 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, ops[0], V4SImode));
1275 175 : DONE;
1276 : })
1277 :
1278 : (define_insn "@sse4_1_insertps_<mode>"
1279 : [(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v")
1280 : (unspec:V2FI
1281 : [(match_operand:V2FI 2 "nonimmediate_operand" "Yrjm,*xjm,vm")
1282 : (match_operand:V2FI 1 "register_operand" "0,0,v")
1283 : (match_operand:SI 3 "const_0_to_255_operand")]
1284 : UNSPEC_INSERTPS))]
1285 6160 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1286 761 : {
1287 458 : if (MEM_P (operands[2]))
1288 : {
1289 22 : unsigned count_s = INTVAL (operands[3]) >> 6;
1290 132 : if (count_s)
1291 11 : operands[3] = GEN_INT (INTVAL (operands[3]) & 0x3f);
1292 132 : operands[2] = adjust_address_nv (operands[2],
1293 43215 : <mmxscalarmode>mode, count_s * 4);
1294 43325 : }
1295 43673 : switch (which_alternative)
1296 43215 : {
1297 43215 : case 0:
1298 43215 : case 1:
1299 43215 : return "insertps\t{%3, %2, %0|%0, %2, %3}";
1300 43673 : case 2:
1301 43673 : return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
1302 43215 : default:
1303 0 : gcc_unreachable ();
1304 40164 : }
1305 : }
1306 321 : [(set_attr "isa" "noavx,noavx,avx")
1307 321 : (set_attr "addr" "gpr16,gpr16,*")
1308 : (set_attr "type" "sselog")
1309 594 : (set_attr "prefix_data16" "1,1,*")
1310 : (set_attr "prefix_extra" "1")
1311 : (set_attr "length_immediate" "1")
1312 : (set_attr "prefix" "orig,orig,maybe_evex")
1313 : (set_attr "mode" "V4SF")])
1314 :
1315 : (define_insn "*mmx_blendps"
1316 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1317 : (vec_merge:V2SF
1318 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1319 : (match_operand:V2SF 1 "register_operand" "0,0,x")
1320 : (match_operand:SI 3 "const_0_to_3_operand")))]
1321 1784 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1322 : "@
1323 : blendps\t{%3, %2, %0|%0, %2, %3}
1324 : blendps\t{%3, %2, %0|%0, %2, %3}
1325 3 : vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1326 3 : [(set_attr "isa" "noavx,noavx,avx")
1327 : (set_attr "type" "ssemov")
1328 3 : (set_attr "c86_attr" "blend")
1329 : (set_attr "length_immediate" "1")
1330 : (set_attr "prefix_data16" "1,1,*")
1331 : (set_attr "prefix_extra" "1")
1332 : (set_attr "prefix" "orig,orig,vex")
1333 : (set_attr "mode" "V4SF")])
1334 :
1335 : (define_insn "mmx_blendvps"
1336 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1337 : (unspec:V2SF
1338 : [(match_operand:V2SF 1 "register_operand" "0,0,x")
1339 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1340 : (match_operand:V2SF 3 "register_operand" "Yz,Yz,x")]
1341 : UNSPEC_BLENDV))]
1342 181 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1343 : "@
1344 : blendvps\t{%3, %2, %0|%0, %2, %3}
1345 : blendvps\t{%3, %2, %0|%0, %2, %3}
1346 3465 : vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1347 3465 : [(set_attr "isa" "noavx,noavx,avx")
1348 : (set_attr "type" "ssemov")
1349 3465 : (set_attr "c86_attr" "blendv")
1350 : (set_attr "length_immediate" "1")
1351 : (set_attr "prefix_data16" "1,1,*")
1352 : (set_attr "prefix_extra" "1")
1353 : (set_attr "prefix" "orig,orig,vex")
1354 : (set_attr "btver2_decode" "vector")
1355 : (set_attr "mode" "V4SF")])
1356 :
1357 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1358 : ;;
1359 : ;; Parallel single-precision floating point logical operations
1360 : ;;
1361 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1362 :
1363 : (define_insn "*mmx_andnotv2sf3"
1364 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1365 : (and:V2SF
1366 : (not:V2SF
1367 : (match_operand:V2SF 1 "register_operand" "0,x"))
1368 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1369 304 : "TARGET_MMX_WITH_SSE"
1370 152 : "@
1371 : andnps\t{%2, %0|%0, %2}
1372 : vandnps\t{%2, %1, %0|%0, %1, %2}"
1373 0 : [(set_attr "isa" "noavx,avx")
1374 0 : (set_attr "type" "sselog")
1375 : (set_attr "prefix" "orig,vex")
1376 0 : (set_attr "mode" "V4SF")])
1377 :
1378 : (define_insn "<code>v2sf3"
1379 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1380 : (any_logic:V2SF
1381 : (match_operand:V2SF 1 "register_operand" "%0,x")
1382 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1383 852 : "TARGET_MMX_WITH_SSE"
1384 275 : "@
1385 : <logic>ps\t{%2, %0|%0, %2}
1386 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
1387 2 : [(set_attr "isa" "noavx,avx")
1388 2 : (set_attr "type" "sselog")
1389 1 : (set_attr "prefix" "orig,vex")
1390 : (set_attr "mode" "V4SF")])
1391 1 :
1392 : (define_expand "copysignv2sf3"
1393 : [(set (match_dup 4)
1394 : (and:V2SF
1395 : (not:V2SF (match_dup 3))
1396 : (match_operand:V2SF 1 "register_operand")))
1397 : (set (match_dup 5)
1398 : (and:V2SF (match_dup 3)
1399 : (match_operand:V2SF 2 "register_operand")))
1400 : (set (match_operand:V2SF 0 "register_operand")
1401 : (ior:V2SF (match_dup 4) (match_dup 5)))]
1402 : "TARGET_MMX_WITH_SSE"
1403 11 : {
1404 11 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1405 :
1406 11 : operands[4] = gen_reg_rtx (V2SFmode);
1407 11 : operands[5] = gen_reg_rtx (V2SFmode);
1408 : })
1409 :
1410 : (define_expand "xorsignv2sf3"
1411 : [(set (match_dup 4)
1412 11 : (and:V2SF (match_dup 3)
1413 : (match_operand:V2SF 2 "register_operand")))
1414 : (set (match_operand:V2SF 0 "register_operand")
1415 : (xor:V2SF (match_dup 4)
1416 : (match_operand:V2SF 1 "register_operand")))]
1417 : "TARGET_MMX_WITH_SSE"
1418 12 : {
1419 1 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1420 :
1421 1 : operands[4] = gen_reg_rtx (V2SFmode);
1422 : })
1423 5 :
1424 : (define_expand "signbitv2sf2"
1425 5 : [(set (match_operand:V2SI 0 "register_operand")
1426 6 : (lshiftrt:V2SI
1427 5 : (subreg:V2SI
1428 : (match_operand:V2SF 1 "register_operand") 0)
1429 : (match_dup 2)))]
1430 : "TARGET_MMX_WITH_SSE"
1431 2 : {
1432 1 : operands[1] = force_reg (V2SFmode, operands[1]);
1433 1 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);
1434 : })
1435 :
1436 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1437 : ;;
1438 2 : ;; Parallel single-precision FMA multiply/accumulate instructions.
1439 1 : ;;
1440 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1441 :
1442 1 : (define_expand "fmav2sf4"
1443 : [(set (match_operand:V2SF 0 "register_operand")
1444 : (fma:V2SF
1445 : (match_operand:V2SF 1 "nonimmediate_operand")
1446 : (match_operand:V2SF 2 "nonimmediate_operand")
1447 82 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1448 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1449 82 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1450 829 : {
1451 829 : rtx op3 = gen_reg_rtx (V4SFmode);
1452 747 : rtx op2 = gen_reg_rtx (V4SFmode);
1453 747 : rtx op1 = gen_reg_rtx (V4SFmode);
1454 747 : rtx op0 = gen_reg_rtx (V4SFmode);
1455 :
1456 747 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1457 747 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1458 747 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1459 :
1460 747 : emit_insn (gen_fmav4sf4 (op0, op1, op2, op3));
1461 :
1462 747 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1463 747 : DONE;
1464 : })
1465 :
1466 : (define_expand "fmsv2sf4"
1467 : [(set (match_operand:V2SF 0 "register_operand")
1468 : (fma:V2SF
1469 : (match_operand:V2SF 1 "nonimmediate_operand")
1470 : (match_operand:V2SF 2 "nonimmediate_operand")
1471 : (neg:V2SF
1472 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1473 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1474 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1475 13 : {
1476 13 : rtx op3 = gen_reg_rtx (V4SFmode);
1477 32 : rtx op2 = gen_reg_rtx (V4SFmode);
1478 13 : rtx op1 = gen_reg_rtx (V4SFmode);
1479 32 : rtx op0 = gen_reg_rtx (V4SFmode);
1480 19 :
1481 32 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1482 13 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1483 13 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1484 :
1485 13 : emit_insn (gen_fmsv4sf4 (op0, op1, op2, op3));
1486 :
1487 13 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1488 13 : DONE;
1489 : })
1490 :
1491 : (define_expand "fnmav2sf4"
1492 : [(set (match_operand:V2SF 0 "register_operand")
1493 : (fma:V2SF
1494 : (neg:V2SF
1495 : (match_operand:V2SF 1 "nonimmediate_operand"))
1496 : (match_operand:V2SF 2 "nonimmediate_operand")
1497 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1498 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1499 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1500 156 : {
1501 156 : rtx op3 = gen_reg_rtx (V4SFmode);
1502 156 : rtx op2 = gen_reg_rtx (V4SFmode);
1503 1239 : rtx op1 = gen_reg_rtx (V4SFmode);
1504 156 : rtx op0 = gen_reg_rtx (V4SFmode);
1505 1083 :
1506 156 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1507 1239 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1508 156 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1509 :
1510 156 : emit_insn (gen_fnmav4sf4 (op0, op1, op2, op3));
1511 :
1512 156 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1513 156 : DONE;
1514 : })
1515 :
1516 : (define_expand "fnmsv2sf4"
1517 : [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1518 : (fma:V2SF
1519 : (neg:V2SF
1520 : (match_operand:V2SF 1 "nonimmediate_operand"))
1521 : (match_operand:V2SF 2 "nonimmediate_operand")
1522 : (neg:V2SF
1523 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1524 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1525 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1526 2 : {
1527 3 : rtx op3 = gen_reg_rtx (V4SFmode);
1528 2 : rtx op2 = gen_reg_rtx (V4SFmode);
1529 3 : rtx op1 = gen_reg_rtx (V4SFmode);
1530 3 : rtx op0 = gen_reg_rtx (V4SFmode);
1531 1 :
1532 2 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1533 2 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1534 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1535 :
1536 2 : emit_insn (gen_fnmsv4sf4 (op0, op1, op2, op3));
1537 :
1538 2 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1539 2 : DONE;
1540 : })
1541 :
1542 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1543 : ;;
1544 : ;; Parallel single-precision floating point conversion operations
1545 : ;;
1546 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1547 :
1548 : (define_expand "fix_truncv2sfv2si2"
1549 : [(set (match_operand:V2SI 0 "register_operand")
1550 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1551 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1552 82 : {
1553 82 : rtx op1 = gen_reg_rtx (V4SFmode);
1554 83 : rtx op0 = gen_reg_rtx (V4SImode);
1555 :
1556 83 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1557 1 :
1558 83 : emit_insn (gen_fix_truncv4sfv4si2 (op0, op1));
1559 :
1560 82 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1561 82 : DONE;
1562 : })
1563 :
1564 : (define_expand "fixuns_truncv2sfv2si2"
1565 : [(set (match_operand:V2SI 0 "register_operand")
1566 : (unsigned_fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1567 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1568 1 : {
1569 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1570 1 : rtx op0 = gen_reg_rtx (V4SImode);
1571 :
1572 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1573 :
1574 1 : emit_insn (gen_fixuns_truncv4sfv4si2 (op0, op1));
1575 87 :
1576 1 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1577 88 : DONE;
1578 0 : })
1579 87 :
1580 : (define_insn "mmx_fix_truncv2sfv2si2"
1581 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1582 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))
1583 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1584 54 : "TARGET_3DNOW"
1585 0 : "pf2id\t{%1, %0|%0, %1}"
1586 : [(set_attr "type" "mmxcvt")
1587 : (set_attr "prefix_extra" "1")
1588 : (set_attr "mode" "V2SF")])
1589 :
1590 2607 : (define_expand "floatv2siv2sf2"
1591 : [(set (match_operand:V2SF 0 "register_operand")
1592 2607 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1593 2607 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1594 63585557 : {
1595 414 : rtx op1 = gen_reg_rtx (V4SImode);
1596 414 : rtx op0 = gen_reg_rtx (V4SFmode);
1597 :
1598 63582950 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1599 63582536 :
1600 63582950 : emit_insn (gen_floatv4siv4sf2 (op0, op1));
1601 63582536 :
1602 414 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1603 62454120 : DONE;
1604 62453706 : })
1605 62453706 :
1606 62453706 : (define_expand "floatunsv2siv2sf2"
1607 : [(set (match_operand:V2SF 0 "register_operand")
1608 62446014 : (unsigned_float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1609 62446014 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1610 62446019 : {
1611 5 : rtx op1 = gen_reg_rtx (V4SImode);
1612 62446019 : rtx op0 = gen_reg_rtx (V4SFmode);
1613 :
1614 39512652 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1615 39512647 :
1616 6 : emit_insn (gen_floatunsv4siv4sf2 (op0, op1));
1617 39510156 :
1618 39510162 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1619 39510162 : DONE;
1620 39510157 : })
1621 :
1622 39500245 : (define_insn "mmx_floatv2siv2sf2"
1623 78666961 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1624 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))
1625 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1626 66 : "TARGET_3DNOW"
1627 0 : "pi2fd\t{%1, %0|%0, %1}"
1628 : [(set_attr "type" "mmxcvt")
1629 : (set_attr "prefix_extra" "1")
1630 : (set_attr "mode" "V2SF")])
1631 :
1632 1 : (define_insn "mmx_pf2iw"
1633 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1634 1 : (sign_extend:V2SI
1635 1 : (ss_truncate:V2HI
1636 72 : (fix:V2SI
1637 : (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
1638 70 : "TARGET_3DNOW_A"
1639 : "pf2iw\t{%1, %0|%0, %1}"
1640 71 : [(set_attr "type" "mmxcvt")
1641 71 : (set_attr "prefix_extra" "1")
1642 34716 : (set_attr "mode" "V2SF")])
1643 34716 :
1644 34645 : (define_insn "mmx_pi2fw"
1645 70 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1646 34715 : (float:V2SF
1647 34645 : (sign_extend:V2SI
1648 34695 : (truncate:V2HI
1649 50 : (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
1650 11201 : "TARGET_3DNOW_A"
1651 11135 : "pi2fw\t{%1, %0|%0, %1}"
1652 12002 : [(set_attr "type" "mmxcvt")
1653 50 : (set_attr "prefix_extra" "1")
1654 50 : (set_attr "mode" "V2SF")])
1655 :
1656 28 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1657 : ;;
1658 0 : ;; Parallel single-precision floating point element swizzling
1659 0 : ;;
1660 268313 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1661 :
1662 : (define_insn "mmx_pswapdv2sf2"
1663 : [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv")
1664 268313 : (vec_select:V2SF
1665 268313 : (match_operand:V2SF 1 "register_mmxmem_operand" "ym,0,Yv")
1666 268313 : (parallel [(const_int 1) (const_int 0)])))]
1667 7179 : "TARGET_3DNOW_A || TARGET_MMX_WITH_SSE"
1668 268313 : "@
1669 268313 : pswapd\t{%1, %0|%0, %1}
1670 : shufps\t{$0xe1, %1, %0|%0, %1, 0xe1}
1671 190707 : vshufps\t{$0xe1, %1, %1, %0|%0, %1, %1, 0xe1}"
1672 4108 : [(set_attr "isa" "*,sse_noavx,avx")
1673 4108 : (set_attr "mmx_isa" "native,*,*")
1674 186599 : (set_attr "type" "mmxcvt,ssemov,ssemov")
1675 186599 : (set_attr "prefix_extra" "1,*,*")
1676 186599 : (set_attr "mode" "V2SF,V4SF,V4SF")])
1677 :
1678 186598 : (define_insn "*mmx_movshdup"
1679 186598 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1680 186598 : (vec_select:V2SF
1681 186598 : (match_operand:V2SF 1 "register_operand" "v,0")
1682 186598 : (parallel [(const_int 1) (const_int 1)])))]
1683 3910 : "TARGET_MMX_WITH_SSE"
1684 3379 : "@
1685 3379 : %vmovshdup\t{%1, %0|%0, %1}
1686 3379 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}"
1687 3379 : [(set_attr "isa" "sse3,*")
1688 3379 : (set_attr "type" "sse,sseshuf1")
1689 6758 : (set_attr "length_immediate" "*,1")
1690 : (set_attr "prefix_rep" "1,*")
1691 : (set_attr "prefix" "maybe_vex,orig")
1692 : (set_attr "mode" "V4SF")])
1693 4608 :
1694 4608 : (define_insn "*mmx_movsldup"
1695 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1696 4177 : (vec_select:V2SF
1697 4177 : (match_operand:V2SF 1 "register_operand" "v,0")
1698 4144 : (parallel [(const_int 0) (const_int 0)])))]
1699 8117 : "TARGET_MMX_WITH_SSE"
1700 : "@
1701 : %vmovsldup\t{%1, %0|%0, %1}
1702 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1703 423 : [(set_attr "isa" "sse3,*")
1704 423 : (set_attr "type" "sse,sseshuf1")
1705 423 : (set_attr "length_immediate" "*,1")
1706 843 : (set_attr "prefix_rep" "1,*")
1707 : (set_attr "prefix" "maybe_vex,orig")
1708 : (set_attr "mode" "V4SF")])
1709 :
1710 : (define_insn_and_split "*vec_interleave_lowv2sf"
1711 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1712 : (vec_select:V2SF
1713 : (vec_concat:V4SF
1714 : (match_operand:V2SF 1 "register_operand" "0,v")
1715 : (match_operand:V2SF 2 "register_operand" "x,v"))
1716 : (parallel [(const_int 0) (const_int 2)])))]
1717 6995 : "TARGET_MMX_WITH_SSE"
1718 : "#"
1719 572 : "&& reload_completed"
1720 286 : [(const_int 0)]
1721 14507 : "ix86_split_mmx_punpck (operands, false); DONE;"
1722 14221 : [(set_attr "isa" "noavx,avx")
1723 724 : (set_attr "type" "sselog")
1724 724 : (set_attr "prefix" "orig,maybe_evex")
1725 : (set_attr "mode" "V4SF")])
1726 :
1727 : (define_insn_and_split "*vec_interleave_highv2sf"
1728 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1729 : (vec_select:V2SF
1730 : (vec_concat:V4SF
1731 : (match_operand:V2SF 1 "register_operand" "0,v")
1732 3190 : (match_operand:V2SF 2 "register_operand" "x,v"))
1733 : (parallel [(const_int 1) (const_int 3)])))]
1734 6042 : "TARGET_MMX_WITH_SSE"
1735 3190 : "#"
1736 3410 : "&& reload_completed"
1737 110 : [(const_int 0)]
1738 7561 : "ix86_split_mmx_punpck (operands, true); DONE;"
1739 7451 : [(set_attr "isa" "noavx,avx")
1740 552 : (set_attr "type" "sselog")
1741 552 : (set_attr "prefix" "orig,vex")
1742 : (set_attr "mode" "V4SF")])
1743 :
1744 : (define_insn "*vec_dupv2sf"
1745 : [(set (match_operand:V2SF 0 "register_operand" "=y,Yv,x")
1746 : (vec_duplicate:V2SF
1747 : (match_operand:SF 1 "register_operand" "0,Yv,0")))]
1748 6882 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1749 422 : "@
1750 : punpckldq\t%0, %0
1751 1 : %vmovsldup\t{%1, %0|%0, %1}
1752 38 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1753 38 : [(set_attr "isa" "*,sse3,sse_noavx")
1754 32 : (set_attr "mmx_isa" "native,*,*")
1755 32 : (set_attr "type" "mmxcvt,sse,sseshuf1")
1756 69 : (set_attr "length_immediate" "*,*,1")
1757 : (set_attr "prefix_rep" "*,1,*")
1758 : (set_attr "prefix" "*,maybe_vex,orig")
1759 : (set_attr "mode" "DI,V4SF,V4SF")])
1760 :
1761 : (define_insn "*mmx_movss_<mode>"
1762 : [(set (match_operand:V2FI 0 "register_operand" "=x,v")
1763 : (vec_merge:V2FI
1764 : (match_operand:V2FI 2 "register_operand" " x,v")
1765 : (match_operand:V2FI 1 "register_operand" " 0,v")
1766 : (const_int 1)))]
1767 4192 : "TARGET_MMX_WITH_SSE"
1768 1504 : "@
1769 : movss\t{%2, %0|%0, %2}
1770 : vmovss\t{%2, %1, %0|%0, %1, %2}"
1771 3377 : [(set_attr "isa" "noavx,avx")
1772 3377 : (set_attr "type" "ssemov")
1773 : (set_attr "prefix" "orig,maybe_evex")
1774 3377 : (set_attr "mode" "SF")])
1775 714505 :
1776 714505 : (define_insn "*mmx_concatv2sf"
1777 714505 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
1778 714505 : (vec_concat:V2SF
1779 714505 : (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
1780 714505 : (match_operand:SF 2 "nonimm_or_0_operand" "ym,C")))]
1781 743286 : "TARGET_MMX && !TARGET_SSE"
1782 714505 : "@
1783 28781 : punpckldq\t{%2, %0|%0, %2}
1784 703349 : movd\t{%1, %0|%0, %1}"
1785 : [(set_attr "type" "mmxcvt,mmxmov")
1786 270 : (set_attr "mode" "DI")])
1787 270 :
1788 : (define_expand "vec_setv2sf"
1789 : [(match_operand:V2SF 0 "register_operand")
1790 270 : (match_operand:SF 1 "register_operand")
1791 : (match_operand 2 "vec_setm_mmx_operand")]
1792 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1793 19 : {
1794 19 : if (CONST_INT_P (operands[2]))
1795 17 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
1796 17 : INTVAL (operands[2]));
1797 : else
1798 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
1799 19 : DONE;
1800 : })
1801 :
1802 : ;; Avoid combining registers from different units in a single alternative,
1803 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1804 : (define_insn_and_split "*vec_extractv2sf_0"
1805 : [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
1806 : (vec_select:SF
1807 : (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
1808 : (parallel [(const_int 0)])))]
1809 2959 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1810 23330 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1811 : "#"
1812 2909 : "&& reload_completed"
1813 1083 : [(set (match_dup 0) (match_dup 1))]
1814 82865 : "operands[1] = gen_lowpart (SFmode, operands[1]);"
1815 81782 : [(set_attr "mmx_isa" "*,*,native,native,*,*")])
1816 13740 :
1817 14822 : ;; Avoid combining registers from different units in a single alternative,
1818 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1819 : (define_insn "*vec_extractv2sf_1"
1820 1083 : [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,x,y,x,f,r")
1821 : (vec_select:SF
1822 : (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,0,o,o,o,o")
1823 : (parallel [(const_int 1)])))]
1824 16782 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1825 16784 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1826 : "@
1827 2 : punpckhdq\t%0, %0
1828 2 : %vmovshdup\t{%1, %0|%0, %1}
1829 18620 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
1830 18618 : #
1831 18454 : #
1832 37072 : #
1833 : #"
1834 18321 : [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
1835 : (set_attr "mmx_isa" "native,*,*,native,*,*,*")
1836 : (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
1837 : (set (attr "length_immediate")
1838 : (if_then_else (eq_attr "alternative" "2")
1839 : (const_string "1")
1840 : (const_string "*")))
1841 : (set (attr "prefix_rep")
1842 : (if_then_else (eq_attr "alternative" "1")
1843 : (const_string "1")
1844 : (const_string "*")))
1845 : (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
1846 : (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
1847 :
1848 : (define_split
1849 : [(set (match_operand:SF 0 "register_operand")
1850 : (vec_select:SF
1851 : (match_operand:V2SF 1 "memory_operand")
1852 : (parallel [(const_int 1)])))]
1853 105 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
1854 87 : [(set (match_dup 0) (match_dup 1))]
1855 87 : "operands[1] = adjust_address (operands[1], SFmode, 4);")
1856 :
1857 6675 : (define_expand "vec_extractv2sfsf"
1858 6762 : [(match_operand:SF 0 "register_operand")
1859 5312 : (match_operand:V2SF 1 "register_operand")
1860 5312 : (match_operand 2 "const_int_operand")]
1861 6762 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1862 3190 : {
1863 3190 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
1864 3190 : operands[1], INTVAL (operands[2]));
1865 3190 : DONE;
1866 1 : })
1867 :
1868 1 : (define_expand "vec_initv2sfsf"
1869 1 : [(match_operand:V2SF 0 "register_operand")
1870 1 : (match_operand 1)]
1871 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
1872 2607 : {
1873 2607 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
1874 : operands[1]);
1875 2607 : DONE;
1876 : })
1877 :
1878 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1879 : ;;
1880 1 : ;; Parallel single-precision floating point rounding operations.
1881 1 : ;;
1882 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1883 :
1884 : (define_expand "nearbyintv2sf2"
1885 : [(match_operand:V2SF 0 "register_operand")
1886 : (match_operand:V2SF 1 "nonimmediate_operand")]
1887 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1888 2 : {
1889 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1890 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1891 1 :
1892 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1893 :
1894 1 : emit_insn (gen_nearbyintv4sf2 (op0, op1));
1895 :
1896 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1897 1 : DONE;
1898 : })
1899 :
1900 : (define_expand "rintv2sf2"
1901 : [(match_operand:V2SF 0 "register_operand")
1902 : (match_operand:V2SF 1 "nonimmediate_operand")]
1903 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1904 1 : {
1905 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1906 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1907 :
1908 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1909 :
1910 123 : emit_insn (gen_rintv4sf2 (op0, op1));
1911 :
1912 123 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1913 123 : DONE;
1914 122 : })
1915 :
1916 : (define_expand "lrintv2sfv2si2"
1917 : [(match_operand:V2SI 0 "register_operand")
1918 : (match_operand:V2SF 1 "nonimmediate_operand")]
1919 : "TARGET_SSE4_1 && !flag_trapping_math
1920 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1921 1 : {
1922 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1923 1 : rtx op0 = gen_reg_rtx (V4SImode);
1924 :
1925 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1926 8 :
1927 1 : emit_insn (gen_lrintv4sfv4si2 (op0, op1));
1928 8 :
1929 9 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1930 9 : DONE;
1931 : })
1932 :
1933 : (define_expand "ceilv2sf2"
1934 : [(match_operand:V2SF 0 "register_operand")
1935 : (match_operand:V2SF 1 "nonimmediate_operand")]
1936 : "TARGET_SSE4_1 && !flag_trapping_math
1937 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1938 1 : {
1939 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1940 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1941 :
1942 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1943 4 :
1944 1 : emit_insn (gen_ceilv4sf2 (op0, op1));
1945 4 :
1946 5 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1947 5 : DONE;
1948 : })
1949 :
1950 : (define_expand "lceilv2sfv2si2"
1951 : [(match_operand:V2SI 0 "register_operand")
1952 : (match_operand:V2SF 1 "nonimmediate_operand")]
1953 : "TARGET_SSE4_1 && !flag_trapping_math
1954 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1955 1 : {
1956 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1957 1 : rtx op0 = gen_reg_rtx (V4SImode);
1958 :
1959 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1960 0 :
1961 1 : emit_insn (gen_lceilv4sfv4si2 (op0, op1));
1962 0 :
1963 1 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1964 1 : DONE;
1965 : })
1966 :
1967 : (define_expand "floorv2sf2"
1968 : [(match_operand:V2SF 0 "register_operand")
1969 : (match_operand:V2SF 1 "nonimmediate_operand")]
1970 : "TARGET_SSE4_1 && !flag_trapping_math
1971 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1972 2 : {
1973 2 : rtx op1 = gen_reg_rtx (V4SFmode);
1974 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1975 :
1976 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1977 5 :
1978 2 : emit_insn (gen_floorv4sf2 (op0, op1));
1979 5 :
1980 7 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1981 2 : DONE;
1982 : })
1983 :
1984 5 : (define_expand "lfloorv2sfv2si2"
1985 : [(match_operand:V2SI 0 "register_operand")
1986 : (match_operand:V2SF 1 "nonimmediate_operand")]
1987 : "TARGET_SSE4_1 && !flag_trapping_math
1988 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1989 10 : {
1990 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1991 10 : rtx op0 = gen_reg_rtx (V4SImode);
1992 9 :
1993 10 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1994 0 :
1995 1 : emit_insn (gen_lfloorv4sfv4si2 (op0, op1));
1996 0 :
1997 1 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1998 1 : DONE;
1999 : })
2000 :
2001 0 : (define_expand "btruncv2sf2"
2002 : [(match_operand:V2SF 0 "register_operand")
2003 : (match_operand:V2SF 1 "nonimmediate_operand")]
2004 : "TARGET_SSE4_1 && !flag_trapping_math
2005 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2006 5 : {
2007 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2008 5 : rtx op0 = gen_reg_rtx (V4SFmode);
2009 4 :
2010 5 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2011 0 :
2012 1 : emit_insn (gen_btruncv4sf2 (op0, op1));
2013 0 :
2014 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2015 1 : DONE;
2016 : })
2017 :
2018 0 : (define_expand "roundv2sf2"
2019 : [(match_operand:V2SF 0 "register_operand")
2020 : (match_operand:V2SF 1 "nonimmediate_operand")]
2021 : "TARGET_SSE4_1 && !flag_trapping_math
2022 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2023 2 : {
2024 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2025 2 : rtx op0 = gen_reg_rtx (V4SFmode);
2026 1 :
2027 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2028 12 :
2029 1 : emit_insn (gen_roundv4sf2 (op0, op1));
2030 12 :
2031 13 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2032 13 : DONE;
2033 : })
2034 :
2035 : (define_expand "lroundv2sfv2si2"
2036 : [(match_operand:V2SI 0 "register_operand")
2037 : (match_operand:V2SF 1 "nonimmediate_operand")]
2038 : "TARGET_SSE4_1 && !flag_trapping_math
2039 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2040 1 : {
2041 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2042 1 : rtx op0 = gen_reg_rtx (V4SImode);
2043 :
2044 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2045 4 :
2046 1 : emit_insn (gen_lroundv4sfv4si2 (op0, op1));
2047 4 :
2048 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
2049 5 : DONE;
2050 : })
2051 :
2052 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2053 : ;;
2054 : ;; Parallel half-precision floating point arithmetic
2055 : ;;
2056 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2057 :
2058 : (define_mode_iterator VHF_32_64 [V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2059 :
2060 : (define_mode_iterator VBF_32_64 [V2BF (V4BF "TARGET_MMX_WITH_SSE")])
2061 :
2062 4 : (define_expand "divv4hf3"
2063 : [(set (match_operand:V4HF 0 "register_operand")
2064 4 : (div:V4HF
2065 4 : (match_operand:V4HF 1 "nonimmediate_operand")
2066 4 : (match_operand:V4HF 2 "register_operand")))]
2067 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math
2068 : && TARGET_MMX_WITH_SSE"
2069 8 : {
2070 8 : rtx op2 = gen_reg_rtx (V8HFmode);
2071 8 : rtx op1 = gen_reg_rtx (V8HFmode);
2072 8 : rtx op0 = gen_reg_rtx (V8HFmode);
2073 :
2074 8 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2075 8 : rtx tmp = gen_rtx_VEC_CONCAT (V8HFmode, operands[2],
2076 : force_reg (V4HFmode, CONST1_RTX (V4HFmode)));
2077 8 : emit_insn (gen_rtx_SET (op2, tmp));
2078 8 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2079 8 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2080 8 : DONE;
2081 : })
2082 :
2083 : (define_mode_attr mov_to_sse_suffix
2084 : [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")])
2085 :
2086 : (define_mode_attr mmxxmmmode
2087 : [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")
2088 : (V4HF "V8HF") (V4HI "V8HI") (V4BF "V8BF")
2089 : (V2SF "V4SF") (V2SI "V4SI")])
2090 :
2091 : (define_mode_attr mmxxmmmodelower
2092 : [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")
2093 : (V4HF "v8hf") (V4HI "v8hi") (V4BF "v8bf")
2094 2 : (V2SF "v4sf") (V2SI "v4si")])
2095 :
2096 2 : (define_expand "movd_<mode>_to_sse"
2097 2 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2098 2 : (vec_merge:<mmxxmmmode>
2099 : (vec_duplicate:<mmxxmmmode>
2100 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2101 : (match_dup 2)
2102 : (const_int 3)))]
2103 : "TARGET_SSE"
2104 126 : {
2105 126 : if (!flag_trapping_math)
2106 : {
2107 13 : rtx op1 = force_reg (<MODE>mode, operands[1]);
2108 13 : emit_move_insn (operands[0],
2109 : lowpart_subreg (<mmxxmmmode>mode, op1, <MODE>mode));
2110 13 : DONE;
2111 : }
2112 113 : operands[2] = CONST0_RTX (<mmxxmmmode>mode);
2113 : })
2114 :
2115 : (define_expand "movd_<mode>_to_sse_reg"
2116 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2117 113 : (vec_merge:<mmxxmmmode>
2118 : (vec_duplicate:<mmxxmmmode>
2119 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2120 : (match_operand:<mmxxmmmode> 2 "register_operand")
2121 113 : (const_int 3)))]
2122 : "TARGET_SSE")
2123 :
2124 : (define_expand "<insn><mode>3"
2125 : [(set (match_operand:VHF_32_64 0 "register_operand")
2126 6 : (plusminusmult:VHF_32_64
2127 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2128 6 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2129 6 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2130 39 : {
2131 37 : rtx op2 = gen_reg_rtx (V8HFmode);
2132 37 : rtx op1 = gen_reg_rtx (V8HFmode);
2133 37 : rtx op0 = gen_reg_rtx (V8HFmode);
2134 :
2135 37 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2136 37 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2137 37 : emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
2138 :
2139 37 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2140 37 : DONE;
2141 : })
2142 :
2143 : ;; VDIVNEPBF16 does not generate floating point exceptions.
2144 : (define_expand "<insn><mode>3"
2145 : [(set (match_operand:VBF_32_64 0 "register_operand")
2146 : (plusminusmultdiv:VBF_32_64
2147 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2148 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2149 26 : "TARGET_AVX10_2"
2150 10 : {
2151 15 : rtx op0 = gen_reg_rtx (V8BFmode);
2152 10 : rtx op1 = lowpart_subreg (V8BFmode,
2153 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2154 16 : rtx op2 = lowpart_subreg (V8BFmode,
2155 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2156 11 :
2157 21 : emit_insn (gen_<insn>v8bf3 (op0, op1, op2));
2158 11 :
2159 10 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2160 10 : DONE;
2161 : })
2162 :
2163 : (define_expand "divv2hf3"
2164 : [(set (match_operand:V2HF 0 "register_operand")
2165 : (div:V2HF
2166 : (match_operand:V2HF 1 "nonimmediate_operand")
2167 : (match_operand:V2HF 2 "nonimmediate_operand")))]
2168 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2169 5 : {
2170 5 : rtx op2 = gen_reg_rtx (V8HFmode);
2171 5 : rtx op1 = gen_reg_rtx (V8HFmode);
2172 5 : rtx op0 = gen_reg_rtx (V8HFmode);
2173 :
2174 13 : emit_insn (gen_movd_v2hf_to_sse_reg (op2, operands[2],
2175 : force_reg (V8HFmode, CONST1_RTX (V8HFmode))));
2176 13 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
2177 13 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2178 8 :
2179 5 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
2180 5 : DONE;
2181 : })
2182 :
2183 : (define_expand "<code><mode>3"
2184 : [(set (match_operand:VHF_32_64 0 "register_operand")
2185 : (smaxmin:VHF_32_64
2186 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2187 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2188 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2189 4 : {
2190 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2191 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2192 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2193 :
2194 5 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2195 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2196 1 :
2197 5 : emit_insn (gen_<code>v8hf3 (op0, op1, op2));
2198 1 :
2199 4 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2200 4 : DONE;
2201 : })
2202 :
2203 : (define_expand "<code><mode>3"
2204 : [(set (match_operand:VBF_32_64 0 "register_operand")
2205 : (smaxmin:VBF_32_64
2206 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2207 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2208 : "TARGET_AVX10_2"
2209 4 : {
2210 4 : rtx op0 = gen_reg_rtx (V8BFmode);
2211 4 : rtx op1 = lowpart_subreg (V8BFmode,
2212 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2213 4 : rtx op2 = lowpart_subreg (V8BFmode,
2214 2 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2215 :
2216 6 : emit_insn (gen_<code>v8bf3 (op0, op1, op2));
2217 2 :
2218 6 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2219 4 : DONE;
2220 : })
2221 :
2222 : (define_expand "sqrt<mode>2"
2223 : [(set (match_operand:VHF_32_64 0 "register_operand")
2224 : (sqrt:VHF_32_64
2225 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
2226 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2227 2 : {
2228 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2229 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2230 :
2231 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2232 2 : emit_insn (gen_sqrtv8hf2 (op0, op1));
2233 6 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2234 3 : DONE;
2235 4 : })
2236 5 :
2237 4 : (define_expand "sqrt<mode>2"
2238 1 : [(set (match_operand:VBF_32_64 0 "register_operand")
2239 : (sqrt:VBF_32_64 (match_operand:VBF_32_64 1 "vector_operand")))]
2240 : "TARGET_AVX10_2"
2241 0 : {
2242 0 : rtx op0 = gen_reg_rtx (V8BFmode);
2243 0 : rtx op1 = lowpart_subreg (V8BFmode,
2244 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2245 :
2246 0 : emit_insn (gen_sqrtv8bf2 (op0, op1));
2247 3 :
2248 1 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2249 3 : DONE;
2250 4 : })
2251 3 :
2252 1 : (define_mode_iterator VHBF_32_64
2253 18 : [V2BF (V4BF "TARGET_MMX_WITH_SSE")
2254 51 : V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2255 24 :
2256 : (define_expand "<code><mode>2"
2257 95 : [(set (match_operand:VHBF_32_64 0 "register_operand")
2258 4844 : (absneg:VHBF_32_64
2259 2514 : (match_operand:VHBF_32_64 1 "register_operand")))]
2260 2698 : "TARGET_SSE"
2261 434 : "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
2262 4504 :
2263 2 : (define_insn_and_split "*mmx_<code><mode>"
2264 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2265 2 : (absneg:VHBF_32_64
2266 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x")))
2267 2 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2268 64 : "TARGET_SSE"
2269 0 : "#"
2270 4 : "&& reload_completed"
2271 : [(set (match_dup 0)
2272 36 : (<absneg_op>:<MODE> (match_dup 1) (match_dup 2)))]
2273 38 : {
2274 33 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
2275 42 : std::swap (operands[1], operands[2]);
2276 9 : }
2277 2 : [(set_attr "isa" "noavx,noavx,avx")])
2278 7 :
2279 11 : (define_insn_and_split "*mmx_nabs<mode>2"
2280 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2281 : (neg:VHBF_32_64
2282 : (abs:VHBF_32_64
2283 11 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x"))))
2284 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2285 0 : "TARGET_SSE"
2286 0 : "#"
2287 0 : "&& reload_completed"
2288 53 : [(set (match_dup 0)
2289 0 : (ior:<MODE> (match_dup 1) (match_dup 2)))])
2290 53 :
2291 53 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2292 53 : ;;
2293 0 : ;; Parallel half-precision floating point comparisons
2294 0 : ;;
2295 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2296 :
2297 : (define_expand "vec_cmpv4hfqi"
2298 0 : [(set (match_operand:QI 0 "register_operand")
2299 : (match_operator:QI 1 ""
2300 : [(match_operand:V4HF 2 "nonimmediate_operand")
2301 : (match_operand:V4HF 3 "nonimmediate_operand")]))]
2302 : "TARGET_MMX_WITH_SSE && TARGET_AVX512FP16 && TARGET_AVX512VL
2303 37 : && ix86_partial_vec_fp_math"
2304 17 : {
2305 54 : rtx ops[4];
2306 54 : ops[3] = gen_reg_rtx (V8HFmode);
2307 54 : ops[2] = gen_reg_rtx (V8HFmode);
2308 :
2309 17 : emit_insn (gen_movq_v4hf_to_sse (ops[3], operands[3]));
2310 17 : emit_insn (gen_movq_v4hf_to_sse (ops[2], operands[2]));
2311 17 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2312 17 : DONE;
2313 : })
2314 :
2315 : (define_expand "vcond_mask_<mode>v4hi"
2316 : [(set (match_operand:V4F_64 0 "register_operand")
2317 : (vec_merge:V4F_64
2318 : (match_operand:V4F_64 1 "vector_or_const_vector_operand")
2319 : (match_operand:V4F_64 2 "vector_or_const_vector_operand")
2320 : (match_operand:V4HI 3 "register_operand")))]
2321 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
2322 18 : {
2323 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2324 : operands[1], operands[2]);
2325 18 : DONE;
2326 0 : })
2327 :
2328 0 : (define_expand "vcond_mask_<mode>qi"
2329 0 : [(set (match_operand:V4FI_64 0 "register_operand")
2330 0 : (vec_merge:V4FI_64
2331 : (match_operand:V4FI_64 1 "register_operand")
2332 : (match_operand:V4FI_64 2 "register_operand")
2333 : (match_operand:QI 3 "register_operand")))]
2334 : "TARGET_MMX_WITH_SSE && TARGET_AVX512BW && TARGET_AVX512VL"
2335 22 : {
2336 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2337 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2338 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2339 25 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2340 : operands[2], operands[3]));
2341 25 : emit_move_insn (operands[0],
2342 3 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2343 25 : DONE;
2344 : })
2345 :
2346 : (define_expand "vcond_mask_<mode>qi"
2347 : [(set (match_operand:V2FI 0 "register_operand")
2348 : (vec_merge:V2FI
2349 : (match_operand:V2FI 1 "register_operand")
2350 : (match_operand:V2FI 2 "register_operand")
2351 : (match_operand:QI 3 "register_operand")))]
2352 : "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
2353 1 : {
2354 1 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2355 1 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2356 1 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2357 29 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2358 : operands[2], operands[3]));
2359 29 : emit_move_insn (operands[0],
2360 28 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2361 29 : DONE;
2362 : })
2363 :
2364 : (define_expand "vec_cmpv2hfqi"
2365 : [(set (match_operand:QI 0 "register_operand")
2366 : (match_operator:QI 1 ""
2367 : [(match_operand:V2HF 2 "nonimmediate_operand")
2368 : (match_operand:V2HF 3 "nonimmediate_operand")]))]
2369 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2370 : && ix86_partial_vec_fp_math"
2371 17 : {
2372 17 : rtx ops[4];
2373 17 : ops[3] = gen_reg_rtx (V8HFmode);
2374 17 : ops[2] = gen_reg_rtx (V8HFmode);
2375 2 :
2376 17 : emit_insn (gen_movd_v2hf_to_sse (ops[3], operands[3]));
2377 19 : emit_insn (gen_movd_v2hf_to_sse (ops[2], operands[2]));
2378 19 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2379 19 : DONE;
2380 : })
2381 :
2382 : (define_expand "vcond_mask_<mode>v2hi"
2383 : [(set (match_operand:V2F_32 0 "register_operand")
2384 : (vec_merge:V2F_32
2385 : (match_operand:V2F_32 1 "vector_or_const_vector_operand")
2386 : (match_operand:V2F_32 2 "vector_or_const_vector_operand")
2387 : (match_operand:V2HI 3 "register_operand")))]
2388 : "TARGET_SSE4_1"
2389 18 : {
2390 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2391 : operands[1], operands[2]);
2392 18 : DONE;
2393 1 : })
2394 :
2395 1 : (define_expand "vcond_mask_<mode>qi"
2396 1 : [(set (match_operand:V2FI_32 0 "register_operand")
2397 1 : (vec_merge:V2FI_32
2398 : (match_operand:V2FI_32 1 "register_operand")
2399 : (match_operand:V2FI_32 2 "register_operand")
2400 : (match_operand:QI 3 "register_operand")))]
2401 : "TARGET_AVX512BW && TARGET_AVX512VL"
2402 22 : {
2403 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2404 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2405 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2406 28 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2407 : operands[2], operands[3]));
2408 28 : emit_move_insn (operands[0],
2409 6 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2410 28 : DONE;
2411 : })
2412 :
2413 : ;;This instruction does not generate floating point exceptions
2414 : (define_expand "vec_cmp<mode>qi"
2415 : [(set (match_operand:QI 0 "register_operand")
2416 : (match_operator:QI 1 ""
2417 : [(match_operand:VBF_32_64 2 "register_operand")
2418 : (match_operand:VBF_32_64 3 "nonimmediate_operand")]))]
2419 : "TARGET_AVX10_2"
2420 10 : {
2421 10 : rtx op2 = lowpart_subreg (V8BFmode,
2422 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2423 10 : rtx op3 = lowpart_subreg (V8BFmode,
2424 1 : force_reg (<MODE>mode, operands[3]), <MODE>mode);
2425 :
2426 11 : emit_insn (gen_vec_cmpv8bfqi (operands[0], operands[1], op2, op3));
2427 11 : DONE;
2428 1 : })
2429 :
2430 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2431 : ;;
2432 : ;; Parallel half-precision floating point rounding operations.
2433 : ;;
2434 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2435 :
2436 : (define_expand "btrunc<mode>2"
2437 : [(match_operand:VHF_32_64 0 "register_operand")
2438 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2439 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2440 : && ix86_partial_vec_fp_math
2441 1 : && !flag_trapping_math"
2442 2 : {
2443 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2444 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2445 1 :
2446 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2447 2 : emit_insn (gen_btruncv8hf2 (op0, op1));
2448 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2449 :
2450 2 : DONE;
2451 : })
2452 :
2453 : (define_expand "nearbyint<mode>2"
2454 : [(match_operand:VHF_32_64 0 "register_operand")
2455 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2456 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2457 : && ix86_partial_vec_fp_math"
2458 2 : {
2459 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2460 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2461 :
2462 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2463 3 : emit_insn (gen_nearbyintv8hf2 (op0, op1));
2464 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2465 1 :
2466 3 : DONE;
2467 1 : })
2468 :
2469 : (define_expand "rint<mode>2"
2470 : [(match_operand:VHF_32_64 0 "register_operand")
2471 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2472 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2473 : && ix86_partial_vec_fp_math"
2474 2 : {
2475 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2476 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2477 :
2478 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2479 4 : emit_insn (gen_rintv8hf2 (op0, op1));
2480 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2481 2 :
2482 4 : DONE;
2483 2 : })
2484 :
2485 : (define_expand "lrint<mode><mmxintvecmodelower>2"
2486 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2487 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2488 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2489 : && ix86_partial_vec_fp_math"
2490 0 : {
2491 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2492 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2493 :
2494 0 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2495 0 : emit_insn (gen_lrintv8hfv8hi2 (op0, op1));
2496 0 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2497 0 :
2498 0 : DONE;
2499 0 : })
2500 :
2501 : (define_expand "floor<mode>2"
2502 : [(match_operand:VHF_32_64 0 "register_operand")
2503 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2504 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2505 : && ix86_partial_vec_fp_math
2506 : && !flag_trapping_math"
2507 2 : {
2508 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2509 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2510 :
2511 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2512 2 : emit_insn (gen_floorv8hf2 (op0, op1));
2513 4 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2514 2 :
2515 4 : DONE;
2516 : })
2517 :
2518 : (define_expand "lfloor<mode><mmxintvecmodelower>2"
2519 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2520 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2521 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2522 : && ix86_partial_vec_fp_math
2523 : && !flag_trapping_math"
2524 0 : {
2525 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2526 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2527 :
2528 0 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2529 0 : emit_insn (gen_lfloorv8hfv8hi2 (op0, op1));
2530 0 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2531 0 :
2532 0 : DONE;
2533 : })
2534 :
2535 : (define_expand "ceil<mode>2"
2536 : [(match_operand:VHF_32_64 0 "register_operand")
2537 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2538 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2539 : && ix86_partial_vec_fp_math
2540 : && !flag_trapping_math"
2541 2 : {
2542 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2543 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2544 :
2545 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2546 2 : emit_insn (gen_ceilv8hf2 (op0, op1));
2547 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2548 0 :
2549 2 : DONE;
2550 : })
2551 :
2552 : (define_expand "lceil<mode><mmxintvecmodelower>2"
2553 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2554 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2555 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2556 : && ix86_partial_vec_fp_math
2557 : && !flag_trapping_math"
2558 0 : {
2559 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2560 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2561 :
2562 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2563 0 : emit_insn (gen_lceilv8hfv8hi2 (op0, op1));
2564 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2565 2 :
2566 2 : DONE;
2567 : })
2568 :
2569 : (define_expand "round<mode>2"
2570 : [(match_operand:VHF_32_64 0 "register_operand")
2571 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2572 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2573 : && ix86_partial_vec_fp_math
2574 : && !flag_trapping_math"
2575 2 : {
2576 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2577 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2578 :
2579 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2580 2 : emit_insn (gen_roundv8hf2 (op0, op1));
2581 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2582 0 :
2583 2 : DONE;
2584 : })
2585 :
2586 : (define_expand "lround<mode><mmxintvecmodelower>2"
2587 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2588 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2589 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2590 : && ix86_partial_vec_fp_math
2591 : && !flag_trapping_math"
2592 0 : {
2593 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2594 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2595 :
2596 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2597 0 : emit_insn (gen_lroundv8hfv8hi2 (op0, op1));
2598 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2599 2 :
2600 2 : DONE;
2601 : })
2602 :
2603 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2604 : ;;
2605 : ;; Parallel half-precision floating point logical operations
2606 : ;;
2607 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2608 :
2609 : (define_insn "*mmx_andnot<mode>3"
2610 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2611 : (and:VHBF_32_64
2612 : (not:VHBF_32_64
2613 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x"))
2614 : (match_operand:VHBF_32_64 2 "register_operand" "x,x")))]
2615 2 : "TARGET_SSE"
2616 0 : "@
2617 0 : andnps\t{%2, %0|%0, %2}
2618 : vandnps\t{%2, %1, %0|%0, %1, %2}"
2619 2 : [(set_attr "isa" "noavx,avx")
2620 2 : (set_attr "type" "sselog")
2621 : (set_attr "prefix" "orig,vex")
2622 2 : (set_attr "mode" "V4SF")])
2623 :
2624 : (define_insn "<code><mode>3"
2625 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2626 : (any_logic:VHBF_32_64
2627 : (match_operand:VHBF_32_64 1 "register_operand" "%0,x")
2628 : (match_operand:VHBF_32_64 2 "register_operand" " x,x")))]
2629 47 : "TARGET_SSE"
2630 24 : "@
2631 : <logic>ps\t{%2, %0|%0, %2}
2632 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
2633 56 : [(set_attr "isa" "noavx,avx")
2634 56 : (set_attr "type" "sselog,sselog")
2635 42 : (set_attr "prefix" "orig,vex")
2636 : (set_attr "mode" "V4SF")])
2637 42 :
2638 : (define_expand "copysign<mode>3"
2639 : [(set (match_dup 4)
2640 : (and:VHBF_32_64
2641 : (not:VHBF_32_64 (match_dup 3))
2642 : (match_operand:VHBF_32_64 1 "register_operand")))
2643 : (set (match_dup 5)
2644 : (and:VHBF_32_64 (match_dup 3)
2645 : (match_operand:VHBF_32_64 2 "register_operand")))
2646 : (set (match_operand:VHBF_32_64 0 "register_operand")
2647 : (ior:VHBF_32_64 (match_dup 4) (match_dup 5)))]
2648 : "TARGET_SSE"
2649 2 : {
2650 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2651 :
2652 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2653 2 : operands[5] = gen_reg_rtx (<MODE>mode);
2654 : })
2655 :
2656 : (define_expand "xorsign<mode>3"
2657 : [(set (match_dup 4)
2658 2 : (and:VHBF_32_64 (match_dup 3)
2659 : (match_operand:VHBF_32_64 2 "register_operand")))
2660 : (set (match_operand:VHBF_32_64 0 "register_operand")
2661 : (xor:VHBF_32_64 (match_dup 4)
2662 : (match_operand:VHBF_32_64 1 "register_operand")))]
2663 : "TARGET_SSE"
2664 4 : {
2665 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2666 :
2667 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2668 : })
2669 2 :
2670 : (define_expand "signbit<mode>2"
2671 2 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
2672 4 : (lshiftrt:<mmxintvecmode>
2673 2 : (subreg:<mmxintvecmode>
2674 : (match_operand:VHBF_32_64 1 "register_operand") 0)
2675 : (match_dup 2)))]
2676 : "TARGET_SSE2"
2677 2 : {
2678 0 : operands[1] = force_reg (<MODE>mode, operands[1]);
2679 0 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);
2680 : })
2681 :
2682 5 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2683 : ;;
2684 5 : ;; Parallel half-precision FMA multiply/accumulate instructions.
2685 5 : ;;
2686 5 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2687 :
2688 0 : (define_expand "fma<mode>4"
2689 : [(set (match_operand:VHF_32_64 0 "register_operand")
2690 : (fma:VHF_32_64
2691 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2692 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2693 4 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2694 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2695 7 : {
2696 7 : rtx op3 = gen_reg_rtx (V8HFmode);
2697 7 : rtx op2 = gen_reg_rtx (V8HFmode);
2698 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2699 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2700 :
2701 3 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2702 3 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2703 3 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2704 :
2705 3 : emit_insn (gen_fmav8hf4 (op0, op1, op2, op3));
2706 :
2707 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2708 3 : DONE;
2709 : })
2710 :
2711 : (define_expand "fms<mode>4"
2712 : [(set (match_operand:VHF_32_64 0 "register_operand")
2713 : (fma:VHF_32_64
2714 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2715 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2716 : (neg:VHF_32_64
2717 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2718 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2719 2 : {
2720 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2721 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2722 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2723 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2724 2 :
2725 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2726 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2727 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2728 :
2729 2 : emit_insn (gen_fmsv8hf4 (op0, op1, op2, op3));
2730 :
2731 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2732 2 : DONE;
2733 : })
2734 :
2735 : (define_expand "fnma<mode>4"
2736 : [(set (match_operand:VHF_32_64 0 "register_operand")
2737 : (fma:VHF_32_64
2738 : (neg:VHF_32_64
2739 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2740 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2741 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2742 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2743 2 : {
2744 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2745 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2746 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2747 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2748 2 :
2749 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2750 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2751 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2752 :
2753 2 : emit_insn (gen_fnmav8hf4 (op0, op1, op2, op3));
2754 :
2755 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2756 2 : DONE;
2757 : })
2758 :
2759 : (define_expand "fnms<mode>4"
2760 : [(set (match_operand:VHF_32_64 0 "register_operand" "=v,v,x")
2761 : (fma:VHF_32_64
2762 : (neg:VHF_32_64
2763 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2764 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2765 : (neg:VHF_32_64
2766 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2767 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2768 2 : {
2769 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2770 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2771 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2772 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2773 2 :
2774 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2775 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2776 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2777 :
2778 2 : emit_insn (gen_fnmsv8hf4 (op0, op1, op2, op3));
2779 :
2780 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2781 2 : DONE;
2782 : })
2783 :
2784 : (define_expand "vec_fmaddsubv4hf4"
2785 : [(match_operand:V4HF 0 "register_operand")
2786 : (match_operand:V4HF 1 "nonimmediate_operand")
2787 : (match_operand:V4HF 2 "nonimmediate_operand")
2788 : (match_operand:V4HF 3 "nonimmediate_operand")]
2789 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2790 : && TARGET_MMX_WITH_SSE
2791 : && ix86_partial_vec_fp_math"
2792 1 : {
2793 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2794 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2795 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2796 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2797 :
2798 3 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2799 3 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2800 3 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2801 :
2802 1 : emit_insn (gen_vec_fmaddsubv8hf4 (op0, op1, op2, op3));
2803 :
2804 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2805 1 : DONE;
2806 : })
2807 :
2808 : (define_expand "vec_fmsubaddv4hf4"
2809 : [(match_operand:V4HF 0 "register_operand")
2810 : (match_operand:V4HF 1 "nonimmediate_operand")
2811 : (match_operand:V4HF 2 "nonimmediate_operand")
2812 : (match_operand:V4HF 3 "nonimmediate_operand")]
2813 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2814 : && ix86_partial_vec_fp_math
2815 : && TARGET_MMX_WITH_SSE"
2816 1 : {
2817 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2818 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2819 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2820 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2821 1 :
2822 2 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2823 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2824 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2825 :
2826 1 : emit_insn (gen_vec_fmsubaddv8hf4 (op0, op1, op2, op3));
2827 :
2828 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2829 1 : DONE;
2830 : })
2831 :
2832 : (define_expand "fma<mode>4"
2833 : [(set (match_operand:VBF_32_64 0 "register_operand")
2834 : (fma:VBF_32_64
2835 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2836 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2837 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2838 : "TARGET_AVX10_2"
2839 2 : {
2840 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2841 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2842 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2843 3 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2844 :
2845 3 : emit_insn (gen_fmav8bf4 (op0, op1, op2, op3));
2846 1 :
2847 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2848 2 : DONE;
2849 : })
2850 :
2851 : (define_expand "fms<mode>4"
2852 : [(set (match_operand:VBF_32_64 0 "register_operand")
2853 : (fma:VBF_32_64
2854 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2855 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2856 : (neg:VBF_32_64
2857 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2858 : "TARGET_AVX10_2"
2859 2 : {
2860 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2861 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2862 4 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2863 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2864 2 :
2865 4 : emit_insn (gen_fmsv8bf4 (op0, op1, op2, op3));
2866 2 :
2867 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2868 2 : DONE;
2869 : })
2870 :
2871 : (define_expand "fnma<mode>4"
2872 : [(set (match_operand:VBF_32_64 0 "register_operand")
2873 : (fma:VBF_32_64
2874 : (neg:VBF_32_64
2875 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2876 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2877 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2878 : "TARGET_AVX10_2"
2879 2 : {
2880 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2881 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2882 6 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2883 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2884 4 :
2885 6 : emit_insn (gen_fnmav8bf4 (op0, op1, op2, op3));
2886 4 :
2887 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2888 2 : DONE;
2889 : })
2890 :
2891 : (define_expand "fnms<mode>4"
2892 : [(set (match_operand:VBF_32_64 0 "register_operand")
2893 : (fma:VBF_32_64
2894 : (neg:VBF_32_64
2895 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2896 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2897 : (neg:VBF_32_64
2898 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2899 : "TARGET_AVX10_2"
2900 2 : {
2901 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2902 6 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2903 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2904 6 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2905 4 :
2906 6 : emit_insn (gen_fnmsv8bf4 (op0, op1, op2, op3));
2907 :
2908 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2909 2 : DONE;
2910 : })
2911 :
2912 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2913 : ;;
2914 : ;; Parallel half-precision floating point complex type operations
2915 : ;;
2916 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2917 :
2918 : (define_expand "cmlav4hf4"
2919 : [(match_operand:V4HF 0 "register_operand")
2920 : (match_operand:V4HF 1 "vector_operand")
2921 : (match_operand:V4HF 2 "vector_operand")
2922 : (match_operand:V4HF 3 "vector_operand")]
2923 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2924 2 : && TARGET_MMX_WITH_SSE"
2925 1 : {
2926 3 : rtx op3 = gen_reg_rtx (V8HFmode);
2927 3 : rtx op2 = gen_reg_rtx (V8HFmode);
2928 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2929 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2930 :
2931 1 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2932 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2933 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2934 :
2935 1 : emit_insn (gen_cmlav8hf4 (op0, op1, op2, op3));
2936 :
2937 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2938 1 : DONE;
2939 : })
2940 :
2941 : (define_expand "cmla_conjv4hf4"
2942 : [(match_operand:V4HF 0 "register_operand")
2943 : (match_operand:V4HF 1 "vector_operand")
2944 : (match_operand:V4HF 2 "vector_operand")
2945 : (match_operand:V4HF 3 "vector_operand")]
2946 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2947 : && TARGET_MMX_WITH_SSE"
2948 1 : {
2949 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2950 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2951 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2952 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2953 :
2954 4 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2955 4 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2956 4 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2957 :
2958 1 : emit_insn (gen_cmla_conjv8hf4 (op0, op1, op2, op3));
2959 :
2960 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2961 1 : DONE;
2962 : })
2963 :
2964 : (define_expand "cmulv4hf3"
2965 : [(match_operand:V4HF 0 "register_operand")
2966 : (match_operand:V4HF 1 "vector_operand")
2967 : (match_operand:V4HF 2 "vector_operand")]
2968 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2969 : && TARGET_MMX_WITH_SSE"
2970 1 : {
2971 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2972 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2973 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2974 :
2975 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2976 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2977 1 :
2978 2 : emit_insn (gen_cmulv8hf3 (op0, op1, op2));
2979 2 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2980 1 : DONE;
2981 : })
2982 :
2983 : (define_expand "cmul_conjv4hf3"
2984 : [(match_operand:V4HF 0 "register_operand")
2985 : (match_operand:V4HF 1 "vector_operand")
2986 : (match_operand:V4HF 2 "vector_operand")]
2987 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2988 : && TARGET_MMX_WITH_SSE"
2989 1 : {
2990 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2991 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2992 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2993 1 :
2994 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2995 2 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2996 1 :
2997 2 : emit_insn (gen_cmul_conjv8hf3 (op0, op1, op2));
2998 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2999 1 : DONE;
3000 : })
3001 :
3002 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3003 : ;;
3004 : ;; Parallel half-precision floating point conversion operations
3005 : ;;
3006 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3007 :
3008 : (define_expand "fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2"
3009 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
3010 : (any_fix:<mmxintvecmode>
3011 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
3012 1 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
3013 8 : {
3014 9 : rtx op1 = gen_reg_rtx (V8HFmode);
3015 9 : rtx op0 = gen_reg_rtx (V8HImode);
3016 1 :
3017 8 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
3018 :
3019 8 : emit_insn (gen_fix<fixunssuffix>_truncv8hfv8hi2 (op0, op1));
3020 :
3021 8 : emit_move_insn (operands[0],
3022 : lowpart_subreg (<mmxintvecmode>mode, op0, V8HImode));
3023 8 : DONE;
3024 : })
3025 :
3026 : (define_expand "fix<fixunssuffix>_truncv2hfv2si2"
3027 : [(set (match_operand:V2SI 0 "register_operand")
3028 : (any_fix:V2SI
3029 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3030 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3031 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3032 2 : {
3033 2 : rtx op1 = gen_reg_rtx (V8HFmode);
3034 2 : rtx op0 = gen_reg_rtx (V4SImode);
3035 :
3036 8 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3037 :
3038 8 : emit_insn (gen_avx512fp16_fix<fixunssuffix>_truncv4si2 (op0, op1));
3039 6 :
3040 8 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
3041 2 : DONE;
3042 : })
3043 :
3044 : (define_expand "float<floatunssuffix><mmxintvecmodelower><mode>2"
3045 : [(set (match_operand:VHF_32_64 0 "register_operand")
3046 : (any_float:VHF_32_64
3047 : (match_operand:<mmxintvecmode> 1 "nonimmediate_operand")))]
3048 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
3049 8 : {
3050 8 : rtx op1 = gen_reg_rtx (V8HImode);
3051 8 : rtx op0 = gen_reg_rtx (V8HFmode);
3052 :
3053 8 : rtx (*gen_movd_sse) (rtx, rtx)
3054 4 : = gen_mov<mov_to_sse_suffix>_<mmxintvecmodelower>_to_sse;
3055 8 : emit_insn (gen_movd_sse (op1, operands[1]));
3056 4 :
3057 12 : emit_insn (gen_float<floatunssuffix>v8hiv8hf2 (op0, op1));
3058 4 :
3059 8 : emit_move_insn (operands[0],
3060 : lowpart_subreg (<MODE>mode, op0, V8HFmode));
3061 8 : DONE;
3062 : })
3063 :
3064 : (define_expand "float<floatunssuffix>v2siv2hf2"
3065 : [(set (match_operand:V2HF 0 "register_operand")
3066 : (any_float:V2HF
3067 : (match_operand:V2SI 1 "nonimmediate_operand")))]
3068 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3069 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3070 2 : {
3071 2 : rtx op1 = gen_reg_rtx (V4SImode);
3072 2 : rtx op0 = gen_reg_rtx (V8HFmode);
3073 :
3074 107 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
3075 :
3076 107 : emit_insn (gen_avx512fp16_float<floatunssuffix>v4siv4hf2 (op0, op1));
3077 105 :
3078 107 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3079 2 : DONE;
3080 : })
3081 :
3082 : (define_expand "extendv2hfv2sf2"
3083 : [(set (match_operand:V2SF 0 "register_operand")
3084 : (float_extend:V2SF
3085 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3086 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3087 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3088 1 : {
3089 1 : rtx op1 = gen_reg_rtx (V8HFmode);
3090 1 : rtx op0 = gen_reg_rtx (V4SFmode);
3091 :
3092 6 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3093 9 :
3094 6 : emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1));
3095 14 :
3096 6 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3097 10 : DONE;
3098 : })
3099 :
3100 : (define_expand "truncv2sfv2hf2"
3101 : [(set (match_operand:V2HF 0 "register_operand")
3102 : (float_truncate:V2HF
3103 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3104 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3105 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3106 1 : {
3107 1 : rtx op1 = gen_reg_rtx (V4SFmode);
3108 1 : rtx op0 = gen_reg_rtx (V8HFmode);
3109 :
3110 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
3111 0 :
3112 1 : emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1));
3113 0 :
3114 1 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3115 1 : DONE;
3116 : })
3117 :
3118 : (define_expand "truncv2sfv2bf2"
3119 : [(set (match_operand:V2BF 0 "register_operand")
3120 : (float_truncate:V2BF
3121 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3122 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE
3123 : && !HONOR_NANS (BFmode) && !flag_rounding_math
3124 : && (flag_unsafe_math_optimizations
3125 : || TARGET_AVXNECONVERT
3126 : || (TARGET_AVX512BF16 && TARGET_AVX512VL))"
3127 2 : {
3128 35 : rtx op1 = gen_reg_rtx (V4SFmode);
3129 2 : rtx op0 = gen_reg_rtx (V4BFmode);
3130 33 :
3131 35 : emit_move_insn (op1, lowpart_subreg (V4SFmode,
3132 33 : force_reg (V2SFmode, operands[1]),
3133 : V2SFmode));
3134 2 : emit_insn (gen_truncv4sfv4bf2 (op0, op1));
3135 :
3136 2 : emit_move_insn (operands[0], lowpart_subreg (V2BFmode, op0, V4BFmode));
3137 2 : DONE;
3138 : })
3139 :
3140 : (define_expand "extendv2bfv2sf2"
3141 : [(set (match_operand:V2SF 0 "register_operand")
3142 : (float_extend:V2SF
3143 : (match_operand:V2BF 1 "nonimmediate_operand")))]
3144 : "TARGET_SSE2 && TARGET_MMX_WITH_SSE && !HONOR_NANS (BFmode)"
3145 2 : {
3146 2 : rtx op0 = gen_reg_rtx (V4SFmode);
3147 2 : rtx op1 = gen_reg_rtx (V4BFmode);
3148 :
3149 2 : emit_move_insn (op1, lowpart_subreg (V4BFmode,
3150 33 : force_reg (V2BFmode, operands[1]),
3151 : V2BFmode));
3152 35 : emit_insn (gen_extendv4bfv4sf2 (op0, op1));
3153 33 :
3154 35 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3155 2 : DONE;
3156 : })
3157 :
3158 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3159 : ;;
3160 : ;; Parallel integral arithmetic
3161 : ;;
3162 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3163 :
3164 : (define_expand "neg<mode>2"
3165 : [(set (match_operand:MMXMODEI 0 "register_operand")
3166 : (minus:MMXMODEI
3167 : (match_dup 2)
3168 33 : (match_operand:MMXMODEI 1 "register_operand")))]
3169 : "TARGET_MMX_WITH_SSE"
3170 129 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3171 33 :
3172 33 : (define_expand "neg<mode>2"
3173 : [(set (match_operand:VI_32 0 "register_operand")
3174 96 : (minus:VI_32
3175 : (match_dup 2)
3176 : (match_operand:VI_32 1 "register_operand")))]
3177 : "TARGET_SSE2"
3178 110 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3179 :
3180 : (define_insn "negv2qi2"
3181 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,&Yw")
3182 14 : (neg:V2QI
3183 109 : (match_operand:V2QI 1 "register_operand" "0,Yw")))
3184 : (clobber (reg:CC FLAGS_REG))]
3185 225 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3186 131 : "#"
3187 122 : [(set_attr "isa" "*,sse2")
3188 13 : (set_attr "type" "multi")
3189 : (set_attr "mode" "QI,TI")
3190 : (set (attr "enabled")
3191 46 : (cond [(and (eq_attr "alternative" "0")
3192 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3193 38146 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3194 38147 : (symbol_ref "false")
3195 47 : ]
3196 5873 : (const_string "*")))])
3197 5874 :
3198 1 : (define_split
3199 : [(set (match_operand:V2QI 0 "general_reg_operand")
3200 : (neg:V2QI
3201 : (match_operand:V2QI 1 "general_reg_operand")))
3202 : (clobber (reg:CC FLAGS_REG))]
3203 9 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3204 9 : && reload_completed"
3205 9 : [(parallel
3206 9 : [(set (strict_low_part (match_dup 0))
3207 0 : (neg:QI (match_dup 1)))
3208 9 : (clobber (reg:CC FLAGS_REG))])
3209 : (parallel
3210 : [(set (zero_extract:HI (match_dup 2) (const_int 8) (const_int 8))
3211 : (subreg:HI
3212 : (neg:QI
3213 : (subreg:QI
3214 : (zero_extract:HI (match_dup 3)
3215 : (const_int 8)
3216 : (const_int 8)) 0)) 0))
3217 : (clobber (reg:CC FLAGS_REG))])]
3218 9 : {
3219 9 : operands[3] = lowpart_subreg (HImode, operands[1], V2QImode);
3220 9 : operands[2] = lowpart_subreg (HImode, operands[0], V2QImode);
3221 9 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3222 9 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3223 : })
3224 :
3225 : (define_split
3226 9 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3227 : (neg:V2QI
3228 : (match_operand:V2QI 1 "sse_reg_operand")))
3229 : (clobber (reg:CC FLAGS_REG))]
3230 0 : "TARGET_SSE2 && reload_completed"
3231 : [(set (match_dup 0) (match_dup 2))
3232 0 : (set (match_dup 0)
3233 : (minus:V16QI (match_dup 0) (match_dup 1)))]
3234 3562 : {
3235 3571 : operands[2] = CONST0_RTX (V16QImode);
3236 0 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3237 54 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3238 108 : })
3239 :
3240 : (define_expand "mmx_<insn><mode>3"
3241 51 : [(set (match_operand:MMXMODEI8 0 "register_operand")
3242 : (plusminus:MMXMODEI8
3243 51 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand")
3244 0 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))]
3245 51 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3246 254 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3247 :
3248 : (define_expand "<insn><mode>3"
3249 : [(set (match_operand:MMXMODEI 0 "register_operand")
3250 380 : (plusminus:MMXMODEI
3251 : (match_operand:MMXMODEI 1 "register_operand")
3252 126 : (match_operand:MMXMODEI 2 "register_operand")))]
3253 126 : "TARGET_MMX_WITH_SSE")
3254 254 :
3255 : (define_insn "*mmx_<insn><mode>3"
3256 : [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,<Yv_Yw>")
3257 126 : (plusminus:MMXMODEI8
3258 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand"
3259 10748 : "<comm>0,0,<Yv_Yw>")
3260 168 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand"
3261 10748 : "ym,x,<Yv_Yw>")))]
3262 22290 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3263 128003 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3264 56015 : "@
3265 35 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3266 10783 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3267 167576 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3268 167576 : [(set_attr "isa" "*,sse2_noavx,avx")
3269 167576 : (set_attr "mmx_isa" "native,*,*")
3270 : (set_attr "type" "mmxadd,sseadd,sseadd")
3271 284703 : (set_attr "mode" "DI,TI,TI")])
3272 :
3273 173 : (define_insn "<insn><mode>3"
3274 173 : [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
3275 173 : (plusminus:VI_32
3276 : (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
3277 : (match_operand:VI_32 2 "register_operand" "x,Yw")))]
3278 10428 : "TARGET_SSE2"
3279 5459 : "@
3280 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3281 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3282 13684 : [(set_attr "isa" "noavx,avx")
3283 1698 : (set_attr "type" "sseadd")
3284 11986 : (set_attr "mode" "TI")])
3285 1698 :
3286 13684 : (define_insn "<insn>v2qi3"
3287 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,x,Yw")
3288 1698 : (plusminus:V2QI
3289 : (match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
3290 : (match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
3291 : (clobber (reg:CC FLAGS_REG))]
3292 2194 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3293 768 : "#"
3294 560 : [(set_attr "isa" "*,sse2_noavx,avx")
3295 560 : (set_attr "type" "multi,sseadd,sseadd")
3296 : (set_attr "mode" "QI,TI,TI")
3297 : (set (attr "enabled")
3298 : (cond [(and (eq_attr "alternative" "0")
3299 8005630 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3300 7839 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3301 7847 : (symbol_ref "false")
3302 172 : ]
3303 119844 : (const_string "*")))])
3304 7692 :
3305 17 : (define_split
3306 7709 : [(set (match_operand:V2QI 0 "general_reg_operand")
3307 : (plusminus:V2QI
3308 1871 : (match_operand:V2QI 1 "general_reg_operand")
3309 1871 : (match_operand:V2QI 2 "general_reg_operand")))
3310 15 : (clobber (reg:CC FLAGS_REG))]
3311 2002 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3312 183 : && reload_completed"
3313 3880 : [(parallel
3314 960 : [(set (strict_low_part (match_dup 0))
3315 51 : (plusminus:QI (match_dup 1) (match_dup 2)))
3316 51 : (clobber (reg:CC FLAGS_REG))])
3317 960 : (parallel
3318 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
3319 : (subreg:HI
3320 : (plusminus:QI
3321 : (subreg:QI
3322 : (zero_extract:HI (match_dup 4)
3323 : (const_int 8)
3324 : (const_int 8)) 0)
3325 : (subreg:QI
3326 : (zero_extract:HI (match_dup 5)
3327 : (const_int 8)
3328 : (const_int 8)) 0)) 0))
3329 : (clobber (reg:CC FLAGS_REG))])]
3330 168 : {
3331 168 : operands[5] = lowpart_subreg (HImode, operands[2], V2QImode);
3332 168 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
3333 168 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
3334 168 : operands[2] = lowpart_subreg (QImode, operands[2], V2QImode);
3335 168 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3336 168 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3337 : })
3338 :
3339 : (define_split
3340 168 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3341 : (plusminus:V2QI
3342 : (match_operand:V2QI 1 "sse_reg_operand")
3343 : (match_operand:V2QI 2 "sse_reg_operand")))
3344 : (clobber (reg:CC FLAGS_REG))]
3345 51 : "TARGET_SSE2 && reload_completed"
3346 : [(set (match_dup 0)
3347 51 : (plusminus:V16QI (match_dup 1) (match_dup 2)))]
3348 51 : {
3349 2989908 : operands[2] = lowpart_subreg (V16QImode, operands[2], V2QImode);
3350 1571628 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3351 1418499 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3352 1418448 : })
3353 77 :
3354 77 : (define_expand "mmx_<insn><mode>3"
3355 478 : [(set (match_operand:MMXMODE12 0 "register_operand")
3356 22 : (sat_plusminus:MMXMODE12
3357 504 : (match_operand:MMXMODE12 1 "register_mmxmem_operand")
3358 393 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))]
3359 444 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3360 208 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3361 :
3362 : (define_expand "<insn><mode>3"
3363 : [(set (match_operand:MMXMODE12 0 "register_operand")
3364 278 : (sat_plusminus:MMXMODE12
3365 : (match_operand:MMXMODE12 1 "register_operand")
3366 2 : (match_operand:MMXMODE12 2 "register_operand")))]
3367 2 : "TARGET_MMX_WITH_SSE")
3368 276 :
3369 : (define_insn "*mmx_<insn><mode>3"
3370 : [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yw")
3371 2 : (sat_plusminus:MMXMODE12
3372 : (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yw")
3373 97 : (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yw")))]
3374 36 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3375 1811 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3376 131 : "@
3377 68 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3378 34 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3379 1041 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3380 1063 : [(set_attr "isa" "*,sse2_noavx,avx")
3381 26 : (set_attr "mmx_isa" "native,*,*")
3382 : (set_attr "type" "mmxadd,sseadd,sseadd")
3383 1 : (set_attr "mode" "DI,TI,TI")])
3384 :
3385 1324 : (define_insn "<insn><mode>3"
3386 39 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
3387 1324 : (sat_plusminus:VI_16_32
3388 1377 : (match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
3389 999 : (match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
3390 206 : "TARGET_SSE2"
3391 14 : "@
3392 378 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3393 17 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3394 445 : [(set_attr "isa" "noavx,avx")
3395 445 : (set_attr "type" "sseadd")
3396 : (set_attr "mode" "TI")])
3397 46 :
3398 337 : (define_insn "mulv2si3"
3399 16097 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
3400 14639 : (mult:V2SI
3401 14304 : (match_operand:V2SI 1 "register_operand" "%0,0,v")
3402 1462 : (match_operand:V2SI 2 "register_operand" "Yr,*x,v")))]
3403 7552 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3404 637 : "@
3405 349027 : pmulld\t{%2, %0|%0, %2}
3406 347970 : pmulld\t{%2, %0|%0, %2}
3407 353407 : vpmulld\t{%2, %1, %0|%0, %1, %2}"
3408 6491 : [(set_attr "isa" "noavx,noavx,avx")
3409 : (set_attr "type" "sseimul")
3410 9596 : (set_attr "prefix_extra" "1")
3411 196 : (set_attr "prefix" "orig,orig,vex")
3412 524 : (set_attr "btver2_decode" "vector")
3413 0 : (set_attr "mode" "TI")])
3414 0 :
3415 0 : (define_expand "mmx_mulv4hi3"
3416 : [(set (match_operand:V4HI 0 "register_operand")
3417 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand")
3418 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3419 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3420 33 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3421 :
3422 : (define_expand "mulv4hi3"
3423 : [(set (match_operand:V4HI 0 "register_operand")
3424 33 : (mult:V4HI (match_operand:V4HI 1 "register_operand")
3425 : (match_operand:V4HI 2 "register_operand")))]
3426 : "TARGET_MMX_WITH_SSE")
3427 :
3428 33 : (define_insn "*mmx_mulv4hi3"
3429 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3430 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3431 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3432 3963 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3433 3985 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3434 1474 : "@
3435 22 : pmullw\t{%2, %0|%0, %2}
3436 22 : pmullw\t{%2, %0|%0, %2}
3437 12240 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3438 12218 : [(set_attr "isa" "*,sse2_noavx,avx")
3439 : (set_attr "mmx_isa" "native,*,*")
3440 12218 : (set_attr "type" "mmxmul,ssemul,ssemul")
3441 : (set_attr "mode" "DI,TI,TI")])
3442 :
3443 : (define_insn "mulv2hi3"
3444 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3445 : (mult:V2HI (match_operand:V2HI 1 "register_operand" "%0,Yw")
3446 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3447 9922 : "TARGET_SSE2"
3448 2296 : "@
3449 : pmullw\t{%2, %0|%0, %2}
3450 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3451 : [(set_attr "isa" "noavx,avx")
3452 : (set_attr "type" "ssemul")
3453 : (set_attr "mode" "TI")])
3454 :
3455 405756 : (define_expand "mulv8qi3"
3456 405756 : [(set (match_operand:V8QI 0 "register_operand")
3457 405756 : (mult:V8QI (match_operand:V8QI 1 "register_operand")
3458 : (match_operand:V8QI 2 "register_operand")))]
3459 224632 : "TARGET_MMX_WITH_SSE"
3460 224991 : {
3461 359 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3462 46060 : DONE;
3463 45701 : })
3464 45701 :
3465 45701 : (define_expand "mulv4qi3"
3466 45701 : [(set (match_operand:V4QI 0 "register_operand")
3467 45701 : (mult:V4QI (match_operand:V4QI 1 "register_operand")
3468 : (match_operand:V4QI 2 "register_operand")))]
3469 21961 : "TARGET_SSE2"
3470 22899 : {
3471 22899 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3472 938 : DONE;
3473 : })
3474 42846 :
3475 : (define_expand "mmx_smulv4hi3_highpart"
3476 11 : [(set (match_operand:V4HI 0 "register_operand")
3477 : (truncate:V4HI
3478 11 : (lshiftrt:V4SI
3479 11 : (mult:V4SI
3480 : (sign_extend:V4SI
3481 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3482 : (sign_extend:V4SI
3483 11 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3484 : (const_int 16))))]
3485 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3486 56 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3487 :
3488 38 : (define_insn "*mmx_smulv4hi3_highpart"
3489 22 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3490 72 : (truncate:V4HI
3491 16 : (lshiftrt:V4SI
3492 : (mult:V4SI
3493 : (sign_extend:V4SI
3494 16 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3495 34 : (sign_extend:V4SI
3496 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3497 : (const_int 16))))]
3498 196 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3499 196 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3500 22 : "@
3501 : pmulhw\t{%2, %0|%0, %2}
3502 22 : pmulhw\t{%2, %0|%0, %2}
3503 27 : vpmulhw\t{%2, %1, %0|%0, %1, %2}"
3504 27 : [(set_attr "isa" "*,sse2_noavx,avx")
3505 : (set_attr "mmx_isa" "native,*,*")
3506 : (set_attr "type" "mmxmul,ssemul,ssemul")
3507 : (set_attr "mode" "DI,TI,TI")])
3508 :
3509 : (define_expand "mmx_umulv4hi3_highpart"
3510 : [(set (match_operand:V4HI 0 "register_operand")
3511 : (truncate:V4HI
3512 : (lshiftrt:V4SI
3513 : (mult:V4SI
3514 : (zero_extend:V4SI
3515 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3516 : (zero_extend:V4SI
3517 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3518 : (const_int 16))))]
3519 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3520 : && (TARGET_SSE || TARGET_3DNOW_A)"
3521 22 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3522 :
3523 : (define_insn "*mmx_umulv4hi3_highpart"
3524 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3525 22 : (truncate:V4HI
3526 : (lshiftrt:V4SI
3527 : (mult:V4SI
3528 : (zero_extend:V4SI
3529 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3530 22 : (zero_extend:V4SI
3531 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3532 : (const_int 16))))]
3533 17 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3534 247 : && (TARGET_SSE || TARGET_3DNOW_A)
3535 248 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3536 0 : "@
3537 1 : pmulhuw\t{%2, %0|%0, %2}
3538 1 : pmulhuw\t{%2, %0|%0, %2}
3539 5 : vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
3540 5 : [(set_attr "isa" "*,sse2_noavx,avx")
3541 : (set_attr "mmx_isa" "native,*,*")
3542 1 : (set_attr "type" "mmxmul,ssemul,ssemul")
3543 : (set_attr "mode" "DI,TI,TI")])
3544 :
3545 : (define_expand "<s>mulv4hi3_highpart"
3546 : [(set (match_operand:V4HI 0 "register_operand")
3547 17 : (truncate:V4HI
3548 : (lshiftrt:V4SI
3549 17 : (mult:V4SI
3550 17 : (any_extend:V4SI
3551 : (match_operand:V4HI 1 "register_operand"))
3552 : (any_extend:V4SI
3553 17 : (match_operand:V4HI 2 "register_operand")))
3554 : (const_int 16))))]
3555 : "TARGET_MMX_WITH_SSE")
3556 :
3557 : (define_insn "<s>mulv2hi3_highpart"
3558 1219 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3559 : (truncate:V2HI
3560 1219 : (lshiftrt:V2SI
3561 1219 : (mult:V2SI
3562 : (any_extend:V2SI
3563 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
3564 : (any_extend:V2SI
3565 1219 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
3566 : (const_int 16))))]
3567 10 : "TARGET_SSE2"
3568 0 : "@
3569 : pmulh<u>w\t{%2, %0|%0, %2}
3570 43 : vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
3571 : [(set_attr "isa" "noavx,avx")
3572 43 : (set_attr "type" "ssemul")
3573 43 : (set_attr "mode" "TI")])
3574 43 :
3575 3690 : (define_expand "mmx_pmaddwd"
3576 3690 : [(set (match_operand:V2SI 0 "register_operand")
3577 : (plus:V2SI
3578 : (mult:V2SI
3579 2384 : (sign_extend:V2SI
3580 494 : (vec_select:V2HI
3581 2137 : (match_operand:V4HI 1 "register_mmxmem_operand")
3582 : (parallel [(const_int 0) (const_int 2)])))
3583 94 : (sign_extend:V2SI
3584 94 : (vec_select:V2HI
3585 : (match_operand:V4HI 2 "register_mmxmem_operand")
3586 94 : (parallel [(const_int 0) (const_int 2)]))))
3587 94 : (mult:V2SI
3588 94 : (sign_extend:V2SI
3589 : (vec_select:V2HI (match_dup 1)
3590 94 : (parallel [(const_int 1) (const_int 3)])))
3591 94 : (sign_extend:V2SI
3592 94 : (vec_select:V2HI (match_dup 2)
3593 : (parallel [(const_int 1) (const_int 3)]))))))]
3594 94 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3595 128 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3596 94 :
3597 94 : (define_insn "*mmx_pmaddwd"
3598 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yw")
3599 128 : (plus:V2SI
3600 94 : (mult:V2SI
3601 94 : (sign_extend:V2SI
3602 : (vec_select:V2HI
3603 94 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3604 94 : (parallel [(const_int 0) (const_int 2)])))
3605 94 : (sign_extend:V2SI
3606 : (vec_select:V2HI
3607 94 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")
3608 94 : (parallel [(const_int 0) (const_int 2)]))))
3609 94 : (mult:V2SI
3610 34 : (sign_extend:V2SI
3611 94 : (vec_select:V2HI (match_dup 1)
3612 94 : (parallel [(const_int 1) (const_int 3)])))
3613 94 : (sign_extend:V2SI
3614 94 : (vec_select:V2HI (match_dup 2)
3615 346 : (parallel [(const_int 1) (const_int 3)]))))))]
3616 275 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3617 527 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3618 433 : "@
3619 : pmaddwd\t{%2, %0|%0, %2}
3620 87 : pmaddwd\t{%2, %0|%0, %2}
3621 87 : vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
3622 339 : [(set_attr "isa" "*,sse2_noavx,avx")
3623 : (set_attr "mmx_isa" "native,*,*")
3624 87 : (set_attr "type" "mmxmul,sseiadd,sseiadd")
3625 1650055 : (set_attr "c86_attr" "madd")
3626 1650055 : (set_attr "mode" "DI,TI,TI")])
3627 1650142 :
3628 1650048 : (define_expand "mmx_pmulhrwv4hi3"
3629 1649968 : [(set (match_operand:V4HI 0 "register_operand")
3630 1650048 : (truncate:V4HI
3631 1649968 : (lshiftrt:V4SI
3632 80 : (plus:V4SI
3633 1247155 : (mult:V4SI
3634 1247155 : (sign_extend:V4SI
3635 1247155 : (match_operand:V4HI 1 "nonimmediate_operand"))
3636 1247155 : (sign_extend:V4SI
3637 1247155 : (match_operand:V4HI 2 "nonimmediate_operand")))
3638 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3639 1116636 : (const_int 32768) (const_int 32768)]))
3640 1116636 : (const_int 16))))]
3641 1116636 : "TARGET_3DNOW"
3642 1116650 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3643 1116636 :
3644 1116636 : (define_insn "*mmx_pmulhrwv4hi3"
3645 1116636 : [(set (match_operand:V4HI 0 "register_operand" "=y")
3646 1116650 : (truncate:V4HI
3647 1116636 : (lshiftrt:V4SI
3648 1116636 : (plus:V4SI
3649 1116636 : (mult:V4SI
3650 1116636 : (sign_extend:V4SI
3651 1116636 : (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
3652 1116636 : (sign_extend:V4SI
3653 : (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
3654 4810 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3655 4796 : (const_int 32768) (const_int 32768)]))
3656 : (const_int 16))))]
3657 4883 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3658 8 : "pmulhrw\t{%2, %0|%0, %2}"
3659 : [(set_attr "type" "mmxmul")
3660 354 : (set_attr "prefix_extra" "1")
3661 1460 : (set_attr "mode" "DI")])
3662 1814 :
3663 1460 : (define_expand "sse2_umulv1siv1di3"
3664 354 : [(set (match_operand:V1DI 0 "register_operand")
3665 1460 : (mult:V1DI
3666 1460 : (zero_extend:V1DI
3667 : (vec_select:V1SI
3668 1424 : (match_operand:V2SI 1 "register_mmxmem_operand")
3669 1424 : (parallel [(const_int 0)])))
3670 1424 : (zero_extend:V1DI
3671 : (vec_select:V1SI
3672 1424 : (match_operand:V2SI 2 "register_mmxmem_operand")
3673 1424 : (parallel [(const_int 0)])))))]
3674 1424 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
3675 1436 : "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
3676 1424 :
3677 : (define_insn "*sse2_umulv1siv1di3"
3678 373 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
3679 385 : (mult:V1DI
3680 : (zero_extend:V1DI
3681 242 : (vec_select:V1SI
3682 : (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
3683 : (parallel [(const_int 0)])))
3684 373 : (zero_extend:V1DI
3685 12 : (vec_select:V1SI
3686 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
3687 : (parallel [(const_int 0)])))))]
3688 65 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3689 65 : && TARGET_SSE2
3690 89 : && ix86_binary_operator_ok (MULT, V2SImode, operands)"
3691 1 : "@
3692 24 : pmuludq\t{%2, %0|%0, %2}
3693 24 : pmuludq\t{%2, %0|%0, %2}
3694 : vpmuludq\t{%2, %1, %0|%0, %1, %2}"
3695 : [(set_attr "isa" "*,sse2_noavx,avx")
3696 24 : (set_attr "mmx_isa" "native,*,*")
3697 : (set_attr "type" "mmxmul,ssemul,ssemul")
3698 95607 : (set_attr "mode" "DI,TI,TI")])
3699 95607 :
3700 95607 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3701 256 : ;;
3702 13034 : ;; Parallel integral shifts
3703 13290 : ;;
3704 13290 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3705 13034 :
3706 13034 : (define_insn "<code><mode>3"
3707 : [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
3708 1801 : (smaxmin:MMXMODE14
3709 1545 : (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
3710 : (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
3711 525 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3712 : "@
3713 1451 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3714 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3715 688 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3716 189 : [(set_attr "isa" "noavx,noavx,avx")
3717 32 : (set_attr "type" "sseiadd")
3718 : (set_attr "prefix_extra" "1")
3719 : (set_attr "prefix" "orig,orig,vex")
3720 : (set_attr "mode" "TI")])
3721 :
3722 : (define_expand "mmx_<code>v4hi3"
3723 : [(set (match_operand:V4HI 0 "register_operand")
3724 : (smaxmin:V4HI
3725 : (match_operand:V4HI 1 "register_mmxmem_operand")
3726 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3727 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3728 : && (TARGET_SSE || TARGET_3DNOW_A)"
3729 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
3730 :
3731 : (define_insn "*mmx_<code>v4hi3"
3732 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3733 44 : (smaxmin:V4HI
3734 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3735 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3736 109 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3737 543 : && (TARGET_SSE || TARGET_3DNOW_A)
3738 998 : && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
3739 : "@
3740 : p<maxmin_int>w\t{%2, %0|%0, %2}
3741 : p<maxmin_int>w\t{%2, %0|%0, %2}
3742 169 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3743 407 : [(set_attr "isa" "*,sse2_noavx,avx")
3744 63 : (set_attr "mmx_isa" "native,*,*")
3745 364 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3746 0 : (set_attr "mode" "DI,TI,TI")])
3747 301 :
3748 : (define_expand "<code>v4hi3"
3749 63 : [(set (match_operand:V4HI 0 "register_operand")
3750 : (smaxmin:V4HI
3751 : (match_operand:V4HI 1 "register_operand")
3752 : (match_operand:V4HI 2 "register_operand")))]
3753 : "TARGET_MMX_WITH_SSE")
3754 306 :
3755 : (define_insn "<code><mode>3"
3756 306 : [(set (match_operand:VI1_16_32 0 "register_operand" "=Yr,*x,Yv")
3757 306 : (smaxmin:VI1_16_32
3758 : (match_operand:VI1_16_32 1 "register_operand" "%0,0,Yv")
3759 : (match_operand:VI1_16_32 2 "register_operand" "Yr,*x,Yv")))]
3760 106 : "TARGET_SSE4_1"
3761 306 : "@
3762 : p<maxmin_int>b\t{%2, %0|%0, %2}
3763 : p<maxmin_int>b\t{%2, %0|%0, %2}
3764 184 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3765 10 : [(set_attr "isa" "noavx,noavx,avx")
3766 18 : (set_attr "type" "sseiadd")
3767 : (set_attr "prefix_extra" "1")
3768 18 : (set_attr "prefix" "orig,orig,vex")
3769 18 : (set_attr "mode" "TI")])
3770 18 :
3771 : (define_insn "<code>v2hi3"
3772 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3773 : (smaxmin:V2HI
3774 : (match_operand:V2HI 1 "register_operand" "%0,Yw")
3775 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3776 174 : "TARGET_SSE2"
3777 : "@
3778 : p<maxmin_int>w\t{%2, %0|%0, %2}
3779 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3780 : [(set_attr "isa" "noavx,avx")
3781 : (set_attr "type" "sseiadd")
3782 : (set_attr "mode" "TI")])
3783 :
3784 : (define_insn "<code><mode>3"
3785 210218 : [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
3786 210218 : (umaxmin:MMXMODE24
3787 117599 : (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
3788 1593 : (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
3789 1819 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3790 0 : "@
3791 125790 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3792 125790 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3793 125937 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3794 280 : [(set_attr "isa" "noavx,noavx,avx")
3795 : (set_attr "type" "sseiadd")
3796 : (set_attr "prefix_extra" "1")
3797 221563 : (set_attr "prefix" "orig,orig,vex")
3798 221563 : (set_attr "mode" "TI")])
3799 221563 :
3800 : (define_expand "mmx_<code>v8qi3"
3801 : [(set (match_operand:V8QI 0 "register_operand")
3802 : (umaxmin:V8QI
3803 3757533 : (match_operand:V8QI 1 "register_mmxmem_operand")
3804 3757533 : (match_operand:V8QI 2 "register_mmxmem_operand")))]
3805 3757533 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3806 : && (TARGET_SSE || TARGET_3DNOW_A)"
3807 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
3808 :
3809 1448095 : (define_insn "*mmx_<code>v8qi3"
3810 1448095 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
3811 1448139 : (umaxmin:V8QI
3812 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
3813 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3814 280 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3815 324 : && (TARGET_SSE || TARGET_3DNOW_A)
3816 4730546 : && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
3817 4730266 : "@
3818 : p<maxmin_int>b\t{%2, %0|%0, %2}
3819 : p<maxmin_int>b\t{%2, %0|%0, %2}
3820 290 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3821 1538547 : [(set_attr "isa" "*,sse2_noavx,avx")
3822 1538421 : (set_attr "mmx_isa" "native,*,*")
3823 1538421 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3824 0 : (set_attr "mode" "DI,TI,TI")])
3825 0 :
3826 : (define_expand "<code>v8qi3"
3827 2411 : [(set (match_operand:V8QI 0 "register_operand")
3828 2329 : (umaxmin:V8QI
3829 2329 : (match_operand:V8QI 1 "register_operand")
3830 : (match_operand:V8QI 2 "register_operand")))]
3831 : "TARGET_MMX_WITH_SSE")
3832 :
3833 1219 : (define_insn "<code><mode>3"
3834 1219 : [(set (match_operand:VI1_16_32 0 "register_operand" "=x,Yw")
3835 1219 : (umaxmin:VI1_16_32
3836 1219 : (match_operand:VI1_16_32 1 "register_operand" "%0,Yw")
3837 0 : (match_operand:VI1_16_32 2 "register_operand" "x,Yw")))]
3838 208 : "TARGET_SSE2"
3839 201 : "@
3840 : p<maxmin_int>b\t{%2, %0|%0, %2}
3841 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3842 38 : [(set_attr "isa" "noavx,avx")
3843 28 : (set_attr "type" "sseiadd")
3844 : (set_attr "mode" "TI")])
3845 :
3846 : (define_insn "<code>v2hi3"
3847 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yv")
3848 : (umaxmin:V2HI
3849 : (match_operand:V2HI 1 "register_operand" "%0,0,Yv")
3850 : (match_operand:V2HI 2 "register_operand" "Yr,*x,Yv")))]
3851 10 : "TARGET_SSE4_1"
3852 0 : "@
3853 : p<maxmin_int>w\t{%2, %0|%0, %2}
3854 : p<maxmin_int>w\t{%2, %0|%0, %2}
3855 0 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3856 0 : [(set_attr "isa" "noavx,noavx,avx")
3857 0 : (set_attr "type" "sseiadd")
3858 0 : (set_attr "prefix_extra" "1")
3859 0 : (set_attr "prefix" "orig,orig,vex")
3860 : (set_attr "mode" "TI")])
3861 :
3862 : (define_insn "ssse3_abs<mode>2"
3863 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
3864 : (abs:MMXMODEI
3865 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))]
3866 106 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
3867 62 : "@
3868 : pabs<mmxvecsize>\t{%1, %0|%0, %1}
3869 : %vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3870 400 : [(set_attr "mmx_isa" "native,*")
3871 400 : (set_attr "type" "sselog1")
3872 390 : (set_attr "prefix_rep" "0")
3873 390 : (set_attr "prefix_extra" "1")
3874 686 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3875 : (set_attr "mode" "DI,TI")])
3876 :
3877 : (define_expand "abs<mode>2"
3878 : [(set (match_operand:MMXMODEI 0 "register_operand")
3879 : (abs:MMXMODEI
3880 : (match_operand:MMXMODEI 1 "register_operand")))]
3881 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
3882 :
3883 : (define_insn "abs<mode>2"
3884 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yv")
3885 : (abs:VI_16_32
3886 : (match_operand:VI_16_32 1 "register_operand" "Yv")))]
3887 40 : "TARGET_SSSE3"
3888 48 : "%vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3889 : [(set_attr "type" "sselog1")
3890 : (set_attr "prefix_rep" "0")
3891 62 : (set_attr "prefix_extra" "1")
3892 62 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3893 50 : (set_attr "mode" "TI")])
3894 50 :
3895 102 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3896 : ;;
3897 2132478 : ;; Parallel integral shifts
3898 : ;;
3899 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3900 :
3901 2132478 : (define_insn "mmx_ashr<mode>3"
3902 2132478 : [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,<Yv_Yw>")
3903 2132478 : (ashiftrt:MMXMODE24
3904 2132478 : (match_operand:MMXMODE24 1 "register_operand" "0,0,<Yv_Yw>")
3905 2132478 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3906 2134758 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3907 434 : "@
3908 1402 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3909 1402 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3910 4211 : vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3911 5613 : [(set_attr "isa" "*,sse2_noavx,avx")
3912 1402 : (set_attr "mmx_isa" "native,*,*")
3913 : (set_attr "type" "mmxshft,sseishft,sseishft")
3914 5166 : (set (attr "length_immediate")
3915 955 : (if_then_else (match_operand 2 "const_int_operand")
3916 931 : (const_string "1")
3917 1527 : (const_string "0")))
3918 : (set_attr "mode" "DI,TI,TI")])
3919 572 :
3920 572 : (define_insn_and_split "*mmx_ashr<mode>3_1"
3921 572 : [(set (match_operand:MMXMODE24 0 "register_operand")
3922 572 : (lt:MMXMODE24
3923 572 : (match_operand:MMXMODE24 1 "register_operand")
3924 : (match_operand:MMXMODE24 2 "const0_operand")))]
3925 7882 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3926 : "#"
3927 100 : "&& 1"
3928 755 : [(set (match_dup 0) (ashiftrt:MMXMODE24 (match_dup 1) (match_dup 3)))]
3929 4456 : "operands[3] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3930 2795 :
3931 381 : (define_expand "ashr<mode>3"
3932 956 : [(set (match_operand:MMXMODE24 0 "register_operand")
3933 : (ashiftrt:MMXMODE24
3934 : (match_operand:MMXMODE24 1 "register_operand")
3935 : (match_operand:DI 2 "nonmemory_operand")))]
3936 655 : "TARGET_MMX_WITH_SSE")
3937 :
3938 : (define_insn "mmx_<insn><mode>3"
3939 : [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,<Yv_Yw>")
3940 : (any_lshift:MMXMODE248
3941 26 : (match_operand:MMXMODE248 1 "register_operand" "0,0,<Yv_Yw>")
3942 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3943 5911 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3944 13709 : "@
3945 26 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3946 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3947 64232 : vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3948 64232 : [(set_attr "isa" "*,sse2_noavx,avx")
3949 : (set_attr "mmx_isa" "native,*,*")
3950 : (set_attr "type" "mmxshft,sseishft,sseishft")
3951 64232 : (set (attr "length_immediate")
3952 : (if_then_else (match_operand 2 "const_int_operand")
3953 : (const_string "1")
3954 : (const_string "0")))
3955 : (set_attr "mode" "DI,TI,TI")])
3956 :
3957 : (define_split
3958 : [(set (match_operand:MMXMODE248 0 "register_operand")
3959 : (and:MMXMODE248
3960 : (lt:MMXMODE248
3961 : (match_operand:MMXMODE248 1 "register_operand")
3962 : (match_operand:MMXMODE248 2 "const0_operand"))
3963 : (match_operand:MMXMODE248 3 "const1_operand")))]
3964 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3965 : [(set (match_dup 0) (lshiftrt:MMXMODE248 (match_dup 1) (match_dup 4)))]
3966 0 : "operands[4] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3967 :
3968 48 : (define_expand "<insn><mode>3"
3969 48 : [(set (match_operand:MMXMODE24 0 "register_operand")
3970 : (any_lshift:MMXMODE24
3971 48 : (match_operand:MMXMODE24 1 "register_operand")
3972 : (match_operand:DI 2 "nonmemory_operand")))]
3973 0 : "TARGET_MMX_WITH_SSE")
3974 :
3975 : (define_insn "mmx_<insn>v1si3"
3976 : [(set (match_operand:V1SI 0 "register_operand" "=x,Yw")
3977 : (any_lshift:V1SI
3978 11 : (match_operand:V1SI 1 "register_operand" "0,Yw")
3979 45 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3980 3812 : "TARGET_SSE2"
3981 394 : "@
3982 11 : p<vshift>d\t{%2, %0|%0, %2}
3983 45 : vp<vshift>d\t{%2, %1, %0|%0, %1, %2}"
3984 846 : [(set_attr "isa" "noavx,avx")
3985 846 : (set_attr "type" "sseishft")
3986 : (set (attr "length_immediate")
3987 : (if_then_else (match_operand 2 "const_int_operand")
3988 846 : (const_string "1")
3989 : (const_string "0")))
3990 : (set_attr "mode" "TI")])
3991 :
3992 : (define_insn "<insn>v2hi3"
3993 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3994 : (any_shift:V2HI
3995 : (match_operand:V2HI 1 "register_operand" "0,Yw")
3996 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3997 1086 : "TARGET_SSE2"
3998 92 : "@
3999 : p<vshift>w\t{%2, %0|%0, %2}
4000 : vp<vshift>w\t{%2, %1, %0|%0, %1, %2}"
4001 243 : [(set_attr "isa" "noavx,avx")
4002 243 : (set_attr "type" "sseishft")
4003 243 : (set (attr "length_immediate")
4004 : (if_then_else (match_operand 2 "const_int_operand")
4005 : (const_string "1")
4006 243 : (const_string "0")))
4007 : (set_attr "mode" "TI")])
4008 :
4009 : (define_insn_and_split "*mmx_ashrv2hi3_1"
4010 : [(set (match_operand:V2HI 0 "register_operand")
4011 : (lt:V2HI
4012 : (match_operand:V2HI 1 "register_operand")
4013 : (match_operand:V2HI 2 "const0_operand")))]
4014 944 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4015 : "#"
4016 : "&& 1"
4017 80 : [(set (match_dup 0) (ashiftrt:V2HI (match_dup 1) (match_dup 3)))]
4018 80 : "operands[3] = gen_int_mode (15, DImode);")
4019 :
4020 : (define_split
4021 80 : [(set (match_operand:V2HI 0 "register_operand")
4022 : (and:V2HI
4023 575452 : (lt:V2HI
4024 575452 : (match_operand:V2HI 1 "register_operand")
4025 1057010 : (match_operand:V2HI 2 "const0_operand"))
4026 1056930 : (match_operand:V2HI 3 "const1_operand")))]
4027 1056930 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4028 575452 : [(set (match_dup 0) (lshiftrt:V2HI (match_dup 1) (match_dup 4)))]
4029 0 : "operands[4] = gen_int_mode (15, DImode);")
4030 5564 :
4031 984056 : (define_expand "<insn>v8qi3"
4032 978487 : [(set (match_operand:V8QI 0 "register_operand")
4033 984056 : (any_shift:V8QI (match_operand:V8QI 1 "register_operand")
4034 0 : (match_operand:DI 2 "nonmemory_operand")))]
4035 256777 : "TARGET_MMX_WITH_SSE"
4036 256869 : {
4037 581175 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4038 581078 : operands[1], operands[2]);
4039 581175 : DONE;
4040 : })
4041 3 :
4042 : (define_expand "<insn>v4qi3"
4043 1579500 : [(set (match_operand:V4QI 0 "register_operand")
4044 1579500 : (any_shift:V4QI (match_operand:V4QI 1 "register_operand")
4045 1579500 : (match_operand:DI 2 "nonmemory_operand")))]
4046 : "TARGET_SSE2"
4047 33 : {
4048 33 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4049 717929 : operands[1], operands[2]);
4050 717962 : DONE;
4051 717929 : })
4052 717929 :
4053 7 : (define_insn_and_split "<insn>v2qi3"
4054 0 : [(set (match_operand:V2QI 0 "register_operand" "=Q")
4055 7 : (any_shift:V2QI
4056 7 : (match_operand:V2QI 1 "register_operand" "0")
4057 7 : (match_operand:QI 2 "nonmemory_operand" "cI")))
4058 : (clobber (reg:CC FLAGS_REG))]
4059 631 : "!TARGET_PARTIAL_REG_STALL || optimize_size"
4060 12 : "#"
4061 284 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
4062 295 : && reload_completed"
4063 : [(parallel
4064 53 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
4065 : (subreg:HI
4066 188523 : (any_shift:QI
4067 188523 : (subreg:QI
4068 142 : (zero_extract:HI (match_dup 4)
4069 68527 : (const_int 8)
4070 132642 : (const_int 8)) 0)
4071 109 : (match_dup 2)) 0))
4072 132533 : (clobber (reg:CC FLAGS_REG))])
4073 63 : (parallel
4074 73 : [(set (strict_low_part (match_dup 0))
4075 20 : (any_shift:QI (match_dup 1) (match_dup 2)))
4076 : (clobber (reg:CC FLAGS_REG))])]
4077 50 : {
4078 50 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
4079 50 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
4080 50 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
4081 50 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
4082 : }
4083 : [(set_attr "type" "multi")
4084 : (set_attr "mode" "QI")])
4085 50 :
4086 : (define_expand "v<insn>v8qi3"
4087 : [(set (match_operand:V8QI 0 "register_operand")
4088 : (any_shift:V8QI
4089 : (match_operand:V8QI 1 "register_operand")
4090 : (match_operand:V8QI 2 "register_operand")))]
4091 : "TARGET_AVX512BW && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
4092 9 : {
4093 9 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4094 50 : operands[1], operands[2]);
4095 9 : DONE;
4096 : })
4097 :
4098 : (define_expand "v<insn>v4qi3"
4099 618 : [(set (match_operand:V4QI 0 "register_operand")
4100 : (any_shift:V4QI
4101 618 : (match_operand:V4QI 1 "register_operand")
4102 618 : (match_operand:V4QI 2 "register_operand")))]
4103 618 : "TARGET_AVX512BW && TARGET_AVX512VL"
4104 4 : {
4105 4 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4106 : operands[1], operands[2]);
4107 4 : DONE;
4108 : })
4109 10 :
4110 : (define_expand "vec_shl_<mode>"
4111 10 : [(set (match_operand:V248FI 0 "register_operand")
4112 10 : (ashift:V1DI
4113 10 : (match_operand:V248FI 1 "nonimmediate_operand")
4114 : (match_operand:DI 2 "nonmemory_operand")))]
4115 : "TARGET_MMX_WITH_SSE"
4116 14 : {
4117 15 : rtx op0 = gen_reg_rtx (V1DImode);
4118 14 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4119 :
4120 14 : emit_insn (gen_mmx_ashlv1di3
4121 16 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4122 14 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4123 16 : DONE;
4124 3 : })
4125 3 :
4126 : (define_expand "vec_shl_<mode>"
4127 : [(set (match_operand:V24FI_32 0 "register_operand")
4128 : (ashift:V1SI
4129 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4130 : (match_operand:DI 2 "nonmemory_operand")))]
4131 : "TARGET_SSE2"
4132 4 : {
4133 5 : rtx op0 = gen_reg_rtx (V1SImode);
4134 4 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4135 :
4136 4 : emit_insn (gen_mmx_ashlv1si3
4137 639 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4138 4 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4139 639 : DONE;
4140 636 : })
4141 636 :
4142 : (define_expand "vec_shr_<mode>"
4143 : [(set (match_operand:V248FI 0 "register_operand")
4144 : (lshiftrt:V1DI
4145 : (match_operand:V248FI 1 "nonimmediate_operand")
4146 : (match_operand:DI 2 "nonmemory_operand")))]
4147 : "TARGET_MMX_WITH_SSE"
4148 1249 : {
4149 1249 : rtx op0 = gen_reg_rtx (V1DImode);
4150 1249 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4151 :
4152 1249 : emit_insn (gen_mmx_lshrv1di3
4153 1490 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4154 1249 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4155 1490 : DONE;
4156 241 : })
4157 241 :
4158 : (define_expand "vec_shr_<mode>"
4159 : [(set (match_operand:V24FI_32 0 "register_operand")
4160 : (lshiftrt:V1SI
4161 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4162 : (match_operand:DI 2 "nonmemory_operand")))]
4163 : "TARGET_SSE2"
4164 241 : {
4165 241 : rtx op0 = gen_reg_rtx (V1SImode);
4166 241 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4167 :
4168 241 : emit_insn (gen_mmx_lshrv1si3
4169 1199 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4170 241 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4171 1199 : DONE;
4172 958 : })
4173 958 :
4174 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4175 : ;;
4176 : ;; Parallel integral comparisons
4177 : ;;
4178 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4179 :
4180 : (define_expand "mmx_eq<mode>3"
4181 : [(set (match_operand:MMXMODEI 0 "register_operand")
4182 : (eq:MMXMODEI
4183 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4184 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4185 164 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4186 105 : "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
4187 164 :
4188 164 : (define_insn "*mmx_eq<mode>3"
4189 164 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4190 105 : (eq:MMXMODEI
4191 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x")
4192 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4193 1954 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4194 12048 : && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
4195 10402 : "@
4196 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4197 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4198 20371 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4199 20568 : [(set_attr "isa" "*,sse2_noavx,avx")
4200 : (set_attr "mmx_isa" "native,*,*")
4201 30591 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4202 197 : (set_attr "mode" "DI,TI,TI")])
4203 197 :
4204 : (define_insn "*eq<mode>3"
4205 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4206 : (eq:VI_16_32
4207 : (match_operand:VI_16_32 1 "register_operand" "%0,x")
4208 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4209 900 : "TARGET_SSE2"
4210 1815 : "@
4211 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4212 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4213 2090 : [(set_attr "isa" "noavx,avx")
4214 2090 : (set_attr "type" "ssecmp")
4215 : (set_attr "mode" "TI")])
4216 2090 :
4217 : (define_insn "mmx_gt<mode>3"
4218 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4219 : (gt:MMXMODEI
4220 : (match_operand:MMXMODEI 1 "register_operand" "0,0,x")
4221 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4222 2987 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4223 4273381 : "@
4224 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4225 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4226 14495 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4227 4287876 : [(set_attr "isa" "*,sse2_noavx,avx")
4228 4273381 : (set_attr "mmx_isa" "native,*,*")
4229 4287876 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4230 4273381 : (set_attr "mode" "DI,TI,TI")])
4231 4273381 :
4232 4273381 : (define_insn "*gt<mode>3"
4233 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4234 4273286 : (gt:VI_16_32
4235 4273286 : (match_operand:VI_16_32 1 "register_operand" "0,x")
4236 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4237 4233543 : "TARGET_SSE2"
4238 4233116 : "@
4239 4233116 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4240 4233116 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4241 4237364 : [(set_attr "isa" "noavx,avx")
4242 4248 : (set_attr "type" "ssecmp")
4243 4940 : (set_attr "mode" "TI")])
4244 9188 :
4245 4940 : (define_insn "*xop_maskcmp<mode>3"
4246 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4247 4458 : (match_operator:MMXMODEI 1 "ix86_comparison_int_operator"
4248 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4249 5108930 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4250 5109099 : "TARGET_XOP"
4251 23485 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4252 5108930 : [(set_attr "type" "sse4arg")
4253 5108930 : (set_attr "mode" "TI")])
4254 5108930 :
4255 19385 : (define_insn "*xop_maskcmp<mode>3"
4256 5786 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4257 25171 : (match_operator:VI_16_32 1 "ix86_comparison_int_operator"
4258 : [(match_operand:VI_16_32 2 "register_operand" "x")
4259 5786 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4260 0 : "TARGET_XOP"
4261 5458 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4262 : [(set_attr "type" "sse4arg")
4263 : (set_attr "mode" "TI")])
4264 3907 :
4265 3907 : (define_insn "*xop_maskcmp_uns<mode>3"
4266 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4267 3907 : (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator"
4268 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4269 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4270 3367821 : "TARGET_XOP"
4271 13608 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4272 : [(set_attr "type" "sse4arg")
4273 : (set_attr "mode" "TI")])
4274 3380350 :
4275 3380350 : (define_insn "*xop_maskcmp_uns<mode>3"
4276 3367821 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4277 3380350 : (match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
4278 3367821 : [(match_operand:VI_16_32 2 "register_operand" "x")
4279 3367821 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4280 3367821 : "TARGET_XOP"
4281 3370740 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4282 3367821 : [(set_attr "type" "sse4arg")
4283 : (set_attr "mode" "TI")])
4284 2218494 :
4285 2218494 : (define_expand "vec_cmp<mode><mode>"
4286 2216714 : [(set (match_operand:MMXMODEI 0 "register_operand")
4287 2218494 : (match_operator:MMXMODEI 1 ""
4288 2216714 : [(match_operand:MMXMODEI 2 "register_operand")
4289 2216714 : (match_operand:MMXMODEI 3 "register_operand")]))]
4290 2216714 : "TARGET_MMX_WITH_SSE"
4291 853 : {
4292 19140 : bool ok = ix86_expand_int_vec_cmp (operands);
4293 19140 : gcc_assert (ok);
4294 3599949 : DONE;
4295 17088 : })
4296 32661 :
4297 : (define_expand "vec_cmp<mode><mode>"
4298 3594212 : [(set (match_operand:VI_16_32 0 "register_operand")
4299 3582008 : (match_operator:VI_16_32 1 ""
4300 3582008 : [(match_operand:VI_16_32 2 "register_operand")
4301 3582008 : (match_operand:VI_16_32 3 "register_operand")]))]
4302 3582008 : "TARGET_SSE2"
4303 3582127 : {
4304 119 : bool ok = ix86_expand_int_vec_cmp (operands);
4305 3085843 : gcc_assert (ok);
4306 3085843 : DONE;
4307 3085724 : })
4308 3085814 :
4309 3085724 : (define_expand "vec_cmpu<mode><mode>"
4310 3085814 : [(set (match_operand:MMXMODEI 0 "register_operand")
4311 3085814 : (match_operator:MMXMODEI 1 ""
4312 3085814 : [(match_operand:MMXMODEI 2 "register_operand")
4313 3085724 : (match_operand:MMXMODEI 3 "register_operand")]))]
4314 3085724 : "TARGET_MMX_WITH_SSE"
4315 3085919 : {
4316 3085919 : bool ok = ix86_expand_int_vec_cmp (operands);
4317 3085919 : gcc_assert (ok);
4318 3085919 : DONE;
4319 3085724 : })
4320 3085998 :
4321 : (define_expand "vec_cmpu<mode><mode>"
4322 3037713 : [(set (match_operand:VI_16_32 0 "register_operand")
4323 2901268 : (match_operator:VI_16_32 1 ""
4324 173633 : [(match_operand:VI_16_32 2 "register_operand")
4325 3210622 : (match_operand:VI_16_32 3 "register_operand")]))]
4326 : "TARGET_SSE2"
4327 7974 : {
4328 7974 : bool ok = ix86_expand_int_vec_cmp (operands);
4329 109 : gcc_assert (ok);
4330 269 : DONE;
4331 160 : })
4332 286 :
4333 160 : (define_expand "vcond_mask_<mode><mmxintvecmodelower>"
4334 286 : [(set (match_operand:MMXMODE124 0 "register_operand")
4335 286 : (vec_merge:MMXMODE124
4336 286 : (match_operand:MMXMODE124 1 "vector_or_const_vector_operand")
4337 : (match_operand:MMXMODE124 2 "vector_or_const_vector_operand")
4338 94 : (match_operand:<mmxintvecmode> 3 "register_operand")))]
4339 94 : "TARGET_MMX_WITH_SSE"
4340 396 : {
4341 302 : ix86_expand_sse_movcc (operands[0], operands[3],
4342 92 : operands[1], operands[2]);
4343 394 : DONE;
4344 : })
4345 9 :
4346 6 : (define_expand "vcond_mask_<mode><mode>"
4347 9 : [(set (match_operand:VI_16_32 0 "register_operand")
4348 6 : (vec_merge:VI_16_32
4349 3 : (match_operand:VI_16_32 1 "vector_or_const_vector_operand")
4350 6 : (match_operand:VI_16_32 2 "vector_or_const_vector_operand")
4351 : (match_operand:VI_16_32 3 "register_operand")))]
4352 2 : "TARGET_SSE2"
4353 128 : {
4354 126 : ix86_expand_sse_movcc (operands[0], operands[3],
4355 : operands[1], operands[2]);
4356 126 : DONE;
4357 : })
4358 33 :
4359 : (define_insn "mmx_pblendvb_v8qi"
4360 33 : [(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x")
4361 0 : (unspec:V8QI
4362 33 : [(match_operand:V8QI 1 "register_operand" "0,0,x")
4363 : (match_operand:V8QI 2 "register_operand" "Yr,*x,x")
4364 : (match_operand:V8QI 3 "register_operand" "Yz,Yz,x")]
4365 : UNSPEC_BLENDV))]
4366 1730 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4367 : "@
4368 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4369 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4370 3578 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4371 3519 : [(set_attr "isa" "noavx,noavx,avx")
4372 59 : (set_attr "type" "ssemov")
4373 3578 : (set_attr "c86_attr" "blendv")
4374 59 : (set_attr "prefix_extra" "1")
4375 : (set_attr "length_immediate" "1")
4376 : (set_attr "prefix" "orig,orig,vex")
4377 : (set_attr "btver2_decode" "vector")
4378 : (set_attr "mode" "TI")])
4379 :
4380 : (define_insn_and_split "*mmx_pblendvb_v8qi_1"
4381 : [(set (match_operand:V8QI 0 "register_operand")
4382 : (unspec:V8QI
4383 : [(match_operand:V8QI 1 "register_operand")
4384 : (match_operand:V8QI 2 "register_operand")
4385 : (eq:V8QI
4386 : (eq:V8QI
4387 : (match_operand:V8QI 3 "register_operand")
4388 : (match_operand:V8QI 4 "nonmemory_operand"))
4389 : (match_operand:V8QI 5 "const0_operand"))]
4390 : UNSPEC_BLENDV))]
4391 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4392 0 : "#"
4393 : "&& 1"
4394 : [(set (match_dup 6)
4395 6 : (eq:V8QI (match_dup 3) (match_dup 7)))
4396 6 : (set (match_dup 0)
4397 6 : (unspec:V8QI
4398 6 : [(match_dup 2)
4399 : (match_dup 1)
4400 : (match_dup 6)]
4401 : UNSPEC_BLENDV))]
4402 0 : {
4403 0 : operands[6] = gen_reg_rtx (V8QImode);
4404 0 : operands[7] = force_reg (V8QImode, operands[4]);
4405 : })
4406 :
4407 : (define_insn_and_split "*mmx_pblendvb_v8qi_2"
4408 0 : [(set (match_operand:V8QI 0 "register_operand")
4409 : (unspec:V8QI
4410 : [(match_operand:V8QI 1 "register_operand")
4411 : (match_operand:V8QI 2 "register_operand")
4412 : (subreg:V8QI
4413 0 : (eq:MMXMODE24
4414 : (eq:MMXMODE24
4415 : (match_operand:MMXMODE24 3 "register_operand")
4416 : (match_operand:MMXMODE24 4 "nonmemory_operand"))
4417 : (match_operand:MMXMODE24 5 "const0_operand")) 0)]
4418 : UNSPEC_BLENDV))]
4419 10 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4420 0 : "#"
4421 1 : "&& 1"
4422 0 : [(set (match_dup 6)
4423 34 : (eq:MMXMODE24 (match_dup 3) (match_dup 8)))
4424 30 : (set (match_dup 0)
4425 15 : (unspec:V8QI
4426 15 : [(match_dup 2)
4427 : (match_dup 1)
4428 : (match_dup 7)]
4429 : UNSPEC_BLENDV))]
4430 3 : {
4431 3 : operands[6] = gen_reg_rtx (<MODE>mode);
4432 3 : operands[7] = lowpart_subreg (V8QImode, operands[6], <MODE>mode);
4433 3 : operands[8] = force_reg (<MODE>mode, operands[4]);
4434 : })
4435 :
4436 : (define_insn "mmx_pblendvb_<mode>"
4437 3 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yr,*x,x")
4438 : (unspec:VI_16_32
4439 : [(match_operand:VI_16_32 1 "register_operand" "0,0,x")
4440 : (match_operand:VI_16_32 2 "register_operand" "Yr,*x,x")
4441 : (match_operand:VI_16_32 3 "register_operand" "Yz,Yz,x")]
4442 3 : UNSPEC_BLENDV))]
4443 1961 : "TARGET_SSE4_1"
4444 : "@
4445 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4446 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4447 1009 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4448 1018 : [(set_attr "isa" "noavx,noavx,avx")
4449 : (set_attr "type" "ssemov")
4450 1018 : (set_attr "c86_attr" "blendv")
4451 0 : (set_attr "prefix_extra" "1")
4452 9 : (set_attr "length_immediate" "1")
4453 : (set_attr "prefix" "orig,orig,vex")
4454 : (set_attr "btver2_decode" "vector")
4455 : (set_attr "mode" "TI")])
4456 :
4457 : (define_insn_and_split "*mmx_pblendvb_<mode>_1"
4458 : [(set (match_operand:VI_16_32 0 "register_operand")
4459 : (unspec:VI_16_32
4460 : [(match_operand:VI_16_32 1 "register_operand")
4461 : (match_operand:VI_16_32 2 "register_operand")
4462 : (eq:VI_16_32
4463 : (eq:VI_16_32
4464 : (match_operand:VI_16_32 3 "register_operand")
4465 : (match_operand:VI_16_32 4 "nonmemory_operand"))
4466 : (match_operand:VI_16_32 5 "const0_operand"))]
4467 : UNSPEC_BLENDV))]
4468 36 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4469 0 : "#"
4470 : "&& 1"
4471 : [(set (match_dup 6)
4472 30 : (eq:VI_16_32 (match_dup 3) (match_dup 7)))
4473 24 : (set (match_dup 0)
4474 12 : (unspec:VI_16_32
4475 24 : [(match_dup 2)
4476 : (match_dup 1)
4477 : (match_dup 6)]
4478 5642 : UNSPEC_BLENDV))]
4479 5660 : {
4480 7938 : operands[6] = gen_reg_rtx (<MODE>mode);
4481 7941 : operands[7] = force_reg (<MODE>mode, operands[4]);
4482 7926 : })
4483 7920 :
4484 7920 : (define_insn_and_split "*mmx_pblendvb_v4qi_2"
4485 7938 : [(set (match_operand:V4QI 0 "register_operand")
4486 7920 : (unspec:V4QI
4487 7920 : [(match_operand:V4QI 1 "register_operand")
4488 7920 : (match_operand:V4QI 2 "register_operand")
4489 7920 : (subreg:V4QI
4490 18 : (eq:V2HI
4491 7920 : (eq:V2HI
4492 : (match_operand:V2HI 3 "register_operand")
4493 6463 : (match_operand:V2HI 4 "nonmemory_operand"))
4494 6463 : (match_operand:V2HI 5 "const0_operand")) 0)]
4495 5 : UNSPEC_BLENDV))]
4496 6518 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4497 5 : "#"
4498 15 : "&& 1"
4499 0 : [(set (match_dup 6)
4500 25 : (eq:V2HI (match_dup 3) (match_dup 8)))
4501 : (set (match_dup 0)
4502 5 : (unspec:V4QI
4503 : [(match_dup 2)
4504 851 : (match_dup 1)
4505 851 : (match_dup 7)]
4506 : UNSPEC_BLENDV))]
4507 15 : {
4508 15 : operands[6] = gen_reg_rtx (V2HImode);
4509 15 : operands[7] = lowpart_subreg (V4QImode, operands[6], V2HImode);
4510 29064 : operands[8] = force_reg (V2HImode, operands[4]);
4511 29049 : })
4512 0 :
4513 776 : ;; XOP parallel XMM conditional moves
4514 797 : (define_insn "*xop_pcmov_<mode>"
4515 : [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
4516 : (if_then_else:MMXMODE124
4517 : (match_operand:MMXMODE124 3 "register_operand" "x")
4518 : (match_operand:MMXMODE124 1 "register_operand" "x")
4519 15 : (match_operand:MMXMODE124 2 "register_operand" "x")))]
4520 174 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4521 204 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4522 : [(set_attr "type" "sse4arg")
4523 : (set_attr "mode" "TI")])
4524 404 :
4525 381 : (define_insn "*xop_pcmov_<mode>"
4526 23 : [(set (match_operand:V4F_64 0 "register_operand" "=x")
4527 407 : (if_then_else:V4F_64
4528 : (match_operand:V4F_64 3 "register_operand" "x")
4529 : (match_operand:V4F_64 1 "register_operand" "x")
4530 : (match_operand:V4F_64 2 "register_operand" "x")))]
4531 32 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4532 0 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4533 : [(set_attr "type" "sse4arg")
4534 : (set_attr "mode" "TI")])
4535 3 :
4536 3 : (define_insn "*xop_pcmov_<mode>"
4537 1 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4538 3 : (if_then_else:VI_16_32
4539 1 : (match_operand:VI_16_32 3 "register_operand" "x")
4540 0 : (match_operand:VI_16_32 1 "register_operand" "x")
4541 1 : (match_operand:VI_16_32 2 "register_operand" "x")))]
4542 0 : "TARGET_XOP"
4543 144 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4544 : [(set_attr "type" "sse4arg")
4545 : (set_attr "mode" "TI")])
4546 243 :
4547 243 : (define_insn "*xop_pcmov_<mode>"
4548 : [(set (match_operand:V2F_32 0 "register_operand" "=x")
4549 243 : (if_then_else:V2F_32
4550 : (match_operand:V2F_32 3 "register_operand" "x")
4551 : (match_operand:V2F_32 1 "register_operand" "x")
4552 : (match_operand:V2F_32 2 "register_operand" "x")))]
4553 3 : "TARGET_XOP"
4554 0 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4555 : [(set_attr "type" "sse4arg")
4556 : (set_attr "mode" "TI")])
4557 3 :
4558 3 : ;; XOP permute instructions
4559 : (define_insn "mmx_ppermv64"
4560 3 : [(set (match_operand:V8QI 0 "register_operand" "=x")
4561 268 : (unspec:V8QI
4562 268 : [(match_operand:V8QI 1 "register_operand" "x")
4563 : (match_operand:V8QI 2 "register_operand" "x")
4564 261 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4565 261 : UNSPEC_XOP_PERMUTE))]
4566 546 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4567 309 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4568 261 : [(set_attr "type" "sse4arg")
4569 : (set_attr "mode" "TI")])
4570 257 :
4571 257 : (define_insn "mmx_ppermv32"
4572 257 : [(set (match_operand:V4QI 0 "register_operand" "=x")
4573 257 : (unspec:V4QI
4574 257 : [(match_operand:V4QI 1 "register_operand" "x")
4575 : (match_operand:V4QI 2 "register_operand" "x")
4576 256 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4577 256 : UNSPEC_XOP_PERMUTE))]
4578 256 : "TARGET_XOP"
4579 256 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4580 : [(set_attr "type" "sse4arg")
4581 252 : (set_attr "mode" "TI")])
4582 :
4583 66 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4584 66 : ;;
4585 : ;; Parallel integral logical operations
4586 13969 : ;;
4587 14035 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4588 :
4589 10 : (define_expand "one_cmpl<mode>2"
4590 10 : [(set (match_operand:MMXMODEI 0 "register_operand")
4591 10 : (xor:MMXMODEI
4592 : (match_operand:MMXMODEI 1 "register_operand")
4593 10 : (match_dup 2)))]
4594 10 : "TARGET_MMX_WITH_SSE"
4595 69 : "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
4596 :
4597 10 : (define_insn "one_cmpl<mode>2"
4598 10 : [(set (match_operand:VI_16_32 0 "register_operand" "=?r,&x,&v")
4599 69 : (not:VI_16_32
4600 10 : (match_operand:VI_16_32 1 "register_operand" "0,x,v")))]
4601 10 : ""
4602 : "#"
4603 59 : [(set_attr "isa" "*,sse2,avx512vl")
4604 0 : (set_attr "type" "negnot,sselog1,sselog1")
4605 0 : (set_attr "mode" "SI,TI,TI")])
4606 :
4607 : (define_split
4608 2 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4609 13 : (not:VI_16_32
4610 2 : (match_operand:VI_16_32 1 "general_reg_operand")))]
4611 16 : "reload_completed"
4612 15 : [(set (match_dup 0)
4613 399373 : (not:SI (match_dup 1)))]
4614 37 : {
4615 39 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4616 399389 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4617 : })
4618 :
4619 : (define_split
4620 15 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4621 0 : (not:VI_16_32
4622 : (match_operand:VI_16_32 1 "sse_reg_operand")))]
4623 33 : "TARGET_SSE2 && reload_completed"
4624 18 : [(set (match_dup 0) (match_dup 2))
4625 399309 : (set (match_dup 0)
4626 47 : (xor:V16QI
4627 47 : (match_dup 0) (match_dup 1)))]
4628 399374 : {
4629 42 : operands[2] = CONSTM1_RTX (V16QImode);
4630 18 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4631 42 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4632 0 : })
4633 24 :
4634 : (define_expand "andn<mode>3"
4635 18 : [(set (match_operand:MMXMODEI 0 "register_operand")
4636 : (and:MMXMODEI
4637 : (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand"))
4638 : (match_operand:MMXMODEI 1 "register_operand")))]
4639 18 : "TARGET_MMX_WITH_SSE")
4640 :
4641 : (define_insn "mmx_andnot<mode>3"
4642 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4643 : (and:MMXMODEI
4644 0 : (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
4645 36 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4646 206 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4647 613 : "@
4648 0 : pandn\t{%2, %0|%0, %2}
4649 36 : pandn\t{%2, %0|%0, %2}
4650 1670 : vpandn\t{%2, %1, %0|%0, %1, %2}
4651 1556 : vpandnd\t{%2, %1, %0|%0, %1, %2}"
4652 114 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4653 1556 : (set_attr "mmx_isa" "native,*,*,*")
4654 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4655 15 : (set_attr "mode" "DI,TI,TI,TI")])
4656 15 :
4657 : (define_insn "*andnot<mode>3"
4658 85 : [(set (match_operand:VI_16_32 0 "register_operand" "=?&r,?r,x,x,v")
4659 85 : (and:VI_16_32
4660 85 : (not:VI_16_32
4661 : (match_operand:VI_16_32 1 "register_operand" "0,r,0,x,v"))
4662 : (match_operand:VI_16_32 2 "register_operand" "r,r,x,x,v")))
4663 13 : (clobber (reg:CC FLAGS_REG))]
4664 13 : ""
4665 : "#"
4666 100 : [(set_attr "isa" "*,bmi,sse2_noavx,avx,avx512vl")
4667 100 : (set_attr "type" "alu,bitmanip,sselog,sselog,sselog")
4668 100 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4669 :
4670 : (define_split
4671 25 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4672 25 : (and:VI_16_32
4673 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4674 0 : (match_operand:VI_16_32 2 "general_reg_operand")))
4675 0 : (clobber (reg:CC FLAGS_REG))]
4676 1 : "TARGET_BMI && reload_completed"
4677 0 : [(parallel
4678 3 : [(set (match_dup 0)
4679 : (and:SI (not:SI (match_dup 1)) (match_dup 2)))
4680 : (clobber (reg:CC FLAGS_REG))])]
4681 0 : {
4682 0 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4683 0 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4684 0 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4685 : })
4686 :
4687 : (define_split
4688 0 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4689 : (and:VI_16_32
4690 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4691 : (match_operand:VI_16_32 2 "general_reg_operand")))
4692 : (clobber (reg:CC FLAGS_REG))]
4693 3 : "!TARGET_BMI && reload_completed"
4694 3 : [(set (match_dup 0)
4695 : (not:SI (match_dup 1)))
4696 120 : (parallel
4697 58 : [(set (match_dup 0)
4698 58 : (and:SI (match_dup 0) (match_dup 2)))
4699 120 : (clobber (reg:CC FLAGS_REG))])]
4700 3 : {
4701 3 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4702 3 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4703 3 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4704 : })
4705 :
4706 : (define_split
4707 3 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4708 : (and:VI_16_32
4709 : (not:VI_16_32 (match_operand:VI_16_32 1 "sse_reg_operand"))
4710 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4711 : (clobber (reg:CC FLAGS_REG))]
4712 61 : "TARGET_SSE2 && reload_completed"
4713 : [(set (match_dup 0)
4714 58 : (and:V16QI (not:V16QI (match_dup 1)) (match_dup 2)))]
4715 58 : {
4716 2154 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4717 2189 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4718 134 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4719 2055 : })
4720 111 :
4721 37 : (define_expand "mmx_<code><mode>3"
4722 136 : [(set (match_operand:MMXMODEI 0 "register_operand")
4723 : (any_logic:MMXMODEI
4724 2 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4725 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4726 58 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4727 70 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4728 :
4729 : (define_expand "<code><mode>3"
4730 : [(set (match_operand:MMXMODEI 0 "register_operand")
4731 438 : (any_logic:MMXMODEI
4732 : (match_operand:MMXMODEI 1 "register_operand")
4733 329 : (match_operand:MMXMODEI 2 "register_operand")))]
4734 329 : "TARGET_MMX_WITH_SSE")
4735 109 :
4736 : (define_insn "*mmx_<code><mode>3"
4737 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4738 294 : (any_logic:MMXMODEI
4739 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
4740 2113 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4741 2080 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4742 32962 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4743 9083 : "@
4744 163 : p<logic>\t{%2, %0|%0, %2}
4745 777 : p<logic>\t{%2, %0|%0, %2}
4746 33713 : vp<logic>\t{%2, %1, %0|%0, %1, %2}
4747 34836 : vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
4748 22563 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4749 : (set_attr "mmx_isa" "native,*,*,*")
4750 40598 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4751 : (set_attr "mode" "DI,TI,TI,TI")])
4752 94 :
4753 5 : (define_expand "<code><mode>3"
4754 94 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand")
4755 212 : (any_logic:VI_16_32
4756 94 : (match_operand:VI_16_32 1 "nonimmediate_operand")
4757 118 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand")))]
4758 113 : ""
4759 381 : "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
4760 :
4761 : (define_insn "*<code><mode>3"
4762 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v")
4763 : (any_logic:VI_16_32
4764 : (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v")
4765 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand" "r,i,x,x,v")))
4766 : (clobber (reg:CC FLAGS_REG))]
4767 3811 : "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4768 33 : "#"
4769 1067 : [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl")
4770 1067 : (set_attr "type" "alu,alu,sselog,sselog,sselog")
4771 5962 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4772 5962 :
4773 1499 : (define_split
4774 1842 : [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand")
4775 10026 : (any_logic:VI_16_32
4776 12277 : (match_operand:VI_16_32 1 "nonimmediate_gr_operand")
4777 101 : (match_operand:VI_16_32 2 "reg_or_const_vector_operand")))
4778 4198 : (clobber (reg:CC FLAGS_REG))]
4779 4220 : "reload_completed"
4780 62 : [(parallel
4781 968 : [(set (match_dup 0)
4782 340 : (any_logic:<mmxinsnmode> (match_dup 1) (match_dup 2)))
4783 340 : (clobber (reg:CC FLAGS_REG))])]
4784 1030 : {
4785 62 : if (!register_operand (operands[2], <MODE>mode))
4786 : {
4787 9 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2],
4788 : <MODE>mode);
4789 9 : operands[2] = GEN_INT (val);
4790 : }
4791 : else
4792 53 : operands[2] = lowpart_subreg (<mmxinsnmode>mode, operands[2], <MODE>mode);
4793 62 : operands[1] = lowpart_subreg (<mmxinsnmode>mode, operands[1], <MODE>mode);
4794 62 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
4795 : })
4796 :
4797 : (define_split
4798 62 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4799 : (any_logic:VI_16_32
4800 : (match_operand:VI_16_32 1 "sse_reg_operand")
4801 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4802 62 : (clobber (reg:CC FLAGS_REG))]
4803 340 : "TARGET_SSE2 && reload_completed"
4804 : [(set (match_dup 0)
4805 340 : (any_logic:V16QI (match_dup 1) (match_dup 2)))]
4806 340 : {
4807 943 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4808 1554 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4809 396 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4810 916 : })
4811 598 :
4812 861 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4813 340 : ;;
4814 : ;; Parallel integral element swizzling
4815 : ;;
4816 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4817 340 :
4818 : (define_insn_and_split "mmx_packsswb"
4819 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4820 : (vec_concat:V8QI
4821 : (ss_truncate:V4QI
4822 : (match_operand:V4HI 1 "register_operand" "0,0,Yw"))
4823 4793 : (ss_truncate:V4QI
4824 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4825 5138 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4826 0 : "@
4827 4793 : packsswb\t{%2, %0|%0, %2}
4828 : #
4829 286 : #"
4830 98 : "&& reload_completed
4831 46 : && SSE_REGNO_P (REGNO (operands[0]))"
4832 : [(const_int 0)]
4833 92 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4834 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4835 112 : (set_attr "type" "mmxshft,sselog,sselog")
4836 224 : (set_attr "mode" "DI,TI,TI")])
4837 :
4838 : ;; This instruction does unsigned saturation of signed source
4839 : ;; and is different from generic us_truncate RTX.
4840 : (define_insn_and_split "mmx_packuswb"
4841 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4842 : (unspec:V8QI
4843 : [(match_operand:V4HI 1 "register_operand" "0,0,Yw")
4844 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")]
4845 239 : UNSPEC_US_TRUNCATE))]
4846 5897 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4847 239 : "@
4848 0 : packuswb\t{%2, %0|%0, %2}
4849 239 : #
4850 1061 : #"
4851 2191 : "&& reload_completed
4852 565 : && SSE_REGNO_P (REGNO (operands[0]))"
4853 : [(const_int 0)]
4854 1130 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4855 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4856 184 : (set_attr "type" "mmxshft,sselog,sselog")
4857 368 : (set_attr "mode" "DI,TI,TI")])
4858 :
4859 : (define_insn_and_split "mmx_packssdw"
4860 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4861 : (vec_concat:V4HI
4862 : (ss_truncate:V2HI
4863 : (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
4864 : (ss_truncate:V2HI
4865 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4866 886 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4867 0 : "@
4868 482 : packssdw\t{%2, %0|%0, %2}
4869 0 : #
4870 482 : #"
4871 112 : "&& reload_completed
4872 56 : && SSE_REGNO_P (REGNO (operands[0]))"
4873 : [(const_int 0)]
4874 112 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4875 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4876 : (set_attr "type" "mmxshft,sselog,sselog")
4877 : (set_attr "mode" "DI,TI,TI")])
4878 :
4879 : (define_insn_and_split "mmx_packusdw"
4880 2329 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
4881 : (unspec:V4HI
4882 581078 : [(match_operand:V2SI 1 "register_operand" "0,0,Yw")
4883 : (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")]
4884 583407 : UNSPEC_US_TRUNCATE))]
4885 585731 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4886 583407 : "#"
4887 583609 : "&& reload_completed"
4888 583425 : [(const_int 0)]
4889 583609 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4890 2329 : [(set_attr "isa" "noavx,noavx,avx")
4891 393545 : (set_attr "type" "sselog")
4892 393545 : (set_attr "mode" "TI")])
4893 444406 :
4894 442077 : (define_insn_and_split "mmx_punpckhbw"
4895 527200 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4896 527200 : (vec_select:V8QI
4897 527200 : (vec_concat:V16QI
4898 527200 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4899 442077 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4900 135060 : (parallel [(const_int 4) (const_int 12)
4901 471637 : (const_int 5) (const_int 13)
4902 42453 : (const_int 6) (const_int 14)
4903 41 : (const_int 7) (const_int 15)])))]
4904 1721 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4905 1616 : "@
4906 1610 : punpckhbw\t{%2, %0|%0, %2}
4907 1616 : #
4908 9669 : #"
4909 922 : "&& reload_completed
4910 430 : && SSE_REGNO_P (REGNO (operands[0]))"
4911 : [(const_int 0)]
4912 860 : "ix86_split_mmx_punpck (operands, true); DONE;"
4913 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4914 964 : (set_attr "type" "mmxcvt,sselog,sselog")
4915 1928 : (set_attr "mode" "DI,TI,TI")])
4916 :
4917 : (define_insn_and_split "mmx_punpckhbw_low"
4918 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4919 : (vec_select:V4QI
4920 : (vec_concat:V8QI
4921 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4922 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4923 90 : (parallel [(const_int 2) (const_int 6)
4924 : (const_int 3) (const_int 7)])))]
4925 4061 : "TARGET_SSE2"
4926 90 : "#"
4927 568 : "&& reload_completed"
4928 : [(const_int 0)]
4929 13179 : "ix86_split_mmx_punpck (operands, true); DONE;"
4930 131 : [(set_attr "isa" "noavx,avx")
4931 2732 : (set_attr "type" "sselog")
4932 5464 : (set_attr "mode" "TI")])
4933 :
4934 : (define_insn_and_split "mmx_punpcklbw"
4935 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4936 : (vec_select:V8QI
4937 : (vec_concat:V16QI
4938 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4939 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4940 101 : (parallel [(const_int 0) (const_int 8)
4941 : (const_int 1) (const_int 9)
4942 101 : (const_int 2) (const_int 10)
4943 101 : (const_int 3) (const_int 11)])))]
4944 7845 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4945 0 : "@
4946 : punpcklbw\t{%2, %0|%0, %k2}
4947 : #
4948 3493 : #"
4949 4457 : "&& reload_completed
4950 482 : && SSE_REGNO_P (REGNO (operands[0]))"
4951 : [(const_int 0)]
4952 964 : "ix86_split_mmx_punpck (operands, false); DONE;"
4953 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4954 478 : (set_attr "type" "mmxcvt,sselog,sselog")
4955 478 : (set_attr "mode" "DI,TI,TI")])
4956 :
4957 : (define_insn_and_split "mmx_punpcklbw_low"
4958 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4959 : (vec_select:V4QI
4960 : (vec_concat:V8QI
4961 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4962 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4963 33 : (parallel [(const_int 0) (const_int 4)
4964 : (const_int 1) (const_int 5)])))]
4965 5315 : "TARGET_SSE2"
4966 33 : "#"
4967 765 : "&& reload_completed"
4968 : [(const_int 0)]
4969 17114 : "ix86_split_mmx_punpck (operands, false); DONE;"
4970 184 : [(set_attr "isa" "noavx,avx")
4971 3598 : (set_attr "type" "sselog")
4972 7196 : (set_attr "mode" "TI")])
4973 :
4974 : (define_insn_and_split "mmx_punpckhwd"
4975 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4976 : (vec_select:V4HI
4977 : (vec_concat:V8HI
4978 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
4979 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
4980 5 : (parallel [(const_int 2) (const_int 6)
4981 : (const_int 3) (const_int 7)])))]
4982 15569 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4983 5 : "@
4984 5 : punpckhwd\t{%2, %0|%0, %2}
4985 : #
4986 4550 : #"
4987 7282 : "&& reload_completed
4988 1366 : && SSE_REGNO_P (REGNO (operands[0]))"
4989 : [(const_int 0)]
4990 2732 : "ix86_split_mmx_punpck (operands, true); DONE;"
4991 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4992 732 : (set_attr "type" "mmxcvt,sselog,sselog")
4993 732 : (set_attr "mode" "DI,TI,TI")])
4994 :
4995 : (define_insn_and_split "mmx_punpcklwd"
4996 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4997 : (vec_select:V4HI
4998 : (vec_concat:V8HI
4999 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
5000 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
5001 95 : (parallel [(const_int 0) (const_int 4)
5002 : (const_int 1) (const_int 5)])))]
5003 20259 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5004 95 : "@
5005 95 : punpcklwd\t{%2, %0|%0, %k2}
5006 : #
5007 : #"
5008 3598 : "&& reload_completed
5009 1799 : && SSE_REGNO_P (REGNO (operands[0]))"
5010 : [(const_int 0)]
5011 7983 : "ix86_split_mmx_punpck (operands, false); DONE;"
5012 4385 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5013 4394 : (set_attr "type" "mmxcvt,sselog,sselog")
5014 : (set_attr "mode" "DI,TI,TI")])
5015 :
5016 : (define_insn_and_split "mmx_punpckhdq"
5017 526412 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
5018 526412 : (vec_select:V2SI
5019 526412 : (vec_concat:V4SI
5020 526412 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
5021 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
5022 346387 : (parallel [(const_int 1)
5023 346263 : (const_int 3)])))]
5024 354390 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5025 124 : "@
5026 124 : punpckhdq\t{%2, %0|%0, %2}
5027 : #
5028 34952 : #"
5029 552 : "&& reload_completed
5030 35228 : && SSE_REGNO_P (REGNO (operands[0]))"
5031 276 : [(const_int 0)]
5032 222261 : "ix86_split_mmx_punpck (operands, true); DONE;"
5033 221985 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5034 217419 : (set_attr "type" "mmxcvt,sselog,sselog")
5035 97 : (set_attr "mode" "DI,TI,TI")])
5036 97 :
5037 11402 : (define_insn_and_split "mmx_punpckldq"
5038 56041 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
5039 56041 : (vec_select:V2SI
5040 56041 : (vec_concat:V4SI
5041 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
5042 0 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
5043 14 : (parallel [(const_int 0)
5044 : (const_int 2)])))]
5045 14959 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5046 14 : "@
5047 14 : punpckldq\t{%2, %0|%0, %k2}
5048 : #
5049 2632 : #"
5050 3356 : "&& reload_completed
5051 362 : && SSE_REGNO_P (REGNO (operands[0]))"
5052 362 : [(const_int 0)]
5053 362 : "ix86_split_mmx_punpck (operands, false); DONE;"
5054 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5055 220 : (set_attr "type" "mmxcvt,sselog,sselog")
5056 220 : (set_attr "mode" "DI,TI,TI")])
5057 :
5058 : (define_insn "sse4_1_<code>v4qiv4hi2"
5059 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
5060 : (any_extend:V4HI
5061 : (vec_select:V4QI
5062 : (match_operand:V8QI 1 "register_operand" "Yr,*x,Yw")
5063 : (parallel [(const_int 0) (const_int 1)
5064 9 : (const_int 2) (const_int 3)]))))]
5065 2602 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5066 3504 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5067 9 : [(set_attr "isa" "noavx,noavx,avx")
5068 9 : (set_attr "type" "ssemov")
5069 12957 : (set_attr "c86_attr" "vpmovx")
5070 12957 : (set_attr "prefix_extra" "1")
5071 : (set_attr "prefix" "orig,orig,maybe_evex")
5072 2770 : (set_attr "mode" "TI")])
5073 2770 :
5074 : (define_expand "<insn>v4qiv4hi2"
5075 : [(set (match_operand:V4HI 0 "register_operand")
5076 : (any_extend:V4HI
5077 : (match_operand:V4QI 1 "register_operand")))]
5078 : "TARGET_MMX_WITH_SSE"
5079 46 : {
5080 46 : if (!TARGET_SSE4_1)
5081 : {
5082 40 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5083 40 : DONE;
5084 : }
5085 :
5086 6 : rtx op1 = force_reg (V4QImode, operands[1]);
5087 6 : op1 = lowpart_subreg (V8QImode, op1, V4QImode);
5088 6 : emit_insn (gen_sse4_1_<code>v4qiv4hi2 (operands[0], op1));
5089 6 : DONE;
5090 : })
5091 :
5092 : (define_insn "sse4_1_<code>v2hiv2si2"
5093 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5094 : (any_extend:V2SI
5095 : (vec_select:V2HI
5096 : (match_operand:V4HI 1 "register_operand" "Yr,*x,v")
5097 : (parallel [(const_int 0) (const_int 1)]))))]
5098 5540 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5099 0 : "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
5100 : [(set_attr "isa" "noavx,noavx,avx")
5101 : (set_attr "type" "ssemov")
5102 329 : (set_attr "c86_attr" "vpmovx")
5103 282 : (set_attr "prefix_extra" "1")
5104 47 : (set_attr "prefix" "orig,orig,maybe_evex")
5105 47 : (set_attr "mode" "TI")])
5106 47 :
5107 : (define_expand "<insn>v2hiv2si2"
5108 : [(set (match_operand:V2SI 0 "register_operand")
5109 : (any_extend:V2SI
5110 : (match_operand:V2HI 1 "register_operand")))]
5111 : "TARGET_MMX_WITH_SSE"
5112 191 : {
5113 191 : if (!TARGET_SSE4_1)
5114 : {
5115 174 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5116 174 : DONE;
5117 : }
5118 :
5119 17 : rtx op1 = force_reg (V2HImode, operands[1]);
5120 17 : op1 = lowpart_subreg (V4HImode, op1, V2HImode);
5121 17 : emit_insn (gen_sse4_1_<code>v2hiv2si2 (operands[0], op1));
5122 17 : DONE;
5123 : })
5124 :
5125 : (define_insn "sse4_1_<code>v2qiv2si2"
5126 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5127 : (any_extend:V2SI
5128 : (vec_select:V2QI
5129 : (match_operand:V4QI 1 "register_operand" "Yr,*x,v")
5130 : (parallel [(const_int 0) (const_int 1)]))))]
5131 564 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5132 0 : "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
5133 : [(set_attr "isa" "noavx,noavx,avx")
5134 : (set_attr "type" "ssemov")
5135 388 : (set_attr "c86_attr" "vpmovx")
5136 180 : (set_attr "prefix_extra" "1")
5137 208 : (set_attr "prefix" "orig,orig,maybe_evex")
5138 208 : (set_attr "mode" "TI")])
5139 208 :
5140 : (define_expand "<insn>v2qiv2si2"
5141 : [(set (match_operand:V2SI 0 "register_operand")
5142 : (any_extend:V2SI
5143 : (match_operand:V2QI 1 "register_operand")))]
5144 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5145 38 : {
5146 38 : rtx op1 = force_reg (V2QImode, operands[1]);
5147 38 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5148 38 : emit_insn (gen_sse4_1_<code>v2qiv2si2 (operands[0], op1));
5149 38 : DONE;
5150 : })
5151 :
5152 : (define_insn "sse4_1_<code>v2qiv2hi2"
5153 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yw")
5154 : (any_extend:V2HI
5155 : (vec_select:V2QI
5156 : (match_operand:V4QI 1 "register_operand" "Yr,*x,Yw")
5157 : (parallel [(const_int 0) (const_int 1)]))))]
5158 180 : "TARGET_SSE4_1"
5159 0 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5160 : [(set_attr "isa" "noavx,noavx,avx")
5161 : (set_attr "type" "ssemov")
5162 723 : (set_attr "c86_attr" "vpmovx")
5163 : (set_attr "prefix_extra" "1")
5164 723 : (set_attr "prefix" "orig,orig,maybe_evex")
5165 723 : (set_attr "mode" "TI")])
5166 116681 :
5167 115958 : (define_expand "<insn>v2qiv2hi2"
5168 3 : [(set (match_operand:V2HI 0 "register_operand")
5169 115961 : (any_extend:V2HI
5170 : (match_operand:V2QI 1 "register_operand")))]
5171 3 : "TARGET_SSE2"
5172 222 : {
5173 222 : if (!TARGET_SSE4_1)
5174 : {
5175 207 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5176 8421 : DONE;
5177 : }
5178 :
5179 12 : rtx op1 = force_reg (V2QImode, operands[1]);
5180 8226 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5181 8226 : emit_insn (gen_sse4_1_<code>v2qiv2hi2 (operands[0], op1));
5182 8226 : DONE;
5183 8214 : })
5184 8214 :
5185 8214 : (define_expand "trunc<mode><mmxhalfmodelower>2"
5186 2085 : [(set (match_operand:<mmxhalfmode> 0 "register_operand")
5187 10233 : (truncate:<mmxhalfmode>
5188 : (match_operand:VI2_32_64 1 "register_operand")))]
5189 2019 : "TARGET_AVX2"
5190 2042 : {
5191 2042 : if (TARGET_AVX512VL && TARGET_AVX512BW)
5192 2040 : emit_insn (gen_avx512vl_trunc<mode><mmxhalfmodelower>2 (operands[0], operands[1]));
5193 : else
5194 2021 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <mmxbytemode>mode);
5195 859 : DONE;
5196 292 : })
5197 1128 :
5198 836 : (define_insn "avx512vl_trunc<mode><mmxhalfmodelower>2"
5199 938 : [(set (match_operand:<mmxhalfmode> 0 "register_operand" "=v")
5200 102 : (truncate:<mmxhalfmode>
5201 72 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
5202 335 : "TARGET_AVX512VL && TARGET_AVX512BW"
5203 : "vpmovwb\t{%1, %0|%0, %1}"
5204 : [(set_attr "type" "ssemov")
5205 : (set_attr "prefix" "evex")
5206 73 : (set_attr "mode" "TI")])
5207 73 :
5208 425 : (define_mode_iterator V2QI_V2HI [V2QI V2HI])
5209 : (define_mode_attr v2qi_quad_v2hi_double
5210 352 : [(V2QI "V8QI") (V2HI "V4HI")])
5211 352 : (define_expand "truncv2si<mode>2"
5212 352 : [(set (match_operand:V2QI_V2HI 0 "register_operand")
5213 : (truncate:V2QI_V2HI
5214 : (match_operand:V2SI 1 "register_operand")))]
5215 : "TARGET_AVX2 && TARGET_MMX_WITH_SSE"
5216 47 : {
5217 47 : if (TARGET_AVX512VL)
5218 15 : emit_insn (gen_avx512vl_truncv2si<mode>2 (operands[0], operands[1]));
5219 : else
5220 32 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <v2qi_quad_v2hi_double>mode);
5221 47 : DONE;
5222 : })
5223 :
5224 : (define_insn "avx512vl_truncv2si<mode>2"
5225 : [(set (match_operand:V2QI_V2HI 0 "register_operand" "=v")
5226 : (truncate:V2QI_V2HI
5227 : (match_operand:V2SI 1 "register_operand" "v")))]
5228 115 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
5229 : "vpmovd<mmxvecsize>\t{%1, %0|%0, %1}"
5230 39 : [(set_attr "type" "ssemov")
5231 15 : (set_attr "prefix" "evex")
5232 39 : (set_attr "mode" "TI")])
5233 :
5234 281 : ;; Pack/unpack vector modes
5235 : (define_mode_attr mmxpackmode
5236 335 : [(V4HI "V8QI") (V2SI "V4HI")])
5237 301 :
5238 335 : (define_expand "vec_pack_trunc_<mode>"
5239 : [(match_operand:<mmxpackmode> 0 "register_operand")
5240 : (match_operand:MMXMODE24 1 "register_operand")
5241 : (match_operand:MMXMODE24 2 "register_operand")]
5242 : "TARGET_MMX_WITH_SSE"
5243 723 : {
5244 723 : rtx op1 = gen_lowpart (<mmxpackmode>mode, operands[1]);
5245 723 : rtx op2 = gen_lowpart (<mmxpackmode>mode, operands[2]);
5246 723 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5247 723 : DONE;
5248 : })
5249 :
5250 : (define_expand "vec_pack_trunc_v2hi"
5251 : [(match_operand:V4QI 0 "register_operand")
5252 : (match_operand:V2HI 1 "register_operand")
5253 : (match_operand:V2HI 2 "register_operand")]
5254 : "TARGET_SSE2"
5255 24 : {
5256 24 : rtx op1 = gen_lowpart (V4QImode, operands[1]);
5257 24 : rtx op2 = gen_lowpart (V4QImode, operands[2]);
5258 24 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5259 24 : DONE;
5260 10 : })
5261 3 :
5262 10 : (define_mode_attr mmxunpackmode
5263 13 : [(V8QI "V4HI") (V4HI "V2SI")])
5264 10 :
5265 3 : (define_expand "vec_unpacks_lo_<mode>"
5266 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5267 : (match_operand:MMXMODE12 1 "register_operand")]
5268 : "TARGET_MMX_WITH_SSE"
5269 602 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5270 :
5271 : (define_expand "vec_unpacks_hi_<mode>"
5272 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5273 0 : (match_operand:MMXMODE12 1 "register_operand")]
5274 : "TARGET_MMX_WITH_SSE"
5275 602 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5276 0 :
5277 0 : (define_expand "vec_unpacku_lo_<mode>"
5278 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5279 : (match_operand:MMXMODE12 1 "register_operand")]
5280 : "TARGET_MMX_WITH_SSE"
5281 900 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5282 :
5283 451 : (define_expand "vec_unpacku_hi_<mode>"
5284 451 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5285 451 : (match_operand:MMXMODE12 1 "register_operand")]
5286 : "TARGET_MMX_WITH_SSE"
5287 461 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5288 :
5289 10 : (define_expand "vec_unpacks_lo_v4qi"
5290 10 : [(match_operand:V2HI 0 "register_operand")
5291 10 : (match_operand:V4QI 1 "register_operand")]
5292 : "TARGET_SSE2"
5293 75 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5294 0 :
5295 75 : (define_expand "vec_unpacks_hi_v4qi"
5296 75 : [(match_operand:V2HI 0 "register_operand")
5297 75 : (match_operand:V4QI 1 "register_operand")]
5298 0 : "TARGET_SSE2"
5299 202 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5300 71 :
5301 202 : (define_expand "vec_unpacku_lo_v4qi"
5302 273 : [(match_operand:V2HI 0 "register_operand")
5303 202 : (match_operand:V4QI 1 "register_operand")]
5304 71 : "TARGET_SSE2"
5305 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5306 2384 :
5307 : (define_expand "vec_unpacku_hi_v4qi"
5308 2384 : [(match_operand:V2HI 0 "register_operand")
5309 0 : (match_operand:V4QI 1 "register_operand")]
5310 2384 : "TARGET_SSE2"
5311 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5312 198 :
5313 : (define_insn "*mmx_pinsrd"
5314 198 : [(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
5315 0 : (vec_merge:V2SI
5316 198 : (vec_duplicate:V2SI
5317 : (match_operand:SI 2 "nonimmediate_operand" "jrjm,rm"))
5318 61 : (match_operand:V2SI 1 "register_operand" "0,Yv")
5319 : (match_operand:SI 3 "const_int_operand")))]
5320 259 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5321 198 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5322 259 : < GET_MODE_NUNITS (V2SImode))"
5323 98 : {
5324 52 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5325 26 : switch (which_alternative)
5326 21 : {
5327 21 : case 1:
5328 0 : return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5329 0 : case 0:
5330 21 : return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
5331 0 : default:
5332 0 : gcc_unreachable ();
5333 : }
5334 : }
5335 : [(set_attr "isa" "noavx,avx")
5336 : (set_attr "addr" "gpr16,*")
5337 : (set_attr "prefix_extra" "1")
5338 0 : (set_attr "type" "sselog")
5339 : (set_attr "c86_attr" "insr")
5340 : (set_attr "length_immediate" "1")
5341 : (set_attr "prefix" "orig,vex")
5342 : (set_attr "mode" "TI")])
5343 :
5344 : (define_insn "*mmx_pinsrw"
5345 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,x,YW,&x")
5346 : (vec_merge:V4FI_64
5347 : (vec_duplicate:V4FI_64
5348 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,rm,x"))
5349 : (match_operand:V4FI_64 1 "register_operand" "0,0,YW,x")
5350 : (match_operand:SI 3 "const_int_operand")))]
5351 63 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5352 406 : && (TARGET_SSE || TARGET_3DNOW_A)
5353 406 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5354 15 : < GET_MODE_NUNITS (V4HImode))"
5355 251 : {
5356 41 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5357 41 : switch (which_alternative)
5358 619 : {
5359 619 : case 3:
5360 : return "#";
5361 16 : case 2:
5362 1026 : if (MEM_P (operands[2]))
5363 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5364 : else
5365 16 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5366 25 : case 1:
5367 25 : case 0:
5368 25 : if (MEM_P (operands[2]))
5369 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
5370 : else
5371 15 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
5372 0 : default:
5373 0 : gcc_unreachable ();
5374 : }
5375 : }
5376 : [(set_attr "isa" "*,sse2_noavx,avx,sse4")
5377 : (set_attr "mmx_isa" "native,*,*,*")
5378 : (set_attr "type" "mmxcvt,sselog,sselog,sselog")
5379 42 : (set_attr "c86_attr" "insr")
5380 : (set_attr "length_immediate" "1")
5381 : (set_attr "mode" "DI,TI,TI,TI")])
5382 :
5383 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
5384 : (define_split
5385 : [(set (match_operand:V4FI_64 0 "sse_reg_operand")
5386 : (vec_merge:V4FI_64
5387 : (vec_duplicate:V4FI_64
5388 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
5389 : (match_operand:V4FI_64 1 "sse_reg_operand")
5390 : (match_operand:SI 3 "const_int_operand")))]
5391 3 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 && reload_completed
5392 3 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5393 3 : < GET_MODE_NUNITS (<MODE>mode))"
5394 : [(set (match_dup 0)
5395 3 : (vec_duplicate:V4FI_64 (match_dup 2)))
5396 : (set (match_dup 0)
5397 123 : (vec_merge:V4FI_64 (match_dup 1) (match_dup 0) (match_dup 3)))]
5398 126 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0xf);")
5399 :
5400 : (define_insn "*mmx_pinsrb"
5401 126 : [(set (match_operand:V8QI 0 "register_operand" "=x,YW")
5402 : (vec_merge:V8QI
5403 : (vec_duplicate:V8QI
5404 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
5405 : (match_operand:V8QI 1 "register_operand" "0,YW")
5406 3 : (match_operand:SI 3 "const_int_operand")))]
5407 10 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5408 10 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5409 10 : < GET_MODE_NUNITS (V8QImode))"
5410 15 : {
5411 28188 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5412 1 : switch (which_alternative)
5413 28193 : {
5414 28194 : case 1:
5415 28187 : if (MEM_P (operands[2]))
5416 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5417 7 : else
5418 1 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5419 0 : case 0:
5420 0 : if (MEM_P (operands[2]))
5421 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
5422 : else
5423 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
5424 0 : default:
5425 0 : gcc_unreachable ();
5426 : }
5427 : }
5428 : [(set_attr "isa" "noavx,avx")
5429 : (set_attr "type" "sselog")
5430 : (set_attr "c86_attr" "insr")
5431 : (set_attr "addr" "gpr16,*")
5432 : (set_attr "prefix_extra" "1")
5433 : (set_attr "length_immediate" "1")
5434 : (set_attr "prefix" "orig,vex")
5435 : (set_attr "mode" "TI")])
5436 :
5437 : (define_insn "*mmx_pextrw"
5438 8 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,jm,m")
5439 : (vec_select:HI
5440 : (match_operand:V4HI 1 "register_operand" "y,YW,YW,YW")
5441 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5442 2334 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5443 2334 : && (TARGET_SSE || TARGET_3DNOW_A)"
5444 : "@
5445 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5446 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
5447 718 : pextrw\t{%2, %1, %0|%0, %1, %2}
5448 718 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
5449 706 : [(set_attr "isa" "*,sse2,sse4_noavx,avx")
5450 718 : (set_attr "addr" "*,*,gpr16,*")
5451 : (set_attr "mmx_isa" "native,*,*,*")
5452 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
5453 : (set_attr "c86_attr" "extr")
5454 : (set_attr "length_immediate" "1")
5455 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
5456 : (set_attr "mode" "DI,TI,TI,TI")])
5457 :
5458 : (define_insn "*mmx_pextrw<mode>"
5459 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,?r,jm,m,x,Yw")
5460 : (vec_select:<mmxscalarmode>
5461 : (match_operand:V4F_64 1 "register_operand" "y,YW,YW,YW,0,YW")
5462 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5463 14 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5464 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5465 8 : {
5466 8 : switch (which_alternative)
5467 : {
5468 1313 : case 0:
5469 1313 : case 1:
5470 1296 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
5471 1317 : case 2:
5472 4 : case 3:
5473 4 : return "%vpextrw\t{%2, %1, %0|%0, %1, %2}";
5474 4 : case 4:
5475 4 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5476 4 : return "psrldq\t{%2, %0|%0, %2}";
5477 0 : case 5:
5478 0 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5479 0 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
5480 :
5481 0 : default:
5482 0 : gcc_unreachable ();
5483 : }
5484 : }
5485 : [(set_attr "isa" "*,sse2,sse4_noavx,avx,noavx,avx")
5486 : (set_attr "addr" "*,*,gpr16,*,*,*")
5487 : (set_attr "mmx_isa" "native,*,*,*,*,*")
5488 0 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
5489 : (set_attr "c86_attr" "extr,extr,extr,extr,*,*")
5490 : (set_attr "length_immediate" "1")
5491 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
5492 : (set_attr "mode" "DI,TI,TI,TI,TI,TI")])
5493 :
5494 : (define_insn "*mmx_pextrw_zext"
5495 : [(set (match_operand:SWI48 0 "register_operand" "=r,r")
5496 : (zero_extend:SWI48
5497 : (vec_select:HI
5498 : (match_operand:V4HI 1 "register_operand" "y,YW")
5499 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
5500 7132 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5501 7132 : && (TARGET_SSE || TARGET_3DNOW_A)"
5502 : "@
5503 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5504 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
5505 5731 : [(set_attr "isa" "*,sse2")
5506 5731 : (set_attr "mmx_isa" "native,*")
5507 : (set_attr "type" "mmxcvt,sselog1")
5508 : (set_attr "c86_attr" "extr")
5509 : (set_attr "length_immediate" "1")
5510 : (set_attr "prefix" "orig,maybe_vex")
5511 : (set_attr "mode" "DI,TI")])
5512 :
5513 : (define_insn "*mmx_pextrb"
5514 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
5515 0 : (vec_select:QI
5516 : (match_operand:V8QI 1 "register_operand" "YW,YW,YW,YW")
5517 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))]
5518 2705 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5519 : "@
5520 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
5521 : pextrb\t{%2, %1, %0|%0, %1, %2}
5522 157 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
5523 157 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
5524 121 : [(set_attr "isa" "noavx,noavx,avx,avx")
5525 157 : (set_attr "addr" "*,gpr16,*,*")
5526 : (set_attr "type" "sselog1")
5527 : (set_attr "c86_attr" "extr")
5528 : (set_attr "prefix_extra" "1")
5529 : (set_attr "length_immediate" "1")
5530 : (set_attr "prefix" "maybe_vex")
5531 : (set_attr "mode" "TI")])
5532 :
5533 : (define_insn "*mmx_pextrb_zext"
5534 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
5535 : (zero_extend:SWI248
5536 : (vec_select:QI
5537 : (match_operand:V8QI 1 "register_operand" "YW,YW")
5538 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))]
5539 4981 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5540 0 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
5541 : [(set_attr "isa" "noavx,avx")
5542 : (set_attr "type" "sselog1")
5543 386 : (set_attr "c86_attr" "extr")
5544 386 : (set_attr "prefix_extra" "1")
5545 : (set_attr "length_immediate" "1")
5546 : (set_attr "prefix" "maybe_vex")
5547 : (set_attr "mode" "TI")])
5548 :
5549 : (define_insn "mmx_pshufbv8qi3"
5550 : [(set (match_operand:V8QI 0 "register_operand" "=x,Yw")
5551 : (unspec:V8QI
5552 : [(match_operand:V8QI 1 "register_operand" "0,Yw")
5553 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5554 : UNSPEC_PSHUFB))]
5555 2670 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
5556 281 : "@
5557 : pshufb\t{%2, %0|%0, %2}
5558 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5559 2919 : [(set_attr "isa" "noavx,avx")
5560 2919 : (set_attr "addr" "gpr16,*")
5561 2919 : (set_attr "type" "sselog1")
5562 2919 : (set_attr "prefix_extra" "1")
5563 2919 : (set_attr "prefix" "orig,maybe_evex")
5564 : (set_attr "btver2_decode" "vector")
5565 : (set_attr "mode" "TI")])
5566 :
5567 : (define_insn "mmx_pshufbv4qi3"
5568 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
5569 : (unspec:V4QI
5570 : [(match_operand:V4QI 1 "register_operand" "0,Yw")
5571 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5572 : UNSPEC_PSHUFB))]
5573 2721 : "TARGET_SSSE3"
5574 198 : "@
5575 : pshufb\t{%2, %0|%0, %2}
5576 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5577 : [(set_attr "isa" "noavx,avx")
5578 : (set_attr "addr" "gpr16,*")
5579 : (set_attr "type" "sselog1")
5580 : (set_attr "prefix_extra" "1")
5581 43851 : (set_attr "prefix" "orig,maybe_evex")
5582 43851 : (set_attr "btver2_decode" "vector")
5583 : (set_attr "mode" "TI")])
5584 11223 :
5585 11223 : (define_expand "mmx_pshufw"
5586 11223 : [(match_operand:V4HI 0 "register_operand")
5587 : (match_operand:V4HI 1 "register_mmxmem_operand")
5588 11139 : (match_operand:SI 2 "const_int_operand")]
5589 11139 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5590 11139 : && (TARGET_SSE || TARGET_3DNOW_A)"
5591 75 : {
5592 9500 : int mask = INTVAL (operands[2]);
5593 9500 : emit_insn (gen_mmx_pshufwv4hi_1 (operands[0], operands[1],
5594 9425 : GEN_INT ((mask >> 0) & 3),
5595 14977 : GEN_INT ((mask >> 2) & 3),
5596 75 : GEN_INT ((mask >> 4) & 3),
5597 75 : GEN_INT ((mask >> 6) & 3)));
5598 75 : DONE;
5599 : })
5600 :
5601 : (define_insn "mmx_pshufw<mode>_1"
5602 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,Yw")
5603 : (vec_select:V4FI_64
5604 : (match_operand:V4FI_64 1 "register_mmxmem_operand" "ym,Yw")
5605 : (parallel [(match_operand 2 "const_0_to_3_operand")
5606 : (match_operand 3 "const_0_to_3_operand")
5607 : (match_operand 4 "const_0_to_3_operand")
5608 : (match_operand 5 "const_0_to_3_operand")])))]
5609 417 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5610 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5611 6500 : {
5612 1164 : int mask = 0;
5613 1164 : mask |= INTVAL (operands[2]) << 0;
5614 13283 : mask |= INTVAL (operands[3]) << 2;
5615 13283 : mask |= INTVAL (operands[4]) << 4;
5616 10194 : mask |= INTVAL (operands[5]) << 6;
5617 9030 : operands[2] = GEN_INT (mask);
5618 19350 :
5619 1164 : switch (which_alternative)
5620 : {
5621 : case 0:
5622 : return "pshufw\t{%2, %1, %0|%0, %1, %2}";
5623 1164 : case 1:
5624 5572063 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
5625 0 : default:
5626 0 : gcc_unreachable ();
5627 : }
5628 5570899 : }
5629 5570899 : [(set_attr "isa" "*,sse2")
5630 5570899 : (set_attr "mmx_isa" "native,*")
5631 5570899 : (set_attr "type" "mmxcvt,sselog1")
5632 5572847 : (set_attr "length_immediate" "1")
5633 5570899 : (set_attr "mode" "DI,TI")])
5634 5570899 :
5635 : (define_insn "*mmx_pshufd_1"
5636 16900 : [(set (match_operand:V2SI 0 "register_operand" "=Yv")
5637 16900 : (vec_select:V2SI
5638 : (match_operand:V2SI 1 "register_operand" "Yv")
5639 16900 : (parallel [(match_operand 2 "const_0_to_1_operand")
5640 16900 : (match_operand 3 "const_0_to_1_operand")])))]
5641 27124 : "TARGET_MMX_WITH_SSE"
5642 784 : {
5643 17684 : int mask = 0;
5644 17684 : mask |= INTVAL (operands[2]) << 0;
5645 17691 : mask |= INTVAL (operands[3]) << 2;
5646 791 : mask |= 2 << 4;
5647 17691 : mask |= 3 << 6;
5648 791 : operands[2] = GEN_INT (mask);
5649 7 :
5650 1808 : return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
5651 48 : }
5652 1053 : [(set_attr "type" "sselog1")
5653 : (set_attr "prefix_data16" "1")
5654 : (set_attr "length_immediate" "1")
5655 : (set_attr "mode" "TI")])
5656 :
5657 : (define_insn "*mmx_pblendw64"
5658 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yr,*x,x")
5659 : (vec_merge:V4FI_64
5660 : (match_operand:V4FI_64 2 "register_operand" "Yr,*x,x")
5661 : (match_operand:V4FI_64 1 "register_operand" "0,0,x")
5662 : (match_operand:SI 3 "const_0_to_15_operand")))]
5663 2953 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5664 : "@
5665 : pblendw\t{%3, %2, %0|%0, %2, %3}
5666 : pblendw\t{%3, %2, %0|%0, %2, %3}
5667 6234 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5668 6234 : [(set_attr "isa" "noavx,noavx,avx")
5669 : (set_attr "type" "ssemov")
5670 6234 : (set_attr "c86_attr" "blend")
5671 : (set_attr "prefix_extra" "1")
5672 : (set_attr "length_immediate" "1")
5673 : (set_attr "prefix" "orig,orig,vex")
5674 : (set_attr "mode" "TI")])
5675 :
5676 : (define_insn "*mmx_pblendw32"
5677 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yr,*x,x")
5678 : (vec_merge:V2FI_32
5679 : (match_operand:V2FI_32 2 "register_operand" "Yr,*x,x")
5680 : (match_operand:V2FI_32 1 "register_operand" "0,0,x")
5681 : (match_operand:SI 3 "const_0_to_7_operand")))]
5682 1 : "TARGET_SSE4_1"
5683 : "@
5684 : pblendw\t{%3, %2, %0|%0, %2, %3}
5685 : pblendw\t{%3, %2, %0|%0, %2, %3}
5686 64 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5687 64 : [(set_attr "isa" "noavx,noavx,avx")
5688 : (set_attr "type" "ssemov")
5689 163606 : (set_attr "c86_attr" "blend")
5690 : (set_attr "prefix_extra" "1")
5691 68808 : (set_attr "length_immediate" "1")
5692 68808 : (set_attr "prefix" "orig,orig,vex")
5693 : (set_attr "mode" "TI")])
5694 2319 :
5695 2319 : ;; Optimize V2SImode load from memory, swapping the elements and
5696 : ;; storing back into the memory into DImode rotate of the memory by 32.
5697 2319 : (define_split
5698 : [(set (match_operand:V2SI 0 "memory_operand")
5699 : (vec_select:V2SI (match_dup 0)
5700 : (parallel [(const_int 1) (const_int 0)])))]
5701 71 : "TARGET_64BIT && (TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())"
5702 71 : [(set (match_dup 0)
5703 : (rotate:DI (match_dup 0) (const_int 32)))]
5704 71 : "operands[0] = adjust_address (operands[0], DImode, 0);")
5705 :
5706 : (define_insn "mmx_pswapdv2si2"
5707 71 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5708 : (vec_select:V2SI
5709 463306 : (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")
5710 : (parallel [(const_int 1) (const_int 0)])))]
5711 283299 : "TARGET_3DNOW_A"
5712 430370 : "@
5713 : pswapd\t{%1, %0|%0, %1}
5714 207359 : %vpshufd\t{$0xe1, %1, %0|%0, %1, 0xe1}";
5715 1283088 : [(set_attr "isa" "*,sse2")
5716 1373664 : (set_attr "mmx_isa" "native,*")
5717 1283088 : (set_attr "type" "mmxcvt,sselog1")
5718 12 : (set_attr "prefix_extra" "1,*")
5719 1283100 : (set_attr "length_immediate" "*,1")
5720 12 : (set_attr "mode" "DI,TI")])
5721 906414 :
5722 906414 : (define_insn "*vec_dupv4hi"
5723 : [(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
5724 105860 : (vec_duplicate:V4HI
5725 105860 : (truncate:HI
5726 : (match_operand:SI 1 "register_operand" "0,Yw"))))]
5727 20506 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5728 20422 : && (TARGET_SSE || TARGET_3DNOW_A)"
5729 0 : "@
5730 : pshufw\t{$0, %0, %0|%0, %0, 0}
5731 : %vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5732 252 : [(set_attr "isa" "*,sse2")
5733 252 : (set_attr "mmx_isa" "native,*")
5734 252 : (set_attr "type" "mmxcvt,sselog1")
5735 252 : (set_attr "length_immediate" "1")
5736 : (set_attr "mode" "DI,TI")])
5737 :
5738 : (define_insn "*vec_dup<mode>"
5739 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yw")
5740 : (vec_duplicate:V4FI_64
5741 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
5742 32 : "TARGET_MMX_WITH_SSE"
5743 75 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5744 : [(set_attr "isa" "sse2")
5745 : (set_attr "type" "sselog1")
5746 14498 : (set_attr "length_immediate" "1")
5747 14498 : (set_attr "mode" "TI")])
5748 13274 :
5749 13274 : (define_insn "*vec_dupv2si"
5750 17949 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5751 : (vec_duplicate:V2SI
5752 : (match_operand:SI 1 "register_operand" "0,Yv")))]
5753 10147 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5754 1168 : "@
5755 : punpckldq\t%0, %0
5756 : %vpshufd\t{$0xe0, %1, %0|%0, %1, 0xe0}"
5757 61 : [(set_attr "isa" "*,sse2")
5758 61 : (set_attr "mmx_isa" "native,*")
5759 50 : (set_attr "type" "mmxcvt,sselog1")
5760 50 : (set_attr "prefix_data16" "*,1")
5761 61 : (set_attr "length_immediate" "*,1")
5762 : (set_attr "mode" "DI,TI")])
5763 :
5764 : (define_insn "*mmx_concatv2si"
5765 : [(set (match_operand:V2SI 0 "register_operand" "=y,y")
5766 : (vec_concat:V2SI
5767 : (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
5768 : (match_operand:SI 2 "nonimm_or_0_operand" "ym,C")))]
5769 266757 : "TARGET_MMX && !TARGET_SSE"
5770 : "@
5771 266757 : punpckldq\t{%2, %0|%0, %2}
5772 : movd\t{%1, %0|%0, %1}"
5773 : [(set_attr "type" "mmxcvt,mmxmov")
5774 : (set_attr "mode" "DI")])
5775 :
5776 : (define_expand "vec_setv2si"
5777 : [(match_operand:V2SI 0 "register_operand")
5778 : (match_operand:SI 1 "register_operand")
5779 : (match_operand 2 "vec_setm_mmx_operand")]
5780 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5781 202 : {
5782 202 : if (CONST_INT_P (operands[2]))
5783 200 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5784 200 : INTVAL (operands[2]));
5785 : else
5786 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5787 202 : DONE;
5788 : })
5789 :
5790 : ;; Avoid combining registers from different units in a single alternative,
5791 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5792 : (define_insn_and_split "*vec_extractv2si_0"
5793 : [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r,r")
5794 : (vec_select:SI
5795 : (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m,x")
5796 : (parallel [(const_int 0)])))]
5797 30154 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5798 30154 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5799 : "#"
5800 4832 : "&& reload_completed"
5801 2384 : [(set (match_dup 0) (match_dup 1))]
5802 369649 : "operands[1] = gen_lowpart (SImode, operands[1]);"
5803 367265 : [(set_attr "isa" "*,*,*,*,*,sse2")
5804 491221 : (set_attr "mmx_isa" "*,*,native,native,*,*")
5805 126340 : (set (attr "preferred_for_speed")
5806 123956 : (cond [(eq_attr "alternative" "5")
5807 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5808 2384 : ]
5809 : (symbol_ref "true")))])
5810 :
5811 : (define_insn "*vec_extractv2si_0_zext_sse4"
5812 : [(set (match_operand:DI 0 "register_operand" "=r,x")
5813 9 : (zero_extend:DI
5814 : (vec_select:SI
5815 9 : (match_operand:V2SI 1 "register_operand" "x,x")
5816 9 : (parallel [(const_int 0)]))))]
5817 856 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE4_1"
5818 : "#"
5819 847 : [(set_attr "isa" "x64,*")
5820 : (set (attr "preferred_for_speed")
5821 : (cond [(eq_attr "alternative" "0")
5822 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5823 : ]
5824 : (symbol_ref "true")))])
5825 :
5826 : (define_insn "*vec_extractv2si_0_zext"
5827 : [(set (match_operand:DI 0 "register_operand" "=r")
5828 : (zero_extend:DI
5829 : (vec_select:SI
5830 : (match_operand:V2SI 1 "register_operand" "x")
5831 : (parallel [(const_int 0)]))))]
5832 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5833 847 : && TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC"
5834 : "#")
5835 :
5836 : (define_split
5837 : [(set (match_operand:DI 0 "register_operand")
5838 3121 : (zero_extend:DI
5839 3121 : (vec_select:SI
5840 : (match_operand:V2SI 1 "register_operand")
5841 2622 : (parallel [(const_int 0)]))))]
5842 396 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5843 396 : && TARGET_SSE2 && reload_completed"
5844 198 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5845 198 : "operands[1] = gen_lowpart (SImode, operands[1]);")
5846 :
5847 1366 : ;; Avoid combining registers from different units in a single alternative,
5848 1564 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5849 1366 : (define_insn "*vec_extractv2si_1"
5850 : [(set (match_operand:SI 0 "nonimmediate_operand" "=y,jrjm,rm,x,x,y,x,r")
5851 198 : (vec_select:SI
5852 : (match_operand:V2SI 1 "nonimmediate_operand" " 0,x, x ,x,0,o,o,o")
5853 : (parallel [(const_int 1)])))]
5854 19405 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5855 19405 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5856 847 : "@
5857 : punpckhdq\t%0, %0
5858 847 : pextrd\t{$1, %1, %0|%0, %1, 1}
5859 209215 : vpextrd\t{$1, %1, %0|%0, %1, 1}
5860 209215 : %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
5861 202100 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
5862 202100 : #
5863 407994 : #
5864 : #"
5865 : [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*")
5866 : (set (attr "addr")
5867 : (if_then_else (eq_attr "alternative" "1")
5868 : (const_string "gpr16")
5869 : (const_string "*")))
5870 : (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
5871 : (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
5872 : (set_attr "c86_attr" "*,extr,extr,*,*,*,*,*")
5873 : (set (attr "length_immediate")
5874 : (if_then_else (eq_attr "alternative" "1,2,3,4")
5875 : (const_string "1")
5876 : (const_string "*")))
5877 : (set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,orig,orig,orig,orig")
5878 : (set_attr "mode" "DI,TI,TI,TI,V4SF,SI,SI,SI")])
5879 :
5880 : (define_split
5881 : [(set (match_operand:SI 0 "register_operand")
5882 : (vec_select:SI
5883 : (match_operand:V2SI 1 "memory_operand")
5884 : (parallel [(const_int 1)])))]
5885 62 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
5886 61 : [(set (match_dup 0) (match_dup 1))]
5887 61 : "operands[1] = adjust_address (operands[1], SImode, 4);")
5888 :
5889 5365 : (define_insn "*vec_extractv2si_1_zext"
5890 5426 : [(set (match_operand:DI 0 "register_operand" "=jr,r")
5891 4095 : (zero_extend:DI
5892 4095 : (vec_select:SI
5893 5455 : (match_operand:V2SI 1 "register_operand" "x,x")
5894 : (parallel [(const_int 1)]))))]
5895 968 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5896 968 : && TARGET_64BIT && TARGET_SSE4_1"
5897 : "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
5898 0 : [(set_attr "isa" "noavx,avx")
5899 : (set_attr "type" "sselog1")
5900 0 : (set_attr "c86_attr" "extr")
5901 0 : (set_attr "prefix_extra" "1")
5902 0 : (set_attr "length_immediate" "1")
5903 3972 : (set_attr "prefix" "maybe_vex")
5904 3972 : (set_attr "mode" "TI")])
5905 :
5906 1448 : (define_insn_and_split "*vec_extractv2si_zext_mem"
5907 1448 : [(set (match_operand:DI 0 "register_operand" "=y,x,r")
5908 2 : (zero_extend:DI
5909 1450 : (vec_select:SI
5910 : (match_operand:V2SI 1 "memory_operand" "o,o,o")
5911 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
5912 2 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_64BIT"
5913 1446 : "#"
5914 0 : "&& reload_completed"
5915 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5916 0 : {
5917 2497 : operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
5918 745 : }
5919 3242 : [(set_attr "isa" "*,sse2,*")
5920 2497 : (set_attr "mmx_isa" "native,*,*")])
5921 745 :
5922 : (define_expand "vec_extractv2sisi"
5923 : [(match_operand:SI 0 "register_operand")
5924 0 : (match_operand:V2SI 1 "register_operand")
5925 : (match_operand 2 "const_int_operand")]
5926 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5927 9565 : {
5928 9565 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5929 13049 : operands[1], INTVAL (operands[2]));
5930 9565 : DONE;
5931 3484 : })
5932 3484 :
5933 3484 : (define_expand "vec_initv2sisi"
5934 : [(match_operand:V2SI 0 "register_operand")
5935 : (match_operand 1)]
5936 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5937 18619 : {
5938 34449 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5939 : operands[1]);
5940 18619 : DONE;
5941 : })
5942 :
5943 2 : (define_expand "vec_set<mode>"
5944 : [(match_operand:V4FI_64 0 "register_operand")
5945 2 : (match_operand:<mmxscalarmode> 1 "register_operand")
5946 2 : (match_operand 2 "vec_setm_mmx_operand")]
5947 2 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5948 11 : {
5949 11 : if (CONST_INT_P (operands[2]))
5950 12 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5951 8 : INTVAL (operands[2]));
5952 : else
5953 7 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5954 11 : DONE;
5955 4 : })
5956 4 :
5957 4 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
5958 : [(match_operand:<mmxscalarmode> 0 "register_operand")
5959 : (match_operand:V4FI_64 1 "register_operand")
5960 : (match_operand 2 "const_int_operand")]
5961 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5962 856 : {
5963 884 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5964 856 : operands[1], INTVAL (operands[2]));
5965 856 : DONE;
5966 : })
5967 1068 :
5968 : (define_expand "vec_initv4hihi"
5969 1068 : [(match_operand:V4HI 0 "register_operand")
5970 1068 : (match_operand 1)]
5971 1068 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5972 3484 : {
5973 3489 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5974 : operands[1]);
5975 3484 : DONE;
5976 : })
5977 :
5978 2 : (define_expand "vec_init<mode><mmxscalarmodelower>"
5979 0 : [(match_operand:V4F_64 0 "register_operand")
5980 2 : (match_operand 1)]
5981 2 : "TARGET_MMX_WITH_SSE"
5982 29 : {
5983 27 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5984 : operands[1]);
5985 27 : DONE;
5986 : })
5987 :
5988 : (define_expand "vec_setv8qi"
5989 1 : [(match_operand:V8QI 0 "register_operand")
5990 : (match_operand:QI 1 "register_operand")
5991 1 : (match_operand 2 "vec_setm_mmx_operand")]
5992 0 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5993 3 : {
5994 2 : if (CONST_INT_P (operands[2]))
5995 0 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5996 0 : INTVAL (operands[2]));
5997 : else
5998 29 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5999 2 : DONE;
6000 27 : })
6001 27 :
6002 27 : (define_expand "vec_extractv8qiqi"
6003 : [(match_operand:QI 0 "register_operand")
6004 : (match_operand:V8QI 1 "register_operand")
6005 : (match_operand 2 "const_int_operand")]
6006 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
6007 630 : {
6008 630 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
6009 630 : operands[1], INTVAL (operands[2]));
6010 630 : DONE;
6011 : })
6012 0 :
6013 : (define_expand "vec_initv8qiqi"
6014 0 : [(match_operand:V8QI 0 "register_operand")
6015 0 : (match_operand 1)]
6016 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
6017 343 : {
6018 347 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6019 : operands[1]);
6020 343 : DONE;
6021 : })
6022 :
6023 442 : (define_insn "*pinsrw"
6024 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,YW,&x")
6025 442 : (vec_merge:V2FI_32
6026 442 : (vec_duplicate:V2FI_32
6027 442 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,x"))
6028 : (match_operand:V2FI_32 1 "register_operand" "0,YW,x")
6029 : (match_operand:SI 3 "const_int_operand")))]
6030 7 : "TARGET_SSE2
6031 682 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6032 7 : < GET_MODE_NUNITS (V2HImode))"
6033 538 : {
6034 61 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6035 63 : switch (which_alternative)
6036 1152 : {
6037 1152 : case 2:
6038 : return "#";
6039 1 : case 1:
6040 1826 : if (MEM_P (operands[2]))
6041 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6042 : else
6043 0 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6044 60 : case 0:
6045 60 : if (MEM_P (operands[2]))
6046 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
6047 : else
6048 41 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6049 0 : default:
6050 0 : gcc_unreachable ();
6051 : }
6052 : }
6053 : [(set_attr "isa" "noavx,avx,sse4")
6054 : (set_attr "type" "sselog")
6055 : (set_attr "c86_attr" "insr")
6056 61 : (set_attr "length_immediate" "1")
6057 : (set_attr "mode" "TI")])
6058 :
6059 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
6060 : (define_split
6061 : [(set (match_operand:V2FI_32 0 "sse_reg_operand")
6062 : (vec_merge:V2FI_32
6063 : (vec_duplicate:V2FI_32
6064 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
6065 : (match_operand:V2FI_32 1 "sse_reg_operand")
6066 : (match_operand:SI 3 "const_int_operand")))]
6067 1 : "TARGET_SSE4_1 && reload_completed
6068 1 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6069 1 : < GET_MODE_NUNITS (<MODE>mode))"
6070 : [(set (match_dup 0)
6071 1 : (vec_duplicate:V2FI_32 (match_dup 2)))
6072 : (set (match_dup 0)
6073 232 : (vec_merge:V2FI_32 (match_dup 1) (match_dup 0) (match_dup 3)))]
6074 233 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0x3);")
6075 :
6076 :
6077 233 : (define_insn "*pinsrb"
6078 : [(set (match_operand:V4QI 0 "register_operand" "=x,YW")
6079 1439488 : (vec_merge:V4QI
6080 : (vec_duplicate:V4QI
6081 1439488 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
6082 1439489 : (match_operand:V4QI 1 "register_operand" "0,YW")
6083 1439488 : (match_operand:SI 3 "const_int_operand")))]
6084 0 : "TARGET_SSE4_1
6085 1439488 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6086 0 : < GET_MODE_NUNITS (V4QImode))"
6087 78 : {
6088 1117230 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6089 93 : switch (which_alternative)
6090 93 : {
6091 93 : case 1:
6092 0 : if (MEM_P (operands[2]))
6093 15 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6094 3041 : else
6095 3041 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6096 0 : case 0:
6097 81 : if (MEM_P (operands[2]))
6098 81 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
6099 : else
6100 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6101 0 : default:
6102 0 : gcc_unreachable ();
6103 0 : }
6104 0 : }
6105 : [(set_attr "isa" "noavx,avx")
6106 : (set_attr "addr" "gpr16,*")
6107 : (set_attr "type" "sselog")
6108 : (set_attr "c86_attr" "insr")
6109 : (set_attr "prefix_extra" "1")
6110 : (set_attr "length_immediate" "1")
6111 : (set_attr "prefix" "orig,vex")
6112 : (set_attr "mode" "TI")])
6113 :
6114 85 : (define_insn "*pextrw"
6115 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,jm,m")
6116 : (vec_select:HI
6117 : (match_operand:V2HI 1 "register_operand" "YW,YW,YW")
6118 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6119 706 : "TARGET_SSE2"
6120 : "@
6121 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
6122 : pextrw\t{%2, %1, %0|%0, %1, %2}
6123 18553 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
6124 18553 : [(set_attr "isa" "*,sse4_noavx,avx")
6125 18380 : (set_attr "addr" "*,gpr16,*")
6126 36933 : (set_attr "type" "sselog1")
6127 : (set_attr "c86_attr" "extr")
6128 : (set_attr "length_immediate" "1")
6129 : (set_attr "prefix" "maybe_vex")
6130 : (set_attr "mode" "TI")])
6131 :
6132 : (define_insn "*pextrw<mode>"
6133 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,jm,m,x,Yw")
6134 : (vec_select:<mmxscalarmode>
6135 : (match_operand:V2F_32 1 "register_operand" "YW,YW,YW,0,YW")
6136 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6137 1296 : "TARGET_SSE2"
6138 102 : {
6139 85 : switch (which_alternative)
6140 : {
6141 3917 : case 0:
6142 3917 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
6143 3770 : case 1:
6144 7687 : return "pextrw\t{%2, %1, %0|%0, %1, %2}";
6145 0 : case 2:
6146 0 : return "vpextrw\t{%2, %1, %0|%0, %1, %2}";
6147 11 : case 3:
6148 11 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6149 11 : return "psrldq\t{%2, %0|%0, %2}";
6150 14 : case 4:
6151 14 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6152 14 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
6153 :
6154 0 : default:
6155 0 : gcc_unreachable ();
6156 : }
6157 : }
6158 : [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
6159 : (set_attr "addr" "*,gpr16,*,*,*")
6160 : (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
6161 0 : (set_attr "c86_attr" "extr,extr,extr,*,*")
6162 : (set_attr "length_immediate" "1")
6163 : (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
6164 : (set_attr "mode" "TI")])
6165 :
6166 : (define_insn "*pextrw_zext"
6167 : [(set (match_operand:SWI48 0 "register_operand" "=r")
6168 0 : (zero_extend:SWI48
6169 : (vec_select:HI
6170 : (match_operand:V2HI 1 "register_operand" "YW")
6171 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
6172 5775 : "TARGET_SSE2"
6173 : "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
6174 : [(set_attr "type" "sselog1")
6175 : (set_attr "c86_attr" "extr")
6176 55845 : (set_attr "length_immediate" "1")
6177 55845 : (set_attr "prefix" "maybe_vex")
6178 : (set_attr "mode" "TI")])
6179 :
6180 : (define_insn "*pextrb"
6181 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
6182 : (vec_select:QI
6183 : (match_operand:V4QI 1 "register_operand" "YW,YW,YW,YW")
6184 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
6185 121 : "TARGET_SSE4_1"
6186 : "@
6187 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
6188 : pextrb\t{%2, %1, %0|%0, %1, %2}
6189 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
6190 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
6191 : [(set_attr "isa" "noavx,noavx,avx,avx")
6192 : (set_attr "addr" "*,gpr16,*,*")
6193 5252 : (set_attr "type" "sselog1")
6194 5252 : (set_attr "c86_attr" "extr")
6195 2862 : (set_attr "prefix_extra" "1")
6196 8114 : (set_attr "length_immediate" "1")
6197 : (set_attr "prefix" "maybe_vex")
6198 : (set_attr "mode" "TI")])
6199 :
6200 : (define_insn "*pextrb_zext"
6201 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
6202 : (zero_extend:SWI248
6203 : (vec_select:QI
6204 : (match_operand:V4QI 1 "register_operand" "YW,YW")
6205 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
6206 386 : "TARGET_SSE4_1"
6207 0 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
6208 : [(set_attr "isa" "noavx,avx")
6209 : (set_attr "type" "sselog1")
6210 14232 : (set_attr "c86_attr" "extr")
6211 14232 : (set_attr "prefix_extra" "1")
6212 : (set_attr "length_immediate" "1")
6213 : (set_attr "prefix" "maybe_vex")
6214 : (set_attr "mode" "TI")])
6215 :
6216 : (define_expand "vec_set<mode>"
6217 : [(match_operand:V2FI_32 0 "register_operand")
6218 : (match_operand:<mmxscalarmode> 1 "register_operand")
6219 : (match_operand 2 "vec_setm_sse41_operand")]
6220 : "TARGET_SSE2"
6221 29 : {
6222 29 : if (CONST_INT_P (operands[2]))
6223 26 : ix86_expand_vector_set (false, operands[0], operands[1],
6224 26 : INTVAL (operands[2]));
6225 : else
6226 3 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6227 29 : DONE;
6228 : })
6229 :
6230 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
6231 : [(match_operand:<mmxscalarmode> 0 "register_operand")
6232 : (match_operand:V2FI_32 1 "register_operand")
6233 : (match_operand 2 "const_int_operand")]
6234 : "TARGET_SSE2"
6235 537 : {
6236 537 : ix86_expand_vector_extract (false, operands[0],
6237 537 : operands[1], INTVAL (operands[2]));
6238 537 : DONE;
6239 : })
6240 483 :
6241 : (define_expand "vec_setv4qi"
6242 483 : [(match_operand:V4QI 0 "register_operand")
6243 483 : (match_operand:QI 1 "register_operand")
6244 483 : (match_operand 2 "vec_setm_mmx_operand")]
6245 : "TARGET_SSE4_1"
6246 2 : {
6247 2 : if (CONST_INT_P (operands[2]))
6248 0 : ix86_expand_vector_set (false, operands[0], operands[1],
6249 0 : INTVAL (operands[2]));
6250 : else
6251 4324 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6252 182 : DONE;
6253 4322 : })
6254 4502 :
6255 4322 : (define_expand "vec_extractv4qiqi"
6256 180 : [(match_operand:QI 0 "register_operand")
6257 : (match_operand:V4QI 1 "register_operand")
6258 : (match_operand 2 "const_int_operand")]
6259 : "TARGET_SSE4_1"
6260 78 : {
6261 78 : ix86_expand_vector_extract (false, operands[0],
6262 78 : operands[1], INTVAL (operands[2]));
6263 78 : DONE;
6264 : })
6265 0 :
6266 : (define_insn_and_split "*punpckwd"
6267 0 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,Yw")
6268 0 : (vec_select:V2FI_32
6269 0 : (vec_concat:<mmxdoublevecmode>
6270 : (match_operand:V2FI_32 1 "register_operand" "0,Yw")
6271 : (match_operand:V2FI_32 2 "register_operand" "x,Yw"))
6272 : (parallel [(match_operand 3 "const_0_to_3_operand")
6273 : (match_operand 4 "const_0_to_3_operand")])))]
6274 0 : "TARGET_SSE2"
6275 0 : "#"
6276 23 : "&& reload_completed"
6277 : [(set (match_dup 5)
6278 2002 : (vec_select:<mmxxmmmode>
6279 1822 : (match_dup 5)
6280 383 : (parallel [(match_dup 3) (match_dup 4)
6281 360 : (const_int 2) (const_int 3)
6282 5935 : (const_int 4) (const_int 5)
6283 5935 : (const_int 6) (const_int 7)])))]
6284 1040 : {
6285 1050 : rtx dest = lowpart_subreg (<mmxxmmmode>mode, operands[0], <MODE>mode);
6286 180 : rtx op1 = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
6287 180 : rtx op2 = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
6288 :
6289 180 : emit_insn (gen_vec_interleave_low<mmxxmmmodelower> (dest, op1, op2));
6290 :
6291 180 : static const int map[4] = { 0, 2, 1, 3 };
6292 :
6293 180 : int sel0 = map[INTVAL (operands[3])];
6294 180 : int sel1 = map[INTVAL (operands[4])];
6295 :
6296 180 : if (sel0 == 0 && sel1 == 1)
6297 69 : DONE;
6298 :
6299 111 : operands[3] = GEN_INT (sel0);
6300 111 : operands[4] = GEN_INT (sel1);
6301 111 : operands[5] = dest;
6302 : }
6303 : [(set_attr "isa" "noavx,avx")
6304 : (set_attr "type" "sselog")
6305 111 : (set_attr "mode" "TI")])
6306 :
6307 : (define_insn "*pshufw<mode>_1"
6308 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6309 : (vec_select:V2FI_32
6310 : (match_operand:V2FI_32 1 "register_operand" "Yw")
6311 111 : (parallel [(match_operand 2 "const_0_to_1_operand")
6312 : (match_operand 3 "const_0_to_1_operand")])))]
6313 0 : "TARGET_SSE2"
6314 84 : {
6315 84 : int mask = 0;
6316 102 : mask |= INTVAL (operands[2]) << 0;
6317 1881 : mask |= INTVAL (operands[3]) << 2;
6318 1899 : mask |= 2 << 4;
6319 1737 : mask |= 3 << 6;
6320 1653 : operands[2] = GEN_INT (mask);
6321 3115 :
6322 147226 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
6323 28350 : }
6324 15649 : [(set_attr "type" "sselog1")
6325 1251 : (set_attr "length_immediate" "1")
6326 1251 : (set_attr "mode" "TI")])
6327 147265 :
6328 : (define_insn "*vec_dupv2hi"
6329 : [(set (match_operand:V2HI 0 "register_operand" "=Yw")
6330 : (vec_duplicate:V2HI
6331 : (truncate:HI
6332 : (match_operand:SI 1 "register_operand" "Yw"))))]
6333 252 : "TARGET_SSE2"
6334 0 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6335 : [(set_attr "type" "sselog1")
6336 : (set_attr "length_immediate" "1")
6337 : (set_attr "mode" "TI")])
6338 :
6339 : (define_insn "*vec_dup<mode>"
6340 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6341 : (vec_duplicate:V2FI_32
6342 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
6343 50 : "TARGET_SSE2"
6344 66 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6345 : [(set_attr "type" "sselog1")
6346 : (set_attr "length_immediate" "1")
6347 6669 : (set_attr "mode" "TI")])
6348 1074 :
6349 1019 : (define_expand "vec_init<mode><mmxscalarmodelower>"
6350 1019 : [(match_operand:V2FI_32 0 "register_operand")
6351 2093 : (match_operand 1)]
6352 1010 : "TARGET_SSE2"
6353 6078 : {
6354 7145 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6355 5595 : operands[1]);
6356 1493 : DONE;
6357 5595 : })
6358 1010 :
6359 5595 : (define_expand "vec_initv4qiqi"
6360 5595 : [(match_operand:V2HI 0 "register_operand")
6361 758 : (match_operand 1)]
6362 758 : "TARGET_SSE2"
6363 5922 : {
6364 8525 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6365 : operands[1]);
6366 8444 : DONE;
6367 4122 : })
6368 4074 :
6369 8606 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6370 : ;;
6371 408 : ;; Miscellaneous
6372 408 : ;;
6373 408 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6374 :
6375 : (define_expand "mmx_uavg<mode>3"
6376 : [(set (match_operand:MMXMODE12 0 "register_operand")
6377 : (truncate:MMXMODE12
6378 : (lshiftrt:<mmxdoublemode>
6379 16 : (plus:<mmxdoublemode>
6380 : (plus:<mmxdoublemode>
6381 16 : (zero_extend:<mmxdoublemode>
6382 16 : (match_operand:MMXMODE12 1 "register_mmxmem_operand"))
6383 16 : (zero_extend:<mmxdoublemode>
6384 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))
6385 : (match_dup 3))
6386 : (const_int 1))))]
6387 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6388 : && (TARGET_SSE || TARGET_3DNOW)"
6389 0 : {
6390 0 : operands[3] = CONST1_RTX(<mmxdoublemode>mode);
6391 0 : ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
6392 : })
6393 :
6394 : (define_insn "*mmx_uavgv8qi3"
6395 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
6396 0 : (truncate:V8QI
6397 : (lshiftrt:V8HI
6398 : (plus:V8HI
6399 : (plus:V8HI
6400 : (zero_extend:V8HI
6401 0 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw"))
6402 : (zero_extend:V8HI
6403 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))
6404 : (const_vector:V8HI [(const_int 1) (const_int 1)
6405 : (const_int 1) (const_int 1)
6406 343 : (const_int 1) (const_int 1)
6407 : (const_int 1) (const_int 1)]))
6408 343 : (const_int 1))))]
6409 549 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6410 549 : && (TARGET_SSE || TARGET_3DNOW)
6411 206 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6412 206 : {
6413 39 : switch (which_alternative)
6414 : {
6415 152 : case 2:
6416 152 : return "vpavgb\t{%2, %1, %0|%0, %1, %2}";
6417 167 : case 1:
6418 15 : case 0:
6419 152 : /* These two instructions have the same operation, but their encoding
6420 152 : is different. Prefer the one that is de facto standard. */
6421 15 : if (TARGET_SSE || TARGET_3DNOW_A)
6422 152 : return "pavgb\t{%2, %0|%0, %2}";
6423 152 : else
6424 0 : return "pavgusb\t{%2, %0|%0, %2}";
6425 152 : default:
6426 152 : gcc_unreachable ();
6427 : }
6428 152 : }
6429 : [(set_attr "isa" "*,sse2_noavx,avx")
6430 132 : (set_attr "mmx_isa" "native,*,*")
6431 132 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6432 : (set (attr "prefix_extra")
6433 : (if_then_else
6434 188 : (not (ior (match_test "TARGET_SSE")
6435 132 : (match_test "TARGET_3DNOW_A")))
6436 : (const_string "1")
6437 0 : (const_string "*")))
6438 : (set_attr "mode" "DI,TI,TI")])
6439 :
6440 : (define_insn "*mmx_uavgv4hi3"
6441 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
6442 : (truncate:V4HI
6443 : (lshiftrt:V4SI
6444 191290 : (plus:V4SI
6445 191290 : (plus:V4SI
6446 191290 : (zero_extend:V4SI
6447 191290 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
6448 191290 : (zero_extend:V4SI
6449 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
6450 : (const_vector:V4SI [(const_int 1) (const_int 1)
6451 : (const_int 1) (const_int 1)]))
6452 : (const_int 1))))]
6453 120 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6454 120 : && (TARGET_SSE || TARGET_3DNOW_A)
6455 120 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6456 12 : "@
6457 152 : pavgw\t{%2, %0|%0, %2}
6458 152 : pavgw\t{%2, %0|%0, %2}
6459 172 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6460 172 : [(set_attr "isa" "*,sse2_noavx,avx")
6461 152 : (set_attr "mmx_isa" "native,*,*")
6462 152 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6463 20 : (set_attr "mode" "DI,TI,TI")])
6464 :
6465 11161 : (define_expand "uavg<mode>3_ceil"
6466 : [(set (match_operand:MMXMODE12 0 "register_operand")
6467 : (truncate:MMXMODE12
6468 : (lshiftrt:<mmxdoublemode>
6469 : (plus:<mmxdoublemode>
6470 : (plus:<mmxdoublemode>
6471 0 : (zero_extend:<mmxdoublemode>
6472 0 : (match_operand:MMXMODE12 1 "register_operand"))
6473 0 : (zero_extend:<mmxdoublemode>
6474 : (match_operand:MMXMODE12 2 "register_operand")))
6475 : (match_dup 3))
6476 : (const_int 1))))]
6477 : "TARGET_MMX_WITH_SSE"
6478 62 : "operands[3] = CONST1_RTX(<mmxdoublemode>mode);")
6479 :
6480 : (define_insn "uavgv4qi3_ceil"
6481 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
6482 116 : (truncate:V4QI
6483 54 : (lshiftrt:V4HI
6484 54 : (plus:V4HI
6485 54 : (plus:V4HI
6486 : (zero_extend:V4HI
6487 62 : (match_operand:V4QI 1 "register_operand" "%0,Yw"))
6488 : (zero_extend:V4HI
6489 : (match_operand:V4QI 2 "register_operand" "x,Yw")))
6490 : (const_vector:V4HI [(const_int 1) (const_int 1)
6491 : (const_int 1) (const_int 1)]))
6492 30 : (const_int 1))))]
6493 5 : "TARGET_SSE2"
6494 700203 : "@
6495 700188 : pavgb\t{%2, %0|%0, %2}
6496 700188 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6497 : [(set_attr "isa" "noavx,avx")
6498 : (set_attr "type" "sseiadd")
6499 : (set_attr "mode" "TI")])
6500 :
6501 222 : (define_insn "uavgv2qi3_ceil"
6502 222 : [(set (match_operand:V2QI 0 "register_operand" "=x,Yw")
6503 222 : (truncate:V2QI
6504 : (lshiftrt:V2HI
6505 222 : (plus:V2HI
6506 222 : (plus:V2HI
6507 : (zero_extend:V2HI
6508 222 : (match_operand:V2QI 1 "register_operand" "%0,Yw"))
6509 : (zero_extend:V2HI
6510 202 : (match_operand:V2QI 2 "register_operand" "x,Yw")))
6511 202 : (const_vector:V2HI [(const_int 1) (const_int 1)]))
6512 : (const_int 1))))]
6513 110 : "TARGET_SSE2"
6514 202 : "@
6515 : pavgb\t{%2, %0|%0, %2}
6516 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6517 20 : [(set_attr "isa" "noavx,avx")
6518 20 : (set_attr "type" "sseiadd")
6519 : (set_attr "mode" "TI")])
6520 :
6521 20 : (define_insn "uavgv2hi3_ceil"
6522 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
6523 : (truncate:V2HI
6524 : (lshiftrt:V2SI
6525 : (plus:V2SI
6526 : (plus:V2SI
6527 : (zero_extend:V2SI
6528 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
6529 : (zero_extend:V2SI
6530 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
6531 : (const_vector:V2SI [(const_int 1) (const_int 1)]))
6532 : (const_int 1))))]
6533 5 : "TARGET_SSE2"
6534 15 : "@
6535 : pavgw\t{%2, %0|%0, %2}
6536 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6537 : [(set_attr "isa" "noavx,avx")
6538 : (set_attr "type" "sseiadd")
6539 : (set_attr "mode" "TI")])
6540 :
6541 : (define_expand "mmx_psadbw"
6542 : [(set (match_operand:V1DI 0 "register_operand")
6543 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand")
6544 : (match_operand:V8QI 2 "register_mmxmem_operand")]
6545 527 : UNSPEC_PSADBW))]
6546 527 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)"
6547 890 : "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
6548 :
6549 522 : (define_insn "*mmx_psadbw"
6550 522 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yw")
6551 885 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
6552 522 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")]
6553 522 : UNSPEC_PSADBW))]
6554 5999 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)
6555 6362 : && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
6556 4473 : "@
6557 522 : psadbw\t{%2, %0|%0, %2}
6558 522 : psadbw\t{%2, %0|%0, %2}
6559 837 : vpsadbw\t{%2, %1, %0|%0, %1, %2}"
6560 1000 : [(set_attr "isa" "*,sse2_noavx,avx")
6561 163 : (set_attr "mmx_isa" "native,*,*")
6562 836 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6563 0 : (set_attr "c86_attr" "sadbw")
6564 359 : (set_attr "mode" "DI,TI,TI")])
6565 338 :
6566 137 : (define_expand "reduc_<code>_scal_<mode>"
6567 120 : [(any_logic:MMXMODE12
6568 403 : (match_operand:<mmxscalarmode> 0 "register_operand")
6569 : (match_operand:MMXMODE12 1 "register_operand"))]
6570 : "TARGET_MMX_WITH_SSE"
6571 48 : {
6572 48 : rtx tmp = gen_reg_rtx (<MODE>mode);
6573 48 : ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
6574 48 : emit_insn (gen_vec_extract<mode><mmxscalarmodelower> (operands[0],
6575 : tmp, const0_rtx));
6576 48 : DONE;
6577 : })
6578 :
6579 : (define_expand "reduc_<code>_scal_v4qi"
6580 : [(any_logic:V4QI
6581 : (match_operand:QI 0 "register_operand")
6582 : (match_operand:V4QI 1 "register_operand"))]
6583 : "TARGET_SSE2"
6584 30 : {
6585 30 : rtx tmp = gen_reg_rtx (V4QImode);
6586 30 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6587 30 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6588 30 : DONE;
6589 243 : })
6590 :
6591 243 : (define_expand "reduc_plus_scal_v8qi"
6592 243 : [(plus:V8QI
6593 243 : (match_operand:QI 0 "register_operand")
6594 : (match_operand:V8QI 1 "register_operand"))]
6595 : "TARGET_MMX_WITH_SSE"
6596 335 : {
6597 335 : rtx tmp = gen_reg_rtx (V8QImode);
6598 335 : emit_move_insn (tmp, CONST0_RTX (V8QImode));
6599 335 : rtx tmp2 = gen_reg_rtx (V1DImode);
6600 335 : emit_insn (gen_mmx_psadbw (tmp2, operands[1], tmp));
6601 341 : tmp2 = gen_lowpart (V8QImode, tmp2);
6602 335 : emit_insn (gen_vec_extractv8qiqi (operands[0], tmp2, const0_rtx));
6603 341 : DONE;
6604 6 : })
6605 6 :
6606 : (define_expand "reduc_plus_scal_v4hi"
6607 : [(plus:V4HI
6608 : (match_operand:HI 0 "register_operand")
6609 : (match_operand:V4HI 1 "register_operand"))]
6610 : "TARGET_MMX_WITH_SSE"
6611 231 : {
6612 231 : rtx tmp = gen_reg_rtx (V4HImode);
6613 231 : ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
6614 231 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6615 231 : DONE;
6616 5 : })
6617 :
6618 5 : (define_expand "reduc_<code>_scal_v4hi"
6619 5 : [(smaxmin:V4HI
6620 5 : (match_operand:HI 0 "register_operand")
6621 : (match_operand:V4HI 1 "register_operand"))]
6622 : "TARGET_MMX_WITH_SSE"
6623 4 : {
6624 4 : rtx tmp = gen_reg_rtx (V4HImode);
6625 4 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6626 4 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6627 4 : DONE;
6628 318 : })
6629 :
6630 318 : (define_expand "reduc_<code>_scal_v4qi"
6631 318 : [(smaxmin:V4QI
6632 318 : (match_operand:QI 0 "register_operand")
6633 : (match_operand:V4QI 1 "register_operand"))]
6634 : "TARGET_SSE4_1"
6635 4 : {
6636 4 : rtx tmp = gen_reg_rtx (V4QImode);
6637 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6638 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6639 4 : DONE;
6640 16 : })
6641 :
6642 16 : (define_expand "reduc_<code>_scal_v4hi"
6643 16 : [(umaxmin:V4HI
6644 16 : (match_operand:HI 0 "register_operand")
6645 : (match_operand:V4HI 1 "register_operand"))]
6646 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6647 6 : {
6648 6 : rtx tmp = gen_reg_rtx (V4HImode);
6649 6 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6650 6 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6651 6 : DONE;
6652 12 : })
6653 :
6654 12 : (define_expand "reduc_<code>_scal_v4qi"
6655 12 : [(umaxmin:V4QI
6656 12 : (match_operand:QI 0 "register_operand")
6657 : (match_operand:V4QI 1 "register_operand"))]
6658 : "TARGET_SSE4_1"
6659 4 : {
6660 4 : rtx tmp = gen_reg_rtx (V4QImode);
6661 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6662 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6663 4 : DONE;
6664 45 : })
6665 :
6666 45 : (define_expand "reduc_plus_scal_v4qi"
6667 45 : [(plus:V4QI
6668 45 : (match_operand:QI 0 "register_operand")
6669 : (match_operand:V4QI 1 "register_operand"))]
6670 : "TARGET_SSE2"
6671 318 : {
6672 318 : rtx op1 = gen_reg_rtx (V16QImode);
6673 318 : emit_insn (gen_vec_setv4si_0 (lowpart_subreg (V4SImode, op1, V16QImode),
6674 : CONST0_RTX (V4SImode),
6675 : lowpart_subreg (SImode,
6676 1 : operands[1],
6677 22 : V4QImode)));
6678 319 : rtx tmp = gen_reg_rtx (V16QImode);
6679 341 : emit_move_insn (tmp, CONST0_RTX (V16QImode));
6680 318 : rtx tmp2 = gen_reg_rtx (V2DImode);
6681 340 : emit_insn (gen_sse2_psadbw (tmp2, op1, tmp));
6682 318 : tmp2 = gen_lowpart (V16QImode, tmp2);
6683 319 : emit_insn (gen_vec_extractv16qiqi (operands[0], tmp2, const0_rtx));
6684 318 : DONE;
6685 : })
6686 :
6687 : (define_expand "usadv8qi"
6688 15 : [(match_operand:V2SI 0 "register_operand")
6689 : (match_operand:V8QI 1 "register_operand")
6690 15 : (match_operand:V8QI 2 "register_operand")
6691 15 : (match_operand:V2SI 3 "register_operand")]
6692 : "TARGET_MMX_WITH_SSE"
6693 5 : {
6694 5 : rtx t1 = gen_reg_rtx (V1DImode);
6695 5 : rtx t2 = gen_reg_rtx (V2SImode);
6696 5 : emit_insn (gen_mmx_psadbw (t1, operands[1], operands[2]));
6697 20120 : convert_move (t2, t1, 0);
6698 5 : emit_insn (gen_addv2si3 (operands[0], t2, operands[3]));
6699 20120 : DONE;
6700 20115 : })
6701 20115 :
6702 : (define_expand "usdot_prodv2siv8qi"
6703 : [(match_operand:V2SI 0 "register_operand")
6704 : (match_operand:V8QI 1 "register_operand")
6705 : (match_operand:V8QI 2 "register_operand")
6706 : (match_operand:V2SI 3 "register_operand")]
6707 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6708 7 : {
6709 7 : operands[1] = force_reg (V8QImode, operands[1]);
6710 7 : operands[2] = force_reg (V8QImode, operands[2]);
6711 7 : operands[3] = force_reg (V2SImode, operands[3]);
6712 :
6713 112 : if ((TARGET_AVX512VNNI && TARGET_AVX512VL)
6714 5 : || TARGET_AVXVNNI)
6715 105 : {
6716 110 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6717 5 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6718 5 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6719 5 : rtx op0 = gen_reg_rtx (V4SImode);
6720 :
6721 5 : emit_insn (gen_usdot_prodv4siv16qi (op0, op1, op2, op3));
6722 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6723 5 : }
6724 : else
6725 : {
6726 2 : rtx op1 = gen_reg_rtx (V8HImode);
6727 2 : rtx op2 = gen_reg_rtx (V8HImode);
6728 2 : rtx op3 = gen_reg_rtx (V4SImode);
6729 2 : rtx op0 = gen_reg_rtx (V4SImode);
6730 2 : rtx op0_1 = gen_reg_rtx (V4SImode);
6731 :
6732 2 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6733 2 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6734 2 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6735 2 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6736 :
6737 : /* vec_perm (op0, 2, 3, 0, 1); */
6738 2 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6739 2 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6740 2 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6741 : lowpart_subreg (V2SImode, op0, V4SImode)));
6742 : }
6743 7 : DONE;
6744 : })
6745 :
6746 : (define_expand "sdot_prodv2siv8qi"
6747 : [(match_operand:V2SI 0 "register_operand")
6748 : (match_operand:V8QI 1 "register_operand")
6749 : (match_operand:V8QI 2 "register_operand")
6750 : (match_operand:V2SI 3 "register_operand")]
6751 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6752 9 : {
6753 9 : operands[1] = force_reg (V8QImode, operands[1]);
6754 9 : operands[2] = force_reg (V8QImode, operands[2]);
6755 9 : operands[3] = force_reg (V2SImode, operands[3]);
6756 :
6757 538025 : if (TARGET_AVXVNNIINT8)
6758 : {
6759 538021 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6760 538021 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6761 538021 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6762 5 : rtx op0 = gen_reg_rtx (V4SImode);
6763 :
6764 5 : emit_insn (gen_sdot_prodv4siv16qi (op0, op1, op2, op3));
6765 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6766 : }
6767 : else
6768 : {
6769 4 : rtx op1 = gen_reg_rtx (V8HImode);
6770 4 : rtx op2 = gen_reg_rtx (V8HImode);
6771 4 : rtx op3 = gen_reg_rtx (V4SImode);
6772 4 : rtx op0 = gen_reg_rtx (V4SImode);
6773 4 : rtx op0_1 = gen_reg_rtx (V4SImode);
6774 :
6775 4 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6776 4 : emit_insn (gen_extendv8qiv8hi2 (op1, operands[1]));
6777 4 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6778 4 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6779 :
6780 : /* vec_perm (op0, 2, 3, 0, 1); */
6781 4 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6782 4 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6783 4 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6784 : lowpart_subreg (V2SImode, op0, V4SImode)));
6785 : }
6786 9 : DONE;
6787 :
6788 : })
6789 :
6790 : (define_expand "udot_prodv2siv8qi"
6791 : [(match_operand:V2SI 0 "register_operand")
6792 : (match_operand:V8QI 1 "register_operand")
6793 : (match_operand:V8QI 2 "register_operand")
6794 : (match_operand:V2SI 3 "register_operand")]
6795 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6796 9 : {
6797 9 : operands[1] = force_reg (V8QImode, operands[1]);
6798 9 : operands[2] = force_reg (V8QImode, operands[2]);
6799 9 : operands[3] = force_reg (V2SImode, operands[3]);
6800 :
6801 152 : if (TARGET_AVXVNNIINT8)
6802 : {
6803 148 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6804 148 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6805 148 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6806 5 : rtx op0 = gen_reg_rtx (V4SImode);
6807 :
6808 5 : emit_insn (gen_udot_prodv4siv16qi (op0, op1, op2, op3));
6809 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6810 : }
6811 : else
6812 : {
6813 4 : rtx op1 = gen_reg_rtx (V8HImode);
6814 4 : rtx op2 = gen_reg_rtx (V8HImode);
6815 4 : rtx op3 = gen_reg_rtx (V4SImode);
6816 4 : rtx op0 = gen_reg_rtx (V4SImode);
6817 4 : rtx op0_1 = gen_reg_rtx (V4SImode);
6818 :
6819 4 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6820 4 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6821 4 : emit_insn (gen_zero_extendv8qiv8hi2 (op2, operands[2]));
6822 4 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6823 :
6824 : /* vec_perm (op0, 2, 3, 0, 1); */
6825 4 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6826 4 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6827 4 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6828 : lowpart_subreg (V2SImode, op0, V4SImode)));
6829 : }
6830 9 : DONE;
6831 :
6832 : })
6833 :
6834 : (define_expand "usdot_prodv2siv4hi"
6835 : [(match_operand:V2SI 0 "register_operand")
6836 : (match_operand:V4HI 1 "register_operand")
6837 : (match_operand:V4HI 2 "register_operand")
6838 : (match_operand:V2SI 3 "register_operand")]
6839 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6840 3 : {
6841 3 : operands[1] = force_reg (V4HImode, operands[1]);
6842 3 : operands[2] = force_reg (V4HImode, operands[2]);
6843 3 : operands[3] = force_reg (V2SImode, operands[3]);
6844 :
6845 16607 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6846 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6847 16607 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6848 16607 : rtx op0 = gen_reg_rtx (V4SImode);
6849 16604 :
6850 3 : emit_insn (gen_usdot_prodv4siv8hi (op0, op1, op2, op3));
6851 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6852 3 : DONE;
6853 : })
6854 :
6855 : (define_expand "udot_prodv2siv4hi"
6856 : [(match_operand:V2SI 0 "register_operand")
6857 : (match_operand:V4HI 1 "register_operand")
6858 : (match_operand:V4HI 2 "register_operand")
6859 : (match_operand:V2SI 3 "register_operand")]
6860 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6861 3 : {
6862 3 : operands[1] = force_reg (V4HImode, operands[1]);
6863 3 : operands[2] = force_reg (V4HImode, operands[2]);
6864 3 : operands[3] = force_reg (V2SImode, operands[3]);
6865 :
6866 9236 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6867 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6868 9236 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6869 9236 : rtx op0 = gen_reg_rtx (V4SImode);
6870 9233 :
6871 3 : emit_insn (gen_udot_prodv4siv8hi (op0, op1, op2, op3));
6872 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6873 3 : DONE;
6874 : })
6875 :
6876 : (define_expand "sdot_prodv2siv4hi"
6877 : [(match_operand:V2SI 0 "register_operand")
6878 : (match_operand:V4HI 1 "register_operand")
6879 : (match_operand:V4HI 2 "register_operand")
6880 : (match_operand:V2SI 3 "register_operand")]
6881 : "TARGET_MMX_WITH_SSE"
6882 42 : {
6883 42 : operands[1] = force_reg (V4HImode, operands[1]);
6884 42 : operands[2] = force_reg (V4HImode, operands[2]);
6885 42 : operands[3] = force_reg (V2SImode, operands[3]);
6886 :
6887 14956 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6888 42 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6889 14956 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6890 14956 : rtx op0 = gen_reg_rtx (V4SImode);
6891 14914 :
6892 42 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6893 42 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6894 42 : DONE;
6895 : })
6896 :
6897 : (define_insn_and_split "mmx_pmovmskb"
6898 : [(set (match_operand:SI 0 "register_operand" "=r,r,jr")
6899 : (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x,x")]
6900 : UNSPEC_MOVMSK))]
6901 111 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6902 111 : && (TARGET_SSE || TARGET_3DNOW_A)"
6903 : "@
6904 : pmovmskb\t{%1, %0|%0, %1}
6905 : #
6906 109 : #"
6907 153 : "TARGET_SSE2 && reload_completed
6908 128999 : && SSE_REGNO_P (REGNO (operands[1]))"
6909 22 : [(set (match_dup 0)
6910 144679 : (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
6911 144679 : (set (match_dup 0)
6912 128868 : (zero_extend:SI (match_dup 2)))]
6913 5019 : {
6914 4997 : /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
6915 44 : operands[1] = lowpart_subreg (V16QImode, operands[1],
6916 22 : GET_MODE (operands[1]));
6917 44 : operands[2] = lowpart_subreg (QImode, operands[0],
6918 22 : GET_MODE (operands[0]));
6919 0 : }
6920 0 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
6921 : (set_attr "type" "mmxcvt,ssemov,ssemov")
6922 22 : (set_attr "mode" "DI,TI,TI")])
6923 :
6924 : (define_expand "mmx_maskmovq"
6925 : [(set (match_operand:V8QI 0 "memory_operand")
6926 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
6927 22 : (match_operand:V8QI 2 "register_operand")
6928 : (match_dup 0)]
6929 : UNSPEC_MASKMOV))]
6930 : "TARGET_SSE || TARGET_3DNOW_A")
6931 :
6932 17069 : (define_insn "*mmx_maskmovq"
6933 : [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
6934 17069 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
6935 17069 : (match_operand:V8QI 2 "register_operand" "y")
6936 17069 : (mem:V8QI (match_dup 0))]
6937 : UNSPEC_MASKMOV))]
6938 9 : "TARGET_SSE || TARGET_3DNOW_A"
6939 : ;; @@@ check ordering of operands in intel/nonintel syntax
6940 : "maskmovq\t{%2, %1|%1, %2}"
6941 : [(set_attr "type" "mmxcvt")
6942 : (set_attr "znver1_decode" "vector")
6943 : (set_attr "c86_decode" "vector")
6944 : (set_attr "mode" "DI")])
6945 :
6946 : (define_int_iterator EMMS
6947 104 : [(UNSPECV_EMMS "TARGET_MMX")
6948 0 : (UNSPECV_FEMMS "TARGET_3DNOW")])
6949 0 :
6950 0 : (define_int_attr emms
6951 15 : [(UNSPECV_EMMS "emms")
6952 15 : (UNSPECV_FEMMS "femms")])
6953 0 :
6954 94546 : (define_expand "mmx_<emms>"
6955 94546 : [(parallel
6956 94546 : [(unspec_volatile [(const_int 0)] EMMS)
6957 94546 : (clobber (reg:XF ST0_REG))
6958 1848679917 : (clobber (reg:XF ST1_REG))
6959 : (clobber (reg:XF ST2_REG))
6960 : (clobber (reg:XF ST3_REG))
6961 : (clobber (reg:XF ST4_REG))
6962 1848679917 : (clobber (reg:XF ST5_REG))
6963 1848679917 : (clobber (reg:XF ST6_REG))
6964 1848679917 : (clobber (reg:XF ST7_REG))
6965 1848679917 : (clobber (reg:DI MM0_REG))
6966 1848679917 : (clobber (reg:DI MM1_REG))
6967 1848679917 : (clobber (reg:DI MM2_REG))
6968 1848679917 : (clobber (reg:DI MM3_REG))
6969 1848679917 : (clobber (reg:DI MM4_REG))
6970 : (clobber (reg:DI MM5_REG))
6971 1564131867 : (clobber (reg:DI MM6_REG))
6972 1564131867 : (clobber (reg:DI MM7_REG))])]
6973 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
6974 139464006 : {
6975 139464006 : if (!TARGET_MMX)
6976 : {
6977 128206457 : emit_insn (gen_nop ());
6978 128206457 : DONE;
6979 128206456 : }
6980 : })
6981 :
6982 : (define_insn "*mmx_<emms>"
6983 8959901 : [(unspec_volatile [(const_int 0)] EMMS)
6984 8960020 : (clobber (reg:XF ST0_REG))
6985 8959901 : (clobber (reg:XF ST1_REG))
6986 : (clobber (reg:XF ST2_REG))
6987 : (clobber (reg:XF ST3_REG))
6988 : (clobber (reg:XF ST4_REG))
6989 619117 : (clobber (reg:XF ST5_REG))
6990 619117 : (clobber (reg:XF ST6_REG))
6991 619117 : (clobber (reg:XF ST7_REG))
6992 : (clobber (reg:DI MM0_REG))
6993 : (clobber (reg:DI MM1_REG))
6994 119 : (clobber (reg:DI MM2_REG))
6995 1485058 : (clobber (reg:DI MM3_REG))
6996 1485058 : (clobber (reg:DI MM4_REG))
6997 1485058 : (clobber (reg:DI MM5_REG))
6998 : (clobber (reg:DI MM6_REG))
6999 71610 : (clobber (reg:DI MM7_REG))]
7000 : ""
7001 147050 : "<emms>"
7002 147050 : [(set_attr "type" "mmx")
7003 147050 : (set_attr "modrm" "0")
7004 : (set_attr "memory" "none")])
7005 :
7006 : (define_insn "popcount<mode>2"
7007 74420 : [(set (match_operand:VI1_16_32_64 0 "register_operand" "=v")
7008 74420 : (popcount:VI1_16_32_64
7009 : (match_operand:VI1_16_32_64 1 "register_operand" "v")))]
7010 73534 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
7011 73538 : "vpopcntb\t{%1, %0|%0, %1}")
7012 :
7013 50645 : (define_insn "popcount<mode>2"
7014 50669 : [(set (match_operand:VI2_32_64 0 "register_operand" "=v")
7015 50669 : (popcount:VI2_32_64
7016 50657 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
7017 50667 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
7018 50691 : "vpopcntw\t{%1, %0|%0, %1}")
7019 :
7020 50645 : (define_insn "popcountv2si2"
7021 50657 : [(set (match_operand:V2SI 0 "register_operand" "=v")
7022 12 : (popcount:V2SI
7023 50651 : (match_operand:V2SI 1 "register_operand" "v")))]
7024 50661 : "TARGET_AVX512VPOPCNTDQ && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
7025 50668 : "vpopcntd\t{%1, %0|%0, %1}")
7026 50645 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7027 : /* (content generated from coverage data) */
7028 : /* ... */
7029 : /* ... */
7030 : /* ... */
7031 : /* ... */
7032 : /* ... */
7033 : /* ... */
7034 4136438 : /* END: function "_Z8recog_63P7rtx_defP8rtx_insnPi" */
7035 : /* ... */
7036 : /* ... */
7037 : /* ... */
7038 4136438 : /* ... */
7039 4136438 : /* ... */
7040 4136438 : /* ... */
7041 4136438 : /* ... */
7042 4136438 : /* ... */
7043 4136438 : /* ... */
7044 : /* ... */
7045 3582008 : /* ... */
7046 3582008 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7047 3582008 : /* (content generated from coverage data) */
7048 3582008 : /* ... */
7049 3582008 : /* ... */
7050 3582008 : /* ... */
7051 3582008 : /* ... */
7052 3582008 : /* ... */
7053 3582008 : /* ... */
7054 3582008 : /* ... */
7055 3582008 : /* ... */
7056 3582008 : /* ... */
7057 3582008 : /* ... */
7058 3582008 : /* ... */
7059 3582008 : /* ... */
7060 3582008 : /* ... */
7061 : /* ... */
7062 3527218 : /* ... */
7063 3390166 : /* ... */
7064 108574 : /* ... */
7065 3635606 : /* ... */
7066 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7067 2110 : /* (content generated from coverage data) */
7068 2110 : /* ... */
7069 : /* ... */
7070 313 : /* ... */
7071 313 : /* ... */
7072 313 : /* ... */
7073 313 : /* ... */
7074 313 : /* ... */
7075 313 : /* ... */
7076 313 : /* ... */
7077 : /* ... */
7078 40 : /* ... */
7079 40 : /* ... */
7080 40 : /* ... */
7081 : /* ... */
7082 40 : /* ... */
7083 : /* ... */
7084 2 : /* ... */
7085 2 : /* ... */
7086 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7087 : /* (content generated from coverage data) */
7088 : /* ... */
7089 : /* ... */
7090 : /* ... */
7091 : /* ... */
7092 : /* ... */
7093 : /* ... */
7094 : /* ... */
7095 : /* ... */
7096 : /* ... */
7097 : /* ... */
7098 : /* ... */
7099 : /* ... */
7100 : /* ... */
7101 : /* ... */
7102 : /* ... */
7103 : /* ... */
7104 : /* ... */
7105 : /* ... */
7106 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7107 : /* (content generated from coverage data) */
7108 : /* ... */
7109 : /* ... */
7110 : /* ... */
7111 : /* ... */
7112 : /* ... */
7113 : /* ... */
7114 : /* ... */
7115 : /* ... */
7116 : /* ... */
7117 : /* ... */
7118 : /* ... */
7119 : /* ... */
7120 : /* ... */
7121 : /* ... */
7122 : /* ... */
7123 : /* ... */
7124 : /* ... */
7125 : /* ... */
7126 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7127 : /* (content generated from coverage data) */
7128 : /* ... */
7129 : /* ... */
7130 : /* ... */
7131 : /* ... */
7132 : /* ... */
7133 : /* ... */
7134 : /* ... */
7135 : /* ... */
7136 : /* ... */
7137 : /* ... */
7138 : /* ... */
7139 : /* ... */
7140 : /* ... */
7141 : /* ... */
7142 : /* ... */
7143 : /* ... */
7144 : /* ... */
7145 : /* ... */
7146 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7147 : /* (content generated from coverage data) */
7148 : /* ... */
7149 : /* ... */
7150 : /* ... */
7151 : /* ... */
7152 : /* ... */
7153 : /* ... */
7154 : /* ... */
7155 : /* ... */
7156 : /* ... */
7157 : /* ... */
7158 : /* ... */
7159 : /* ... */
7160 : /* ... */
7161 : /* ... */
7162 : /* ... */
7163 : /* ... */
7164 : /* ... */
7165 : /* ... */
7166 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7167 : /* (content generated from coverage data) */
7168 : /* ... */
7169 : /* ... */
7170 : /* ... */
7171 : /* ... */
7172 : /* ... */
7173 : /* ... */
7174 : /* ... */
7175 : /* ... */
7176 : /* ... */
7177 : /* ... */
7178 : /* ... */
7179 : /* ... */
7180 : /* ... */
7181 : /* ... */
7182 : /* ... */
7183 : /* ... */
7184 : /* ... */
7185 : /* ... */
7186 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7187 : /* (content generated from coverage data) */
7188 : /* ... */
7189 : /* ... */
7190 : /* ... */
7191 : /* ... */
7192 : /* ... */
7193 : /* ... */
7194 : /* ... */
7195 : /* ... */
7196 : /* ... */
7197 : /* ... */
7198 : /* ... */
7199 : /* ... */
7200 : /* ... */
7201 : /* ... */
7202 : /* ... */
7203 : /* ... */
7204 : /* ... */
7205 : /* ... */
7206 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7207 : /* (content generated from coverage data) */
7208 : /* ... */
7209 : /* ... */
7210 : /* ... */
7211 : /* ... */
7212 : /* ... */
7213 : /* ... */
7214 : /* ... */
7215 : /* ... */
7216 : /* ... */
7217 : /* ... */
7218 : /* ... */
7219 : /* ... */
7220 : /* ... */
7221 : /* ... */
7222 : /* ... */
7223 : /* ... */
7224 : /* ... */
7225 : /* ... */
7226 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7227 : /* (content generated from coverage data) */
7228 : /* ... */
7229 : /* ... */
7230 : /* ... */
7231 : /* ... */
7232 : /* ... */
7233 : /* ... */
7234 : /* ... */
7235 : /* ... */
7236 : /* ... */
7237 : /* ... */
7238 : /* ... */
7239 : /* ... */
7240 : /* ... */
7241 : /* ... */
7242 : /* ... */
7243 : /* ... */
7244 : /* ... */
7245 : /* ... */
7246 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7247 : /* (content generated from coverage data) */
7248 : /* ... */
7249 : /* ... */
7250 : /* ... */
7251 : /* ... */
7252 : /* ... */
7253 : /* ... */
7254 : /* ... */
7255 : /* ... */
7256 : /* ... */
7257 : /* ... */
7258 : /* ... */
7259 : /* ... */
7260 : /* ... */
7261 : /* ... */
7262 : /* ... */
7263 : /* ... */
7264 : /* ... */
7265 : /* ... */
7266 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7267 : /* (content generated from coverage data) */
7268 : /* ... */
7269 : /* ... */
7270 : /* ... */
7271 : /* ... */
7272 : /* ... */
7273 : /* ... */
7274 : /* ... */
7275 : /* ... */
7276 : /* ... */
7277 : /* ... */
7278 : /* ... */
7279 : /* ... */
7280 : /* ... */
7281 : /* ... */
7282 : /* ... */
7283 : /* ... */
7284 : /* ... */
7285 : /* ... */
7286 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7287 : /* (content generated from coverage data) */
7288 : /* ... */
7289 : /* ... */
7290 : /* ... */
7291 : /* ... */
7292 : /* ... */
7293 : /* ... */
7294 : /* ... */
7295 : /* ... */
7296 : /* ... */
7297 : /* ... */
7298 : /* ... */
7299 : /* ... */
7300 : /* ... */
7301 : /* ... */
7302 : /* ... */
7303 : /* ... */
7304 : /* ... */
7305 : /* ... */
7306 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7307 : /* (content generated from coverage data) */
7308 : /* ... */
7309 : /* ... */
7310 : /* ... */
7311 : /* ... */
7312 : /* ... */
7313 : /* ... */
7314 : /* ... */
7315 : /* ... */
7316 : /* ... */
7317 : /* ... */
7318 : /* ... */
7319 : /* ... */
7320 : /* ... */
7321 : /* ... */
7322 : /* ... */
7323 : /* ... */
7324 : /* ... */
7325 : /* ... */
7326 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7327 : /* (content generated from coverage data) */
7328 : /* ... */
7329 : /* ... */
7330 : /* ... */
7331 : /* ... */
7332 : /* ... */
7333 : /* ... */
7334 : /* ... */
7335 : /* ... */
7336 : /* ... */
7337 : /* ... */
7338 : /* ... */
7339 : /* ... */
7340 : /* ... */
7341 : /* ... */
7342 : /* ... */
7343 : /* ... */
7344 : /* ... */
7345 : /* ... */
7346 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7347 : /* (content generated from coverage data) */
7348 : /* ... */
7349 : /* ... */
7350 : /* ... */
7351 : /* ... */
7352 : /* ... */
7353 : /* ... */
7354 : /* ... */
7355 : /* ... */
7356 : /* ... */
7357 : /* ... */
7358 : /* ... */
7359 : /* ... */
7360 : /* ... */
7361 : /* ... */
7362 : /* ... */
7363 : /* ... */
7364 : /* ... */
7365 : /* ... */
7366 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7367 : /* (content generated from coverage data) */
7368 : /* ... */
7369 : /* ... */
7370 : /* ... */
7371 : /* ... */
7372 : /* ... */
7373 : /* ... */
7374 : /* ... */
7375 : /* ... */
7376 : /* ... */
7377 : /* ... */
7378 : /* ... */
7379 : /* ... */
7380 : /* ... */
7381 : /* ... */
7382 : /* ... */
7383 : /* ... */
7384 : /* ... */
7385 : /* ... */
7386 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7387 : /* (content generated from coverage data) */
7388 : /* ... */
7389 : /* ... */
7390 : /* ... */
7391 : /* ... */
7392 : /* ... */
7393 : /* ... */
7394 : /* ... */
7395 : /* ... */
7396 : /* ... */
7397 : /* ... */
7398 : /* ... */
7399 : /* ... */
7400 : /* ... */
7401 : /* ... */
7402 : /* ... */
7403 : /* ... */
7404 : /* ... */
7405 : /* ... */
7406 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7407 : /* (content generated from coverage data) */
7408 : /* ... */
7409 : /* ... */
7410 : /* ... */
7411 : /* ... */
7412 : /* ... */
7413 : /* ... */
7414 : /* ... */
7415 : /* ... */
7416 : /* ... */
7417 : /* ... */
7418 : /* ... */
7419 : /* ... */
7420 : /* ... */
7421 : /* ... */
7422 : /* ... */
7423 : /* ... */
7424 : /* ... */
7425 : /* ... */
7426 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7427 : /* (content generated from coverage data) */
7428 : /* ... */
7429 : /* ... */
7430 : /* ... */
7431 : /* ... */
7432 : /* ... */
7433 : /* ... */
7434 : /* ... */
7435 : /* ... */
7436 : /* ... */
7437 : /* ... */
7438 : /* ... */
7439 : /* ... */
7440 : /* ... */
7441 : /* ... */
7442 : /* ... */
7443 : /* ... */
7444 : /* ... */
7445 : /* ... */
7446 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7447 : /* (content generated from coverage data) */
7448 : /* ... */
7449 : /* ... */
7450 : /* ... */
7451 : /* ... */
7452 : /* ... */
7453 : /* ... */
7454 : /* ... */
7455 : /* ... */
7456 : /* ... */
7457 : /* ... */
7458 : /* ... */
7459 : /* ... */
7460 : /* ... */
7461 : /* ... */
7462 : /* ... */
7463 : /* ... */
7464 : /* ... */
7465 : /* ... */
7466 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7467 : /* (content generated from coverage data) */
7468 : /* ... */
7469 : /* ... */
7470 : /* ... */
7471 : /* ... */
7472 : /* ... */
7473 : /* ... */
7474 : /* ... */
7475 : /* ... */
7476 : /* ... */
7477 : /* ... */
7478 : /* ... */
7479 : /* ... */
7480 : /* ... */
7481 : /* ... */
7482 : /* ... */
7483 : /* ... */
7484 : /* ... */
7485 : /* ... */
7486 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7487 : /* (content generated from coverage data) */
7488 : /* ... */
7489 : /* ... */
7490 : /* ... */
7491 : /* ... */
7492 : /* ... */
7493 : /* ... */
7494 : /* ... */
7495 : /* ... */
7496 : /* ... */
7497 : /* ... */
7498 : /* ... */
7499 : /* ... */
7500 : /* ... */
7501 : /* ... */
7502 : /* ... */
7503 : /* ... */
7504 : /* ... */
7505 : /* ... */
7506 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7507 : /* (content generated from coverage data) */
7508 : /* ... */
7509 : /* ... */
7510 : /* ... */
7511 : /* ... */
7512 : /* ... */
7513 : /* ... */
7514 : /* ... */
7515 : /* ... */
7516 : /* ... */
7517 : /* ... */
7518 : /* ... */
7519 : /* ... */
7520 : /* ... */
7521 : /* ... */
7522 : /* ... */
7523 : /* ... */
7524 : /* ... */
7525 : /* ... */
7526 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7527 : /* (content generated from coverage data) */
7528 : /* ... */
7529 : /* ... */
7530 : /* ... */
7531 : /* ... */
7532 : /* ... */
7533 : /* ... */
7534 : /* ... */
7535 : /* ... */
7536 : /* ... */
7537 : /* ... */
7538 : /* ... */
7539 : /* ... */
7540 : /* ... */
7541 : /* ... */
7542 : /* ... */
7543 : /* ... */
7544 : /* ... */
7545 : /* ... */
7546 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7547 : /* (content generated from coverage data) */
7548 : /* ... */
7549 : /* ... */
7550 : /* ... */
7551 : /* ... */
7552 : /* ... */
7553 : /* ... */
7554 : /* ... */
7555 : /* ... */
7556 : /* ... */
7557 : /* ... */
7558 : /* ... */
7559 : /* ... */
7560 : /* ... */
7561 : /* ... */
7562 : /* ... */
7563 : /* ... */
7564 : /* ... */
7565 : /* ... */
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7736 : /* ... */
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7739 : /* ... */
7740 : /* ... */
7741 : /* ... */
7742 : /* ... */
7743 : /* ... */
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7748 : /* ... */
7749 : /* ... */
7750 : /* ... */
7751 : /* ... */
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7754 : /* ... */
7755 : /* ... */
7756 : /* ... */
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7760 : /* ... */
7761 : /* ... */
7762 : /* ... */
7763 : /* ... */
7764 : /* ... */
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7766 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
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7770 : /* ... */
7771 : /* ... */
7772 : /* ... */
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7774 : /* ... */
7775 : /* ... */
7776 : /* ... */
7777 : /* ... */
7778 : /* ... */
7779 : /* ... */
7780 0 : /* ... */
7781 0 : /* ... */
7782 0 : /* ... */
7783 0 : /* ... */
7784 : /* ... */
7785 0 : /* ... */
7786 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7787 : /* (content generated from coverage data) */
7788 : /* ... */
7789 : /* ... */
7790 : /* ... */
7791 : /* ... */
7792 : /* ... */
7793 : /* ... */
7794 : /* ... */
7795 : /* ... */
7796 : /* ... */
7797 : /* ... */
7798 : /* ... */
7799 : /* ... */
7800 : /* ... */
7801 454904756 : /* END: function "_Z19get_attr_prefix_rexP8rtx_insn" */
7802 : /* ... */
7803 454904756 : /* ... */
7804 : /* ... */
7805 454904756 : /* ... */
7806 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7807 862741 : /* (content generated from coverage data) */
7808 862741 : /* ... */
7809 862741 : /* ... */
7810 862741 : /* ... */
7811 862741 : /* ... */
7812 : /* ... */
7813 : /* ... */
7814 : /* ... */
7815 : /* ... */
7816 : /* ... */
7817 797058 : /* ... */
|
