Line data Source code
1 : ;; GCC machine description for MMX and 3dNOW! instructions
2 : ;; Copyright (C) 2005-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; The MMX and 3dNOW! patterns are in the same file because they use
21 : ;; the same register file, and 3dNOW! adds a number of extensions to
22 : ;; the base integer MMX isa.
23 :
24 : ;; Note! Except for the basic move instructions, *all* of these
25 : ;; patterns are outside the normal optabs namespace. This is because
26 : ;; use of these registers requires the insertion of emms or femms
27 : ;; instructions to return to normal fpu mode. The compiler doesn't
28 : ;; know how to do that itself, which means it's up to the user. Which
29 : ;; means that we should never use any of these patterns except at the
30 : ;; direction of the user via a builtin.
31 :
32 : (define_c_enum "unspec" [
33 : UNSPEC_3DNOW
34 :
35 : UNSPEC_MOVNTQ
36 : UNSPEC_PFRCP
37 : UNSPEC_PFRCPIT1
38 : UNSPEC_PFRCPIT2
39 : UNSPEC_PFRSQRT
40 : UNSPEC_PFRSQIT1
41 : ])
42 :
43 : (define_c_enum "unspecv" [
44 : UNSPECV_EMMS
45 : UNSPECV_FEMMS
46 : ])
47 :
48 : ;; 8 byte integral modes handled by MMX (and by extension, SSE)
49 : (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
50 284 : (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")])
51 56 :
52 : ;; All 8-byte vector modes handled by MMX
53 : (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF V4HF V4BF])
54 14680 : (define_mode_iterator MMXMODE124 [V8QI V4HI V2SI V2SF])
55 14680 :
56 14680 : ;; Mix-n-match
57 : (define_mode_iterator MMXMODE12 [V8QI V4HI])
58 14680 : (define_mode_iterator MMXMODE14 [V8QI V2SI])
59 : (define_mode_iterator MMXMODE24 [V4HI V2SI])
60 : (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
61 :
62 : ;; All 4-byte integer/float16 vector modes
63 : (define_mode_iterator V_32 [V4QI V2HI V1SI V2HF V2BF])
64 :
65 : (define_mode_iterator V2FI_32 [V2HF V2BF V2HI])
66 : (define_mode_iterator V4FI_64 [V4HF V4BF V4HI])
67 : (define_mode_iterator V4F_64 [V4HF V4BF])
68 : (define_mode_iterator V2F_32 [V2HF V2BF])
69 : ;; 4-byte integer vector modes
70 : (define_mode_iterator VI_32 [V4QI V2HI])
71 :
72 : ;; 8-byte and 4-byte HImode vector modes
73 110 : (define_mode_iterator VI2_32_64 [(V4HI "TARGET_MMX_WITH_SSE") V2HI])
74 7 :
75 82 : ;; 8-byte, 4-byte and 2-byte QImode vector modes
76 5 : (define_mode_iterator VI1_16_32_64 [(V8QI "TARGET_MMX_WITH_SSE") V4QI V2QI])
77 23 :
78 12 : ;; 4-byte and 2-byte integer vector modes
79 22 : (define_mode_iterator VI_16_32 [V4QI V2QI V2HI])
80 22 :
81 45 : ;; 4-byte and 2-byte QImode vector modes
82 6 : (define_mode_iterator VI1_16_32 [V4QI V2QI])
83 6 :
84 17 : ;; All 2-byte, 4-byte and 8-byte vector modes.
85 : (define_mode_iterator V_16_32_64
86 : [V2QI V4QI V2HI V1SI V2HF V2BF
87 1473 : (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT")
88 15 : (V4HF "TARGET_64BIT") (V4BF "TARGET_64BIT")
89 51503 : (V2SI "TARGET_64BIT") (V2SF "TARGET_64BIT")
90 161 : (V1DI "TARGET_64BIT")])
91 31729200 :
92 32431129 : ;; V2S* modes
93 50305393 : (define_mode_iterator V2FI [V2SF V2SI])
94 77832237 :
95 59198109 : (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI])
96 37312721 :
97 13893271 : (define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI])
98 :
99 : (define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI])
100 :
101 : ;; Mapping from integer vector mode to mnemonic suffix
102 : (define_mode_attr mmxvecsize
103 : [(V8QI "b") (V4QI "b") (V2QI "b")
104 : (V4HI "w") (V2HI "w") (V2SI "d") (V1DI "q")])
105 :
106 : ;; Mapping to same size integral mode.
107 : (define_mode_attr mmxinsnmode
108 : [(V8QI "DI") (V4QI "SI") (V2QI "HI")
109 : (V4HI "DI") (V2HI "SI")
110 : (V2SI "DI")
111 : (V1DI "DI") (V1SI "SI")
112 : (V4HF "DI") (V2HF "SI")
113 : (V4BF "DI") (V2BF "SI")
114 : (V2SF "DI")])
115 :
116 : (define_mode_attr mmxdoublemode
117 : [(V8QI "V8HI") (V4HI "V4SI")])
118 :
119 : (define_mode_attr mmxhalfmode
120 : [(V4HI "V4QI") (V2HI "V2QI")])
121 :
122 : (define_mode_attr mmxbytemode
123 : [(V4HI "V8QI") (V2HI "V4QI")])
124 :
125 : (define_mode_attr mmxhalfmodelower
126 : [(V4HI "v4qi") (V2HI "v2qi")])
127 :
128 : ;; Mapping of vector float modes to an integer mode of the same size
129 : (define_mode_attr mmxintvecmode
130 : [(V2SF "V2SI") (V2SI "V2SI") (V4HI "V4HI") (V8QI "V8QI")
131 : (V4HF "V4HI") (V2HF "V2HI") (V4BF "V4HI") (V2BF "V2HI")])
132 :
133 : (define_mode_attr mmxintvecmodelower
134 : [(V2SF "v2si") (V2SI "v2si") (V4HI "v4hi") (V8QI "v8qi")
135 : (V4HF "v4hi") (V2HF "v2hi")])
136 :
137 : ;; Mapping of vector modes to a vector mode of double size
138 : (define_mode_attr mmxdoublevecmode
139 : [(V2SF "V4SF") (V2SI "V4SI") (V4HF "V8HF") (V4HI "V8HI")
140 : (V2HI "V4HI") (V2HF "V4HF") (V2BF "V4BF")])
141 :
142 : ;; Mapping of vector modes back to the scalar modes
143 : (define_mode_attr mmxscalarmode
144 : [(V2SI "SI") (V2SF "SF")
145 : (V4HF "HF") (V4BF "BF")
146 : (V2HF "HF") (V2BF "BF")
147 : (V4HI "HI") (V2HI "HI")
148 : (V8QI "QI")])
149 :
150 : (define_mode_attr mmxscalarmodelower
151 : [(V2SI "si") (V2SF "sf")
152 : (V4HF "hf") (V4BF "bf")
153 : (V2HF "hf") (V2BF "bf")
154 : (V4HI "hi") (V2HI "hi")
155 : (V8QI "qi")])
156 :
157 : (define_mode_attr mmxscalarsize
158 : [(V1DI "64")
159 : (V2SI "32") (V2SF "32")
160 : (V4HF "16") (V4BF "16")
161 : (V2HF "16") (V2BF "16")
162 : (V4HI "16") (V2HI "16")
163 : (V8QI "8")])
164 :
165 : (define_mode_attr Yv_Yw
166 : [(V8QI "Yw") (V4HI "Yw") (V2SI "Yv") (V1DI "Yv") (V2SF "Yv")])
167 :
168 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
169 : ;;
170 : ;; Move patterns
171 : ;;
172 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
173 :
174 : ;; All of these patterns are enabled for MMX as well as 3dNOW.
175 : ;; This is essential for maintaining stable calling conventions.
176 :
177 : (define_expand "mov<mode>"
178 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
179 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"))]
180 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
181 494977 : {
182 494977 : ix86_expand_vector_move (<MODE>mode, operands);
183 494977 : DONE;
184 : })
185 :
186 : (define_insn "*mov<mode>_internal"
187 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand"
188 : "=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!y,v,v,v,m,r,v,!y,*x")
189 : (match_operand:MMXMODE 1 "nonimm_or_0_operand"
190 : "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))]
191 72804615 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
192 72470491 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))
193 72182189 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
194 226637 : {
195 28224175 : switch (get_attr_type (insn))
196 819881 : {
197 27997922 : case TYPE_MULTI:
198 : return "#";
199 384 :
200 56934 : case TYPE_IMOV:
201 57318 : if (get_attr_mode (insn) == MODE_SI)
202 : return "mov{l}\t{%1, %k0|%k0, %1}";
203 : else
204 56856 : return "mov{q}\t{%1, %0|%0, %1}";
205 :
206 0 : case TYPE_MMX:
207 0 : return "pxor\t%0, %0";
208 :
209 549 : case TYPE_MMXMOV:
210 : /* Handle broken assemblers that require movd instead of movq. */
211 549 : if (!HAVE_AS_IX86_INTERUNIT_MOVQ
212 : && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1])))
213 : return "movd\t{%1, %0|%0, %1}";
214 549 : return "movq\t{%1, %0|%0, %1}";
215 :
216 147 : case TYPE_SSECVT:
217 147 : if (SSE_REG_P (operands[0]))
218 : return "movq2dq\t{%1, %0|%0, %1}";
219 : else
220 41 : return "movdq2q\t{%1, %0|%0, %1}";
221 :
222 1857 : case TYPE_SSELOG1:
223 1857 : return standard_sse_constant_opcode (insn, operands);
224 :
225 167150 : case TYPE_SSEMOV:
226 167150 : return ix86_output_ssemov (insn, operands);
227 :
228 0 : default:
229 0 : gcc_unreachable ();
230 : }
231 : }
232 : [(set (attr "isa")
233 : (cond [(eq_attr "alternative" "0,1")
234 : (const_string "nox64")
235 229673 : (eq_attr "alternative" "2,3,4,9,10")
236 : (const_string "x64")
237 : (eq_attr "alternative" "15,16")
238 : (const_string "x64_sse2")
239 : (eq_attr "alternative" "17,18")
240 : (const_string "sse2")
241 : ]
242 : (const_string "*")))
243 : (set (attr "type")
244 : (cond [(eq_attr "alternative" "0,1")
245 : (const_string "multi")
246 : (eq_attr "alternative" "2,3,4")
247 : (const_string "imov")
248 : (eq_attr "alternative" "5")
249 : (const_string "mmx")
250 : (eq_attr "alternative" "6,7,8,9,10")
251 : (const_string "mmxmov")
252 : (eq_attr "alternative" "11")
253 : (const_string "sselog1")
254 : (eq_attr "alternative" "17,18")
255 : (const_string "ssecvt")
256 : ]
257 : (const_string "ssemov")))
258 : (set (attr "prefix_rex")
259 : (if_then_else (eq_attr "alternative" "9,10,15,16")
260 : (const_string "1")
261 : (const_string "*")))
262 : (set (attr "prefix")
263 : (if_then_else (eq_attr "type" "sselog1,ssemov")
264 : (const_string "maybe_vex")
265 : (const_string "orig")))
266 : (set (attr "prefix_data16")
267 : (if_then_else
268 : (and (eq_attr "type" "ssemov") (eq_attr "mode" "DI"))
269 : (const_string "1")
270 : (const_string "*")))
271 : (set (attr "mode")
272 : (cond [(eq_attr "alternative" "2")
273 : (const_string "SI")
274 : (eq_attr "alternative" "11,12")
275 : (cond [(match_test "<MODE>mode == V2SFmode
276 : || <MODE>mode == V4HFmode
277 : || <MODE>mode == V4BFmode")
278 : (const_string "V4SF")
279 : (ior (not (match_test "TARGET_SSE2"))
280 : (match_test "optimize_function_for_size_p (cfun)"))
281 46046 : (const_string "V4SF")
282 : ]
283 : (const_string "TI"))
284 :
285 : (and (eq_attr "alternative" "13")
286 1810024 : (ior (ior (and (match_test "<MODE>mode == V2SFmode")
287 : (not (match_test "TARGET_MMX_WITH_SSE")))
288 : (not (match_test "TARGET_SSE2")))
289 : (match_test "<MODE>mode == V4HFmode
290 : || <MODE>mode == V4BFmode")))
291 : (const_string "V2SF")
292 :
293 : (and (eq_attr "alternative" "14")
294 5750913 : (ior (ior (match_test "<MODE>mode == V2SFmode")
295 : (not (match_test "TARGET_SSE2")))
296 : (match_test "<MODE>mode == V4HFmode
297 : || <MODE>mode == V4BFmode")))
298 : (const_string "V2SF")
299 6128891 : ]
300 6128891 : (const_string "DI")))
301 6128891 : (set (attr "preferred_for_speed")
302 : (cond [(eq_attr "alternative" "9,15")
303 18236 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
304 : (eq_attr "alternative" "10,16")
305 5991113 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
306 : ]
307 415321 : (symbol_ref "true")))])
308 :
309 : (define_split
310 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
311 : (match_operand:MMXMODE 1 "nonimmediate_gr_operand"))]
312 184264 : "!TARGET_64BIT && reload_completed"
313 66111 : [(const_int 0)]
314 773859 : "ix86_split_long_move (operands); DONE;")
315 20705 :
316 707748 : (define_split
317 : [(set (match_operand:MMXMODE 0 "nonimmediate_gr_operand")
318 : (match_operand:MMXMODE 1 "const0_operand"))]
319 33945 : "!TARGET_64BIT && reload_completed"
320 17272 : [(const_int 0)]
321 64327 : "ix86_split_long_move (operands); DONE;")
322 41451 :
323 47055 : (define_expand "movmisalign<mode>"
324 : [(set (match_operand:MMXMODE 0 "nonimmediate_operand")
325 5401 : (match_operand:MMXMODE 1 "nonimmediate_operand"))]
326 17171 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
327 129574 : {
328 136156 : ix86_expand_vector_move (<MODE>mode, operands);
329 124173 : DONE;
330 17171 : })
331 :
332 146895 : (define_expand "mov<mode>"
333 : [(set (match_operand:V_32 0 "nonimmediate_operand")
334 146895 : (match_operand:V_32 1 "nonimm_or_0_operand"))]
335 146895 : ""
336 162510 : {
337 43738 : ix86_expand_vector_move (<MODE>mode, operands);
338 43738 : DONE;
339 : })
340 :
341 : (define_insn "*mov<mode>_internal"
342 15444 : [(set (match_operand:V_32 0 "nonimmediate_operand"
343 0 : "=r ,m ,v,v,v,m,r,v")
344 15444 : (match_operand:V_32 1 "nonimm_or_0_operand"
345 15444 : "rmC,rC,C,v,m,v,v,r"))]
346 10046153 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
347 40513516 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
348 16620 : {
349 18789026 : switch (get_attr_type (insn))
350 3 : {
351 18772406 : case TYPE_IMOV:
352 0 : return "mov{l}\t{%1, %0|%0, %1}";
353 :
354 184 : case TYPE_SSELOG1:
355 184 : return standard_sse_constant_opcode (insn, operands);
356 0 :
357 7391 : case TYPE_SSEMOV:
358 7391 : return ix86_output_ssemov (insn, operands);
359 :
360 0 : default:
361 0 : gcc_unreachable ();
362 : }
363 : }
364 : [(set (attr "isa")
365 : (cond [(eq_attr "alternative" "6,7")
366 : (const_string "sse2")
367 4889 : ]
368 : (const_string "*")))
369 : (set (attr "type")
370 : (cond [(eq_attr "alternative" "2")
371 : (const_string "sselog1")
372 : (eq_attr "alternative" "3,4,5,6,7")
373 : (const_string "ssemov")
374 : ]
375 : (const_string "imov")))
376 : (set (attr "prefix")
377 : (if_then_else (eq_attr "type" "sselog1,ssemov")
378 : (const_string "maybe_vex")
379 : (const_string "orig")))
380 : (set (attr "prefix_data16")
381 : (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
382 : (const_string "1")
383 : (const_string "*")))
384 : (set (attr "mode")
385 : (cond [(eq_attr "alternative" "2,3")
386 : (cond [(match_test "<MODE>mode == V2HFmode
387 131211 : || <MODE>mode == V2BFmode")
388 : (const_string "V4SF")
389 : (match_test "TARGET_AVX")
390 : (const_string "TI")
391 26892 : (ior (not (match_test "TARGET_SSE2"))
392 22063 : (match_test "optimize_function_for_size_p (cfun)"))
393 : (const_string "V4SF")
394 : ]
395 : (const_string "TI"))
396 :
397 : (and (eq_attr "alternative" "4,5")
398 : (ior (match_test "<MODE>mode == V2HFmode
399 : || <MODE>mode == V2BFmode")
400 : (not (match_test "TARGET_SSE2"))))
401 : (const_string "SF")
402 : ]
403 : (const_string "SI")))
404 : (set (attr "preferred_for_speed")
405 : (cond [(eq_attr "alternative" "6")
406 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
407 : (eq_attr "alternative" "7")
408 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
409 : ]
410 : (symbol_ref "true")))])
411 :
412 : ;; For TARGET_64BIT we always round up to 8 bytes.
413 : (define_insn "*push<mode>2_rex64"
414 : [(set (match_operand:V_32 0 "push_operand" "=X,X")
415 : (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))]
416 3 : "TARGET_64BIT"
417 : "@
418 18772403 : push{q}\t%q1
419 18772403 : #"
420 : [(set_attr "type" "push,multi")
421 : (set_attr "mode" "DI")])
422 :
423 59452621 : (define_split
424 59452621 : [(set (match_operand:V_32 0 "push_operand")
425 40773425 : (match_operand:V_32 1 "sse_reg_operand"))]
426 91715555 : "TARGET_64BIT && TARGET_SSE && reload_completed"
427 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
428 : (set (match_dup 0) (match_dup 1))]
429 0 : {
430 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<V_32:MODE>mode)));
431 : /* Preserve memory attributes. */
432 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
433 : })
434 :
435 : (define_expand "movmisalign<mode>"
436 0 : [(set (match_operand:V_32 0 "nonimmediate_operand")
437 : (match_operand:V_32 1 "nonimmediate_operand"))]
438 : ""
439 8522 : {
440 8522 : ix86_expand_vector_move (<MODE>mode, operands);
441 8522 : DONE;
442 : })
443 :
444 : (define_expand "movv2qi"
445 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
446 53158 : (match_operand:V2QI 1 "nonimm_or_0_operand"))]
447 110 : ""
448 97794 : {
449 53268 : ix86_expand_vector_move (V2QImode, operands);
450 53158 : DONE;
451 110 : })
452 :
453 : (define_insn "*movv2qi_internal"
454 : [(set (match_operand:V2QI 0 "nonimmediate_operand"
455 15 : "=r,r,r,m ,v,v,v,jm,m,r,v")
456 : (match_operand:V2QI 1 "nonimm_or_0_operand"
457 15 : "r ,C,m,rC,C,v,m,x,v,v,r"))]
458 8412344 : "!(MEM_P (operands[0]) && MEM_P (operands[1]))
459 8381740 : && ix86_hardreg_mov_ok (operands[0], operands[1])"
460 22063 : {
461 3863390 : switch (get_attr_type (insn))
462 47336 : {
463 3858860 : case TYPE_IMOV:
464 17533 : if (get_attr_mode (insn) == MODE_SI)
465 : return "mov{l}\t{%k1, %k0|%k0, %k1}";
466 0 : else
467 17309 : return "mov{w}\t{%1, %0|%0, %1}";
468 0 :
469 : case TYPE_IMOVX:
470 : /* movzwl is faster than movw on p2 due to partial word stalls,
471 : though not as fast as an aligned movl. */
472 : return "movz{wl|x}\t{%1, %k0|%k0, %1}";
473 :
474 393 : case TYPE_SSELOG1:
475 393 : if (satisfies_constraint_C (operands[1]))
476 46 : return standard_sse_constant_opcode (insn, operands);
477 :
478 347 : if (SSE_REG_P (operands[0]))
479 : return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
480 : else
481 25 : return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
482 :
483 408 : case TYPE_SSEMOV:
484 408 : return ix86_output_ssemov (insn, operands);
485 :
486 0 : default:
487 0 : gcc_unreachable ();
488 : }
489 : }
490 : [(set (attr "isa")
491 : (cond [(eq_attr "alternative" "6,9,10")
492 : (const_string "sse2")
493 0 : (eq_attr "alternative" "7")
494 : (const_string "sse4_noavx")
495 : (eq_attr "alternative" "8")
496 : (const_string "avx")
497 : ]
498 : (const_string "*")))
499 : (set (attr "addr")
500 : (if_then_else (eq_attr "alternative" "7")
501 : (const_string "gpr16")
502 : (const_string "*")))
503 : (set (attr "type")
504 : (cond [(eq_attr "alternative" "6,7,8")
505 : (if_then_else (match_test "TARGET_AVX512FP16")
506 : (const_string "ssemov")
507 : (const_string "sselog1"))
508 : (eq_attr "alternative" "4")
509 : (const_string "sselog1")
510 : (eq_attr "alternative" "5,9,10")
511 : (const_string "ssemov")
512 : (match_test "optimize_function_for_size_p (cfun)")
513 : (const_string "imov")
514 : (and (eq_attr "alternative" "0")
515 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
516 0 : (not (match_test "TARGET_HIMODE_MATH"))))
517 : (const_string "imov")
518 : (and (eq_attr "alternative" "1,2")
519 : (match_operand:V2QI 1 "aligned_operand"))
520 25100103 : (const_string "imov")
521 105800113 : (and (match_test "TARGET_MOVX")
522 : (eq_attr "alternative" "0,2"))
523 : (const_string "imovx")
524 19467439 : ]
525 26395529 : (const_string "imov")))
526 26395529 : (set (attr "prefix")
527 26452529 : (cond [(eq_attr "alternative" "4,5,6,7,8,9,10")
528 : (const_string "maybe_evex")
529 0 : ]
530 131472046 : (const_string "orig")))
531 119654865 : (set (attr "mode")
532 93342396 : (cond [(eq_attr "alternative" "6,7,8")
533 77663 : (if_then_else (match_test "TARGET_AVX512FP16")
534 60255 : (const_string "HI")
535 8370654 : (const_string "TI"))
536 92758577 : (eq_attr "alternative" "9,10")
537 17408 : (if_then_else (match_test "TARGET_AVX512FP16")
538 38069395 : (const_string "HI")
539 38069395 : (const_string "SI"))
540 92742238 : (eq_attr "alternative" "4")
541 38069395 : (cond [(match_test "TARGET_AVX")
542 37850 : (const_string "TI")
543 38069395 : (ior (not (match_test "TARGET_SSE2"))
544 126616272 : (match_test "optimize_function_for_size_p (cfun)"))
545 : (const_string "V4SF")
546 5077947 : ]
547 5077947 : (const_string "TI"))
548 5077947 : (eq_attr "alternative" "5")
549 : (cond [(match_test "TARGET_AVX512FP16")
550 : (const_string "HF")
551 : (match_test "TARGET_AVX")
552 : (const_string "TI")
553 76 : (ior (not (match_test "TARGET_SSE2"))
554 76 : (match_test "optimize_function_for_size_p (cfun)"))
555 76 : (const_string "V4SF")
556 : ]
557 26398599 : (const_string "TI"))
558 26398599 : (eq_attr "type" "imovx")
559 26398599 : (const_string "SI")
560 : (and (eq_attr "alternative" "1,2")
561 : (match_operand:V2QI 1 "aligned_operand"))
562 : (const_string "SI")
563 25822547 : (and (eq_attr "alternative" "0")
564 32811 : (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
565 32811 : (not (match_test "TARGET_HIMODE_MATH"))))
566 32811 : (const_string "SI")
567 25855358 : ]
568 : (const_string "HI")))
569 : (set (attr "preferred_for_speed")
570 : (cond [(eq_attr "alternative" "9")
571 24837969 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
572 : (eq_attr "alternative" "10")
573 : (symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
574 : ]
575 : (symbol_ref "true")))])
576 9742 :
577 9742 : (define_split
578 9742 : [(set (match_operand:V_16_32_64 0 "general_reg_operand")
579 : (match_operand:V_16_32_64 1 "memory_operand"))]
580 26617600 : "reload_completed
581 26625139 : && SYMBOL_REF_P (XEXP (operands[1], 0))
582 26608864 : && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
583 110 : [(set (match_dup 0) (match_dup 1))]
584 61260 : {
585 61260 : rtx op1 = avoid_constant_pool_reference (operands[1]);
586 26406156 :
587 75736 : if (!CONST_VECTOR_P (op1))
588 22865 : FAIL;
589 68542 :
590 24791457 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
591 15208 :
592 15511 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
593 15511 : operands[1] = GEN_INT (val);
594 20994800 : })
595 :
596 : ;; 16-bit, 32-bit and 64-bit constant vector stores. After reload,
597 303 : ;; convert them to immediate integer stores.
598 : (define_insn_and_split "*mov<mode>_imm"
599 : [(set (match_operand:V_16_32_64 0 "memory_operand" "=m")
600 303 : (match_operand:V_16_32_64 1 "x86_64_const_vector_operand" "i"))]
601 42786 : "!TARGET_LCP_STALL || <MODE>mode != V2QImode"
602 : "#"
603 5409453 : "&& reload_completed"
604 5390334 : [(set (match_dup 0) (match_dup 1))]
605 1549007 : {
606 1569265 : rtx op1 = operands[1];
607 109542 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op1, <MODE>mode);
608 4407513 :
609 4402466 : operands[0] = adjust_address (operands[0], <mmxinsnmode>mode, 0);
610 3491438 : operands[1] = GEN_INT (val);
611 4400916 : })
612 9306396 :
613 9306396 : ;; We always round up to UNITS_PER_WORD bytes.
614 10505618 : (define_insn "*pushv2qi2"
615 : [(set (match_operand:V2QI 0 "push_operand" "=X,X")
616 772066 : (match_operand:V2QI 1 "nonmemory_no_elim_operand" "rC,v"))]
617 20953 : ""
618 419429 : "* return TARGET_64BIT ? \"push{q}\t%q1\" : \"push{l}\t%k1\";
619 419429 : #"
620 419429 : [(set_attr "isa" "*,sse4")
621 : (set_attr "type" "push,multi")
622 67093 : (set (attr "mode")
623 46493 : (cond [(eq_attr "alternative" "0")
624 1115543 : (if_then_else (match_test "TARGET_64BIT")
625 1116426 : (const_string "DI")
626 1115123 : (const_string "SI"))
627 46493 : (eq_attr "alternative" "1")
628 45610 : (if_then_else (match_test "TARGET_AVX512FP16")
629 45610 : (const_string "HI")
630 97169 : (const_string "TI"))
631 97169 : ]
632 97169 : (const_string "HI")))])
633 52115 :
634 : (define_split
635 237 : [(set (match_operand:V2QI 0 "push_operand")
636 237 : (match_operand:V2QI 1 "sse_reg_operand"))]
637 0 : "TARGET_SSE4_1 && reload_completed"
638 : [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
639 : (set (match_dup 0) (match_dup 1))]
640 0 : {
641 0 : operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (V2QImode)));
642 0 : /* Preserve memory attributes. */
643 0 : operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
644 0 : })
645 :
646 : (define_expand "movmisalignv2qi"
647 0 : [(set (match_operand:V2QI 0 "nonimmediate_operand")
648 : (match_operand:V2QI 1 "nonimmediate_operand"))]
649 : ""
650 5774 : {
651 5774 : ix86_expand_vector_move (V2QImode, operands);
652 5774 : DONE;
653 77399 : })
654 77399 :
655 77399 : (define_insn "sse_movntq"
656 : [(set (match_operand:DI 0 "memory_operand" "=m,m")
657 3317 : (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
658 0 : UNSPEC_MOVNTQ))]
659 80473 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
660 3317 : && (TARGET_SSE || TARGET_3DNOW_A)"
661 3317 : "@
662 0 : movntq\t{%1, %0|%0, %1}
663 77094 : movnti\t{%1, %0|%0, %1}"
664 1024 : [(set_attr "isa" "*,x64")
665 1024 : (set_attr "mmx_isa" "native,*")
666 26 : (set_attr "type" "mmxmov,ssemov")
667 291 : (set_attr "c86_attr" "movnt")
668 317 : (set_attr "mode" "DI")])
669 0 :
670 26 : (define_expand "movq_<mode>_to_sse"
671 : [(set (match_operand:<mmxdoublevecmode> 0 "register_operand")
672 95090 : (vec_concat:<mmxdoublevecmode>
673 95090 : (match_operand:V24FI 1 "nonimmediate_operand")
674 95090 : (match_dup 2)))]
675 : "TARGET_SSE2"
676 15673 : {
677 15673 : if (<MODE>mode != V2SImode
678 16293 : && !flag_trapping_math)
679 : {
680 10086 : rtx op1 = force_reg (<MODE>mode, operands[1]);
681 10086 : emit_move_insn (operands[0], lowpart_subreg (<mmxdoublevecmode>mode,
682 0 : op1, <MODE>mode));
683 10086 : DONE;
684 : }
685 :
686 5587 : operands[2] = CONST0_RTX (<MODE>mode);
687 : })
688 :
689 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
690 : ;;
691 1044617 : ;; Parallel single-precision floating point arithmetic
692 1039030 : ;;
693 1039030 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
694 1039030 :
695 5587 : (define_expand "<code>v2sf2"
696 : [(set (match_operand:V2SF 0 "register_operand")
697 : (absneg:V2SF
698 993022 : (match_operand:V2SF 1 "register_operand")))]
699 : "TARGET_MMX_WITH_SSE"
700 432 : "ix86_expand_fp_absneg_operator (<CODE>, V2SFmode, operands); DONE;")
701 :
702 993418 : (define_insn_and_split "*mmx_<code>v2sf2"
703 396 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
704 367 : (absneg:V2SF
705 : (match_operand:V2SF 1 "register_operand" "0,x,x")))
706 993022 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
707 405 : "TARGET_MMX_WITH_SSE"
708 29 : "#"
709 72 : "&& reload_completed"
710 : [(set (match_dup 0)
711 42 : (<absneg_op>:V2SF (match_dup 1) (match_dup 2)))]
712 2007 : {
713 62 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
714 1972 : std::swap (operands[1], operands[2]);
715 7009 : }
716 7009 : [(set_attr "isa" "noavx,noavx,avx")])
717 5050 :
718 5064 : (define_insn_and_split "*mmx_nabsv2sf2"
719 5028 : [(set (match_operand:V2SF 0 "register_operand" "=x,x,x")
720 : (neg:V2SF
721 : (abs:V2SF
722 36 : (match_operand:V2SF 1 "register_operand" "0,x,x"))))
723 : (use (match_operand:V2SF 2 "nonimmediate_operand" "x,0,x"))]
724 0 : "TARGET_MMX_WITH_SSE"
725 : "#"
726 0 : "&& reload_completed"
727 152 : [(set (match_dup 0)
728 2605 : (ior:V2SF (match_dup 1) (match_dup 2)))]
729 2757 : {
730 2757 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
731 2757 : std::swap (operands[1], operands[2]);
732 2605 : }
733 2605 : [(set_attr "isa" "noavx,noavx,avx")])
734 2605 :
735 2605 : (define_expand "<insn>v2sf3"
736 2605 : [(set (match_operand:V2SF 0 "register_operand")
737 2605 : (plusminusmult:V2SF
738 : (match_operand:V2SF 1 "nonimmediate_operand")
739 0 : (match_operand:V2SF 2 "nonimmediate_operand")))]
740 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
741 5610 : {
742 5610 : rtx op2 = gen_reg_rtx (V4SFmode);
743 5610 : rtx op1 = gen_reg_rtx (V4SFmode);
744 5669 : rtx op0 = gen_reg_rtx (V4SFmode);
745 :
746 6797 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
747 6797 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
748 1187 :
749 5610 : emit_insn (gen_<insn>v4sf3 (op0, op1, op2));
750 :
751 5610 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
752 6721 : DONE;
753 : })
754 :
755 : (define_expand "mmx_addv2sf3"
756 1111 : [(parallel
757 : [(set (match_operand:V2SF 0 "register_operand")
758 : (plus:V2SF
759 : (match_operand:V2SF 1 "nonimmediate_operand")
760 1111 : (match_operand:V2SF 2 "nonimmediate_operand")))
761 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
762 : "TARGET_3DNOW"
763 18 : "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
764 :
765 : (define_insn "*mmx_addv2sf3"
766 42 : [(set (match_operand:V2SF 0 "register_operand" "=y")
767 18 : (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
768 42 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
769 163989 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
770 164061 : "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
771 163960 : "pfadd\t{%2, %0|%0, %2}"
772 163965 : [(set_attr "type" "mmxadd")
773 : (set_attr "prefix_extra" "1")
774 296 : (set_attr "mode" "V2SF")])
775 296 :
776 : (define_expand "mmx_subv2sf3"
777 74 : [(parallel
778 103 : [(set (match_operand:V2SF 0 "register_operand")
779 74 : (minus:V2SF (match_operand:V2SF 1 "register_operand")
780 75 : (match_operand:V2SF 2 "nonimmediate_operand")))
781 209136 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
782 209211 : "TARGET_3DNOW")
783 209151 :
784 : (define_expand "mmx_subrv2sf3"
785 15 : [(parallel
786 15 : [(set (match_operand:V2SF 0 "register_operand")
787 15 : (minus:V2SF (match_operand:V2SF 2 "register_operand")
788 : (match_operand:V2SF 1 "nonimmediate_operand")))
789 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
790 : "TARGET_3DNOW")
791 :
792 722178 : (define_insn "*mmx_subv2sf3"
793 722178 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
794 722178 : (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
795 : (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))
796 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
797 0 : "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
798 97035 : "@
799 : pfsub\t{%2, %0|%0, %2}
800 : pfsubr\t{%1, %0|%0, %1}"
801 : [(set_attr "type" "mmxadd")
802 54186 : (set_attr "prefix_extra" "1")
803 : (set_attr "mode" "V2SF")])
804 :
805 53 : (define_expand "mmx_mulv2sf3"
806 53 : [(parallel
807 53 : [(set (match_operand:V2SF 0 "register_operand")
808 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
809 : (match_operand:V2SF 2 "nonimmediate_operand")))
810 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
811 30913 : "TARGET_3DNOW"
812 30875 : "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
813 30904 :
814 44 : (define_insn "*mmx_mulv2sf3"
815 : [(set (match_operand:V2SF 0 "register_operand" "=y")
816 15 : (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
817 25949 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
818 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
819 78 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
820 9 : "pfmul\t{%2, %0|%0, %2}"
821 25964 : [(set_attr "type" "mmxmul")
822 : (set_attr "prefix_extra" "1")
823 : (set_attr "mode" "V2SF")])
824 :
825 : (define_expand "divv2sf3"
826 : [(set (match_operand:V2SF 0 "register_operand")
827 367916 : (div:V2SF (match_operand:V2SF 1 "register_operand")
828 367915 : (match_operand:V2SF 2 "register_operand")))]
829 1 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
830 545497 : {
831 644252 : rtx op2 = gen_reg_rtx (V4SFmode);
832 644251 : rtx op1 = gen_reg_rtx (V4SFmode);
833 69 : rtx op0 = gen_reg_rtx (V4SFmode);
834 :
835 69 : rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
836 : force_reg (V2SFmode, CONST1_RTX (V2SFmode)));
837 69 : emit_insn (gen_rtx_SET (op2, tmp));
838 69 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
839 :
840 69 : emit_insn (gen_divv4sf3 (op0, op1, op2));
841 :
842 69 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
843 69 : DONE;
844 : })
845 :
846 : (define_expand "<code>v2sf3"
847 : [(set (match_operand:V2SF 0 "register_operand")
848 : (smaxmin:V2SF
849 : (match_operand:V2SF 1 "register_operand")
850 : (match_operand:V2SF 2 "register_operand")))]
851 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
852 142 : {
853 142 : rtx op2 = gen_reg_rtx (V4SFmode);
854 142 : rtx op1 = gen_reg_rtx (V4SFmode);
855 142 : rtx op0 = gen_reg_rtx (V4SFmode);
856 :
857 1861797 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
858 1861791 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
859 1861655 :
860 148 : emit_insn (gen_<code>v4sf3 (op0, op1, op2));
861 6 :
862 142 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
863 142 : DONE;
864 : })
865 :
866 : (define_expand "mmx_<code>v2sf3"
867 : [(parallel
868 282242 : [(set (match_operand:V2SF 0 "register_operand")
869 282242 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
870 282242 : (match_operand:V2SF 2 "nonimmediate_operand")))
871 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
872 : "TARGET_3DNOW"
873 28 : {
874 28 : if (!flag_finite_math_only || flag_signed_zeros)
875 : {
876 28 : operands[1] = force_reg (V2SFmode, operands[1]);
877 310 : emit_insn (gen_mmx_ieee_<maxmin_float>v2sf3
878 : (operands[0], operands[1], operands[2]));
879 310 : DONE;
880 282 : }
881 282 : else
882 0 : ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
883 : })
884 :
885 : ;; These versions of the min/max patterns are intentionally ignorant of
886 : ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
887 0 : ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
888 : ;; are undefined in this condition, we're certain this is correct.
889 :
890 : (define_insn "*mmx_<code>v2sf3"
891 : [(set (match_operand:V2SF 0 "register_operand" "=y")
892 0 : (smaxmin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
893 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
894 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
895 0 : "TARGET_3DNOW && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
896 : "pf<maxmin_float>\t{%2, %0|%0, %2}"
897 8 : [(set_attr "type" "mmxadd")
898 : (set_attr "prefix_extra" "1")
899 8 : (set_attr "mode" "V2SF")])
900 8 :
901 8 : ;; These versions of the min/max patterns implement exactly the operations
902 : ;; min = (op1 < op2 ? op1 : op2)
903 : ;; max = (!(op1 < op2) ? op1 : op2)
904 433112 : ;; Their operands are not commutative, and thus they may be used in the
905 433112 : ;; presence of -0.0 and NaN.
906 :
907 238912 : (define_insn "mmx_ieee_<ieee_maxmin>v2sf3"
908 238912 : [(set (match_operand:V2SF 0 "register_operand" "=y")
909 : (unspec:V2SF
910 : [(match_operand:V2SF 1 "register_operand" "0")
911 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
912 : IEEE_MAXMIN))
913 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
914 63 : "TARGET_3DNOW"
915 : "pf<ieee_maxmin>\t{%2, %0|%0, %2}"
916 : [(set_attr "type" "mmxadd")
917 : (set_attr "prefix_extra" "1")
918 7809 : (set_attr "mode" "V2SF")])
919 330 :
920 7809 : (define_insn "mmx_rcpv2sf2"
921 : [(set (match_operand:V2SF 0 "register_operand" "=y")
922 7479 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
923 7479 : UNSPEC_PFRCP))]
924 7550 : "TARGET_3DNOW"
925 7479 : "pfrcp\t{%1, %0|%0, %1}"
926 7479 : [(set_attr "type" "mmx")
927 : (set_attr "prefix_extra" "1")
928 7557 : (set_attr "mode" "V2SF")])
929 7557 :
930 : (define_insn "mmx_rcpit1v2sf3"
931 7352 : [(set (match_operand:V2SF 0 "register_operand" "=y")
932 7352 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
933 7352 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
934 7274 : UNSPEC_PFRCPIT1))]
935 7425 : "TARGET_3DNOW"
936 7345 : "pfrcpit1\t{%2, %0|%0, %2}"
937 7345 : [(set_attr "type" "mmx")
938 71 : (set_attr "prefix_extra" "1")
939 7368 : (set_attr "mode" "V2SF")])
940 7368 :
941 7274 : (define_insn "mmx_rcpit2v2sf3"
942 7368 : [(set (match_operand:V2SF 0 "register_operand" "=y")
943 7274 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
944 7274 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
945 7274 : UNSPEC_PFRCPIT2))]
946 7354 : "TARGET_3DNOW"
947 : "pfrcpit2\t{%2, %0|%0, %2}"
948 6477 : [(set_attr "type" "mmx")
949 : (set_attr "prefix_extra" "1")
950 872 : (set_attr "mode" "V2SF")])
951 872 :
952 778 : (define_expand "sqrtv2sf2"
953 94 : [(set (match_operand:V2SF 0 "register_operand")
954 778 : (sqrt:V2SF (match_operand:V2SF 1 "nonimmediate_operand")))]
955 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
956 8 : {
957 8 : rtx op1 = gen_reg_rtx (V4SFmode);
958 8 : rtx op0 = gen_reg_rtx (V4SFmode);
959 :
960 8 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
961 0 :
962 8 : emit_insn (gen_sqrtv4sf2 (op0, op1));
963 :
964 8 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
965 8 : DONE;
966 : })
967 :
968 : (define_insn "mmx_rsqrtv2sf2"
969 : [(set (match_operand:V2SF 0 "register_operand" "=y")
970 : (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
971 : UNSPEC_PFRSQRT))]
972 71 : "TARGET_3DNOW"
973 : "pfrsqrt\t{%1, %0|%0, %1}"
974 : [(set_attr "type" "mmx")
975 : (set_attr "prefix_extra" "1")
976 2016 : (set_attr "mode" "V2SF")])
977 2016 :
978 122 : (define_insn "mmx_rsqit1v2sf3"
979 210 : [(set (match_operand:V2SF 0 "register_operand" "=y")
980 332 : (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
981 332 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
982 122 : UNSPEC_PFRSQIT1))]
983 289 : "TARGET_3DNOW"
984 209 : "pfrsqit1\t{%2, %0|%0, %2}"
985 209 : [(set_attr "type" "mmx")
986 : (set_attr "prefix_extra" "1")
987 117670 : (set_attr "mode" "V2SF")])
988 117670 :
989 146 : (define_expand "mmx_haddv2sf3"
990 4811 : [(set (match_operand:V2SF 0 "register_operand")
991 28 : (vec_concat:V2SF
992 : (plus:SF
993 : (vec_select:SF
994 : (match_operand:V2SF 1 "register_operand")
995 : (parallel [(const_int 0)]))
996 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
997 : (plus:SF
998 : (vec_select:SF
999 : (match_operand:V2SF 2 "nonimmediate_operand")
1000 : (parallel [(const_int 0)]))
1001 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1002 : "TARGET_3DNOW")
1003 :
1004 : (define_insn "*mmx_haddv2sf3"
1005 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1006 : (vec_concat:V2SF
1007 : (plus:SF
1008 : (vec_select:SF
1009 : (match_operand:V2SF 1 "register_operand" "0")
1010 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1011 : (vec_select:SF (match_dup 1)
1012 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))
1013 : (plus:SF
1014 : (vec_select:SF
1015 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1016 : (parallel [(match_operand:SI 5 "const_0_to_1_operand")]))
1017 : (vec_select:SF (match_dup 2)
1018 : (parallel [(match_operand:SI 6 "const_0_to_1_operand")])))))]
1019 79 : "TARGET_3DNOW
1020 79 : && INTVAL (operands[3]) != INTVAL (operands[4])
1021 79 : && INTVAL (operands[5]) != INTVAL (operands[6])"
1022 0 : "pfacc\t{%2, %0|%0, %2}"
1023 : [(set_attr "type" "mmxadd")
1024 : (set_attr "prefix_extra" "1")
1025 1679 : (set_attr "mode" "V2SF")])
1026 1679 :
1027 : (define_insn_and_split "*mmx_haddv2sf3_low"
1028 173 : [(set (match_operand:SF 0 "register_operand")
1029 1852 : (plus:SF
1030 1506 : (vec_select:SF
1031 173 : (match_operand:V2SF 1 "nonimmediate_operand")
1032 173 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))
1033 173 : (vec_select:SF
1034 173 : (match_dup 1)
1035 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))))]
1036 164 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1037 162 : && INTVAL (operands[2]) != INTVAL (operands[3])
1038 3 : && ix86_pre_reload_split ()"
1039 178 : "#"
1040 159 : "&& 1"
1041 218 : [(const_int 0)]
1042 101 : {
1043 259 : rtx op1 = gen_reg_rtx (V4SFmode);
1044 725 : rtx op0 = gen_reg_rtx (V4SFmode);
1045 804 :
1046 200 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1047 30 :
1048 46 : emit_insn (gen_sse3_haddv4sf3 (op0, op1, op1));
1049 80 :
1050 81 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1051 81 : DONE;
1052 80 : })
1053 :
1054 80 : (define_insn "mmx_hsubv2sf3"
1055 80 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1056 80 : (vec_concat:V2SF
1057 80 : (minus:SF
1058 : (vec_select:SF
1059 : (match_operand:V2SF 1 "register_operand" "0")
1060 : (parallel [(const_int 0)]))
1061 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1062 : (minus:SF
1063 719 : (vec_select:SF
1064 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1065 719 : (parallel [(const_int 0)]))
1066 719 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1067 799 : "TARGET_3DNOW_A"
1068 : "pfnacc\t{%2, %0|%0, %2}"
1069 : [(set_attr "type" "mmxadd")
1070 : (set_attr "prefix_extra" "1")
1071 79 : (set_attr "mode" "V2SF")])
1072 79 :
1073 79 : (define_insn_and_split "*mmx_hsubv2sf3_low"
1074 79 : [(set (match_operand:SF 0 "register_operand")
1075 : (minus:SF
1076 79 : (vec_select:SF
1077 79 : (match_operand:V2SF 1 "register_operand")
1078 79 : (parallel [(const_int 0)]))
1079 : (vec_select:SF
1080 79 : (match_dup 1)
1081 79 : (parallel [(const_int 1)]))))]
1082 82 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math
1083 3 : && ix86_pre_reload_split ()"
1084 79 : "#"
1085 79 : "&& 1"
1086 79 : [(const_int 0)]
1087 13 : {
1088 91 : rtx op1 = gen_reg_rtx (V4SFmode);
1089 391 : rtx op0 = gen_reg_rtx (V4SFmode);
1090 390 :
1091 12 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1092 109 :
1093 125 : emit_insn (gen_sse3_hsubv4sf3 (op0, op1, op1));
1094 79 :
1095 1 : emit_move_insn (operands[0], lowpart_subreg (SFmode, op0, V4SFmode));
1096 80 : DONE;
1097 79 : })
1098 79 :
1099 : (define_expand "mmx_haddsubv2sf3"
1100 79 : [(set (match_operand:V2SF 0 "register_operand")
1101 79 : (vec_concat:V2SF
1102 79 : (minus:SF
1103 : (vec_select:SF
1104 : (match_operand:V2SF 1 "register_operand")
1105 : (parallel [(const_int 0)]))
1106 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1107 : (plus:SF
1108 14 : (vec_select:SF
1109 : (match_operand:V2SF 2 "nonimmediate_operand")
1110 14 : (parallel [(const_int 0)]))
1111 14 : (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
1112 14 : "TARGET_3DNOW_A")
1113 :
1114 : (define_insn "*mmx_haddsubv2sf3"
1115 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1116 : (vec_concat:V2SF
1117 : (minus:SF
1118 : (vec_select:SF
1119 : (match_operand:V2SF 1 "register_operand" "0")
1120 : (parallel [(const_int 0)]))
1121 : (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1122 : (plus:SF
1123 : (vec_select:SF
1124 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")
1125 : (parallel [(match_operand:SI 3 "const_0_to_1_operand")]))
1126 : (vec_select:SF
1127 : (match_dup 2)
1128 : (parallel [(match_operand:SI 4 "const_0_to_1_operand")])))))]
1129 79 : "TARGET_3DNOW_A
1130 79 : && INTVAL (operands[3]) != INTVAL (operands[4])"
1131 : "pfpnacc\t{%2, %0|%0, %2}"
1132 : [(set_attr "type" "mmxadd")
1133 : (set_attr "prefix_extra" "1")
1134 : (set_attr "mode" "V2SF")])
1135 :
1136 : (define_expand "vec_addsubv2sf3"
1137 : [(set (match_operand:V2SF 0 "register_operand")
1138 3179041 : (vec_merge:V2SF
1139 3179041 : (minus:V2SF
1140 3179041 : (match_operand:V2SF 1 "nonimmediate_operand")
1141 3179041 : (match_operand:V2SF 2 "nonimmediate_operand"))
1142 3179041 : (plus:V2SF (match_dup 1) (match_dup 2))
1143 3179041 : (const_int 1)))]
1144 3179041 : "TARGET_SSE3 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1145 277 : {
1146 94921 : rtx op2 = gen_reg_rtx (V4SFmode);
1147 94921 : rtx op1 = gen_reg_rtx (V4SFmode);
1148 90603 : rtx op0 = gen_reg_rtx (V4SFmode);
1149 184970 :
1150 8097 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1151 87101 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1152 :
1153 81228 : emit_insn (gen_vec_addsubv4sf3 (op0, op1, op2));
1154 :
1155 277 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1156 277 : DONE;
1157 : })
1158 :
1159 : (define_expand "vec_fmaddsubv2sf4"
1160 : [(match_operand:V2SF 0 "register_operand")
1161 : (match_operand:V2SF 1 "nonimmediate_operand")
1162 : (match_operand:V2SF 2 "nonimmediate_operand")
1163 : (match_operand:V2SF 3 "nonimmediate_operand")]
1164 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1165 : && TARGET_MMX_WITH_SSE
1166 : && ix86_partial_vec_fp_math"
1167 6 : {
1168 6 : rtx op3 = gen_reg_rtx (V4SFmode);
1169 6 : rtx op2 = gen_reg_rtx (V4SFmode);
1170 6 : rtx op1 = gen_reg_rtx (V4SFmode);
1171 8 : rtx op0 = gen_reg_rtx (V4SFmode);
1172 :
1173 8 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1174 8 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1175 8 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1176 :
1177 6 : emit_insn (gen_vec_fmaddsubv4sf4 (op0, op1, op2, op3));
1178 :
1179 6 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1180 6 : DONE;
1181 : })
1182 :
1183 : (define_expand "vec_fmsubaddv2sf4"
1184 : [(match_operand:V2SF 0 "register_operand")
1185 : (match_operand:V2SF 1 "nonimmediate_operand")
1186 : (match_operand:V2SF 2 "nonimmediate_operand")
1187 : (match_operand:V2SF 3 "nonimmediate_operand")]
1188 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1189 : && TARGET_MMX_WITH_SSE
1190 : && ix86_partial_vec_fp_math"
1191 5 : {
1192 5 : rtx op3 = gen_reg_rtx (V4SFmode);
1193 5 : rtx op2 = gen_reg_rtx (V4SFmode);
1194 395 : rtx op1 = gen_reg_rtx (V4SFmode);
1195 5 : rtx op0 = gen_reg_rtx (V4SFmode);
1196 390 :
1197 395 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1198 395 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1199 5 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1200 :
1201 5 : emit_insn (gen_vec_fmsubaddv4sf4 (op0, op1, op2, op3));
1202 :
1203 5 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1204 5 : DONE;
1205 : })
1206 :
1207 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1208 : ;;
1209 : ;; Parallel single-precision floating point comparisons
1210 : ;;
1211 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1212 :
1213 : (define_expand "mmx_eqv2sf3"
1214 : [(parallel
1215 : [(set (match_operand:V2SI 0 "register_operand")
1216 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand")
1217 : (match_operand:V2SF 2 "nonimmediate_operand")))
1218 : (unspec [(const_int 0)] UNSPEC_3DNOW)])]
1219 218 : "TARGET_3DNOW"
1220 14 : "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
1221 218 :
1222 0 : (define_insn "*mmx_eqv2sf3"
1223 218 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1224 14 : (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
1225 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1226 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1227 70 : "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
1228 0 : "pfcmpeq\t{%2, %0|%0, %2}"
1229 14 : [(set_attr "type" "mmxcmp")
1230 : (set_attr "prefix_extra" "1")
1231 : (set_attr "mode" "V2SF")])
1232 :
1233 : (define_insn "mmx_gtv2sf3"
1234 151 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1235 : (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
1236 151 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1237 51418 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1238 221 : "TARGET_3DNOW"
1239 : "pfcmpgt\t{%2, %0|%0, %2}"
1240 : [(set_attr "type" "mmxcmp")
1241 51267 : (set_attr "prefix_extra" "1")
1242 94230 : (set_attr "mode" "V2SF")])
1243 94230 :
1244 94230 : (define_insn "mmx_gev2sf3"
1245 51267 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1246 51267 : (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
1247 51267 : (match_operand:V2SF 2 "nonimmediate_operand" "ym")))
1248 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1249 26931 : "TARGET_3DNOW"
1250 26861 : "pfcmpge\t{%2, %0|%0, %2}"
1251 26861 : [(set_attr "type" "mmxcmp")
1252 26861 : (set_attr "prefix_extra" "1")
1253 26861 : (set_attr "mode" "V2SF")])
1254 26861 :
1255 : (define_expand "vec_cmpv2sfv2si"
1256 627684 : [(set (match_operand:V2SI 0 "register_operand")
1257 627684 : (match_operator:V2SI 1 ""
1258 : [(match_operand:V2SF 2 "nonimmediate_operand")
1259 22 : (match_operand:V2SF 3 "nonimmediate_operand")]))]
1260 22 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1261 133 : {
1262 133 : rtx ops[4];
1263 133 : ops[3] = gen_reg_rtx (V4SFmode);
1264 122 : ops[2] = gen_reg_rtx (V4SFmode);
1265 133 : ops[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), V4SImode, ops[2], ops[3]);
1266 133 : ops[0] = gen_reg_rtx (V4SImode);
1267 11 :
1268 144 : emit_insn (gen_movq_v2sf_to_sse (ops[3], operands[3]));
1269 122 : emit_insn (gen_movq_v2sf_to_sse (ops[2], operands[2]));
1270 11 :
1271 133 : bool ok = ix86_expand_fp_vec_cmp (ops);
1272 133 : gcc_assert (ok);
1273 11 :
1274 133 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, ops[0], V4SImode));
1275 122 : DONE;
1276 : })
1277 :
1278 : (define_insn "@sse4_1_insertps_<mode>"
1279 : [(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v")
1280 : (unspec:V2FI
1281 : [(match_operand:V2FI 2 "nonimmediate_operand" "Yrjm,*xjm,vm")
1282 : (match_operand:V2FI 1 "register_operand" "0,0,v")
1283 : (match_operand:SI 3 "const_0_to_255_operand")]
1284 : UNSPEC_INSERTPS))]
1285 6786 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1286 556 : {
1287 556 : if (MEM_P (operands[2]))
1288 : {
1289 6 : unsigned count_s = INTVAL (operands[3]) >> 6;
1290 125 : if (count_s)
1291 0 : operands[3] = GEN_INT (INTVAL (operands[3]) & 0x3f);
1292 125 : operands[2] = adjust_address_nv (operands[2],
1293 43299 : <mmxscalarmode>mode, count_s * 4);
1294 43418 : }
1295 43855 : switch (which_alternative)
1296 43299 : {
1297 43299 : case 0:
1298 43299 : case 1:
1299 43299 : return "insertps\t{%3, %2, %0|%0, %2, %3}";
1300 43855 : case 2:
1301 43855 : return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
1302 43299 : default:
1303 0 : gcc_unreachable ();
1304 40248 : }
1305 : }
1306 321 : [(set_attr "isa" "noavx,noavx,avx")
1307 321 : (set_attr "addr" "gpr16,gpr16,*")
1308 : (set_attr "type" "sselog")
1309 594 : (set_attr "prefix_data16" "1,1,*")
1310 : (set_attr "prefix_extra" "1")
1311 : (set_attr "length_immediate" "1")
1312 : (set_attr "prefix" "orig,orig,maybe_evex")
1313 : (set_attr "mode" "V4SF")])
1314 :
1315 : (define_insn "*mmx_blendps"
1316 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1317 : (vec_merge:V2SF
1318 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1319 : (match_operand:V2SF 1 "register_operand" "0,0,x")
1320 : (match_operand:SI 3 "const_0_to_3_operand")))]
1321 1893 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1322 : "@
1323 : blendps\t{%3, %2, %0|%0, %2, %3}
1324 : blendps\t{%3, %2, %0|%0, %2, %3}
1325 3 : vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1326 3 : [(set_attr "isa" "noavx,noavx,avx")
1327 : (set_attr "type" "ssemov")
1328 3 : (set_attr "c86_attr" "blend")
1329 : (set_attr "length_immediate" "1")
1330 : (set_attr "prefix_data16" "1,1,*")
1331 : (set_attr "prefix_extra" "1")
1332 : (set_attr "prefix" "orig,orig,vex")
1333 : (set_attr "mode" "V4SF")])
1334 :
1335 : (define_insn "mmx_blendvps"
1336 : [(set (match_operand:V2SF 0 "register_operand" "=Yr,*x,x")
1337 : (unspec:V2SF
1338 : [(match_operand:V2SF 1 "register_operand" "0,0,x")
1339 : (match_operand:V2SF 2 "register_operand" "Yr,*x,x")
1340 : (match_operand:V2SF 3 "register_operand" "Yz,Yz,x")]
1341 : UNSPEC_BLENDV))]
1342 18 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
1343 : "@
1344 : blendvps\t{%3, %2, %0|%0, %2, %3}
1345 : blendvps\t{%3, %2, %0|%0, %2, %3}
1346 3806 : vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1347 3806 : [(set_attr "isa" "noavx,noavx,avx")
1348 : (set_attr "type" "ssemov")
1349 3806 : (set_attr "c86_attr" "blendv")
1350 : (set_attr "length_immediate" "1")
1351 : (set_attr "prefix_data16" "1,1,*")
1352 : (set_attr "prefix_extra" "1")
1353 : (set_attr "prefix" "orig,orig,vex")
1354 : (set_attr "btver2_decode" "vector")
1355 : (set_attr "mode" "V4SF")])
1356 :
1357 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1358 : ;;
1359 : ;; Parallel single-precision floating point logical operations
1360 : ;;
1361 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1362 :
1363 : (define_insn "*mmx_andnotv2sf3"
1364 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1365 : (and:V2SF
1366 : (not:V2SF
1367 : (match_operand:V2SF 1 "register_operand" "0,x"))
1368 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1369 234 : "TARGET_MMX_WITH_SSE"
1370 : "@
1371 : andnps\t{%2, %0|%0, %2}
1372 : vandnps\t{%2, %1, %0|%0, %1, %2}"
1373 0 : [(set_attr "isa" "noavx,avx")
1374 0 : (set_attr "type" "sselog")
1375 : (set_attr "prefix" "orig,vex")
1376 0 : (set_attr "mode" "V4SF")])
1377 :
1378 : (define_insn "<code>v2sf3"
1379 : [(set (match_operand:V2SF 0 "register_operand" "=x,x")
1380 : (any_logic:V2SF
1381 : (match_operand:V2SF 1 "register_operand" "%0,x")
1382 : (match_operand:V2SF 2 "register_operand" "x,x")))]
1383 630 : "TARGET_MMX_WITH_SSE"
1384 : "@
1385 : <logic>ps\t{%2, %0|%0, %2}
1386 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
1387 2 : [(set_attr "isa" "noavx,avx")
1388 2 : (set_attr "type" "sselog")
1389 1 : (set_attr "prefix" "orig,vex")
1390 : (set_attr "mode" "V4SF")])
1391 1 :
1392 : (define_expand "copysignv2sf3"
1393 : [(set (match_dup 4)
1394 : (and:V2SF
1395 : (not:V2SF (match_dup 3))
1396 : (match_operand:V2SF 1 "register_operand")))
1397 : (set (match_dup 5)
1398 : (and:V2SF (match_dup 3)
1399 : (match_operand:V2SF 2 "register_operand")))
1400 : (set (match_operand:V2SF 0 "register_operand")
1401 : (ior:V2SF (match_dup 4) (match_dup 5)))]
1402 : "TARGET_MMX_WITH_SSE"
1403 7 : {
1404 7 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1405 :
1406 7 : operands[4] = gen_reg_rtx (V2SFmode);
1407 7 : operands[5] = gen_reg_rtx (V2SFmode);
1408 : })
1409 :
1410 : (define_expand "xorsignv2sf3"
1411 : [(set (match_dup 4)
1412 7 : (and:V2SF (match_dup 3)
1413 : (match_operand:V2SF 2 "register_operand")))
1414 : (set (match_operand:V2SF 0 "register_operand")
1415 : (xor:V2SF (match_dup 4)
1416 : (match_operand:V2SF 1 "register_operand")))]
1417 : "TARGET_MMX_WITH_SSE"
1418 8 : {
1419 1 : operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
1420 :
1421 1 : operands[4] = gen_reg_rtx (V2SFmode);
1422 : })
1423 2 :
1424 : (define_expand "signbitv2sf2"
1425 2 : [(set (match_operand:V2SI 0 "register_operand")
1426 3 : (lshiftrt:V2SI
1427 2 : (subreg:V2SI
1428 : (match_operand:V2SF 1 "register_operand") 0)
1429 : (match_dup 2)))]
1430 : "TARGET_MMX_WITH_SSE"
1431 2 : {
1432 1 : operands[1] = force_reg (V2SFmode, operands[1]);
1433 1 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);
1434 : })
1435 :
1436 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1437 : ;;
1438 2 : ;; Parallel single-precision FMA multiply/accumulate instructions.
1439 1 : ;;
1440 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1441 :
1442 1 : (define_expand "fmav2sf4"
1443 : [(set (match_operand:V2SF 0 "register_operand")
1444 : (fma:V2SF
1445 : (match_operand:V2SF 1 "nonimmediate_operand")
1446 : (match_operand:V2SF 2 "nonimmediate_operand")
1447 81 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1448 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1449 81 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1450 800 : {
1451 800 : rtx op3 = gen_reg_rtx (V4SFmode);
1452 719 : rtx op2 = gen_reg_rtx (V4SFmode);
1453 719 : rtx op1 = gen_reg_rtx (V4SFmode);
1454 719 : rtx op0 = gen_reg_rtx (V4SFmode);
1455 :
1456 719 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1457 719 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1458 719 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1459 :
1460 719 : emit_insn (gen_fmav4sf4 (op0, op1, op2, op3));
1461 :
1462 719 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1463 719 : DONE;
1464 : })
1465 :
1466 : (define_expand "fmsv2sf4"
1467 : [(set (match_operand:V2SF 0 "register_operand")
1468 : (fma:V2SF
1469 : (match_operand:V2SF 1 "nonimmediate_operand")
1470 : (match_operand:V2SF 2 "nonimmediate_operand")
1471 : (neg:V2SF
1472 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1473 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1474 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1475 14 : {
1476 14 : rtx op3 = gen_reg_rtx (V4SFmode);
1477 29 : rtx op2 = gen_reg_rtx (V4SFmode);
1478 14 : rtx op1 = gen_reg_rtx (V4SFmode);
1479 29 : rtx op0 = gen_reg_rtx (V4SFmode);
1480 15 :
1481 29 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1482 14 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1483 14 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1484 :
1485 14 : emit_insn (gen_fmsv4sf4 (op0, op1, op2, op3));
1486 :
1487 14 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1488 14 : DONE;
1489 : })
1490 :
1491 : (define_expand "fnmav2sf4"
1492 : [(set (match_operand:V2SF 0 "register_operand")
1493 : (fma:V2SF
1494 : (neg:V2SF
1495 : (match_operand:V2SF 1 "nonimmediate_operand"))
1496 : (match_operand:V2SF 2 "nonimmediate_operand")
1497 : (match_operand:V2SF 3 "nonimmediate_operand")))]
1498 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1499 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1500 151 : {
1501 151 : rtx op3 = gen_reg_rtx (V4SFmode);
1502 151 : rtx op2 = gen_reg_rtx (V4SFmode);
1503 697 : rtx op1 = gen_reg_rtx (V4SFmode);
1504 151 : rtx op0 = gen_reg_rtx (V4SFmode);
1505 546 :
1506 151 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1507 697 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1508 151 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1509 :
1510 151 : emit_insn (gen_fnmav4sf4 (op0, op1, op2, op3));
1511 :
1512 151 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1513 151 : DONE;
1514 : })
1515 :
1516 : (define_expand "fnmsv2sf4"
1517 : [(set (match_operand:V2SF 0 "register_operand" "=v,v,x")
1518 : (fma:V2SF
1519 : (neg:V2SF
1520 : (match_operand:V2SF 1 "nonimmediate_operand"))
1521 : (match_operand:V2SF 2 "nonimmediate_operand")
1522 : (neg:V2SF
1523 : (match_operand:V2SF 3 "nonimmediate_operand"))))]
1524 : "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512VL)
1525 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1526 2 : {
1527 3 : rtx op3 = gen_reg_rtx (V4SFmode);
1528 2 : rtx op2 = gen_reg_rtx (V4SFmode);
1529 3 : rtx op1 = gen_reg_rtx (V4SFmode);
1530 3 : rtx op0 = gen_reg_rtx (V4SFmode);
1531 1 :
1532 2 : emit_insn (gen_movq_v2sf_to_sse (op3, operands[3]));
1533 2 : emit_insn (gen_movq_v2sf_to_sse (op2, operands[2]));
1534 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1535 :
1536 2 : emit_insn (gen_fnmsv4sf4 (op0, op1, op2, op3));
1537 :
1538 2 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1539 2 : DONE;
1540 : })
1541 :
1542 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1543 : ;;
1544 : ;; Parallel single-precision floating point conversion operations
1545 : ;;
1546 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1547 :
1548 : (define_expand "fix_truncv2sfv2si2"
1549 : [(set (match_operand:V2SI 0 "register_operand")
1550 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1551 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1552 81 : {
1553 81 : rtx op1 = gen_reg_rtx (V4SFmode);
1554 82 : rtx op0 = gen_reg_rtx (V4SImode);
1555 :
1556 82 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1557 1 :
1558 82 : emit_insn (gen_fix_truncv4sfv4si2 (op0, op1));
1559 :
1560 81 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1561 81 : DONE;
1562 : })
1563 :
1564 : (define_expand "fixuns_truncv2sfv2si2"
1565 : [(set (match_operand:V2SI 0 "register_operand")
1566 : (unsigned_fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand")))]
1567 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1568 1 : {
1569 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1570 1 : rtx op0 = gen_reg_rtx (V4SImode);
1571 :
1572 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1573 :
1574 1316 : emit_insn (gen_fixuns_truncv4sfv4si2 (op0, op1));
1575 :
1576 1316 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1577 1316 : DONE;
1578 1315 : })
1579 :
1580 : (define_insn "mmx_fix_truncv2sfv2si2"
1581 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1582 : (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))
1583 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1584 54 : "TARGET_3DNOW"
1585 : "pf2id\t{%1, %0|%0, %1}"
1586 : [(set_attr "type" "mmxcvt")
1587 : (set_attr "prefix_extra" "1")
1588 : (set_attr "mode" "V2SF")])
1589 :
1590 1941 : (define_expand "floatv2siv2sf2"
1591 : [(set (match_operand:V2SF 0 "register_operand")
1592 1941 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1593 1941 : "TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1594 62119740 : {
1595 390 : rtx op1 = gen_reg_rtx (V4SImode);
1596 390 : rtx op0 = gen_reg_rtx (V4SFmode);
1597 :
1598 62117799 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1599 62117409 :
1600 62117799 : emit_insn (gen_floatv4siv4sf2 (op0, op1));
1601 62117409 :
1602 390 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1603 61015348 : DONE;
1604 61014958 : })
1605 61014958 :
1606 61014958 : (define_expand "floatunsv2siv2sf2"
1607 : [(set (match_operand:V2SF 0 "register_operand")
1608 61007411 : (unsigned_float:V2SF (match_operand:V2SI 1 "nonimmediate_operand")))]
1609 61007411 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1610 61007413 : {
1611 2 : rtx op1 = gen_reg_rtx (V4SImode);
1612 61007413 : rtx op0 = gen_reg_rtx (V4SFmode);
1613 :
1614 38007609 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
1615 38007607 :
1616 3 : emit_insn (gen_floatunsv4siv4sf2 (op0, op1));
1617 38005100 :
1618 38005103 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1619 38005103 : DONE;
1620 38005101 : })
1621 9097 :
1622 37996003 : (define_insn "mmx_floatv2siv2sf2"
1623 75612604 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1624 : (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))
1625 : (unspec [(const_int 0)] UNSPEC_3DNOW)]
1626 66 : "TARGET_3DNOW"
1627 : "pi2fd\t{%1, %0|%0, %1}"
1628 : [(set_attr "type" "mmxcvt")
1629 : (set_attr "prefix_extra" "1")
1630 : (set_attr "mode" "V2SF")])
1631 :
1632 1 : (define_insn "mmx_pf2iw"
1633 : [(set (match_operand:V2SI 0 "register_operand" "=y")
1634 1 : (sign_extend:V2SI
1635 1 : (ss_truncate:V2HI
1636 92 : (fix:V2SI
1637 : (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
1638 70 : "TARGET_3DNOW_A"
1639 : "pf2iw\t{%1, %0|%0, %1}"
1640 91 : [(set_attr "type" "mmxcvt")
1641 91 : (set_attr "prefix_extra" "1")
1642 33907 : (set_attr "mode" "V2SF")])
1643 33907 :
1644 33816 : (define_insn "mmx_pi2fw"
1645 90 : [(set (match_operand:V2SF 0 "register_operand" "=y")
1646 33906 : (float:V2SF
1647 33816 : (sign_extend:V2SI
1648 33866 : (truncate:V2HI
1649 50 : (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
1650 11468 : "TARGET_3DNOW_A"
1651 11402 : "pi2fw\t{%1, %0|%0, %1}"
1652 12236 : [(set_attr "type" "mmxcvt")
1653 50 : (set_attr "prefix_extra" "1")
1654 50 : (set_attr "mode" "V2SF")])
1655 :
1656 28 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1657 : ;;
1658 0 : ;; Parallel single-precision floating point element swizzling
1659 0 : ;;
1660 229242 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1661 :
1662 : (define_insn "mmx_pswapdv2sf2"
1663 : [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv")
1664 229242 : (vec_select:V2SF
1665 229242 : (match_operand:V2SF 1 "register_mmxmem_operand" "ym,0,Yv")
1666 229242 : (parallel [(const_int 1) (const_int 0)])))]
1667 236198 : "TARGET_3DNOW_A || TARGET_MMX_WITH_SSE"
1668 229242 : "@
1669 229242 : pswapd\t{%1, %0|%0, %1}
1670 : shufps\t{$0xe1, %1, %0|%0, %1, 0xe1}
1671 155441 : vshufps\t{$0xe1, %1, %1, %0|%0, %1, %1, 0xe1}"
1672 155441 : [(set_attr "isa" "*,sse_noavx,avx")
1673 155441 : (set_attr "mmx_isa" "native,*,*")
1674 151096 : (set_attr "type" "mmxcvt,ssemov,ssemov")
1675 151096 : (set_attr "prefix_extra" "1,*,*")
1676 151096 : (set_attr "mode" "V2SF,V4SF,V4SF")])
1677 :
1678 151095 : (define_insn "*mmx_movshdup"
1679 151095 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1680 151095 : (vec_select:V2SF
1681 151095 : (match_operand:V2SF 1 "register_operand" "v,0")
1682 151095 : (parallel [(const_int 1) (const_int 1)])))]
1683 4161 : "TARGET_MMX_WITH_SSE"
1684 3334 : "@
1685 3334 : %vmovshdup\t{%1, %0|%0, %1}
1686 3334 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}"
1687 3334 : [(set_attr "isa" "sse3,*")
1688 3334 : (set_attr "type" "sse,sseshuf1")
1689 6668 : (set_attr "length_immediate" "*,1")
1690 : (set_attr "prefix_rep" "1,*")
1691 : (set_attr "prefix" "maybe_vex,orig")
1692 : (set_attr "mode" "V4SF")])
1693 4881 :
1694 4881 : (define_insn "*mmx_movsldup"
1695 : [(set (match_operand:V2SF 0 "register_operand" "=v,x")
1696 4444 : (vec_select:V2SF
1697 4444 : (match_operand:V2SF 1 "register_operand" "v,0")
1698 4411 : (parallel [(const_int 0) (const_int 0)])))]
1699 8657 : "TARGET_MMX_WITH_SSE"
1700 : "@
1701 : %vmovsldup\t{%1, %0|%0, %1}
1702 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1703 429 : [(set_attr "isa" "sse3,*")
1704 429 : (set_attr "type" "sse,sseshuf1")
1705 429 : (set_attr "length_immediate" "*,1")
1706 855 : (set_attr "prefix_rep" "1,*")
1707 : (set_attr "prefix" "maybe_vex,orig")
1708 : (set_attr "mode" "V4SF")])
1709 :
1710 : (define_insn_and_split "*vec_interleave_lowv2sf"
1711 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1712 : (vec_select:V2SF
1713 : (vec_concat:V4SF
1714 : (match_operand:V2SF 1 "register_operand" "0,v")
1715 : (match_operand:V2SF 2 "register_operand" "x,v"))
1716 : (parallel [(const_int 0) (const_int 2)])))]
1717 5685 : "TARGET_MMX_WITH_SSE"
1718 : "#"
1719 436 : "&& reload_completed"
1720 218 : [(const_int 0)]
1721 13977 : "ix86_split_mmx_punpck (operands, false); DONE;"
1722 13759 : [(set_attr "isa" "noavx,avx")
1723 698 : (set_attr "type" "sselog")
1724 698 : (set_attr "prefix" "orig,maybe_evex")
1725 : (set_attr "mode" "V4SF")])
1726 :
1727 : (define_insn_and_split "*vec_interleave_highv2sf"
1728 : [(set (match_operand:V2SF 0 "register_operand" "=x,v")
1729 : (vec_select:V2SF
1730 : (vec_concat:V4SF
1731 : (match_operand:V2SF 1 "register_operand" "0,v")
1732 : (match_operand:V2SF 2 "register_operand" "x,v"))
1733 43 : (parallel [(const_int 1) (const_int 3)])))]
1734 2640 : "TARGET_MMX_WITH_SSE"
1735 43 : "#"
1736 238 : "&& reload_completed"
1737 162 : [(const_int 0)]
1738 7448 : "ix86_split_mmx_punpck (operands, true); DONE;"
1739 7329 : [(set_attr "isa" "noavx,avx")
1740 560 : (set_attr "type" "sselog")
1741 560 : (set_attr "prefix" "orig,vex")
1742 : (set_attr "mode" "V4SF")])
1743 :
1744 : (define_insn "*vec_dupv2sf"
1745 : [(set (match_operand:V2SF 0 "register_operand" "=y,Yv,x")
1746 : (vec_duplicate:V2SF
1747 : (match_operand:SF 1 "register_operand" "0,Yv,0")))]
1748 5193 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1749 416 : "@
1750 : punpckldq\t%0, %0
1751 1 : %vmovsldup\t{%1, %0|%0, %1}
1752 38 : shufps\t{$0xe0, %0, %0|%0, %0, 0xe0}"
1753 38 : [(set_attr "isa" "*,sse3,sse_noavx")
1754 32 : (set_attr "mmx_isa" "native,*,*")
1755 32 : (set_attr "type" "mmxcvt,sse,sseshuf1")
1756 69 : (set_attr "length_immediate" "*,*,1")
1757 : (set_attr "prefix_rep" "*,1,*")
1758 : (set_attr "prefix" "*,maybe_vex,orig")
1759 : (set_attr "mode" "DI,V4SF,V4SF")])
1760 :
1761 : (define_insn "*mmx_movss_<mode>"
1762 : [(set (match_operand:V2FI 0 "register_operand" "=x,v")
1763 : (vec_merge:V2FI
1764 : (match_operand:V2FI 2 "register_operand" " x,v")
1765 : (match_operand:V2FI 1 "register_operand" " 0,v")
1766 : (const_int 1)))]
1767 4293 : "TARGET_MMX_WITH_SSE"
1768 : "@
1769 : movss\t{%2, %0|%0, %2}
1770 : vmovss\t{%2, %1, %0|%0, %1, %2}"
1771 3396 : [(set_attr "isa" "noavx,avx")
1772 3396 : (set_attr "type" "ssemov")
1773 : (set_attr "prefix" "orig,maybe_evex")
1774 3396 : (set_attr "mode" "SF")])
1775 399783 :
1776 399783 : (define_insn "*mmx_concatv2sf"
1777 399783 : [(set (match_operand:V2SF 0 "register_operand" "=y,y")
1778 399783 : (vec_concat:V2SF
1779 399783 : (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
1780 399783 : (match_operand:SF 2 "nonimm_or_0_operand" "ym,C")))]
1781 480734 : "TARGET_MMX && !TARGET_SSE"
1782 399783 : "@
1783 80951 : punpckldq\t{%2, %0|%0, %2}
1784 388650 : movd\t{%1, %0|%0, %1}"
1785 : [(set_attr "type" "mmxcvt,mmxmov")
1786 272 : (set_attr "mode" "DI")])
1787 272 :
1788 : (define_expand "vec_setv2sf"
1789 : [(match_operand:V2SF 0 "register_operand")
1790 272 : (match_operand:SF 1 "register_operand")
1791 : (match_operand 2 "vec_setm_mmx_operand")]
1792 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1793 15 : {
1794 15 : if (CONST_INT_P (operands[2]))
1795 13 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
1796 13 : INTVAL (operands[2]));
1797 : else
1798 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
1799 15 : DONE;
1800 : })
1801 :
1802 : ;; Avoid combining registers from different units in a single alternative,
1803 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1804 : (define_insn_and_split "*vec_extractv2sf_0"
1805 : [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
1806 : (vec_select:SF
1807 : (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
1808 : (parallel [(const_int 0)])))]
1809 1643 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1810 11418 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1811 : "#"
1812 1593 : "&& reload_completed"
1813 546 : [(set (match_dup 0) (match_dup 1))]
1814 84266 : "operands[1] = gen_lowpart (SFmode, operands[1]);"
1815 83720 : [(set_attr "mmx_isa" "*,*,native,native,*,*")])
1816 14231 :
1817 14776 : ;; Avoid combining registers from different units in a single alternative,
1818 : ;; see comment above inline_secondary_memory_needed function in i386.cc
1819 : (define_insn "*vec_extractv2sf_1"
1820 546 : [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,x,y,x,f,r")
1821 : (vec_select:SF
1822 : (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,0,o,o,o,o")
1823 : (parallel [(const_int 1)])))]
1824 5403 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
1825 5405 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1826 : "@
1827 2 : punpckhdq\t%0, %0
1828 2 : %vmovshdup\t{%1, %0|%0, %1}
1829 14288 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
1830 14286 : #
1831 14110 : #
1832 28396 : #
1833 : #"
1834 13925 : [(set_attr "isa" "*,sse3,noavx,*,*,*,*")
1835 : (set_attr "mmx_isa" "native,*,*,native,*,*,*")
1836 : (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov")
1837 : (set (attr "length_immediate")
1838 : (if_then_else (eq_attr "alternative" "2")
1839 : (const_string "1")
1840 : (const_string "*")))
1841 : (set (attr "prefix_rep")
1842 : (if_then_else (eq_attr "alternative" "1")
1843 : (const_string "1")
1844 : (const_string "*")))
1845 : (set_attr "prefix" "orig,maybe_vex,orig,orig,orig,orig,orig")
1846 : (set_attr "mode" "DI,V4SF,V4SF,SF,SF,SF,SF")])
1847 :
1848 : (define_split
1849 : [(set (match_operand:SF 0 "register_operand")
1850 : (vec_select:SF
1851 : (match_operand:V2SF 1 "memory_operand")
1852 : (parallel [(const_int 1)])))]
1853 49 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
1854 43 : [(set (match_dup 0) (match_dup 1))]
1855 43 : "operands[1] = adjust_address (operands[1], SFmode, 4);")
1856 :
1857 5570 : (define_expand "vec_extractv2sfsf"
1858 5613 : [(match_operand:SF 0 "register_operand")
1859 4226 : (match_operand:V2SF 1 "register_operand")
1860 4226 : (match_operand 2 "const_int_operand")]
1861 5613 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
1862 1315 : {
1863 1315 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
1864 1315 : operands[1], INTVAL (operands[2]));
1865 1315 : DONE;
1866 1 : })
1867 :
1868 1 : (define_expand "vec_initv2sfsf"
1869 1 : [(match_operand:V2SF 0 "register_operand")
1870 1 : (match_operand 1)]
1871 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
1872 1941 : {
1873 1941 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
1874 : operands[1]);
1875 1941 : DONE;
1876 : })
1877 :
1878 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1879 : ;;
1880 1 : ;; Parallel single-precision floating point rounding operations.
1881 1 : ;;
1882 1 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1883 :
1884 : (define_expand "nearbyintv2sf2"
1885 : [(match_operand:V2SF 0 "register_operand")
1886 : (match_operand:V2SF 1 "nonimmediate_operand")]
1887 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1888 2 : {
1889 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1890 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1891 1 :
1892 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1893 :
1894 1 : emit_insn (gen_nearbyintv4sf2 (op0, op1));
1895 :
1896 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1897 1 : DONE;
1898 : })
1899 :
1900 : (define_expand "rintv2sf2"
1901 : [(match_operand:V2SF 0 "register_operand")
1902 : (match_operand:V2SF 1 "nonimmediate_operand")]
1903 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1904 1 : {
1905 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1906 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1907 :
1908 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1909 :
1910 9 : emit_insn (gen_rintv4sf2 (op0, op1));
1911 :
1912 9 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1913 9 : DONE;
1914 8 : })
1915 :
1916 : (define_expand "lrintv2sfv2si2"
1917 : [(match_operand:V2SI 0 "register_operand")
1918 : (match_operand:V2SF 1 "nonimmediate_operand")]
1919 : "TARGET_SSE4_1 && !flag_trapping_math
1920 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1921 1 : {
1922 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1923 1 : rtx op0 = gen_reg_rtx (V4SImode);
1924 :
1925 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1926 111 :
1927 1 : emit_insn (gen_lrintv4sfv4si2 (op0, op1));
1928 111 :
1929 112 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1930 112 : DONE;
1931 : })
1932 :
1933 : (define_expand "ceilv2sf2"
1934 : [(match_operand:V2SF 0 "register_operand")
1935 : (match_operand:V2SF 1 "nonimmediate_operand")]
1936 : "TARGET_SSE4_1 && !flag_trapping_math
1937 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1938 1 : {
1939 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1940 1 : rtx op0 = gen_reg_rtx (V4SFmode);
1941 :
1942 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1943 0 :
1944 1 : emit_insn (gen_ceilv4sf2 (op0, op1));
1945 0 :
1946 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1947 1 : DONE;
1948 : })
1949 :
1950 : (define_expand "lceilv2sfv2si2"
1951 : [(match_operand:V2SI 0 "register_operand")
1952 : (match_operand:V2SF 1 "nonimmediate_operand")]
1953 : "TARGET_SSE4_1 && !flag_trapping_math
1954 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1955 1 : {
1956 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1957 1 : rtx op0 = gen_reg_rtx (V4SImode);
1958 :
1959 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1960 4 :
1961 1 : emit_insn (gen_lceilv4sfv4si2 (op0, op1));
1962 4 :
1963 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1964 5 : DONE;
1965 : })
1966 :
1967 : (define_expand "floorv2sf2"
1968 : [(match_operand:V2SF 0 "register_operand")
1969 : (match_operand:V2SF 1 "nonimmediate_operand")]
1970 : "TARGET_SSE4_1 && !flag_trapping_math
1971 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1972 2 : {
1973 2 : rtx op1 = gen_reg_rtx (V4SFmode);
1974 2 : rtx op0 = gen_reg_rtx (V4SFmode);
1975 :
1976 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1977 5 :
1978 2 : emit_insn (gen_floorv4sf2 (op0, op1));
1979 5 :
1980 7 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
1981 2 : DONE;
1982 : })
1983 :
1984 5 : (define_expand "lfloorv2sfv2si2"
1985 : [(match_operand:V2SI 0 "register_operand")
1986 : (match_operand:V2SF 1 "nonimmediate_operand")]
1987 : "TARGET_SSE4_1 && !flag_trapping_math
1988 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
1989 8 : {
1990 1 : rtx op1 = gen_reg_rtx (V4SFmode);
1991 8 : rtx op0 = gen_reg_rtx (V4SImode);
1992 7 :
1993 8 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
1994 0 :
1995 1 : emit_insn (gen_lfloorv4sfv4si2 (op0, op1));
1996 0 :
1997 1 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
1998 1 : DONE;
1999 : })
2000 :
2001 0 : (define_expand "btruncv2sf2"
2002 : [(match_operand:V2SF 0 "register_operand")
2003 : (match_operand:V2SF 1 "nonimmediate_operand")]
2004 : "TARGET_SSE4_1 && !flag_trapping_math
2005 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2006 5 : {
2007 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2008 5 : rtx op0 = gen_reg_rtx (V4SFmode);
2009 4 :
2010 5 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2011 0 :
2012 1 : emit_insn (gen_btruncv4sf2 (op0, op1));
2013 0 :
2014 1 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2015 1 : DONE;
2016 : })
2017 :
2018 0 : (define_expand "roundv2sf2"
2019 : [(match_operand:V2SF 0 "register_operand")
2020 : (match_operand:V2SF 1 "nonimmediate_operand")]
2021 : "TARGET_SSE4_1 && !flag_trapping_math
2022 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2023 2 : {
2024 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2025 2 : rtx op0 = gen_reg_rtx (V4SFmode);
2026 1 :
2027 2 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2028 10 :
2029 1 : emit_insn (gen_roundv4sf2 (op0, op1));
2030 10 :
2031 11 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
2032 11 : DONE;
2033 : })
2034 :
2035 : (define_expand "lroundv2sfv2si2"
2036 : [(match_operand:V2SI 0 "register_operand")
2037 : (match_operand:V2SF 1 "nonimmediate_operand")]
2038 : "TARGET_SSE4_1 && !flag_trapping_math
2039 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
2040 1 : {
2041 1 : rtx op1 = gen_reg_rtx (V4SFmode);
2042 1 : rtx op0 = gen_reg_rtx (V4SImode);
2043 :
2044 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
2045 4 :
2046 1 : emit_insn (gen_lroundv4sfv4si2 (op0, op1));
2047 4 :
2048 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
2049 5 : DONE;
2050 : })
2051 :
2052 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2053 : ;;
2054 : ;; Parallel half-precision floating point arithmetic
2055 : ;;
2056 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2057 :
2058 : (define_mode_iterator VHF_32_64 [V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2059 :
2060 : (define_mode_iterator VBF_32_64 [V2BF (V4BF "TARGET_MMX_WITH_SSE")])
2061 :
2062 4 : (define_expand "divv4hf3"
2063 : [(set (match_operand:V4HF 0 "register_operand")
2064 4 : (div:V4HF
2065 4 : (match_operand:V4HF 1 "nonimmediate_operand")
2066 4 : (match_operand:V4HF 2 "register_operand")))]
2067 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math
2068 : && TARGET_MMX_WITH_SSE"
2069 8 : {
2070 8 : rtx op2 = gen_reg_rtx (V8HFmode);
2071 8 : rtx op1 = gen_reg_rtx (V8HFmode);
2072 8 : rtx op0 = gen_reg_rtx (V8HFmode);
2073 :
2074 8 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2075 8 : rtx tmp = gen_rtx_VEC_CONCAT (V8HFmode, operands[2],
2076 : force_reg (V4HFmode, CONST1_RTX (V4HFmode)));
2077 8 : emit_insn (gen_rtx_SET (op2, tmp));
2078 8 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2079 8 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2080 8 : DONE;
2081 : })
2082 :
2083 : (define_mode_attr mov_to_sse_suffix
2084 : [(V2HF "d") (V4HF "q") (V2HI "d") (V4HI "q")])
2085 :
2086 : (define_mode_attr mmxxmmmode
2087 : [(V2HF "V8HF") (V2HI "V8HI") (V2BF "V8BF")
2088 : (V4HF "V8HF") (V4HI "V8HI") (V4BF "V8BF")])
2089 :
2090 : (define_mode_attr mmxxmmmodelower
2091 : [(V2HF "v8hf") (V2HI "v8hi") (V2BF "v8bf")
2092 : (V4HF "v8hf") (V4HI "v8hi") (V4BF "v8bf")])
2093 :
2094 2 : (define_expand "movd_<mode>_to_sse"
2095 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2096 2 : (vec_merge:<mmxxmmmode>
2097 2 : (vec_duplicate:<mmxxmmmode>
2098 2 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2099 : (match_dup 2)
2100 : (const_int 3)))]
2101 : "TARGET_SSE"
2102 115 : {
2103 115 : if (!flag_trapping_math)
2104 : {
2105 13 : rtx op1 = force_reg (<MODE>mode, operands[1]);
2106 13 : emit_move_insn (operands[0],
2107 : lowpart_subreg (<mmxxmmmode>mode, op1, <MODE>mode));
2108 13 : DONE;
2109 : }
2110 102 : operands[2] = CONST0_RTX (<mmxxmmmode>mode);
2111 : })
2112 :
2113 : (define_expand "movd_<mode>_to_sse_reg"
2114 : [(set (match_operand:<mmxxmmmode> 0 "register_operand")
2115 102 : (vec_merge:<mmxxmmmode>
2116 : (vec_duplicate:<mmxxmmmode>
2117 : (match_operand:V2FI_32 1 "nonimmediate_operand"))
2118 : (match_operand:<mmxxmmmode> 2 "register_operand")
2119 102 : (const_int 3)))]
2120 : "TARGET_SSE")
2121 :
2122 : (define_expand "<insn><mode>3"
2123 : [(set (match_operand:VHF_32_64 0 "register_operand")
2124 6 : (plusminusmult:VHF_32_64
2125 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2126 6 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2127 6 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2128 35 : {
2129 33 : rtx op2 = gen_reg_rtx (V8HFmode);
2130 33 : rtx op1 = gen_reg_rtx (V8HFmode);
2131 33 : rtx op0 = gen_reg_rtx (V8HFmode);
2132 :
2133 33 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2134 33 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2135 33 : emit_insn (gen_<insn>v8hf3 (op0, op1, op2));
2136 :
2137 33 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2138 33 : DONE;
2139 : })
2140 :
2141 : ;; VDIVNEPBF16 does not generate floating point exceptions.
2142 : (define_expand "<insn><mode>3"
2143 : [(set (match_operand:VBF_32_64 0 "register_operand")
2144 : (plusminusmultdiv:VBF_32_64
2145 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2146 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2147 : "TARGET_AVX10_2"
2148 10 : {
2149 41 : rtx op0 = gen_reg_rtx (V8BFmode);
2150 10 : rtx op1 = lowpart_subreg (V8BFmode,
2151 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2152 16 : rtx op2 = lowpart_subreg (V8BFmode,
2153 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2154 11 :
2155 21 : emit_insn (gen_<insn>v8bf3 (op0, op1, op2));
2156 11 :
2157 10 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2158 10 : DONE;
2159 : })
2160 :
2161 : (define_expand "divv2hf3"
2162 : [(set (match_operand:V2HF 0 "register_operand")
2163 : (div:V2HF
2164 : (match_operand:V2HF 1 "nonimmediate_operand")
2165 : (match_operand:V2HF 2 "nonimmediate_operand")))]
2166 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2167 5 : {
2168 5 : rtx op2 = gen_reg_rtx (V8HFmode);
2169 5 : rtx op1 = gen_reg_rtx (V8HFmode);
2170 5 : rtx op0 = gen_reg_rtx (V8HFmode);
2171 :
2172 13 : emit_insn (gen_movd_v2hf_to_sse_reg (op2, operands[2],
2173 : force_reg (V8HFmode, CONST1_RTX (V8HFmode))));
2174 13 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
2175 13 : emit_insn (gen_divv8hf3 (op0, op1, op2));
2176 8 :
2177 5 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
2178 5 : DONE;
2179 : })
2180 :
2181 : (define_expand "<code><mode>3"
2182 : [(set (match_operand:VHF_32_64 0 "register_operand")
2183 : (smaxmin:VHF_32_64
2184 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2185 : (match_operand:VHF_32_64 2 "nonimmediate_operand")))]
2186 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2187 4 : {
2188 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2189 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2190 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2191 :
2192 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2193 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2194 0 :
2195 4 : emit_insn (gen_<code>v8hf3 (op0, op1, op2));
2196 0 :
2197 4 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2198 4 : DONE;
2199 : })
2200 :
2201 : (define_expand "<code><mode>3"
2202 : [(set (match_operand:VBF_32_64 0 "register_operand")
2203 : (smaxmin:VBF_32_64
2204 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2205 : (match_operand:VBF_32_64 2 "nonimmediate_operand")))]
2206 : "TARGET_AVX10_2"
2207 4 : {
2208 4 : rtx op0 = gen_reg_rtx (V8BFmode);
2209 4 : rtx op1 = lowpart_subreg (V8BFmode,
2210 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2211 4 : rtx op2 = lowpart_subreg (V8BFmode,
2212 3 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2213 :
2214 7 : emit_insn (gen_<code>v8bf3 (op0, op1, op2));
2215 3 :
2216 7 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2217 4 : DONE;
2218 : })
2219 :
2220 : (define_expand "sqrt<mode>2"
2221 : [(set (match_operand:VHF_32_64 0 "register_operand")
2222 : (sqrt:VHF_32_64
2223 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
2224 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2225 2 : {
2226 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2227 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2228 :
2229 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2230 2 : emit_insn (gen_sqrtv8hf2 (op0, op1));
2231 6 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2232 3 : DONE;
2233 4 : })
2234 5 :
2235 4 : (define_expand "sqrt<mode>2"
2236 1 : [(set (match_operand:VBF_32_64 0 "register_operand")
2237 : (sqrt:VBF_32_64 (match_operand:VBF_32_64 1 "vector_operand")))]
2238 : "TARGET_AVX10_2"
2239 0 : {
2240 0 : rtx op0 = gen_reg_rtx (V8BFmode);
2241 0 : rtx op1 = lowpart_subreg (V8BFmode,
2242 : force_reg (<MODE>mode, operands[1]), <MODE>mode);
2243 :
2244 0 : emit_insn (gen_sqrtv8bf2 (op0, op1));
2245 1 :
2246 1 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2247 1 : DONE;
2248 2 : })
2249 1 :
2250 1 : (define_mode_iterator VHBF_32_64
2251 18 : [V2BF (V4BF "TARGET_MMX_WITH_SSE")
2252 51 : V2HF (V4HF "TARGET_MMX_WITH_SSE")])
2253 :
2254 : (define_expand "<code><mode>2"
2255 67 : [(set (match_operand:VHBF_32_64 0 "register_operand")
2256 5007 : (absneg:VHBF_32_64
2257 2661 : (match_operand:VHBF_32_64 1 "register_operand")))]
2258 2736 : "TARGET_SSE"
2259 452 : "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
2260 4557 :
2261 2 : (define_insn_and_split "*mmx_<code><mode>"
2262 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2263 2 : (absneg:VHBF_32_64
2264 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x")))
2265 2 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2266 38 : "TARGET_SSE"
2267 : "#"
2268 4 : "&& reload_completed"
2269 : [(set (match_dup 0)
2270 21 : (<absneg_op>:<MODE> (match_dup 1) (match_dup 2)))]
2271 36 : {
2272 27 : if (!TARGET_AVX && operands_match_p (operands[0], operands[2]))
2273 36 : std::swap (operands[1], operands[2]);
2274 7 : }
2275 2 : [(set_attr "isa" "noavx,noavx,avx")])
2276 5 :
2277 9 : (define_insn_and_split "*mmx_nabs<mode>2"
2278 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x,x")
2279 : (neg:VHBF_32_64
2280 : (abs:VHBF_32_64
2281 9 : (match_operand:VHBF_32_64 1 "register_operand" "0,x,x"))))
2282 : (use (match_operand:VHBF_32_64 2 "register_operand" "x,0,x"))]
2283 0 : "TARGET_SSE"
2284 : "#"
2285 0 : "&& reload_completed"
2286 70 : [(set (match_dup 0)
2287 0 : (ior:<MODE> (match_dup 1) (match_dup 2)))])
2288 70 :
2289 70 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2290 70 : ;;
2291 0 : ;; Parallel half-precision floating point comparisons
2292 0 : ;;
2293 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2294 :
2295 : (define_expand "vec_cmpv4hfqi"
2296 0 : [(set (match_operand:QI 0 "register_operand")
2297 : (match_operator:QI 1 ""
2298 : [(match_operand:V4HF 2 "nonimmediate_operand")
2299 : (match_operand:V4HF 3 "nonimmediate_operand")]))]
2300 : "TARGET_MMX_WITH_SSE && TARGET_AVX512FP16 && TARGET_AVX512VL
2301 22 : && ix86_partial_vec_fp_math"
2302 17 : {
2303 39 : rtx ops[4];
2304 39 : ops[3] = gen_reg_rtx (V8HFmode);
2305 39 : ops[2] = gen_reg_rtx (V8HFmode);
2306 :
2307 17 : emit_insn (gen_movq_v4hf_to_sse (ops[3], operands[3]));
2308 17 : emit_insn (gen_movq_v4hf_to_sse (ops[2], operands[2]));
2309 17 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2310 17 : DONE;
2311 : })
2312 :
2313 : (define_expand "vcond_mask_<mode>v4hi"
2314 : [(set (match_operand:V4F_64 0 "register_operand")
2315 : (vec_merge:V4F_64
2316 : (match_operand:V4F_64 1 "register_operand")
2317 : (match_operand:V4F_64 2 "register_operand")
2318 : (match_operand:V4HI 3 "register_operand")))]
2319 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
2320 18 : {
2321 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2322 : operands[1], operands[2]);
2323 18 : DONE;
2324 5 : })
2325 :
2326 5 : (define_expand "vcond_mask_<mode>qi"
2327 5 : [(set (match_operand:V4FI_64 0 "register_operand")
2328 5 : (vec_merge:V4FI_64
2329 : (match_operand:V4FI_64 1 "register_operand")
2330 : (match_operand:V4FI_64 2 "register_operand")
2331 : (match_operand:QI 3 "register_operand")))]
2332 : "TARGET_MMX_WITH_SSE && TARGET_AVX512BW && TARGET_AVX512VL"
2333 22 : {
2334 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2335 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2336 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2337 44 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2338 : operands[2], operands[3]));
2339 44 : emit_move_insn (operands[0],
2340 22 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2341 44 : DONE;
2342 : })
2343 :
2344 : (define_expand "vec_cmpv2hfqi"
2345 : [(set (match_operand:QI 0 "register_operand")
2346 : (match_operator:QI 1 ""
2347 : [(match_operand:V2HF 2 "nonimmediate_operand")
2348 : (match_operand:V2HF 3 "nonimmediate_operand")]))]
2349 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2350 : && ix86_partial_vec_fp_math"
2351 17 : {
2352 17 : rtx ops[4];
2353 17 : ops[3] = gen_reg_rtx (V8HFmode);
2354 17 : ops[2] = gen_reg_rtx (V8HFmode);
2355 3 :
2356 17 : emit_insn (gen_movd_v2hf_to_sse (ops[3], operands[3]));
2357 20 : emit_insn (gen_movd_v2hf_to_sse (ops[2], operands[2]));
2358 20 : emit_insn (gen_vec_cmpv8hfqi (operands[0], operands[1], ops[2], ops[3]));
2359 20 : DONE;
2360 : })
2361 :
2362 : (define_expand "vcond_mask_<mode>v2hi"
2363 : [(set (match_operand:V2F_32 0 "register_operand")
2364 : (vec_merge:V2F_32
2365 : (match_operand:V2F_32 1 "register_operand")
2366 : (match_operand:V2F_32 2 "register_operand")
2367 : (match_operand:V2HI 3 "register_operand")))]
2368 : "TARGET_SSE4_1"
2369 18 : {
2370 18 : ix86_expand_sse_movcc (operands[0], operands[3],
2371 : operands[1], operands[2]);
2372 18 : DONE;
2373 1 : })
2374 :
2375 1 : (define_expand "vcond_mask_<mode>qi"
2376 1 : [(set (match_operand:V2FI_32 0 "register_operand")
2377 1 : (vec_merge:V2FI_32
2378 : (match_operand:V2FI_32 1 "register_operand")
2379 : (match_operand:V2FI_32 2 "register_operand")
2380 : (match_operand:QI 3 "register_operand")))]
2381 : "TARGET_AVX512BW && TARGET_AVX512VL"
2382 22 : {
2383 22 : rtx op0 = gen_reg_rtx (<mmxxmmmode>mode);
2384 22 : operands[1] = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
2385 22 : operands[2] = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
2386 28 : emit_insn (gen_vcond_mask_<mmxxmmmodelower>qi (op0, operands[1],
2387 : operands[2], operands[3]));
2388 28 : emit_move_insn (operands[0],
2389 6 : lowpart_subreg (<MODE>mode, op0, <mmxxmmmode>mode));
2390 28 : DONE;
2391 : })
2392 :
2393 : ;;This instruction does not generate floating point exceptions
2394 : (define_expand "vec_cmp<mode>qi"
2395 : [(set (match_operand:QI 0 "register_operand")
2396 : (match_operator:QI 1 ""
2397 : [(match_operand:VBF_32_64 2 "register_operand")
2398 : (match_operand:VBF_32_64 3 "nonimmediate_operand")]))]
2399 : "TARGET_AVX10_2"
2400 10 : {
2401 10 : rtx op2 = lowpart_subreg (V8BFmode,
2402 : force_reg (<MODE>mode, operands[2]), <MODE>mode);
2403 10 : rtx op3 = lowpart_subreg (V8BFmode,
2404 2 : force_reg (<MODE>mode, operands[3]), <MODE>mode);
2405 :
2406 12 : emit_insn (gen_vec_cmpv8bfqi (operands[0], operands[1], op2, op3));
2407 12 : DONE;
2408 2 : })
2409 :
2410 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2411 : ;;
2412 : ;; Parallel half-precision floating point rounding operations.
2413 : ;;
2414 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2415 :
2416 : (define_expand "btrunc<mode>2"
2417 : [(match_operand:VHF_32_64 0 "register_operand")
2418 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2419 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2420 : && ix86_partial_vec_fp_math
2421 1 : && !flag_trapping_math"
2422 2 : {
2423 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2424 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2425 1 :
2426 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2427 2 : emit_insn (gen_btruncv8hf2 (op0, op1));
2428 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2429 :
2430 2 : DONE;
2431 : })
2432 :
2433 : (define_expand "nearbyint<mode>2"
2434 : [(match_operand:VHF_32_64 0 "register_operand")
2435 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2436 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2437 : && ix86_partial_vec_fp_math"
2438 2 : {
2439 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2440 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2441 :
2442 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2443 3 : emit_insn (gen_nearbyintv8hf2 (op0, op1));
2444 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2445 1 :
2446 3 : DONE;
2447 1 : })
2448 :
2449 : (define_expand "rint<mode>2"
2450 : [(match_operand:VHF_32_64 0 "register_operand")
2451 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2452 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2453 : && ix86_partial_vec_fp_math"
2454 2 : {
2455 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2456 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2457 :
2458 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2459 3 : emit_insn (gen_rintv8hf2 (op0, op1));
2460 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2461 1 :
2462 3 : DONE;
2463 1 : })
2464 :
2465 : (define_expand "lrint<mode><mmxintvecmodelower>2"
2466 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2467 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2468 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2469 : && ix86_partial_vec_fp_math"
2470 0 : {
2471 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2472 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2473 :
2474 0 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2475 0 : emit_insn (gen_lrintv8hfv8hi2 (op0, op1));
2476 0 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2477 0 :
2478 0 : DONE;
2479 0 : })
2480 :
2481 : (define_expand "floor<mode>2"
2482 : [(match_operand:VHF_32_64 0 "register_operand")
2483 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2484 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2485 : && ix86_partial_vec_fp_math
2486 : && !flag_trapping_math"
2487 2 : {
2488 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2489 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2490 :
2491 3 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2492 2 : emit_insn (gen_floorv8hf2 (op0, op1));
2493 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2494 1 :
2495 3 : DONE;
2496 : })
2497 :
2498 : (define_expand "lfloor<mode><mmxintvecmodelower>2"
2499 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2500 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2501 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2502 : && ix86_partial_vec_fp_math
2503 : && !flag_trapping_math"
2504 0 : {
2505 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2506 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2507 :
2508 1 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2509 0 : emit_insn (gen_lfloorv8hfv8hi2 (op0, op1));
2510 1 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2511 1 :
2512 1 : DONE;
2513 : })
2514 :
2515 : (define_expand "ceil<mode>2"
2516 : [(match_operand:VHF_32_64 0 "register_operand")
2517 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2518 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2519 : && ix86_partial_vec_fp_math
2520 : && !flag_trapping_math"
2521 2 : {
2522 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2523 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2524 :
2525 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2526 2 : emit_insn (gen_ceilv8hf2 (op0, op1));
2527 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2528 0 :
2529 2 : DONE;
2530 : })
2531 :
2532 : (define_expand "lceil<mode><mmxintvecmodelower>2"
2533 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2534 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2535 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2536 : && ix86_partial_vec_fp_math
2537 : && !flag_trapping_math"
2538 0 : {
2539 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2540 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2541 :
2542 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2543 0 : emit_insn (gen_lceilv8hfv8hi2 (op0, op1));
2544 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2545 2 :
2546 2 : DONE;
2547 : })
2548 :
2549 : (define_expand "round<mode>2"
2550 : [(match_operand:VHF_32_64 0 "register_operand")
2551 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2552 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2553 : && ix86_partial_vec_fp_math
2554 : && !flag_trapping_math"
2555 2 : {
2556 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2557 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2558 :
2559 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2560 2 : emit_insn (gen_roundv8hf2 (op0, op1));
2561 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2562 0 :
2563 2 : DONE;
2564 : })
2565 :
2566 : (define_expand "lround<mode><mmxintvecmodelower>2"
2567 : [(match_operand:<mmxintvecmode> 0 "register_operand")
2568 : (match_operand:VHF_32_64 1 "nonimmediate_operand")]
2569 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2570 : && ix86_partial_vec_fp_math
2571 : && !flag_trapping_math"
2572 0 : {
2573 0 : rtx op1 = gen_reg_rtx (V8HFmode);
2574 0 : rtx op0 = gen_reg_rtx (V8HFmode);
2575 :
2576 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2577 0 : emit_insn (gen_lroundv8hfv8hi2 (op0, op1));
2578 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2579 2 :
2580 2 : DONE;
2581 : })
2582 :
2583 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2584 : ;;
2585 : ;; Parallel half-precision floating point logical operations
2586 : ;;
2587 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2588 :
2589 : (define_insn "*mmx_andnot<mode>3"
2590 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2591 : (and:VHBF_32_64
2592 : (not:VHBF_32_64
2593 0 : (match_operand:VHBF_32_64 1 "register_operand" "0,x"))
2594 : (match_operand:VHBF_32_64 2 "register_operand" "x,x")))]
2595 2 : "TARGET_SSE"
2596 0 : "@
2597 0 : andnps\t{%2, %0|%0, %2}
2598 : vandnps\t{%2, %1, %0|%0, %1, %2}"
2599 2 : [(set_attr "isa" "noavx,avx")
2600 2 : (set_attr "type" "sselog")
2601 : (set_attr "prefix" "orig,vex")
2602 2 : (set_attr "mode" "V4SF")])
2603 :
2604 : (define_insn "<code><mode>3"
2605 : [(set (match_operand:VHBF_32_64 0 "register_operand" "=x,x")
2606 : (any_logic:VHBF_32_64
2607 : (match_operand:VHBF_32_64 1 "register_operand" "%0,x")
2608 : (match_operand:VHBF_32_64 2 "register_operand" " x,x")))]
2609 45 : "TARGET_SSE"
2610 : "@
2611 : <logic>ps\t{%2, %0|%0, %2}
2612 : v<logic>ps\t{%2, %1, %0|%0, %1, %2}"
2613 56 : [(set_attr "isa" "noavx,avx")
2614 56 : (set_attr "type" "sselog,sselog")
2615 42 : (set_attr "prefix" "orig,vex")
2616 : (set_attr "mode" "V4SF")])
2617 42 :
2618 : (define_expand "copysign<mode>3"
2619 : [(set (match_dup 4)
2620 : (and:VHBF_32_64
2621 : (not:VHBF_32_64 (match_dup 3))
2622 : (match_operand:VHBF_32_64 1 "register_operand")))
2623 : (set (match_dup 5)
2624 : (and:VHBF_32_64 (match_dup 3)
2625 : (match_operand:VHBF_32_64 2 "register_operand")))
2626 : (set (match_operand:VHBF_32_64 0 "register_operand")
2627 : (ior:VHBF_32_64 (match_dup 4) (match_dup 5)))]
2628 : "TARGET_SSE"
2629 2 : {
2630 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2631 :
2632 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2633 2 : operands[5] = gen_reg_rtx (<MODE>mode);
2634 : })
2635 :
2636 : (define_expand "xorsign<mode>3"
2637 : [(set (match_dup 4)
2638 2 : (and:VHBF_32_64 (match_dup 3)
2639 : (match_operand:VHBF_32_64 2 "register_operand")))
2640 : (set (match_operand:VHBF_32_64 0 "register_operand")
2641 : (xor:VHBF_32_64 (match_dup 4)
2642 : (match_operand:VHBF_32_64 1 "register_operand")))]
2643 : "TARGET_SSE"
2644 4 : {
2645 2 : operands[3] = ix86_build_signbit_mask (<MODE>mode, true, false);
2646 :
2647 2 : operands[4] = gen_reg_rtx (<MODE>mode);
2648 : })
2649 2 :
2650 : (define_expand "signbit<mode>2"
2651 2 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
2652 4 : (lshiftrt:<mmxintvecmode>
2653 2 : (subreg:<mmxintvecmode>
2654 : (match_operand:VHBF_32_64 1 "register_operand") 0)
2655 : (match_dup 2)))]
2656 : "TARGET_SSE2"
2657 2 : {
2658 0 : operands[1] = force_reg (<MODE>mode, operands[1]);
2659 0 : operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode)-1);
2660 : })
2661 :
2662 4 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2663 : ;;
2664 4 : ;; Parallel half-precision FMA multiply/accumulate instructions.
2665 4 : ;;
2666 4 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2667 :
2668 0 : (define_expand "fma<mode>4"
2669 : [(set (match_operand:VHF_32_64 0 "register_operand")
2670 : (fma:VHF_32_64
2671 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2672 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2673 4 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2674 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2675 6 : {
2676 6 : rtx op3 = gen_reg_rtx (V8HFmode);
2677 6 : rtx op2 = gen_reg_rtx (V8HFmode);
2678 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2679 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2680 :
2681 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2682 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2683 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2684 :
2685 2 : emit_insn (gen_fmav8hf4 (op0, op1, op2, op3));
2686 :
2687 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2688 2 : DONE;
2689 : })
2690 :
2691 : (define_expand "fms<mode>4"
2692 : [(set (match_operand:VHF_32_64 0 "register_operand")
2693 : (fma:VHF_32_64
2694 : (match_operand:VHF_32_64 1 "nonimmediate_operand")
2695 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2696 : (neg:VHF_32_64
2697 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2698 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2699 2 : {
2700 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2701 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2702 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2703 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2704 2 :
2705 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2706 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2707 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2708 :
2709 2 : emit_insn (gen_fmsv8hf4 (op0, op1, op2, op3));
2710 :
2711 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2712 2 : DONE;
2713 : })
2714 :
2715 : (define_expand "fnma<mode>4"
2716 : [(set (match_operand:VHF_32_64 0 "register_operand")
2717 : (fma:VHF_32_64
2718 : (neg:VHF_32_64
2719 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2720 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2721 : (match_operand:VHF_32_64 3 "nonimmediate_operand")))]
2722 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2723 2 : {
2724 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2725 2 : rtx op2 = gen_reg_rtx (V8HFmode);
2726 4 : rtx op1 = gen_reg_rtx (V8HFmode);
2727 2 : rtx op0 = gen_reg_rtx (V8HFmode);
2728 2 :
2729 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2730 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2731 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2732 :
2733 2 : emit_insn (gen_fnmav8hf4 (op0, op1, op2, op3));
2734 :
2735 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2736 2 : DONE;
2737 : })
2738 :
2739 : (define_expand "fnms<mode>4"
2740 : [(set (match_operand:VHF_32_64 0 "register_operand" "=v,v,x")
2741 : (fma:VHF_32_64
2742 : (neg:VHF_32_64
2743 : (match_operand:VHF_32_64 1 "nonimmediate_operand"))
2744 : (match_operand:VHF_32_64 2 "nonimmediate_operand")
2745 : (neg:VHF_32_64
2746 : (match_operand:VHF_32_64 3 "nonimmediate_operand"))))]
2747 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2748 2 : {
2749 2 : rtx op3 = gen_reg_rtx (V8HFmode);
2750 4 : rtx op2 = gen_reg_rtx (V8HFmode);
2751 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2752 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2753 2 :
2754 4 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op3, operands[3]));
2755 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op2, operands[2]));
2756 2 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2757 :
2758 2 : emit_insn (gen_fnmsv8hf4 (op0, op1, op2, op3));
2759 :
2760 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8HFmode));
2761 2 : DONE;
2762 : })
2763 :
2764 : (define_expand "vec_fmaddsubv4hf4"
2765 : [(match_operand:V4HF 0 "register_operand")
2766 : (match_operand:V4HF 1 "nonimmediate_operand")
2767 : (match_operand:V4HF 2 "nonimmediate_operand")
2768 : (match_operand:V4HF 3 "nonimmediate_operand")]
2769 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2770 : && TARGET_MMX_WITH_SSE
2771 : && ix86_partial_vec_fp_math"
2772 1 : {
2773 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2774 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2775 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2776 3 : rtx op0 = gen_reg_rtx (V8HFmode);
2777 :
2778 3 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2779 3 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2780 3 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2781 :
2782 1 : emit_insn (gen_vec_fmaddsubv8hf4 (op0, op1, op2, op3));
2783 :
2784 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2785 1 : DONE;
2786 : })
2787 :
2788 : (define_expand "vec_fmsubaddv4hf4"
2789 : [(match_operand:V4HF 0 "register_operand")
2790 : (match_operand:V4HF 1 "nonimmediate_operand")
2791 : (match_operand:V4HF 2 "nonimmediate_operand")
2792 : (match_operand:V4HF 3 "nonimmediate_operand")]
2793 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2794 : && ix86_partial_vec_fp_math
2795 : && TARGET_MMX_WITH_SSE"
2796 1 : {
2797 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2798 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2799 2 : rtx op1 = gen_reg_rtx (V8HFmode);
2800 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2801 1 :
2802 2 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2803 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2804 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2805 :
2806 1 : emit_insn (gen_vec_fmsubaddv8hf4 (op0, op1, op2, op3));
2807 :
2808 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2809 1 : DONE;
2810 : })
2811 :
2812 : (define_expand "fma<mode>4"
2813 : [(set (match_operand:VBF_32_64 0 "register_operand")
2814 : (fma:VBF_32_64
2815 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2816 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2817 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2818 : "TARGET_AVX10_2"
2819 2 : {
2820 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2821 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2822 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2823 3 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2824 :
2825 3 : emit_insn (gen_fmav8bf4 (op0, op1, op2, op3));
2826 1 :
2827 3 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2828 2 : DONE;
2829 : })
2830 :
2831 : (define_expand "fms<mode>4"
2832 : [(set (match_operand:VBF_32_64 0 "register_operand")
2833 : (fma:VBF_32_64
2834 : (match_operand:VBF_32_64 1 "nonimmediate_operand")
2835 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2836 : (neg:VBF_32_64
2837 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2838 : "TARGET_AVX10_2"
2839 2 : {
2840 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2841 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2842 4 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2843 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2844 2 :
2845 4 : emit_insn (gen_fmsv8bf4 (op0, op1, op2, op3));
2846 2 :
2847 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2848 2 : DONE;
2849 : })
2850 :
2851 : (define_expand "fnma<mode>4"
2852 : [(set (match_operand:VBF_32_64 0 "register_operand")
2853 : (fma:VBF_32_64
2854 : (neg:VBF_32_64
2855 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2856 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2857 : (match_operand:VBF_32_64 3 "nonimmediate_operand")))]
2858 : "TARGET_AVX10_2"
2859 2 : {
2860 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2861 2 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2862 6 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2863 2 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2864 4 :
2865 6 : emit_insn (gen_fnmav8bf4 (op0, op1, op2, op3));
2866 4 :
2867 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2868 2 : DONE;
2869 : })
2870 :
2871 : (define_expand "fnms<mode>4"
2872 : [(set (match_operand:VBF_32_64 0 "register_operand")
2873 : (fma:VBF_32_64
2874 : (neg:VBF_32_64
2875 : (match_operand:VBF_32_64 1 "nonimmediate_operand"))
2876 : (match_operand:VBF_32_64 2 "nonimmediate_operand")
2877 : (neg:VBF_32_64
2878 : (match_operand:VBF_32_64 3 "nonimmediate_operand"))))]
2879 : "TARGET_AVX10_2"
2880 2 : {
2881 2 : rtx op0 = gen_reg_rtx (V8BFmode);
2882 6 : rtx op1 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[1]), <MODE>mode);
2883 2 : rtx op2 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[2]), <MODE>mode);
2884 6 : rtx op3 = lowpart_subreg (V8BFmode, force_reg (<MODE>mode, operands[3]), <MODE>mode);
2885 4 :
2886 6 : emit_insn (gen_fnmsv8bf4 (op0, op1, op2, op3));
2887 :
2888 2 : emit_move_insn (operands[0], lowpart_subreg (<MODE>mode, op0, V8BFmode));
2889 2 : DONE;
2890 : })
2891 :
2892 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2893 : ;;
2894 : ;; Parallel half-precision floating point complex type operations
2895 : ;;
2896 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2897 :
2898 : (define_expand "cmlav4hf4"
2899 : [(match_operand:V4HF 0 "register_operand")
2900 : (match_operand:V4HF 1 "vector_operand")
2901 : (match_operand:V4HF 2 "vector_operand")
2902 : (match_operand:V4HF 3 "vector_operand")]
2903 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2904 2 : && TARGET_MMX_WITH_SSE"
2905 1 : {
2906 3 : rtx op3 = gen_reg_rtx (V8HFmode);
2907 3 : rtx op2 = gen_reg_rtx (V8HFmode);
2908 3 : rtx op1 = gen_reg_rtx (V8HFmode);
2909 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2910 :
2911 1 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2912 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2913 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2914 :
2915 1 : emit_insn (gen_cmlav8hf4 (op0, op1, op2, op3));
2916 :
2917 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2918 1 : DONE;
2919 : })
2920 :
2921 : (define_expand "cmla_conjv4hf4"
2922 : [(match_operand:V4HF 0 "register_operand")
2923 : (match_operand:V4HF 1 "vector_operand")
2924 : (match_operand:V4HF 2 "vector_operand")
2925 : (match_operand:V4HF 3 "vector_operand")]
2926 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2927 : && TARGET_MMX_WITH_SSE"
2928 1 : {
2929 1 : rtx op3 = gen_reg_rtx (V8HFmode);
2930 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2931 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2932 4 : rtx op0 = gen_reg_rtx (V8HFmode);
2933 :
2934 4 : emit_insn (gen_movq_v4hf_to_sse (op3, operands[3]));
2935 4 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2936 4 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2937 :
2938 1 : emit_insn (gen_cmla_conjv8hf4 (op0, op1, op2, op3));
2939 :
2940 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2941 1 : DONE;
2942 : })
2943 :
2944 : (define_expand "cmulv4hf3"
2945 : [(match_operand:V4HF 0 "register_operand")
2946 : (match_operand:V4HF 1 "vector_operand")
2947 : (match_operand:V4HF 2 "vector_operand")]
2948 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2949 : && TARGET_MMX_WITH_SSE"
2950 1 : {
2951 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2952 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2953 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2954 :
2955 2 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2956 1 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2957 1 :
2958 2 : emit_insn (gen_cmulv8hf3 (op0, op1, op2));
2959 2 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2960 1 : DONE;
2961 : })
2962 :
2963 : (define_expand "cmul_conjv4hf3"
2964 : [(match_operand:V4HF 0 "register_operand")
2965 : (match_operand:V4HF 1 "vector_operand")
2966 : (match_operand:V4HF 2 "vector_operand")]
2967 : "TARGET_AVX512FP16 && TARGET_AVX512VL
2968 : && TARGET_MMX_WITH_SSE"
2969 1 : {
2970 1 : rtx op2 = gen_reg_rtx (V8HFmode);
2971 1 : rtx op1 = gen_reg_rtx (V8HFmode);
2972 1 : rtx op0 = gen_reg_rtx (V8HFmode);
2973 1 :
2974 1 : emit_insn (gen_movq_v4hf_to_sse (op2, operands[2]));
2975 2 : emit_insn (gen_movq_v4hf_to_sse (op1, operands[1]));
2976 1 :
2977 2 : emit_insn (gen_cmul_conjv8hf3 (op0, op1, op2));
2978 1 : emit_move_insn (operands[0], lowpart_subreg (V4HFmode, op0, V8HFmode));
2979 1 : DONE;
2980 : })
2981 :
2982 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2983 : ;;
2984 : ;; Parallel half-precision floating point conversion operations
2985 : ;;
2986 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2987 :
2988 : (define_expand "fix<fixunssuffix>_trunc<mode><mmxintvecmodelower>2"
2989 : [(set (match_operand:<mmxintvecmode> 0 "register_operand")
2990 : (any_fix:<mmxintvecmode>
2991 : (match_operand:VHF_32_64 1 "nonimmediate_operand")))]
2992 1 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
2993 8 : {
2994 9 : rtx op1 = gen_reg_rtx (V8HFmode);
2995 9 : rtx op0 = gen_reg_rtx (V8HImode);
2996 1 :
2997 8 : emit_insn (gen_mov<mov_to_sse_suffix>_<mode>_to_sse (op1, operands[1]));
2998 :
2999 8 : emit_insn (gen_fix<fixunssuffix>_truncv8hfv8hi2 (op0, op1));
3000 :
3001 8 : emit_move_insn (operands[0],
3002 : lowpart_subreg (<mmxintvecmode>mode, op0, V8HImode));
3003 8 : DONE;
3004 : })
3005 :
3006 : (define_expand "fix<fixunssuffix>_truncv2hfv2si2"
3007 : [(set (match_operand:V2SI 0 "register_operand")
3008 : (any_fix:V2SI
3009 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3010 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3011 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3012 2 : {
3013 2 : rtx op1 = gen_reg_rtx (V8HFmode);
3014 2 : rtx op0 = gen_reg_rtx (V4SImode);
3015 :
3016 8 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3017 :
3018 8 : emit_insn (gen_avx512fp16_fix<fixunssuffix>_truncv4si2 (op0, op1));
3019 6 :
3020 8 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
3021 2 : DONE;
3022 : })
3023 :
3024 : (define_expand "float<floatunssuffix><mmxintvecmodelower><mode>2"
3025 : [(set (match_operand:VHF_32_64 0 "register_operand")
3026 : (any_float:VHF_32_64
3027 : (match_operand:<mmxintvecmode> 1 "nonimmediate_operand")))]
3028 : "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
3029 8 : {
3030 8 : rtx op1 = gen_reg_rtx (V8HImode);
3031 8 : rtx op0 = gen_reg_rtx (V8HFmode);
3032 :
3033 8 : rtx (*gen_movd_sse) (rtx, rtx)
3034 4 : = gen_mov<mov_to_sse_suffix>_<mmxintvecmodelower>_to_sse;
3035 8 : emit_insn (gen_movd_sse (op1, operands[1]));
3036 4 :
3037 12 : emit_insn (gen_float<floatunssuffix>v8hiv8hf2 (op0, op1));
3038 4 :
3039 8 : emit_move_insn (operands[0],
3040 : lowpart_subreg (<MODE>mode, op0, V8HFmode));
3041 8 : DONE;
3042 : })
3043 :
3044 : (define_expand "float<floatunssuffix>v2siv2hf2"
3045 : [(set (match_operand:V2HF 0 "register_operand")
3046 : (any_float:V2HF
3047 : (match_operand:V2SI 1 "nonimmediate_operand")))]
3048 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3049 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3050 2 : {
3051 2 : rtx op1 = gen_reg_rtx (V4SImode);
3052 2 : rtx op0 = gen_reg_rtx (V8HFmode);
3053 :
3054 14 : emit_insn (gen_movq_v2si_to_sse (op1, operands[1]));
3055 4 :
3056 14 : emit_insn (gen_avx512fp16_float<floatunssuffix>v4siv4hf2 (op0, op1));
3057 16 :
3058 14 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3059 6 : DONE;
3060 : })
3061 :
3062 : (define_expand "extendv2hfv2sf2"
3063 : [(set (match_operand:V2SF 0 "register_operand")
3064 : (float_extend:V2SF
3065 : (match_operand:V2HF 1 "nonimmediate_operand")))]
3066 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3067 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3068 1 : {
3069 1 : rtx op1 = gen_reg_rtx (V8HFmode);
3070 1 : rtx op0 = gen_reg_rtx (V4SFmode);
3071 :
3072 89 : emit_insn (gen_movd_v2hf_to_sse (op1, operands[1]));
3073 :
3074 89 : emit_insn (gen_avx512fp16_float_extend_phv4sf2 (op0, op1));
3075 88 :
3076 89 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3077 1 : DONE;
3078 : })
3079 :
3080 : (define_expand "truncv2sfv2hf2"
3081 : [(set (match_operand:V2HF 0 "register_operand")
3082 : (float_truncate:V2HF
3083 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3084 : "TARGET_AVX512FP16 && TARGET_AVX512VL
3085 : && TARGET_MMX_WITH_SSE && ix86_partial_vec_fp_math"
3086 1 : {
3087 1 : rtx op1 = gen_reg_rtx (V4SFmode);
3088 1 : rtx op0 = gen_reg_rtx (V8HFmode);
3089 :
3090 1 : emit_insn (gen_movq_v2sf_to_sse (op1, operands[1]));
3091 0 :
3092 1 : emit_insn (gen_avx512fp16_truncv4sfv4hf2 (op0, op1));
3093 0 :
3094 1 : emit_move_insn (operands[0], lowpart_subreg (V2HFmode, op0, V8HFmode));
3095 1 : DONE;
3096 : })
3097 :
3098 : (define_expand "truncv2sfv2bf2"
3099 : [(set (match_operand:V2BF 0 "register_operand")
3100 : (float_truncate:V2BF
3101 : (match_operand:V2SF 1 "nonimmediate_operand")))]
3102 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE
3103 : && !HONOR_NANS (BFmode) && !flag_rounding_math
3104 : && (flag_unsafe_math_optimizations
3105 : || TARGET_AVXNECONVERT
3106 : || (TARGET_AVX512BF16 && TARGET_AVX512VL))"
3107 2 : {
3108 35 : rtx op1 = gen_reg_rtx (V4SFmode);
3109 2 : rtx op0 = gen_reg_rtx (V4BFmode);
3110 33 :
3111 35 : emit_move_insn (op1, lowpart_subreg (V4SFmode,
3112 33 : force_reg (V2SFmode, operands[1]),
3113 : V2SFmode));
3114 2 : emit_insn (gen_truncv4sfv4bf2 (op0, op1));
3115 :
3116 2 : emit_move_insn (operands[0], lowpart_subreg (V2BFmode, op0, V4BFmode));
3117 2 : DONE;
3118 : })
3119 :
3120 : (define_expand "extendv2bfv2sf2"
3121 : [(set (match_operand:V2SF 0 "register_operand")
3122 : (float_extend:V2SF
3123 : (match_operand:V2BF 1 "nonimmediate_operand")))]
3124 : "TARGET_SSE2 && TARGET_MMX_WITH_SSE && !HONOR_NANS (BFmode)"
3125 2 : {
3126 2 : rtx op0 = gen_reg_rtx (V4SFmode);
3127 2 : rtx op1 = gen_reg_rtx (V4BFmode);
3128 :
3129 2 : emit_move_insn (op1, lowpart_subreg (V4BFmode,
3130 33 : force_reg (V2BFmode, operands[1]),
3131 : V2BFmode));
3132 35 : emit_insn (gen_extendv4bfv4sf2 (op0, op1));
3133 33 :
3134 35 : emit_move_insn (operands[0], lowpart_subreg (V2SFmode, op0, V4SFmode));
3135 2 : DONE;
3136 : })
3137 :
3138 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3139 : ;;
3140 : ;; Parallel integral arithmetic
3141 : ;;
3142 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3143 :
3144 : (define_expand "neg<mode>2"
3145 : [(set (match_operand:MMXMODEI 0 "register_operand")
3146 : (minus:MMXMODEI
3147 : (match_dup 2)
3148 40 : (match_operand:MMXMODEI 1 "register_operand")))]
3149 : "TARGET_MMX_WITH_SSE"
3150 133 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3151 40 :
3152 40 : (define_expand "neg<mode>2"
3153 : [(set (match_operand:VI_32 0 "register_operand")
3154 93 : (minus:VI_32
3155 : (match_dup 2)
3156 : (match_operand:VI_32 1 "register_operand")))]
3157 : "TARGET_SSE2"
3158 100 : "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
3159 :
3160 : (define_insn "negv2qi2"
3161 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,&Yw")
3162 7 : (neg:V2QI
3163 102 : (match_operand:V2QI 1 "register_operand" "0,Yw")))
3164 : (clobber (reg:CC FLAGS_REG))]
3165 148 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3166 112 : "#"
3167 108 : [(set_attr "isa" "*,sse2")
3168 6 : (set_attr "type" "multi")
3169 : (set_attr "mode" "QI,TI")
3170 : (set (attr "enabled")
3171 46 : (cond [(and (eq_attr "alternative" "0")
3172 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3173 37173 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3174 37174 : (symbol_ref "false")
3175 47 : ]
3176 5801 : (const_string "*")))])
3177 5802 :
3178 1 : (define_split
3179 : [(set (match_operand:V2QI 0 "general_reg_operand")
3180 : (neg:V2QI
3181 : (match_operand:V2QI 1 "general_reg_operand")))
3182 : (clobber (reg:CC FLAGS_REG))]
3183 4 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3184 4 : && reload_completed"
3185 4 : [(parallel
3186 4 : [(set (strict_low_part (match_dup 0))
3187 0 : (neg:QI (match_dup 1)))
3188 4 : (clobber (reg:CC FLAGS_REG))])
3189 : (parallel
3190 : [(set (zero_extract:HI (match_dup 2) (const_int 8) (const_int 8))
3191 : (subreg:HI
3192 : (neg:QI
3193 : (subreg:QI
3194 : (zero_extract:HI (match_dup 3)
3195 : (const_int 8)
3196 : (const_int 8)) 0)) 0))
3197 : (clobber (reg:CC FLAGS_REG))])]
3198 4 : {
3199 4 : operands[3] = lowpart_subreg (HImode, operands[1], V2QImode);
3200 4 : operands[2] = lowpart_subreg (HImode, operands[0], V2QImode);
3201 4 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3202 4 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3203 : })
3204 :
3205 : (define_split
3206 4 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3207 : (neg:V2QI
3208 : (match_operand:V2QI 1 "sse_reg_operand")))
3209 : (clobber (reg:CC FLAGS_REG))]
3210 0 : "TARGET_SSE2 && reload_completed"
3211 4 : [(set (match_dup 0) (match_dup 2))
3212 0 : (set (match_dup 0)
3213 : (minus:V16QI (match_dup 0) (match_dup 1)))]
3214 3497 : {
3215 3501 : operands[2] = CONST0_RTX (V16QImode);
3216 0 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3217 52 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3218 104 : })
3219 :
3220 1124 : (define_expand "mmx_<insn><mode>3"
3221 0 : [(set (match_operand:MMXMODEI8 0 "register_operand")
3222 1124 : (plusminus:MMXMODEI8
3223 1124 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand")
3224 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))]
3225 0 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3226 254 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3227 1124 :
3228 : (define_expand "<insn><mode>3"
3229 : [(set (match_operand:MMXMODEI 0 "register_operand")
3230 7483 : (plusminus:MMXMODEI
3231 : (match_operand:MMXMODEI 1 "register_operand")
3232 7262 : (match_operand:MMXMODEI 2 "register_operand")))]
3233 7229 : "TARGET_MMX_WITH_SSE")
3234 287 :
3235 33 : (define_insn "*mmx_<insn><mode>3"
3236 33 : [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,<Yv_Yw>")
3237 7229 : (plusminus:MMXMODEI8
3238 : (match_operand:MMXMODEI8 1 "register_mmxmem_operand"
3239 2440 : "<comm>0,0,<Yv_Yw>")
3240 233 : (match_operand:MMXMODEI8 2 "register_mmxmem_operand"
3241 2440 : "ym,x,<Yv_Yw>")))]
3242 14184 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3243 126607 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3244 55335 : "@
3245 33 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3246 2473 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3247 165298 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3248 165298 : [(set_attr "isa" "*,sse2_noavx,avx")
3249 165298 : (set_attr "mmx_isa" "native,*,*")
3250 : (set_attr "type" "mmxadd,sseadd,sseadd")
3251 280859 : (set_attr "mode" "DI,TI,TI")])
3252 :
3253 142 : (define_insn "<insn><mode>3"
3254 142 : [(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
3255 142 : (plusminus:VI_32
3256 : (match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
3257 : (match_operand:VI_32 2 "register_operand" "x,Yw")))]
3258 10323 : "TARGET_SSE2"
3259 : "@
3260 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3261 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3262 13575 : [(set_attr "isa" "noavx,avx")
3263 1765 : (set_attr "type" "sseadd")
3264 11810 : (set_attr "mode" "TI")])
3265 1765 :
3266 13575 : (define_insn "<insn>v2qi3"
3267 : [(set (match_operand:V2QI 0 "register_operand" "=?Q,x,Yw")
3268 1765 : (plusminus:V2QI
3269 : (match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
3270 : (match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
3271 : (clobber (reg:CC FLAGS_REG))]
3272 2300 : "!TARGET_PARTIAL_REG_STALL || optimize_size || TARGET_SSE2"
3273 : "#"
3274 585 : [(set_attr "isa" "*,sse2_noavx,avx")
3275 585 : (set_attr "type" "multi,sseadd,sseadd")
3276 : (set_attr "mode" "QI,TI,TI")
3277 : (set (attr "enabled")
3278 : (cond [(and (eq_attr "alternative" "0")
3279 7467970 : (and (match_test "TARGET_PARTIAL_REG_STALL")
3280 7694 : (not (match_test "optimize_function_for_size_p (cfun)"))))
3281 7723 : (symbol_ref "false")
3282 176 : ]
3283 120565 : (const_string "*")))])
3284 7564 :
3285 17 : (define_split
3286 7564 : [(set (match_operand:V2QI 0 "general_reg_operand")
3287 : (plusminus:V2QI
3288 1871 : (match_operand:V2QI 1 "general_reg_operand")
3289 1871 : (match_operand:V2QI 2 "general_reg_operand")))
3290 1871 : (clobber (reg:CC FLAGS_REG))]
3291 2015 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
3292 198 : && reload_completed"
3293 3895 : [(parallel
3294 974 : [(set (strict_low_part (match_dup 0))
3295 50 : (plusminus:QI (match_dup 1) (match_dup 2)))
3296 50 : (clobber (reg:CC FLAGS_REG))])
3297 974 : (parallel
3298 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
3299 : (subreg:HI
3300 : (plusminus:QI
3301 : (subreg:QI
3302 : (zero_extract:HI (match_dup 4)
3303 : (const_int 8)
3304 : (const_int 8)) 0)
3305 : (subreg:QI
3306 : (zero_extract:HI (match_dup 5)
3307 : (const_int 8)
3308 : (const_int 8)) 0)) 0))
3309 : (clobber (reg:CC FLAGS_REG))])]
3310 183 : {
3311 183 : operands[5] = lowpart_subreg (HImode, operands[2], V2QImode);
3312 183 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
3313 183 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
3314 183 : operands[2] = lowpart_subreg (QImode, operands[2], V2QImode);
3315 183 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
3316 183 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
3317 : })
3318 :
3319 : (define_split
3320 183 : [(set (match_operand:V2QI 0 "sse_reg_operand")
3321 : (plusminus:V2QI
3322 : (match_operand:V2QI 1 "sse_reg_operand")
3323 : (match_operand:V2QI 2 "sse_reg_operand")))
3324 : (clobber (reg:CC FLAGS_REG))]
3325 50 : "TARGET_SSE2 && reload_completed"
3326 924 : [(set (match_dup 0)
3327 50 : (plusminus:V16QI (match_dup 1) (match_dup 2)))]
3328 50 : {
3329 2852651 : operands[2] = lowpart_subreg (V16QImode, operands[2], V2QImode);
3330 1440530 : operands[1] = lowpart_subreg (V16QImode, operands[1], V2QImode);
3331 1412354 : operands[0] = lowpart_subreg (V16QImode, operands[0], V2QImode);
3332 1412304 : })
3333 81 :
3334 81 : (define_expand "mmx_<insn><mode>3"
3335 1046 : [(set (match_operand:MMXMODE12 0 "register_operand")
3336 24 : (sat_plusminus:MMXMODE12
3337 1077 : (match_operand:MMXMODE12 1 "register_mmxmem_operand")
3338 960 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))]
3339 1010 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3340 208 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
3341 :
3342 : (define_expand "<insn><mode>3"
3343 : [(set (match_operand:MMXMODE12 0 "register_operand")
3344 277 : (sat_plusminus:MMXMODE12
3345 : (match_operand:MMXMODE12 1 "register_operand")
3346 1 : (match_operand:MMXMODE12 2 "register_operand")))]
3347 1 : "TARGET_MMX_WITH_SSE")
3348 276 :
3349 : (define_insn "*mmx_<insn><mode>3"
3350 : [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yw")
3351 1 : (sat_plusminus:MMXMODE12
3352 : (match_operand:MMXMODE12 1 "register_mmxmem_operand" "<comm>0,0,Yw")
3353 98 : (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yw")))]
3354 232 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3355 1812 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
3356 459 : "@
3357 68 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3358 361 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3359 1368 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3360 1031 : [(set_attr "isa" "*,sse2_noavx,avx")
3361 26 : (set_attr "mmx_isa" "native,*,*")
3362 : (set_attr "type" "mmxadd,sseadd,sseadd")
3363 361 : (set_attr "mode" "DI,TI,TI")])
3364 :
3365 427 : (define_insn "<insn><mode>3"
3366 39 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
3367 427 : (sat_plusminus:VI_16_32
3368 492 : (match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
3369 465 : (match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
3370 218 : "TARGET_SSE2"
3371 26 : "@
3372 27 : p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
3373 17 : vp<plusminus_mnemonic><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3374 445 : [(set_attr "isa" "noavx,avx")
3375 445 : (set_attr "type" "sseadd")
3376 : (set_attr "mode" "TI")])
3377 34 :
3378 337 : (define_insn "mulv2si3"
3379 16220 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
3380 14762 : (mult:V2SI
3381 14427 : (match_operand:V2SI 1 "register_operand" "%0,0,v")
3382 1462 : (match_operand:V2SI 2 "register_operand" "Yr,*x,v")))]
3383 7488 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3384 : "@
3385 346853 : pmulld\t{%2, %0|%0, %2}
3386 345796 : pmulld\t{%2, %0|%0, %2}
3387 351256 : vpmulld\t{%2, %1, %0|%0, %1, %2}"
3388 6514 : [(set_attr "isa" "noavx,noavx,avx")
3389 : (set_attr "type" "sseimul")
3390 9656 : (set_attr "prefix_extra" "1")
3391 196 : (set_attr "prefix" "orig,orig,vex")
3392 536 : (set_attr "btver2_decode" "vector")
3393 0 : (set_attr "mode" "TI")])
3394 0 :
3395 0 : (define_expand "mmx_mulv4hi3"
3396 : [(set (match_operand:V4HI 0 "register_operand")
3397 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand")
3398 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3399 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3400 33 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3401 :
3402 : (define_expand "mulv4hi3"
3403 : [(set (match_operand:V4HI 0 "register_operand")
3404 33 : (mult:V4HI (match_operand:V4HI 1 "register_operand")
3405 : (match_operand:V4HI 2 "register_operand")))]
3406 : "TARGET_MMX_WITH_SSE")
3407 :
3408 33 : (define_insn "*mmx_mulv4hi3"
3409 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3410 : (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3411 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3412 4000 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3413 4022 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3414 1460 : "@
3415 22 : pmullw\t{%2, %0|%0, %2}
3416 22 : pmullw\t{%2, %0|%0, %2}
3417 11256 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3418 11234 : [(set_attr "isa" "*,sse2_noavx,avx")
3419 : (set_attr "mmx_isa" "native,*,*")
3420 11234 : (set_attr "type" "mmxmul,ssemul,ssemul")
3421 : (set_attr "mode" "DI,TI,TI")])
3422 :
3423 : (define_insn "mulv2hi3"
3424 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3425 : (mult:V2HI (match_operand:V2HI 1 "register_operand" "%0,Yw")
3426 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3427 9325 : "TARGET_SSE2"
3428 : "@
3429 : pmullw\t{%2, %0|%0, %2}
3430 : vpmullw\t{%2, %1, %0|%0, %1, %2}"
3431 : [(set_attr "isa" "noavx,avx")
3432 : (set_attr "type" "ssemul")
3433 : (set_attr "mode" "TI")])
3434 :
3435 387553 : (define_expand "mulv8qi3"
3436 387553 : [(set (match_operand:V8QI 0 "register_operand")
3437 387553 : (mult:V8QI (match_operand:V8QI 1 "register_operand")
3438 : (match_operand:V8QI 2 "register_operand")))]
3439 210181 : "TARGET_MMX_WITH_SSE"
3440 210540 : {
3441 359 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3442 39424 : DONE;
3443 39065 : })
3444 39065 :
3445 39065 : (define_expand "mulv4qi3"
3446 39065 : [(set (match_operand:V4QI 0 "register_operand")
3447 39065 : (mult:V4QI (match_operand:V4QI 1 "register_operand")
3448 : (match_operand:V4QI 2 "register_operand")))]
3449 21241 : "TARGET_SSE2"
3450 22179 : {
3451 22179 : ix86_expand_vecop_qihi_partial (MULT, operands[0], operands[1], operands[2]);
3452 938 : DONE;
3453 : })
3454 41456 :
3455 : (define_expand "mmx_smulv4hi3_highpart"
3456 11 : [(set (match_operand:V4HI 0 "register_operand")
3457 : (truncate:V4HI
3458 11 : (lshiftrt:V4SI
3459 11 : (mult:V4SI
3460 : (sign_extend:V4SI
3461 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3462 : (sign_extend:V4SI
3463 11 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3464 : (const_int 16))))]
3465 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3466 56 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3467 :
3468 38 : (define_insn "*mmx_smulv4hi3_highpart"
3469 22 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3470 72 : (truncate:V4HI
3471 16 : (lshiftrt:V4SI
3472 : (mult:V4SI
3473 : (sign_extend:V4SI
3474 16 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3475 34 : (sign_extend:V4SI
3476 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3477 : (const_int 16))))]
3478 16 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3479 196 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3480 22 : "@
3481 : pmulhw\t{%2, %0|%0, %2}
3482 22 : pmulhw\t{%2, %0|%0, %2}
3483 27 : vpmulhw\t{%2, %1, %0|%0, %1, %2}"
3484 27 : [(set_attr "isa" "*,sse2_noavx,avx")
3485 : (set_attr "mmx_isa" "native,*,*")
3486 : (set_attr "type" "mmxmul,ssemul,ssemul")
3487 : (set_attr "mode" "DI,TI,TI")])
3488 :
3489 : (define_expand "mmx_umulv4hi3_highpart"
3490 : [(set (match_operand:V4HI 0 "register_operand")
3491 : (truncate:V4HI
3492 : (lshiftrt:V4SI
3493 : (mult:V4SI
3494 : (zero_extend:V4SI
3495 : (match_operand:V4HI 1 "register_mmxmem_operand"))
3496 : (zero_extend:V4SI
3497 : (match_operand:V4HI 2 "register_mmxmem_operand")))
3498 : (const_int 16))))]
3499 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3500 : && (TARGET_SSE || TARGET_3DNOW_A)"
3501 22 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3502 :
3503 : (define_insn "*mmx_umulv4hi3_highpart"
3504 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3505 22 : (truncate:V4HI
3506 : (lshiftrt:V4SI
3507 : (mult:V4SI
3508 : (zero_extend:V4SI
3509 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
3510 22 : (zero_extend:V4SI
3511 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
3512 : (const_int 16))))]
3513 17 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3514 247 : && (TARGET_SSE || TARGET_3DNOW_A)
3515 248 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3516 0 : "@
3517 1 : pmulhuw\t{%2, %0|%0, %2}
3518 1 : pmulhuw\t{%2, %0|%0, %2}
3519 5 : vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
3520 5 : [(set_attr "isa" "*,sse2_noavx,avx")
3521 : (set_attr "mmx_isa" "native,*,*")
3522 1 : (set_attr "type" "mmxmul,ssemul,ssemul")
3523 : (set_attr "mode" "DI,TI,TI")])
3524 :
3525 : (define_expand "<s>mulv4hi3_highpart"
3526 : [(set (match_operand:V4HI 0 "register_operand")
3527 17 : (truncate:V4HI
3528 : (lshiftrt:V4SI
3529 17 : (mult:V4SI
3530 17 : (any_extend:V4SI
3531 : (match_operand:V4HI 1 "register_operand"))
3532 : (any_extend:V4SI
3533 17 : (match_operand:V4HI 2 "register_operand")))
3534 : (const_int 16))))]
3535 : "TARGET_MMX_WITH_SSE")
3536 :
3537 : (define_insn "<s>mulv2hi3_highpart"
3538 1121 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3539 : (truncate:V2HI
3540 1121 : (lshiftrt:V2SI
3541 1121 : (mult:V2SI
3542 : (any_extend:V2SI
3543 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
3544 : (any_extend:V2SI
3545 1121 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
3546 : (const_int 16))))]
3547 10 : "TARGET_SSE2"
3548 : "@
3549 : pmulh<u>w\t{%2, %0|%0, %2}
3550 43 : vpmulh<u>w\t{%2, %1, %0|%0, %1, %2}"
3551 : [(set_attr "isa" "noavx,avx")
3552 43 : (set_attr "type" "ssemul")
3553 43 : (set_attr "mode" "TI")])
3554 43 :
3555 3600 : (define_expand "mmx_pmaddwd"
3556 3600 : [(set (match_operand:V2SI 0 "register_operand")
3557 : (plus:V2SI
3558 : (mult:V2SI
3559 2442 : (sign_extend:V2SI
3560 494 : (vec_select:V2HI
3561 2195 : (match_operand:V4HI 1 "register_mmxmem_operand")
3562 : (parallel [(const_int 0) (const_int 2)])))
3563 94 : (sign_extend:V2SI
3564 94 : (vec_select:V2HI
3565 : (match_operand:V4HI 2 "register_mmxmem_operand")
3566 94 : (parallel [(const_int 0) (const_int 2)]))))
3567 94 : (mult:V2SI
3568 94 : (sign_extend:V2SI
3569 : (vec_select:V2HI (match_dup 1)
3570 94 : (parallel [(const_int 1) (const_int 3)])))
3571 94 : (sign_extend:V2SI
3572 94 : (vec_select:V2HI (match_dup 2)
3573 : (parallel [(const_int 1) (const_int 3)]))))))]
3574 94 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3575 128 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3576 94 :
3577 94 : (define_insn "*mmx_pmaddwd"
3578 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yw")
3579 128 : (plus:V2SI
3580 94 : (mult:V2SI
3581 94 : (sign_extend:V2SI
3582 : (vec_select:V2HI
3583 94 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3584 94 : (parallel [(const_int 0) (const_int 2)])))
3585 94 : (sign_extend:V2SI
3586 : (vec_select:V2HI
3587 94 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")
3588 94 : (parallel [(const_int 0) (const_int 2)]))))
3589 94 : (mult:V2SI
3590 34 : (sign_extend:V2SI
3591 94 : (vec_select:V2HI (match_dup 1)
3592 94 : (parallel [(const_int 1) (const_int 3)])))
3593 94 : (sign_extend:V2SI
3594 94 : (vec_select:V2HI (match_dup 2)
3595 346 : (parallel [(const_int 1) (const_int 3)]))))))]
3596 275 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3597 527 : && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3598 433 : "@
3599 7 : pmaddwd\t{%2, %0|%0, %2}
3600 87 : pmaddwd\t{%2, %0|%0, %2}
3601 87 : vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
3602 339 : [(set_attr "isa" "*,sse2_noavx,avx")
3603 : (set_attr "mmx_isa" "native,*,*")
3604 87 : (set_attr "type" "mmxmul,sseiadd,sseiadd")
3605 1595358 : (set_attr "c86_attr" "madd")
3606 1595358 : (set_attr "mode" "DI,TI,TI")])
3607 1595445 :
3608 1595283 : (define_expand "mmx_pmulhrwv4hi3"
3609 1595271 : [(set (match_operand:V4HI 0 "register_operand")
3610 1595283 : (truncate:V4HI
3611 1595271 : (lshiftrt:V4SI
3612 12 : (plus:V4SI
3613 1200345 : (mult:V4SI
3614 1200345 : (sign_extend:V4SI
3615 1200345 : (match_operand:V4HI 1 "nonimmediate_operand"))
3616 1200345 : (sign_extend:V4SI
3617 1200345 : (match_operand:V4HI 2 "nonimmediate_operand")))
3618 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3619 1069236 : (const_int 32768) (const_int 32768)]))
3620 1069236 : (const_int 16))))]
3621 1069236 : "TARGET_3DNOW"
3622 1069250 : "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
3623 1069236 :
3624 1069236 : (define_insn "*mmx_pmulhrwv4hi3"
3625 1069236 : [(set (match_operand:V4HI 0 "register_operand" "=y")
3626 1069250 : (truncate:V4HI
3627 1069236 : (lshiftrt:V4SI
3628 1069236 : (plus:V4SI
3629 1069236 : (mult:V4SI
3630 1069236 : (sign_extend:V4SI
3631 1069236 : (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
3632 1069236 : (sign_extend:V4SI
3633 : (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
3634 4110 : (const_vector:V4SI [(const_int 32768) (const_int 32768)
3635 4096 : (const_int 32768) (const_int 32768)]))
3636 : (const_int 16))))]
3637 4183 : "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
3638 8 : "pmulhrw\t{%2, %0|%0, %2}"
3639 : [(set_attr "type" "mmxmul")
3640 237 : (set_attr "prefix_extra" "1")
3641 1528 : (set_attr "mode" "DI")])
3642 1765 :
3643 1528 : (define_expand "sse2_umulv1siv1di3"
3644 237 : [(set (match_operand:V1DI 0 "register_operand")
3645 1528 : (mult:V1DI
3646 1528 : (zero_extend:V1DI
3647 : (vec_select:V1SI
3648 1492 : (match_operand:V2SI 1 "register_mmxmem_operand")
3649 1492 : (parallel [(const_int 0)])))
3650 1492 : (zero_extend:V1DI
3651 : (vec_select:V1SI
3652 1492 : (match_operand:V2SI 2 "register_mmxmem_operand")
3653 1492 : (parallel [(const_int 0)])))))]
3654 1492 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2"
3655 1504 : "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
3656 1492 :
3657 : (define_insn "*sse2_umulv1siv1di3"
3658 419 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv")
3659 431 : (mult:V1DI
3660 : (zero_extend:V1DI
3661 277 : (vec_select:V1SI
3662 : (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv")
3663 : (parallel [(const_int 0)])))
3664 419 : (zero_extend:V1DI
3665 12 : (vec_select:V1SI
3666 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
3667 : (parallel [(const_int 0)])))))]
3668 65 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3669 65 : && TARGET_SSE2
3670 89 : && ix86_binary_operator_ok (MULT, V2SImode, operands)"
3671 1 : "@
3672 24 : pmuludq\t{%2, %0|%0, %2}
3673 24 : pmuludq\t{%2, %0|%0, %2}
3674 : vpmuludq\t{%2, %1, %0|%0, %1, %2}"
3675 : [(set_attr "isa" "*,sse2_noavx,avx")
3676 24 : (set_attr "mmx_isa" "native,*,*")
3677 : (set_attr "type" "mmxmul,ssemul,ssemul")
3678 92834 : (set_attr "mode" "DI,TI,TI")])
3679 92834 :
3680 92834 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3681 262 : ;;
3682 12995 : ;; Parallel integral shifts
3683 13257 : ;;
3684 13257 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3685 12995 :
3686 12995 : (define_insn "<code><mode>3"
3687 : [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv")
3688 1807 : (smaxmin:MMXMODE14
3689 1545 : (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv")
3690 : (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))]
3691 410 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3692 : "@
3693 1451 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3694 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3695 573 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3696 74 : [(set_attr "isa" "noavx,noavx,avx")
3697 32 : (set_attr "type" "sseiadd")
3698 : (set_attr "prefix_extra" "1")
3699 : (set_attr "prefix" "orig,orig,vex")
3700 : (set_attr "mode" "TI")])
3701 :
3702 : (define_expand "mmx_<code>v4hi3"
3703 : [(set (match_operand:V4HI 0 "register_operand")
3704 : (smaxmin:V4HI
3705 : (match_operand:V4HI 1 "register_mmxmem_operand")
3706 : (match_operand:V4HI 2 "register_mmxmem_operand")))]
3707 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3708 : && (TARGET_SSE || TARGET_3DNOW_A)"
3709 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
3710 :
3711 : (define_insn "*mmx_<code>v4hi3"
3712 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
3713 44 : (smaxmin:V4HI
3714 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw")
3715 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3716 109 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3717 543 : && (TARGET_SSE || TARGET_3DNOW_A)
3718 998 : && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
3719 : "@
3720 : p<maxmin_int>w\t{%2, %0|%0, %2}
3721 : p<maxmin_int>w\t{%2, %0|%0, %2}
3722 169 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3723 319 : [(set_attr "isa" "*,sse2_noavx,avx")
3724 63 : (set_attr "mmx_isa" "native,*,*")
3725 276 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3726 0 : (set_attr "mode" "DI,TI,TI")])
3727 213 :
3728 : (define_expand "<code>v4hi3"
3729 63 : [(set (match_operand:V4HI 0 "register_operand")
3730 : (smaxmin:V4HI
3731 : (match_operand:V4HI 1 "register_operand")
3732 : (match_operand:V4HI 2 "register_operand")))]
3733 : "TARGET_MMX_WITH_SSE")
3734 317 :
3735 : (define_insn "<code><mode>3"
3736 317 : [(set (match_operand:VI1_16_32 0 "register_operand" "=Yr,*x,Yv")
3737 317 : (smaxmin:VI1_16_32
3738 : (match_operand:VI1_16_32 1 "register_operand" "%0,0,Yv")
3739 : (match_operand:VI1_16_32 2 "register_operand" "Yr,*x,Yv")))]
3740 106 : "TARGET_SSE4_1"
3741 317 : "@
3742 : p<maxmin_int>b\t{%2, %0|%0, %2}
3743 : p<maxmin_int>b\t{%2, %0|%0, %2}
3744 184 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3745 10 : [(set_attr "isa" "noavx,noavx,avx")
3746 18 : (set_attr "type" "sseiadd")
3747 : (set_attr "prefix_extra" "1")
3748 18 : (set_attr "prefix" "orig,orig,vex")
3749 18 : (set_attr "mode" "TI")])
3750 18 :
3751 : (define_insn "<code>v2hi3"
3752 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3753 : (smaxmin:V2HI
3754 : (match_operand:V2HI 1 "register_operand" "%0,Yw")
3755 : (match_operand:V2HI 2 "register_operand" "x,Yw")))]
3756 174 : "TARGET_SSE2"
3757 : "@
3758 : p<maxmin_int>w\t{%2, %0|%0, %2}
3759 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3760 : [(set_attr "isa" "noavx,avx")
3761 : (set_attr "type" "sseiadd")
3762 : (set_attr "mode" "TI")])
3763 :
3764 : (define_insn "<code><mode>3"
3765 198888 : [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv")
3766 198888 : (umaxmin:MMXMODE24
3767 109034 : (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv")
3768 1652 : (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))]
3769 1878 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
3770 : "@
3771 103867 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3772 103867 : p<maxmin_int><mmxvecsize>\t{%2, %0|%0, %2}
3773 104147 : vp<maxmin_int><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3774 280 : [(set_attr "isa" "noavx,noavx,avx")
3775 : (set_attr "type" "sseiadd")
3776 : (set_attr "prefix_extra" "1")
3777 222860 : (set_attr "prefix" "orig,orig,vex")
3778 222860 : (set_attr "mode" "TI")])
3779 222860 :
3780 : (define_expand "mmx_<code>v8qi3"
3781 : [(set (match_operand:V8QI 0 "register_operand")
3782 : (umaxmin:V8QI
3783 4168028 : (match_operand:V8QI 1 "register_mmxmem_operand")
3784 4168028 : (match_operand:V8QI 2 "register_mmxmem_operand")))]
3785 4168028 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3786 : && (TARGET_SSE || TARGET_3DNOW_A)"
3787 44 : "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
3788 :
3789 1115922 : (define_insn "*mmx_<code>v8qi3"
3790 1115922 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
3791 1115966 : (umaxmin:V8QI
3792 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
3793 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))]
3794 280 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
3795 4129819 : && (TARGET_SSE || TARGET_3DNOW_A)
3796 4129775 : && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
3797 4129495 : "@
3798 : p<maxmin_int>b\t{%2, %0|%0, %2}
3799 : p<maxmin_int>b\t{%2, %0|%0, %2}
3800 294 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3801 1470570 : [(set_attr "isa" "*,sse2_noavx,avx")
3802 1470448 : (set_attr "mmx_isa" "native,*,*")
3803 1470448 : (set_attr "type" "mmxadd,sseiadd,sseiadd")
3804 0 : (set_attr "mode" "DI,TI,TI")])
3805 0 :
3806 : (define_expand "<code>v8qi3"
3807 2441 : [(set (match_operand:V8QI 0 "register_operand")
3808 2355 : (umaxmin:V8QI
3809 2355 : (match_operand:V8QI 1 "register_operand")
3810 : (match_operand:V8QI 2 "register_operand")))]
3811 : "TARGET_MMX_WITH_SSE")
3812 :
3813 1219 : (define_insn "<code><mode>3"
3814 1219 : [(set (match_operand:VI1_16_32 0 "register_operand" "=x,Yw")
3815 1219 : (umaxmin:VI1_16_32
3816 1219 : (match_operand:VI1_16_32 1 "register_operand" "%0,Yw")
3817 0 : (match_operand:VI1_16_32 2 "register_operand" "x,Yw")))]
3818 409 : "TARGET_SSE2"
3819 201 : "@
3820 : p<maxmin_int>b\t{%2, %0|%0, %2}
3821 : vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
3822 38 : [(set_attr "isa" "noavx,avx")
3823 28 : (set_attr "type" "sseiadd")
3824 : (set_attr "mode" "TI")])
3825 :
3826 : (define_insn "<code>v2hi3"
3827 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yv")
3828 : (umaxmin:V2HI
3829 : (match_operand:V2HI 1 "register_operand" "%0,0,Yv")
3830 : (match_operand:V2HI 2 "register_operand" "Yr,*x,Yv")))]
3831 10 : "TARGET_SSE4_1"
3832 : "@
3833 : p<maxmin_int>w\t{%2, %0|%0, %2}
3834 : p<maxmin_int>w\t{%2, %0|%0, %2}
3835 0 : vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
3836 0 : [(set_attr "isa" "noavx,noavx,avx")
3837 0 : (set_attr "type" "sseiadd")
3838 0 : (set_attr "prefix_extra" "1")
3839 0 : (set_attr "prefix" "orig,orig,vex")
3840 : (set_attr "mode" "TI")])
3841 :
3842 : (define_insn "ssse3_abs<mode>2"
3843 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
3844 : (abs:MMXMODEI
3845 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))]
3846 106 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
3847 62 : "@
3848 : pabs<mmxvecsize>\t{%1, %0|%0, %1}
3849 : %vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3850 396 : [(set_attr "mmx_isa" "native,*")
3851 396 : (set_attr "type" "sselog1")
3852 386 : (set_attr "prefix_rep" "0")
3853 386 : (set_attr "prefix_extra" "1")
3854 682 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3855 : (set_attr "mode" "DI,TI")])
3856 :
3857 : (define_expand "abs<mode>2"
3858 : [(set (match_operand:MMXMODEI 0 "register_operand")
3859 : (abs:MMXMODEI
3860 : (match_operand:MMXMODEI 1 "register_operand")))]
3861 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE")
3862 :
3863 : (define_insn "abs<mode>2"
3864 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yv")
3865 : (abs:VI_16_32
3866 : (match_operand:VI_16_32 1 "register_operand" "Yv")))]
3867 36 : "TARGET_SSSE3"
3868 48 : "%vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
3869 : [(set_attr "type" "sselog1")
3870 : (set_attr "prefix_rep" "0")
3871 62 : (set_attr "prefix_extra" "1")
3872 62 : (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
3873 50 : (set_attr "mode" "TI")])
3874 50 :
3875 102 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3876 : ;;
3877 1803471 : ;; Parallel integral shifts
3878 : ;;
3879 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3880 :
3881 1803471 : (define_insn "mmx_ashr<mode>3"
3882 1803471 : [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,<Yv_Yw>")
3883 1803471 : (ashiftrt:MMXMODE24
3884 1803471 : (match_operand:MMXMODE24 1 "register_operand" "0,0,<Yv_Yw>")
3885 1803471 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3886 1805501 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3887 : "@
3888 1413 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3889 1413 : psra<mmxvecsize>\t{%2, %0|%0, %2}
3890 3954 : vpsra<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3891 5367 : [(set_attr "isa" "*,sse2_noavx,avx")
3892 1413 : (set_attr "mmx_isa" "native,*,*")
3893 : (set_attr "type" "mmxshft,sseishft,sseishft")
3894 4736 : (set (attr "length_immediate")
3895 782 : (if_then_else (match_operand 2 "const_int_operand")
3896 782 : (const_string "1")
3897 1320 : (const_string "0")))
3898 244 : (set_attr "mode" "DI,TI,TI")])
3899 538 :
3900 538 : (define_insn_and_split "*mmx_ashr<mode>3_1"
3901 538 : [(set (match_operand:MMXMODE24 0 "register_operand")
3902 538 : (lt:MMXMODE24
3903 538 : (match_operand:MMXMODE24 1 "register_operand")
3904 : (match_operand:MMXMODE24 2 "const0_operand")))]
3905 5463 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3906 : "#"
3907 100 : "&& 1"
3908 550 : [(set (match_dup 0) (ashiftrt:MMXMODE24 (match_dup 1) (match_dup 3)))]
3909 2607 : "operands[3] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3910 1880 :
3911 225 : (define_expand "ashr<mode>3"
3912 663 : [(set (match_operand:MMXMODE24 0 "register_operand")
3913 : (ashiftrt:MMXMODE24
3914 : (match_operand:MMXMODE24 1 "register_operand")
3915 : (match_operand:DI 2 "nonmemory_operand")))]
3916 450 : "TARGET_MMX_WITH_SSE")
3917 :
3918 : (define_insn "mmx_<insn><mode>3"
3919 : [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,<Yv_Yw>")
3920 : (any_lshift:MMXMODE248
3921 26 : (match_operand:MMXMODE248 1 "register_operand" "0,0,<Yv_Yw>")
3922 : (match_operand:DI 2 "nonmemory_operand" "yN,xN,<Yv_Yw>N")))]
3923 6019 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
3924 26 : "@
3925 26 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3926 : p<vshift><mmxvecsize>\t{%2, %0|%0, %2}
3927 60323 : vp<vshift><mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
3928 60323 : [(set_attr "isa" "*,sse2_noavx,avx")
3929 : (set_attr "mmx_isa" "native,*,*")
3930 : (set_attr "type" "mmxshft,sseishft,sseishft")
3931 60323 : (set (attr "length_immediate")
3932 : (if_then_else (match_operand 2 "const_int_operand")
3933 : (const_string "1")
3934 : (const_string "0")))
3935 : (set_attr "mode" "DI,TI,TI")])
3936 :
3937 : (define_split
3938 : [(set (match_operand:MMXMODE248 0 "register_operand")
3939 : (and:MMXMODE248
3940 : (lt:MMXMODE248
3941 : (match_operand:MMXMODE248 1 "register_operand")
3942 : (match_operand:MMXMODE248 2 "const0_operand"))
3943 : (match_operand:MMXMODE248 3 "const1_operand")))]
3944 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
3945 28 : [(set (match_dup 0) (lshiftrt:MMXMODE248 (match_dup 1) (match_dup 4)))]
3946 0 : "operands[4] = gen_int_mode (<mmxscalarsize> - 1, DImode);")
3947 :
3948 28 : (define_expand "<insn><mode>3"
3949 28 : [(set (match_operand:MMXMODE24 0 "register_operand")
3950 : (any_lshift:MMXMODE24
3951 28 : (match_operand:MMXMODE24 1 "register_operand")
3952 : (match_operand:DI 2 "nonmemory_operand")))]
3953 0 : "TARGET_MMX_WITH_SSE")
3954 :
3955 : (define_insn "mmx_<insn>v1si3"
3956 : [(set (match_operand:V1SI 0 "register_operand" "=x,Yw")
3957 : (any_lshift:V1SI
3958 11 : (match_operand:V1SI 1 "register_operand" "0,Yw")
3959 45 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3960 3822 : "TARGET_SSE2"
3961 56 : "@
3962 11 : p<vshift>d\t{%2, %0|%0, %2}
3963 45 : vp<vshift>d\t{%2, %1, %0|%0, %1, %2}"
3964 846 : [(set_attr "isa" "noavx,avx")
3965 846 : (set_attr "type" "sseishft")
3966 : (set (attr "length_immediate")
3967 : (if_then_else (match_operand 2 "const_int_operand")
3968 846 : (const_string "1")
3969 : (const_string "0")))
3970 : (set_attr "mode" "TI")])
3971 :
3972 : (define_insn "<insn>v2hi3"
3973 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
3974 : (any_shift:V2HI
3975 : (match_operand:V2HI 1 "register_operand" "0,Yw")
3976 : (match_operand:DI 2 "nonmemory_operand" "xN,YwN")))]
3977 946 : "TARGET_SSE2"
3978 : "@
3979 : p<vshift>w\t{%2, %0|%0, %2}
3980 : vp<vshift>w\t{%2, %1, %0|%0, %1, %2}"
3981 253 : [(set_attr "isa" "noavx,avx")
3982 253 : (set_attr "type" "sseishft")
3983 253 : (set (attr "length_immediate")
3984 : (if_then_else (match_operand 2 "const_int_operand")
3985 : (const_string "1")
3986 253 : (const_string "0")))
3987 : (set_attr "mode" "TI")])
3988 :
3989 : (define_insn_and_split "*mmx_ashrv2hi3_1"
3990 : [(set (match_operand:V2HI 0 "register_operand")
3991 : (lt:V2HI
3992 : (match_operand:V2HI 1 "register_operand")
3993 : (match_operand:V2HI 2 "const0_operand")))]
3994 147 : "TARGET_SSE2 && ix86_pre_reload_split ()"
3995 : "#"
3996 : "&& 1"
3997 12 : [(set (match_dup 0) (ashiftrt:V2HI (match_dup 1) (match_dup 3)))]
3998 12 : "operands[3] = gen_int_mode (15, DImode);")
3999 :
4000 : (define_split
4001 12 : [(set (match_operand:V2HI 0 "register_operand")
4002 : (and:V2HI
4003 547469 : (lt:V2HI
4004 547469 : (match_operand:V2HI 1 "register_operand")
4005 1015124 : (match_operand:V2HI 2 "const0_operand"))
4006 1015112 : (match_operand:V2HI 3 "const1_operand")))]
4007 1015112 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4008 547469 : [(set (match_dup 0) (lshiftrt:V2HI (match_dup 1) (match_dup 4)))]
4009 0 : "operands[4] = gen_int_mode (15, DImode);")
4010 3681 :
4011 1048318 : (define_expand "<insn>v8qi3"
4012 1044632 : [(set (match_operand:V8QI 0 "register_operand")
4013 1048318 : (any_shift:V8QI (match_operand:V8QI 1 "register_operand")
4014 0 : (match_operand:DI 2 "nonmemory_operand")))]
4015 246646 : "TARGET_MMX_WITH_SSE"
4016 246738 : {
4017 484172 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4018 484075 : operands[1], operands[2]);
4019 484172 : DONE;
4020 : })
4021 3 :
4022 : (define_expand "<insn>v4qi3"
4023 1594206 : [(set (match_operand:V4QI 0 "register_operand")
4024 1594206 : (any_shift:V4QI (match_operand:V4QI 1 "register_operand")
4025 1594206 : (match_operand:DI 2 "nonmemory_operand")))]
4026 : "TARGET_SSE2"
4027 33 : {
4028 33 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4029 709759 : operands[1], operands[2]);
4030 709792 : DONE;
4031 709759 : })
4032 709759 :
4033 7 : (define_insn_and_split "<insn>v2qi3"
4034 0 : [(set (match_operand:V2QI 0 "register_operand" "=Q")
4035 7 : (any_shift:V2QI
4036 7 : (match_operand:V2QI 1 "register_operand" "0")
4037 7 : (match_operand:QI 2 "nonmemory_operand" "cI")))
4038 : (clobber (reg:CC FLAGS_REG))]
4039 637 : "!TARGET_PARTIAL_REG_STALL || optimize_size"
4040 54 : "#"
4041 123 : "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
4042 299 : && reload_completed"
4043 50 : [(parallel
4044 53 : [(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
4045 : (subreg:HI
4046 156662 : (any_shift:QI
4047 156669 : (subreg:QI
4048 134 : (zero_extract:HI (match_dup 4)
4049 67954 : (const_int 8)
4050 128726 : (const_int 8)) 0)
4051 128726 : (match_dup 2)) 0))
4052 128623 : (clobber (reg:CC FLAGS_REG))])
4053 59 : (parallel
4054 69 : [(set (strict_low_part (match_dup 0))
4055 20 : (any_shift:QI (match_dup 1) (match_dup 2)))
4056 : (clobber (reg:CC FLAGS_REG))])]
4057 50 : {
4058 50 : operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
4059 50 : operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
4060 50 : operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
4061 50 : operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
4062 : }
4063 : [(set_attr "type" "multi")
4064 : (set_attr "mode" "QI")])
4065 50 :
4066 : (define_expand "v<insn>v8qi3"
4067 : [(set (match_operand:V8QI 0 "register_operand")
4068 : (any_shift:V8QI
4069 : (match_operand:V8QI 1 "register_operand")
4070 : (match_operand:V8QI 2 "register_operand")))]
4071 : "TARGET_AVX512BW && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
4072 9 : {
4073 9 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4074 50 : operands[1], operands[2]);
4075 9 : DONE;
4076 : })
4077 :
4078 : (define_expand "v<insn>v4qi3"
4079 3 : [(set (match_operand:V4QI 0 "register_operand")
4080 : (any_shift:V4QI
4081 3 : (match_operand:V4QI 1 "register_operand")
4082 3 : (match_operand:V4QI 2 "register_operand")))]
4083 3 : "TARGET_AVX512BW && TARGET_AVX512VL"
4084 4 : {
4085 4 : ix86_expand_vecop_qihi_partial (<CODE>, operands[0],
4086 : operands[1], operands[2]);
4087 4 : DONE;
4088 : })
4089 5 :
4090 : (define_expand "vec_shl_<mode>"
4091 5 : [(set (match_operand:V248FI 0 "register_operand")
4092 5 : (ashift:V1DI
4093 5 : (match_operand:V248FI 1 "nonimmediate_operand")
4094 : (match_operand:DI 2 "nonmemory_operand")))]
4095 : "TARGET_MMX_WITH_SSE"
4096 7 : {
4097 8 : rtx op0 = gen_reg_rtx (V1DImode);
4098 7 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4099 :
4100 7 : emit_insn (gen_mmx_ashlv1di3
4101 9 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4102 7 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4103 9 : DONE;
4104 3 : })
4105 3 :
4106 : (define_expand "vec_shl_<mode>"
4107 : [(set (match_operand:V24FI_32 0 "register_operand")
4108 : (ashift:V1SI
4109 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4110 : (match_operand:DI 2 "nonmemory_operand")))]
4111 : "TARGET_SSE2"
4112 4 : {
4113 4 : rtx op0 = gen_reg_rtx (V1SImode);
4114 4 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4115 :
4116 4 : emit_insn (gen_mmx_ashlv1si3
4117 1254 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4118 4 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4119 1254 : DONE;
4120 1250 : })
4121 1250 :
4122 : (define_expand "vec_shr_<mode>"
4123 : [(set (match_operand:V248FI 0 "register_operand")
4124 : (lshiftrt:V1DI
4125 : (match_operand:V248FI 1 "nonimmediate_operand")
4126 : (match_operand:DI 2 "nonmemory_operand")))]
4127 : "TARGET_MMX_WITH_SSE"
4128 1250 : {
4129 1250 : rtx op0 = gen_reg_rtx (V1DImode);
4130 1250 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4131 :
4132 1250 : emit_insn (gen_mmx_lshrv1di3
4133 1491 : (op0, gen_lowpart (V1DImode, op1), operands[2]));
4134 1250 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4135 1491 : DONE;
4136 241 : })
4137 241 :
4138 : (define_expand "vec_shr_<mode>"
4139 : [(set (match_operand:V24FI_32 0 "register_operand")
4140 : (lshiftrt:V1SI
4141 : (match_operand:V24FI_32 1 "nonimmediate_operand")
4142 : (match_operand:DI 2 "nonmemory_operand")))]
4143 : "TARGET_SSE2"
4144 241 : {
4145 241 : rtx op0 = gen_reg_rtx (V1SImode);
4146 241 : rtx op1 = force_reg (<MODE>mode, operands[1]);
4147 :
4148 241 : emit_insn (gen_mmx_lshrv1si3
4149 1133 : (op0, gen_lowpart (V1SImode, op1), operands[2]));
4150 241 : emit_move_insn (operands[0], gen_lowpart (<MODE>mode, op0));
4151 1133 : DONE;
4152 892 : })
4153 892 :
4154 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4155 : ;;
4156 : ;; Parallel integral comparisons
4157 : ;;
4158 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4159 :
4160 : (define_expand "mmx_eq<mode>3"
4161 : [(set (match_operand:MMXMODEI 0 "register_operand")
4162 : (eq:MMXMODEI
4163 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4164 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4165 161 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4166 105 : "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
4167 161 :
4168 161 : (define_insn "*mmx_eq<mode>3"
4169 161 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4170 105 : (eq:MMXMODEI
4171 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x")
4172 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4173 1831 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4174 11479 : && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
4175 10011 : "@
4176 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4177 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4178 19740 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4179 19934 : [(set_attr "isa" "*,sse2_noavx,avx")
4180 : (set_attr "mmx_isa" "native,*,*")
4181 29511 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4182 194 : (set_attr "mode" "DI,TI,TI")])
4183 194 :
4184 : (define_insn "*eq<mode>3"
4185 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4186 : (eq:VI_16_32
4187 : (match_operand:VI_16_32 1 "register_operand" "%0,x")
4188 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4189 928 : "TARGET_SSE2"
4190 : "@
4191 : pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
4192 : vpcmpeq<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4193 2102 : [(set_attr "isa" "noavx,avx")
4194 2102 : (set_attr "type" "ssecmp")
4195 : (set_attr "mode" "TI")])
4196 2102 :
4197 : (define_insn "mmx_gt<mode>3"
4198 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
4199 : (gt:MMXMODEI
4200 : (match_operand:MMXMODEI 1 "register_operand" "0,0,x")
4201 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")))]
4202 2073 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4203 6132567 : "@
4204 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4205 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4206 11734 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4207 6144301 : [(set_attr "isa" "*,sse2_noavx,avx")
4208 6132567 : (set_attr "mmx_isa" "native,*,*")
4209 6144301 : (set_attr "type" "mmxcmp,ssecmp,ssecmp")
4210 6132567 : (set_attr "mode" "DI,TI,TI")])
4211 6132567 :
4212 : (define_insn "*gt<mode>3"
4213 427849 : [(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
4214 427849 : (gt:VI_16_32
4215 : (match_operand:VI_16_32 1 "register_operand" "0,x")
4216 0 : (match_operand:VI_16_32 2 "register_operand" "x,x")))]
4217 370 : "TARGET_SSE2"
4218 : "@
4219 : pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
4220 : vpcmpgt<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
4221 1557 : [(set_attr "isa" "noavx,avx")
4222 1557 : (set_attr "type" "ssecmp")
4223 : (set_attr "mode" "TI")])
4224 1557 :
4225 : (define_insn "*xop_maskcmp<mode>3"
4226 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4227 : (match_operator:MMXMODEI 1 "ix86_comparison_int_operator"
4228 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4229 4572873 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4230 4573002 : "TARGET_XOP"
4231 4572873 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4232 4572873 : [(set_attr "type" "sse4arg")
4233 4572873 : (set_attr "mode" "TI")])
4234 4572873 :
4235 17522 : (define_insn "*xop_maskcmp<mode>3"
4236 4299 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4237 21821 : (match_operator:VI_16_32 1 "ix86_comparison_int_operator"
4238 : [(match_operand:VI_16_32 2 "register_operand" "x")
4239 4299 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4240 0 : "TARGET_XOP"
4241 : "vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4242 : [(set_attr "type" "sse4arg")
4243 : (set_attr "mode" "TI")])
4244 2366 :
4245 2366 : (define_insn "*xop_maskcmp_uns<mode>3"
4246 : [(set (match_operand:MMXMODEI 0 "register_operand" "=x")
4247 2366 : (match_operator:MMXMODEI 1 "ix86_comparison_uns_operator"
4248 : [(match_operand:MMXMODEI 2 "register_operand" "x")
4249 : (match_operand:MMXMODEI 3 "register_operand" "x")]))]
4250 38287736 : "TARGET_XOP"
4251 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4252 : [(set_attr "type" "sse4arg")
4253 : (set_attr "mode" "TI")])
4254 38299955 :
4255 38299955 : (define_insn "*xop_maskcmp_uns<mode>3"
4256 38287736 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4257 38299955 : (match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
4258 38287736 : [(match_operand:VI_16_32 2 "register_operand" "x")
4259 : (match_operand:VI_16_32 3 "register_operand" "x")]))]
4260 30877151 : "TARGET_XOP"
4261 30877151 : "vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
4262 30877151 : [(set_attr "type" "sse4arg")
4263 : (set_attr "mode" "TI")])
4264 1774 :
4265 1774 : (define_expand "vec_cmp<mode><mode>"
4266 3767286 : [(set (match_operand:MMXMODEI 0 "register_operand")
4267 3769060 : (match_operator:MMXMODEI 1 ""
4268 3767286 : [(match_operand:MMXMODEI 2 "register_operand")
4269 : (match_operand:MMXMODEI 3 "register_operand")]))]
4270 : "TARGET_MMX_WITH_SSE"
4271 787 : {
4272 3125911 : bool ok = ix86_expand_int_vec_cmp (operands);
4273 3125911 : gcc_assert (ok);
4274 6357214 : DONE;
4275 : })
4276 :
4277 : (define_expand "vec_cmp<mode><mode>"
4278 3749478 : [(set (match_operand:VI_16_32 0 "register_operand")
4279 3749478 : (match_operator:VI_16_32 1 ""
4280 3231303 : [(match_operand:VI_16_32 2 "register_operand")
4281 3231738 : (match_operand:VI_16_32 3 "register_operand")]))]
4282 3231738 : "TARGET_SSE2"
4283 3231858 : {
4284 120 : bool ok = ix86_expand_int_vec_cmp (operands);
4285 2759066 : gcc_assert (ok);
4286 2759066 : DONE;
4287 2758946 : })
4288 2758655 :
4289 2758903 : (define_expand "vec_cmpu<mode><mode>"
4290 2758992 : [(set (match_operand:MMXMODEI 0 "register_operand")
4291 2758992 : (match_operator:MMXMODEI 1 ""
4292 2758992 : [(match_operand:MMXMODEI 2 "register_operand")
4293 2758566 : (match_operand:MMXMODEI 3 "register_operand")]))]
4294 2758566 : "TARGET_MMX_WITH_SSE"
4295 2758754 : {
4296 2758754 : bool ok = ix86_expand_int_vec_cmp (operands);
4297 2758754 : gcc_assert (ok);
4298 2758754 : DONE;
4299 2758566 : })
4300 2758790 :
4301 : (define_expand "vec_cmpu<mode><mode>"
4302 2712085 : [(set (match_operand:VI_16_32 0 "register_operand")
4303 2592716 : (match_operator:VI_16_32 1 ""
4304 162690 : [(match_operand:VI_16_32 2 "register_operand")
4305 2874151 : (match_operand:VI_16_32 3 "register_operand")]))]
4306 : "TARGET_SSE2"
4307 5836 : {
4308 5836 : bool ok = ix86_expand_int_vec_cmp (operands);
4309 109 : gcc_assert (ok);
4310 303 : DONE;
4311 194 : })
4312 320 :
4313 194 : (define_expand "vcond_mask_<mode><mmxintvecmodelower>"
4314 320 : [(set (match_operand:MMXMODE124 0 "register_operand")
4315 320 : (vec_merge:MMXMODE124
4316 320 : (match_operand:MMXMODE124 1 "register_operand")
4317 46 : (match_operand:MMXMODE124 2 "register_operand")
4318 148 : (match_operand:<mmxintvecmode> 3 "register_operand")))]
4319 148 : "TARGET_MMX_WITH_SSE"
4320 399 : {
4321 251 : ix86_expand_sse_movcc (operands[0], operands[3],
4322 126 : operands[1], operands[2]);
4323 377 : DONE;
4324 : })
4325 9 :
4326 6 : (define_expand "vcond_mask_<mode><mode>"
4327 9 : [(set (match_operand:VI_16_32 0 "register_operand")
4328 6 : (vec_merge:VI_16_32
4329 3 : (match_operand:VI_16_32 1 "register_operand")
4330 6 : (match_operand:VI_16_32 2 "register_operand")
4331 : (match_operand:VI_16_32 3 "register_operand")))]
4332 2 : "TARGET_SSE2"
4333 128 : {
4334 126 : ix86_expand_sse_movcc (operands[0], operands[3],
4335 : operands[1], operands[2]);
4336 126 : DONE;
4337 : })
4338 33 :
4339 : (define_insn "mmx_pblendvb_v8qi"
4340 33 : [(set (match_operand:V8QI 0 "register_operand" "=Yr,*x,x")
4341 0 : (unspec:V8QI
4342 33 : [(match_operand:V8QI 1 "register_operand" "0,0,x")
4343 : (match_operand:V8QI 2 "register_operand" "Yr,*x,x")
4344 : (match_operand:V8QI 3 "register_operand" "Yz,Yz,x")]
4345 : UNSPEC_BLENDV))]
4346 1851 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4347 : "@
4348 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4349 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4350 3569 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4351 3522 : [(set_attr "isa" "noavx,noavx,avx")
4352 47 : (set_attr "type" "ssemov")
4353 3569 : (set_attr "c86_attr" "blendv")
4354 47 : (set_attr "prefix_extra" "1")
4355 : (set_attr "length_immediate" "1")
4356 : (set_attr "prefix" "orig,orig,vex")
4357 : (set_attr "btver2_decode" "vector")
4358 : (set_attr "mode" "TI")])
4359 :
4360 : (define_insn_and_split "*mmx_pblendvb_v8qi_1"
4361 : [(set (match_operand:V8QI 0 "register_operand")
4362 : (unspec:V8QI
4363 : [(match_operand:V8QI 1 "register_operand")
4364 : (match_operand:V8QI 2 "register_operand")
4365 : (eq:V8QI
4366 : (eq:V8QI
4367 : (match_operand:V8QI 3 "register_operand")
4368 : (match_operand:V8QI 4 "nonmemory_operand"))
4369 : (match_operand:V8QI 5 "const0_operand"))]
4370 : UNSPEC_BLENDV))]
4371 0 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4372 0 : "#"
4373 : "&& 1"
4374 0 : [(set (match_dup 6)
4375 6 : (eq:V8QI (match_dup 3) (match_dup 7)))
4376 6 : (set (match_dup 0)
4377 6 : (unspec:V8QI
4378 6 : [(match_dup 2)
4379 : (match_dup 1)
4380 : (match_dup 6)]
4381 : UNSPEC_BLENDV))]
4382 0 : {
4383 0 : operands[6] = gen_reg_rtx (V8QImode);
4384 0 : operands[7] = force_reg (V8QImode, operands[4]);
4385 : })
4386 :
4387 : (define_insn_and_split "*mmx_pblendvb_v8qi_2"
4388 0 : [(set (match_operand:V8QI 0 "register_operand")
4389 : (unspec:V8QI
4390 : [(match_operand:V8QI 1 "register_operand")
4391 : (match_operand:V8QI 2 "register_operand")
4392 : (subreg:V8QI
4393 0 : (eq:MMXMODE24
4394 : (eq:MMXMODE24
4395 : (match_operand:MMXMODE24 3 "register_operand")
4396 : (match_operand:MMXMODE24 4 "nonmemory_operand"))
4397 : (match_operand:MMXMODE24 5 "const0_operand")) 0)]
4398 : UNSPEC_BLENDV))]
4399 10 : "TARGET_MMX_WITH_SSE && ix86_pre_reload_split ()"
4400 0 : "#"
4401 1 : "&& 1"
4402 0 : [(set (match_dup 6)
4403 34 : (eq:MMXMODE24 (match_dup 3) (match_dup 8)))
4404 30 : (set (match_dup 0)
4405 15 : (unspec:V8QI
4406 15 : [(match_dup 2)
4407 : (match_dup 1)
4408 : (match_dup 7)]
4409 : UNSPEC_BLENDV))]
4410 3 : {
4411 3 : operands[6] = gen_reg_rtx (<MODE>mode);
4412 3 : operands[7] = lowpart_subreg (V8QImode, operands[6], <MODE>mode);
4413 3 : operands[8] = force_reg (<MODE>mode, operands[4]);
4414 : })
4415 :
4416 : (define_insn "mmx_pblendvb_<mode>"
4417 3 : [(set (match_operand:VI_16_32 0 "register_operand" "=Yr,*x,x")
4418 : (unspec:VI_16_32
4419 : [(match_operand:VI_16_32 1 "register_operand" "0,0,x")
4420 : (match_operand:VI_16_32 2 "register_operand" "Yr,*x,x")
4421 : (match_operand:VI_16_32 3 "register_operand" "Yz,Yz,x")]
4422 3 : UNSPEC_BLENDV))]
4423 1964 : "TARGET_SSE4_1"
4424 : "@
4425 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4426 : pblendvb\t{%3, %2, %0|%0, %2, %3}
4427 1007 : vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4428 1011 : [(set_attr "isa" "noavx,noavx,avx")
4429 : (set_attr "type" "ssemov")
4430 1011 : (set_attr "c86_attr" "blendv")
4431 0 : (set_attr "prefix_extra" "1")
4432 4 : (set_attr "length_immediate" "1")
4433 : (set_attr "prefix" "orig,orig,vex")
4434 : (set_attr "btver2_decode" "vector")
4435 : (set_attr "mode" "TI")])
4436 :
4437 : (define_insn_and_split "*mmx_pblendvb_<mode>_1"
4438 : [(set (match_operand:VI_16_32 0 "register_operand")
4439 : (unspec:VI_16_32
4440 : [(match_operand:VI_16_32 1 "register_operand")
4441 : (match_operand:VI_16_32 2 "register_operand")
4442 : (eq:VI_16_32
4443 : (eq:VI_16_32
4444 : (match_operand:VI_16_32 3 "register_operand")
4445 : (match_operand:VI_16_32 4 "nonmemory_operand"))
4446 : (match_operand:VI_16_32 5 "const0_operand"))]
4447 : UNSPEC_BLENDV))]
4448 36 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4449 0 : "#"
4450 : "&& 1"
4451 0 : [(set (match_dup 6)
4452 30 : (eq:VI_16_32 (match_dup 3) (match_dup 7)))
4453 24 : (set (match_dup 0)
4454 12 : (unspec:VI_16_32
4455 24 : [(match_dup 2)
4456 : (match_dup 1)
4457 : (match_dup 6)]
4458 5639 : UNSPEC_BLENDV))]
4459 5657 : {
4460 8499 : operands[6] = gen_reg_rtx (<MODE>mode);
4461 8502 : operands[7] = force_reg (<MODE>mode, operands[4]);
4462 8487 : })
4463 8481 :
4464 8481 : (define_insn_and_split "*mmx_pblendvb_v4qi_2"
4465 8499 : [(set (match_operand:V4QI 0 "register_operand")
4466 8481 : (unspec:V4QI
4467 8481 : [(match_operand:V4QI 1 "register_operand")
4468 8481 : (match_operand:V4QI 2 "register_operand")
4469 8481 : (subreg:V4QI
4470 18 : (eq:V2HI
4471 8481 : (eq:V2HI
4472 : (match_operand:V2HI 3 "register_operand")
4473 7048 : (match_operand:V2HI 4 "nonmemory_operand"))
4474 7048 : (match_operand:V2HI 5 "const0_operand")) 0)]
4475 5 : UNSPEC_BLENDV))]
4476 7102 : "TARGET_SSE2 && ix86_pre_reload_split ()"
4477 5 : "#"
4478 14 : "&& 1"
4479 0 : [(set (match_dup 6)
4480 24 : (eq:V2HI (match_dup 3) (match_dup 8)))
4481 : (set (match_dup 0)
4482 5 : (unspec:V4QI
4483 : [(match_dup 2)
4484 834 : (match_dup 1)
4485 834 : (match_dup 7)]
4486 : UNSPEC_BLENDV))]
4487 15 : {
4488 15 : operands[6] = gen_reg_rtx (V2HImode);
4489 15 : operands[7] = lowpart_subreg (V4QImode, operands[6], V2HImode);
4490 29036 : operands[8] = force_reg (V2HImode, operands[4]);
4491 29021 : })
4492 0 :
4493 797 : ;; XOP parallel XMM conditional moves
4494 818 : (define_insn "*xop_pcmov_<mode>"
4495 : [(set (match_operand:MMXMODE124 0 "register_operand" "=x")
4496 : (if_then_else:MMXMODE124
4497 : (match_operand:MMXMODE124 3 "register_operand" "x")
4498 : (match_operand:MMXMODE124 1 "register_operand" "x")
4499 15 : (match_operand:MMXMODE124 2 "register_operand" "x")))]
4500 174 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4501 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4502 : [(set_attr "type" "sse4arg")
4503 : (set_attr "mode" "TI")])
4504 390 :
4505 381 : (define_insn "*xop_pcmov_<mode>"
4506 9 : [(set (match_operand:V4F_64 0 "register_operand" "=x")
4507 393 : (if_then_else:V4F_64
4508 : (match_operand:V4F_64 3 "register_operand" "x")
4509 : (match_operand:V4F_64 1 "register_operand" "x")
4510 : (match_operand:V4F_64 2 "register_operand" "x")))]
4511 18 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4512 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4513 : [(set_attr "type" "sse4arg")
4514 : (set_attr "mode" "TI")])
4515 3 :
4516 3 : (define_insn "*xop_pcmov_<mode>"
4517 1 : [(set (match_operand:VI_16_32 0 "register_operand" "=x")
4518 3 : (if_then_else:VI_16_32
4519 1 : (match_operand:VI_16_32 3 "register_operand" "x")
4520 0 : (match_operand:VI_16_32 1 "register_operand" "x")
4521 1 : (match_operand:VI_16_32 2 "register_operand" "x")))]
4522 0 : "TARGET_XOP"
4523 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4524 : [(set_attr "type" "sse4arg")
4525 : (set_attr "mode" "TI")])
4526 243 :
4527 243 : (define_insn "*xop_pcmov_<mode>"
4528 : [(set (match_operand:V2F_32 0 "register_operand" "=x")
4529 243 : (if_then_else:V2F_32
4530 : (match_operand:V2F_32 3 "register_operand" "x")
4531 : (match_operand:V2F_32 1 "register_operand" "x")
4532 : (match_operand:V2F_32 2 "register_operand" "x")))]
4533 3 : "TARGET_XOP"
4534 : "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4535 : [(set_attr "type" "sse4arg")
4536 : (set_attr "mode" "TI")])
4537 3 :
4538 3 : ;; XOP permute instructions
4539 : (define_insn "mmx_ppermv64"
4540 3 : [(set (match_operand:V8QI 0 "register_operand" "=x")
4541 318 : (unspec:V8QI
4542 318 : [(match_operand:V8QI 1 "register_operand" "x")
4543 : (match_operand:V8QI 2 "register_operand" "x")
4544 311 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4545 311 : UNSPEC_XOP_PERMUTE))]
4546 546 : "TARGET_XOP && TARGET_MMX_WITH_SSE"
4547 311 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4548 311 : [(set_attr "type" "sse4arg")
4549 : (set_attr "mode" "TI")])
4550 307 :
4551 307 : (define_insn "mmx_ppermv32"
4552 307 : [(set (match_operand:V4QI 0 "register_operand" "=x")
4553 307 : (unspec:V4QI
4554 307 : [(match_operand:V4QI 1 "register_operand" "x")
4555 : (match_operand:V4QI 2 "register_operand" "x")
4556 306 : (match_operand:V16QI 3 "nonimmediate_operand" "xm")]
4557 306 : UNSPEC_XOP_PERMUTE))]
4558 306 : "TARGET_XOP"
4559 306 : "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
4560 : [(set_attr "type" "sse4arg")
4561 302 : (set_attr "mode" "TI")])
4562 :
4563 80 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4564 80 : ;;
4565 : ;; Parallel integral logical operations
4566 14267 : ;;
4567 14347 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4568 :
4569 10 : (define_expand "one_cmpl<mode>2"
4570 10 : [(set (match_operand:MMXMODEI 0 "register_operand")
4571 10 : (xor:MMXMODEI
4572 : (match_operand:MMXMODEI 1 "register_operand")
4573 10 : (match_dup 2)))]
4574 10 : "TARGET_MMX_WITH_SSE"
4575 57 : "operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode));")
4576 :
4577 10 : (define_insn "one_cmpl<mode>2"
4578 10 : [(set (match_operand:VI_16_32 0 "register_operand" "=?r,&x,&v")
4579 57 : (not:VI_16_32
4580 10 : (match_operand:VI_16_32 1 "register_operand" "0,x,v")))]
4581 10 : ""
4582 : "#"
4583 47 : [(set_attr "isa" "*,sse2,avx512vl")
4584 0 : (set_attr "type" "negnot,sselog1,sselog1")
4585 0 : (set_attr "mode" "SI,TI,TI")])
4586 :
4587 : (define_split
4588 2 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4589 4 : (not:VI_16_32
4590 2 : (match_operand:VI_16_32 1 "general_reg_operand")))]
4591 7 : "reload_completed"
4592 6 : [(set (match_dup 0)
4593 381832 : (not:SI (match_dup 1)))]
4594 17 : {
4595 19 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4596 381839 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4597 : })
4598 :
4599 : (define_split
4600 6 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4601 0 : (not:VI_16_32
4602 : (match_operand:VI_16_32 1 "sse_reg_operand")))]
4603 18 : "TARGET_SSE2 && reload_completed"
4604 12 : [(set (match_dup 0) (match_dup 2))
4605 381795 : (set (match_dup 0)
4606 43 : (xor:V16QI
4607 43 : (match_dup 0) (match_dup 1)))]
4608 381850 : {
4609 44 : operands[2] = CONSTM1_RTX (V16QImode);
4610 12 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4611 44 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4612 0 : })
4613 32 :
4614 : (define_expand "andn<mode>3"
4615 12 : [(set (match_operand:MMXMODEI 0 "register_operand")
4616 : (and:MMXMODEI
4617 : (not:MMXMODEI (match_operand:MMXMODEI 2 "register_operand"))
4618 : (match_operand:MMXMODEI 1 "register_operand")))]
4619 12 : "TARGET_MMX_WITH_SSE")
4620 :
4621 : (define_insn "mmx_andnot<mode>3"
4622 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4623 : (and:MMXMODEI
4624 0 : (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,x,v"))
4625 36 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4626 215 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4627 36 : "@
4628 0 : pandn\t{%2, %0|%0, %2}
4629 36 : pandn\t{%2, %0|%0, %2}
4630 1877 : vpandn\t{%2, %1, %0|%0, %1, %2}
4631 1664 : vpandnd\t{%2, %1, %0|%0, %1, %2}"
4632 213 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4633 1664 : (set_attr "mmx_isa" "native,*,*,*")
4634 174 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4635 39 : (set_attr "mode" "DI,TI,TI,TI")])
4636 39 :
4637 : (define_insn "*andnot<mode>3"
4638 97 : [(set (match_operand:VI_16_32 0 "register_operand" "=?&r,?r,x,x,v")
4639 97 : (and:VI_16_32
4640 97 : (not:VI_16_32
4641 : (match_operand:VI_16_32 1 "register_operand" "0,r,0,x,v"))
4642 84 : (match_operand:VI_16_32 2 "register_operand" "r,r,x,x,v")))
4643 13 : (clobber (reg:CC FLAGS_REG))]
4644 13 : ""
4645 : "#"
4646 124 : [(set_attr "isa" "*,bmi,sse2_noavx,avx,avx512vl")
4647 124 : (set_attr "type" "alu,bitmanip,sselog,sselog,sselog")
4648 124 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4649 :
4650 99 : (define_split
4651 25 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4652 25 : (and:VI_16_32
4653 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4654 0 : (match_operand:VI_16_32 2 "general_reg_operand")))
4655 0 : (clobber (reg:CC FLAGS_REG))]
4656 1 : "TARGET_BMI && reload_completed"
4657 0 : [(parallel
4658 3 : [(set (match_dup 0)
4659 : (and:SI (not:SI (match_dup 1)) (match_dup 2)))
4660 : (clobber (reg:CC FLAGS_REG))])]
4661 0 : {
4662 0 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4663 0 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4664 0 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4665 : })
4666 :
4667 : (define_split
4668 0 : [(set (match_operand:VI_16_32 0 "general_reg_operand")
4669 : (and:VI_16_32
4670 : (not:VI_16_32 (match_operand:VI_16_32 1 "general_reg_operand"))
4671 : (match_operand:VI_16_32 2 "general_reg_operand")))
4672 : (clobber (reg:CC FLAGS_REG))]
4673 3 : "!TARGET_BMI && reload_completed"
4674 3 : [(set (match_dup 0)
4675 : (not:SI (match_dup 1)))
4676 136 : (parallel
4677 66 : [(set (match_dup 0)
4678 66 : (and:SI (match_dup 0) (match_dup 2)))
4679 136 : (clobber (reg:CC FLAGS_REG))])]
4680 3 : {
4681 3 : operands[2] = lowpart_subreg (SImode, operands[2], <MODE>mode);
4682 3 : operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
4683 3 : operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
4684 : })
4685 :
4686 : (define_split
4687 3 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4688 : (and:VI_16_32
4689 : (not:VI_16_32 (match_operand:VI_16_32 1 "sse_reg_operand"))
4690 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4691 : (clobber (reg:CC FLAGS_REG))]
4692 69 : "TARGET_SSE2 && reload_completed"
4693 70 : [(set (match_dup 0)
4694 66 : (and:V16QI (not:V16QI (match_dup 1)) (match_dup 2)))]
4695 66 : {
4696 2074 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4697 2148 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4698 142 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4699 2006 : })
4700 150 :
4701 76 : (define_expand "mmx_<code><mode>3"
4702 144 : [(set (match_operand:MMXMODEI 0 "register_operand")
4703 : (any_logic:MMXMODEI
4704 2 : (match_operand:MMXMODEI 1 "register_mmxmem_operand")
4705 : (match_operand:MMXMODEI 2 "register_mmxmem_operand")))]
4706 66 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4707 109 : "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4708 :
4709 : (define_expand "<code><mode>3"
4710 : [(set (match_operand:MMXMODEI 0 "register_operand")
4711 433 : (any_logic:MMXMODEI
4712 : (match_operand:MMXMODEI 1 "register_operand")
4713 324 : (match_operand:MMXMODEI 2 "register_operand")))]
4714 324 : "TARGET_MMX_WITH_SSE")
4715 109 :
4716 : (define_insn "*mmx_<code><mode>3"
4717 : [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x,v")
4718 289 : (any_logic:MMXMODEI
4719 : (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,x,v")
4720 2014 : (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x,v")))]
4721 2095 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
4722 31516 : && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4723 8689 : "@
4724 167 : p<logic>\t{%2, %0|%0, %2}
4725 698 : p<logic>\t{%2, %0|%0, %2}
4726 31958 : vp<logic>\t{%2, %1, %0|%0, %1, %2}
4727 33107 : vp<logic>d\t{%2, %1, %0|%0, %1, %2}"
4728 21873 : [(set_attr "isa" "*,sse2_noavx,avx,avx512vl")
4729 : (set_attr "mmx_isa" "native,*,*,*")
4730 39342 : (set_attr "type" "mmxadd,sselog,sselog,sselog")
4731 : (set_attr "mode" "DI,TI,TI,TI")])
4732 96 :
4733 5 : (define_expand "<code><mode>3"
4734 96 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand")
4735 202 : (any_logic:VI_16_32
4736 96 : (match_operand:VI_16_32 1 "nonimmediate_operand")
4737 106 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand")))]
4738 101 : ""
4739 364 : "ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
4740 :
4741 : (define_insn "*<code><mode>3"
4742 : [(set (match_operand:VI_16_32 0 "nonimmediate_operand" "=?r,m,x,x,v")
4743 : (any_logic:VI_16_32
4744 : (match_operand:VI_16_32 1 "nonimmediate_operand" "%0,0,0,x,v")
4745 : (match_operand:VI_16_32 2 "nonimmediate_or_x86_64_const_vector_operand" "r,i,x,x,v")))
4746 : (clobber (reg:CC FLAGS_REG))]
4747 3805 : "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4748 217 : "#"
4749 981 : [(set_attr "isa" "*,*,sse2_noavx,avx,avx512vl")
4750 981 : (set_attr "type" "alu,alu,sselog,sselog,sselog")
4751 5656 : (set_attr "mode" "SI,SI,TI,TI,TI")])
4752 5992 :
4753 1348 : (define_split
4754 1648 : [(set (match_operand:VI_16_32 0 "nonimmediate_gr_operand")
4755 9907 : (any_logic:VI_16_32
4756 11895 : (match_operand:VI_16_32 1 "nonimmediate_gr_operand")
4757 102 : (match_operand:VI_16_32 2 "reg_or_const_vector_operand")))
4758 4146 : (clobber (reg:CC FLAGS_REG))]
4759 4168 : "reload_completed"
4760 57 : [(parallel
4761 965 : [(set (match_dup 0)
4762 328 : (any_logic:<mmxinsnmode> (match_dup 1) (match_dup 2)))
4763 328 : (clobber (reg:CC FLAGS_REG))])]
4764 1022 : {
4765 57 : if (!register_operand (operands[2], <MODE>mode))
4766 : {
4767 9 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (operands[2],
4768 : <MODE>mode);
4769 9 : operands[2] = GEN_INT (val);
4770 : }
4771 : else
4772 48 : operands[2] = lowpart_subreg (<mmxinsnmode>mode, operands[2], <MODE>mode);
4773 57 : operands[1] = lowpart_subreg (<mmxinsnmode>mode, operands[1], <MODE>mode);
4774 57 : operands[0] = lowpart_subreg (<mmxinsnmode>mode, operands[0], <MODE>mode);
4775 : })
4776 :
4777 : (define_split
4778 57 : [(set (match_operand:VI_16_32 0 "sse_reg_operand")
4779 : (any_logic:VI_16_32
4780 : (match_operand:VI_16_32 1 "sse_reg_operand")
4781 : (match_operand:VI_16_32 2 "sse_reg_operand")))
4782 57 : (clobber (reg:CC FLAGS_REG))]
4783 328 : "TARGET_SSE2 && reload_completed"
4784 637 : [(set (match_dup 0)
4785 328 : (any_logic:V16QI (match_dup 1) (match_dup 2)))]
4786 328 : {
4787 879 : operands[2] = lowpart_subreg (V16QImode, operands[2], <MODE>mode);
4788 1495 : operands[1] = lowpart_subreg (V16QImode, operands[1], <MODE>mode);
4789 379 : operands[0] = lowpart_subreg (V16QImode, operands[0], <MODE>mode);
4790 910 : })
4791 541 :
4792 860 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4793 328 : ;;
4794 : ;; Parallel integral element swizzling
4795 : ;;
4796 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4797 328 :
4798 : (define_insn_and_split "mmx_packsswb"
4799 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4800 : (vec_concat:V8QI
4801 : (ss_truncate:V4QI
4802 : (match_operand:V4HI 1 "register_operand" "0,0,Yw"))
4803 4419 : (ss_truncate:V4QI
4804 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4805 4764 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4806 0 : "@
4807 4419 : packsswb\t{%2, %0|%0, %2}
4808 : #
4809 286 : #"
4810 98 : "&& reload_completed
4811 46 : && SSE_REGNO_P (REGNO (operands[0]))"
4812 : [(const_int 0)]
4813 92 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4814 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4815 112 : (set_attr "type" "mmxshft,sselog,sselog")
4816 224 : (set_attr "mode" "DI,TI,TI")])
4817 :
4818 : ;; This instruction does unsigned saturation of signed source
4819 : ;; and is different from generic us_truncate RTX.
4820 : (define_insn_and_split "mmx_packuswb"
4821 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4822 : (unspec:V8QI
4823 : [(match_operand:V4HI 1 "register_operand" "0,0,Yw")
4824 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")]
4825 431 : UNSPEC_US_TRUNCATE))]
4826 5979 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4827 431 : "@
4828 0 : packuswb\t{%2, %0|%0, %2}
4829 431 : #
4830 1061 : #"
4831 2201 : "&& reload_completed
4832 570 : && SSE_REGNO_P (REGNO (operands[0]))"
4833 : [(const_int 0)]
4834 1140 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4835 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4836 184 : (set_attr "type" "mmxshft,sselog,sselog")
4837 368 : (set_attr "mode" "DI,TI,TI")])
4838 :
4839 : (define_insn_and_split "mmx_packssdw"
4840 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4841 : (vec_concat:V4HI
4842 : (ss_truncate:V2HI
4843 : (match_operand:V2SI 1 "register_operand" "0,0,Yw"))
4844 : (ss_truncate:V2HI
4845 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yw"))))]
4846 770 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4847 : "@
4848 366 : packssdw\t{%2, %0|%0, %2}
4849 0 : #
4850 366 : #"
4851 112 : "&& reload_completed
4852 56 : && SSE_REGNO_P (REGNO (operands[0]))"
4853 : [(const_int 0)]
4854 112 : "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;"
4855 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4856 : (set_attr "type" "mmxshft,sselog,sselog")
4857 : (set_attr "mode" "DI,TI,TI")])
4858 :
4859 : (define_insn_and_split "mmx_packusdw"
4860 14050 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
4861 : (unspec:V4HI
4862 484075 : [(match_operand:V2SI 1 "register_operand" "0,0,Yw")
4863 : (match_operand:V2SI 2 "register_operand" "Yr,*x,Yw")]
4864 498125 : UNSPEC_US_TRUNCATE))]
4865 500451 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
4866 498125 : "#"
4867 498329 : "&& reload_completed"
4868 498145 : [(const_int 0)]
4869 498329 : "ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
4870 14050 : [(set_attr "isa" "noavx,noavx,avx")
4871 318195 : (set_attr "type" "sselog")
4872 318195 : (set_attr "mode" "TI")])
4873 368927 :
4874 354877 : (define_insn_and_split "mmx_punpckhbw"
4875 447782 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4876 447782 : (vec_select:V8QI
4877 447782 : (vec_concat:V16QI
4878 439096 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4879 363520 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4880 143621 : (parallel [(const_int 4) (const_int 12)
4881 384430 : (const_int 5) (const_int 13)
4882 48696 : (const_int 6) (const_int 14)
4883 6416 : (const_int 7) (const_int 15)])))]
4884 1720 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4885 7992 : "@
4886 7986 : punpckhbw\t{%2, %0|%0, %2}
4887 1616 : #
4888 11926 : #"
4889 3600 : "&& reload_completed
4890 381 : && SSE_REGNO_P (REGNO (operands[0]))"
4891 : [(const_int 0)]
4892 958 : "ix86_split_mmx_punpck (operands, true); DONE;"
4893 392 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4894 862 : (set_attr "type" "mmxcvt,sselog,sselog")
4895 1724 : (set_attr "mode" "DI,TI,TI")])
4896 :
4897 : (define_insn_and_split "mmx_punpckhbw_low"
4898 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4899 : (vec_select:V4QI
4900 : (vec_concat:V8QI
4901 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4902 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4903 18 : (parallel [(const_int 2) (const_int 6)
4904 : (const_int 3) (const_int 7)])))]
4905 3925 : "TARGET_SSE2"
4906 18 : "#"
4907 496 : "&& reload_completed"
4908 : [(const_int 0)]
4909 12260 : "ix86_split_mmx_punpck (operands, true); DONE;"
4910 131 : [(set_attr "isa" "noavx,avx")
4911 2550 : (set_attr "type" "sselog")
4912 5100 : (set_attr "mode" "TI")])
4913 :
4914 : (define_insn_and_split "mmx_punpcklbw"
4915 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
4916 : (vec_select:V8QI
4917 : (vec_concat:V16QI
4918 : (match_operand:V8QI 1 "register_operand" "0,0,Yw")
4919 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw"))
4920 21 : (parallel [(const_int 0) (const_int 8)
4921 : (const_int 1) (const_int 9)
4922 21 : (const_int 2) (const_int 10)
4923 21 : (const_int 3) (const_int 11)])))]
4924 7144 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4925 : "@
4926 : punpcklbw\t{%2, %0|%0, %k2}
4927 : #
4928 3429 : #"
4929 4291 : "&& reload_completed
4930 431 : && SSE_REGNO_P (REGNO (operands[0]))"
4931 : [(const_int 0)]
4932 862 : "ix86_split_mmx_punpck (operands, false); DONE;"
4933 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4934 478 : (set_attr "type" "mmxcvt,sselog,sselog")
4935 478 : (set_attr "mode" "DI,TI,TI")])
4936 :
4937 : (define_insn_and_split "mmx_punpcklbw_low"
4938 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
4939 : (vec_select:V4QI
4940 : (vec_concat:V8QI
4941 : (match_operand:V4QI 1 "register_operand" "0,Yw")
4942 : (match_operand:V4QI 2 "register_operand" "x,Yw"))
4943 33 : (parallel [(const_int 0) (const_int 4)
4944 : (const_int 1) (const_int 5)])))]
4945 5239 : "TARGET_SSE2"
4946 33 : "#"
4947 765 : "&& reload_completed"
4948 : [(const_int 0)]
4949 16111 : "ix86_split_mmx_punpck (operands, false); DONE;"
4950 184 : [(set_attr "isa" "noavx,avx")
4951 3426 : (set_attr "type" "sselog")
4952 6852 : (set_attr "mode" "TI")])
4953 :
4954 : (define_insn_and_split "mmx_punpckhwd"
4955 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4956 : (vec_select:V4HI
4957 : (vec_concat:V8HI
4958 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
4959 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
4960 5 : (parallel [(const_int 2) (const_int 6)
4961 : (const_int 3) (const_int 7)])))]
4962 14468 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4963 5 : "@
4964 5 : punpckhwd\t{%2, %0|%0, %2}
4965 : #
4966 4474 : #"
4967 7024 : "&& reload_completed
4968 1275 : && SSE_REGNO_P (REGNO (operands[0]))"
4969 : [(const_int 0)]
4970 2550 : "ix86_split_mmx_punpck (operands, true); DONE;"
4971 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4972 732 : (set_attr "type" "mmxcvt,sselog,sselog")
4973 732 : (set_attr "mode" "DI,TI,TI")])
4974 :
4975 : (define_insn_and_split "mmx_punpcklwd"
4976 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
4977 : (vec_select:V4HI
4978 : (vec_concat:V8HI
4979 : (match_operand:V4HI 1 "register_operand" "0,0,Yw")
4980 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw"))
4981 29 : (parallel [(const_int 0) (const_int 4)
4982 : (const_int 1) (const_int 5)])))]
4983 19018 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
4984 29 : "@
4985 29 : punpcklwd\t{%2, %0|%0, %k2}
4986 : #
4987 : #"
4988 3426 : "&& reload_completed
4989 1713 : && SSE_REGNO_P (REGNO (operands[0]))"
4990 : [(const_int 0)]
4991 7696 : "ix86_split_mmx_punpck (operands, false); DONE;"
4992 4270 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
4993 4279 : (set_attr "type" "mmxcvt,sselog,sselog")
4994 : (set_attr "mode" "DI,TI,TI")])
4995 :
4996 : (define_insn_and_split "mmx_punpckhdq"
4997 495815 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
4998 495815 : (vec_select:V2SI
4999 495815 : (vec_concat:V4SI
5000 495815 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
5001 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
5002 320067 : (parallel [(const_int 1)
5003 320033 : (const_int 3)])))]
5004 327956 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5005 34 : "@
5006 34 : punpckhdq\t{%2, %0|%0, %2}
5007 : #
5008 35651 : #"
5009 560 : "&& reload_completed
5010 35931 : && SSE_REGNO_P (REGNO (operands[0]))"
5011 280 : [(const_int 0)]
5012 221724 : "ix86_split_mmx_punpck (operands, true); DONE;"
5013 221444 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5014 216812 : (set_attr "type" "mmxcvt,sselog,sselog")
5015 81 : (set_attr "mode" "DI,TI,TI")])
5016 81 :
5017 11339 : (define_insn_and_split "mmx_punpckldq"
5018 57136 : [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
5019 57136 : (vec_select:V2SI
5020 57136 : (vec_concat:V4SI
5021 : (match_operand:V2SI 1 "register_operand" "0,0,Yv")
5022 0 : (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))
5023 14 : (parallel [(const_int 0)
5024 : (const_int 2)])))]
5025 14471 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5026 14 : "@
5027 14 : punpckldq\t{%2, %0|%0, %k2}
5028 : #
5029 2402 : #"
5030 3100 : "&& reload_completed
5031 349 : && SSE_REGNO_P (REGNO (operands[0]))"
5032 349 : [(const_int 0)]
5033 349 : "ix86_split_mmx_punpck (operands, false); DONE;"
5034 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
5035 238 : (set_attr "type" "mmxcvt,sselog,sselog")
5036 238 : (set_attr "mode" "DI,TI,TI")])
5037 :
5038 : (define_insn "sse4_1_<code>v4qiv4hi2"
5039 : [(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
5040 : (any_extend:V4HI
5041 : (vec_select:V4QI
5042 : (match_operand:V8QI 1 "register_operand" "Yr,*x,Yw")
5043 : (parallel [(const_int 0) (const_int 1)
5044 9 : (const_int 2) (const_int 3)]))))]
5045 2552 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5046 9 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5047 9 : [(set_attr "isa" "noavx,noavx,avx")
5048 9 : (set_attr "type" "ssemov")
5049 12459 : (set_attr "c86_attr" "vpmovx")
5050 12459 : (set_attr "prefix_extra" "1")
5051 : (set_attr "prefix" "orig,orig,maybe_evex")
5052 2557 : (set_attr "mode" "TI")])
5053 2557 :
5054 : (define_expand "<insn>v4qiv4hi2"
5055 : [(set (match_operand:V4HI 0 "register_operand")
5056 : (any_extend:V4HI
5057 : (match_operand:V4QI 1 "register_operand")))]
5058 : "TARGET_MMX_WITH_SSE"
5059 47 : {
5060 47 : if (!TARGET_SSE4_1)
5061 : {
5062 32 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5063 32 : DONE;
5064 : }
5065 :
5066 15 : rtx op1 = force_reg (V4QImode, operands[1]);
5067 15 : op1 = lowpart_subreg (V8QImode, op1, V4QImode);
5068 15 : emit_insn (gen_sse4_1_<code>v4qiv4hi2 (operands[0], op1));
5069 15 : DONE;
5070 : })
5071 :
5072 : (define_insn "sse4_1_<code>v2hiv2si2"
5073 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5074 : (any_extend:V2SI
5075 : (vec_select:V2HI
5076 : (match_operand:V4HI 1 "register_operand" "Yr,*x,v")
5077 : (parallel [(const_int 0) (const_int 1)]))))]
5078 5114 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5079 : "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
5080 : [(set_attr "isa" "noavx,noavx,avx")
5081 : (set_attr "type" "ssemov")
5082 329 : (set_attr "c86_attr" "vpmovx")
5083 282 : (set_attr "prefix_extra" "1")
5084 47 : (set_attr "prefix" "orig,orig,maybe_evex")
5085 47 : (set_attr "mode" "TI")])
5086 47 :
5087 : (define_expand "<insn>v2hiv2si2"
5088 : [(set (match_operand:V2SI 0 "register_operand")
5089 : (any_extend:V2SI
5090 : (match_operand:V2HI 1 "register_operand")))]
5091 : "TARGET_MMX_WITH_SSE"
5092 39 : {
5093 39 : if (!TARGET_SSE4_1)
5094 : {
5095 30 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5096 30 : DONE;
5097 : }
5098 :
5099 9 : rtx op1 = force_reg (V2HImode, operands[1]);
5100 9 : op1 = lowpart_subreg (V4HImode, op1, V2HImode);
5101 9 : emit_insn (gen_sse4_1_<code>v2hiv2si2 (operands[0], op1));
5102 9 : DONE;
5103 : })
5104 :
5105 : (define_insn "sse4_1_<code>v2qiv2si2"
5106 : [(set (match_operand:V2SI 0 "register_operand" "=Yr,*x,v")
5107 : (any_extend:V2SI
5108 : (vec_select:V2QI
5109 : (match_operand:V4QI 1 "register_operand" "Yr,*x,v")
5110 : (parallel [(const_int 0) (const_int 1)]))))]
5111 564 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5112 : "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
5113 : [(set_attr "isa" "noavx,noavx,avx")
5114 : (set_attr "type" "ssemov")
5115 446 : (set_attr "c86_attr" "vpmovx")
5116 112 : (set_attr "prefix_extra" "1")
5117 334 : (set_attr "prefix" "orig,orig,maybe_evex")
5118 334 : (set_attr "mode" "TI")])
5119 334 :
5120 : (define_expand "<insn>v2qiv2si2"
5121 : [(set (match_operand:V2SI 0 "register_operand")
5122 : (any_extend:V2SI
5123 : (match_operand:V2QI 1 "register_operand")))]
5124 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5125 38 : {
5126 38 : rtx op1 = force_reg (V2QImode, operands[1]);
5127 38 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5128 38 : emit_insn (gen_sse4_1_<code>v2qiv2si2 (operands[0], op1));
5129 38 : DONE;
5130 : })
5131 :
5132 : (define_insn "sse4_1_<code>v2qiv2hi2"
5133 : [(set (match_operand:V2HI 0 "register_operand" "=Yr,*x,Yw")
5134 : (any_extend:V2HI
5135 : (vec_select:V2QI
5136 : (match_operand:V4QI 1 "register_operand" "Yr,*x,Yw")
5137 : (parallel [(const_int 0) (const_int 1)]))))]
5138 112 : "TARGET_SSE4_1"
5139 : "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
5140 : [(set_attr "isa" "noavx,noavx,avx")
5141 : (set_attr "type" "ssemov")
5142 727 : (set_attr "c86_attr" "vpmovx")
5143 : (set_attr "prefix_extra" "1")
5144 727 : (set_attr "prefix" "orig,orig,maybe_evex")
5145 727 : (set_attr "mode" "TI")])
5146 110441 :
5147 109714 : (define_expand "<insn>v2qiv2hi2"
5148 3 : [(set (match_operand:V2HI 0 "register_operand")
5149 109717 : (any_extend:V2HI
5150 : (match_operand:V2QI 1 "register_operand")))]
5151 3 : "TARGET_SSE2"
5152 66 : {
5153 66 : if (!TARGET_SSE4_1)
5154 : {
5155 57 : ix86_expand_sse_extend (operands[0], operands[1], <u_bool>);
5156 2511 : DONE;
5157 : }
5158 :
5159 6 : rtx op1 = force_reg (V2QImode, operands[1]);
5160 2460 : op1 = lowpart_subreg (V4QImode, op1, V2QImode);
5161 2460 : emit_insn (gen_sse4_1_<code>v2qiv2hi2 (operands[0], op1));
5162 2460 : DONE;
5163 2454 : })
5164 2454 :
5165 2454 : (define_expand "trunc<mode><mmxhalfmodelower>2"
5166 2454 : [(set (match_operand:<mmxhalfmode> 0 "register_operand")
5167 2454 : (truncate:<mmxhalfmode>
5168 2454 : (match_operand:VI2_32_64 1 "register_operand")))]
5169 : "TARGET_AVX2"
5170 41 : {
5171 41 : if (TARGET_AVX512VL && TARGET_AVX512BW)
5172 21 : emit_insn (gen_avx512vl_trunc<mode><mmxhalfmodelower>2 (operands[0], operands[1]));
5173 : else
5174 11 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <mmxbytemode>mode);
5175 475 : DONE;
5176 : })
5177 443 :
5178 443 : (define_insn "avx512vl_trunc<mode><mmxhalfmodelower>2"
5179 443 : [(set (match_operand:<mmxhalfmode> 0 "register_operand" "=v")
5180 : (truncate:<mmxhalfmode>
5181 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
5182 175 : "TARGET_AVX512VL && TARGET_AVX512BW"
5183 : "vpmovwb\t{%1, %0|%0, %1}"
5184 : [(set_attr "type" "ssemov")
5185 : (set_attr "prefix" "evex")
5186 73 : (set_attr "mode" "TI")])
5187 73 :
5188 370 : (define_mode_iterator V2QI_V2HI [V2QI V2HI])
5189 : (define_mode_attr v2qi_quad_v2hi_double
5190 297 : [(V2QI "V8QI") (V2HI "V4HI")])
5191 297 : (define_expand "truncv2si<mode>2"
5192 297 : [(set (match_operand:V2QI_V2HI 0 "register_operand")
5193 : (truncate:V2QI_V2HI
5194 : (match_operand:V2SI 1 "register_operand")))]
5195 : "TARGET_AVX2 && TARGET_MMX_WITH_SSE"
5196 47 : {
5197 47 : if (TARGET_AVX512VL)
5198 15 : emit_insn (gen_avx512vl_truncv2si<mode>2 (operands[0], operands[1]));
5199 : else
5200 32 : ix86_expand_trunc_with_avx2_noavx512f (operands[0], operands[1], <v2qi_quad_v2hi_double>mode);
5201 47 : DONE;
5202 : })
5203 :
5204 : (define_insn "avx512vl_truncv2si<mode>2"
5205 : [(set (match_operand:V2QI_V2HI 0 "register_operand" "=v")
5206 : (truncate:V2QI_V2HI
5207 : (match_operand:V2SI 1 "register_operand" "v")))]
5208 115 : "TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
5209 : "vpmovd<mmxvecsize>\t{%1, %0|%0, %1}"
5210 40 : [(set_attr "type" "ssemov")
5211 15 : (set_attr "prefix" "evex")
5212 40 : (set_attr "mode" "TI")])
5213 :
5214 281 : ;; Pack/unpack vector modes
5215 : (define_mode_attr mmxpackmode
5216 335 : [(V4HI "V8QI") (V2SI "V4HI")])
5217 301 :
5218 335 : (define_expand "vec_pack_trunc_<mode>"
5219 : [(match_operand:<mmxpackmode> 0 "register_operand")
5220 : (match_operand:MMXMODE24 1 "register_operand")
5221 : (match_operand:MMXMODE24 2 "register_operand")]
5222 : "TARGET_MMX_WITH_SSE"
5223 727 : {
5224 727 : rtx op1 = gen_lowpart (<mmxpackmode>mode, operands[1]);
5225 727 : rtx op2 = gen_lowpart (<mmxpackmode>mode, operands[2]);
5226 727 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5227 727 : DONE;
5228 : })
5229 :
5230 : (define_expand "vec_pack_trunc_v2hi"
5231 : [(match_operand:V4QI 0 "register_operand")
5232 : (match_operand:V2HI 1 "register_operand")
5233 : (match_operand:V2HI 2 "register_operand")]
5234 : "TARGET_SSE2"
5235 24 : {
5236 24 : rtx op1 = gen_lowpart (V4QImode, operands[1]);
5237 24 : rtx op2 = gen_lowpart (V4QImode, operands[2]);
5238 24 : ix86_expand_vec_extract_even_odd (operands[0], op1, op2, 0);
5239 24 : DONE;
5240 10 : })
5241 3 :
5242 10 : (define_mode_attr mmxunpackmode
5243 13 : [(V8QI "V4HI") (V4HI "V2SI")])
5244 10 :
5245 3 : (define_expand "vec_unpacks_lo_<mode>"
5246 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5247 : (match_operand:MMXMODE12 1 "register_operand")]
5248 : "TARGET_MMX_WITH_SSE"
5249 439 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5250 :
5251 : (define_expand "vec_unpacks_hi_<mode>"
5252 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5253 0 : (match_operand:MMXMODE12 1 "register_operand")]
5254 : "TARGET_MMX_WITH_SSE"
5255 443 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5256 0 :
5257 0 : (define_expand "vec_unpacku_lo_<mode>"
5258 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5259 : (match_operand:MMXMODE12 1 "register_operand")]
5260 : "TARGET_MMX_WITH_SSE"
5261 900 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5262 :
5263 451 : (define_expand "vec_unpacku_hi_<mode>"
5264 451 : [(match_operand:<mmxunpackmode> 0 "register_operand")
5265 451 : (match_operand:MMXMODE12 1 "register_operand")]
5266 : "TARGET_MMX_WITH_SSE"
5267 461 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5268 :
5269 10 : (define_expand "vec_unpacks_lo_v4qi"
5270 10 : [(match_operand:V2HI 0 "register_operand")
5271 10 : (match_operand:V4QI 1 "register_operand")]
5272 : "TARGET_SSE2"
5273 75 : "ix86_expand_sse_unpack (operands[0], operands[1], false, false); DONE;")
5274 0 :
5275 75 : (define_expand "vec_unpacks_hi_v4qi"
5276 75 : [(match_operand:V2HI 0 "register_operand")
5277 75 : (match_operand:V4QI 1 "register_operand")]
5278 0 : "TARGET_SSE2"
5279 191 : "ix86_expand_sse_unpack (operands[0], operands[1], false, true); DONE;")
5280 55 :
5281 191 : (define_expand "vec_unpacku_lo_v4qi"
5282 246 : [(match_operand:V2HI 0 "register_operand")
5283 191 : (match_operand:V4QI 1 "register_operand")]
5284 55 : "TARGET_SSE2"
5285 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, false); DONE;")
5286 1940 :
5287 : (define_expand "vec_unpacku_hi_v4qi"
5288 1940 : [(match_operand:V2HI 0 "register_operand")
5289 0 : (match_operand:V4QI 1 "register_operand")]
5290 1940 : "TARGET_SSE2"
5291 10 : "ix86_expand_sse_unpack (operands[0], operands[1], true, true); DONE;")
5292 199 :
5293 : (define_insn "*mmx_pinsrd"
5294 199 : [(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
5295 0 : (vec_merge:V2SI
5296 199 : (vec_duplicate:V2SI
5297 : (match_operand:SI 2 "nonimmediate_operand" "jrjm,rm"))
5298 43 : (match_operand:V2SI 1 "register_operand" "0,Yv")
5299 : (match_operand:SI 3 "const_int_operand")))]
5300 243 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5301 200 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5302 243 : < GET_MODE_NUNITS (V2SImode))"
5303 26 : {
5304 52 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5305 26 : switch (which_alternative)
5306 21 : {
5307 21 : case 1:
5308 0 : return "vpinsrd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5309 0 : case 0:
5310 21 : return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
5311 0 : default:
5312 0 : gcc_unreachable ();
5313 : }
5314 : }
5315 : [(set_attr "isa" "noavx,avx")
5316 : (set_attr "addr" "gpr16,*")
5317 : (set_attr "prefix_extra" "1")
5318 0 : (set_attr "type" "sselog")
5319 : (set_attr "c86_attr" "insr")
5320 : (set_attr "length_immediate" "1")
5321 : (set_attr "prefix" "orig,vex")
5322 : (set_attr "mode" "TI")])
5323 :
5324 : (define_insn "*mmx_pinsrw"
5325 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,x,YW,&x")
5326 : (vec_merge:V4FI_64
5327 : (vec_duplicate:V4FI_64
5328 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,rm,x"))
5329 : (match_operand:V4FI_64 1 "register_operand" "0,0,YW,x")
5330 : (match_operand:SI 3 "const_int_operand")))]
5331 63 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5332 372 : && (TARGET_SSE || TARGET_3DNOW_A)
5333 372 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5334 15 : < GET_MODE_NUNITS (V4HImode))"
5335 39 : {
5336 39 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5337 39 : switch (which_alternative)
5338 567 : {
5339 567 : case 3:
5340 : return "#";
5341 16 : case 2:
5342 940 : if (MEM_P (operands[2]))
5343 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5344 : else
5345 16 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5346 23 : case 1:
5347 23 : case 0:
5348 23 : if (MEM_P (operands[2]))
5349 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
5350 : else
5351 13 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
5352 0 : default:
5353 0 : gcc_unreachable ();
5354 : }
5355 : }
5356 : [(set_attr "isa" "*,sse2_noavx,avx,sse4")
5357 : (set_attr "mmx_isa" "native,*,*,*")
5358 : (set_attr "type" "mmxcvt,sselog,sselog,sselog")
5359 40 : (set_attr "c86_attr" "insr")
5360 : (set_attr "length_immediate" "1")
5361 : (set_attr "mode" "DI,TI,TI,TI")])
5362 :
5363 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
5364 : (define_split
5365 : [(set (match_operand:V4FI_64 0 "sse_reg_operand")
5366 : (vec_merge:V4FI_64
5367 : (vec_duplicate:V4FI_64
5368 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
5369 : (match_operand:V4FI_64 1 "sse_reg_operand")
5370 : (match_operand:SI 3 "const_int_operand")))]
5371 3 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 && reload_completed
5372 3 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5373 3 : < GET_MODE_NUNITS (<MODE>mode))"
5374 : [(set (match_dup 0)
5375 3 : (vec_duplicate:V4FI_64 (match_dup 2)))
5376 : (set (match_dup 0)
5377 115 : (vec_merge:V4FI_64 (match_dup 1) (match_dup 0) (match_dup 3)))]
5378 118 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0xf);")
5379 :
5380 : (define_insn "*mmx_pinsrb"
5381 118 : [(set (match_operand:V8QI 0 "register_operand" "=x,YW")
5382 : (vec_merge:V8QI
5383 : (vec_duplicate:V8QI
5384 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
5385 : (match_operand:V8QI 1 "register_operand" "0,YW")
5386 3 : (match_operand:SI 3 "const_int_operand")))]
5387 10 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
5388 10 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
5389 10 : < GET_MODE_NUNITS (V8QImode))"
5390 1 : {
5391 26721 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
5392 1 : switch (which_alternative)
5393 26726 : {
5394 26727 : case 1:
5395 26720 : if (MEM_P (operands[2]))
5396 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
5397 7 : else
5398 1 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
5399 0 : case 0:
5400 0 : if (MEM_P (operands[2]))
5401 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
5402 : else
5403 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
5404 0 : default:
5405 0 : gcc_unreachable ();
5406 : }
5407 : }
5408 : [(set_attr "isa" "noavx,avx")
5409 : (set_attr "type" "sselog")
5410 : (set_attr "c86_attr" "insr")
5411 : (set_attr "addr" "gpr16,*")
5412 : (set_attr "prefix_extra" "1")
5413 : (set_attr "length_immediate" "1")
5414 : (set_attr "prefix" "orig,vex")
5415 : (set_attr "mode" "TI")])
5416 :
5417 : (define_insn "*mmx_pextrw"
5418 8 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,jm,m")
5419 : (vec_select:HI
5420 : (match_operand:V4HI 1 "register_operand" "y,YW,YW,YW")
5421 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5422 2124 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5423 2124 : && (TARGET_SSE || TARGET_3DNOW_A)"
5424 : "@
5425 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5426 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
5427 640 : pextrw\t{%2, %1, %0|%0, %1, %2}
5428 640 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
5429 628 : [(set_attr "isa" "*,sse2,sse4_noavx,avx")
5430 640 : (set_attr "addr" "*,*,gpr16,*")
5431 : (set_attr "mmx_isa" "native,*,*,*")
5432 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
5433 : (set_attr "c86_attr" "extr")
5434 : (set_attr "length_immediate" "1")
5435 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
5436 : (set_attr "mode" "DI,TI,TI,TI")])
5437 :
5438 : (define_insn "*mmx_pextrw<mode>"
5439 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,?r,jm,m,x,Yw")
5440 : (vec_select:<mmxscalarmode>
5441 : (match_operand:V4F_64 1 "register_operand" "y,YW,YW,YW,0,YW")
5442 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
5443 14 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5444 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5445 8 : {
5446 8 : switch (which_alternative)
5447 : {
5448 68 : case 0:
5449 68 : case 1:
5450 62 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
5451 72 : case 2:
5452 4 : case 3:
5453 4 : return "%vpextrw\t{%2, %1, %0|%0, %1, %2}";
5454 4 : case 4:
5455 4 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5456 4 : return "psrldq\t{%2, %0|%0, %2}";
5457 0 : case 5:
5458 0 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
5459 0 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
5460 :
5461 0 : default:
5462 0 : gcc_unreachable ();
5463 : }
5464 : }
5465 : [(set_attr "isa" "*,sse2,sse4_noavx,avx,noavx,avx")
5466 : (set_attr "addr" "*,*,gpr16,*,*,*")
5467 : (set_attr "mmx_isa" "native,*,*,*,*,*")
5468 0 : (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
5469 : (set_attr "c86_attr" "extr,extr,extr,extr,*,*")
5470 : (set_attr "length_immediate" "1")
5471 : (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
5472 : (set_attr "mode" "DI,TI,TI,TI,TI,TI")])
5473 :
5474 : (define_insn "*mmx_pextrw_zext"
5475 : [(set (match_operand:SWI48 0 "register_operand" "=r,r")
5476 : (zero_extend:SWI48
5477 : (vec_select:HI
5478 : (match_operand:V4HI 1 "register_operand" "y,YW")
5479 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
5480 6925 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5481 6925 : && (TARGET_SSE || TARGET_3DNOW_A)"
5482 : "@
5483 : pextrw\t{%2, %1, %k0|%k0, %1, %2}
5484 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
5485 5089 : [(set_attr "isa" "*,sse2")
5486 5089 : (set_attr "mmx_isa" "native,*")
5487 : (set_attr "type" "mmxcvt,sselog1")
5488 : (set_attr "c86_attr" "extr")
5489 : (set_attr "length_immediate" "1")
5490 : (set_attr "prefix" "orig,maybe_vex")
5491 : (set_attr "mode" "DI,TI")])
5492 :
5493 : (define_insn "*mmx_pextrb"
5494 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
5495 0 : (vec_select:QI
5496 : (match_operand:V8QI 1 "register_operand" "YW,YW,YW,YW")
5497 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))]
5498 3251 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5499 : "@
5500 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
5501 : pextrb\t{%2, %1, %0|%0, %1, %2}
5502 152 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
5503 152 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
5504 109 : [(set_attr "isa" "noavx,noavx,avx,avx")
5505 152 : (set_attr "addr" "*,gpr16,*,*")
5506 : (set_attr "type" "sselog1")
5507 : (set_attr "c86_attr" "extr")
5508 : (set_attr "prefix_extra" "1")
5509 : (set_attr "length_immediate" "1")
5510 : (set_attr "prefix" "maybe_vex")
5511 : (set_attr "mode" "TI")])
5512 :
5513 : (define_insn "*mmx_pextrb_zext"
5514 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
5515 : (zero_extend:SWI248
5516 : (vec_select:QI
5517 : (match_operand:V8QI 1 "register_operand" "YW,YW")
5518 : (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))]
5519 5067 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5520 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
5521 : [(set_attr "isa" "noavx,avx")
5522 : (set_attr "type" "sselog1")
5523 386 : (set_attr "c86_attr" "extr")
5524 386 : (set_attr "prefix_extra" "1")
5525 : (set_attr "length_immediate" "1")
5526 : (set_attr "prefix" "maybe_vex")
5527 : (set_attr "mode" "TI")])
5528 :
5529 : (define_insn "mmx_pshufbv8qi3"
5530 : [(set (match_operand:V8QI 0 "register_operand" "=x,Yw")
5531 : (unspec:V8QI
5532 : [(match_operand:V8QI 1 "register_operand" "0,Yw")
5533 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5534 : UNSPEC_PSHUFB))]
5535 2670 : "TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
5536 281 : "@
5537 : pshufb\t{%2, %0|%0, %2}
5538 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5539 2919 : [(set_attr "isa" "noavx,avx")
5540 2919 : (set_attr "addr" "gpr16,*")
5541 2919 : (set_attr "type" "sselog1")
5542 2919 : (set_attr "prefix_extra" "1")
5543 2919 : (set_attr "prefix" "orig,maybe_evex")
5544 : (set_attr "btver2_decode" "vector")
5545 : (set_attr "mode" "TI")])
5546 :
5547 : (define_insn "mmx_pshufbv4qi3"
5548 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
5549 : (unspec:V4QI
5550 : [(match_operand:V4QI 1 "register_operand" "0,Yw")
5551 : (match_operand:V16QI 2 "vector_operand" "xja,Ywm")]
5552 : UNSPEC_PSHUFB))]
5553 2721 : "TARGET_SSSE3"
5554 198 : "@
5555 : pshufb\t{%2, %0|%0, %2}
5556 : vpshufb\t{%2, %1, %0|%0, %1, %2}"
5557 : [(set_attr "isa" "noavx,avx")
5558 : (set_attr "addr" "gpr16,*")
5559 : (set_attr "type" "sselog1")
5560 : (set_attr "prefix_extra" "1")
5561 43304 : (set_attr "prefix" "orig,maybe_evex")
5562 43304 : (set_attr "btver2_decode" "vector")
5563 : (set_attr "mode" "TI")])
5564 11196 :
5565 11196 : (define_expand "mmx_pshufw"
5566 11196 : [(match_operand:V4HI 0 "register_operand")
5567 : (match_operand:V4HI 1 "register_mmxmem_operand")
5568 11112 : (match_operand:SI 2 "const_int_operand")]
5569 11112 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5570 11112 : && (TARGET_SSE || TARGET_3DNOW_A)"
5571 75 : {
5572 9459 : int mask = INTVAL (operands[2]);
5573 9459 : emit_insn (gen_mmx_pshufwv4hi_1 (operands[0], operands[1],
5574 9384 : GEN_INT ((mask >> 0) & 3),
5575 14899 : GEN_INT ((mask >> 2) & 3),
5576 75 : GEN_INT ((mask >> 4) & 3),
5577 75 : GEN_INT ((mask >> 6) & 3)));
5578 75 : DONE;
5579 : })
5580 :
5581 : (define_insn "mmx_pshufw<mode>_1"
5582 : [(set (match_operand:V4FI_64 0 "register_operand" "=y,Yw")
5583 : (vec_select:V4FI_64
5584 : (match_operand:V4FI_64 1 "register_mmxmem_operand" "ym,Yw")
5585 : (parallel [(match_operand 2 "const_0_to_3_operand")
5586 : (match_operand 3 "const_0_to_3_operand")
5587 : (match_operand 4 "const_0_to_3_operand")
5588 : (match_operand 5 "const_0_to_3_operand")])))]
5589 417 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5590 0 : && (TARGET_SSE || TARGET_3DNOW_A)"
5591 6478 : {
5592 1156 : int mask = 0;
5593 1156 : mask |= INTVAL (operands[2]) << 0;
5594 13309 : mask |= INTVAL (operands[3]) << 2;
5595 13309 : mask |= INTVAL (operands[4]) << 4;
5596 10217 : mask |= INTVAL (operands[5]) << 6;
5597 9061 : operands[2] = GEN_INT (mask);
5598 19432 :
5599 1156 : switch (which_alternative)
5600 : {
5601 : case 0:
5602 : return "pshufw\t{%2, %1, %0|%0, %1, %2}";
5603 1156 : case 1:
5604 1340 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
5605 0 : default:
5606 0 : gcc_unreachable ();
5607 : }
5608 184 : }
5609 184 : [(set_attr "isa" "*,sse2")
5610 184 : (set_attr "mmx_isa" "native,*")
5611 184 : (set_attr "type" "mmxcvt,sselog1")
5612 2137 : (set_attr "length_immediate" "1")
5613 184 : (set_attr "mode" "DI,TI")])
5614 184 :
5615 184 : (define_insn "*mmx_pshufd_1"
5616 184 : [(set (match_operand:V2SI 0 "register_operand" "=Yv")
5617 184 : (vec_select:V2SI
5618 184 : (match_operand:V2SI 1 "register_operand" "Yv")
5619 : (parallel [(match_operand 2 "const_0_to_1_operand")
5620 10 : (match_operand 3 "const_0_to_1_operand")])))]
5621 9783 : "TARGET_MMX_WITH_SSE"
5622 807 : {
5623 807 : int mask = 0;
5624 807 : mask |= INTVAL (operands[2]) << 0;
5625 807 : mask |= INTVAL (operands[3]) << 2;
5626 804 : mask |= 2 << 4;
5627 814 : mask |= 3 << 6;
5628 804 : operands[2] = GEN_INT (mask);
5629 7 :
5630 797 : return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
5631 : }
5632 : [(set_attr "type" "sselog1")
5633 : (set_attr "prefix_data16" "1")
5634 : (set_attr "length_immediate" "1")
5635 : (set_attr "mode" "TI")])
5636 :
5637 : (define_insn "*mmx_pblendw64"
5638 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yr,*x,x")
5639 : (vec_merge:V4FI_64
5640 : (match_operand:V4FI_64 2 "register_operand" "Yr,*x,x")
5641 : (match_operand:V4FI_64 1 "register_operand" "0,0,x")
5642 : (match_operand:SI 3 "const_0_to_15_operand")))]
5643 2957 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5644 : "@
5645 : pblendw\t{%3, %2, %0|%0, %2, %3}
5646 : pblendw\t{%3, %2, %0|%0, %2, %3}
5647 6226 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5648 6226 : [(set_attr "isa" "noavx,noavx,avx")
5649 : (set_attr "type" "ssemov")
5650 6226 : (set_attr "c86_attr" "blend")
5651 : (set_attr "prefix_extra" "1")
5652 : (set_attr "length_immediate" "1")
5653 : (set_attr "prefix" "orig,orig,vex")
5654 : (set_attr "mode" "TI")])
5655 :
5656 : (define_insn "*mmx_pblendw32"
5657 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yr,*x,x")
5658 : (vec_merge:V2FI_32
5659 : (match_operand:V2FI_32 2 "register_operand" "Yr,*x,x")
5660 : (match_operand:V2FI_32 1 "register_operand" "0,0,x")
5661 : (match_operand:SI 3 "const_0_to_7_operand")))]
5662 1 : "TARGET_SSE4_1"
5663 : "@
5664 : pblendw\t{%3, %2, %0|%0, %2, %3}
5665 : pblendw\t{%3, %2, %0|%0, %2, %3}
5666 64 : vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
5667 64 : [(set_attr "isa" "noavx,noavx,avx")
5668 : (set_attr "type" "ssemov")
5669 165082 : (set_attr "c86_attr" "blend")
5670 : (set_attr "prefix_extra" "1")
5671 66609 : (set_attr "length_immediate" "1")
5672 66609 : (set_attr "prefix" "orig,orig,vex")
5673 : (set_attr "mode" "TI")])
5674 2492 :
5675 2492 : ;; Optimize V2SImode load from memory, swapping the elements and
5676 : ;; storing back into the memory into DImode rotate of the memory by 32.
5677 2492 : (define_split
5678 : [(set (match_operand:V2SI 0 "memory_operand")
5679 : (vec_select:V2SI (match_dup 0)
5680 : (parallel [(const_int 1) (const_int 0)])))]
5681 55 : "TARGET_64BIT && (TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())"
5682 55 : [(set (match_dup 0)
5683 : (rotate:DI (match_dup 0) (const_int 32)))]
5684 55 : "operands[0] = adjust_address (operands[0], DImode, 0);")
5685 :
5686 : (define_insn "mmx_pswapdv2si2"
5687 55 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5688 : (vec_select:V2SI
5689 437371 : (match_operand:V2SI 1 "register_mmxmem_operand" "ym,Yv")
5690 : (parallel [(const_int 1) (const_int 0)])))]
5691 261699 : "TARGET_3DNOW_A"
5692 411686 : "@
5693 194880 : pswapd\t{%1, %0|%0, %1}
5694 : %vpshufd\t{$0xe1, %1, %0|%0, %1, 0xe1}";
5695 1246002 : [(set_attr "isa" "*,sse2")
5696 1174011 : (set_attr "mmx_isa" "native,*")
5697 1174002 : (set_attr "type" "mmxcvt,sselog1")
5698 138799 : (set_attr "prefix_extra" "1,*")
5699 1140596 : (set_attr "length_immediate" "*,1")
5700 28370 : (set_attr "mode" "DI,TI")])
5701 838252 :
5702 809891 : (define_insn "*vec_dupv4hi"
5703 3 : [(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
5704 96375 : (vec_duplicate:V4HI
5705 96375 : (truncate:HI
5706 : (match_operand:SI 1 "register_operand" "0,Yw"))))]
5707 9910 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5708 9826 : && (TARGET_SSE || TARGET_3DNOW_A)"
5709 : "@
5710 : pshufw\t{$0, %0, %0|%0, %0, 0}
5711 : %vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5712 246 : [(set_attr "isa" "*,sse2")
5713 246 : (set_attr "mmx_isa" "native,*")
5714 246 : (set_attr "type" "mmxcvt,sselog1")
5715 246 : (set_attr "length_immediate" "1")
5716 : (set_attr "mode" "DI,TI")])
5717 :
5718 : (define_insn "*vec_dup<mode>"
5719 : [(set (match_operand:V4FI_64 0 "register_operand" "=Yw")
5720 : (vec_duplicate:V4FI_64
5721 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
5722 32 : "TARGET_MMX_WITH_SSE"
5723 77 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
5724 : [(set_attr "isa" "sse2")
5725 : (set_attr "type" "sselog1")
5726 15098 : (set_attr "length_immediate" "1")
5727 15098 : (set_attr "mode" "TI")])
5728 13871 :
5729 13871 : (define_insn "*vec_dupv2si"
5730 18485 : [(set (match_operand:V2SI 0 "register_operand" "=y,Yv")
5731 : (vec_duplicate:V2SI
5732 : (match_operand:SI 1 "register_operand" "0,Yv")))]
5733 10808 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5734 1169 : "@
5735 : punpckldq\t%0, %0
5736 : %vpshufd\t{$0xe0, %1, %0|%0, %1, 0xe0}"
5737 23 : [(set_attr "isa" "*,sse2")
5738 23 : (set_attr "mmx_isa" "native,*")
5739 18 : (set_attr "type" "mmxcvt,sselog1")
5740 18 : (set_attr "prefix_data16" "*,1")
5741 23 : (set_attr "length_immediate" "*,1")
5742 : (set_attr "mode" "DI,TI")])
5743 :
5744 : (define_insn "*mmx_concatv2si"
5745 : [(set (match_operand:V2SI 0 "register_operand" "=y,y")
5746 : (vec_concat:V2SI
5747 : (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
5748 : (match_operand:SI 2 "nonimm_or_0_operand" "ym,C")))]
5749 396591 : "TARGET_MMX && !TARGET_SSE"
5750 : "@
5751 396591 : punpckldq\t{%2, %0|%0, %2}
5752 : movd\t{%1, %0|%0, %1}"
5753 : [(set_attr "type" "mmxcvt,mmxmov")
5754 : (set_attr "mode" "DI")])
5755 :
5756 : (define_expand "vec_setv2si"
5757 : [(match_operand:V2SI 0 "register_operand")
5758 : (match_operand:SI 1 "register_operand")
5759 : (match_operand 2 "vec_setm_mmx_operand")]
5760 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5761 191 : {
5762 191 : if (CONST_INT_P (operands[2]))
5763 189 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5764 189 : INTVAL (operands[2]));
5765 : else
5766 2 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5767 191 : DONE;
5768 : })
5769 :
5770 : ;; Avoid combining registers from different units in a single alternative,
5771 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5772 : (define_insn_and_split "*vec_extractv2si_0"
5773 : [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r,r")
5774 : (vec_select:SI
5775 : (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m,x")
5776 : (parallel [(const_int 0)])))]
5777 25121 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5778 25121 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5779 : "#"
5780 3943 : "&& reload_completed"
5781 1940 : [(set (match_dup 0) (match_dup 1))]
5782 331336 : "operands[1] = gen_lowpart (SImode, operands[1]);"
5783 329396 : [(set_attr "isa" "*,*,*,*,*,sse2")
5784 444296 : (set_attr "mmx_isa" "*,*,native,native,*,*")
5785 116840 : (set (attr "preferred_for_speed")
5786 114900 : (cond [(eq_attr "alternative" "5")
5787 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5788 1940 : ]
5789 : (symbol_ref "true")))])
5790 :
5791 : (define_insn "*vec_extractv2si_0_zext_sse4"
5792 : [(set (match_operand:DI 0 "register_operand" "=r,x")
5793 7 : (zero_extend:DI
5794 : (vec_select:SI
5795 7 : (match_operand:V2SI 1 "register_operand" "x,x")
5796 7 : (parallel [(const_int 0)]))))]
5797 859 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE4_1"
5798 : "#"
5799 852 : [(set_attr "isa" "x64,*")
5800 : (set (attr "preferred_for_speed")
5801 : (cond [(eq_attr "alternative" "0")
5802 : (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
5803 : ]
5804 : (symbol_ref "true")))])
5805 :
5806 : (define_insn "*vec_extractv2si_0_zext"
5807 : [(set (match_operand:DI 0 "register_operand" "=r")
5808 : (zero_extend:DI
5809 : (vec_select:SI
5810 : (match_operand:V2SI 1 "register_operand" "x")
5811 : (parallel [(const_int 0)]))))]
5812 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5813 852 : && TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC"
5814 : "#")
5815 :
5816 : (define_split
5817 : [(set (match_operand:DI 0 "register_operand")
5818 3116 : (zero_extend:DI
5819 3116 : (vec_select:SI
5820 : (match_operand:V2SI 1 "register_operand")
5821 2630 : (parallel [(const_int 0)]))))]
5822 398 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5823 398 : && TARGET_SSE2 && reload_completed"
5824 199 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5825 199 : "operands[1] = gen_lowpart (SImode, operands[1]);")
5826 :
5827 1360 : ;; Avoid combining registers from different units in a single alternative,
5828 1559 : ;; see comment above inline_secondary_memory_needed function in i386.cc
5829 1360 : (define_insn "*vec_extractv2si_1"
5830 : [(set (match_operand:SI 0 "nonimmediate_operand" "=y,jrjm,rm,x,x,y,x,r")
5831 199 : (vec_select:SI
5832 : (match_operand:V2SI 1 "nonimmediate_operand" " 0,x, x ,x,0,o,o,o")
5833 : (parallel [(const_int 1)])))]
5834 15380 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5835 15380 : && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5836 816 : "@
5837 : punpckhdq\t%0, %0
5838 816 : pextrd\t{$1, %1, %0|%0, %1, 1}
5839 183371 : vpextrd\t{$1, %1, %0|%0, %1, 1}
5840 183371 : %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
5841 176361 : shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
5842 176361 : #
5843 356812 : #
5844 : #"
5845 : [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*")
5846 : (set (attr "addr")
5847 : (if_then_else (eq_attr "alternative" "1")
5848 : (const_string "gpr16")
5849 : (const_string "*")))
5850 : (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
5851 : (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
5852 : (set_attr "c86_attr" "*,extr,extr,*,*,*,*,*")
5853 : (set (attr "length_immediate")
5854 : (if_then_else (eq_attr "alternative" "1,2,3,4")
5855 : (const_string "1")
5856 : (const_string "*")))
5857 : (set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,orig,orig,orig,orig")
5858 : (set_attr "mode" "DI,TI,TI,TI,V4SF,SI,SI,SI")])
5859 :
5860 : (define_split
5861 : [(set (match_operand:SI 0 "register_operand")
5862 : (vec_select:SI
5863 : (match_operand:V2SI 1 "memory_operand")
5864 : (parallel [(const_int 1)])))]
5865 43 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed"
5866 43 : [(set (match_dup 0) (match_dup 1))]
5867 43 : "operands[1] = adjust_address (operands[1], SImode, 4);")
5868 :
5869 4328 : (define_insn "*vec_extractv2si_1_zext"
5870 4371 : [(set (match_operand:DI 0 "register_operand" "=jr,r")
5871 3097 : (zero_extend:DI
5872 3097 : (vec_select:SI
5873 4403 : (match_operand:V2SI 1 "register_operand" "x,x")
5874 : (parallel [(const_int 1)]))))]
5875 974 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
5876 974 : && TARGET_64BIT && TARGET_SSE4_1"
5877 : "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
5878 0 : [(set_attr "isa" "noavx,avx")
5879 : (set_attr "type" "sselog1")
5880 0 : (set_attr "c86_attr" "extr")
5881 0 : (set_attr "prefix_extra" "1")
5882 0 : (set_attr "length_immediate" "1")
5883 4134 : (set_attr "prefix" "maybe_vex")
5884 4134 : (set_attr "mode" "TI")])
5885 :
5886 1457 : (define_insn_and_split "*vec_extractv2si_zext_mem"
5887 1457 : [(set (match_operand:DI 0 "register_operand" "=y,x,r")
5888 2 : (zero_extend:DI
5889 1459 : (vec_select:SI
5890 : (match_operand:V2SI 1 "memory_operand" "o,o,o")
5891 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
5892 2 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_64BIT"
5893 1455 : "#"
5894 0 : "&& reload_completed"
5895 199 : [(set (match_dup 0) (zero_extend:DI (match_dup 1)))]
5896 2650 : {
5897 2650 : operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4);
5898 740 : }
5899 3390 : [(set_attr "isa" "*,sse2,*")
5900 2650 : (set_attr "mmx_isa" "native,*,*")])
5901 740 :
5902 : (define_expand "vec_extractv2sisi"
5903 : [(match_operand:SI 0 "register_operand")
5904 0 : (match_operand:V2SI 1 "register_operand")
5905 : (match_operand 2 "const_int_operand")]
5906 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5907 8273 : {
5908 8273 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5909 11735 : operands[1], INTVAL (operands[2]));
5910 8273 : DONE;
5911 3462 : })
5912 3462 :
5913 3462 : (define_expand "vec_initv2sisi"
5914 : [(match_operand:V2SI 0 "register_operand")
5915 : (match_operand 1)]
5916 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5917 18444 : {
5918 34251 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5919 : operands[1]);
5920 18444 : DONE;
5921 : })
5922 :
5923 2 : (define_expand "vec_set<mode>"
5924 : [(match_operand:V4FI_64 0 "register_operand")
5925 2 : (match_operand:<mmxscalarmode> 1 "register_operand")
5926 2 : (match_operand 2 "vec_setm_mmx_operand")]
5927 2 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5928 9 : {
5929 9 : if (CONST_INT_P (operands[2]))
5930 10 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5931 6 : INTVAL (operands[2]));
5932 : else
5933 7 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5934 9 : DONE;
5935 4 : })
5936 4 :
5937 4 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
5938 : [(match_operand:<mmxscalarmode> 0 "register_operand")
5939 : (match_operand:V4FI_64 1 "register_operand")
5940 : (match_operand 2 "const_int_operand")]
5941 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
5942 825 : {
5943 853 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5944 825 : operands[1], INTVAL (operands[2]));
5945 825 : DONE;
5946 : })
5947 968 :
5948 : (define_expand "vec_initv4hihi"
5949 968 : [(match_operand:V4HI 0 "register_operand")
5950 968 : (match_operand 1)]
5951 968 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5952 3462 : {
5953 3467 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5954 : operands[1]);
5955 3462 : DONE;
5956 : })
5957 :
5958 2 : (define_expand "vec_init<mode><mmxscalarmodelower>"
5959 0 : [(match_operand:V4F_64 0 "register_operand")
5960 2 : (match_operand 1)]
5961 2 : "TARGET_MMX_WITH_SSE"
5962 23 : {
5963 21 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5964 : operands[1]);
5965 21 : DONE;
5966 : })
5967 :
5968 : (define_expand "vec_setv8qi"
5969 1 : [(match_operand:V8QI 0 "register_operand")
5970 : (match_operand:QI 1 "register_operand")
5971 1 : (match_operand 2 "vec_setm_mmx_operand")]
5972 0 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5973 3 : {
5974 2 : if (CONST_INT_P (operands[2]))
5975 0 : ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1],
5976 0 : INTVAL (operands[2]));
5977 : else
5978 29 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
5979 2 : DONE;
5980 27 : })
5981 27 :
5982 27 : (define_expand "vec_extractv8qiqi"
5983 0 : [(match_operand:QI 0 "register_operand")
5984 : (match_operand:V8QI 1 "register_operand")
5985 : (match_operand 2 "const_int_operand")]
5986 : "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
5987 630 : {
5988 630 : ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0],
5989 630 : operands[1], INTVAL (operands[2]));
5990 630 : DONE;
5991 : })
5992 0 :
5993 : (define_expand "vec_initv8qiqi"
5994 0 : [(match_operand:V8QI 0 "register_operand")
5995 0 : (match_operand 1)]
5996 0 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE"
5997 331 : {
5998 335 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
5999 : operands[1]);
6000 331 : DONE;
6001 : })
6002 :
6003 392 : (define_insn "*pinsrw"
6004 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,YW,&x")
6005 392 : (vec_merge:V2FI_32
6006 392 : (vec_duplicate:V2FI_32
6007 392 : (match_operand:<mmxscalarmode> 2 "nonimmediate_operand" "rm,rm,x"))
6008 : (match_operand:V2FI_32 1 "register_operand" "0,YW,x")
6009 : (match_operand:SI 3 "const_int_operand")))]
6010 7 : "TARGET_SSE2
6011 682 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6012 7 : < GET_MODE_NUNITS (V2HImode))"
6013 63 : {
6014 61 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6015 63 : switch (which_alternative)
6016 1152 : {
6017 1152 : case 2:
6018 : return "#";
6019 1 : case 1:
6020 1826 : if (MEM_P (operands[2]))
6021 : return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6022 : else
6023 0 : return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6024 60 : case 0:
6025 60 : if (MEM_P (operands[2]))
6026 : return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
6027 : else
6028 41 : return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6029 0 : default:
6030 0 : gcc_unreachable ();
6031 : }
6032 : }
6033 : [(set_attr "isa" "noavx,avx,sse4")
6034 : (set_attr "type" "sselog")
6035 : (set_attr "c86_attr" "insr")
6036 61 : (set_attr "length_immediate" "1")
6037 : (set_attr "mode" "TI")])
6038 :
6039 : ;; For TARGET_SSE2, implement insert from XMM reg with PSHULFW + PBLENDW.
6040 : (define_split
6041 : [(set (match_operand:V2FI_32 0 "sse_reg_operand")
6042 : (vec_merge:V2FI_32
6043 : (vec_duplicate:V2FI_32
6044 : (match_operand:<mmxscalarmode> 2 "sse_reg_operand"))
6045 : (match_operand:V2FI_32 1 "sse_reg_operand")
6046 : (match_operand:SI 3 "const_int_operand")))]
6047 1 : "TARGET_SSE4_1 && reload_completed
6048 1 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6049 1 : < GET_MODE_NUNITS (<MODE>mode))"
6050 : [(set (match_dup 0)
6051 1 : (vec_duplicate:V2FI_32 (match_dup 2)))
6052 : (set (match_dup 0)
6053 232 : (vec_merge:V2FI_32 (match_dup 1) (match_dup 0) (match_dup 3)))]
6054 233 : "operands[3] = GEN_INT (~INTVAL (operands[3]) & 0x3);")
6055 :
6056 :
6057 233 : (define_insn "*pinsrb"
6058 : [(set (match_operand:V4QI 0 "register_operand" "=x,YW")
6059 1408332 : (vec_merge:V4QI
6060 : (vec_duplicate:V4QI
6061 1408332 : (match_operand:QI 2 "nonimmediate_operand" "jrjm,rm"))
6062 1408333 : (match_operand:V4QI 1 "register_operand" "0,YW")
6063 1408332 : (match_operand:SI 3 "const_int_operand")))]
6064 1408332 : "TARGET_SSE4_1
6065 1408332 : && ((unsigned) exact_log2 (INTVAL (operands[3]))
6066 0 : < GET_MODE_NUNITS (V4QImode))"
6067 1094048 : {
6068 1093970 : operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6069 93 : switch (which_alternative)
6070 93 : {
6071 93 : case 1:
6072 0 : if (MEM_P (operands[2]))
6073 15 : return "vpinsrb\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6074 3277 : else
6075 3277 : return "vpinsrb\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6076 0 : case 0:
6077 95 : if (MEM_P (operands[2]))
6078 95 : return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
6079 : else
6080 0 : return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6081 0 : default:
6082 0 : gcc_unreachable ();
6083 0 : }
6084 0 : }
6085 : [(set_attr "isa" "noavx,avx")
6086 : (set_attr "addr" "gpr16,*")
6087 : (set_attr "type" "sselog")
6088 : (set_attr "c86_attr" "insr")
6089 : (set_attr "prefix_extra" "1")
6090 : (set_attr "length_immediate" "1")
6091 : (set_attr "prefix" "orig,vex")
6092 : (set_attr "mode" "TI")])
6093 :
6094 7 : (define_insn "*pextrw"
6095 : [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,jm,m")
6096 : (vec_select:HI
6097 : (match_operand:V2HI 1 "register_operand" "YW,YW,YW")
6098 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6099 628 : "TARGET_SSE2"
6100 : "@
6101 : %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
6102 : pextrw\t{%2, %1, %0|%0, %1, %2}
6103 19755 : vpextrw\t{%2, %1, %0|%0, %1, %2}"
6104 19755 : [(set_attr "isa" "*,sse4_noavx,avx")
6105 19582 : (set_attr "addr" "*,gpr16,*")
6106 39337 : (set_attr "type" "sselog1")
6107 : (set_attr "c86_attr" "extr")
6108 : (set_attr "length_immediate" "1")
6109 : (set_attr "prefix" "maybe_vex")
6110 : (set_attr "mode" "TI")])
6111 :
6112 : (define_insn "*pextrw<mode>"
6113 : [(set (match_operand:<mmxscalarmode> 0 "register_sse4nonimm_operand" "=?r,jm,m,x,Yw")
6114 : (vec_select:<mmxscalarmode>
6115 : (match_operand:V2F_32 1 "register_operand" "YW,YW,YW,0,YW")
6116 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
6117 62 : "TARGET_SSE2"
6118 13 : {
6119 7 : switch (which_alternative)
6120 : {
6121 4224 : case 0:
6122 4224 : return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
6123 4077 : case 1:
6124 8301 : return "pextrw\t{%2, %1, %0|%0, %1, %2}";
6125 0 : case 2:
6126 0 : return "vpextrw\t{%2, %1, %0|%0, %1, %2}";
6127 1 : case 3:
6128 1 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6129 1 : return "psrldq\t{%2, %0|%0, %2}";
6130 6 : case 4:
6131 6 : operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
6132 6 : return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
6133 :
6134 0 : default:
6135 0 : gcc_unreachable ();
6136 : }
6137 : }
6138 : [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
6139 : (set_attr "addr" "*,gpr16,*,*,*")
6140 : (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
6141 0 : (set_attr "c86_attr" "extr,extr,extr,*,*")
6142 : (set_attr "length_immediate" "1")
6143 : (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
6144 : (set_attr "mode" "TI")])
6145 :
6146 : (define_insn "*pextrw_zext"
6147 : [(set (match_operand:SWI48 0 "register_operand" "=r")
6148 0 : (zero_extend:SWI48
6149 : (vec_select:HI
6150 : (match_operand:V2HI 1 "register_operand" "YW")
6151 : (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
6152 5105 : "TARGET_SSE2"
6153 : "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
6154 : [(set_attr "type" "sselog1")
6155 : (set_attr "c86_attr" "extr")
6156 50858 : (set_attr "length_immediate" "1")
6157 50858 : (set_attr "prefix" "maybe_vex")
6158 : (set_attr "mode" "TI")])
6159 :
6160 : (define_insn "*pextrb"
6161 : [(set (match_operand:QI 0 "nonimmediate_operand" "=jr,jm,r,m")
6162 : (vec_select:QI
6163 : (match_operand:V4QI 1 "register_operand" "YW,YW,YW,YW")
6164 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
6165 109 : "TARGET_SSE4_1"
6166 : "@
6167 : pextrb\t{%2, %1, %k0|%k0, %1, %2}
6168 : pextrb\t{%2, %1, %0|%0, %1, %2}
6169 : vpextrb\t{%2, %1, %k0|%k0, %1, %2}
6170 : vpextrb\t{%2, %1, %0|%0, %1, %2}"
6171 : [(set_attr "isa" "noavx,noavx,avx,avx")
6172 : (set_attr "addr" "*,gpr16,*,*")
6173 5296 : (set_attr "type" "sselog1")
6174 5296 : (set_attr "c86_attr" "extr")
6175 2883 : (set_attr "prefix_extra" "1")
6176 8179 : (set_attr "length_immediate" "1")
6177 : (set_attr "prefix" "maybe_vex")
6178 : (set_attr "mode" "TI")])
6179 :
6180 : (define_insn "*pextrb_zext"
6181 : [(set (match_operand:SWI248 0 "register_operand" "=jr,r")
6182 : (zero_extend:SWI248
6183 : (vec_select:QI
6184 : (match_operand:V4QI 1 "register_operand" "YW,YW")
6185 : (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
6186 386 : "TARGET_SSE4_1"
6187 : "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
6188 : [(set_attr "isa" "noavx,avx")
6189 : (set_attr "type" "sselog1")
6190 14050 : (set_attr "c86_attr" "extr")
6191 14050 : (set_attr "prefix_extra" "1")
6192 : (set_attr "length_immediate" "1")
6193 : (set_attr "prefix" "maybe_vex")
6194 : (set_attr "mode" "TI")])
6195 :
6196 : (define_expand "vec_set<mode>"
6197 : [(match_operand:V2FI_32 0 "register_operand")
6198 : (match_operand:<mmxscalarmode> 1 "register_operand")
6199 : (match_operand 2 "vec_setm_sse41_operand")]
6200 : "TARGET_SSE2"
6201 29 : {
6202 29 : if (CONST_INT_P (operands[2]))
6203 26 : ix86_expand_vector_set (false, operands[0], operands[1],
6204 26 : INTVAL (operands[2]));
6205 : else
6206 3 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6207 29 : DONE;
6208 : })
6209 :
6210 : (define_expand "vec_extract<mode><mmxscalarmodelower>"
6211 : [(match_operand:<mmxscalarmode> 0 "register_operand")
6212 : (match_operand:V2FI_32 1 "register_operand")
6213 : (match_operand 2 "const_int_operand")]
6214 : "TARGET_SSE2"
6215 399 : {
6216 399 : ix86_expand_vector_extract (false, operands[0],
6217 399 : operands[1], INTVAL (operands[2]));
6218 399 : DONE;
6219 : })
6220 314 :
6221 : (define_expand "vec_setv4qi"
6222 314 : [(match_operand:V4QI 0 "register_operand")
6223 314 : (match_operand:QI 1 "register_operand")
6224 314 : (match_operand 2 "vec_setm_mmx_operand")]
6225 : "TARGET_SSE4_1"
6226 2 : {
6227 2 : if (CONST_INT_P (operands[2]))
6228 0 : ix86_expand_vector_set (false, operands[0], operands[1],
6229 0 : INTVAL (operands[2]));
6230 : else
6231 4317 : ix86_expand_vector_set_var (operands[0], operands[1], operands[2]);
6232 182 : DONE;
6233 4315 : })
6234 4495 :
6235 4315 : (define_expand "vec_extractv4qiqi"
6236 180 : [(match_operand:QI 0 "register_operand")
6237 : (match_operand:V4QI 1 "register_operand")
6238 : (match_operand 2 "const_int_operand")]
6239 : "TARGET_SSE4_1"
6240 78 : {
6241 78 : ix86_expand_vector_extract (false, operands[0],
6242 78 : operands[1], INTVAL (operands[2]));
6243 78 : DONE;
6244 : })
6245 22 :
6246 : (define_insn_and_split "*punpckwd"
6247 22 : [(set (match_operand:V2FI_32 0 "register_operand" "=x,Yw")
6248 22 : (vec_select:V2FI_32
6249 22 : (vec_concat:<mmxdoublevecmode>
6250 : (match_operand:V2FI_32 1 "register_operand" "0,Yw")
6251 : (match_operand:V2FI_32 2 "register_operand" "x,Yw"))
6252 : (parallel [(match_operand 3 "const_0_to_3_operand")
6253 : (match_operand 4 "const_0_to_3_operand")])))]
6254 0 : "TARGET_SSE2"
6255 : "#"
6256 363 : "&& reload_completed"
6257 : [(set (match_dup 5)
6258 2342 : (vec_select:<mmxxmmmode>
6259 2162 : (match_dup 5)
6260 723 : (parallel [(match_dup 3) (match_dup 4)
6261 360 : (const_int 2) (const_int 3)
6262 5493 : (const_int 4) (const_int 5)
6263 5493 : (const_int 6) (const_int 7)])))]
6264 942 : {
6265 952 : rtx dest = lowpart_subreg (<mmxxmmmode>mode, operands[0], <MODE>mode);
6266 180 : rtx op1 = lowpart_subreg (<mmxxmmmode>mode, operands[1], <MODE>mode);
6267 180 : rtx op2 = lowpart_subreg (<mmxxmmmode>mode, operands[2], <MODE>mode);
6268 :
6269 180 : emit_insn (gen_vec_interleave_low<mmxxmmmodelower> (dest, op1, op2));
6270 :
6271 180 : static const int map[4] = { 0, 2, 1, 3 };
6272 :
6273 180 : int sel0 = map[INTVAL (operands[3])];
6274 180 : int sel1 = map[INTVAL (operands[4])];
6275 :
6276 180 : if (sel0 == 0 && sel1 == 1)
6277 69 : DONE;
6278 :
6279 111 : operands[3] = GEN_INT (sel0);
6280 111 : operands[4] = GEN_INT (sel1);
6281 111 : operands[5] = dest;
6282 : }
6283 : [(set_attr "isa" "noavx,avx")
6284 : (set_attr "type" "sselog")
6285 111 : (set_attr "mode" "TI")])
6286 :
6287 : (define_insn "*pshufw<mode>_1"
6288 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6289 : (vec_select:V2FI_32
6290 : (match_operand:V2FI_32 1 "register_operand" "Yw")
6291 111 : (parallel [(match_operand 2 "const_0_to_1_operand")
6292 : (match_operand 3 "const_0_to_1_operand")])))]
6293 0 : "TARGET_SSE2"
6294 82 : {
6295 82 : int mask = 0;
6296 96 : mask |= INTVAL (operands[2]) << 0;
6297 1855 : mask |= INTVAL (operands[3]) << 2;
6298 1869 : mask |= 2 << 4;
6299 1707 : mask |= 3 << 6;
6300 1625 : operands[2] = GEN_INT (mask);
6301 3073 :
6302 150124 : return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
6303 28301 : }
6304 15404 : [(set_attr "type" "sselog1")
6305 1263 : (set_attr "length_immediate" "1")
6306 1263 : (set_attr "mode" "TI")])
6307 150166 :
6308 : (define_insn "*vec_dupv2hi"
6309 : [(set (match_operand:V2HI 0 "register_operand" "=Yw")
6310 : (vec_duplicate:V2HI
6311 : (truncate:HI
6312 : (match_operand:SI 1 "register_operand" "Yw"))))]
6313 246 : "TARGET_SSE2"
6314 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6315 : [(set_attr "type" "sselog1")
6316 : (set_attr "length_immediate" "1")
6317 : (set_attr "mode" "TI")])
6318 :
6319 : (define_insn "*vec_dup<mode>"
6320 : [(set (match_operand:V2FI_32 0 "register_operand" "=Yw")
6321 : (vec_duplicate:V2FI_32
6322 : (match_operand:<mmxscalarmode> 1 "register_operand" "Yw")))]
6323 18 : "TARGET_SSE2"
6324 52 : "%vpshuflw\t{$0, %1, %0|%0, %1, 0}"
6325 : [(set_attr "type" "sselog1")
6326 : (set_attr "length_immediate" "1")
6327 13196605 : (set_attr "mode" "TI")])
6328 1007 :
6329 960 : (define_expand "vec_init<mode><mmxscalarmodelower>"
6330 960 : [(match_operand:V2FI_32 0 "register_operand")
6331 1967 : (match_operand 1)]
6332 1006 : "TARGET_SSE2"
6333 13195912 : {
6334 13196975 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6335 13196604 : operands[1]);
6336 1320 : DONE;
6337 13195598 : })
6338 1006 :
6339 13195598 : (define_expand "vec_initv4qiqi"
6340 760 : [(match_operand:V2HI 0 "register_operand")
6341 760 : (match_operand 1)]
6342 760 : "TARGET_SSE2"
6343 5879 : {
6344 7042446 : ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0],
6345 7038153 : operands[1]);
6346 7042428 : DONE;
6347 7038153 : })
6348 :
6349 3118120 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6350 3118110 : ;;
6351 3085007 : ;; Miscellaneous
6352 6032011 : ;;
6353 10 : ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6354 :
6355 : (define_expand "mmx_uavg<mode>3"
6356 : [(set (match_operand:MMXMODE12 0 "register_operand")
6357 : (truncate:MMXMODE12
6358 : (lshiftrt:<mmxdoublemode>
6359 16 : (plus:<mmxdoublemode>
6360 : (plus:<mmxdoublemode>
6361 16 : (zero_extend:<mmxdoublemode>
6362 16 : (match_operand:MMXMODE12 1 "register_mmxmem_operand"))
6363 16 : (zero_extend:<mmxdoublemode>
6364 : (match_operand:MMXMODE12 2 "register_mmxmem_operand")))
6365 : (match_dup 3))
6366 : (const_int 1))))]
6367 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6368 : && (TARGET_SSE || TARGET_3DNOW)"
6369 62 : {
6370 62 : operands[3] = CONST1_RTX(<mmxdoublemode>mode);
6371 62 : ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
6372 : })
6373 :
6374 : (define_insn "*mmx_uavgv8qi3"
6375 : [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
6376 62 : (truncate:V8QI
6377 : (lshiftrt:V8HI
6378 : (plus:V8HI
6379 : (plus:V8HI
6380 : (zero_extend:V8HI
6381 62 : (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw"))
6382 : (zero_extend:V8HI
6383 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")))
6384 : (const_vector:V8HI [(const_int 1) (const_int 1)
6385 : (const_int 1) (const_int 1)
6386 343 : (const_int 1) (const_int 1)
6387 : (const_int 1) (const_int 1)]))
6388 343 : (const_int 1))))]
6389 584 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6390 584 : && (TARGET_SSE || TARGET_3DNOW)
6391 241 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6392 220 : {
6393 42 : switch (which_alternative)
6394 : {
6395 165 : case 2:
6396 165 : return "vpavgb\t{%2, %1, %0|%0, %1, %2}";
6397 181 : case 1:
6398 16 : case 0:
6399 165 : /* These two instructions have the same operation, but their encoding
6400 165 : is different. Prefer the one that is de facto standard. */
6401 16 : if (TARGET_SSE || TARGET_3DNOW_A)
6402 165 : return "pavgb\t{%2, %0|%0, %2}";
6403 165 : else
6404 0 : return "pavgusb\t{%2, %0|%0, %2}";
6405 165 : default:
6406 165 : gcc_unreachable ();
6407 : }
6408 165 : }
6409 : [(set_attr "isa" "*,sse2_noavx,avx")
6410 145 : (set_attr "mmx_isa" "native,*,*")
6411 145 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6412 : (set (attr "prefix_extra")
6413 : (if_then_else
6414 204 : (not (ior (match_test "TARGET_SSE")
6415 145 : (match_test "TARGET_3DNOW_A")))
6416 : (const_string "1")
6417 0 : (const_string "*")))
6418 : (set_attr "mode" "DI,TI,TI")])
6419 :
6420 : (define_insn "*mmx_uavgv4hi3"
6421 : [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yw")
6422 : (truncate:V4HI
6423 : (lshiftrt:V4SI
6424 167428 : (plus:V4SI
6425 167428 : (plus:V4SI
6426 167428 : (zero_extend:V4SI
6427 167428 : (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yw"))
6428 167428 : (zero_extend:V4SI
6429 : (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yw")))
6430 : (const_vector:V4SI [(const_int 1) (const_int 1)
6431 : (const_int 1) (const_int 1)]))
6432 : (const_int 1))))]
6433 133 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6434 133 : && (TARGET_SSE || TARGET_3DNOW_A)
6435 133 : && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6436 : "@
6437 152 : pavgw\t{%2, %0|%0, %2}
6438 152 : pavgw\t{%2, %0|%0, %2}
6439 172 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6440 172 : [(set_attr "isa" "*,sse2_noavx,avx")
6441 152 : (set_attr "mmx_isa" "native,*,*")
6442 152 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6443 20 : (set_attr "mode" "DI,TI,TI")])
6444 :
6445 10728 : (define_expand "uavg<mode>3_ceil"
6446 : [(set (match_operand:MMXMODE12 0 "register_operand")
6447 : (truncate:MMXMODE12
6448 : (lshiftrt:<mmxdoublemode>
6449 : (plus:<mmxdoublemode>
6450 : (plus:<mmxdoublemode>
6451 76 : (zero_extend:<mmxdoublemode>
6452 76 : (match_operand:MMXMODE12 1 "register_operand"))
6453 76 : (zero_extend:<mmxdoublemode>
6454 76 : (match_operand:MMXMODE12 2 "register_operand")))
6455 76 : (match_dup 3))
6456 : (const_int 1))))]
6457 : "TARGET_MMX_WITH_SSE"
6458 4 : "operands[3] = CONST1_RTX(<mmxdoublemode>mode);")
6459 :
6460 : (define_insn "uavgv4qi3_ceil"
6461 : [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
6462 4 : (truncate:V4QI
6463 : (lshiftrt:V4HI
6464 786001 : (plus:V4HI
6465 786001 : (plus:V4HI
6466 786001 : (zero_extend:V4HI
6467 4 : (match_operand:V4QI 1 "register_operand" "%0,Yw"))
6468 : (zero_extend:V4HI
6469 : (match_operand:V4QI 2 "register_operand" "x,Yw")))
6470 : (const_vector:V4HI [(const_int 1) (const_int 1)
6471 : (const_int 1) (const_int 1)]))
6472 30 : (const_int 1))))]
6473 5 : "TARGET_SSE2"
6474 30 : "@
6475 30 : pavgb\t{%2, %0|%0, %2}
6476 30 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6477 : [(set_attr "isa" "noavx,avx")
6478 : (set_attr "type" "sseiadd")
6479 : (set_attr "mode" "TI")])
6480 :
6481 222 : (define_insn "uavgv2qi3_ceil"
6482 222 : [(set (match_operand:V2QI 0 "register_operand" "=x,Yw")
6483 222 : (truncate:V2QI
6484 : (lshiftrt:V2HI
6485 222 : (plus:V2HI
6486 222 : (plus:V2HI
6487 : (zero_extend:V2HI
6488 222 : (match_operand:V2QI 1 "register_operand" "%0,Yw"))
6489 : (zero_extend:V2HI
6490 202 : (match_operand:V2QI 2 "register_operand" "x,Yw")))
6491 202 : (const_vector:V2HI [(const_int 1) (const_int 1)]))
6492 : (const_int 1))))]
6493 110 : "TARGET_SSE2"
6494 202 : "@
6495 : pavgb\t{%2, %0|%0, %2}
6496 : vpavgb\t{%2, %1, %0|%0, %1, %2}"
6497 20 : [(set_attr "isa" "noavx,avx")
6498 20 : (set_attr "type" "sseiadd")
6499 : (set_attr "mode" "TI")])
6500 :
6501 20 : (define_insn "uavgv2hi3_ceil"
6502 : [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
6503 : (truncate:V2HI
6504 : (lshiftrt:V2SI
6505 : (plus:V2SI
6506 : (plus:V2SI
6507 : (zero_extend:V2SI
6508 : (match_operand:V2HI 1 "register_operand" "%0,Yw"))
6509 : (zero_extend:V2SI
6510 : (match_operand:V2HI 2 "register_operand" "x,Yw")))
6511 : (const_vector:V2SI [(const_int 1) (const_int 1)]))
6512 : (const_int 1))))]
6513 5 : "TARGET_SSE2"
6514 : "@
6515 : pavgw\t{%2, %0|%0, %2}
6516 : vpavgw\t{%2, %1, %0|%0, %1, %2}"
6517 : [(set_attr "isa" "noavx,avx")
6518 : (set_attr "type" "sseiadd")
6519 : (set_attr "mode" "TI")])
6520 :
6521 : (define_expand "mmx_psadbw"
6522 : [(set (match_operand:V1DI 0 "register_operand")
6523 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand")
6524 : (match_operand:V8QI 2 "register_mmxmem_operand")]
6525 517 : UNSPEC_PSADBW))]
6526 517 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)"
6527 880 : "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
6528 :
6529 512 : (define_insn "*mmx_psadbw"
6530 512 : [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yw")
6531 875 : (unspec:V1DI [(match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yw")
6532 512 : (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")]
6533 512 : UNSPEC_PSADBW))]
6534 5952 : "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)
6535 6315 : && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
6536 4459 : "@
6537 512 : psadbw\t{%2, %0|%0, %2}
6538 512 : psadbw\t{%2, %0|%0, %2}
6539 837 : vpsadbw\t{%2, %1, %0|%0, %1, %2}"
6540 1000 : [(set_attr "isa" "*,sse2_noavx,avx")
6541 163 : (set_attr "mmx_isa" "native,*,*")
6542 836 : (set_attr "type" "mmxshft,sseiadd,sseiadd")
6543 0 : (set_attr "c86_attr" "sadbw")
6544 359 : (set_attr "mode" "DI,TI,TI")])
6545 338 :
6546 137 : (define_expand "reduc_<code>_scal_<mode>"
6547 120 : [(any_logic:MMXMODE12
6548 403 : (match_operand:<mmxscalarmode> 0 "register_operand")
6549 : (match_operand:MMXMODE12 1 "register_operand"))]
6550 : "TARGET_MMX_WITH_SSE"
6551 44 : {
6552 44 : rtx tmp = gen_reg_rtx (<MODE>mode);
6553 44 : ix86_expand_reduc (gen_<code><mode>3, tmp, operands[1]);
6554 44 : emit_insn (gen_vec_extract<mode><mmxscalarmodelower> (operands[0],
6555 : tmp, const0_rtx));
6556 44 : DONE;
6557 : })
6558 :
6559 : (define_expand "reduc_<code>_scal_v4qi"
6560 : [(any_logic:V4QI
6561 : (match_operand:QI 0 "register_operand")
6562 : (match_operand:V4QI 1 "register_operand"))]
6563 : "TARGET_SSE2"
6564 30 : {
6565 30 : rtx tmp = gen_reg_rtx (V4QImode);
6566 30 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6567 30 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6568 30 : DONE;
6569 243 : })
6570 :
6571 243 : (define_expand "reduc_plus_scal_v8qi"
6572 243 : [(plus:V8QI
6573 243 : (match_operand:QI 0 "register_operand")
6574 : (match_operand:V8QI 1 "register_operand"))]
6575 : "TARGET_MMX_WITH_SSE"
6576 335 : {
6577 335 : rtx tmp = gen_reg_rtx (V8QImode);
6578 335 : emit_move_insn (tmp, CONST0_RTX (V8QImode));
6579 335 : rtx tmp2 = gen_reg_rtx (V1DImode);
6580 335 : emit_insn (gen_mmx_psadbw (tmp2, operands[1], tmp));
6581 341 : tmp2 = gen_lowpart (V8QImode, tmp2);
6582 335 : emit_insn (gen_vec_extractv8qiqi (operands[0], tmp2, const0_rtx));
6583 341 : DONE;
6584 6 : })
6585 6 :
6586 : (define_expand "reduc_plus_scal_v4hi"
6587 : [(plus:V4HI
6588 : (match_operand:HI 0 "register_operand")
6589 : (match_operand:V4HI 1 "register_operand"))]
6590 : "TARGET_MMX_WITH_SSE"
6591 231 : {
6592 231 : rtx tmp = gen_reg_rtx (V4HImode);
6593 231 : ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]);
6594 231 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6595 231 : DONE;
6596 5 : })
6597 :
6598 5 : (define_expand "reduc_<code>_scal_v4hi"
6599 5 : [(smaxmin:V4HI
6600 5 : (match_operand:HI 0 "register_operand")
6601 : (match_operand:V4HI 1 "register_operand"))]
6602 : "TARGET_MMX_WITH_SSE"
6603 4 : {
6604 4 : rtx tmp = gen_reg_rtx (V4HImode);
6605 4 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6606 4 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6607 4 : DONE;
6608 314 : })
6609 :
6610 314 : (define_expand "reduc_<code>_scal_v4qi"
6611 314 : [(smaxmin:V4QI
6612 314 : (match_operand:QI 0 "register_operand")
6613 : (match_operand:V4QI 1 "register_operand"))]
6614 : "TARGET_SSE4_1"
6615 4 : {
6616 4 : rtx tmp = gen_reg_rtx (V4QImode);
6617 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6618 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6619 4 : DONE;
6620 16 : })
6621 :
6622 16 : (define_expand "reduc_<code>_scal_v4hi"
6623 16 : [(umaxmin:V4HI
6624 16 : (match_operand:HI 0 "register_operand")
6625 : (match_operand:V4HI 1 "register_operand"))]
6626 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6627 6 : {
6628 6 : rtx tmp = gen_reg_rtx (V4HImode);
6629 6 : ix86_expand_reduc (gen_<code>v4hi3, tmp, operands[1]);
6630 6 : emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx));
6631 6 : DONE;
6632 12 : })
6633 :
6634 12 : (define_expand "reduc_<code>_scal_v4qi"
6635 12 : [(umaxmin:V4QI
6636 12 : (match_operand:QI 0 "register_operand")
6637 : (match_operand:V4QI 1 "register_operand"))]
6638 : "TARGET_SSE4_1"
6639 4 : {
6640 4 : rtx tmp = gen_reg_rtx (V4QImode);
6641 4 : ix86_expand_reduc (gen_<code>v4qi3, tmp, operands[1]);
6642 4 : emit_insn (gen_vec_extractv4qiqi (operands[0], tmp, const0_rtx));
6643 4 : DONE;
6644 45 : })
6645 :
6646 45 : (define_expand "reduc_plus_scal_v4qi"
6647 45 : [(plus:V4QI
6648 45 : (match_operand:QI 0 "register_operand")
6649 : (match_operand:V4QI 1 "register_operand"))]
6650 : "TARGET_SSE2"
6651 314 : {
6652 314 : rtx op1 = gen_reg_rtx (V16QImode);
6653 314 : emit_insn (gen_vec_setv4si_0 (lowpart_subreg (V4SImode, op1, V16QImode),
6654 : CONST0_RTX (V4SImode),
6655 : lowpart_subreg (SImode,
6656 1 : operands[1],
6657 22 : V4QImode)));
6658 315 : rtx tmp = gen_reg_rtx (V16QImode);
6659 337 : emit_move_insn (tmp, CONST0_RTX (V16QImode));
6660 314 : rtx tmp2 = gen_reg_rtx (V2DImode);
6661 336 : emit_insn (gen_sse2_psadbw (tmp2, op1, tmp));
6662 314 : tmp2 = gen_lowpart (V16QImode, tmp2);
6663 315 : emit_insn (gen_vec_extractv16qiqi (operands[0], tmp2, const0_rtx));
6664 314 : DONE;
6665 : })
6666 :
6667 : (define_expand "usadv8qi"
6668 15 : [(match_operand:V2SI 0 "register_operand")
6669 : (match_operand:V8QI 1 "register_operand")
6670 15 : (match_operand:V8QI 2 "register_operand")
6671 15 : (match_operand:V2SI 3 "register_operand")]
6672 : "TARGET_MMX_WITH_SSE"
6673 5 : {
6674 5 : rtx t1 = gen_reg_rtx (V1DImode);
6675 5 : rtx t2 = gen_reg_rtx (V2SImode);
6676 5 : emit_insn (gen_mmx_psadbw (t1, operands[1], operands[2]));
6677 19677 : convert_move (t2, t1, 0);
6678 5 : emit_insn (gen_addv2si3 (operands[0], t2, operands[3]));
6679 19677 : DONE;
6680 19672 : })
6681 19672 :
6682 : (define_expand "usdot_prodv2siv8qi"
6683 : [(match_operand:V2SI 0 "register_operand")
6684 : (match_operand:V8QI 1 "register_operand")
6685 : (match_operand:V8QI 2 "register_operand")
6686 : (match_operand:V2SI 3 "register_operand")]
6687 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6688 7 : {
6689 7 : operands[1] = force_reg (V8QImode, operands[1]);
6690 7 : operands[2] = force_reg (V8QImode, operands[2]);
6691 7 : operands[3] = force_reg (V2SImode, operands[3]);
6692 :
6693 112 : if ((TARGET_AVX512VNNI && TARGET_AVX512VL)
6694 5 : || TARGET_AVXVNNI)
6695 105 : {
6696 110 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6697 5 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6698 5 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6699 5 : rtx op0 = gen_reg_rtx (V4SImode);
6700 :
6701 5 : emit_insn (gen_usdot_prodv4siv16qi (op0, op1, op2, op3));
6702 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6703 5 : }
6704 : else
6705 : {
6706 2 : rtx op1 = gen_reg_rtx (V8HImode);
6707 2 : rtx op2 = gen_reg_rtx (V8HImode);
6708 2 : rtx op3 = gen_reg_rtx (V4SImode);
6709 2 : rtx op0 = gen_reg_rtx (V4SImode);
6710 2 : rtx op0_1 = gen_reg_rtx (V4SImode);
6711 :
6712 2 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6713 2 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6714 2 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6715 2 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6716 :
6717 : /* vec_perm (op0, 2, 3, 0, 1); */
6718 2 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6719 2 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6720 2 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6721 : lowpart_subreg (V2SImode, op0, V4SImode)));
6722 : }
6723 7 : DONE;
6724 : })
6725 :
6726 : (define_expand "sdot_prodv2siv8qi"
6727 : [(match_operand:V2SI 0 "register_operand")
6728 : (match_operand:V8QI 1 "register_operand")
6729 : (match_operand:V8QI 2 "register_operand")
6730 : (match_operand:V2SI 3 "register_operand")]
6731 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6732 9 : {
6733 9 : operands[1] = force_reg (V8QImode, operands[1]);
6734 9 : operands[2] = force_reg (V8QImode, operands[2]);
6735 9 : operands[3] = force_reg (V2SImode, operands[3]);
6736 :
6737 495857 : if (TARGET_AVXVNNIINT8)
6738 : {
6739 495853 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6740 495853 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6741 495853 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6742 5 : rtx op0 = gen_reg_rtx (V4SImode);
6743 :
6744 5 : emit_insn (gen_sdot_prodv4siv16qi (op0, op1, op2, op3));
6745 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6746 : }
6747 : else
6748 : {
6749 4 : rtx op1 = gen_reg_rtx (V8HImode);
6750 4 : rtx op2 = gen_reg_rtx (V8HImode);
6751 4 : rtx op3 = gen_reg_rtx (V4SImode);
6752 4 : rtx op0 = gen_reg_rtx (V4SImode);
6753 4 : rtx op0_1 = gen_reg_rtx (V4SImode);
6754 :
6755 4 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6756 4 : emit_insn (gen_extendv8qiv8hi2 (op1, operands[1]));
6757 4 : emit_insn (gen_extendv8qiv8hi2 (op2, operands[2]));
6758 4 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6759 :
6760 : /* vec_perm (op0, 2, 3, 0, 1); */
6761 4 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6762 4 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6763 4 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6764 : lowpart_subreg (V2SImode, op0, V4SImode)));
6765 : }
6766 9 : DONE;
6767 :
6768 : })
6769 :
6770 : (define_expand "udot_prodv2siv8qi"
6771 : [(match_operand:V2SI 0 "register_operand")
6772 : (match_operand:V8QI 1 "register_operand")
6773 : (match_operand:V8QI 2 "register_operand")
6774 : (match_operand:V2SI 3 "register_operand")]
6775 : "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
6776 9 : {
6777 9 : operands[1] = force_reg (V8QImode, operands[1]);
6778 9 : operands[2] = force_reg (V8QImode, operands[2]);
6779 9 : operands[3] = force_reg (V2SImode, operands[3]);
6780 :
6781 207 : if (TARGET_AVXVNNIINT8)
6782 : {
6783 203 : rtx op1 = lowpart_subreg (V16QImode, operands[1], V8QImode);
6784 203 : rtx op2 = lowpart_subreg (V16QImode, operands[2], V8QImode);
6785 203 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6786 5 : rtx op0 = gen_reg_rtx (V4SImode);
6787 :
6788 5 : emit_insn (gen_udot_prodv4siv16qi (op0, op1, op2, op3));
6789 5 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6790 : }
6791 : else
6792 : {
6793 4 : rtx op1 = gen_reg_rtx (V8HImode);
6794 4 : rtx op2 = gen_reg_rtx (V8HImode);
6795 4 : rtx op3 = gen_reg_rtx (V4SImode);
6796 4 : rtx op0 = gen_reg_rtx (V4SImode);
6797 4 : rtx op0_1 = gen_reg_rtx (V4SImode);
6798 :
6799 4 : emit_move_insn (op3, CONST0_RTX (V4SImode));
6800 4 : emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1]));
6801 4 : emit_insn (gen_zero_extendv8qiv8hi2 (op2, operands[2]));
6802 4 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6803 :
6804 : /* vec_perm (op0, 2, 3, 0, 1); */
6805 4 : emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78)));
6806 4 : emit_insn (gen_addv4si3 (op0, op0, op0_1));
6807 4 : emit_insn (gen_addv2si3 (operands[0], operands[3],
6808 : lowpart_subreg (V2SImode, op0, V4SImode)));
6809 : }
6810 9 : DONE;
6811 :
6812 : })
6813 :
6814 : (define_expand "usdot_prodv2siv4hi"
6815 : [(match_operand:V2SI 0 "register_operand")
6816 : (match_operand:V4HI 1 "register_operand")
6817 : (match_operand:V4HI 2 "register_operand")
6818 : (match_operand:V2SI 3 "register_operand")]
6819 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6820 3 : {
6821 3 : operands[1] = force_reg (V4HImode, operands[1]);
6822 3 : operands[2] = force_reg (V4HImode, operands[2]);
6823 3 : operands[3] = force_reg (V2SImode, operands[3]);
6824 :
6825 16609 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6826 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6827 16609 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6828 16609 : rtx op0 = gen_reg_rtx (V4SImode);
6829 16606 :
6830 3 : emit_insn (gen_usdot_prodv4siv8hi (op0, op1, op2, op3));
6831 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6832 3 : DONE;
6833 : })
6834 :
6835 : (define_expand "udot_prodv2siv4hi"
6836 : [(match_operand:V2SI 0 "register_operand")
6837 : (match_operand:V4HI 1 "register_operand")
6838 : (match_operand:V4HI 2 "register_operand")
6839 : (match_operand:V2SI 3 "register_operand")]
6840 : "TARGET_AVXVNNIINT16 && TARGET_MMX_WITH_SSE"
6841 3 : {
6842 3 : operands[1] = force_reg (V4HImode, operands[1]);
6843 3 : operands[2] = force_reg (V4HImode, operands[2]);
6844 3 : operands[3] = force_reg (V2SImode, operands[3]);
6845 :
6846 9275 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6847 3 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6848 9275 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6849 9275 : rtx op0 = gen_reg_rtx (V4SImode);
6850 9272 :
6851 3 : emit_insn (gen_udot_prodv4siv8hi (op0, op1, op2, op3));
6852 3 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6853 3 : DONE;
6854 : })
6855 :
6856 : (define_expand "sdot_prodv2siv4hi"
6857 : [(match_operand:V2SI 0 "register_operand")
6858 : (match_operand:V4HI 1 "register_operand")
6859 : (match_operand:V4HI 2 "register_operand")
6860 : (match_operand:V2SI 3 "register_operand")]
6861 : "TARGET_MMX_WITH_SSE"
6862 42 : {
6863 42 : operands[1] = force_reg (V4HImode, operands[1]);
6864 42 : operands[2] = force_reg (V4HImode, operands[2]);
6865 42 : operands[3] = force_reg (V2SImode, operands[3]);
6866 :
6867 15030 : rtx op1 = lowpart_subreg (V8HImode, operands[1], V4HImode);
6868 42 : rtx op2 = lowpart_subreg (V8HImode, operands[2], V4HImode);
6869 15030 : rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode);
6870 15030 : rtx op0 = gen_reg_rtx (V4SImode);
6871 14988 :
6872 42 : emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3));
6873 42 : emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode));
6874 42 : DONE;
6875 : })
6876 :
6877 : (define_insn_and_split "mmx_pmovmskb"
6878 : [(set (match_operand:SI 0 "register_operand" "=r,r,jr")
6879 : (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x,x")]
6880 : UNSPEC_MOVMSK))]
6881 111 : "(TARGET_MMX || TARGET_MMX_WITH_SSE)
6882 111 : && (TARGET_SSE || TARGET_3DNOW_A)"
6883 : "@
6884 : pmovmskb\t{%1, %0|%0, %1}
6885 : #
6886 109 : #"
6887 153 : "TARGET_SSE2 && reload_completed
6888 120693 : && SSE_REGNO_P (REGNO (operands[1]))"
6889 22 : [(set (match_dup 0)
6890 128655 : (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
6891 128655 : (set (match_dup 0)
6892 120562 : (zero_extend:SI (match_dup 2)))]
6893 2428 : {
6894 2406 : /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */
6895 44 : operands[1] = lowpart_subreg (V16QImode, operands[1],
6896 22 : GET_MODE (operands[1]));
6897 44 : operands[2] = lowpart_subreg (QImode, operands[0],
6898 22 : GET_MODE (operands[0]));
6899 0 : }
6900 0 : [(set_attr "mmx_isa" "native,sse_noavx,avx")
6901 : (set_attr "type" "mmxcvt,ssemov,ssemov")
6902 22 : (set_attr "mode" "DI,TI,TI")])
6903 :
6904 : (define_expand "mmx_maskmovq"
6905 : [(set (match_operand:V8QI 0 "memory_operand")
6906 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand")
6907 22 : (match_operand:V8QI 2 "register_operand")
6908 : (match_dup 0)]
6909 : UNSPEC_MASKMOV))]
6910 : "TARGET_SSE || TARGET_3DNOW_A")
6911 :
6912 16804 : (define_insn "*mmx_maskmovq"
6913 : [(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
6914 16804 : (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
6915 16804 : (match_operand:V8QI 2 "register_operand" "y")
6916 16804 : (mem:V8QI (match_dup 0))]
6917 : UNSPEC_MASKMOV))]
6918 9 : "TARGET_SSE || TARGET_3DNOW_A"
6919 : ;; @@@ check ordering of operands in intel/nonintel syntax
6920 : "maskmovq\t{%2, %1|%1, %2}"
6921 : [(set_attr "type" "mmxcvt")
6922 : (set_attr "znver1_decode" "vector")
6923 : (set_attr "c86_decode" "vector")
6924 : (set_attr "mode" "DI")])
6925 :
6926 : (define_int_iterator EMMS
6927 104 : [(UNSPECV_EMMS "TARGET_MMX")
6928 15 : (UNSPECV_FEMMS "TARGET_3DNOW")])
6929 0 :
6930 0 : (define_int_attr emms
6931 15 : [(UNSPECV_EMMS "emms")
6932 15 : (UNSPECV_FEMMS "femms")])
6933 0 :
6934 94994 : (define_expand "mmx_<emms>"
6935 94994 : [(parallel
6936 94994 : [(unspec_volatile [(const_int 0)] EMMS)
6937 94994 : (clobber (reg:XF ST0_REG))
6938 1814860320 : (clobber (reg:XF ST1_REG))
6939 : (clobber (reg:XF ST2_REG))
6940 : (clobber (reg:XF ST3_REG))
6941 : (clobber (reg:XF ST4_REG))
6942 1814860320 : (clobber (reg:XF ST5_REG))
6943 1814860320 : (clobber (reg:XF ST6_REG))
6944 1814860320 : (clobber (reg:XF ST7_REG))
6945 1814860320 : (clobber (reg:DI MM0_REG))
6946 1814860320 : (clobber (reg:DI MM1_REG))
6947 1814860320 : (clobber (reg:DI MM2_REG))
6948 1814860320 : (clobber (reg:DI MM3_REG))
6949 1814860320 : (clobber (reg:DI MM4_REG))
6950 : (clobber (reg:DI MM5_REG))
6951 1551888473 : (clobber (reg:DI MM6_REG))
6952 1551888473 : (clobber (reg:DI MM7_REG))])]
6953 : "TARGET_MMX || TARGET_MMX_WITH_SSE"
6954 134826174 : {
6955 134826174 : if (!TARGET_MMX)
6956 : {
6957 124545371 : emit_insn (gen_nop ());
6958 124545371 : DONE;
6959 124545370 : }
6960 : })
6961 :
6962 : (define_insn "*mmx_<emms>"
6963 8164093 : [(unspec_volatile [(const_int 0)] EMMS)
6964 8164212 : (clobber (reg:XF ST0_REG))
6965 8164093 : (clobber (reg:XF ST1_REG))
6966 : (clobber (reg:XF ST2_REG))
6967 : (clobber (reg:XF ST3_REG))
6968 : (clobber (reg:XF ST4_REG))
6969 565091 : (clobber (reg:XF ST5_REG))
6970 565091 : (clobber (reg:XF ST6_REG))
6971 565091 : (clobber (reg:XF ST7_REG))
6972 : (clobber (reg:DI MM0_REG))
6973 : (clobber (reg:DI MM1_REG))
6974 119 : (clobber (reg:DI MM2_REG))
6975 1360921 : (clobber (reg:DI MM3_REG))
6976 1360921 : (clobber (reg:DI MM4_REG))
6977 1360921 : (clobber (reg:DI MM5_REG))
6978 : (clobber (reg:DI MM6_REG))
6979 71228 : (clobber (reg:DI MM7_REG))]
6980 : ""
6981 143855 : "<emms>"
6982 143855 : [(set_attr "type" "mmx")
6983 143855 : (set_attr "modrm" "0")
6984 : (set_attr "memory" "none")])
6985 :
6986 : (define_insn "popcount<mode>2"
6987 74620 : [(set (match_operand:VI1_16_32_64 0 "register_operand" "=v")
6988 74620 : (popcount:VI1_16_32_64
6989 : (match_operand:VI1_16_32_64 1 "register_operand" "v")))]
6990 73823 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
6991 73827 : "vpopcntb\t{%1, %0|%0, %1}")
6992 :
6993 50640 : (define_insn "popcount<mode>2"
6994 50664 : [(set (match_operand:VI2_32_64 0 "register_operand" "=v")
6995 50664 : (popcount:VI2_32_64
6996 50652 : (match_operand:VI2_32_64 1 "register_operand" "v")))]
6997 50662 : "TARGET_AVX512VL && TARGET_AVX512BITALG"
6998 50686 : "vpopcntw\t{%1, %0|%0, %1}")
6999 :
7000 50640 : (define_insn "popcountv2si2"
7001 50652 : [(set (match_operand:V2SI 0 "register_operand" "=v")
7002 12 : (popcount:V2SI
7003 50646 : (match_operand:V2SI 1 "register_operand" "v")))]
7004 50656 : "TARGET_AVX512VPOPCNTDQ && TARGET_AVX512VL && TARGET_MMX_WITH_SSE"
7005 50663 : "vpopcntd\t{%1, %0|%0, %1}")
7006 50640 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7007 : /* (content generated from coverage data) */
7008 : /* ... */
7009 : /* ... */
7010 : /* ... */
7011 : /* ... */
7012 : /* ... */
7013 : /* ... */
7014 3125124 : /* END: function "_Z8recog_60P7rtx_defP8rtx_insnPi" */
7015 : /* ... */
7016 : /* ... */
7017 : /* ... */
7018 3125124 : /* ... */
7019 3125124 : /* ... */
7020 3125124 : /* ... */
7021 3125124 : /* ... */
7022 3125124 : /* ... */
7023 3125124 : /* ... */
7024 3125124 : /* ... */
7025 3125124 : /* ... */
7026 3125124 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7027 : /* (content generated from coverage data) */
7028 2082323 : /* ... */
7029 2082323 : /* ... */
7030 2082323 : /* ... */
7031 2082323 : /* ... */
7032 2082323 : /* ... */
7033 2082323 : /* ... */
7034 2082323 : /* ... */
7035 : /* ... */
7036 17662 : /* ... */
7037 17662 : /* ... */
7038 16974 : /* ... */
7039 16974 : /* ... */
7040 32307 : /* ... */
7041 5170 : /* ... */
7042 12492 : /* ... */
7043 : /* ... */
7044 : /* ... */
7045 : /* ... */
7046 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7047 : /* (content generated from coverage data) */
7048 : /* ... */
7049 : /* ... */
7050 : /* ... */
7051 : /* ... */
7052 : /* ... */
7053 : /* ... */
7054 : /* ... */
7055 : /* ... */
7056 : /* ... */
7057 : /* ... */
7058 : /* ... */
7059 : /* ... */
7060 : /* ... */
7061 : /* ... */
7062 : /* ... */
7063 : /* ... */
7064 : /* ... */
7065 : /* ... */
7066 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7067 : /* (content generated from coverage data) */
7068 : /* ... */
7069 : /* ... */
7070 : /* ... */
7071 : /* ... */
7072 : /* ... */
7073 : /* ... */
7074 : /* ... */
7075 : /* ... */
7076 : /* ... */
7077 : /* ... */
7078 : /* ... */
7079 : /* ... */
7080 : /* ... */
7081 : /* ... */
7082 : /* ... */
7083 : /* ... */
7084 : /* ... */
7085 : /* ... */
7086 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7087 : /* (content generated from coverage data) */
7088 : /* ... */
7089 : /* ... */
7090 : /* ... */
7091 : /* ... */
7092 : /* ... */
7093 : /* ... */
7094 : /* ... */
7095 : /* ... */
7096 : /* ... */
7097 : /* ... */
7098 : /* ... */
7099 : /* ... */
7100 : /* ... */
7101 : /* ... */
7102 : /* ... */
7103 : /* ... */
7104 : /* ... */
7105 : /* ... */
7106 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7107 : /* (content generated from coverage data) */
7108 : /* ... */
7109 : /* ... */
7110 : /* ... */
7111 : /* ... */
7112 : /* ... */
7113 : /* ... */
7114 : /* ... */
7115 : /* ... */
7116 : /* ... */
7117 : /* ... */
7118 : /* ... */
7119 : /* ... */
7120 : /* ... */
7121 : /* ... */
7122 : /* ... */
7123 : /* ... */
7124 : /* ... */
7125 : /* ... */
7126 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7127 : /* (content generated from coverage data) */
7128 : /* ... */
7129 : /* ... */
7130 : /* ... */
7131 : /* ... */
7132 : /* ... */
7133 : /* ... */
7134 : /* ... */
7135 : /* ... */
7136 : /* ... */
7137 : /* ... */
7138 : /* ... */
7139 : /* ... */
7140 : /* ... */
7141 : /* ... */
7142 : /* ... */
7143 : /* ... */
7144 : /* ... */
7145 : /* ... */
7146 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7147 : /* (content generated from coverage data) */
7148 : /* ... */
7149 : /* ... */
7150 : /* ... */
7151 : /* ... */
7152 : /* ... */
7153 : /* ... */
7154 : /* ... */
7155 : /* ... */
7156 : /* ... */
7157 : /* ... */
7158 : /* ... */
7159 : /* ... */
7160 : /* ... */
7161 : /* ... */
7162 : /* ... */
7163 : /* ... */
7164 : /* ... */
7165 : /* ... */
7166 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7167 : /* (content generated from coverage data) */
7168 : /* ... */
7169 : /* ... */
7170 : /* ... */
7171 : /* ... */
7172 : /* ... */
7173 : /* ... */
7174 : /* ... */
7175 : /* ... */
7176 : /* ... */
7177 : /* ... */
7178 : /* ... */
7179 : /* ... */
7180 : /* ... */
7181 : /* ... */
7182 : /* ... */
7183 : /* ... */
7184 : /* ... */
7185 : /* ... */
7186 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7187 : /* (content generated from coverage data) */
7188 : /* ... */
7189 : /* ... */
7190 : /* ... */
7191 : /* ... */
7192 : /* ... */
7193 : /* ... */
7194 : /* ... */
7195 : /* ... */
7196 : /* ... */
7197 : /* ... */
7198 : /* ... */
7199 : /* ... */
7200 : /* ... */
7201 : /* ... */
7202 : /* ... */
7203 : /* ... */
7204 : /* ... */
7205 : /* ... */
7206 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7207 : /* (content generated from coverage data) */
7208 : /* ... */
7209 : /* ... */
7210 : /* ... */
7211 : /* ... */
7212 : /* ... */
7213 : /* ... */
7214 : /* ... */
7215 : /* ... */
7216 : /* ... */
7217 : /* ... */
7218 : /* ... */
7219 : /* ... */
7220 : /* ... */
7221 : /* ... */
7222 : /* ... */
7223 : /* ... */
7224 : /* ... */
7225 : /* ... */
7226 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7227 : /* (content generated from coverage data) */
7228 : /* ... */
7229 : /* ... */
7230 : /* ... */
7231 : /* ... */
7232 : /* ... */
7233 : /* ... */
7234 : /* ... */
7235 : /* ... */
7236 : /* ... */
7237 : /* ... */
7238 : /* ... */
7239 : /* ... */
7240 : /* ... */
7241 : /* ... */
7242 : /* ... */
7243 : /* ... */
7244 : /* ... */
7245 : /* ... */
7246 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7247 : /* (content generated from coverage data) */
7248 : /* ... */
7249 : /* ... */
7250 : /* ... */
7251 : /* ... */
7252 : /* ... */
7253 : /* ... */
7254 : /* ... */
7255 : /* ... */
7256 : /* ... */
7257 : /* ... */
7258 : /* ... */
7259 : /* ... */
7260 : /* ... */
7261 : /* ... */
7262 : /* ... */
7263 : /* ... */
7264 : /* ... */
7265 : /* ... */
7266 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7267 : /* (content generated from coverage data) */
7268 : /* ... */
7269 : /* ... */
7270 : /* ... */
7271 : /* ... */
7272 : /* ... */
7273 : /* ... */
7274 : /* ... */
7275 : /* ... */
7276 : /* ... */
7277 : /* ... */
7278 : /* ... */
7279 : /* ... */
7280 : /* ... */
7281 : /* ... */
7282 : /* ... */
7283 : /* ... */
7284 : /* ... */
7285 : /* ... */
7286 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7287 : /* (content generated from coverage data) */
7288 : /* ... */
7289 : /* ... */
7290 : /* ... */
7291 : /* ... */
7292 : /* ... */
7293 : /* ... */
7294 : /* ... */
7295 : /* ... */
7296 : /* ... */
7297 : /* ... */
7298 : /* ... */
7299 : /* ... */
7300 : /* ... */
7301 : /* ... */
7302 : /* ... */
7303 : /* ... */
7304 : /* ... */
7305 : /* ... */
7306 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7307 : /* (content generated from coverage data) */
7308 : /* ... */
7309 : /* ... */
7310 : /* ... */
7311 : /* ... */
7312 : /* ... */
7313 : /* ... */
7314 : /* ... */
7315 : /* ... */
7316 : /* ... */
7317 : /* ... */
7318 : /* ... */
7319 : /* ... */
7320 : /* ... */
7321 : /* ... */
7322 : /* ... */
7323 : /* ... */
7324 : /* ... */
7325 : /* ... */
7326 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7327 : /* (content generated from coverage data) */
7328 : /* ... */
7329 : /* ... */
7330 : /* ... */
7331 : /* ... */
7332 : /* ... */
7333 : /* ... */
7334 : /* ... */
7335 : /* ... */
7336 : /* ... */
7337 : /* ... */
7338 : /* ... */
7339 : /* ... */
7340 : /* ... */
7341 : /* ... */
7342 : /* ... */
7343 : /* ... */
7344 : /* ... */
7345 : /* ... */
7346 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7347 : /* (content generated from coverage data) */
7348 : /* ... */
7349 : /* ... */
7350 : /* ... */
7351 : /* ... */
7352 : /* ... */
7353 : /* ... */
7354 : /* ... */
7355 : /* ... */
7356 : /* ... */
7357 : /* ... */
7358 : /* ... */
7359 : /* ... */
7360 : /* ... */
7361 : /* ... */
7362 : /* ... */
7363 : /* ... */
7364 : /* ... */
7365 : /* ... */
7366 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7367 : /* (content generated from coverage data) */
7368 : /* ... */
7369 : /* ... */
7370 : /* ... */
7371 : /* ... */
7372 : /* ... */
7373 : /* ... */
7374 : /* ... */
7375 : /* ... */
7376 : /* ... */
7377 : /* ... */
7378 : /* ... */
7379 : /* ... */
7380 : /* ... */
7381 : /* ... */
7382 : /* ... */
7383 : /* ... */
7384 : /* ... */
7385 : /* ... */
7386 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7387 : /* (content generated from coverage data) */
7388 : /* ... */
7389 : /* ... */
7390 : /* ... */
7391 : /* ... */
7392 : /* ... */
7393 : /* ... */
7394 : /* ... */
7395 : /* ... */
7396 : /* ... */
7397 : /* ... */
7398 : /* ... */
7399 : /* ... */
7400 : /* ... */
7401 : /* ... */
7402 : /* ... */
7403 : /* ... */
7404 : /* ... */
7405 : /* ... */
7406 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7407 : /* (content generated from coverage data) */
7408 : /* ... */
7409 : /* ... */
7410 : /* ... */
7411 : /* ... */
7412 : /* ... */
7413 : /* ... */
7414 : /* ... */
7415 : /* ... */
7416 : /* ... */
7417 : /* ... */
7418 : /* ... */
7419 : /* ... */
7420 : /* ... */
7421 : /* ... */
7422 : /* ... */
7423 : /* ... */
7424 : /* ... */
7425 : /* ... */
7426 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7427 : /* (content generated from coverage data) */
7428 : /* ... */
7429 : /* ... */
7430 : /* ... */
7431 : /* ... */
7432 : /* ... */
7433 : /* ... */
7434 : /* ... */
7435 : /* ... */
7436 : /* ... */
7437 : /* ... */
7438 : /* ... */
7439 : /* ... */
7440 : /* ... */
7441 : /* ... */
7442 : /* ... */
7443 : /* ... */
7444 : /* ... */
7445 : /* ... */
7446 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7447 : /* (content generated from coverage data) */
7448 : /* ... */
7449 : /* ... */
7450 : /* ... */
7451 : /* ... */
7452 : /* ... */
7453 : /* ... */
7454 : /* ... */
7455 : /* ... */
7456 : /* ... */
7457 : /* ... */
7458 : /* ... */
7459 : /* ... */
7460 : /* ... */
7461 : /* ... */
7462 : /* ... */
7463 : /* ... */
7464 : /* ... */
7465 : /* ... */
7466 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7467 : /* (content generated from coverage data) */
7468 : /* ... */
7469 : /* ... */
7470 : /* ... */
7471 : /* ... */
7472 : /* ... */
7473 : /* ... */
7474 : /* ... */
7475 : /* ... */
7476 : /* ... */
7477 : /* ... */
7478 : /* ... */
7479 : /* ... */
7480 : /* ... */
7481 : /* ... */
7482 : /* ... */
7483 : /* ... */
7484 : /* ... */
7485 : /* ... */
7486 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7487 : /* (content generated from coverage data) */
7488 : /* ... */
7489 : /* ... */
7490 : /* ... */
7491 : /* ... */
7492 : /* ... */
7493 : /* ... */
7494 : /* ... */
7495 : /* ... */
7496 : /* ... */
7497 : /* ... */
7498 : /* ... */
7499 : /* ... */
7500 : /* ... */
7501 : /* ... */
7502 : /* ... */
7503 : /* ... */
7504 : /* ... */
7505 : /* ... */
7506 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7507 : /* (content generated from coverage data) */
7508 : /* ... */
7509 : /* ... */
7510 : /* ... */
7511 : /* ... */
7512 : /* ... */
7513 : /* ... */
7514 : /* ... */
7515 : /* ... */
7516 : /* ... */
7517 : /* ... */
7518 : /* ... */
7519 : /* ... */
7520 : /* ... */
7521 : /* ... */
7522 : /* ... */
7523 : /* ... */
7524 : /* ... */
7525 : /* ... */
7526 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7527 : /* (content generated from coverage data) */
7528 : /* ... */
7529 : /* ... */
7530 : /* ... */
7531 : /* ... */
7532 : /* ... */
7533 : /* ... */
7534 : /* ... */
7535 : /* ... */
7536 : /* ... */
7537 : /* ... */
7538 : /* ... */
7539 : /* ... */
7540 : /* ... */
7541 : /* ... */
7542 : /* ... */
7543 : /* ... */
7544 : /* ... */
7545 : /* ... */
7546 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7547 : /* (content generated from coverage data) */
7548 : /* ... */
7549 : /* ... */
7550 : /* ... */
7551 : /* ... */
7552 : /* ... */
7553 : /* ... */
7554 : /* ... */
7555 : /* ... */
7556 : /* ... */
7557 : /* ... */
7558 : /* ... */
7559 : /* ... */
7560 : /* ... */
7561 : /* ... */
7562 : /* ... */
7563 : /* ... */
7564 : /* ... */
7565 : /* ... */
7566 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7567 : /* (content generated from coverage data) */
7568 : /* ... */
7569 : /* ... */
7570 : /* ... */
7571 : /* ... */
7572 : /* ... */
7573 : /* ... */
7574 : /* ... */
7575 : /* ... */
7576 : /* ... */
7577 : /* ... */
7578 : /* ... */
7579 : /* ... */
7580 : /* ... */
7581 : /* ... */
7582 : /* ... */
7583 : /* ... */
7584 : /* ... */
7585 : /* ... */
7586 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7587 : /* (content generated from coverage data) */
7588 : /* ... */
7589 : /* ... */
7590 : /* ... */
7591 : /* ... */
7592 : /* ... */
7593 : /* ... */
7594 : /* ... */
7595 : /* ... */
7596 : /* ... */
7597 : /* ... */
7598 : /* ... */
7599 : /* ... */
7600 : /* ... */
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7618 : /* ... */
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7620 : /* ... */
7621 : /* ... */
7622 : /* ... */
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7628 : /* ... */
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7630 : /* ... */
7631 : /* ... */
7632 : /* ... */
7633 : /* ... */
7634 : /* ... */
7635 : /* ... */
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7637 : /* ... */
7638 : /* ... */
7639 : /* ... */
7640 : /* ... */
7641 : /* ... */
7642 : /* ... */
7643 : /* ... */
7644 : /* ... */
7645 : /* ... */
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7650 : /* ... */
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7656 : /* ... */
7657 : /* ... */
7658 : /* ... */
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7661 : /* ... */
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7664 : /* ... */
7665 : /* ... */
7666 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7667 : /* (content generated from coverage data) */
7668 : /* ... */
7669 : /* ... */
7670 : /* ... */
7671 : /* ... */
7672 : /* ... */
7673 : /* ... */
7674 : /* ... */
7675 : /* ... */
7676 : /* ... */
7677 : /* ... */
7678 : /* ... */
7679 : /* ... */
7680 : /* ... */
7681 : /* ... */
7682 : /* ... */
7683 : /* ... */
7684 : /* ... */
7685 : /* ... */
7686 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7687 : /* (content generated from coverage data) */
7688 : /* ... */
7689 : /* ... */
7690 : /* ... */
7691 : /* ... */
7692 : /* ... */
7693 : /* ... */
7694 : /* ... */
7695 : /* ... */
7696 : /* ... */
7697 : /* ... */
7698 : /* ... */
7699 : /* ... */
7700 : /* ... */
7701 : /* ... */
7702 : /* ... */
7703 : /* ... */
7704 : /* ... */
7705 : /* ... */
7706 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7707 : /* (content generated from coverage data) */
7708 : /* ... */
7709 : /* ... */
7710 : /* ... */
7711 : /* ... */
7712 : /* ... */
7713 : /* ... */
7714 : /* ... */
7715 : /* ... */
7716 : /* ... */
7717 : /* ... */
7718 : /* ... */
7719 : /* ... */
7720 : /* ... */
7721 : /* ... */
7722 : /* ... */
7723 : /* ... */
7724 : /* ... */
7725 : /* ... */
7726 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7727 : /* (content generated from coverage data) */
7728 : /* ... */
7729 : /* ... */
7730 : /* ... */
7731 : /* ... */
7732 : /* ... */
7733 : /* ... */
7734 : /* ... */
7735 : /* ... */
7736 : /* ... */
7737 : /* ... */
7738 : /* ... */
7739 : /* ... */
7740 : /* ... */
7741 : /* ... */
7742 : /* ... */
7743 : /* ... */
7744 : /* ... */
7745 : /* ... */
7746 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7747 0 : /* (content generated from coverage data) */
7748 0 : /* ... */
7749 0 : /* ... */
7750 0 : /* ... */
7751 : /* ... */
7752 0 : /* ... */
7753 : /* ... */
7754 : /* ... */
7755 : /* ... */
7756 : /* ... */
7757 : /* ... */
7758 : /* ... */
7759 : /* ... */
7760 : /* ... */
7761 : /* ... */
7762 : /* ... */
7763 : /* ... */
7764 : /* ... */
7765 : /* ... */
7766 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/mmx.md not long enough */
7767 : /* (content generated from coverage data) */
7768 441426954 : /* END: function "_Z19get_attr_prefix_rexP8rtx_insn" */
7769 : /* ... */
7770 441426954 : /* ... */
7771 : /* ... */
7772 441426954 : /* ... */
7773 : /* ... */
7774 804918 : /* ... */
7775 804918 : /* ... */
7776 804918 : /* ... */
7777 804918 : /* ... */
7778 804918 : /* ... */
7779 : /* ... */
7780 : /* ... */
7781 : /* ... */
7782 : /* ... */
7783 : /* ... */
7784 788090 : /* ... */
|
