Line data Source code
1 : ;; Predicate definitions for IA-32 and x86-64.
2 : ;; Copyright (C) 2004-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; Return true if OP is either a i387 or SSE fp register.
21 : (define_predicate "any_fp_register_operand"
22 : (and (match_code "reg")
23 134288277 : (match_test "ANY_FP_REGNO_P (REGNO (op))")))
24 40558 :
25 : ;; Return true if OP is an i387 fp register.
26 : (define_predicate "fp_register_operand"
27 : (and (match_code "reg")
28 1543331 : (match_test "STACK_REGNO_P (REGNO (op))")))
29 1454921 :
30 442080177 : ;; True if the operand is a GENERAL class register.
31 : (define_predicate "general_reg_operand"
32 : (and (match_code "reg")
33 276561701 : (match_test "GENERAL_REGNO_P (REGNO (op))")))
34 208256529 :
35 460476984 : ;; True if the operand is an INDEX class register.
36 : (define_predicate "index_reg_operand"
37 : (and (match_code "reg")
38 674265 : (match_test "INDEX_REGNO_P (REGNO (op))")))
39 674190 :
40 674962 : ;; True if the operand is a nonimmediate operand with GENERAL class register.
41 : (define_predicate "nonimmediate_gr_operand"
42 : (if_then_else (match_code "reg")
43 57644784 : (match_test "GENERAL_REGNO_P (REGNO (op))")
44 63933153 : (match_operand 0 "nonimmediate_operand")))
45 80013917 :
46 : ;; True if the operand is a general operand with GENERAL class register.
47 : (define_predicate "general_gr_operand"
48 93408720 : (if_then_else (match_code "reg")
49 40628793 : (match_test "GENERAL_REGNO_P (REGNO (op))")
50 118520917 : (match_operand 0 "general_operand")))
51 :
52 : ;; True if the operand is an MMX register.
53 : (define_predicate "mmx_reg_operand"
54 40106276 : (and (match_code "reg")
55 192 : (match_test "MMX_REGNO_P (REGNO (op))")))
56 40106276 :
57 : ;; Match register operands, but include memory operands for
58 : ;; !TARGET_MMX_WITH_SSE.
59 : (define_predicate "register_mmxmem_operand"
60 635979 : (ior (match_operand 0 "register_operand")
61 12 : (and (not (match_test "TARGET_MMX_WITH_SSE"))
62 635979 : (match_operand 0 "memory_operand"))))
63 :
64 : ;; True if the operand is an SSE register.
65 161795679 : (define_predicate "sse_reg_operand"
66 : (and (match_code "reg")
67 161795679 : (match_test "SSE_REGNO_P (REGNO (op))")))
68 1704354 :
69 : ;; Return true if op is a QImode register.
70 : (define_predicate "any_QIreg_operand"
71 : (and (match_code "reg")
72 8160985 : (match_test "ANY_QI_REGNO_P (REGNO (op))")))
73 3825637 :
74 9726640 : ;; Return true if op is one of QImode registers: %[abcd][hl].
75 : (define_predicate "QIreg_operand"
76 : (and (match_code "reg")
77 2304496 : (match_test "QI_REGNO_P (REGNO (op))")))
78 2174860 :
79 6129591 : ;; Return true if op is a QImode register operand other than %[abcd][hl].
80 : (define_predicate "ext_QIreg_operand"
81 3325039 : (and (match_test "TARGET_64BIT")
82 3325342 : (match_code "reg")
83 965098 : (not (match_test "QI_REGNO_P (REGNO (op))"))))
84 3585864 :
85 : ;; Return true if op is the AX register.
86 : (define_predicate "ax_reg_operand"
87 : (and (match_code "reg")
88 23073129 : (match_test "REGNO (op) == AX_REG")))
89 0 :
90 116491030 : ;; Return true if op is the flags register.
91 : (define_special_predicate "flags_reg_operand"
92 : (and (match_code "reg")
93 115423755 : (match_test "REGNO (op) == FLAGS_REG")))
94 :
95 41560050 : ;; True if the operand is a MASK register.
96 : (define_predicate "mask_reg_operand"
97 9808386 : (and (match_code "reg")
98 4537 : (match_test "MASK_REGNO_P (REGNO (op))")))
99 9812923 :
100 : ;; Return true if op is the block scale register.
101 : (define_special_predicate "bsr0_operand"
102 : (and (match_code "reg")
103 869 : (match_test "REGNO (op) == BSR0_REG")))
104 :
105 291 : ;; Match a DI, SI or HImode register operand.
106 : (define_special_predicate "int248_register_operand"
107 353646 : (and (match_operand 0 "register_operand")
108 595194 : (ior (and (match_test "TARGET_64BIT")
109 353646 : (match_test "GET_MODE (op) == DImode"))
110 263598 : (match_test "GET_MODE (op) == SImode")
111 353646 : (match_test "GET_MODE (op) == HImode"))))
112 :
113 : ;; Match a DI, SI, HI or QImode nonimmediate_operand.
114 : (define_special_predicate "int_nonimmediate_operand"
115 385073 : (and (match_operand 0 "nonimmediate_operand")
116 450023 : (ior (and (match_test "TARGET_64BIT")
117 385073 : (match_test "GET_MODE (op) == DImode"))
118 173825 : (match_test "GET_MODE (op) == SImode")
119 : (match_test "GET_MODE (op) == HImode")
120 385073 : (match_test "GET_MODE (op) == QImode"))))
121 :
122 : ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
123 : (define_predicate "register_ssemem_operand"
124 2899211 : (if_then_else
125 2899211 : (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
126 2899211 : (match_operand 0 "nonimmediate_operand")
127 : (match_operand 0 "register_operand")))
128 :
129 1082780 : ;; Match nonimmediate operands, but exclude memory operands
130 : ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
131 1082780 : (define_predicate "nonimm_ssenomem_operand"
132 : (if_then_else
133 1082780 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
134 2165560 : (not (match_test "TARGET_MIX_SSE_I387")))
135 : (match_operand 0 "register_operand")
136 : (match_operand 0 "nonimmediate_operand")))
137 :
138 773124 : ;; The above predicate, suitable for x87 arithmetic operators.
139 : (define_predicate "x87nonimm_ssenomem_operand"
140 773124 : (if_then_else
141 773124 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
142 1546248 : (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
143 : (match_operand 0 "register_operand")
144 : (match_operand 0 "nonimmediate_operand")))
145 :
146 34376 : ;; Match register operands, include memory operand for TARGET_SSE4_1.
147 : (define_predicate "register_sse4nonimm_operand"
148 34376 : (if_then_else (match_test "TARGET_SSE4_1")
149 : (match_operand 0 "nonimmediate_operand")
150 : (match_operand 0 "register_operand")))
151 :
152 14090 : ;; Return true if VALUE is symbol reference
153 : (define_predicate "symbol_operand"
154 14090 : (match_code "symbol_ref"))
155 14090 :
156 : ;; Return true if VALUE is an ENDBR opcode in immediate field.
157 : (define_predicate "ix86_endbr_immediate_operand"
158 : (match_code "const_int")
159 6467521048 : {
160 6467521048 : if (flag_cf_protection & CF_BRANCH)
161 : {
162 1230940781 : unsigned HOST_WIDE_INT imm = UINTVAL (op);
163 1230940781 : unsigned HOST_WIDE_INT val = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
164 :
165 1230940781 : if (imm == val)
166 : return true;
167 :
168 : /* NB: Encoding is byte based. */
169 1230940573 : if (TARGET_64BIT)
170 2385399885 : for (; imm >= val; imm >>= 8)
171 1343568436 : if (imm == val)
172 : return true;
173 : }
174 :
175 : return false;
176 : })
177 :
178 : ;; Return true if VALUE can be stored in a sign extended immediate field.
179 8376173431 : (define_predicate "x86_64_immediate_operand"
180 : (match_code "const_int,symbol_ref,label_ref,const")
181 8376173431 : {
182 11467923673 : if (ix86_endbr_immediate_operand (op, VOIDmode))
183 : return false;
184 :
185 5000402374 : if (!TARGET_64BIT)
186 5187297233 : return immediate_operand (op, mode);
187 :
188 4813507766 : switch (GET_CODE (op))
189 : {
190 3946502920 : case CONST_INT:
191 3946502920 : {
192 3946502920 : HOST_WIDE_INT val = INTVAL (op);
193 3946502920 : return trunc_int_for_mode (val, SImode) == val;
194 : }
195 706659642 : case SYMBOL_REF:
196 : /* TLS symbols are not constant. */
197 706659642 : if (SYMBOL_REF_TLS_MODEL (op))
198 : return false;
199 :
200 : /* Load the external function address via the GOT slot. */
201 706623719 : if (ix86_force_load_from_GOT_p (op))
202 : return false;
203 :
204 : /* For certain code models, the symbolic references are known to fit.
205 : in CM_SMALL_PIC model we know it fits if it is local to the shared
206 : library. Don't count TLS SYMBOL_REFs here, since they should fit
207 : only if inside of UNSPEC handled below. */
208 706623617 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
209 706623617 : || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
210 :
211 23932244 : case LABEL_REF:
212 : /* For certain code models, the code is near as well. */
213 23932244 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
214 : || ix86_cmodel == CM_KERNEL);
215 :
216 136412960 : case CONST:
217 : /* We also may accept the offsetted memory references in certain
218 : special cases. */
219 136412960 : if (GET_CODE (XEXP (op, 0)) == UNSPEC)
220 738988 : switch (XINT (XEXP (op, 0), 1))
221 : {
222 : case UNSPEC_GOTPCREL:
223 : case UNSPEC_DTPOFF:
224 : case UNSPEC_GOTNTPOFF:
225 : case UNSPEC_NTPOFF:
226 : case UNSPEC_SECREL32:
227 : return true;
228 : default:
229 : break;
230 : }
231 :
232 135675482 : if (GET_CODE (XEXP (op, 0)) == PLUS)
233 : {
234 135673972 : rtx op1 = XEXP (XEXP (op, 0), 0);
235 135673972 : rtx op2 = XEXP (XEXP (op, 0), 1);
236 :
237 135673972 : if (ix86_cmodel == CM_LARGE && GET_CODE (op1) != UNSPEC)
238 : return false;
239 135673967 : if (!CONST_INT_P (op2))
240 : return false;
241 :
242 135673967 : HOST_WIDE_INT offset = INTVAL (op2);
243 135673967 : if (trunc_int_for_mode (offset, SImode) != offset)
244 : return false;
245 :
246 135668564 : switch (GET_CODE (op1))
247 : {
248 135327761 : case SYMBOL_REF:
249 : /* TLS symbols are not constant. */
250 135327761 : if (SYMBOL_REF_TLS_MODEL (op1))
251 : return false;
252 :
253 : /* Load the external function address via the GOT slot. */
254 135317241 : if (ix86_force_load_from_GOT_p (op1))
255 : return false;
256 :
257 : /* For CM_SMALL assume that latest object is 16MB before
258 : end of 31bits boundary. We may also accept pretty
259 : large negative constants knowing that all objects are
260 : in the positive half of address space. */
261 135317235 : if ((ix86_cmodel == CM_SMALL
262 266248 : || (ix86_cmodel == CM_MEDIUM
263 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
264 135317235 : && offset < 16*1024*1024)
265 : return true;
266 : /* For CM_KERNEL we know that all object resist in the
267 : negative half of 32bits address space. We may not
268 : accept negative offsets, since they may be just off
269 : and we may accept pretty large positive ones. */
270 269158 : if (ix86_cmodel == CM_KERNEL
271 0 : && offset > 0)
272 : return true;
273 : break;
274 :
275 6026 : case LABEL_REF:
276 : /* These conditions are similar to SYMBOL_REF ones, just the
277 : constraints for code models differ. */
278 6026 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
279 6026 : && offset < 16*1024*1024)
280 : return true;
281 0 : if (ix86_cmodel == CM_KERNEL
282 0 : && offset > 0)
283 : return true;
284 : break;
285 :
286 334777 : case UNSPEC:
287 334777 : switch (XINT (op1, 1))
288 : {
289 : case UNSPEC_DTPOFF:
290 : case UNSPEC_NTPOFF:
291 : return true;
292 : }
293 : break;
294 :
295 : default:
296 : break;
297 : }
298 : }
299 : break;
300 :
301 0 : default:
302 0 : gcc_unreachable ();
303 : }
304 :
305 : return false;
306 : })
307 :
308 : ;; Return true if VALUE can be stored in the zero extended immediate field.
309 5493181336 : (define_predicate "x86_64_zext_immediate_operand"
310 : (match_code "const_int,symbol_ref,label_ref,const")
311 5493181336 : {
312 752736597 : if (ix86_endbr_immediate_operand (op, VOIDmode))
313 5000402625 : return false;
314 5000402625 :
315 752736449 : switch (GET_CODE (op))
316 5000402625 : {
317 5684342960 : case CONST_INT:
318 683940335 : return !(INTVAL (op) & ~HOST_WIDE_INT_C (0xffffffff));
319 :
320 62383743 : case SYMBOL_REF:
321 5000402625 : /* TLS symbols are not constant. */
322 5062786368 : if (SYMBOL_REF_TLS_MODEL (op))
323 273456403 : return false;
324 :
325 : /* Load the external function address via the GOT slot. */
326 62348691 : if (ix86_force_load_from_GOT_p (op))
327 752736597 : return false;
328 :
329 : /* For certain code models, the symbolic references are known to fit. */
330 62348590 : return (ix86_cmodel == CM_SMALL
331 62348590 : || (ix86_cmodel == CM_MEDIUM
332 218 : && !SYMBOL_REF_FAR_ADDR_P (op)));
333 :
334 2377408 : case LABEL_REF:
335 : /* For certain code models, the code is near as well. */
336 2377408 : return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
337 :
338 4034963 : case CONST:
339 : /* We also may accept the offsetted memory references in certain
340 : special cases. */
341 4034963 : if (GET_CODE (XEXP (op, 0)) == PLUS)
342 : {
343 4030376 : rtx op1 = XEXP (XEXP (op, 0), 0);
344 4030376 : rtx op2 = XEXP (XEXP (op, 0), 1);
345 :
346 4030376 : if (ix86_cmodel == CM_LARGE)
347 : return false;
348 4030374 : if (!CONST_INT_P (op2))
349 : return false;
350 :
351 4030374 : HOST_WIDE_INT offset = INTVAL (op2);
352 4030374 : if (trunc_int_for_mode (offset, SImode) != offset)
353 : return false;
354 :
355 4027541 : switch (GET_CODE (op1))
356 : {
357 4027050 : case SYMBOL_REF:
358 : /* TLS symbols are not constant. */
359 4027050 : if (SYMBOL_REF_TLS_MODEL (op1))
360 : return false;
361 :
362 : /* Load the external function address via the GOT slot. */
363 4017758 : if (ix86_force_load_from_GOT_p (op1))
364 : return false;
365 :
366 : /* For small code model we may accept pretty large positive
367 : offsets, since one bit is available for free. Negative
368 : offsets are limited by the size of NULL pointer area
369 : specified by the ABI. */
370 4017752 : if ((ix86_cmodel == CM_SMALL
371 234206 : || (ix86_cmodel == CM_MEDIUM
372 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
373 4017752 : && offset > -0x10000)
374 : return true;
375 : /* ??? For the kernel, we may accept adjustment of
376 : -0x10000000, since we know that it will just convert
377 : negative address space to positive, but perhaps this
378 : is not worthwhile. */
379 : break;
380 :
381 0 : case LABEL_REF:
382 : /* These conditions are similar to SYMBOL_REF ones, just the
383 : constraints for code models differ. */
384 0 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
385 0 : && offset > -0x10000)
386 : return true;
387 : break;
388 :
389 : default:
390 : return false;
391 : }
392 : }
393 : break;
394 :
395 0 : default:
396 0 : gcc_unreachable ();
397 : }
398 : return false;
399 : })
400 :
401 : ;; Return true if VALUE is a constant integer whose negation satisfies
402 1007112422 : ;; x86_64_immediate_operand.
403 : (define_predicate "x86_64_neg_const_int_operand"
404 1007112422 : (match_code "const_int")
405 : {
406 752770669 : HOST_WIDE_INT val = -UINTVAL (op);
407 16174 : if (mode == DImode && trunc_int_for_mode (val, SImode) != val)
408 752736597 : return false;
409 33475 : if (flag_cf_protection & CF_BRANCH)
410 752736597 : {
411 13802 : unsigned HOST_WIDE_INT endbr = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
412 13802 : if ((val & HOST_WIDE_INT_C (0xffffffff)) == endbr)
413 0 : return false;
414 752736597 : }
415 752736597 : return true;
416 54551773 : })
417 :
418 : ;; Return true if VALUE is a constant integer whose low and high words satisfy
419 47743 : ;; x86_64_immediate_operand.
420 34072 : (define_predicate "x86_64_hilo_int_operand"
421 81815 : (match_code "const_int,const_wide_int")
422 34072 : {
423 44895179 : switch (GET_CODE (op))
424 : {
425 44841762 : case CONST_INT:
426 44895179 : return x86_64_immediate_operand (op, mode);
427 :
428 53417 : case CONST_WIDE_INT:
429 53417 : gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
430 53417 : return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
431 : DImode)
432 53417 : && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
433 : 1)),
434 : DImode));
435 :
436 0 : default:
437 0 : gcc_unreachable ();
438 : }
439 : })
440 :
441 : ;; Return true if VALUE is a constant integer whose value is
442 45467790 : ;; x86_64_immediate_operand value zero extended from word mode to mode.
443 : (define_predicate "x86_64_dwzext_immediate_operand"
444 45467790 : (match_code "const_int,const_wide_int")
445 : {
446 3742 : if (ix86_endbr_immediate_operand (op, VOIDmode))
447 44895179 : return false;
448 44895179 :
449 3742 : switch (GET_CODE (op))
450 : {
451 1624 : case CONST_INT:
452 1624 : if (!TARGET_64BIT)
453 44895179 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff);
454 1624 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff);
455 :
456 2118 : case CONST_WIDE_INT:
457 5860 : if (!TARGET_64BIT)
458 : return false;
459 2118 : return (CONST_WIDE_INT_NUNITS (op) == 2
460 2118 : && CONST_WIDE_INT_ELT (op, 1) == 0
461 4236 : && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode)
462 2118 : == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0)));
463 :
464 0 : default:
465 0 : gcc_unreachable ();
466 : }
467 : })
468 :
469 : ;; Return true if size of VALUE can be stored in a sign
470 3742 : ;; extended immediate field.
471 : (define_predicate "x86_64_immediate_size_operand"
472 3742 : (and (match_code "symbol_ref")
473 0 : (ior (not (match_test "TARGET_64BIT"))
474 0 : (match_test "ix86_cmodel == CM_SMALL")
475 0 : (match_test "ix86_cmodel == CM_KERNEL"))))
476 0 :
477 : ;; Return true if OP is general operand representable on x86_64.
478 : (define_predicate "x86_64_general_operand"
479 151326948 : (if_then_else (match_test "TARGET_64BIT")
480 151330690 : (ior (match_operand 0 "nonimmediate_operand")
481 3742 : (match_operand 0 "x86_64_immediate_operand"))
482 151326948 : (match_operand 0 "general_operand")))
483 63802038 :
484 : ;; Return true if OP's both words are general operands representable
485 63802038 : ;; on x86_64.
486 : (define_predicate "x86_64_hilo_general_operand"
487 63802038 : (if_then_else (match_test "TARGET_64BIT")
488 : (ior (match_operand 0 "nonimmediate_operand")
489 : (match_operand 0 "x86_64_hilo_int_operand"))
490 : (match_operand 0 "general_operand")))
491 279639 :
492 : ;; Return true if OP is non-VOIDmode general operand representable
493 279639 : ;; on x86_64. This predicate is used in sign-extending conversion
494 : ;; operations that require non-VOIDmode immediate operands.
495 : (define_predicate "x86_64_sext_operand"
496 279639 : (and (match_test "GET_MODE (op) != VOIDmode")
497 : (match_operand 0 "x86_64_general_operand")))
498 :
499 : ;; Return true if OP is non-VOIDmode general operand. This predicate
500 11347 : ;; is used in sign-extending conversion operations that require
501 : ;; non-VOIDmode immediate operands.
502 11347 : (define_predicate "sext_operand"
503 11347 : (and (match_test "GET_MODE (op) != VOIDmode")
504 : (match_operand 0 "general_operand")))
505 :
506 : ;; Return true if OP is representable on x86_64 as zero-extended operand.
507 3613487 : ;; This predicate is used in zero-extending conversion operations that
508 : ;; require non-VOIDmode immediate operands.
509 3613487 : (define_predicate "x86_64_zext_operand"
510 3613487 : (if_then_else (match_test "TARGET_64BIT")
511 : (ior (match_operand 0 "nonimmediate_operand")
512 : (and (match_operand 0 "x86_64_zext_immediate_operand")
513 125753 : (match_test "GET_MODE (op) != VOIDmode")))
514 : (match_operand 0 "nonimmediate_operand")))
515 :
516 : ;; Return true if OP is general operand representable on x86_64
517 2502101 : ;; as either sign extended or zero extended constant.
518 : (define_predicate "x86_64_szext_general_operand"
519 2502101 : (if_then_else (match_test "TARGET_64BIT")
520 : (ior (match_operand 0 "nonimmediate_operand")
521 : (match_operand 0 "x86_64_immediate_operand")
522 : (match_operand 0 "x86_64_zext_immediate_operand"))
523 30695835 : (match_operand 0 "general_operand")))
524 :
525 30695835 : ;; Return true if OP is nonmemory operand representable on x86_64.
526 : (define_predicate "x86_64_nonmemory_operand"
527 30695835 : (if_then_else (match_test "TARGET_64BIT")
528 : (ior (match_operand 0 "register_operand")
529 : (match_operand 0 "x86_64_immediate_operand"))
530 : (match_operand 0 "nonmemory_operand")))
531 19791 :
532 : ;; Return true if OP is nonmemory operand representable on x86_64.
533 19791 : (define_predicate "x86_64_szext_nonmemory_operand"
534 19791 : (if_then_else (match_test "TARGET_64BIT")
535 : (ior (match_operand 0 "register_operand")
536 : (match_operand 0 "x86_64_immediate_operand")
537 : (match_operand 0 "x86_64_zext_immediate_operand"))
538 179072321 : (match_operand 0 "nonmemory_operand")))
539 :
540 : ;; Return true when operand is PIC expression that can be computed by lea
541 : ;; operation.
542 : (define_predicate "pic_32bit_operand"
543 : (match_code "const,symbol_ref,label_ref")
544 : {
545 179072321 : if (!flag_pic)
546 : return false;
547 :
548 : /* Rule out relocations that translate into 64bit constants. */
549 20959004 : if (TARGET_64BIT && GET_CODE (op) == CONST)
550 : {
551 183896 : rtx tmp = XEXP (op, 0);
552 183896 : if (GET_CODE (tmp) == PLUS && CONST_INT_P (XEXP (tmp, 1)))
553 182434 : tmp = XEXP (tmp, 0);
554 183896 : if (GET_CODE (tmp) == UNSPEC
555 1462 : && (XINT (tmp, 1) == UNSPEC_GOTOFF
556 1462 : || XINT (tmp, 1) == UNSPEC_GOT))
557 : return false;
558 : }
559 :
560 20958082 : return symbolic_operand (op, mode);
561 : })
562 :
563 : ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
564 1320230430 : (define_predicate "x86_64_movabs_operand"
565 : (and (match_operand 0 "nonmemory_operand")
566 1320230430 : (not (match_operand 0 "pic_32bit_operand"))))
567 :
568 179072321 : ;; Return true if OP is either a symbol reference or a sum of a symbol
569 179072321 : ;; reference and a constant.
570 179072321 : (define_predicate "symbolic_operand"
571 179072321 : (match_code "symbol_ref,label_ref,const")
572 : {
573 21704446 : switch (GET_CODE (op))
574 : {
575 179072321 : case SYMBOL_REF:
576 179072321 : case LABEL_REF:
577 560008 : return true;
578 :
579 220610 : case CONST:
580 220610 : op = XEXP (op, 0);
581 522110469 : if (SYMBOL_REF_P (op)
582 220610 : || LABEL_REF_P (op)
583 522110469 : || (GET_CODE (op) == UNSPEC
584 8399 : && (XINT (op, 1) == UNSPEC_GOT
585 8399 : || XINT (op, 1) == UNSPEC_GOTOFF
586 : || XINT (op, 1) == UNSPEC_SECREL32
587 21704446 : || XINT (op, 1) == UNSPEC_PCREL
588 : || XINT (op, 1) == UNSPEC_GOTPCREL)))
589 : return true;
590 212880 : if (GET_CODE (op) != PLUS
591 212211 : || !CONST_INT_P (XEXP (op, 1)))
592 : return false;
593 :
594 212211 : op = XEXP (op, 0);
595 212211 : if (SYMBOL_REF_P (op)
596 212211 : || LABEL_REF_P (op))
597 : return true;
598 : /* Only @GOTOFF and @SECREL32 get offsets. */
599 2136 : if (GET_CODE (op) != UNSPEC
600 2136 : || (XINT (op, 1) != UNSPEC_GOTOFF
601 0 : && XINT (op, 1) != UNSPEC_SECREL32))
602 : return false;
603 :
604 2136 : op = XVECEXP (op, 0, 0);
605 2136 : if (SYMBOL_REF_P (op)
606 2136 : || LABEL_REF_P (op))
607 2136 : return true;
608 : return false;
609 :
610 0 : default:
611 0 : gcc_unreachable ();
612 : }
613 : })
614 :
615 : ;; Return true if OP is a symbolic operand that resolves locally.
616 31413060 : (define_predicate "local_symbolic_operand"
617 : (match_code "const,label_ref,symbol_ref")
618 31413060 : {
619 2912072 : if (GET_CODE (op) == CONST
620 16172 : && GET_CODE (XEXP (op, 0)) == PLUS
621 8527 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
622 8527 : op = XEXP (XEXP (op, 0), 0);
623 21704446 :
624 2912072 : if (LABEL_REF_P (op))
625 : return true;
626 :
627 2866534 : if (!SYMBOL_REF_P (op))
628 21704446 : return false;
629 1306243 :
630 2856753 : if (SYMBOL_REF_TLS_MODEL (op))
631 : return false;
632 :
633 2912072 : /* Dll-imported symbols are always external. */
634 2856753 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
635 : return false;
636 2856753 : if (SYMBOL_REF_LOCAL_P (op))
637 : return true;
638 :
639 : /* There is, however, a not insubstantial body of code in the rest of
640 : the compiler that assumes it can just stick the results of
641 : ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
642 : /* ??? This is a hack. Should update the body of the compiler to
643 : always create a DECL an invoke targetm.encode_section_info. */
644 93668 : if (strncmp (XSTR (op, 0), internal_label_prefix,
645 : internal_label_prefix_len) == 0)
646 0 : return true;
647 :
648 : return false;
649 : })
650 :
651 : (define_predicate "local_func_symbolic_operand"
652 2920810 : (match_operand 0 "local_symbolic_operand")
653 : {
654 2920810 : if (GET_CODE (op) == CONST
655 0 : && GET_CODE (XEXP (op, 0)) == PLUS
656 0 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
657 0 : op = XEXP (XEXP (op, 0), 0);
658 2912072 :
659 2912084 : if (SYMBOL_REF_P (op)
660 12 : && !SYMBOL_REF_FUNCTION_P (op))
661 0 : return false;
662 :
663 2912072 : return true;
664 2912072 : })
665 2808614 :
666 : ;; Test for a legitimate @GOTOFF operand.
667 30 : ;;
668 : ;; VxWorks does not impose a fixed gap between segments; the run-time
669 42 : ;; gap can be different from the object-file gap. We therefore can't
670 12 : ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
671 : ;; same segment as the GOT. Unfortunately, the flexibility of linker
672 : ;; scripts means that we can't be sure of that in general, so assume
673 : ;; @GOTOFF is not valid on VxWorks, except with the large code model.
674 2920743 : ;; The comments above seem to apply only to VxWorks releases before 7.
675 : (define_predicate "gotoff_operand"
676 2920743 : (and (ior (not (match_test "TARGET_VXWORKS_VAROFF"))
677 : (match_test "ix86_cmodel == CM_LARGE")
678 2920743 : (match_test "ix86_cmodel == CM_LARGE_PIC"))
679 : (match_operand 0 "local_symbolic_operand")))
680 :
681 : ;; Test for various thread-local symbols.
682 30001 : (define_special_predicate "tls_symbolic_operand"
683 : (and (match_code "symbol_ref")
684 30001 : (match_test "SYMBOL_REF_TLS_MODEL (op)")))
685 :
686 : (define_special_predicate "tls_modbase_operand"
687 : (and (match_code "symbol_ref")
688 72 : (match_test "op == ix86_tls_module_base ()")))
689 :
690 144 : (define_predicate "tls_address_pattern"
691 : (and (match_code "set,parallel,unspec,unspec_volatile")
692 239947773 : (match_test "ix86_tls_address_pattern_p (op)")))
693 0 :
694 239947773 : ;; Test for a pc-relative call operand
695 : (define_predicate "constant_call_address_operand"
696 239947773 : (match_code "symbol_ref")
697 377316006 : {
698 137368024 : if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
699 137368013 : || flag_force_indirect_call
700 274734742 : || (TARGET_INDIRECT_BRANCH_REGISTER
701 1022 : && ix86_nopic_noplt_attribute_p (op)))
702 1748 : return false;
703 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
704 239947773 : return false;
705 : return true;
706 : })
707 :
708 : ;; True for any non-virtual and non-eliminable register. Used in places where
709 143071976 : ;; instantiation of such a register may cause the pattern to not be recognized.
710 : (define_predicate "register_no_elim_operand"
711 137368233 : (match_operand 0 "register_operand")
712 280438461 : {
713 99065585 : if (SUBREG_P (op))
714 58481 : op = SUBREG_REG (op);
715 :
716 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
717 20733497 : because it is guaranteed to be reloaded into one. */
718 20733497 : if (MEM_P (op))
719 : return true;
720 :
721 20733497 : return !(op == arg_pointer_rtx
722 20705467 : || op == frame_pointer_rtx
723 20703199 : || VIRTUAL_REGISTER_P (op));
724 : })
725 :
726 : ;; Similarly, but include the stack pointer. This is used
727 24716274 : ;; to prevent esp from being used as an index reg.
728 : (define_predicate "register_no_SP_operand"
729 24716274 : (match_operand 0 "register_operand")
730 20733497 : {
731 332823 : if (SUBREG_P (op))
732 7935 : op = SUBREG_REG (op);
733 :
734 332823 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
735 : because it is guaranteed to be reloaded into one. */
736 332823 : if (MEM_P (op))
737 : return true;
738 :
739 332823 : return !(op == arg_pointer_rtx
740 332823 : || op == frame_pointer_rtx
741 332823 : || op == stack_pointer_rtx
742 332823 : || VIRTUAL_REGISTER_P (op));
743 : })
744 :
745 : ;; P6 processors will jump to the address after the decrement when %esp
746 369984 : ;; is used as a call operand, so they will execute return address as a code.
747 : ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
748 369984 :
749 332823 : (define_predicate "call_register_operand"
750 1852003 : (if_then_else (match_test "TARGET_64BIT")
751 : (match_operand 0 "register_operand")
752 : (match_operand 0 "register_no_SP_operand")))
753 1852003 :
754 17934566 : ;; Return false if this is any eliminable register. Otherwise general_operand.
755 1852003 : (define_predicate "general_no_elim_operand"
756 17934566 : (if_then_else (match_code "reg,subreg")
757 : (match_operand 0 "register_no_elim_operand")
758 : (match_operand 0 "general_operand")))
759 :
760 11596644 : ;; Return false if this is any eliminable register. Otherwise
761 : ;; register_operand or a constant.
762 11596644 : (define_predicate "nonmemory_no_elim_operand"
763 : (ior (match_operand 0 "register_no_elim_operand")
764 : (match_operand 0 "immediate_operand")))
765 :
766 628223 : ;; Test for a valid operand for indirect branch.
767 : (define_predicate "indirect_branch_operand"
768 628223 : (ior (match_operand 0 "register_operand")
769 572756 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
770 572729 : (not (match_test "TARGET_X32"))
771 : (match_operand 0 "memory_operand"))))
772 :
773 : ;; Return true if OP is a memory operands that can be used in sibcalls.
774 24049 : ;; Since sibcall never returns, we can only use call-clobbered register
775 : ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
776 : ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
777 : ;; and *sibcall_value_GOT_32 patterns.
778 : (define_predicate "sibcall_memory_operand"
779 : (match_operand 0 "memory_operand")
780 : {
781 24049 : op = XEXP (op, 0);
782 24049 : if (CONSTANT_P (op))
783 : return true;
784 10508 : if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
785 : {
786 9482 : int regno = REGNO (XEXP (op, 0));
787 9482 : if (!HARD_REGISTER_NUM_P (regno) || call_used_or_fixed_reg_p (regno))
788 : {
789 7758 : op = XEXP (op, 1);
790 7758 : if (GOT32_symbol_operand (op, VOIDmode))
791 : return true;
792 : }
793 : }
794 : return false;
795 : })
796 :
797 : ;; Return true if OP is a GOT memory operand.
798 1386703 : (define_predicate "GOT_memory_operand"
799 : (and (match_operand 0 "memory_operand")
800 1410752 : (match_code "const" "0")
801 24049 : (match_code "unspec" "00")
802 566 : (match_test "XINT (XEXP (XEXP (op, 0), 0), 1) == UNSPEC_GOTPCREL")))
803 :
804 : ;; Test for a valid operand for a call instruction.
805 464 : ;; Allow constant call address operands in Pmode only.
806 49137142 : (define_special_predicate "call_insn_operand"
807 464 : (ior (match_test "constant_call_address_operand
808 55301240 : (op, mode == VOIDmode ? mode : Pmode)")
809 : (match_operand 0 "call_register_operand")
810 846522 : (match_test "satisfies_constraint_Bw (op)")))
811 :
812 : ;; Similarly, but for tail calls, in which we cannot allow memory references.
813 : (define_special_predicate "sibcall_insn_operand"
814 1228457 : (ior (match_test "constant_call_address_operand
815 1388721 : (op, mode == VOIDmode ? mode : Pmode)")
816 1228457 : (match_operand 0 "register_no_elim_operand")
817 122714 : (match_test "satisfies_constraint_Bs (op)")))
818 :
819 : ;; Return true if OP is a 32-bit GOT symbol operand.
820 : (define_predicate "GOT32_symbol_operand"
821 9670 : (and (match_code "const")
822 : (match_code "unspec" "0")
823 9670 : (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_GOT")))
824 0 :
825 : ;; Match exactly zero.
826 : (define_predicate "const0_operand"
827 : (match_code "const_int,const_double,const_vector")
828 138719073 : {
829 138719073 : if (mode == VOIDmode)
830 21581339 : mode = GET_MODE (op);
831 138719073 : return op == CONST0_RTX (mode);
832 : })
833 :
834 : ;; Match one or a vector with all elements equal to one.
835 994372961 : (define_predicate "const1_operand"
836 : (match_code "const_int,const_double,const_vector")
837 994372961 : {
838 11713747 : if (mode == VOIDmode)
839 11651813 : mode = GET_MODE (op);
840 150432820 : return op == CONST1_RTX (mode);
841 138719073 : })
842 138719073 :
843 : ;; Match exactly -1.
844 12970730 : (define_predicate "constm1_operand"
845 : (and (match_code "const_int")
846 151689803 : (match_test "op == constm1_rtx")))
847 138719073 :
848 63478649 : ;; Match 0 or -1.
849 11713747 : (define_predicate "const0_or_m1_operand"
850 11716640 : (ior (match_operand 0 "const0_operand")
851 11713747 : (match_operand 0 "constm1_operand")))
852 2893 :
853 : ;; Match exactly eight.
854 : (define_predicate "const8_operand"
855 11713747 : (and (match_code "const_int")
856 11713747 : (match_test "INTVAL (op) == 8")))
857 9997 :
858 208613 : ;; Match exactly 128.
859 : (define_predicate "const128_operand"
860 27673642 : (and (match_code "const_int")
861 246172651 : (match_test "INTVAL (op) == 128")))
862 27673642 :
863 195352251 : ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
864 : (define_predicate "const_32bit_mask"
865 2927190 : (and (match_code "const_int")
866 1945938 : (match_test "trunc_int_for_mode (INTVAL (op), DImode)
867 4873128 : == HOST_WIDE_INT_C (0xffffffff)")))
868 :
869 : ;; Match 2, 4, or 8. Used for leal multiplicands.
870 : (define_predicate "const248_operand"
871 304343 : (match_code "const_int")
872 : {
873 304343 : HOST_WIDE_INT i = INTVAL (op);
874 304343 : return i == 2 || i == 4 || i == 8;
875 : })
876 :
877 : ;; Match 1, 2, or 3. Used for lea shift amounts.
878 1028205 : (define_predicate "const123_operand"
879 : (match_code "const_int")
880 1028205 : {
881 1256809 : HOST_WIDE_INT i = INTVAL (op);
882 228604 : return i == 1 || i == 2 || i == 3;
883 : })
884 :
885 228604 : ;; Match 2, 3, 6, or 7
886 237016 : (define_predicate "const2367_operand"
887 : (match_code "const_int")
888 237016 : {
889 228604 : HOST_WIDE_INT i = INTVAL (op);
890 0 : return i == 2 || i == 3 || i == 6 || i == 7;
891 : })
892 :
893 0 : ;; Match 1, 2, 4, or 8
894 0 : (define_predicate "const1248_operand"
895 : (match_code "const_int")
896 0 : {
897 110266 : HOST_WIDE_INT i = INTVAL (op);
898 110266 : return i == 1 || i == 2 || i == 4 || i == 8;
899 : })
900 :
901 110266 : ;; Match 3, 5, or 9. Used for leal multiplicands.
902 537855 : (define_predicate "const359_operand"
903 : (match_code "const_int")
904 537855 : {
905 584821 : HOST_WIDE_INT i = INTVAL (op);
906 46966 : return i == 3 || i == 5 || i == 9;
907 : })
908 :
909 46966 : ;; Match 4 or 8 to 11. Used for embedded rounding.
910 223626 : (define_predicate "const_4_or_8_to_11_operand"
911 : (match_code "const_int")
912 223626 : {
913 303648 : HOST_WIDE_INT i = INTVAL (op);
914 80022 : return i == 4 || (i >= 8 && i <= 11);
915 : })
916 :
917 80022 : ;; Match 4 or 8. Used for SAE.
918 80024 : (define_predicate "const48_operand"
919 : (match_code "const_int")
920 80024 : {
921 80022 : HOST_WIDE_INT i = INTVAL (op);
922 65776 : return i == 4 || i == 8;
923 : })
924 :
925 65776 : ;; Match 0 or 1.
926 65776 : (define_predicate "const_0_to_1_operand"
927 : (and (match_code "const_int")
928 65776 : (ior (match_test "op == const0_rtx")
929 300590 : (match_test "op == const1_rtx"))))
930 :
931 : ;; Match 0 to 3.
932 : (define_predicate "const_0_to_3_operand"
933 7841931 : (and (match_code "const_int")
934 14895875 : (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
935 7841931 :
936 : ;; Match 0 to 4.
937 : (define_predicate "const_0_to_4_operand"
938 0 : (and (match_code "const_int")
939 0 : (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
940 0 :
941 : ;; Match 0 to 5.
942 : (define_predicate "const_0_to_5_operand"
943 0 : (and (match_code "const_int")
944 0 : (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
945 0 :
946 : ;; Match 0 to 7.
947 : (define_predicate "const_0_to_7_operand"
948 781402 : (and (match_code "const_int")
949 1562789 : (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
950 781402 :
951 : ;; Match 0 to 15.
952 : (define_predicate "const_0_to_15_operand"
953 81772 : (and (match_code "const_int")
954 163528 : (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
955 81772 :
956 : ;; Match 0 to 31.
957 : (define_predicate "const_0_to_31_operand"
958 54296 : (and (match_code "const_int")
959 108034 : (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
960 54296 :
961 : ;; Match 0 to 63.
962 : (define_predicate "const_0_to_63_operand"
963 27068 : (and (match_code "const_int")
964 52289 : (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
965 27068 :
966 : ;; Match 0 to 127.
967 : (define_predicate "const_0_to_127_operand"
968 9791 : (and (match_code "const_int")
969 18614 : (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
970 9791 :
971 : ;; Match 0 to 255.
972 : (define_predicate "const_0_to_255_operand"
973 8919818 : (and (match_code "const_int")
974 17811882 : (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
975 8919818 :
976 : ;; Match (0 to 255) * 8
977 : (define_predicate "const_0_to_255_mul_8_operand"
978 507836 : (match_code "const_int")
979 : {
980 507836 : unsigned HOST_WIDE_INT val = INTVAL (op);
981 507836 : return val <= 255*8 && val % 8 == 0;
982 : })
983 :
984 : ;; Match 1 to 255 except multiples of 8
985 507838 : (define_predicate "const_0_to_255_not_mul_8_operand"
986 : (match_code "const_int")
987 507838 : {
988 9 : unsigned HOST_WIDE_INT val = INTVAL (op);
989 912489 : return val <= 255 && val % 8 != 0;
990 : })
991 :
992 912503 : ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
993 912503 : ;; for shift & compare patterns, as shifting by 0 does not change flags).
994 : (define_predicate "const_1_to_31_operand"
995 912503 : (and (match_code "const_int")
996 691239 : (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
997 :
998 : ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
999 : ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
1000 109747 : (define_predicate "const_1_to_63_operand"
1001 : (and (match_code "const_int")
1002 109747 : (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
1003 :
1004 : ;; Match 2 or 3.
1005 : (define_predicate "const_2_to_3_operand"
1006 73075 : (and (match_code "const_int")
1007 146150 : (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
1008 73075 :
1009 : ;; Match 4 to 5.
1010 : (define_predicate "const_4_to_5_operand"
1011 5490 : (and (match_code "const_int")
1012 10980 : (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
1013 5490 :
1014 : ;; Match 4 to 7.
1015 : (define_predicate "const_4_to_7_operand"
1016 1105305 : (and (match_code "const_int")
1017 2210610 : (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
1018 1105305 :
1019 : ;; Match 6 to 7.
1020 : (define_predicate "const_6_to_7_operand"
1021 700 : (and (match_code "const_int")
1022 1400 : (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
1023 700 :
1024 : ;; Match 8 to 9.
1025 : (define_predicate "const_8_to_9_operand"
1026 513 : (and (match_code "const_int")
1027 1026 : (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
1028 513 :
1029 : ;; Match 8 to 11.
1030 : (define_predicate "const_8_to_11_operand"
1031 35513 : (and (match_code "const_int")
1032 71026 : (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
1033 35513 :
1034 : ;; Match 8 to 15.
1035 : (define_predicate "const_8_to_15_operand"
1036 40034 : (and (match_code "const_int")
1037 80068 : (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
1038 40034 :
1039 : ;; Match 10 to 11.
1040 : (define_predicate "const_10_to_11_operand"
1041 267 : (and (match_code "const_int")
1042 534 : (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
1043 267 :
1044 : ;; Match 12 to 13.
1045 : (define_predicate "const_12_to_13_operand"
1046 266 : (and (match_code "const_int")
1047 532 : (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
1048 266 :
1049 : ;; Match 12 to 15.
1050 : (define_predicate "const_12_to_15_operand"
1051 23714 : (and (match_code "const_int")
1052 47428 : (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
1053 23714 :
1054 : ;; Match 14 to 15.
1055 : (define_predicate "const_14_to_15_operand"
1056 266 : (and (match_code "const_int")
1057 532 : (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
1058 266 :
1059 : ;; Match 16 to 19.
1060 : (define_predicate "const_16_to_19_operand"
1061 924 : (and (match_code "const_int")
1062 1848 : (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
1063 924 :
1064 : ;; Match 16 to 31.
1065 : (define_predicate "const_16_to_31_operand"
1066 10153 : (and (match_code "const_int")
1067 20306 : (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
1068 10153 :
1069 : ;; Match 20 to 23.
1070 : (define_predicate "const_20_to_23_operand"
1071 532 : (and (match_code "const_int")
1072 1064 : (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
1073 532 :
1074 : ;; Match 24 to 27.
1075 : (define_predicate "const_24_to_27_operand"
1076 532 : (and (match_code "const_int")
1077 1064 : (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
1078 532 :
1079 : ;; Match 28 to 31.
1080 : (define_predicate "const_28_to_31_operand"
1081 532 : (and (match_code "const_int")
1082 1064 : (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
1083 532 :
1084 : (define_predicate "cmpps_imm_operand"
1085 : (ior (match_operand 0 "const_0_to_7_operand")
1086 4057 : (and (match_test "TARGET_AVX")
1087 : (match_operand 0 "const_0_to_31_operand"))))
1088 60106 :
1089 : ;; True if this is a constant appropriate for an increment or decrement.
1090 102836638 : (define_predicate "incdec_operand"
1091 : (match_code "const_int")
1092 : {
1093 : /* On Pentium4, the inc and dec operations causes extra dependency on flag
1094 : registers, since carry flag is not set. */
1095 102836638 : if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
1096 : return false;
1097 2625040 : return op == const1_rtx || op == constm1_rtx;
1098 : })
1099 :
1100 : ;; True for registers, or const_int_operand, used to vec_setm expander.
1101 127834783 : (define_predicate "vec_setm_sse41_operand"
1102 : (ior (and (match_operand 0 "register_operand")
1103 230672303 : (match_test "TARGET_SSE4_1"))
1104 102836638 : (match_code "const_int")))
1105 :
1106 : (define_predicate "vec_setm_avx2_operand"
1107 : (ior (and (match_operand 0 "register_operand")
1108 1053 : (match_test "TARGET_AVX2"))
1109 0 : (match_code "const_int")))
1110 1357 :
1111 : (define_predicate "vec_setm_mmx_operand"
1112 : (ior (and (match_operand 0 "register_operand")
1113 22 : (match_test "TARGET_SSE4_1")
1114 260 : (match_test "TARGET_MMX_WITH_SSE"))
1115 260 : (match_code "const_int")))
1116 :
1117 : ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
1118 : (define_predicate "reg_or_pm1_operand"
1119 4453982 : (ior (match_operand 0 "register_operand")
1120 : (and (match_code "const_int")
1121 4453982 : (ior (match_test "op == const1_rtx")
1122 259554 : (match_test "op == constm1_rtx")))))
1123 243210 :
1124 : ;; True for registers, or (not: registers). Used to optimize 3-operand
1125 : ;; bitwise operation.
1126 : (define_predicate "regmem_or_bitnot_regmem_operand"
1127 725849 : (ior (match_operand 0 "nonimmediate_operand")
1128 : (and (match_code "not")
1129 725849 : (match_test "nonimmediate_operand (XEXP (op, 0), mode)"))))
1130 29259 :
1131 : ;; True for expressions valid for 3-operand ternlog instructions.
1132 : (define_predicate "ternlog_operand"
1133 : (and (match_code "not,and,ior,xor")
1134 2338755 : (match_test "ix86_ternlog_operand_p (op)")))
1135 257801 :
1136 65848191 : ;; True if OP is acceptable as operand of DImode shift expander.
1137 : (define_predicate "shiftdi_operand"
1138 1380788 : (if_then_else (match_test "TARGET_64BIT")
1139 3719543 : (match_operand 0 "nonimmediate_operand")
1140 2338755 : (match_operand 0 "register_operand")))
1141 1380788 :
1142 2983676 : (define_predicate "ashldi_input_operand"
1143 644921 : (if_then_else (match_test "TARGET_64BIT")
1144 644921 : (match_operand 0 "nonimmediate_operand")
1145 : (match_operand 0 "reg_or_pm1_operand")))
1146 2338755 :
1147 573998 : ;; Return true if OP is a vector load from the constant pool with just
1148 : ;; the first element nonzero.
1149 : (define_predicate "zero_extended_scalar_load_operand"
1150 : (match_code "mem")
1151 : {
1152 573998 : unsigned n_elts;
1153 573998 : op = avoid_constant_pool_reference (op);
1154 :
1155 573998 : if (!CONST_VECTOR_P (op))
1156 : return false;
1157 :
1158 84487 : n_elts = CONST_VECTOR_NUNITS (op);
1159 :
1160 180287 : for (n_elts--; n_elts > 0; n_elts--)
1161 : {
1162 129411 : rtx elt = CONST_VECTOR_ELT (op, n_elts);
1163 258822 : if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
1164 : return false;
1165 : }
1166 : return true;
1167 : })
1168 :
1169 : /* Return true if operand is a float vector constant that is all ones. */
1170 1964749 : (define_predicate "float_vector_all_ones_operand"
1171 : (match_code "const_vector,mem")
1172 573998 : {
1173 2015625 : mode = GET_MODE (op);
1174 50876 : if (!FLOAT_MODE_P (mode)
1175 13244133 : || (MEM_P (op)
1176 11381314 : && (!SYMBOL_REF_P (XEXP (op, 0))
1177 1390234 : || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))))
1178 16067847 : return false;
1179 :
1180 3010520 : if (MEM_P (op))
1181 : {
1182 1147701 : op = get_pool_constant (XEXP (op, 0));
1183 1147701 : if (!CONST_VECTOR_P (op))
1184 : return false;
1185 :
1186 1147697 : if (GET_MODE (op) != mode
1187 5973 : && INTEGRAL_MODE_P (GET_MODE (op))
1188 5973 : && op == CONSTM1_RTX (GET_MODE (op)))
1189 : return true;
1190 : }
1191 :
1192 3010516 : rtx first = XVECEXP (op, 0, 0);
1193 8721738 : for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++)
1194 : {
1195 3832188 : rtx tmp = XVECEXP (op, 0, i);
1196 3832188 : if (!rtx_equal_p (tmp, first))
1197 : return false;
1198 : }
1199 528681 : if (GET_MODE (first) == E_SFmode)
1200 : {
1201 244314 : long l;
1202 244314 : REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1203 244314 : return (l & 0xffffffff) == 0xffffffff;
1204 : }
1205 284367 : else if (GET_MODE (first) == E_DFmode)
1206 : {
1207 277413 : long l[2];
1208 277413 : REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1209 277413 : return ((l[0] & 0xffffffff) == 0xffffffff
1210 277413 : && (l[1] & 0xffffffff) == 0xffffffff);
1211 : }
1212 : else
1213 : return false;
1214 : })
1215 :
1216 : /* Return true if operand is an integral vector constant that is all ones. */
1217 55556107 : (define_predicate "vector_all_ones_operand"
1218 : (and (match_code "const_vector")
1219 69196844 : (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1220 11842098 : (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1221 1083588 :
1222 16067847 : /* Return true if operand is a vector constant that is all ones. */
1223 16067847 : (define_predicate "int_float_vector_all_ones_operand"
1224 : (ior (match_operand 0 "vector_all_ones_operand")
1225 9078469 : (match_operand 0 "float_vector_all_ones_operand")
1226 0 : (match_test "op == constm1_rtx")))
1227 9078469 :
1228 16067847 : /* Return true if operand is an 128/256bit all ones vector
1229 3072 : that zero-extends to 256/512bit. */
1230 : (define_predicate "vector_all_ones_zero_extend_half_operand"
1231 12099215 : (match_code "const_vector")
1232 : {
1233 175461490 : mode = GET_MODE (op);
1234 12099215 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1235 185961881 : || (GET_MODE_SIZE (mode) != 32
1236 10198640 : && GET_MODE_SIZE (mode) != 64))
1237 : return false;
1238 :
1239 469860 : int nelts = CONST_VECTOR_NUNITS (op);
1240 542685 : for (int i = 0; i != nelts; i++)
1241 : {
1242 541677 : rtx elt = CONST_VECTOR_ELT (op, i);
1243 541677 : if (i < nelts / 2
1244 1064602 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1245 : return false;
1246 83866 : if (i >= nelts / 2
1247 102618 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1248 : return false;
1249 : }
1250 : return true;
1251 : })
1252 :
1253 : /* Return true if operand is an 128bit all ones vector
1254 176788491 : that zero extends to 512bit. */
1255 : (define_predicate "vector_all_ones_zero_extend_quarter_operand"
1256 12099215 : (match_code "const_vector")
1257 176789499 : {
1258 1008 : mode = GET_MODE (op);
1259 12098207 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1260 10499383 : || GET_MODE_SIZE (mode) != 64)
1261 : return false;
1262 12098207 :
1263 167890 : int nelts = CONST_VECTOR_NUNITS (op);
1264 181632 : for (int i = 0; i != nelts; i++)
1265 : {
1266 181540 : rtx elt = CONST_VECTOR_ELT (op, i);
1267 181540 : if (i < nelts / 4
1268 359559 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1269 : return false;
1270 16393 : if (i >= nelts / 4
1271 19914 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1272 : return false;
1273 : }
1274 : return true;
1275 : })
1276 :
1277 : ; Return true when OP is operand acceptable for vector memory operand.
1278 176787483 : ; Only AVX can have misaligned memory operand.
1279 : (define_predicate "vector_memory_operand"
1280 12098207 : (and (match_operand 0 "memory_operand")
1281 177875256 : (ior (match_test "TARGET_AVX")
1282 1087773 : (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1283 :
1284 : ; Return true when OP is register_operand or vector_memory_operand.
1285 : (define_predicate "vector_operand"
1286 19799164 : (ior (match_operand 0 "register_operand")
1287 : (match_operand 0 "vector_memory_operand")))
1288 19799164 :
1289 : ; Return true when OP is register_operand, vector_memory_operand
1290 : ; or const_vector.
1291 : (define_predicate "vector_or_const_vector_operand"
1292 94107 : (ior (match_operand 0 "register_operand")
1293 : (match_operand 0 "vector_memory_operand")
1294 94107 : (match_code "const_vector")))
1295 45043 :
1296 : (define_predicate "bcst_mem_operand"
1297 : (and (match_code "vec_duplicate")
1298 14420 : (and (match_test "TARGET_AVX512F")
1299 168183635 : (ior (match_test "TARGET_AVX512VL")
1300 9036 : (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64")))
1301 153589 : (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))")
1302 13472 : (match_test "GET_MODE (XEXP (op, 0))
1303 40405 : == GET_MODE_INNER (GET_MODE (op))")
1304 168197895 : (match_test "memory_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
1305 5317 :
1306 : ; Return true when OP is bcst_mem_operand or vector_memory_operand.
1307 : (define_predicate "bcst_vector_operand"
1308 : (ior (match_operand 0 "vector_operand")
1309 5294019 : (match_operand 0 "bcst_mem_operand")))
1310 :
1311 5294019 : ;; Return true when OP is either nonimmediate operand, or any
1312 : ;; CONST_VECTOR.
1313 : (define_predicate "nonimmediate_or_const_vector_operand"
1314 : (ior (match_operand 0 "nonimmediate_operand")
1315 92160 : (match_code "const_vector")))
1316 :
1317 92160 : (define_predicate "nonimmediate_or_const_vec_dup_operand"
1318 14988 : (ior (match_operand 0 "nonimmediate_operand")
1319 46 : (match_test "const_vec_duplicate_p (op)")))
1320 46 :
1321 : ;; Return true when OP is either register operand, or any
1322 94 : ;; CONST_VECTOR.
1323 : (define_predicate "reg_or_const_vector_operand"
1324 94 : (ior (match_operand 0 "register_operand")
1325 : (match_code "const_vector")))
1326 275 :
1327 173 : ;; Return true when OP is CONST_VECTOR which can be converted to a
1328 : ;; sign extended 32-bit integer.
1329 : (define_predicate "x86_64_const_vector_operand"
1330 : (match_code "const_vector")
1331 159081 : {
1332 159081 : if (mode == VOIDmode)
1333 0 : mode = GET_MODE (op);
1334 159081 : else if (GET_MODE (op) != mode)
1335 : return false;
1336 374609 : if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1337 : return false;
1338 116071 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op, mode);
1339 116071 : return trunc_int_for_mode (val, SImode) == val;
1340 : })
1341 :
1342 : (define_predicate "nonimmediate_or_x86_64_const_vector_operand"
1343 982354 : (ior (match_operand 0 "nonimmediate_operand")
1344 : (match_operand 0 "x86_64_const_vector_operand")))
1345 159081 :
1346 1064605 : ;; Return true when OP is nonimmediate or standard SSE constant.
1347 82251 : (define_predicate "nonimmediate_or_sse_const_operand"
1348 : (ior (match_operand 0 "nonimmediate_operand")
1349 25251510 : (match_test "standard_sse_constant_p (op, mode)")))
1350 2822306 :
1351 6681 : ;; Return true if OP is a register or a zero.
1352 : (define_predicate "reg_or_0_operand"
1353 6681 : (ior (match_operand 0 "register_operand")
1354 396084 : (match_operand 0 "const0_operand")))
1355 :
1356 396084 : ; Return true when OP is a nonimmediate or zero.
1357 94925830 : (define_predicate "nonimm_or_0_operand"
1358 : (ior (match_operand 0 "nonimmediate_operand")
1359 117355034 : (match_operand 0 "const0_operand")))
1360 127138350 :
1361 : ; Return true when OP is a nonimmediate or zero or all ones.
1362 127138350 : (define_predicate "nonimm_or_0_or_1s_operand"
1363 : (ior (match_operand 0 "nonimmediate_operand")
1364 : (match_operand 0 "const0_operand")
1365 : (match_operand 0 "int_float_vector_all_ones_operand")))
1366 82244 :
1367 : ;; Return true for RTX codes that force SImode address.
1368 82244 : (define_predicate "SImode_address_operand"
1369 : (match_code "subreg,zero_extend,and"))
1370 :
1371 : ;; Return true if op is a valid address for LEA, and does not contain
1372 275647012 : ;; a segment override. Defined as a special predicate to allow
1373 : ;; mode-less const_int operands pass to address_operand.
1374 275647012 : (define_special_predicate "address_no_seg_operand"
1375 184335552 : (match_test "address_operand (op, VOIDmode)")
1376 67632985 : {
1377 68013127 : struct ix86_address parts;
1378 68013127 : int ok;
1379 380142 :
1380 67671475 : if (!CONST_INT_P (op)
1381 64708859 : && mode != VOIDmode
1382 64708859 : && GET_MODE (op) != mode)
1383 380142 : return false;
1384 380142 :
1385 67632921 : ok = ix86_decompose_address (op, &parts);
1386 67632921 : gcc_assert (ok);
1387 67632921 : return parts.seg == ADDR_SPACE_GENERIC;
1388 67632985 : })
1389 :
1390 : ;; Return true if op if a valid base register, displacement or
1391 116702567 : ;; sum of base register and displacement for VSIB addressing.
1392 : (define_predicate "vsib_address_operand"
1393 116741057 : (match_test "address_operand (op, VOIDmode)")
1394 77741 : {
1395 37780 : struct ix86_address parts;
1396 38490 : int ok;
1397 38490 : rtx disp;
1398 :
1399 38490 : ok = ix86_decompose_address (op, &parts);
1400 38490 : gcc_assert (ok);
1401 64586 : if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1402 26096 : return false;
1403 :
1404 : /* VSIB addressing doesn't support (%rip). */
1405 38470 : if (parts.disp)
1406 26142087 : {
1407 6375 : disp = parts.disp;
1408 6375 : if (GET_CODE (disp) == CONST)
1409 : {
1410 148 : disp = XEXP (disp, 0);
1411 148 : if (GET_CODE (disp) == PLUS)
1412 148 : disp = XEXP (disp, 0);
1413 148 : if (GET_CODE (disp) == UNSPEC)
1414 0 : switch (XINT (disp, 1))
1415 : {
1416 : case UNSPEC_GOTPCREL:
1417 : case UNSPEC_PCREL:
1418 : case UNSPEC_GOTNTPOFF:
1419 : return false;
1420 : }
1421 : }
1422 6375 : if (TARGET_64BIT
1423 6375 : && flag_pic
1424 0 : && (SYMBOL_REF_P (disp)
1425 0 : || LABEL_REF_P (disp)))
1426 0 : return false;
1427 : }
1428 :
1429 : return true;
1430 : })
1431 :
1432 : (define_predicate "vsib_mem_operator"
1433 39271 : (match_code "mem"))
1434 :
1435 39271 : ;; Return true if the rtx is known to be at least 32 bits aligned.
1436 : (define_predicate "aligned_operand"
1437 : (match_operand 0 "general_operand")
1438 : {
1439 26142087 : struct ix86_address parts;
1440 26142087 : int ok;
1441 :
1442 : /* Registers and immediate operands are always "aligned". */
1443 26142087 : if (!MEM_P (op))
1444 : return true;
1445 :
1446 : /* All patterns using aligned_operand on memory operands ends up
1447 : in promoting memory operand to 64bit and thus causing memory mismatch. */
1448 8286399 : if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1449 : return false;
1450 :
1451 : /* Don't even try to do any aligned optimizations with volatiles. */
1452 123408 : if (MEM_VOLATILE_P (op))
1453 : return false;
1454 :
1455 117463 : if (MEM_ALIGN (op) >= 32)
1456 : return true;
1457 :
1458 45924 : op = XEXP (op, 0);
1459 :
1460 : /* Pushes and pops are only valid on the stack pointer. */
1461 45924 : if (GET_CODE (op) == PRE_DEC
1462 45924 : || GET_CODE (op) == POST_INC)
1463 : return true;
1464 :
1465 : /* Decode the address. */
1466 45924 : ok = ix86_decompose_address (op, &parts);
1467 45924 : gcc_assert (ok);
1468 :
1469 45924 : if (parts.base && SUBREG_P (parts.base))
1470 0 : parts.base = SUBREG_REG (parts.base);
1471 45924 : if (parts.index && SUBREG_P (parts.index))
1472 0 : parts.index = SUBREG_REG (parts.index);
1473 :
1474 : /* Look for some component that isn't known to be aligned. */
1475 45924 : if (parts.index)
1476 : {
1477 3264 : if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1478 : return false;
1479 : }
1480 42660 : if (parts.base)
1481 : {
1482 35794 : if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1483 : return false;
1484 : }
1485 13258 : if (parts.disp)
1486 : {
1487 13258 : if (!CONST_INT_P (parts.disp)
1488 6490 : || (INTVAL (parts.disp) & 3))
1489 12968 : return false;
1490 : }
1491 :
1492 : /* Didn't find one -- this must be an aligned address. */
1493 : return true;
1494 : })
1495 :
1496 : ;; Return true if OP is memory operand with a displacement.
1497 26647531 : (define_predicate "memory_displacement_operand"
1498 : (match_operand 0 "memory_operand")
1499 52789618 : {
1500 26142087 : struct ix86_address parts;
1501 0 : int ok;
1502 :
1503 0 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1504 0 : gcc_assert (ok);
1505 0 : return parts.disp != NULL_RTX;
1506 : })
1507 :
1508 : ;; Return true if OP is memory operand with a displacement only.
1509 0 : (define_predicate "memory_displacement_only_operand"
1510 : (match_operand 0 "memory_operand")
1511 0 : {
1512 0 : struct ix86_address parts;
1513 39043250 : int ok;
1514 :
1515 39043250 : if (TARGET_64BIT)
1516 39043250 : return false;
1517 :
1518 19106120 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1519 19106120 : gcc_assert (ok);
1520 :
1521 19106120 : if (parts.base || parts.index)
1522 : return false;
1523 :
1524 239331 : return parts.disp != NULL_RTX;
1525 : })
1526 :
1527 : ;; Return true if OP is memory operand that cannot be represented
1528 60599099 : ;; by the modRM array.
1529 : (define_predicate "long_memory_operand"
1530 99642349 : (and (match_operand 0 "memory_operand")
1531 39043250 : (match_test "memory_address_length (op, false)")))
1532 :
1533 : ;; Return true if OP is a comparison operator that can be issued by fcmov.
1534 : (define_predicate "fcmov_comparison_operator"
1535 70187 : (match_operand 0 "comparison_operator")
1536 : {
1537 0 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1538 70187 : enum rtx_code code = GET_CODE (op);
1539 :
1540 70187 : if (inmode == CCFPmode)
1541 9936 : code = ix86_fp_compare_code_to_integer (code);
1542 :
1543 : /* i387 supports just limited amount of conditional codes. */
1544 70187 : switch (code)
1545 : {
1546 2414 : case GEU: case LTU:
1547 2414 : if (inmode == CCCmode || inmode == CCGZmode)
1548 : return true;
1549 : /* FALLTHRU */
1550 7848 : case GTU: case LEU:
1551 7848 : if (inmode == CCmode || inmode == CCFPmode)
1552 : return true;
1553 : return false;
1554 : case ORDERED: case UNORDERED:
1555 : case EQ: case NE:
1556 : return true;
1557 : default:
1558 : return false;
1559 : }
1560 : })
1561 :
1562 : ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1563 70187 : ;; The first set are supported directly; the second set can't be done with
1564 : ;; full IEEE support, i.e. NaNs.
1565 140374 :
1566 70187 : (define_predicate "sse_comparison_operator"
1567 : (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1568 398196 : (and (match_test "TARGET_AVX")
1569 398196 : (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1570 513589 :
1571 : ;; SSE2 doesn't have quiet vector compare for UNLT/UNLE/UNGT/UNGE, so reject
1572 513589 : ;; them in the packed FP vec_cmp expanders when trapping math is in effect
1573 104385 : ;; and NaNs are honored
1574 :
1575 104385 : (define_predicate "ix86_fp_vec_cmp_operator"
1576 : (and (match_operand 0 "comparison_operator")
1577 : (ior (not (match_code "unlt,unle,ungt,unge"))
1578 8407 : (match_test "TARGET_AVX")
1579 15460 : (not (match_test "flag_trapping_math"))
1580 7697 : (not (match_test "HONOR_NANS (GET_MODE (XEXP (op, 0)))")))))
1581 :
1582 : (define_predicate "ix86_comparison_int_operator"
1583 : (match_code "ne,eq,ge,gt,le,lt"))
1584 217691 :
1585 : (define_predicate "ix86_comparison_uns_operator"
1586 217691 : (match_code "ne,eq,geu,gtu,leu,ltu"))
1587 :
1588 217691 : (define_predicate "bt_comparison_operator"
1589 217691 : (match_code "ne,eq"))
1590 217691 :
1591 217691 : (define_predicate "shr_comparison_operator"
1592 217691 : (match_code "gtu,leu"))
1593 217691 :
1594 217691 : (define_predicate "add_comparison_operator"
1595 : (match_code "geu,ltu"))
1596 :
1597 : (define_predicate "ieee_maxmin_comparison_operator"
1598 217691 : (match_code "lt,gt"))
1599 217691 :
1600 : ;; Return true if OP is a valid comparison operator in valid mode.
1601 : (define_predicate "ix86_comparison_operator"
1602 : (match_operand 0 "comparison_operator")
1603 113236 : {
1604 102188305 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1605 113236 : enum rtx_code code = GET_CODE (op);
1606 :
1607 102301541 : if (inmode == CCFPmode)
1608 6965922 : return ix86_trivial_fp_comparison_operator (op, mode);
1609 113236 :
1610 95222383 : switch (code)
1611 113236 : {
1612 73220727 : case EQ: case NE:
1613 73107491 : if (inmode == CCGZmode)
1614 0 : return false;
1615 : return true;
1616 4327250 : case GE: case LT:
1617 4327250 : if (inmode == CCmode || inmode == CCGCmode
1618 2483100 : || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode)
1619 3817936 : return true;
1620 : return false;
1621 7795501 : case GEU: case LTU:
1622 7795501 : if (inmode == CCCmode || inmode == CCGZmode)
1623 : return true;
1624 63939193 : /* FALLTHRU */
1625 11005325 : case GTU: case LEU:
1626 11005325 : if (inmode == CCmode)
1627 9759014 : return true;
1628 52659101 : return false;
1629 3497 : case ORDERED: case UNORDERED:
1630 3497 : if (inmode == CCmode)
1631 3312 : return true;
1632 52659101 : return false;
1633 52659101 : case GT: case LE:
1634 6283186 : if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1635 5508321 : return true;
1636 : return false;
1637 846365 : default:
1638 : return false;
1639 846365 : }
1640 : })
1641 846365 :
1642 846365 : ;; Return true if OP is a valid comparison operator
1643 117942095 : ;; testing carry flag to be set.
1644 : (define_predicate "ix86_carry_flag_operator"
1645 219284035 : (match_code "ltu,unlt")
1646 102188305 : {
1647 1737245 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1648 846365 : enum rtx_code code = GET_CODE (op);
1649 :
1650 890880 : if (inmode == CCFPmode)
1651 14881 : code = ix86_fp_compare_code_to_integer (code);
1652 1374928 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1653 : return false;
1654 1374928 :
1655 695609 : return code == LTU;
1656 1374928 : })
1657 1374928 :
1658 1374928 : ;; Return true if OP is a valid comparison operator
1659 3771354 : ;; testing carry flag to be unset.
1660 : (define_predicate "ix86_carry_flag_unset_operator"
1661 3771354 : (match_code "geu,ge")
1662 1374928 : {
1663 1374928 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1664 893240 : enum rtx_code code = GET_CODE (op);
1665 890880 :
1666 2360 : if (inmode == CCFPmode)
1667 93 : code = ix86_fp_compare_code_to_integer (code);
1668 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1669 1436 : return false;
1670 890880 :
1671 432130 : return code == GEU;
1672 1436 : })
1673 1436 :
1674 : ;; Return true if this comparison only requires testing one flag bit.
1675 2623142 : ;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
1676 : (define_predicate "ix86_trivial_fp_comparison_operator"
1677 12096787 : (if_then_else (match_test "TARGET_AVX10_2")
1678 672603 : (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
1679 2360 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
1680 2360 :
1681 2360 : (define_predicate "ix86_trivial_fp_comparison_operator_xf"
1682 103565879 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1683 :
1684 1377574 : ;; Return true if we know how to do this comparison. Others require
1685 2360 : ;; testing more than one flag bit, and we let the generic middle-end
1686 414889 : ;; code do that.
1687 414274 : (define_predicate "ix86_fp_comparison_operator"
1688 2922612 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1689 2922612 : == IX86_FPCMP_ARITH")
1690 412529 : (match_operand 0 "comparison_operator")
1691 9888534 : (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1692 412529 :
1693 9888534 : (define_predicate "ix86_fp_comparison_operator_xf"
1694 1790103 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1695 1377574 : == IX86_FPCMP_ARITH")
1696 : (match_operand 0 "comparison_operator")
1697 : (match_operand 0 "ix86_trivial_fp_comparison_operator_xf")))
1698 412529 :
1699 848009 : ;; Return true if we can perform this comparison on TImode operands.
1700 : (define_predicate "ix86_timode_comparison_operator"
1701 435480 : (if_then_else (match_test "TARGET_64BIT")
1702 : (match_operand 0 "ordered_comparison_operator")
1703 2510083 : (match_operand 0 "bt_comparison_operator")))
1704 :
1705 2510083 : ;; Return true if this is a valid second operand for a TImode comparison.
1706 : (define_predicate "ix86_timode_comparison_operand"
1707 155708 : (if_then_else (match_test "TARGET_64BIT")
1708 : (match_operand 0 "x86_64_general_operand")
1709 : (match_operand 0 "nonimmediate_operand")))
1710 :
1711 2043852 : ;; Nearly general operand, but accept any const_double, since we wish
1712 : ;; to be able to drop them into memory rather than have them get pulled
1713 518601 : ;; into registers.
1714 2562453 : (define_predicate "cmp_fp_expander_operand"
1715 : (ior (match_code "const_double")
1716 : (match_operand 0 "general_operand")))
1717 :
1718 4993222 : ;; Return true if this is a valid binary floating-point operation.
1719 : (define_predicate "binary_fp_operator"
1720 4993222 : (match_code "plus,minus,mult,div"))
1721 :
1722 4984141 : ;; Return true if this is a multiply operation.
1723 4984141 : (define_predicate "mult_operator"
1724 4984141 : (match_code "mult"))
1725 4984141 :
1726 4984141 : ;; Return true if this is a division operation.
1727 : (define_predicate "div_operator"
1728 : (match_code "div"))
1729 :
1730 4984141 : ;; Return true if this is an and, ior or xor operation.
1731 4984141 : (define_predicate "logic_operator"
1732 : (match_code "and,ior,xor"))
1733 :
1734 : ;; Return true if this is an and operation.
1735 17069733 : (define_predicate "and_operator"
1736 : (match_code "and"))
1737 17069733 :
1738 3451068 : ;; Return true if this is a plus, minus, and, ior or xor operation.
1739 : (define_predicate "plusminuslogic_operator"
1740 : (match_code "plus,minus,and,ior,xor"))
1741 :
1742 2772092 : ;; Return true for ARITHMETIC_P.
1743 : (define_predicate "arith_or_logical_operator"
1744 2772092 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1745 957744 : mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1746 :
1747 : ;; Return true for COMMUTATIVE_P.
1748 : (define_predicate "commutative_operator"
1749 0 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1750 :
1751 0 : ;; Return true if OP is a binary operator that can be promoted to wider mode.
1752 : (define_predicate "promotable_binary_operator"
1753 0 : (ior (match_code "plus,minus,and,ior,xor,ashift")
1754 0 : (and (match_code "mult")
1755 25647678 : (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1756 0 :
1757 : (define_predicate "compare_operator"
1758 : (match_code "compare"))
1759 :
1760 7632351 : (define_predicate "extract_high_operator"
1761 0 : (match_code "zero_extract,sign_extract,ashiftrt,lshiftrt")
1762 7632351 : {
1763 0 : return (const8_operand (XEXP (op, 1), VOIDmode)
1764 147750 : && (BINARY_P (op) || const8_operand (XEXP (op, 2), VOIDmode)));
1765 100 : })
1766 :
1767 147850 : ;; Return true if OP is a memory operand, aligned to
1768 0 : ;; less than its natural alignment.
1769 : (define_predicate "misaligned_operand"
1770 147750 : (and (match_code "mem")
1771 6312097 : (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1772 1596494 :
1773 147750 : ;; Return true if OP is a parallel for an mov{d,q,dqa,ps,pd} vec_select,
1774 545291 : ;; where one of the two operands of the vec_concat is const0_operand.
1775 147750 : (define_predicate "movq_parallel"
1776 2100385 : (match_code "parallel")
1777 540791 : {
1778 1952635 : unsigned nelt = XVECLEN (op, 0);
1779 1952635 : unsigned nelt2 = nelt >> 1;
1780 2100385 : unsigned i;
1781 147750 :
1782 1466738 : if (nelt < 2)
1783 : return false;
1784 :
1785 540791 : /* Validate that all of the elements are constants,
1786 540791 : lower halves of permute are lower halves of the first operand,
1787 : upper halves of permute come from any of the second operand. */
1788 15805055 : for (i = 0; i < nelt; ++i)
1789 : {
1790 6815918 : rtx er = XVECEXP (op, 0, i);
1791 2461735 : unsigned HOST_WIDE_INT ei;
1792 4354183 :
1793 2461735 : if (!CONST_INT_P (er))
1794 4354183 : return false;
1795 6815918 : ei = INTVAL (er);
1796 2461735 : if (i < nelt2 && ei != i)
1797 4354183 : return false;
1798 1206260 : if (i >= nelt2 && (ei < nelt || ei >= nelt << 1))
1799 4354183 : return false;
1800 4354183 : }
1801 4354183 :
1802 4354183 : return true;
1803 4354183 : })
1804 4354183 :
1805 4354183 : ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1806 5766027 : (define_predicate "vzeroall_operation"
1807 4354183 : (match_code "parallel")
1808 7177871 : {
1809 1411863 : unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1810 0 :
1811 3896 : if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1812 4354183 : return false;
1813 4354183 :
1814 69976 : for (i = 0; i < nregs; i++)
1815 : {
1816 62184 : rtx elt = XVECEXP (op, 0, i+1);
1817 :
1818 4416367 : if (GET_CODE (elt) != SET
1819 4416367 : || GET_CODE (SET_DEST (elt)) != REG
1820 62184 : || GET_MODE (SET_DEST (elt)) != V8SImode
1821 62184 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
1822 124368 : || SET_SRC (elt) != CONST0_RTX (V8SImode))
1823 979041 : return false;
1824 : }
1825 979041 : return true;
1826 : })
1827 332344 :
1828 332344 : ;; return true if OP is a vzeroall pattern.
1829 336240 : (define_predicate "vzeroall_pattern"
1830 332344 : (and (match_code "parallel")
1831 340136 : (match_code "unspec_volatile" "a")
1832 4009 : (match_test "XINT (XVECEXP (op, 0, 0), 1) == UNSPECV_VZEROALL")))
1833 0 :
1834 332344 : ;; return true if OP is a vzeroupper pattern.
1835 332344 : (define_predicate "vzeroupper_pattern"
1836 332344 : (and (match_code "parallel")
1837 4219270 : (match_code "unspec" "b")
1838 4604 : (match_test "XINT (XVECEXP (op, 0, 1), 1) == UNSPEC_CALLEE_ABI")
1839 4219270 : (match_test "INTVAL (XVECEXP (XVECEXP (op, 0, 1), 0, 0)) == ABI_VZEROUPPER")))
1840 0 :
1841 332344 : ;; Return true if OP is an addsub vec_merge operation
1842 : (define_predicate "addsub_vm_operator"
1843 : (match_code "vec_merge")
1844 8495 : {
1845 25656173 : rtx op0, op1;
1846 8495 : int swapped;
1847 25647678 : HOST_WIDE_INT mask;
1848 8495 : int nunits, elt;
1849 :
1850 8495 : op0 = XEXP (op, 0);
1851 8495 : op1 = XEXP (op, 1);
1852 :
1853 : /* Sanity check. */
1854 8495 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1855 : swapped = 0;
1856 4335 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1857 : swapped = 1;
1858 : else
1859 0 : gcc_unreachable ();
1860 :
1861 8495 : mask = INTVAL (XEXP (op, 2));
1862 8495 : nunits = GET_MODE_NUNITS (mode);
1863 :
1864 32859 : for (elt = 0; elt < nunits; elt++)
1865 : {
1866 : /* bit clear: take from op0, set: take from op1 */
1867 24610 : int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1868 :
1869 24610 : if (bit != ((elt & 1) ^ swapped))
1870 : return false;
1871 : }
1872 :
1873 : return true;
1874 : })
1875 :
1876 : ;; Return true if OP is an addsub vec_select/vec_concat operation
1877 8495 : (define_predicate "addsub_vs_operator"
1878 : (and (match_code "vec_select")
1879 8495 : (match_code "vec_concat" "0"))
1880 16744 : {
1881 8249 : rtx op0, op1;
1882 0 : bool swapped;
1883 0 : int nunits, elt;
1884 :
1885 0 : op0 = XEXP (XEXP (op, 0), 0);
1886 0 : op1 = XEXP (XEXP (op, 0), 1);
1887 :
1888 : /* Sanity check. */
1889 0 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1890 : swapped = false;
1891 0 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1892 : swapped = true;
1893 : else
1894 0 : gcc_unreachable ();
1895 :
1896 0 : nunits = GET_MODE_NUNITS (mode);
1897 0 : if (XVECLEN (XEXP (op, 1), 0) != nunits)
1898 : return false;
1899 :
1900 : /* We already checked that permutation is suitable for addsub,
1901 : so only look at the first element of the parallel. */
1902 0 : elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1903 :
1904 0 : return elt == (swapped ? nunits : 0);
1905 : })
1906 :
1907 : ;; Return true if OP is a parallel for an addsub vec_select.
1908 0 : (define_predicate "addsub_vs_parallel"
1909 : (and (match_code "parallel")
1910 0 : (match_code "const_int" "a"))
1911 0 : {
1912 0 : int nelt = XVECLEN (op, 0);
1913 493 : int elt, i;
1914 :
1915 493 : if (nelt < 2)
1916 493 : return false;
1917 :
1918 : /* Check that the permutation is suitable for addsub.
1919 : For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1920 493 : elt = INTVAL (XVECEXP (op, 0, 0));
1921 493 : if (elt == 0)
1922 : {
1923 447 : for (i = 1; i < nelt; ++i)
1924 439 : if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1925 : return false;
1926 : }
1927 54 : else if (elt == nelt)
1928 : {
1929 0 : for (i = 1; i < nelt; ++i)
1930 0 : if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1931 : return false;
1932 : }
1933 : else
1934 : return false;
1935 :
1936 : return true;
1937 : })
1938 :
1939 : ;; Return true if OP is a constant pool in perm{w,d,b} which contains index
1940 493 : ;; match pmov{dw,wb,qd}.
1941 : (define_predicate "permvar_truncate_operand"
1942 493 : (match_code "mem")
1943 986 : {
1944 0 : int nelt = GET_MODE_NUNITS (mode);
1945 16 : int perm[128];
1946 16 : int id;
1947 :
1948 32 : if (!INTEGRAL_MODE_P (mode) || !VECTOR_MODE_P (mode))
1949 : return false;
1950 :
1951 16 : if (nelt < 2)
1952 : return false;
1953 :
1954 16 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1955 : return false;
1956 :
1957 16 : id = exact_log2 (nelt);
1958 :
1959 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
1960 : For example V16HImode to V8HImode
1961 : { 0 2 4 6 8 10 12 14 * * * * * * * * }. */
1962 232 : for (int i = 0; i != nelt / 2; i++)
1963 216 : if ((perm[i] & ((1 << id) - 1)) != i * 2)
1964 : return false;
1965 :
1966 : return true;
1967 : })
1968 :
1969 : ;; Return true if OP is a constant pool in shufb which contains index
1970 49 : ;; match pmovdw.
1971 : (define_predicate "pshufb_truncv4siv4hi_operand"
1972 16 : (match_code "mem")
1973 65 : {
1974 16 : int perm[128];
1975 :
1976 8 : if (mode != E_V16QImode)
1977 : return false;
1978 8 :
1979 8 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1980 : return false;
1981 :
1982 : /* Check that the permutation is suitable for pmovdw.
1983 : For example V4SImode to V4HImode
1984 : { 0 1 4 5 8 9 12 13 * * * * * * * * }.
1985 : index = i % 2 + (i / 2) * 4. */
1986 58 : for (int i = 0; i != 8; i++)
1987 : {
1988 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
1989 52 : if (perm[i] & 128)
1990 : return false;
1991 :
1992 52 : if ((perm[i] & 15) != ((i & 1) + (i & 0xFE) * 2))
1993 : return false;
1994 : }
1995 :
1996 : return true;
1997 : })
1998 :
1999 : ;; Return true if OP is a constant pool in shufb which contains index
2000 11 : ;; match pmovdw.
2001 : (define_predicate "pshufb_truncv8hiv8qi_operand"
2002 8 : (match_code "mem")
2003 17 : {
2004 6 : int perm[128];
2005 :
2006 11 : if (mode != E_V16QImode)
2007 : return false;
2008 11 :
2009 11 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
2010 : return false;
2011 :
2012 : /* Check that the permutation is suitable for pmovwb.
2013 : For example V16QImode to V8QImode
2014 : { 0 2 4 6 8 10 12 14 * * * * * * * * }.
2015 : index = i % 2 + (i / 2) * 4. */
2016 57 : for (int i = 0; i != 8; i++)
2017 : {
2018 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
2019 52 : if (perm[i] & 128)
2020 : return false;
2021 :
2022 52 : if ((perm[i] & 15) != i * 2)
2023 : return false;
2024 : }
2025 :
2026 : return true;
2027 : })
2028 :
2029 : ;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select,
2030 14 : ;; where one of the two operands of the vec_concat is const0_operand.
2031 : (define_predicate "pmovzx_parallel"
2032 11 : (and (match_code "parallel")
2033 19 : (match_code "const_int" "a"))
2034 5 : {
2035 1483179 : int nelt = XVECLEN (op, 0);
2036 1483179 : int elt, i;
2037 :
2038 1483179 : if (nelt < 2)
2039 : return false;
2040 :
2041 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
2042 : For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */
2043 1483177 : elt = INTVAL (XVECEXP (op, 0, 0));
2044 1483177 : if (elt == 0)
2045 : {
2046 3440257 : for (i = 1; i < nelt; ++i)
2047 2950968 : if ((i & 1) != 0)
2048 : {
2049 1889213 : if (INTVAL (XVECEXP (op, 0, i)) < nelt)
2050 : return false;
2051 : }
2052 1061755 : else if (INTVAL (XVECEXP (op, 0, i)) != i / 2)
2053 : return false;
2054 : }
2055 : else
2056 : return false;
2057 :
2058 : return true;
2059 : })
2060 :
2061 : ;; Return true if OP is a parallel for an insertps vec_select,
2062 1483179 : ;; where one of the two operands of the vec_concat is const0_operand.
2063 : (define_predicate "insertps_parallel"
2064 1483179 : (and (match_code "parallel")
2065 2966358 : (match_code "const_int" "a"))
2066 0 : {
2067 12845 : int i;
2068 :
2069 12845 : if (XVECLEN (op, 0) != 4)
2070 12845 : return false;
2071 :
2072 : /* One element in [0..3], and the other 3 in [4..7]. */
2073 : bool found = false;
2074 41383 : for (i = 0; i < 4; ++i)
2075 39764 : if (INTVAL (XVECEXP (op, 0, i)) < 4)
2076 : {
2077 24071 : if (found)
2078 : return false;
2079 : found = true;
2080 : }
2081 :
2082 : return found;
2083 : })
2084 :
2085 : ;; Return true if OP is a const vector with duplicate value.
2086 12845 : (define_predicate "const_vector_duplicate_operand"
2087 : (match_code "const_vector")
2088 12845 : {
2089 25690 : rtx elt = XVECEXP (op, 0, 0);
2090 0 : int i, nelt = XVECLEN (op, 0);
2091 :
2092 96 : for (i = 1; i < nelt; ++i)
2093 93 : if (!rtx_equal_p (elt, XVECEXP (op, 0, i)))
2094 3 : return false;
2095 : return true;
2096 : })
2097 :
2098 : ;; Return true if OP is a parallel for a vbroadcast permute.
2099 3 : (define_predicate "avx_vbroadcast_operand"
2100 : (and (match_code "parallel")
2101 3 : (match_code "const_int" "a"))
2102 6 : {
2103 3 : rtx elt = XVECEXP (op, 0, 0);
2104 389142 : int i, nelt = XVECLEN (op, 0);
2105 :
2106 : /* Don't bother checking there are the right number of operands,
2107 389142 : merely that they're all identical. */
2108 492007 : for (i = 1; i < nelt; ++i)
2109 277316 : if (XVECEXP (op, 0, i) != elt)
2110 : return false;
2111 : return true;
2112 : })
2113 :
2114 : ;; Return true if OP is a parallel for a vbroadcastf128 permute.
2115 389142 : (define_predicate "avx_vbroadcast128_operand"
2116 : (and (match_code "parallel")
2117 389142 : (match_code "const_int" "a"))
2118 778284 : {
2119 0 : int i, nelt = XVECLEN (op, 0);
2120 1400049 : int half = nelt / 2;
2121 :
2122 2329428 : for (i = 0; i < nelt; ++i)
2123 1400049 : {
2124 2329278 : int index = INTVAL (XVECEXP (op, 0, i));
2125 2329278 : if ((i < half && index != i)
2126 1085215 : || (i >= half && index != (i - half)))
2127 : return false;
2128 : }
2129 :
2130 : return true;
2131 : })
2132 :
2133 : ;; Return true if OP is a parallel for a palignr permute.
2134 1400049 : (define_predicate "palignr_operand"
2135 : (and (match_code "parallel")
2136 1400049 : (match_code "const_int" "a"))
2137 2800098 : {
2138 0 : int elt = INTVAL (XVECEXP (op, 0, 0));
2139 26392 : int i, nelt = XVECLEN (op, 0);
2140 :
2141 : /* Check that an order in the permutation is suitable for palignr.
2142 26392 : For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
2143 61857 : for (i = 1; i < nelt; ++i)
2144 58092 : if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
2145 : return false;
2146 : return true;
2147 : })
2148 :
2149 : ;; Return true if OP is a proper third operand to vpblendw256.
2150 26392 : (define_predicate "avx2_pblendw_operand"
2151 : (match_code "const_int")
2152 26392 : {
2153 52784 : HOST_WIDE_INT val = INTVAL (op);
2154 0 : HOST_WIDE_INT low = val & 0xff;
2155 7033 : return val == ((low << 8) | low);
2156 : })
2157 :
2158 7033 : ;; Return true if OP is vector_operand or CONST_VECTOR.
2159 7033 : (define_predicate "general_vector_operand"
2160 : (ior (match_operand 0 "vector_operand")
2161 7033 : (match_code "const_vector")))
2162 7033 :
2163 : ;; Return true if OP is either -1 constant or stored in register.
2164 : (define_predicate "register_or_constm1_operand"
2165 : (ior (match_operand 0 "register_operand")
2166 13118 : (and (match_code "const_int")
2167 0 : (match_test "op == constm1_rtx"))))
2168 13118 :
2169 2459 : ;; Return true if the vector ends with between 12 and 18 register saves using
2170 : ;; RAX as the base address.
2171 : (define_predicate "save_multiple"
2172 226317 : (match_code "parallel")
2173 1324 : {
2174 226317 : const unsigned len = XVECLEN (op, 0);
2175 1324 : unsigned i;
2176 :
2177 : /* Starting from end of vector, count register saves. */
2178 319026 : for (i = 0; i < len; ++i)
2179 : {
2180 319026 : rtx src, dest, addr;
2181 319026 : rtx e = XVECEXP (op, 0, len - 1 - i);
2182 :
2183 319026 : if (GET_CODE (e) != SET)
2184 : break;
2185 :
2186 311981 : src = SET_SRC (e);
2187 311981 : dest = SET_DEST (e);
2188 :
2189 311981 : if (!REG_P (src) || !MEM_P (dest))
2190 : break;
2191 :
2192 92709 : addr = XEXP (dest, 0);
2193 :
2194 : /* Good if dest address is in RAX. */
2195 92709 : if (REG_P (addr) && REGNO (addr) == AX_REG)
2196 4202 : continue;
2197 :
2198 : /* Good if dest address is offset of RAX. */
2199 177014 : if (GET_CODE (addr) == PLUS
2200 88507 : && REG_P (XEXP (addr, 0))
2201 177014 : && REGNO (XEXP (addr, 0)) == AX_REG)
2202 88507 : continue;
2203 :
2204 : break;
2205 : }
2206 226317 : return (i >= 12 && i <= 18);
2207 : })
2208 :
2209 :
2210 226317 : ;; Return true if the vector ends with between 12 and 18 register loads using
2211 : ;; RSI as the base address.
2212 452634 : (define_predicate "restore_multiple"
2213 226317 : (match_code "parallel")
2214 0 : {
2215 7890062 : const unsigned len = XVECLEN (op, 0);
2216 7890062 : unsigned i;
2217 :
2218 7890062 : /* Starting from end of vector, count register restores. */
2219 7996390 : for (i = 0; i < len; ++i)
2220 : {
2221 7996390 : rtx src, dest, addr;
2222 7996390 : rtx e = XVECEXP (op, 0, len - 1 - i);
2223 :
2224 7996390 : if (GET_CODE (e) != SET)
2225 : break;
2226 :
2227 4502079 : src = SET_SRC (e);
2228 4502079 : dest = SET_DEST (e);
2229 :
2230 4502079 : if (!MEM_P (src) || !REG_P (dest))
2231 : break;
2232 :
2233 1385036 : addr = XEXP (src, 0);
2234 :
2235 : /* Good if src address is in RSI. */
2236 1385036 : if (REG_P (addr) && REGNO (addr) == SI_REG)
2237 5129 : continue;
2238 :
2239 : /* Good if src address is offset of RSI. */
2240 1481106 : if (GET_CODE (addr) == PLUS
2241 939867 : && REG_P (XEXP (addr, 0))
2242 2254479 : && REGNO (XEXP (addr, 0)) == SI_REG)
2243 101199 : continue;
2244 :
2245 : break;
2246 : }
2247 7890062 : return (i >= 12 && i <= 18);
2248 : })
2249 :
2250 : ;; Keylocker specific predicates
2251 7890062 : (define_predicate "encodekey128_operation"
2252 : (match_code "parallel")
2253 15780124 : {
2254 7890062 : unsigned i;
2255 0 : rtx elt;
2256 :
2257 108 : if (XVECLEN (op, 0) != 8)
2258 : return false;
2259 108 :
2260 392 : for(i = 0; i < 3; i++)
2261 : {
2262 294 : elt = XVECEXP (op, 0, i + 1);
2263 294 : if (GET_CODE (elt) != SET
2264 294 : || GET_CODE (SET_DEST (elt)) != REG
2265 294 : || GET_MODE (SET_DEST (elt)) != V2DImode
2266 294 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2267 294 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2268 294 : || GET_MODE (SET_SRC (elt)) != V2DImode
2269 294 : || XVECLEN(SET_SRC (elt), 0) != 1
2270 588 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2271 : return false;
2272 : }
2273 :
2274 392 : for(i = 4; i < 7; i++)
2275 : {
2276 294 : elt = XVECEXP (op, 0, i);
2277 294 : if (GET_CODE (elt) != CLOBBER
2278 294 : || GET_MODE (elt) != VOIDmode
2279 294 : || GET_CODE (XEXP (elt, 0)) != REG
2280 294 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2281 588 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2282 : return false;
2283 : }
2284 :
2285 98 : elt = XVECEXP (op, 0, 7);
2286 98 : if (GET_CODE (elt) != CLOBBER
2287 98 : || GET_MODE (elt) != VOIDmode
2288 98 : || GET_CODE (XEXP (elt, 0)) != REG
2289 98 : || GET_MODE (XEXP (elt, 0)) != CCmode
2290 196 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2291 0 : return false;
2292 : return true;
2293 : })
2294 :
2295 : (define_predicate "encodekey256_operation"
2296 108 : (match_code "parallel")
2297 : {
2298 337 : unsigned i;
2299 108 : rtx elt;
2300 0 :
2301 121 : if (XVECLEN (op, 0) != 9)
2302 : return false;
2303 :
2304 121 : elt = SET_SRC (XVECEXP (op, 0, 0));
2305 112 : elt = XVECEXP (elt, 0, 2);
2306 112 : if (!REG_P (elt)
2307 112 : || REGNO(elt) != GET_SSE_REGNO (1))
2308 : return false;
2309 :
2310 560 : for(i = 0; i < 4; i++)
2311 : {
2312 448 : elt = XVECEXP (op, 0, i + 1);
2313 448 : if (GET_CODE (elt) != SET
2314 448 : || GET_CODE (SET_DEST (elt)) != REG
2315 448 : || GET_MODE (SET_DEST (elt)) != V2DImode
2316 448 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2317 448 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2318 448 : || GET_MODE (SET_SRC (elt)) != V2DImode
2319 448 : || XVECLEN(SET_SRC (elt), 0) != 1
2320 896 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2321 : return false;
2322 : }
2323 :
2324 448 : for(i = 4; i < 7; i++)
2325 : {
2326 336 : elt = XVECEXP (op, 0, i + 1);
2327 336 : if (GET_CODE (elt) != CLOBBER
2328 336 : || GET_MODE (elt) != VOIDmode
2329 336 : || GET_CODE (XEXP (elt, 0)) != REG
2330 336 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2331 672 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2332 : return false;
2333 : }
2334 :
2335 112 : elt = XVECEXP (op, 0, 8);
2336 112 : if (GET_CODE (elt) != CLOBBER
2337 112 : || GET_MODE (elt) != VOIDmode
2338 112 : || GET_CODE (XEXP (elt, 0)) != REG
2339 112 : || GET_MODE (XEXP (elt, 0)) != CCmode
2340 224 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2341 0 : return false;
2342 : return true;
2343 : })
2344 :
2345 :
2346 121 : (define_predicate "aeswidekl_operation"
2347 : (match_code "parallel")
2348 242 : {
2349 121 : unsigned i;
2350 0 : rtx elt;
2351 :
2352 5796 : for (i = 0; i < 8; i++)
2353 : {
2354 660 : elt = XVECEXP (op, 0, i + 1);
2355 5168 : if (GET_CODE (elt) != SET
2356 5168 : || GET_CODE (SET_DEST (elt)) != REG
2357 5168 : || GET_MODE (SET_DEST (elt)) != V2DImode
2358 5168 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2359 5168 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2360 5168 : || GET_MODE (SET_SRC (elt)) != V2DImode
2361 5168 : || XVECLEN (SET_SRC (elt), 0) != 1
2362 5168 : || !REG_P (XVECEXP (SET_SRC (elt), 0, 0))
2363 10304 : || REGNO (XVECEXP (SET_SRC (elt), 0, 0)) != GET_SSE_REGNO (i))
2364 : return false;
2365 : }
2366 : return true;
2367 : })
2368 :
2369 : ;; Return true if OP is a memory operand that can be also used in APX
2370 660 : ;; EVEX-encoded patterns (i.e. APX NDD/NF) with immediate operand. With
2371 : ;; non-default address space, segment register or address size prefix,
2372 1320 : ;; APX EVEX-encoded instruction length can exceed the 15 byte size limit.
2373 660 : (define_predicate "apx_evex_memory_operand"
2374 0 : (match_operand 0 "memory_operand")
2375 : {
2376 : /* OK if immediate operand size < 4 bytes. */
2377 1686 : if (GET_MODE_SIZE (mode) < 4)
2378 1686 : return true;
2379 :
2380 1527 : bool default_addr = ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (op));
2381 1695 : bool address_size_prefix = TARGET_X32 && Pmode == SImode;
2382 :
2383 1527 : struct ix86_address parts;
2384 1527 : int ok;
2385 :
2386 1527 : op = XEXP (op, 0);
2387 1527 : ok = ix86_decompose_address (op, &parts);
2388 1527 : gcc_assert (ok);
2389 :
2390 1527 : if (default_addr)
2391 : {
2392 : /* Default address space. */
2393 :
2394 : /* Not OK with address size prefix, index register and disp. */
2395 691 : if (address_size_prefix
2396 168 : && parts.index
2397 42 : && parts.disp
2398 42 : && parts.disp != const0_rtx)
2399 42 : return false;
2400 : }
2401 : else
2402 : {
2403 : /* Non-default address space. */
2404 :
2405 : /* Not OK without base register. */
2406 836 : if (!parts.base)
2407 : return false;
2408 :
2409 : /* Not OK with disp and address size prefix. */
2410 668 : if (address_size_prefix && parts.disp)
2411 0 : return false;
2412 : }
2413 :
2414 : return true;
2415 : })
2416 :
2417 : ;; Return true if OP is a memory operand which can be used in APX EVEX-encoded
2418 1804 : ;; ADD patterns (i.e. APX NDD/NF) for with register source operand.
2419 : ;; UNSPEC_GOTNTPOFF memory operand is allowed with APX EVEX-encoded ADD only if
2420 3490 : ;; R_X86_64_CODE_6_GOTTPOFF works.
2421 1686 : (define_predicate "apx_evex_add_memory_operand"
2422 : (match_operand 0 "memory_operand")
2423 : {
2424 : /* OK if "add %reg1, name@gottpoff(%rip), %reg2" or
2425 : "{nf} add name@gottpoff(%rip), %reg1" are supported. */
2426 : if (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF)
2427 : return true;
2428 :
2429 : op = XEXP (op, 0);
2430 :
2431 : /* Disallow APX EVEX-encoded ADD with UNSPEC_GOTNTPOFF. */
2432 : if (GET_CODE (op) == CONST
2433 : && GET_CODE (XEXP (op, 0)) == UNSPEC
2434 : && XINT (XEXP (op, 0), 1) == UNSPEC_GOTNTPOFF)
2435 : return false;
2436 :
2437 : return true;
2438 : })
2439 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2440 : /* (content generated from coverage data) */
2441 848 : /* BEGIN: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2442 : /* ... */
2443 848 : /* ... */
2444 848 : /* ... */
2445 : /* END: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2446 : /* ... */
2447 : /* ... */
2448 1009169236 : /* BEGIN: function "_Z19lookup_constraint_1PKc" */
2449 : /* ... */
2450 1009169236 : /* ... */
2451 : /* ... */
2452 : /* ... */
2453 : /* ... */
2454 0 : /* ... */
2455 0 : /* ... */
2456 0 : /* ... */
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2464 8585170 : /* ... */
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2466 136595292 : /* ... */
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2468 137069 : /* ... */
2469 : /* ... */
2470 1723550 : /* ... */
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2472 1440723 : /* ... */
2473 : /* ... */
2474 57614308 : /* ... */
2475 : /* ... */
2476 52584062 : /* ... */
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2478 101793658 : /* ... */
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2540 1418 : /* (content generated from coverage data) */
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2554 4023355 : /* ... */
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2558 1378195 : /* ... */
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2560 19928 : /* (content generated from coverage data) */
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2562 197214064 : /* ... */
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2564 1180065 : /* ... */
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2566 142809453 : /* ... */
2567 : /* ... */
2568 3153896 : /* ... */
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2570 474279 : /* ... */
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2590 8686140 : /* ... */
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2594 1327812 : /* ... */
2595 : /* ... */
2596 0 : /* ... */
2597 : /* ... */
2598 0 : /* ... */
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2605 : /* ... */
2606 220901 : /* ... */
2607 : /* ... */
2608 8293 : /* ... */
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2610 6193571 : /* ... */
2611 : /* ... */
2612 158284 : /* ... */
2613 : /* ... */
2614 270005 : /* ... */
2615 : /* ... */
2616 3489 : /* ... */
2617 : /* ... */
2618 0 : /* ... */
2619 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2645 0 : /* ... */
2646 0 : /* ... */
2647 0 : /* ... */
2648 : /* ... */
2649 : /* ... */
2650 1337 : /* ... */
2651 : /* END: function "_Z19lookup_constraint_1PKc" */
2652 : /* ... */
2653 : /* ... */
2654 : /* ... */
2655 : /* ... */
2656 : /* ... */
2657 : /* ... */
2658 : /* ... */
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2697 : /* ... */
2698 : /* ... */
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2702 : /* ... */
2703 : /* ... */
2704 : /* ... */
2705 : /* ... */
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2707 : /* ... */
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2709 : /* ... */
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2711 : /* ... */
2712 : /* ... */
2713 : /* ... */
2714 : /* ... */
2715 : /* ... */
2716 : /* ... */
2717 : /* ... */
2718 : /* ... */
2719 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2720 : /* (content generated from coverage data) */
2721 : /* ... */
2722 : /* ... */
2723 : /* ... */
2724 : /* ... */
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2730 : /* ... */
2731 : /* ... */
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2733 : /* ... */
2734 : /* ... */
2735 : /* ... */
2736 : /* ... */
2737 : /* ... */
2738 : /* ... */
2739 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2740 : /* (content generated from coverage data) */
2741 : /* ... */
2742 : /* ... */
2743 : /* ... */
2744 : /* ... */
2745 : /* ... */
2746 : /* ... */
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2880 : /* (content generated from coverage data) */
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2913 7420251601 : /* BEGIN: function "_Z26reg_class_for_constraint_114constraint_num" */
2914 : /* ... */
2915 7420251601 : /* ... */
2916 : /* ... */
2917 : /* ... */
2918 : /* ... */
2919 136819294 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2921 54758684 : /* ... */
2922 23648218 : /* ... */
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2924 24837295 : /* ... */
2925 9877613 : /* ... */
2926 749203 : /* ... */
2927 957747 : /* ... */
2928 795167 : /* ... */
2929 1456138 : /* ... */
2930 218627331 : /* ... */
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2932 8637 : /* ... */
2933 920272 : /* ... */
2934 45241072 : /* ... */
2935 673084062 : /* ... */
2936 242859053 : /* ... */
2937 1516296045 : /* ... */
2938 14331 : /* ... */
2939 5626782 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2940 4022928 : /* (content generated from coverage data) */
2941 1312022 : /* ... */
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2943 1378191 : /* ... */
2944 14125 : /* ... */
2945 186549930 : /* ... */
2946 320923 : /* ... */
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2948 2758545 : /* ... */
2949 419343 : /* ... */
2950 : /* ... */
2951 131341 : /* ... */
2952 6192351 : /* ... */
2953 : /* ... */
2954 : /* ... */
2955 : /* ... */
2956 : /* END: function "_Z26reg_class_for_constraint_114constraint_num" */
2957 : /* ... */
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2959 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2979 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2995 : /* ... */
2996 : /* ... */
2997 : /* ... */
2998 : /* ... */
2999 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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3018 : /* ... */
3019 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
3020 7305762 : /* END: function "_Z32insn_const_int_ok_for_constraintl14constraint_num" */
3021 : /* ... */
3022 7305762 : /* ... */
3023 : /* ... */
3024 1351653 : /* ... */
3025 1351653 : /* ... */
|
