Line data Source code
1 : ;; Predicate definitions for IA-32 and x86-64.
2 : ;; Copyright (C) 2004-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; Return true if OP is either a i387 or SSE fp register.
21 : (define_predicate "any_fp_register_operand"
22 : (and (match_code "reg")
23 129896101 : (match_test "ANY_FP_REGNO_P (REGNO (op))")))
24 40527 :
25 : ;; Return true if OP is an i387 fp register.
26 : (define_predicate "fp_register_operand"
27 : (and (match_code "reg")
28 1577900 : (match_test "STACK_REGNO_P (REGNO (op))")))
29 1494327 :
30 427483502 : ;; True if the operand is a GENERAL class register.
31 : (define_predicate "general_reg_operand"
32 : (and (match_code "reg")
33 264768069 : (match_test "GENERAL_REGNO_P (REGNO (op))")))
34 197764521 :
35 442251374 : ;; True if the operand is an INDEX class register.
36 : (define_predicate "index_reg_operand"
37 : (and (match_code "reg")
38 659932 : (match_test "INDEX_REGNO_P (REGNO (op))")))
39 659857 :
40 660436 : ;; True if the operand is a nonimmediate operand with GENERAL class register.
41 : (define_predicate "nonimmediate_gr_operand"
42 : (if_then_else (match_code "reg")
43 54810321 : (match_test "GENERAL_REGNO_P (REGNO (op))")
44 60973150 : (match_operand 0 "nonimmediate_operand")))
45 76374084 :
46 : ;; True if the operand is a general operand with GENERAL class register.
47 : (define_predicate "general_gr_operand"
48 89141183 : (if_then_else (match_code "reg")
49 38532943 : (match_test "GENERAL_REGNO_P (REGNO (op))")
50 112817036 : (match_operand 0 "general_operand")))
51 :
52 : ;; True if the operand is an MMX register.
53 : (define_predicate "mmx_reg_operand"
54 38722160 : (and (match_code "reg")
55 192 : (match_test "MMX_REGNO_P (REGNO (op))")))
56 38722160 :
57 : ;; Match register operands, but include memory operands for
58 : ;; !TARGET_MMX_WITH_SSE.
59 : (define_predicate "register_mmxmem_operand"
60 614152 : (ior (match_operand 0 "register_operand")
61 12 : (and (not (match_test "TARGET_MMX_WITH_SSE"))
62 614152 : (match_operand 0 "memory_operand"))))
63 :
64 : ;; True if the operand is an SSE register.
65 154684806 : (define_predicate "sse_reg_operand"
66 : (and (match_code "reg")
67 154684806 : (match_test "SSE_REGNO_P (REGNO (op))")))
68 1703592 :
69 : ;; Return true if op is a QImode register.
70 : (define_predicate "any_QIreg_operand"
71 : (and (match_code "reg")
72 2171844 : (match_test "ANY_QI_REGNO_P (REGNO (op))")))
73 741913 :
74 2199371 : ;; Return true if op is one of QImode registers: %[abcd][hl].
75 : (define_predicate "QIreg_operand"
76 : (and (match_code "reg")
77 783800 : (match_test "QI_REGNO_P (REGNO (op))")))
78 611581 :
79 1619477 : ;; Return true if op is a QImode register operand other than %[abcd][hl].
80 : (define_predicate "ext_QIreg_operand"
81 3204514 : (and (match_test "TARGET_64BIT")
82 3204849 : (match_code "reg")
83 981144 : (not (match_test "QI_REGNO_P (REGNO (op))"))))
84 3466644 :
85 : ;; Return true if op is the AX register.
86 : (define_predicate "ax_reg_operand"
87 : (and (match_code "reg")
88 22270596 : (match_test "REGNO (op) == AX_REG")))
89 0 :
90 113206049 : ;; Return true if op is the flags register.
91 : (define_special_predicate "flags_reg_operand"
92 : (and (match_code "reg")
93 112183793 : (match_test "REGNO (op) == FLAGS_REG")))
94 :
95 40420266 : ;; True if the operand is a MASK register.
96 : (define_predicate "mask_reg_operand"
97 9680454 : (and (match_code "reg")
98 4559 : (match_test "MASK_REGNO_P (REGNO (op))")))
99 9685013 :
100 : ;; Match a DI, SI or HImode register operand.
101 : (define_special_predicate "int248_register_operand"
102 : (and (match_operand 0 "register_operand")
103 978372 : (ior (and (match_test "TARGET_64BIT")
104 280851 : (match_test "GET_MODE (op) == DImode"))
105 583268 : (match_test "GET_MODE (op) == SImode")
106 363070 : (match_test "GET_MODE (op) == HImode"))))
107 :
108 : ;; Match a DI, SI, HI or QImode nonimmediate_operand.
109 : (define_special_predicate "int_nonimmediate_operand"
110 437757 : (and (match_operand 0 "nonimmediate_operand")
111 591550 : (ior (and (match_test "TARGET_64BIT")
112 437757 : (match_test "GET_MODE (op) == DImode"))
113 172729 : (match_test "GET_MODE (op) == SImode")
114 : (match_test "GET_MODE (op) == HImode")
115 437757 : (match_test "GET_MODE (op) == QImode"))))
116 :
117 : ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
118 : (define_predicate "register_ssemem_operand"
119 2789138 : (if_then_else
120 2789138 : (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
121 2789138 : (match_operand 0 "nonimmediate_operand")
122 : (match_operand 0 "register_operand")))
123 :
124 1077693 : ;; Match nonimmediate operands, but exclude memory operands
125 : ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
126 1077693 : (define_predicate "nonimm_ssenomem_operand"
127 : (if_then_else
128 1077693 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
129 2155386 : (not (match_test "TARGET_MIX_SSE_I387")))
130 : (match_operand 0 "register_operand")
131 : (match_operand 0 "nonimmediate_operand")))
132 :
133 724973 : ;; The above predicate, suitable for x87 arithmetic operators.
134 : (define_predicate "x87nonimm_ssenomem_operand"
135 724973 : (if_then_else
136 724973 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
137 1449946 : (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
138 : (match_operand 0 "register_operand")
139 : (match_operand 0 "nonimmediate_operand")))
140 :
141 35055 : ;; Match register operands, include memory operand for TARGET_SSE4_1.
142 : (define_predicate "register_sse4nonimm_operand"
143 35055 : (if_then_else (match_test "TARGET_SSE4_1")
144 : (match_operand 0 "nonimmediate_operand")
145 : (match_operand 0 "register_operand")))
146 :
147 14090 : ;; Return true if VALUE is symbol reference
148 : (define_predicate "symbol_operand"
149 14090 : (match_code "symbol_ref"))
150 14090 :
151 : ;; Return true if VALUE is an ENDBR opcode in immediate field.
152 : (define_predicate "ix86_endbr_immediate_operand"
153 : (match_code "const_int")
154 6378218963 : {
155 6378218963 : if (flag_cf_protection & CF_BRANCH)
156 : {
157 1187050985 : unsigned HOST_WIDE_INT imm = UINTVAL (op);
158 1187050985 : unsigned HOST_WIDE_INT val = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
159 :
160 1187050985 : if (imm == val)
161 : return true;
162 :
163 : /* NB: Encoding is byte based. */
164 1187050777 : if (TARGET_64BIT)
165 2256913670 : for (; imm >= val; imm >>= 8)
166 1261981748 : if (imm == val)
167 : return true;
168 : }
169 :
170 : return false;
171 : })
172 :
173 : ;; Return true if VALUE can be stored in a sign extended immediate field.
174 8247231241 : (define_predicate "x86_64_immediate_operand"
175 : (match_code "const_int,symbol_ref,label_ref,const")
176 8247231241 : {
177 11287067761 : if (ix86_endbr_immediate_operand (op, VOIDmode))
178 : return false;
179 :
180 4908848547 : if (!TARGET_64BIT)
181 5095753741 : return immediate_operand (op, mode);
182 :
183 4721943604 : switch (GET_CODE (op))
184 : {
185 3864466763 : case CONST_INT:
186 3864466763 : {
187 3864466763 : HOST_WIDE_INT val = INTVAL (op);
188 3864466763 : return trunc_int_for_mode (val, SImode) == val;
189 : }
190 694089015 : case SYMBOL_REF:
191 : /* TLS symbols are not constant. */
192 694089015 : if (SYMBOL_REF_TLS_MODEL (op))
193 : return false;
194 :
195 : /* Load the external function address via the GOT slot. */
196 694053248 : if (ix86_force_load_from_GOT_p (op))
197 : return false;
198 :
199 : /* For certain code models, the symbolic references are known to fit.
200 : in CM_SMALL_PIC model we know it fits if it is local to the shared
201 : library. Don't count TLS SYMBOL_REFs here, since they should fit
202 : only if inside of UNSPEC handled below. */
203 694053146 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
204 694053146 : || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
205 :
206 23121539 : case LABEL_REF:
207 : /* For certain code models, the code is near as well. */
208 23121539 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
209 : || ix86_cmodel == CM_KERNEL);
210 :
211 140266287 : case CONST:
212 : /* We also may accept the offsetted memory references in certain
213 : special cases. */
214 140266287 : if (GET_CODE (XEXP (op, 0)) == UNSPEC)
215 734083 : switch (XINT (XEXP (op, 0), 1))
216 : {
217 : case UNSPEC_GOTPCREL:
218 : case UNSPEC_DTPOFF:
219 : case UNSPEC_GOTNTPOFF:
220 : case UNSPEC_NTPOFF:
221 : case UNSPEC_SECREL32:
222 : return true;
223 : default:
224 : break;
225 : }
226 :
227 139533714 : if (GET_CODE (XEXP (op, 0)) == PLUS)
228 : {
229 139532204 : rtx op1 = XEXP (XEXP (op, 0), 0);
230 139532204 : rtx op2 = XEXP (XEXP (op, 0), 1);
231 :
232 139532204 : if (ix86_cmodel == CM_LARGE && GET_CODE (op1) != UNSPEC)
233 : return false;
234 139532199 : if (!CONST_INT_P (op2))
235 : return false;
236 :
237 139532199 : HOST_WIDE_INT offset = INTVAL (op2);
238 139532199 : if (trunc_int_for_mode (offset, SImode) != offset)
239 : return false;
240 :
241 139526725 : switch (GET_CODE (op1))
242 : {
243 139190639 : case SYMBOL_REF:
244 : /* TLS symbols are not constant. */
245 139190639 : if (SYMBOL_REF_TLS_MODEL (op1))
246 : return false;
247 :
248 : /* Load the external function address via the GOT slot. */
249 139180089 : if (ix86_force_load_from_GOT_p (op1))
250 : return false;
251 :
252 : /* For CM_SMALL assume that latest object is 16MB before
253 : end of 31bits boundary. We may also accept pretty
254 : large negative constants knowing that all objects are
255 : in the positive half of address space. */
256 139180083 : if ((ix86_cmodel == CM_SMALL
257 195834 : || (ix86_cmodel == CM_MEDIUM
258 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
259 139180083 : && offset < 16*1024*1024)
260 : return true;
261 : /* For CM_KERNEL we know that all object resist in the
262 : negative half of 32bits address space. We may not
263 : accept negative offsets, since they may be just off
264 : and we may accept pretty large positive ones. */
265 199162 : if (ix86_cmodel == CM_KERNEL
266 0 : && offset > 0)
267 : return true;
268 : break;
269 :
270 5305 : case LABEL_REF:
271 : /* These conditions are similar to SYMBOL_REF ones, just the
272 : constraints for code models differ. */
273 5305 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
274 5305 : && offset < 16*1024*1024)
275 : return true;
276 0 : if (ix86_cmodel == CM_KERNEL
277 0 : && offset > 0)
278 : return true;
279 : break;
280 :
281 330781 : case UNSPEC:
282 330781 : switch (XINT (op1, 1))
283 : {
284 : case UNSPEC_DTPOFF:
285 : case UNSPEC_NTPOFF:
286 : return true;
287 : }
288 : break;
289 :
290 : default:
291 : break;
292 : }
293 : }
294 : break;
295 :
296 0 : default:
297 0 : gcc_unreachable ();
298 : }
299 :
300 : return false;
301 : })
302 :
303 : ;; Return true if VALUE can be stored in the zero extended immediate field.
304 5387286980 : (define_predicate "x86_64_zext_immediate_operand"
305 : (match_code "const_int,symbol_ref,label_ref,const")
306 5387286980 : {
307 730891438 : if (ix86_endbr_immediate_operand (op, VOIDmode))
308 4908848798 : return false;
309 4908848798 :
310 730891290 : switch (GET_CODE (op))
311 4908848798 : {
312 5574024160 : case CONST_INT:
313 665175362 : return !(INTVAL (op) & ~HOST_WIDE_INT_C (0xffffffff));
314 :
315 59538248 : case SYMBOL_REF:
316 4908848798 : /* TLS symbols are not constant. */
317 4968387046 : if (SYMBOL_REF_TLS_MODEL (op))
318 265092002 : return false;
319 :
320 : /* Load the external function address via the GOT slot. */
321 59503352 : if (ix86_force_load_from_GOT_p (op))
322 730891438 : return false;
323 :
324 : /* For certain code models, the symbolic references are known to fit. */
325 59503251 : return (ix86_cmodel == CM_SMALL
326 59503251 : || (ix86_cmodel == CM_MEDIUM
327 219 : && !SYMBOL_REF_FAR_ADDR_P (op)));
328 :
329 2146989 : case LABEL_REF:
330 : /* For certain code models, the code is near as well. */
331 2146989 : return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
332 :
333 4030691 : case CONST:
334 : /* We also may accept the offsetted memory references in certain
335 : special cases. */
336 4030691 : if (GET_CODE (XEXP (op, 0)) == PLUS)
337 : {
338 4026025 : rtx op1 = XEXP (XEXP (op, 0), 0);
339 4026025 : rtx op2 = XEXP (XEXP (op, 0), 1);
340 :
341 4026025 : if (ix86_cmodel == CM_LARGE)
342 : return false;
343 4026023 : if (!CONST_INT_P (op2))
344 : return false;
345 :
346 4026023 : HOST_WIDE_INT offset = INTVAL (op2);
347 4026023 : if (trunc_int_for_mode (offset, SImode) != offset)
348 : return false;
349 :
350 4023113 : switch (GET_CODE (op1))
351 : {
352 4022610 : case SYMBOL_REF:
353 : /* TLS symbols are not constant. */
354 4022610 : if (SYMBOL_REF_TLS_MODEL (op1))
355 : return false;
356 :
357 : /* Load the external function address via the GOT slot. */
358 4013288 : if (ix86_force_load_from_GOT_p (op1))
359 : return false;
360 :
361 : /* For small code model we may accept pretty large positive
362 : offsets, since one bit is available for free. Negative
363 : offsets are limited by the size of NULL pointer area
364 : specified by the ABI. */
365 4013282 : if ((ix86_cmodel == CM_SMALL
366 164938 : || (ix86_cmodel == CM_MEDIUM
367 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
368 4013282 : && offset > -0x10000)
369 : return true;
370 : /* ??? For the kernel, we may accept adjustment of
371 : -0x10000000, since we know that it will just convert
372 : negative address space to positive, but perhaps this
373 : is not worthwhile. */
374 : break;
375 :
376 0 : case LABEL_REF:
377 : /* These conditions are similar to SYMBOL_REF ones, just the
378 : constraints for code models differ. */
379 0 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
380 0 : && offset > -0x10000)
381 : return true;
382 : break;
383 :
384 : default:
385 : return false;
386 : }
387 : }
388 : break;
389 :
390 0 : default:
391 0 : gcc_unreachable ();
392 : }
393 : return false;
394 : })
395 :
396 : ;; Return true if VALUE is a constant integer whose negation satisfies
397 976766265 : ;; x86_64_immediate_operand.
398 : (define_predicate "x86_64_neg_const_int_operand"
399 976766265 : (match_code "const_int")
400 : {
401 730927163 : HOST_WIDE_INT val = -UINTVAL (op);
402 14775 : if (mode == DImode && trunc_int_for_mode (val, SImode) != val)
403 730891438 : return false;
404 35028 : if (flag_cf_protection & CF_BRANCH)
405 730891438 : {
406 16348 : unsigned HOST_WIDE_INT endbr = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
407 16348 : if ((val & HOST_WIDE_INT_C (0xffffffff)) == endbr)
408 : return false;
409 730891438 : }
410 730891438 : return true;
411 56229376 : })
412 :
413 : ;; Return true if VALUE is a constant integer whose low and high words satisfy
414 49061 : ;; x86_64_immediate_operand.
415 35725 : (define_predicate "x86_64_hilo_int_operand"
416 84786 : (match_code "const_int,const_wide_int")
417 35725 : {
418 42475055 : switch (GET_CODE (op))
419 : {
420 42425661 : case CONST_INT:
421 42475055 : return x86_64_immediate_operand (op, mode);
422 :
423 49394 : case CONST_WIDE_INT:
424 49394 : gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
425 49394 : return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
426 : DImode)
427 49394 : && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
428 : 1)),
429 : DImode));
430 :
431 0 : default:
432 0 : gcc_unreachable ();
433 : }
434 : })
435 :
436 : ;; Return true if VALUE is a constant integer whose value is
437 43154072 : ;; x86_64_immediate_operand value zero extended from word mode to mode.
438 : (define_predicate "x86_64_dwzext_immediate_operand"
439 43154072 : (match_code "const_int,const_wide_int")
440 : {
441 3742 : if (ix86_endbr_immediate_operand (op, VOIDmode))
442 42475055 : return false;
443 42475055 :
444 3742 : switch (GET_CODE (op))
445 : {
446 1624 : case CONST_INT:
447 1624 : if (!TARGET_64BIT)
448 42475055 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff);
449 1624 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff);
450 :
451 2118 : case CONST_WIDE_INT:
452 5860 : if (!TARGET_64BIT)
453 : return false;
454 2118 : return (CONST_WIDE_INT_NUNITS (op) == 2
455 2118 : && CONST_WIDE_INT_ELT (op, 1) == 0
456 4236 : && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode)
457 2118 : == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0)));
458 :
459 0 : default:
460 0 : gcc_unreachable ();
461 : }
462 : })
463 :
464 : ;; Return true if size of VALUE can be stored in a sign
465 3742 : ;; extended immediate field.
466 : (define_predicate "x86_64_immediate_size_operand"
467 3742 : (and (match_code "symbol_ref")
468 0 : (ior (not (match_test "TARGET_64BIT"))
469 0 : (match_test "ix86_cmodel == CM_SMALL")
470 0 : (match_test "ix86_cmodel == CM_KERNEL"))))
471 0 :
472 : ;; Return true if OP is general operand representable on x86_64.
473 : (define_predicate "x86_64_general_operand"
474 145749808 : (if_then_else (match_test "TARGET_64BIT")
475 145753550 : (ior (match_operand 0 "nonimmediate_operand")
476 3742 : (match_operand 0 "x86_64_immediate_operand"))
477 145749808 : (match_operand 0 "general_operand")))
478 60166792 :
479 : ;; Return true if OP's both words are general operands representable
480 60166792 : ;; on x86_64.
481 : (define_predicate "x86_64_hilo_general_operand"
482 60166792 : (if_then_else (match_test "TARGET_64BIT")
483 : (ior (match_operand 0 "nonimmediate_operand")
484 : (match_operand 0 "x86_64_hilo_int_operand"))
485 : (match_operand 0 "general_operand")))
486 256097 :
487 : ;; Return true if OP is non-VOIDmode general operand representable
488 256097 : ;; on x86_64. This predicate is used in sign-extending conversion
489 : ;; operations that require non-VOIDmode immediate operands.
490 : (define_predicate "x86_64_sext_operand"
491 256097 : (and (match_test "GET_MODE (op) != VOIDmode")
492 : (match_operand 0 "x86_64_general_operand")))
493 :
494 : ;; Return true if OP is non-VOIDmode general operand. This predicate
495 11471 : ;; is used in sign-extending conversion operations that require
496 : ;; non-VOIDmode immediate operands.
497 11471 : (define_predicate "sext_operand"
498 11471 : (and (match_test "GET_MODE (op) != VOIDmode")
499 : (match_operand 0 "general_operand")))
500 :
501 : ;; Return true if OP is representable on x86_64 as zero-extended operand.
502 3743394 : ;; This predicate is used in zero-extending conversion operations that
503 : ;; require non-VOIDmode immediate operands.
504 3743394 : (define_predicate "x86_64_zext_operand"
505 3743394 : (if_then_else (match_test "TARGET_64BIT")
506 : (ior (match_operand 0 "nonimmediate_operand")
507 : (and (match_operand 0 "x86_64_zext_immediate_operand")
508 114377 : (match_test "GET_MODE (op) != VOIDmode")))
509 : (match_operand 0 "nonimmediate_operand")))
510 :
511 : ;; Return true if OP is general operand representable on x86_64
512 2444294 : ;; as either sign extended or zero extended constant.
513 : (define_predicate "x86_64_szext_general_operand"
514 2444294 : (if_then_else (match_test "TARGET_64BIT")
515 : (ior (match_operand 0 "nonimmediate_operand")
516 : (match_operand 0 "x86_64_immediate_operand")
517 : (match_operand 0 "x86_64_zext_immediate_operand"))
518 29426425 : (match_operand 0 "general_operand")))
519 :
520 29426425 : ;; Return true if OP is nonmemory operand representable on x86_64.
521 : (define_predicate "x86_64_nonmemory_operand"
522 29426425 : (if_then_else (match_test "TARGET_64BIT")
523 : (ior (match_operand 0 "register_operand")
524 : (match_operand 0 "x86_64_immediate_operand"))
525 : (match_operand 0 "nonmemory_operand")))
526 18814 :
527 : ;; Return true if OP is nonmemory operand representable on x86_64.
528 18814 : (define_predicate "x86_64_szext_nonmemory_operand"
529 18814 : (if_then_else (match_test "TARGET_64BIT")
530 : (ior (match_operand 0 "register_operand")
531 : (match_operand 0 "x86_64_immediate_operand")
532 : (match_operand 0 "x86_64_zext_immediate_operand"))
533 169141096 : (match_operand 0 "nonmemory_operand")))
534 :
535 : ;; Return true when operand is PIC expression that can be computed by lea
536 : ;; operation.
537 : (define_predicate "pic_32bit_operand"
538 : (match_code "const,symbol_ref,label_ref")
539 : {
540 169141096 : if (!flag_pic)
541 : return false;
542 :
543 : /* Rule out relocations that translate into 64bit constants. */
544 8043921 : if (TARGET_64BIT && GET_CODE (op) == CONST)
545 : {
546 150328 : rtx tmp = XEXP (op, 0);
547 150328 : if (GET_CODE (tmp) == PLUS && CONST_INT_P (XEXP (tmp, 1)))
548 148866 : tmp = XEXP (tmp, 0);
549 150328 : if (GET_CODE (tmp) == UNSPEC
550 1462 : && (XINT (tmp, 1) == UNSPEC_GOTOFF
551 1462 : || XINT (tmp, 1) == UNSPEC_GOT))
552 : return false;
553 : }
554 :
555 8042999 : return symbolic_operand (op, mode);
556 : })
557 :
558 : ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
559 1243969160 : (define_predicate "x86_64_movabs_operand"
560 : (and (match_operand 0 "nonmemory_operand")
561 1243969160 : (not (match_operand 0 "pic_32bit_operand"))))
562 :
563 169141096 : ;; Return true if OP is either a symbol reference or a sum of a symbol
564 169141096 : ;; reference and a constant.
565 169141096 : (define_predicate "symbolic_operand"
566 169141096 : (match_code "symbol_ref,label_ref,const")
567 : {
568 8403973 : switch (GET_CODE (op))
569 : {
570 169141096 : case SYMBOL_REF:
571 169141096 : case LABEL_REF:
572 179488 : return true;
573 :
574 182548 : case CONST:
575 182548 : op = XEXP (op, 0);
576 491886922 : if (SYMBOL_REF_P (op)
577 182548 : || LABEL_REF_P (op)
578 491886922 : || (GET_CODE (op) == UNSPEC
579 8504 : && (XINT (op, 1) == UNSPEC_GOT
580 8504 : || XINT (op, 1) == UNSPEC_GOTOFF
581 : || XINT (op, 1) == UNSPEC_SECREL32
582 8403973 : || XINT (op, 1) == UNSPEC_PCREL
583 : || XINT (op, 1) == UNSPEC_GOTPCREL)))
584 : return true;
585 174713 : if (GET_CODE (op) != PLUS
586 174044 : || !CONST_INT_P (XEXP (op, 1)))
587 : return false;
588 :
589 174044 : op = XEXP (op, 0);
590 174044 : if (SYMBOL_REF_P (op)
591 174044 : || LABEL_REF_P (op))
592 : return true;
593 : /* Only @GOTOFF and @SECREL32 get offsets. */
594 2123 : if (GET_CODE (op) != UNSPEC
595 2123 : || (XINT (op, 1) != UNSPEC_GOTOFF
596 0 : && XINT (op, 1) != UNSPEC_SECREL32))
597 : return false;
598 :
599 2123 : op = XVECEXP (op, 0, 0);
600 2123 : if (SYMBOL_REF_P (op)
601 2123 : || LABEL_REF_P (op))
602 2123 : return true;
603 : return false;
604 :
605 0 : default:
606 0 : gcc_unreachable ();
607 : }
608 : })
609 :
610 : ;; Return true if OP is a symbolic operand that resolves locally.
611 15803761 : (define_predicate "local_symbolic_operand"
612 : (match_code "const,label_ref,symbol_ref")
613 15803761 : {
614 2933671 : if (GET_CODE (op) == CONST
615 16273 : && GET_CODE (XEXP (op, 0)) == PLUS
616 8523 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
617 8523 : op = XEXP (XEXP (op, 0), 0);
618 8403973 :
619 2933671 : if (LABEL_REF_P (op))
620 : return true;
621 :
622 2888974 : if (!SYMBOL_REF_P (op))
623 8403973 : return false;
624 540333 :
625 2879101 : if (SYMBOL_REF_TLS_MODEL (op))
626 : return false;
627 :
628 2933671 : /* Dll-imported symbols are always external. */
629 2879101 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
630 : return false;
631 2879101 : if (SYMBOL_REF_LOCAL_P (op))
632 : return true;
633 :
634 : /* There is, however, a not insubstantial body of code in the rest of
635 : the compiler that assumes it can just stick the results of
636 : ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
637 : /* ??? This is a hack. Should update the body of the compiler to
638 : always create a DECL an invoke targetm.encode_section_info. */
639 93698 : if (strncmp (XSTR (op, 0), internal_label_prefix,
640 : internal_label_prefix_len) == 0)
641 0 : return true;
642 :
643 : return false;
644 : })
645 :
646 : (define_predicate "local_func_symbolic_operand"
647 2942357 : (match_operand 0 "local_symbolic_operand")
648 : {
649 2942357 : if (GET_CODE (op) == CONST
650 0 : && GET_CODE (XEXP (op, 0)) == PLUS
651 0 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
652 0 : op = XEXP (XEXP (op, 0), 0);
653 2933671 :
654 2933683 : if (SYMBOL_REF_P (op)
655 12 : && !SYMBOL_REF_FUNCTION_P (op))
656 0 : return false;
657 :
658 2933671 : return true;
659 2933671 : })
660 2830091 :
661 : ;; Test for a legitimate @GOTOFF operand.
662 30 : ;;
663 : ;; VxWorks does not impose a fixed gap between segments; the run-time
664 42 : ;; gap can be different from the object-file gap. We therefore can't
665 12 : ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
666 : ;; same segment as the GOT. Unfortunately, the flexibility of linker
667 : ;; scripts means that we can't be sure of that in general, so assume
668 : ;; @GOTOFF is not valid on VxWorks, except with the large code model.
669 2942290 : ;; The comments above seem to apply only to VxWorks releases before 7.
670 : (define_predicate "gotoff_operand"
671 2942290 : (and (ior (not (match_test "TARGET_VXWORKS_VAROFF"))
672 : (match_test "ix86_cmodel == CM_LARGE")
673 2942290 : (match_test "ix86_cmodel == CM_LARGE_PIC"))
674 : (match_operand 0 "local_symbolic_operand")))
675 :
676 : ;; Test for various thread-local symbols.
677 30084 : (define_special_predicate "tls_symbolic_operand"
678 : (and (match_code "symbol_ref")
679 30084 : (match_test "SYMBOL_REF_TLS_MODEL (op)")))
680 :
681 : (define_special_predicate "tls_modbase_operand"
682 : (and (match_code "symbol_ref")
683 72 : (match_test "op == ix86_tls_module_base ()")))
684 :
685 144 : (define_predicate "tls_address_pattern"
686 : (and (match_code "set,parallel,unspec,unspec_volatile")
687 231914092 : (match_test "ix86_tls_address_pattern_p (op)")))
688 0 :
689 231914092 : ;; Test for a pc-relative call operand
690 : (define_predicate "constant_call_address_operand"
691 231914092 : (match_code "symbol_ref")
692 363215578 : {
693 131301277 : if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
694 131301266 : || flag_force_indirect_call
695 262601248 : || (TARGET_INDIRECT_BRANCH_REGISTER
696 1022 : && ix86_nopic_noplt_attribute_p (op)))
697 1748 : return false;
698 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
699 231914092 : return false;
700 : return true;
701 : })
702 :
703 : ;; True for any non-virtual and non-eliminable register. Used in places where
704 136851034 : ;; instantiation of such a register may cause the pattern to not be recognized.
705 : (define_predicate "register_no_elim_operand"
706 131301486 : (match_operand 0 "register_operand")
707 268150772 : {
708 94541310 : if (SUBREG_P (op))
709 62551 : op = SUBREG_REG (op);
710 :
711 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
712 20457534 : because it is guaranteed to be reloaded into one. */
713 20457534 : if (MEM_P (op))
714 : return true;
715 :
716 20457534 : return !(op == arg_pointer_rtx
717 20429697 : || op == frame_pointer_rtx
718 20427280 : || VIRTUAL_REGISTER_P (op));
719 : })
720 :
721 : ;; Similarly, but include the stack pointer. This is used
722 25141999 : ;; to prevent esp from being used as an index reg.
723 : (define_predicate "register_no_SP_operand"
724 25141999 : (match_operand 0 "register_operand")
725 20457534 : {
726 331875 : if (SUBREG_P (op))
727 8027 : op = SUBREG_REG (op);
728 :
729 331875 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
730 : because it is guaranteed to be reloaded into one. */
731 331875 : if (MEM_P (op))
732 : return true;
733 :
734 331875 : return !(op == arg_pointer_rtx
735 331875 : || op == frame_pointer_rtx
736 331875 : || op == stack_pointer_rtx
737 331875 : || VIRTUAL_REGISTER_P (op));
738 : })
739 :
740 : ;; P6 processors will jump to the address after the decrement when %esp
741 368545 : ;; is used as a call operand, so they will execute return address as a code.
742 : ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
743 368545 :
744 331875 : (define_predicate "call_register_operand"
745 1807957 : (if_then_else (match_test "TARGET_64BIT")
746 : (match_operand 0 "register_operand")
747 : (match_operand 0 "register_no_SP_operand")))
748 1807957 :
749 18591416 : ;; Return false if this is any eliminable register. Otherwise general_operand.
750 1807957 : (define_predicate "general_no_elim_operand"
751 18591416 : (if_then_else (match_code "reg,subreg")
752 : (match_operand 0 "register_no_elim_operand")
753 : (match_operand 0 "general_operand")))
754 :
755 12276689 : ;; Return false if this is any eliminable register. Otherwise
756 : ;; register_operand or a constant.
757 12276689 : (define_predicate "nonmemory_no_elim_operand"
758 : (ior (match_operand 0 "register_no_elim_operand")
759 : (match_operand 0 "immediate_operand")))
760 :
761 618945 : ;; Test for a valid operand for indirect branch.
762 : (define_predicate "indirect_branch_operand"
763 618945 : (ior (match_operand 0 "register_operand")
764 571278 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
765 571251 : (not (match_test "TARGET_X32"))
766 : (match_operand 0 "memory_operand"))))
767 :
768 : ;; Return true if OP is a memory operands that can be used in sibcalls.
769 24001 : ;; Since sibcall never returns, we can only use call-clobbered register
770 : ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
771 : ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
772 : ;; and *sibcall_value_GOT_32 patterns.
773 : (define_predicate "sibcall_memory_operand"
774 : (match_operand 0 "memory_operand")
775 : {
776 24001 : op = XEXP (op, 0);
777 24001 : if (CONSTANT_P (op))
778 : return true;
779 10496 : if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
780 : {
781 9528 : int regno = REGNO (XEXP (op, 0));
782 9528 : if (!HARD_REGISTER_NUM_P (regno) || call_used_or_fixed_reg_p (regno))
783 : {
784 7810 : op = XEXP (op, 1);
785 7810 : if (GOT32_symbol_operand (op, VOIDmode))
786 : return true;
787 : }
788 : }
789 : return false;
790 : })
791 :
792 : ;; Return true if OP is a GOT memory operand.
793 1340989 : (define_predicate "GOT_memory_operand"
794 : (and (match_operand 0 "memory_operand")
795 1364990 : (match_code "const" "0")
796 24001 : (match_code "unspec" "00")
797 564 : (match_test "XINT (XEXP (XEXP (op, 0), 0), 1) == UNSPEC_GOTPCREL")))
798 :
799 : ;; Test for a valid operand for a call instruction.
800 462 : ;; Allow constant call address operands in Pmode only.
801 46898155 : (define_special_predicate "call_insn_operand"
802 462 : (ior (match_test "constant_call_address_operand
803 53035001 : (op, mode == VOIDmode ? mode : Pmode)")
804 : (match_operand 0 "call_register_operand")
805 824494 : (match_test "satisfies_constraint_Bw (op)")))
806 :
807 : ;; Similarly, but for tail calls, in which we cannot allow memory references.
808 : (define_special_predicate "sibcall_insn_operand"
809 1190013 : (ior (match_test "constant_call_address_operand
810 1349386 : (op, mode == VOIDmode ? mode : Pmode)")
811 1190013 : (match_operand 0 "register_no_elim_operand")
812 121902 : (match_test "satisfies_constraint_Bs (op)")))
813 :
814 : ;; Return true if OP is a 32-bit GOT symbol operand.
815 : (define_predicate "GOT32_symbol_operand"
816 9737 : (and (match_code "const")
817 : (match_code "unspec" "0")
818 9737 : (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_GOT")))
819 0 :
820 : ;; Match exactly zero.
821 : (define_predicate "const0_operand"
822 : (match_code "const_int,const_double,const_vector")
823 131144377 : {
824 131144377 : if (mode == VOIDmode)
825 20709320 : mode = GET_MODE (op);
826 131144377 : return op == CONST0_RTX (mode);
827 : })
828 :
829 : ;; Match one or a vector with all elements equal to one.
830 955995151 : (define_predicate "const1_operand"
831 : (match_code "const_int,const_double,const_vector")
832 955995151 : {
833 12411245 : if (mode == VOIDmode)
834 12408410 : mode = GET_MODE (op);
835 143555622 : return op == CONST1_RTX (mode);
836 131144377 : })
837 131144377 :
838 : ;; Match exactly -1.
839 13406642 : (define_predicate "constm1_operand"
840 : (and (match_code "const_int")
841 144551019 : (match_test "op == constm1_rtx")))
842 131144377 :
843 60017456 : ;; Match 0 or -1.
844 12411245 : (define_predicate "const0_or_m1_operand"
845 12414134 : (ior (match_operand 0 "const0_operand")
846 12411245 : (match_operand 0 "constm1_operand")))
847 2889 :
848 : ;; Match exactly eight.
849 : (define_predicate "const8_operand"
850 12411245 : (and (match_code "const_int")
851 12411245 : (match_test "INTVAL (op) == 8")))
852 2808 :
853 216445 : ;; Match exactly 128.
854 : (define_predicate "const128_operand"
855 26620081 : (and (match_code "const_int")
856 234671670 : (match_test "INTVAL (op) == 128")))
857 26620081 :
858 185663333 : ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
859 : (define_predicate "const_32bit_mask"
860 2742960 : (and (match_code "const_int")
861 1799134 : (match_test "trunc_int_for_mode (INTVAL (op), DImode)
862 4542094 : == HOST_WIDE_INT_C (0xffffffff)")))
863 :
864 : ;; Match 2, 4, or 8. Used for leal multiplicands.
865 : (define_predicate "const248_operand"
866 292443 : (match_code "const_int")
867 : {
868 292443 : HOST_WIDE_INT i = INTVAL (op);
869 292443 : return i == 2 || i == 4 || i == 8;
870 : })
871 :
872 : ;; Match 1, 2, or 3. Used for lea shift amounts.
873 982539 : (define_predicate "const123_operand"
874 : (match_code "const_int")
875 982539 : {
876 1202612 : HOST_WIDE_INT i = INTVAL (op);
877 220073 : return i == 1 || i == 2 || i == 3;
878 : })
879 :
880 220073 : ;; Match 2, 3, 6, or 7
881 228471 : (define_predicate "const2367_operand"
882 : (match_code "const_int")
883 228471 : {
884 220073 : HOST_WIDE_INT i = INTVAL (op);
885 0 : return i == 2 || i == 3 || i == 6 || i == 7;
886 : })
887 :
888 0 : ;; Match 1, 2, 4, or 8
889 0 : (define_predicate "const1248_operand"
890 : (match_code "const_int")
891 0 : {
892 108344 : HOST_WIDE_INT i = INTVAL (op);
893 108344 : return i == 1 || i == 2 || i == 4 || i == 8;
894 : })
895 :
896 108344 : ;; Match 3, 5, or 9. Used for leal multiplicands.
897 492230 : (define_predicate "const359_operand"
898 : (match_code "const_int")
899 492230 : {
900 538661 : HOST_WIDE_INT i = INTVAL (op);
901 46431 : return i == 3 || i == 5 || i == 9;
902 : })
903 :
904 46431 : ;; Match 4 or 8 to 11. Used for embeded rounding.
905 200947 : (define_predicate "const_4_or_8_to_11_operand"
906 : (match_code "const_int")
907 200947 : {
908 281065 : HOST_WIDE_INT i = INTVAL (op);
909 80118 : return i == 4 || (i >= 8 && i <= 11);
910 : })
911 :
912 80118 : ;; Match 4 or 8. Used for SAE.
913 80120 : (define_predicate "const48_operand"
914 : (match_code "const_int")
915 80120 : {
916 80118 : HOST_WIDE_INT i = INTVAL (op);
917 64620 : return i == 4 || i == 8;
918 : })
919 :
920 64620 : ;; Match 0 or 1.
921 64620 : (define_predicate "const_0_to_1_operand"
922 : (and (match_code "const_int")
923 64620 : (ior (match_test "op == const0_rtx")
924 292343 : (match_test "op == const1_rtx"))))
925 :
926 : ;; Match 0 to 3.
927 : (define_predicate "const_0_to_3_operand"
928 7272061 : (and (match_code "const_int")
929 13758155 : (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
930 7272061 :
931 : ;; Match 0 to 4.
932 : (define_predicate "const_0_to_4_operand"
933 0 : (and (match_code "const_int")
934 0 : (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
935 0 :
936 : ;; Match 0 to 5.
937 : (define_predicate "const_0_to_5_operand"
938 0 : (and (match_code "const_int")
939 0 : (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
940 0 :
941 : ;; Match 0 to 7.
942 : (define_predicate "const_0_to_7_operand"
943 784769 : (and (match_code "const_int")
944 1569524 : (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
945 784769 :
946 : ;; Match 0 to 15.
947 : (define_predicate "const_0_to_15_operand"
948 80903 : (and (match_code "const_int")
949 161790 : (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
950 80903 :
951 : ;; Match 0 to 31.
952 : (define_predicate "const_0_to_31_operand"
953 58875 : (and (match_code "const_int")
954 117182 : (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
955 58875 :
956 : ;; Match 0 to 63.
957 : (define_predicate "const_0_to_63_operand"
958 28854 : (and (match_code "const_int")
959 55893 : (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
960 28854 :
961 : ;; Match 0 to 127.
962 : (define_predicate "const_0_to_127_operand"
963 9956 : (and (match_code "const_int")
964 18932 : (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
965 9956 :
966 : ;; Match 0 to 255.
967 : (define_predicate "const_0_to_255_operand"
968 8564595 : (and (match_code "const_int")
969 17101410 : (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
970 8564595 :
971 : ;; Match (0 to 255) * 8
972 : (define_predicate "const_0_to_255_mul_8_operand"
973 435836 : (match_code "const_int")
974 : {
975 435836 : unsigned HOST_WIDE_INT val = INTVAL (op);
976 435836 : return val <= 255*8 && val % 8 == 0;
977 : })
978 :
979 : ;; Match 1 to 255 except multiples of 8
980 435838 : (define_predicate "const_0_to_255_not_mul_8_operand"
981 : (match_code "const_int")
982 435838 : {
983 1261193 : unsigned HOST_WIDE_INT val = INTVAL (op);
984 825341 : return val <= 255 && val % 8 != 0;
985 : })
986 :
987 825355 : ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
988 825355 : ;; for shift & compare patterns, as shifting by 0 does not change flags).
989 : (define_predicate "const_1_to_31_operand"
990 825355 : (and (match_code "const_int")
991 871711 : (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
992 :
993 : ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
994 : ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
995 93968 : (define_predicate "const_1_to_63_operand"
996 : (and (match_code "const_int")
997 93968 : (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
998 :
999 : ;; Match 2 or 3.
1000 : (define_predicate "const_2_to_3_operand"
1001 74055 : (and (match_code "const_int")
1002 148110 : (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
1003 74055 :
1004 : ;; Match 4 to 5.
1005 : (define_predicate "const_4_to_5_operand"
1006 5114 : (and (match_code "const_int")
1007 10228 : (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
1008 5114 :
1009 : ;; Match 4 to 7.
1010 : (define_predicate "const_4_to_7_operand"
1011 953758 : (and (match_code "const_int")
1012 1907516 : (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
1013 953758 :
1014 : ;; Match 6 to 7.
1015 : (define_predicate "const_6_to_7_operand"
1016 700 : (and (match_code "const_int")
1017 1400 : (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
1018 700 :
1019 : ;; Match 8 to 9.
1020 : (define_predicate "const_8_to_9_operand"
1021 504 : (and (match_code "const_int")
1022 1008 : (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
1023 504 :
1024 : ;; Match 8 to 11.
1025 : (define_predicate "const_8_to_11_operand"
1026 35605 : (and (match_code "const_int")
1027 71210 : (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
1028 35605 :
1029 : ;; Match 8 to 15.
1030 : (define_predicate "const_8_to_15_operand"
1031 39963 : (and (match_code "const_int")
1032 79926 : (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
1033 39963 :
1034 : ;; Match 10 to 11.
1035 : (define_predicate "const_10_to_11_operand"
1036 267 : (and (match_code "const_int")
1037 534 : (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
1038 267 :
1039 : ;; Match 12 to 13.
1040 : (define_predicate "const_12_to_13_operand"
1041 266 : (and (match_code "const_int")
1042 532 : (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
1043 266 :
1044 : ;; Match 12 to 15.
1045 : (define_predicate "const_12_to_15_operand"
1046 23786 : (and (match_code "const_int")
1047 47572 : (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
1048 23786 :
1049 : ;; Match 14 to 15.
1050 : (define_predicate "const_14_to_15_operand"
1051 266 : (and (match_code "const_int")
1052 532 : (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
1053 266 :
1054 : ;; Match 16 to 19.
1055 : (define_predicate "const_16_to_19_operand"
1056 1212 : (and (match_code "const_int")
1057 2424 : (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
1058 1212 :
1059 : ;; Match 16 to 31.
1060 : (define_predicate "const_16_to_31_operand"
1061 10399 : (and (match_code "const_int")
1062 20798 : (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
1063 10399 :
1064 : ;; Match 20 to 23.
1065 : (define_predicate "const_20_to_23_operand"
1066 788 : (and (match_code "const_int")
1067 1576 : (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
1068 788 :
1069 : ;; Match 24 to 27.
1070 : (define_predicate "const_24_to_27_operand"
1071 788 : (and (match_code "const_int")
1072 1576 : (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
1073 788 :
1074 : ;; Match 28 to 31.
1075 : (define_predicate "const_28_to_31_operand"
1076 788 : (and (match_code "const_int")
1077 1576 : (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
1078 788 :
1079 : (define_predicate "cmpps_imm_operand"
1080 : (ior (match_operand 0 "const_0_to_7_operand")
1081 4082 : (and (match_test "TARGET_AVX")
1082 : (match_operand 0 "const_0_to_31_operand"))))
1083 59783 :
1084 : ;; True if this is a constant appropriate for an increment or decrement.
1085 99234338 : (define_predicate "incdec_operand"
1086 : (match_code "const_int")
1087 : {
1088 : /* On Pentium4, the inc and dec operations causes extra dependency on flag
1089 : registers, since carry flag is not set. */
1090 99234338 : if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
1091 : return false;
1092 2560629 : return op == const1_rtx || op == constm1_rtx;
1093 : })
1094 :
1095 : ;; True for registers, or const_int_operand, used to vec_setm expander.
1096 122537332 : (define_predicate "vec_setm_sse41_operand"
1097 : (ior (and (match_operand 0 "register_operand")
1098 221772406 : (match_test "TARGET_SSE4_1"))
1099 99234338 : (match_code "const_int")))
1100 :
1101 : (define_predicate "vec_setm_avx2_operand"
1102 : (ior (and (match_operand 0 "register_operand")
1103 947 : (match_test "TARGET_AVX2"))
1104 0 : (match_code "const_int")))
1105 1209 :
1106 : (define_predicate "vec_setm_mmx_operand"
1107 : (ior (and (match_operand 0 "register_operand")
1108 22 : (match_test "TARGET_SSE4_1")
1109 252 : (match_test "TARGET_MMX_WITH_SSE"))
1110 252 : (match_code "const_int")))
1111 :
1112 : ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
1113 : (define_predicate "reg_or_pm1_operand"
1114 4332757 : (ior (match_operand 0 "register_operand")
1115 : (and (match_code "const_int")
1116 4332757 : (ior (match_test "op == const1_rtx")
1117 258069 : (match_test "op == constm1_rtx")))))
1118 241995 :
1119 : ;; True for registers, or (not: registers). Used to optimize 3-operand
1120 : ;; bitwise operation.
1121 : (define_predicate "regmem_or_bitnot_regmem_operand"
1122 678488 : (ior (match_operand 0 "nonimmediate_operand")
1123 : (and (match_code "not")
1124 678488 : (match_test "nonimmediate_operand (XEXP (op, 0), mode)"))))
1125 28805 :
1126 : ;; True for expressions valid for 3-operand ternlog instructions.
1127 : (define_predicate "ternlog_operand"
1128 : (and (match_code "not,and,ior,xor")
1129 2240204 : (match_test "ix86_ternlog_operand_p (op)")))
1130 240927 :
1131 64608890 : ;; True if OP is acceptable as operand of DImode shift expander.
1132 : (define_predicate "shiftdi_operand"
1133 1282295 : (if_then_else (match_test "TARGET_64BIT")
1134 3522499 : (match_operand 0 "nonimmediate_operand")
1135 2240204 : (match_operand 0 "register_operand")))
1136 1282295 :
1137 2856551 : (define_predicate "ashldi_input_operand"
1138 616347 : (if_then_else (match_test "TARGET_64BIT")
1139 616347 : (match_operand 0 "nonimmediate_operand")
1140 : (match_operand 0 "reg_or_pm1_operand")))
1141 2240204 :
1142 560737 : ;; Return true if OP is a vector load from the constant pool with just
1143 : ;; the first element nonzero.
1144 : (define_predicate "zero_extended_scalar_load_operand"
1145 : (match_code "mem")
1146 : {
1147 560737 : unsigned n_elts;
1148 560737 : op = avoid_constant_pool_reference (op);
1149 :
1150 560737 : if (!CONST_VECTOR_P (op))
1151 : return false;
1152 :
1153 77209 : n_elts = CONST_VECTOR_NUNITS (op);
1154 :
1155 162011 : for (n_elts--; n_elts > 0; n_elts--)
1156 : {
1157 116723 : rtx elt = CONST_VECTOR_ELT (op, n_elts);
1158 233446 : if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
1159 : return false;
1160 : }
1161 : return true;
1162 : })
1163 :
1164 : /* Return true if operand is a float vector constant that is all ones. */
1165 1880080 : (define_predicate "float_vector_all_ones_operand"
1166 : (match_code "const_vector,mem")
1167 560737 : {
1168 1925368 : mode = GET_MODE (op);
1169 45288 : if (!FLOAT_MODE_P (mode)
1170 13395840 : || (MEM_P (op)
1171 11646964 : && (!SYMBOL_REF_P (XEXP (op, 0))
1172 1321892 : || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))))
1173 16426151 : return false;
1174 :
1175 2831247 : if (MEM_P (op))
1176 : {
1177 1082371 : op = get_pool_constant (XEXP (op, 0));
1178 1082371 : if (!CONST_VECTOR_P (op))
1179 : return false;
1180 :
1181 1082367 : if (GET_MODE (op) != mode
1182 5850 : && INTEGRAL_MODE_P (GET_MODE (op))
1183 5850 : && op == CONSTM1_RTX (GET_MODE (op)))
1184 : return true;
1185 : }
1186 :
1187 2831243 : rtx first = XVECEXP (op, 0, 0);
1188 8277296 : for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++)
1189 : {
1190 3638895 : rtx tmp = XVECEXP (op, 0, i);
1191 3638895 : if (!rtx_equal_p (tmp, first))
1192 : return false;
1193 : }
1194 499753 : if (GET_MODE (first) == E_SFmode)
1195 : {
1196 233046 : long l;
1197 233046 : REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1198 233046 : return (l & 0xffffffff) == 0xffffffff;
1199 : }
1200 266707 : else if (GET_MODE (first) == E_DFmode)
1201 : {
1202 260013 : long l[2];
1203 260013 : REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1204 260013 : return ((l[0] & 0xffffffff) == 0xffffffff
1205 260013 : && (l[1] & 0xffffffff) == 0xffffffff);
1206 : }
1207 : else
1208 : return false;
1209 : })
1210 :
1211 : /* Return true if operand is an integral vector constant that is all ones. */
1212 54538687 : (define_predicate "vector_all_ones_operand"
1213 : (and (match_code "const_vector")
1214 67331563 : (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1215 11108307 : (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1216 858468 :
1217 16426151 : /* Return true if operand is a vector constant that is all ones. */
1218 16426151 : (define_predicate "int_float_vector_all_ones_operand"
1219 : (ior (match_operand 0 "vector_all_ones_operand")
1220 9006121 : (match_operand 0 "float_vector_all_ones_operand")
1221 0 : (match_test "op == constm1_rtx")))
1222 9006121 :
1223 16426151 : /* Return true if operand is an 128/256bit all ones vector
1224 3177 : that zero-extends to 256/512bit. */
1225 : (define_predicate "vector_all_ones_zero_extend_half_operand"
1226 11495111 : (match_code "const_vector")
1227 : {
1228 162397499 : mode = GET_MODE (op);
1229 11495111 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1230 172404927 : || (GET_MODE_SIZE (mode) != 32
1231 9708685 : && GET_MODE_SIZE (mode) != 64))
1232 : return false;
1233 :
1234 464488 : int nelts = CONST_VECTOR_NUNITS (op);
1235 536707 : for (int i = 0; i != nelts; i++)
1236 : {
1237 535757 : rtx elt = CONST_VECTOR_ELT (op, i);
1238 535757 : if (i < nelts / 2
1239 1052899 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1240 : return false;
1241 83231 : if (i >= nelts / 2
1242 101846 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1243 : return false;
1244 : }
1245 : return true;
1246 : })
1247 :
1248 : /* Return true if operand is an 128bit all ones vector
1249 164135049 : that zero extends to 512bit. */
1250 : (define_predicate "vector_all_ones_zero_extend_quarter_operand"
1251 11495111 : (match_code "const_vector")
1252 164135999 : {
1253 950 : mode = GET_MODE (op);
1254 11494161 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1255 10006478 : || GET_MODE_SIZE (mode) != 64)
1256 : return false;
1257 11494161 :
1258 165536 : int nelts = CONST_VECTOR_NUNITS (op);
1259 179087 : for (int i = 0; i != nelts; i++)
1260 : {
1261 178999 : rtx elt = CONST_VECTOR_ELT (op, i);
1262 178999 : if (i < nelts / 4
1263 354538 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1264 : return false;
1265 16177 : if (i >= nelts / 4
1266 19637 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1267 : return false;
1268 : }
1269 : return true;
1270 : })
1271 :
1272 : ; Return true when OP is operand acceptable for vector memory operand.
1273 164134099 : ; Only AVX can have misaligned memory operand.
1274 : (define_predicate "vector_memory_operand"
1275 11494161 : (and (match_operand 0 "memory_operand")
1276 165349095 : (ior (match_test "TARGET_AVX")
1277 1214996 : (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1278 :
1279 : ; Return true when OP is register_operand or vector_memory_operand.
1280 : (define_predicate "vector_operand"
1281 18844925 : (ior (match_operand 0 "register_operand")
1282 : (match_operand 0 "vector_memory_operand")))
1283 18844925 :
1284 : ; Return true when OP is register_operand, vector_memory_operand
1285 : ; or const_vector.
1286 : (define_predicate "vector_or_const_vector_operand"
1287 15178 : (ior (match_operand 0 "register_operand")
1288 : (match_operand 0 "vector_memory_operand")
1289 15178 : (match_code "const_vector")))
1290 8936 :
1291 : ; Return true when OP is register_operand, vector_memory_operand,
1292 : ; const_vector zero or const_vector all ones.
1293 : (define_predicate "vector_or_0_or_1s_operand"
1294 4604 : (ior (match_operand 0 "register_operand")
1295 : (match_operand 0 "vector_memory_operand")
1296 4604 : (match_operand 0 "const0_operand")
1297 : (match_operand 0 "int_float_vector_all_ones_operand")))
1298 :
1299 : (define_predicate "bcst_mem_operand"
1300 160808904 : (and (match_code "vec_duplicate")
1301 14316 : (and (match_test "TARGET_AVX512F")
1302 94197 : (ior (match_test "TARGET_AVX512VL")
1303 8906 : (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64")))
1304 53885 : (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))")
1305 13430 : (match_test "GET_MODE (XEXP (op, 0))
1306 40274 : == GET_MODE_INNER (GET_MODE (op))")
1307 160827633 : (match_test "memory_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
1308 5315 :
1309 : ; Return true when OP is bcst_mem_operand or vector_memory_operand.
1310 : (define_predicate "bcst_vector_operand"
1311 : (ior (match_operand 0 "vector_operand")
1312 5105095 : (match_operand 0 "bcst_mem_operand")))
1313 :
1314 5105095 : ;; Return true when OP is either nonimmediate operand, or any
1315 : ;; CONST_VECTOR.
1316 : (define_predicate "nonimmediate_or_const_vector_operand"
1317 : (ior (match_operand 0 "nonimmediate_operand")
1318 85230 : (match_code "const_vector")))
1319 :
1320 85230 : (define_predicate "nonimmediate_or_const_vec_dup_operand"
1321 12566 : (ior (match_operand 0 "nonimmediate_operand")
1322 58 : (match_test "const_vec_duplicate_p (op)")))
1323 58 :
1324 : ;; Return true when OP is either register operand, or any
1325 106 : ;; CONST_VECTOR.
1326 : (define_predicate "reg_or_const_vector_operand"
1327 106 : (ior (match_operand 0 "register_operand")
1328 : (match_code "const_vector")))
1329 246 :
1330 153 : ;; Return true when OP is CONST_VECTOR which can be converted to a
1331 : ;; sign extended 32-bit integer.
1332 : (define_predicate "x86_64_const_vector_operand"
1333 : (match_code "const_vector")
1334 158604 : {
1335 158604 : if (mode == VOIDmode)
1336 0 : mode = GET_MODE (op);
1337 158604 : else if (GET_MODE (op) != mode)
1338 : return false;
1339 373622 : if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1340 : return false;
1341 115624 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op, mode);
1342 115624 : return trunc_int_for_mode (val, SImode) == val;
1343 : })
1344 :
1345 : (define_predicate "nonimmediate_or_x86_64_const_vector_operand"
1346 959978 : (ior (match_operand 0 "nonimmediate_operand")
1347 : (match_operand 0 "x86_64_const_vector_operand")))
1348 158604 :
1349 1043089 : ;; Return true when OP is nonimmediate or standard SSE constant.
1350 83111 : (define_predicate "nonimmediate_or_sse_const_operand"
1351 : (ior (match_operand 0 "nonimmediate_operand")
1352 23679314 : (match_test "standard_sse_constant_p (op, mode)")))
1353 2619021 :
1354 5388 : ;; Return true if OP is a register or a zero.
1355 : (define_predicate "reg_or_0_operand"
1356 5388 : (ior (match_operand 0 "register_operand")
1357 583591 : (match_operand 0 "const0_operand")))
1358 :
1359 583591 : ; Return true when OP is a nonimmediate or zero.
1360 98064031 : (define_predicate "nonimm_or_0_operand"
1361 : (ior (match_operand 0 "nonimmediate_operand")
1362 119124324 : (match_operand 0 "const0_operand")))
1363 124213513 :
1364 : ; Return true when OP is a nonimmediate or zero or all ones.
1365 124213513 : (define_predicate "nonimm_or_0_or_1s_operand"
1366 : (ior (match_operand 0 "nonimmediate_operand")
1367 : (match_operand 0 "const0_operand")
1368 : (match_operand 0 "int_float_vector_all_ones_operand")))
1369 97092 :
1370 : ;; Return true for RTX codes that force SImode address.
1371 97092 : (define_predicate "SImode_address_operand"
1372 : (match_code "subreg,zero_extend,and"))
1373 :
1374 : ;; Return true if op is a valid address for LEA, and does not contain
1375 264725973 : ;; a segment override. Defined as a special predicate to allow
1376 : ;; mode-less const_int operands pass to address_operand.
1377 264725973 : (define_special_predicate "address_no_seg_operand"
1378 173449531 : (match_test "address_operand (op, VOIDmode)")
1379 63137981 : {
1380 63567793 : struct ix86_address parts;
1381 63567793 : int ok;
1382 429812 :
1383 63177391 : if (!CONST_INT_P (op)
1384 60323066 : && mode != VOIDmode
1385 60323066 : && GET_MODE (op) != mode)
1386 429812 : return false;
1387 429812 :
1388 63137917 : ok = ix86_decompose_address (op, &parts);
1389 63137917 : gcc_assert (ok);
1390 63137917 : return parts.seg == ADDR_SPACE_GENERIC;
1391 63137981 : })
1392 :
1393 : ;; Return true if op if a valid base register, displacement or
1394 110311550 : ;; sum of base register and displacement for VSIB addressing.
1395 : (define_predicate "vsib_address_operand"
1396 110350960 : (match_test "address_operand (op, VOIDmode)")
1397 79581 : {
1398 38232 : struct ix86_address parts;
1399 39410 : int ok;
1400 39410 : rtx disp;
1401 :
1402 39410 : ok = ix86_decompose_address (op, &parts);
1403 39410 : gcc_assert (ok);
1404 66028 : if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1405 26618 : return false;
1406 :
1407 : /* VSIB addressing doesn't support (%rip). */
1408 39390 : if (parts.disp)
1409 27383454 : {
1410 7342 : disp = parts.disp;
1411 7342 : if (GET_CODE (disp) == CONST)
1412 : {
1413 148 : disp = XEXP (disp, 0);
1414 148 : if (GET_CODE (disp) == PLUS)
1415 148 : disp = XEXP (disp, 0);
1416 148 : if (GET_CODE (disp) == UNSPEC)
1417 0 : switch (XINT (disp, 1))
1418 : {
1419 : case UNSPEC_GOTPCREL:
1420 : case UNSPEC_PCREL:
1421 : case UNSPEC_GOTNTPOFF:
1422 : return false;
1423 : }
1424 : }
1425 7342 : if (TARGET_64BIT
1426 7342 : && flag_pic
1427 0 : && (SYMBOL_REF_P (disp)
1428 0 : || LABEL_REF_P (disp)))
1429 0 : return false;
1430 : }
1431 :
1432 : return true;
1433 : })
1434 :
1435 : (define_predicate "vsib_mem_operator"
1436 40191 : (match_code "mem"))
1437 :
1438 40191 : ;; Return true if the rtx is known to be at least 32 bits aligned.
1439 : (define_predicate "aligned_operand"
1440 : (match_operand 0 "general_operand")
1441 : {
1442 27383454 : struct ix86_address parts;
1443 27383454 : int ok;
1444 :
1445 : /* Registers and immediate operands are always "aligned". */
1446 27383454 : if (!MEM_P (op))
1447 : return true;
1448 :
1449 : /* All patterns using aligned_operand on memory operands ends up
1450 : in promoting memory operand to 64bit and thus causing memory mismatch. */
1451 7490942 : if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1452 : return false;
1453 :
1454 : /* Don't even try to do any aligned optimizations with volatiles. */
1455 130759 : if (MEM_VOLATILE_P (op))
1456 : return false;
1457 :
1458 132506 : if (MEM_ALIGN (op) >= 32)
1459 : return true;
1460 :
1461 53711 : op = XEXP (op, 0);
1462 :
1463 : /* Pushes and pops are only valid on the stack pointer. */
1464 53711 : if (GET_CODE (op) == PRE_DEC
1465 53711 : || GET_CODE (op) == POST_INC)
1466 : return true;
1467 :
1468 : /* Decode the address. */
1469 53711 : ok = ix86_decompose_address (op, &parts);
1470 53711 : gcc_assert (ok);
1471 :
1472 53711 : if (parts.base && SUBREG_P (parts.base))
1473 0 : parts.base = SUBREG_REG (parts.base);
1474 53711 : if (parts.index && SUBREG_P (parts.index))
1475 0 : parts.index = SUBREG_REG (parts.index);
1476 :
1477 : /* Look for some component that isn't known to be aligned. */
1478 53711 : if (parts.index)
1479 : {
1480 7331 : if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1481 : return false;
1482 : }
1483 46380 : if (parts.base)
1484 : {
1485 38734 : if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1486 : return false;
1487 : }
1488 13991 : if (parts.disp)
1489 : {
1490 13991 : if (!CONST_INT_P (parts.disp)
1491 6456 : || (INTVAL (parts.disp) & 3))
1492 : return false;
1493 : }
1494 :
1495 : /* Didn't find one -- this must be an aligned address. */
1496 : return true;
1497 : })
1498 :
1499 : ;; Return true if OP is memory operand with a displacement.
1500 27939215 : (define_predicate "memory_displacement_operand"
1501 : (match_operand 0 "memory_operand")
1502 55322669 : {
1503 27383454 : struct ix86_address parts;
1504 0 : int ok;
1505 :
1506 0 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1507 0 : gcc_assert (ok);
1508 0 : return parts.disp != NULL_RTX;
1509 : })
1510 :
1511 : ;; Return true if OP is memory operand with a displacement only.
1512 0 : (define_predicate "memory_displacement_only_operand"
1513 : (match_operand 0 "memory_operand")
1514 0 : {
1515 0 : struct ix86_address parts;
1516 38523461 : int ok;
1517 :
1518 38523461 : if (TARGET_64BIT)
1519 38523461 : return false;
1520 :
1521 18899614 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1522 18899614 : gcc_assert (ok);
1523 :
1524 18899614 : if (parts.base || parts.index)
1525 : return false;
1526 :
1527 235325 : return parts.disp != NULL_RTX;
1528 : })
1529 :
1530 : ;; Return true if OP is memory operand that cannot be represented
1531 59605666 : ;; by the modRM array.
1532 : (define_predicate "long_memory_operand"
1533 98129127 : (and (match_operand 0 "memory_operand")
1534 38523461 : (match_test "memory_address_length (op, false)")))
1535 :
1536 : ;; Return true if OP is a comparison operator that can be issued by fcmov.
1537 : (define_predicate "fcmov_comparison_operator"
1538 84070 : (match_operand 0 "comparison_operator")
1539 : {
1540 0 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1541 84070 : enum rtx_code code = GET_CODE (op);
1542 :
1543 84070 : if (inmode == CCFPmode)
1544 8546 : code = ix86_fp_compare_code_to_integer (code);
1545 :
1546 : /* i387 supports just limited amount of conditional codes. */
1547 84070 : switch (code)
1548 : {
1549 1939 : case GEU: case LTU:
1550 1939 : if (inmode == CCCmode || inmode == CCGZmode)
1551 : return true;
1552 : /* FALLTHRU */
1553 6545 : case GTU: case LEU:
1554 6545 : if (inmode == CCmode || inmode == CCFPmode)
1555 : return true;
1556 : return false;
1557 : case ORDERED: case UNORDERED:
1558 : case EQ: case NE:
1559 : return true;
1560 : default:
1561 : return false;
1562 : }
1563 : })
1564 :
1565 : ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1566 84070 : ;; The first set are supported directly; the second set can't be done with
1567 : ;; full IEEE support, i.e. NaNs.
1568 168140 :
1569 84070 : (define_predicate "sse_comparison_operator"
1570 : (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1571 133217 : (and (match_test "TARGET_AVX")
1572 133217 : (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1573 134922 :
1574 : (define_predicate "ix86_comparison_int_operator"
1575 134922 : (match_code "ne,eq,ge,gt,le,lt"))
1576 219566 :
1577 : (define_predicate "ix86_comparison_uns_operator"
1578 219566 : (match_code "ne,eq,geu,gtu,leu,ltu"))
1579 :
1580 219566 : (define_predicate "bt_comparison_operator"
1581 219566 : (match_code "ne,eq"))
1582 219566 :
1583 219566 : (define_predicate "shr_comparison_operator"
1584 219566 : (match_code "gtu,leu"))
1585 219566 :
1586 219566 : (define_predicate "add_comparison_operator"
1587 : (match_code "geu,ltu"))
1588 :
1589 : (define_predicate "ieee_maxmin_comparison_operator"
1590 219566 : (match_code "lt,gt"))
1591 219566 :
1592 : ;; Return true if OP is a valid comparison operator in valid mode.
1593 : (define_predicate "ix86_comparison_operator"
1594 : (match_operand 0 "comparison_operator")
1595 123063 : {
1596 98879424 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1597 123063 : enum rtx_code code = GET_CODE (op);
1598 :
1599 99002487 : if (inmode == CCFPmode)
1600 6802310 : return ix86_trivial_fp_comparison_operator (op, mode);
1601 123063 :
1602 92077114 : switch (code)
1603 123063 : {
1604 70742693 : case EQ: case NE:
1605 70619630 : if (inmode == CCGZmode)
1606 0 : return false;
1607 : return true;
1608 4395346 : case GE: case LT:
1609 4395346 : if (inmode == CCmode || inmode == CCGCmode
1610 2361126 : || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode)
1611 3879787 : return true;
1612 : return false;
1613 7696661 : case GEU: case LTU:
1614 7696661 : if (inmode == CCCmode || inmode == CCGZmode)
1615 : return true;
1616 61167394 : /* FALLTHRU */
1617 10673102 : case GTU: case LEU:
1618 10673102 : if (inmode == CCmode)
1619 9460962 : return true;
1620 50474611 : return false;
1621 3456 : case ORDERED: case UNORDERED:
1622 3456 : if (inmode == CCmode)
1623 3203 : return true;
1624 50474611 : return false;
1625 50474611 : case GT: case LE:
1626 5926969 : if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1627 5192890 : return true;
1628 : return false;
1629 757700 : default:
1630 : return false;
1631 757700 : }
1632 : })
1633 757700 :
1634 757700 : ;; Return true if OP is a valid comparison operator
1635 113974743 : ;; testing carry flag to be set.
1636 : (define_predicate "ix86_carry_flag_operator"
1637 212096467 : (match_code "ltu,unlt")
1638 98879424 : {
1639 1582681 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1640 757700 : enum rtx_code code = GET_CODE (op);
1641 :
1642 824981 : if (inmode == CCFPmode)
1643 8473 : code = ix86_fp_compare_code_to_integer (code);
1644 816508 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1645 : return false;
1646 1347818 :
1647 621521 : return code == LTU;
1648 1347818 : })
1649 1347818 :
1650 1347818 : ;; Return true if OP is a valid comparison operator
1651 4094191 : ;; testing carry flag to be unset.
1652 : (define_predicate "ix86_carry_flag_unset_operator"
1653 4094191 : (match_code "geu,ge")
1654 1347818 : {
1655 1347818 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1656 826628 : enum rtx_code code = GET_CODE (op);
1657 824981 :
1658 1647 : if (inmode == CCFPmode)
1659 68 : code = ix86_fp_compare_code_to_integer (code);
1660 1579 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1661 918 : return false;
1662 824981 :
1663 428095 : return code == GEU;
1664 918 : })
1665 918 :
1666 : ;; Return true if this comparison only requires testing one flag bit.
1667 3019805 : ;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
1668 : (define_predicate "ix86_trivial_fp_comparison_operator"
1669 12269128 : (if_then_else (match_test "TARGET_AVX10_2")
1670 657598 : (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
1671 1647 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
1672 1647 :
1673 1647 : (define_predicate "ix86_trivial_fp_comparison_operator_xf"
1674 100236305 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1675 :
1676 1356881 : ;; Return true if we know how to do this comparison. Others require
1677 1647 : ;; testing more than one flag bit, and we let the generic middle-end
1678 410606 : ;; code do that.
1679 410172 : (define_predicate "ix86_fp_comparison_operator"
1680 2857619 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1681 2857619 : == IX86_FPCMP_ARITH")
1682 408959 : (match_operand 0 "comparison_operator")
1683 9659929 : (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1684 408959 :
1685 9659929 : (define_predicate "ix86_fp_comparison_operator_xf"
1686 1765840 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1687 1356881 : == IX86_FPCMP_ARITH")
1688 : (match_operand 0 "comparison_operator")
1689 : (match_operand 0 "ix86_trivial_fp_comparison_operator_xf")))
1690 408959 :
1691 830016 : ;; Return true if we can perform this comparison on TImode operands.
1692 : (define_predicate "ix86_timode_comparison_operator"
1693 421057 : (if_then_else (match_test "TARGET_64BIT")
1694 : (match_operand 0 "ordered_comparison_operator")
1695 2448660 : (match_operand 0 "bt_comparison_operator")))
1696 :
1697 2448660 : ;; Return true if this is a valid second operand for a TImode comparison.
1698 : (define_predicate "ix86_timode_comparison_operand"
1699 150536 : (if_then_else (match_test "TARGET_64BIT")
1700 : (match_operand 0 "x86_64_general_operand")
1701 : (match_operand 0 "nonimmediate_operand")))
1702 :
1703 1975142 : ;; Nearly general operand, but accept any const_double, since we wish
1704 : ;; to be able to drop them into memory rather than have them get pulled
1705 511593 : ;; into registers.
1706 2486735 : (define_predicate "cmp_fp_expander_operand"
1707 : (ior (match_code "const_double")
1708 : (match_operand 0 "general_operand")))
1709 :
1710 4894752 : ;; Return true if this is a valid binary floating-point operation.
1711 : (define_predicate "binary_fp_operator"
1712 4894752 : (match_code "plus,minus,mult,div"))
1713 :
1714 4887324 : ;; Return true if this is a multiply operation.
1715 4887324 : (define_predicate "mult_operator"
1716 4887324 : (match_code "mult"))
1717 4887324 :
1718 4887324 : ;; Return true if this is a division operation.
1719 : (define_predicate "div_operator"
1720 : (match_code "div"))
1721 :
1722 4887324 : ;; Return true if this is an and, ior or xor operation.
1723 4887324 : (define_predicate "logic_operator"
1724 : (match_code "and,ior,xor"))
1725 :
1726 : ;; Return true if this is an and operation.
1727 17009973 : (define_predicate "and_operator"
1728 : (match_code "and"))
1729 17009973 :
1730 3453770 : ;; Return true if this is a plus, minus, and, ior or xor operation.
1731 : (define_predicate "plusminuslogic_operator"
1732 : (match_code "plus,minus,and,ior,xor"))
1733 :
1734 2622855 : ;; Return true for ARITHMETIC_P.
1735 : (define_predicate "arith_or_logical_operator"
1736 2622855 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1737 915216 : mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1738 :
1739 : ;; Return true for COMMUTATIVE_P.
1740 : (define_predicate "commutative_operator"
1741 0 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1742 :
1743 0 : ;; Return true if OP is a binary operator that can be promoted to wider mode.
1744 : (define_predicate "promotable_binary_operator"
1745 0 : (ior (match_code "plus,minus,and,ior,xor,ashift")
1746 0 : (and (match_code "mult")
1747 24915375 : (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1748 0 :
1749 : (define_predicate "compare_operator"
1750 : (match_code "compare"))
1751 :
1752 7656014 : (define_predicate "extract_high_operator"
1753 0 : (match_code "zero_extract,sign_extract,ashiftrt,lshiftrt")
1754 7656014 : {
1755 0 : return (const8_operand (XEXP (op, 1), VOIDmode)
1756 152689 : && (BINARY_P (op) || const8_operand (XEXP (op, 2), VOIDmode)));
1757 100 : })
1758 :
1759 152789 : ;; Return true if OP is a memory operand, aligned to
1760 0 : ;; less than its natural alignment.
1761 : (define_predicate "misaligned_operand"
1762 152689 : (and (match_code "mem")
1763 6507683 : (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1764 1722745 :
1765 152689 : ;; Return true if OP is a parallel for an mov{d,q,dqa,ps,pd} vec_select,
1766 497556 : ;; where one of the two operands of the vec_concat is const0_operand.
1767 152689 : (define_predicate "movq_parallel"
1768 1903959 : (match_code "parallel")
1769 493583 : {
1770 1751270 : unsigned nelt = XVECLEN (op, 0);
1771 1751270 : unsigned nelt2 = nelt >> 1;
1772 1903959 : unsigned i;
1773 152689 :
1774 1315822 : if (nelt < 2)
1775 : return false;
1776 :
1777 493583 : /* Validate that all of the elements are constants,
1778 493583 : lower halves of permute are lower halves of the first operand,
1779 : upper halves of permute come from any of the second operand. */
1780 15480694 : for (i = 0; i < nelt; ++i)
1781 : {
1782 6232481 : rtx er = XVECEXP (op, 0, i);
1783 2031790 : unsigned HOST_WIDE_INT ei;
1784 4200691 :
1785 2031790 : if (!CONST_INT_P (er))
1786 4200691 : return false;
1787 6232481 : ei = INTVAL (er);
1788 2031790 : if (i < nelt2 && ei != i)
1789 4200691 : return false;
1790 873452 : if (i >= nelt2 && (ei < nelt || ei >= nelt << 1))
1791 4200691 : return false;
1792 4200691 : }
1793 4200691 :
1794 4200691 : return true;
1795 4200691 : })
1796 4200691 :
1797 4200691 : ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1798 5458378 : (define_predicate "vzeroall_operation"
1799 4200691 : (match_code "parallel")
1800 6716065 : {
1801 1257706 : unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1802 0 :
1803 4351 : if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1804 4200691 : return false;
1805 4200691 :
1806 78166 : for (i = 0; i < nregs; i++)
1807 : {
1808 69464 : rtx elt = XVECEXP (op, 0, i+1);
1809 :
1810 4270155 : if (GET_CODE (elt) != SET
1811 4270155 : || GET_CODE (SET_DEST (elt)) != REG
1812 69464 : || GET_MODE (SET_DEST (elt)) != V8SImode
1813 69464 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
1814 138928 : || SET_SRC (elt) != CONST0_RTX (V8SImode))
1815 920012 : return false;
1816 : }
1817 920012 : return true;
1818 : })
1819 322547 :
1820 322547 : ;; return true if OP is a vzeroall pattern.
1821 326898 : (define_predicate "vzeroall_pattern"
1822 322547 : (and (match_code "parallel")
1823 331249 : (match_code "unspec_volatile" "a")
1824 4477 : (match_test "XINT (XVECEXP (op, 0, 0), 1) == UNSPECV_VZEROALL")))
1825 0 :
1826 322547 : ;; return true if OP is a vzeroupper pattern.
1827 322547 : (define_predicate "vzeroupper_pattern"
1828 322547 : (and (match_code "parallel")
1829 251967307 : (match_code "unspec" "b")
1830 964384 : (match_test "XINT (XVECEXP (op, 0, 1), 1) == UNSPEC_CALLEE_ABI")
1831 251967307 : (match_test "INTVAL (XVECEXP (XVECEXP (op, 0, 1), 0, 0)) == ABI_VZEROUPPER")))
1832 0 :
1833 322547 : ;; Return true if OP is an addsub vec_merge operation
1834 : (define_predicate "addsub_vm_operator"
1835 : (match_code "vec_merge")
1836 8250 : {
1837 24923625 : rtx op0, op1;
1838 8250 : int swapped;
1839 24915375 : HOST_WIDE_INT mask;
1840 8250 : int nunits, elt;
1841 :
1842 8250 : op0 = XEXP (op, 0);
1843 8250 : op1 = XEXP (op, 1);
1844 :
1845 : /* Sanity check. */
1846 8250 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1847 : swapped = 0;
1848 4198 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1849 : swapped = 1;
1850 : else
1851 0 : gcc_unreachable ();
1852 :
1853 8250 : mask = INTVAL (XEXP (op, 2));
1854 8250 : nunits = GET_MODE_NUNITS (mode);
1855 :
1856 32314 : for (elt = 0; elt < nunits; elt++)
1857 : {
1858 : /* bit clear: take from op0, set: take from op1 */
1859 24316 : int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1860 :
1861 24316 : if (bit != ((elt & 1) ^ swapped))
1862 : return false;
1863 : }
1864 :
1865 : return true;
1866 : })
1867 :
1868 : ;; Return true if OP is an addsub vec_select/vec_concat operation
1869 8250 : (define_predicate "addsub_vs_operator"
1870 : (and (match_code "vec_select")
1871 8250 : (match_code "vec_concat" "0"))
1872 16248 : {
1873 7998 : rtx op0, op1;
1874 0 : bool swapped;
1875 0 : int nunits, elt;
1876 :
1877 0 : op0 = XEXP (XEXP (op, 0), 0);
1878 0 : op1 = XEXP (XEXP (op, 0), 1);
1879 :
1880 : /* Sanity check. */
1881 0 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1882 : swapped = false;
1883 0 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1884 : swapped = true;
1885 : else
1886 0 : gcc_unreachable ();
1887 :
1888 0 : nunits = GET_MODE_NUNITS (mode);
1889 0 : if (XVECLEN (XEXP (op, 1), 0) != nunits)
1890 : return false;
1891 :
1892 : /* We already checked that permutation is suitable for addsub,
1893 : so only look at the first element of the parallel. */
1894 0 : elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1895 :
1896 0 : return elt == (swapped ? nunits : 0);
1897 : })
1898 :
1899 : ;; Return true if OP is a parallel for an addsub vec_select.
1900 0 : (define_predicate "addsub_vs_parallel"
1901 : (and (match_code "parallel")
1902 0 : (match_code "const_int" "a"))
1903 0 : {
1904 0 : int nelt = XVECLEN (op, 0);
1905 474 : int elt, i;
1906 :
1907 474 : if (nelt < 2)
1908 474 : return false;
1909 :
1910 : /* Check that the permutation is suitable for addsub.
1911 : For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1912 474 : elt = INTVAL (XVECEXP (op, 0, 0));
1913 474 : if (elt == 0)
1914 : {
1915 442 : for (i = 1; i < nelt; ++i)
1916 434 : if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1917 : return false;
1918 : }
1919 40 : else if (elt == nelt)
1920 : {
1921 0 : for (i = 1; i < nelt; ++i)
1922 0 : if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1923 : return false;
1924 : }
1925 : else
1926 : return false;
1927 :
1928 : return true;
1929 : })
1930 :
1931 : ;; Return true if OP is a constant pool in perm{w,d,b} which constains index
1932 474 : ;; match pmov{dw,wb,qd}.
1933 : (define_predicate "permvar_truncate_operand"
1934 474 : (match_code "mem")
1935 948 : {
1936 0 : int nelt = GET_MODE_NUNITS (mode);
1937 16 : int perm[128];
1938 16 : int id;
1939 :
1940 32 : if (!INTEGRAL_MODE_P (mode) || !VECTOR_MODE_P (mode))
1941 : return false;
1942 :
1943 16 : if (nelt < 2)
1944 : return false;
1945 :
1946 16 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1947 : return false;
1948 :
1949 16 : id = exact_log2 (nelt);
1950 :
1951 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
1952 : For example V16HImode to V8HImode
1953 : { 0 2 4 6 8 10 12 14 * * * * * * * * }. */
1954 232 : for (int i = 0; i != nelt / 2; i++)
1955 216 : if ((perm[i] & ((1 << id) - 1)) != i * 2)
1956 : return false;
1957 :
1958 : return true;
1959 : })
1960 :
1961 : ;; Return true if OP is a constant pool in shufb which constains index
1962 49 : ;; match pmovdw.
1963 : (define_predicate "pshufb_truncv4siv4hi_operand"
1964 16 : (match_code "mem")
1965 65 : {
1966 16 : int perm[128];
1967 :
1968 8 : if (mode != E_V16QImode)
1969 : return false;
1970 8 :
1971 8 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1972 : return false;
1973 :
1974 : /* Check that the permutation is suitable for pmovdw.
1975 : For example V4SImode to V4HImode
1976 : { 0 1 4 5 8 9 12 13 * * * * * * * * }.
1977 : index = i % 2 + (i / 2) * 4. */
1978 58 : for (int i = 0; i != 8; i++)
1979 : {
1980 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
1981 52 : if (perm[i] & 128)
1982 : return false;
1983 :
1984 52 : if ((perm[i] & 15) != ((i & 1) + (i & 0xFE) * 2))
1985 : return false;
1986 : }
1987 :
1988 : return true;
1989 : })
1990 :
1991 : ;; Return true if OP is a constant pool in shufb which constains index
1992 11 : ;; match pmovdw.
1993 : (define_predicate "pshufb_truncv8hiv8qi_operand"
1994 8 : (match_code "mem")
1995 17 : {
1996 6 : int perm[128];
1997 :
1998 11 : if (mode != E_V16QImode)
1999 : return false;
2000 11 :
2001 11 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
2002 : return false;
2003 :
2004 : /* Check that the permutation is suitable for pmovwb.
2005 : For example V16QImode to V8QImode
2006 : { 0 2 4 6 8 10 12 14 * * * * * * * * }.
2007 : index = i % 2 + (i / 2) * 4. */
2008 57 : for (int i = 0; i != 8; i++)
2009 : {
2010 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
2011 52 : if (perm[i] & 128)
2012 : return false;
2013 :
2014 52 : if ((perm[i] & 15) != i * 2)
2015 : return false;
2016 : }
2017 :
2018 : return true;
2019 : })
2020 :
2021 : ;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select,
2022 14 : ;; where one of the two operands of the vec_concat is const0_operand.
2023 : (define_predicate "pmovzx_parallel"
2024 11 : (and (match_code "parallel")
2025 19 : (match_code "const_int" "a"))
2026 5 : {
2027 1326864 : int nelt = XVECLEN (op, 0);
2028 1326864 : int elt, i;
2029 :
2030 1326864 : if (nelt < 2)
2031 : return false;
2032 :
2033 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
2034 : For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */
2035 1326862 : elt = INTVAL (XVECEXP (op, 0, 0));
2036 1326862 : if (elt == 0)
2037 : {
2038 3062240 : for (i = 1; i < nelt; ++i)
2039 2629460 : if ((i & 1) != 0)
2040 : {
2041 1659767 : if (INTVAL (XVECEXP (op, 0, i)) < nelt)
2042 : return false;
2043 : }
2044 969693 : else if (INTVAL (XVECEXP (op, 0, i)) != i / 2)
2045 : return false;
2046 : }
2047 : else
2048 : return false;
2049 :
2050 : return true;
2051 : })
2052 :
2053 : ;; Return true if OP is a const vector with duplicate value.
2054 1326864 : (define_predicate "const_vector_duplicate_operand"
2055 : (match_code "const_vector")
2056 1326864 : {
2057 2653728 : rtx elt = XVECEXP (op, 0, 0);
2058 0 : int i, nelt = XVECLEN (op, 0);
2059 :
2060 96 : for (i = 1; i < nelt; ++i)
2061 93 : if (!rtx_equal_p (elt, XVECEXP (op, 0, i)))
2062 3 : return false;
2063 : return true;
2064 : })
2065 :
2066 : ;; Return true if OP is a parallel for a vbroadcast permute.
2067 3 : (define_predicate "avx_vbroadcast_operand"
2068 : (and (match_code "parallel")
2069 3 : (match_code "const_int" "a"))
2070 6 : {
2071 3 : rtx elt = XVECEXP (op, 0, 0);
2072 407796 : int i, nelt = XVECLEN (op, 0);
2073 :
2074 : /* Don't bother checking there are the right number of operands,
2075 407796 : merely that they're all identical. */
2076 503124 : for (i = 1; i < nelt; ++i)
2077 265108 : if (XVECEXP (op, 0, i) != elt)
2078 : return false;
2079 : return true;
2080 : })
2081 :
2082 : ;; Return true if OP is a parallel for a vbroadcastf128 permute.
2083 407796 : (define_predicate "avx_vbroadcast128_operand"
2084 : (and (match_code "parallel")
2085 407796 : (match_code "const_int" "a"))
2086 815592 : {
2087 0 : int i, nelt = XVECLEN (op, 0);
2088 1246842 : int half = nelt / 2;
2089 :
2090 1970232 : for (i = 0; i < nelt; ++i)
2091 1246842 : {
2092 1970089 : int index = INTVAL (XVECEXP (op, 0, i));
2093 1970089 : if ((i < half && index != i)
2094 822152 : || (i >= half && index != (i - half)))
2095 : return false;
2096 : }
2097 :
2098 : return true;
2099 : })
2100 :
2101 : ;; Return true if OP is a parallel for a palignr permute.
2102 1246842 : (define_predicate "palignr_operand"
2103 : (and (match_code "parallel")
2104 1246842 : (match_code "const_int" "a"))
2105 2493684 : {
2106 0 : int elt = INTVAL (XVECEXP (op, 0, 0));
2107 26855 : int i, nelt = XVECLEN (op, 0);
2108 :
2109 : /* Check that an order in the permutation is suitable for palignr.
2110 26855 : For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
2111 61564 : for (i = 1; i < nelt; ++i)
2112 57793 : if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
2113 : return false;
2114 : return true;
2115 : })
2116 :
2117 : ;; Return true if OP is a proper third operand to vpblendw256.
2118 26855 : (define_predicate "avx2_pblendw_operand"
2119 : (match_code "const_int")
2120 26855 : {
2121 53710 : HOST_WIDE_INT val = INTVAL (op);
2122 0 : HOST_WIDE_INT low = val & 0xff;
2123 7121 : return val == ((low << 8) | low);
2124 : })
2125 :
2126 7121 : ;; Return true if OP is vector_operand or CONST_VECTOR.
2127 7121 : (define_predicate "general_vector_operand"
2128 : (ior (match_operand 0 "vector_operand")
2129 7121 : (match_code "const_vector")))
2130 7121 :
2131 : ;; Return true if OP is either -1 constant or stored in register.
2132 : (define_predicate "register_or_constm1_operand"
2133 : (ior (match_operand 0 "register_operand")
2134 12718 : (and (match_code "const_int")
2135 0 : (match_test "op == constm1_rtx"))))
2136 12718 :
2137 2378 : ;; Return true if the vector ends with between 12 and 18 register saves using
2138 : ;; RAX as the base address.
2139 : (define_predicate "save_multiple"
2140 221359 : (match_code "parallel")
2141 1324 : {
2142 221359 : const unsigned len = XVECLEN (op, 0);
2143 1324 : unsigned i;
2144 :
2145 : /* Starting from end of vector, count register saves. */
2146 314192 : for (i = 0; i < len; ++i)
2147 : {
2148 314192 : rtx src, dest, addr;
2149 314192 : rtx e = XVECEXP (op, 0, len - 1 - i);
2150 :
2151 314192 : if (GET_CODE (e) != SET)
2152 : break;
2153 :
2154 307147 : src = SET_SRC (e);
2155 307147 : dest = SET_DEST (e);
2156 :
2157 307147 : if (!REG_P (src) || !MEM_P (dest))
2158 : break;
2159 :
2160 92833 : addr = XEXP (dest, 0);
2161 :
2162 : /* Good if dest address is in RAX. */
2163 92833 : if (REG_P (addr) && REGNO (addr) == AX_REG)
2164 4202 : continue;
2165 :
2166 : /* Good if dest address is offset of RAX. */
2167 177262 : if (GET_CODE (addr) == PLUS
2168 88631 : && REG_P (XEXP (addr, 0))
2169 177262 : && REGNO (XEXP (addr, 0)) == AX_REG)
2170 88631 : continue;
2171 :
2172 : break;
2173 : }
2174 221359 : return (i >= 12 && i <= 18);
2175 : })
2176 :
2177 :
2178 221359 : ;; Return true if the vector ends with between 12 and 18 register loads using
2179 : ;; RSI as the base address.
2180 442718 : (define_predicate "restore_multiple"
2181 221359 : (match_code "parallel")
2182 0 : {
2183 7375342 : const unsigned len = XVECLEN (op, 0);
2184 7375342 : unsigned i;
2185 :
2186 7375342 : /* Starting from end of vector, count register restores. */
2187 7481920 : for (i = 0; i < len; ++i)
2188 : {
2189 7481920 : rtx src, dest, addr;
2190 7481920 : rtx e = XVECEXP (op, 0, len - 1 - i);
2191 :
2192 7481920 : if (GET_CODE (e) != SET)
2193 : break;
2194 :
2195 4206236 : src = SET_SRC (e);
2196 4206236 : dest = SET_DEST (e);
2197 :
2198 4206236 : if (!MEM_P (src) || !REG_P (dest))
2199 : break;
2200 :
2201 1257907 : addr = XEXP (src, 0);
2202 :
2203 : /* Good if src address is in RSI. */
2204 1257907 : if (REG_P (addr) && REGNO (addr) == SI_REG)
2205 5137 : continue;
2206 :
2207 : /* Good if src address is offset of RSI. */
2208 1354211 : if (GET_CODE (addr) == PLUS
2209 839901 : && REG_P (XEXP (addr, 0))
2210 2011939 : && REGNO (XEXP (addr, 0)) == SI_REG)
2211 101441 : continue;
2212 :
2213 : break;
2214 : }
2215 7375342 : return (i >= 12 && i <= 18);
2216 : })
2217 :
2218 : ;; Keylocker specific predicates
2219 7375342 : (define_predicate "encodekey128_operation"
2220 : (match_code "parallel")
2221 14750684 : {
2222 7375342 : unsigned i;
2223 0 : rtx elt;
2224 :
2225 108 : if (XVECLEN (op, 0) != 8)
2226 : return false;
2227 108 :
2228 392 : for(i = 0; i < 3; i++)
2229 : {
2230 294 : elt = XVECEXP (op, 0, i + 1);
2231 294 : if (GET_CODE (elt) != SET
2232 294 : || GET_CODE (SET_DEST (elt)) != REG
2233 294 : || GET_MODE (SET_DEST (elt)) != V2DImode
2234 294 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2235 294 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2236 294 : || GET_MODE (SET_SRC (elt)) != V2DImode
2237 294 : || XVECLEN(SET_SRC (elt), 0) != 1
2238 588 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2239 : return false;
2240 : }
2241 :
2242 392 : for(i = 4; i < 7; i++)
2243 : {
2244 294 : elt = XVECEXP (op, 0, i);
2245 294 : if (GET_CODE (elt) != CLOBBER
2246 294 : || GET_MODE (elt) != VOIDmode
2247 294 : || GET_CODE (XEXP (elt, 0)) != REG
2248 294 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2249 588 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2250 : return false;
2251 : }
2252 :
2253 98 : elt = XVECEXP (op, 0, 7);
2254 98 : if (GET_CODE (elt) != CLOBBER
2255 98 : || GET_MODE (elt) != VOIDmode
2256 98 : || GET_CODE (XEXP (elt, 0)) != REG
2257 98 : || GET_MODE (XEXP (elt, 0)) != CCmode
2258 196 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2259 : return false;
2260 : return true;
2261 : })
2262 :
2263 : (define_predicate "encodekey256_operation"
2264 108 : (match_code "parallel")
2265 : {
2266 337 : unsigned i;
2267 108 : rtx elt;
2268 0 :
2269 121 : if (XVECLEN (op, 0) != 9)
2270 : return false;
2271 :
2272 121 : elt = SET_SRC (XVECEXP (op, 0, 0));
2273 112 : elt = XVECEXP (elt, 0, 2);
2274 112 : if (!REG_P (elt)
2275 112 : || REGNO(elt) != GET_SSE_REGNO (1))
2276 : return false;
2277 :
2278 560 : for(i = 0; i < 4; i++)
2279 : {
2280 448 : elt = XVECEXP (op, 0, i + 1);
2281 448 : if (GET_CODE (elt) != SET
2282 448 : || GET_CODE (SET_DEST (elt)) != REG
2283 448 : || GET_MODE (SET_DEST (elt)) != V2DImode
2284 448 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2285 448 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2286 448 : || GET_MODE (SET_SRC (elt)) != V2DImode
2287 448 : || XVECLEN(SET_SRC (elt), 0) != 1
2288 896 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2289 : return false;
2290 : }
2291 :
2292 448 : for(i = 4; i < 7; i++)
2293 : {
2294 336 : elt = XVECEXP (op, 0, i + 1);
2295 336 : if (GET_CODE (elt) != CLOBBER
2296 336 : || GET_MODE (elt) != VOIDmode
2297 336 : || GET_CODE (XEXP (elt, 0)) != REG
2298 336 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2299 672 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2300 : return false;
2301 : }
2302 :
2303 112 : elt = XVECEXP (op, 0, 8);
2304 112 : if (GET_CODE (elt) != CLOBBER
2305 112 : || GET_MODE (elt) != VOIDmode
2306 112 : || GET_CODE (XEXP (elt, 0)) != REG
2307 112 : || GET_MODE (XEXP (elt, 0)) != CCmode
2308 224 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2309 : return false;
2310 : return true;
2311 : })
2312 :
2313 :
2314 121 : (define_predicate "aeswidekl_operation"
2315 : (match_code "parallel")
2316 242 : {
2317 121 : unsigned i;
2318 0 : rtx elt;
2319 :
2320 5796 : for (i = 0; i < 8; i++)
2321 : {
2322 660 : elt = XVECEXP (op, 0, i + 1);
2323 5168 : if (GET_CODE (elt) != SET
2324 5168 : || GET_CODE (SET_DEST (elt)) != REG
2325 5168 : || GET_MODE (SET_DEST (elt)) != V2DImode
2326 5168 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2327 5168 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2328 5168 : || GET_MODE (SET_SRC (elt)) != V2DImode
2329 5168 : || XVECLEN (SET_SRC (elt), 0) != 1
2330 5168 : || !REG_P (XVECEXP (SET_SRC (elt), 0, 0))
2331 10304 : || REGNO (XVECEXP (SET_SRC (elt), 0, 0)) != GET_SSE_REGNO (i))
2332 : return false;
2333 : }
2334 : return true;
2335 : })
2336 :
2337 : ;; Return true if OP is a memory operand that can be also used in APX
2338 660 : ;; EVEX-encoded patterns (i.e. APX NDD/NF) with immediate operand. With
2339 : ;; non-default address space, segment register or address size prefix,
2340 1320 : ;; APX EVEX-encoded instruction length can exceed the 15 byte size limit.
2341 660 : (define_predicate "apx_evex_memory_operand"
2342 0 : (match_operand 0 "memory_operand")
2343 : {
2344 : /* OK if immediate operand size < 4 bytes. */
2345 1689 : if (GET_MODE_SIZE (mode) < 4)
2346 1689 : return true;
2347 :
2348 1530 : bool default_addr = ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (op));
2349 1698 : bool address_size_prefix = TARGET_X32 && Pmode == SImode;
2350 :
2351 1530 : struct ix86_address parts;
2352 1530 : int ok;
2353 :
2354 1530 : op = XEXP (op, 0);
2355 1530 : ok = ix86_decompose_address (op, &parts);
2356 1530 : gcc_assert (ok);
2357 :
2358 1530 : if (default_addr)
2359 : {
2360 : /* Default address space. */
2361 :
2362 : /* Not OK with address size prefix, index register and disp. */
2363 694 : if (address_size_prefix
2364 168 : && parts.index
2365 42 : && parts.disp
2366 42 : && parts.disp != const0_rtx)
2367 : return false;
2368 : }
2369 : else
2370 : {
2371 : /* Non-default address space. */
2372 :
2373 : /* Not OK without base register. */
2374 836 : if (!parts.base)
2375 : return false;
2376 :
2377 : /* Not OK with disp and address size prefix. */
2378 668 : if (address_size_prefix && parts.disp)
2379 : return false;
2380 : }
2381 :
2382 : return true;
2383 : })
2384 :
2385 : ;; Return true if OP is a memory operand which can be used in APX EVEX-encoded
2386 1900 : ;; ADD patterns (i.e. APX NDD/NF) for with register source operand.
2387 : ;; UNSPEC_GOTNTPOFF memory operand is allowed with APX EVEX-encoded ADD only if
2388 3589 : ;; R_X86_64_CODE_6_GOTTPOFF works.
2389 1689 : (define_predicate "apx_evex_add_memory_operand"
2390 : (match_operand 0 "memory_operand")
2391 : {
2392 : /* OK if "add %reg1, name@gottpoff(%rip), %reg2" or
2393 : "{nf} add name@gottpoff(%rip), %reg1" are supported. */
2394 : if (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF)
2395 : return true;
2396 :
2397 : op = XEXP (op, 0);
2398 :
2399 : /* Disallow APX EVEX-encoded ADD with UNSPEC_GOTNTPOFF. */
2400 : if (GET_CODE (op) == CONST
2401 : && GET_CODE (XEXP (op, 0)) == UNSPEC
2402 : && XINT (XEXP (op, 0), 1) == UNSPEC_GOTNTPOFF)
2403 : return false;
2404 :
2405 : return true;
2406 : })
2407 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2408 : /* (content generated from coverage data) */
2409 992 : /* BEGIN: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2410 : /* ... */
2411 992 : /* ... */
2412 992 : /* ... */
2413 : /* END: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2414 : /* ... */
2415 : /* ... */
2416 993384719 : /* BEGIN: function "_Z19lookup_constraint_1PKc" */
2417 : /* ... */
2418 993384719 : /* ... */
2419 : /* ... */
2420 : /* ... */
2421 : /* ... */
2422 0 : /* ... */
2423 0 : /* ... */
2424 0 : /* ... */
2425 0 : /* ... */
2426 0 : /* ... */
2427 0 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2428 590450434 : /* (content generated from coverage data) */
2429 590450434 : /* ... */
2430 : /* ... */
2431 : /* ... */
2432 7766378 : /* ... */
2433 : /* ... */
2434 133369865 : /* ... */
2435 : /* ... */
2436 143910 : /* ... */
2437 : /* ... */
2438 1632879 : /* ... */
2439 : /* ... */
2440 1381307 : /* ... */
2441 : /* ... */
2442 54930407 : /* ... */
2443 : /* ... */
2444 50133204 : /* ... */
2445 : /* ... */
2446 105135825 : /* ... */
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2448 39333145 : /* (content generated from coverage data) */
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2500 5399 : /* ... */
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2502 293784 : /* ... */
2503 : /* ... */
2504 2850242 : /* ... */
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2506 249189 : /* ... */
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2508 1418 : /* (content generated from coverage data) */
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2520 9576530 : /* ... */
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2522 1217844 : /* ... */
2523 : /* ... */
2524 1471825 : /* ... */
2525 : /* ... */
2526 18829 : /* ... */
2527 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2528 195008778 : /* (content generated from coverage data) */
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2530 1074975 : /* ... */
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2532 139671247 : /* ... */
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2534 3055246 : /* ... */
2535 : /* ... */
2536 415757 : /* ... */
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2543 0 : /* ... */
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2556 8345734 : /* ... */
2557 8345734 : /* ... */
2558 : /* ... */
2559 : /* ... */
2560 1086733 : /* ... */
2561 : /* ... */
2562 0 : /* ... */
2563 : /* ... */
2564 0 : /* ... */
2565 : /* ... */
2566 0 : /* ... */
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2568 0 : /* (content generated from coverage data) */
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2571 : /* ... */
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2573 : /* ... */
2574 8598 : /* ... */
2575 : /* ... */
2576 6116057 : /* ... */
2577 : /* ... */
2578 154459 : /* ... */
2579 : /* ... */
2580 267001 : /* ... */
2581 : /* ... */
2582 3379 : /* ... */
2583 : /* ... */
2584 0 : /* ... */
2585 : /* ... */
2586 0 : /* ... */
2587 0 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2588 0 : /* (content generated from coverage data) */
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2606 0 : /* ... */
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2610 0 : /* ... */
2611 0 : /* ... */
2612 0 : /* ... */
2613 0 : /* ... */
2614 : /* ... */
2615 : /* ... */
2616 1337 : /* ... */
2617 : /* END: function "_Z19lookup_constraint_1PKc" */
2618 : /* ... */
2619 : /* ... */
2620 : /* ... */
2621 : /* ... */
2622 : /* ... */
2623 : /* ... */
2624 : /* ... */
2625 : /* ... */
2626 : /* ... */
2627 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2628 : /* (content generated from coverage data) */
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2640 : /* ... */
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2642 : /* ... */
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2660 : /* ... */
2661 : /* ... */
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2663 : /* ... */
2664 : /* ... */
2665 : /* ... */
2666 : /* ... */
2667 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2670 : /* ... */
2671 : /* ... */
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2673 : /* ... */
2674 : /* ... */
2675 : /* ... */
2676 : /* ... */
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2678 : /* ... */
2679 : /* ... */
2680 : /* ... */
2681 : /* ... */
2682 : /* ... */
2683 : /* ... */
2684 : /* ... */
2685 : /* ... */
2686 : /* ... */
2687 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2688 : /* (content generated from coverage data) */
2689 : /* ... */
2690 : /* ... */
2691 : /* ... */
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2700 : /* ... */
2701 : /* ... */
2702 : /* ... */
2703 : /* ... */
2704 : /* ... */
2705 : /* ... */
2706 : /* ... */
2707 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2708 : /* (content generated from coverage data) */
2709 : /* ... */
2710 : /* ... */
2711 : /* ... */
2712 : /* ... */
2713 : /* ... */
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2716 : /* ... */
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2718 : /* ... */
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2720 : /* ... */
2721 : /* ... */
2722 : /* ... */
2723 : /* ... */
2724 : /* ... */
2725 : /* ... */
2726 : /* ... */
2727 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2728 : /* (content generated from coverage data) */
2729 : /* ... */
2730 : /* ... */
2731 : /* ... */
2732 : /* ... */
2733 : /* ... */
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2740 : /* ... */
2741 : /* ... */
2742 : /* ... */
2743 : /* ... */
2744 : /* ... */
2745 : /* ... */
2746 : /* ... */
2747 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2748 : /* (content generated from coverage data) */
2749 : /* ... */
2750 : /* ... */
2751 : /* ... */
2752 : /* ... */
2753 : /* ... */
2754 : /* ... */
2755 : /* ... */
2756 : /* ... */
2757 : /* ... */
2758 : /* ... */
2759 : /* ... */
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2879 7255900765 : /* BEGIN: function "_Z26reg_class_for_constraint_114constraint_num" */
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2902 241802417 : /* ... */
2903 1505755059 : /* ... */
2904 14370 : /* ... */
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2906 1217844 : /* ... */
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2916 94488 : /* ... */
2917 6116057 : /* ... */
2918 : /* ... */
2919 : /* ... */
2920 : /* ... */
2921 : /* END: function "_Z26reg_class_for_constraint_114constraint_num" */
2922 : /* ... */
2923 : /* ... */
2924 : /* ... */
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2983 : /* ... */
2984 : /* ... */
2985 7015698 : /* END: function "_Z32insn_const_int_ok_for_constraintl14constraint_num" */
2986 : /* ... */
2987 7015698 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2988 : /* (content generated from coverage data) */
2989 1341450 : /* ... */
2990 1341450 : /* ... */
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