Line data Source code
1 : ;; Predicate definitions for IA-32 and x86-64.
2 : ;; Copyright (C) 2004-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; Return true if OP is either a i387 or SSE fp register.
21 : (define_predicate "any_fp_register_operand"
22 : (and (match_code "reg")
23 132275608 : (match_test "ANY_FP_REGNO_P (REGNO (op))")))
24 40535 :
25 : ;; Return true if OP is an i387 fp register.
26 : (define_predicate "fp_register_operand"
27 : (and (match_code "reg")
28 1534342 : (match_test "STACK_REGNO_P (REGNO (op))")))
29 1446260 :
30 435434974 : ;; True if the operand is a GENERAL class register.
31 : (define_predicate "general_reg_operand"
32 : (and (match_code "reg")
33 271530684 : (match_test "GENERAL_REGNO_P (REGNO (op))")))
34 203592456 :
35 452684069 : ;; True if the operand is an INDEX class register.
36 : (define_predicate "index_reg_operand"
37 : (and (match_code "reg")
38 683743 : (match_test "INDEX_REGNO_P (REGNO (op))")))
39 683667 :
40 684448 : ;; True if the operand is a nonimmediate operand with GENERAL class register.
41 : (define_predicate "nonimmediate_gr_operand"
42 : (if_then_else (match_code "reg")
43 56422714 : (match_test "GENERAL_REGNO_P (REGNO (op))")
44 62785444 : (match_operand 0 "nonimmediate_operand")))
45 78466693 :
46 : ;; True if the operand is a general operand with GENERAL class register.
47 : (define_predicate "general_gr_operand"
48 91676823 : (if_then_else (match_code "reg")
49 39694904 : (match_test "GENERAL_REGNO_P (REGNO (op))")
50 116147385 : (match_operand 0 "general_operand")))
51 :
52 : ;; True if the operand is an MMX register.
53 : (define_predicate "mmx_reg_operand"
54 39498096 : (and (match_code "reg")
55 193 : (match_test "MMX_REGNO_P (REGNO (op))")))
56 39498096 :
57 : ;; Match register operands, but include memory operands for
58 : ;; !TARGET_MMX_WITH_SSE.
59 : (define_predicate "register_mmxmem_operand"
60 627577 : (ior (match_operand 0 "register_operand")
61 12 : (and (not (match_test "TARGET_MMX_WITH_SSE"))
62 627577 : (match_operand 0 "memory_operand"))))
63 :
64 : ;; True if the operand is an SSE register.
65 158837215 : (define_predicate "sse_reg_operand"
66 : (and (match_code "reg")
67 158837215 : (match_test "SSE_REGNO_P (REGNO (op))")))
68 1731982 :
69 : ;; Return true if op is a QImode register.
70 : (define_predicate "any_QIreg_operand"
71 : (and (match_code "reg")
72 8177700 : (match_test "ANY_QI_REGNO_P (REGNO (op))")))
73 3805919 :
74 9725413 : ;; Return true if op is one of QImode registers: %[abcd][hl].
75 : (define_predicate "QIreg_operand"
76 : (and (match_code "reg")
77 2317134 : (match_test "QI_REGNO_P (REGNO (op))")))
78 2188375 :
79 6117485 : ;; Return true if op is a QImode register operand other than %[abcd][hl].
80 : (define_predicate "ext_QIreg_operand"
81 3268045 : (and (match_test "TARGET_64BIT")
82 3268386 : (match_code "reg")
83 962962 : (not (match_test "QI_REGNO_P (REGNO (op))"))))
84 3524788 :
85 : ;; Return true if op is the AX register.
86 : (define_predicate "ax_reg_operand"
87 : (and (match_code "reg")
88 22821367 : (match_test "REGNO (op) == AX_REG")))
89 0 :
90 114342686 : ;; Return true if op is the flags register.
91 : (define_special_predicate "flags_reg_operand"
92 : (and (match_code "reg")
93 113687222 : (match_test "REGNO (op) == FLAGS_REG")))
94 :
95 40943152 : ;; True if the operand is a MASK register.
96 : (define_predicate "mask_reg_operand"
97 9934503 : (and (match_code "reg")
98 4548 : (match_test "MASK_REGNO_P (REGNO (op))")))
99 9939051 :
100 : ;; Match a DI, SI or HImode register operand.
101 : (define_special_predicate "int248_register_operand"
102 : (and (match_operand 0 "register_operand")
103 957413 : (ior (and (match_test "TARGET_64BIT")
104 273423 : (match_test "GET_MODE (op) == DImode"))
105 571023 : (match_test "GET_MODE (op) == SImode")
106 357288 : (match_test "GET_MODE (op) == HImode"))))
107 :
108 : ;; Match a DI, SI, HI or QImode nonimmediate_operand.
109 : (define_special_predicate "int_nonimmediate_operand"
110 377129 : (and (match_operand 0 "nonimmediate_operand")
111 455912 : (ior (and (match_test "TARGET_64BIT")
112 377129 : (match_test "GET_MODE (op) == DImode"))
113 172391 : (match_test "GET_MODE (op) == SImode")
114 : (match_test "GET_MODE (op) == HImode")
115 377129 : (match_test "GET_MODE (op) == QImode"))))
116 :
117 : ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
118 : (define_predicate "register_ssemem_operand"
119 2855893 : (if_then_else
120 2855893 : (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
121 2855893 : (match_operand 0 "nonimmediate_operand")
122 : (match_operand 0 "register_operand")))
123 :
124 1078954 : ;; Match nonimmediate operands, but exclude memory operands
125 : ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
126 1078954 : (define_predicate "nonimm_ssenomem_operand"
127 : (if_then_else
128 1078954 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
129 2157908 : (not (match_test "TARGET_MIX_SSE_I387")))
130 : (match_operand 0 "register_operand")
131 : (match_operand 0 "nonimmediate_operand")))
132 :
133 766981 : ;; The above predicate, suitable for x87 arithmetic operators.
134 : (define_predicate "x87nonimm_ssenomem_operand"
135 766981 : (if_then_else
136 766981 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
137 1533962 : (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
138 : (match_operand 0 "register_operand")
139 : (match_operand 0 "nonimmediate_operand")))
140 :
141 34813 : ;; Match register operands, include memory operand for TARGET_SSE4_1.
142 : (define_predicate "register_sse4nonimm_operand"
143 34813 : (if_then_else (match_test "TARGET_SSE4_1")
144 : (match_operand 0 "nonimmediate_operand")
145 : (match_operand 0 "register_operand")))
146 :
147 14090 : ;; Return true if VALUE is symbol reference
148 : (define_predicate "symbol_operand"
149 14090 : (match_code "symbol_ref"))
150 14090 :
151 : ;; Return true if VALUE is an ENDBR opcode in immediate field.
152 : (define_predicate "ix86_endbr_immediate_operand"
153 : (match_code "const_int")
154 6382428959 : {
155 6382428959 : if (flag_cf_protection & CF_BRANCH)
156 : {
157 1190097642 : unsigned HOST_WIDE_INT imm = UINTVAL (op);
158 1190097642 : unsigned HOST_WIDE_INT val = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
159 :
160 1190097642 : if (imm == val)
161 : return true;
162 :
163 : /* NB: Encoding is byte based. */
164 1190097434 : if (TARGET_64BIT)
165 2297079862 : for (; imm >= val; imm >>= 8)
166 1294939168 : if (imm == val)
167 : return true;
168 : }
169 :
170 : return false;
171 : })
172 :
173 : ;; Return true if VALUE can be stored in a sign extended immediate field.
174 8282748362 : (define_predicate "x86_64_immediate_operand"
175 : (match_code "const_int,symbol_ref,label_ref,const")
176 8282748362 : {
177 11334766271 : if (ix86_endbr_immediate_operand (op, VOIDmode))
178 : return false;
179 :
180 4952337061 : if (!TARGET_64BIT)
181 5139016849 : return immediate_operand (op, mode);
182 :
183 4765657524 : switch (GET_CODE (op))
184 : {
185 3893131016 : case CONST_INT:
186 3893131016 : {
187 3893131016 : HOST_WIDE_INT val = INTVAL (op);
188 3893131016 : return trunc_int_for_mode (val, SImode) == val;
189 : }
190 710500392 : case SYMBOL_REF:
191 : /* TLS symbols are not constant. */
192 710500392 : if (SYMBOL_REF_TLS_MODEL (op))
193 : return false;
194 :
195 : /* Load the external function address via the GOT slot. */
196 710464397 : if (ix86_force_load_from_GOT_p (op))
197 : return false;
198 :
199 : /* For certain code models, the symbolic references are known to fit.
200 : in CM_SMALL_PIC model we know it fits if it is local to the shared
201 : library. Don't count TLS SYMBOL_REFs here, since they should fit
202 : only if inside of UNSPEC handled below. */
203 710464295 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
204 710464295 : || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
205 :
206 23584030 : case LABEL_REF:
207 : /* For certain code models, the code is near as well. */
208 23584030 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
209 : || ix86_cmodel == CM_KERNEL);
210 :
211 138442086 : case CONST:
212 : /* We also may accept the offsetted memory references in certain
213 : special cases. */
214 138442086 : if (GET_CODE (XEXP (op, 0)) == UNSPEC)
215 738424 : switch (XINT (XEXP (op, 0), 1))
216 : {
217 : case UNSPEC_GOTPCREL:
218 : case UNSPEC_DTPOFF:
219 : case UNSPEC_GOTNTPOFF:
220 : case UNSPEC_NTPOFF:
221 : case UNSPEC_SECREL32:
222 : return true;
223 : default:
224 : break;
225 : }
226 :
227 137705172 : if (GET_CODE (XEXP (op, 0)) == PLUS)
228 : {
229 137703662 : rtx op1 = XEXP (XEXP (op, 0), 0);
230 137703662 : rtx op2 = XEXP (XEXP (op, 0), 1);
231 :
232 137703662 : if (ix86_cmodel == CM_LARGE && GET_CODE (op1) != UNSPEC)
233 : return false;
234 137703657 : if (!CONST_INT_P (op2))
235 : return false;
236 :
237 137703657 : HOST_WIDE_INT offset = INTVAL (op2);
238 137703657 : if (trunc_int_for_mode (offset, SImode) != offset)
239 : return false;
240 :
241 137698347 : switch (GET_CODE (op1))
242 : {
243 137359727 : case SYMBOL_REF:
244 : /* TLS symbols are not constant. */
245 137359727 : if (SYMBOL_REF_TLS_MODEL (op1))
246 : return false;
247 :
248 : /* Load the external function address via the GOT slot. */
249 137349177 : if (ix86_force_load_from_GOT_p (op1))
250 : return false;
251 :
252 : /* For CM_SMALL assume that latest object is 16MB before
253 : end of 31bits boundary. We may also accept pretty
254 : large negative constants knowing that all objects are
255 : in the positive half of address space. */
256 137349171 : if ((ix86_cmodel == CM_SMALL
257 195794 : || (ix86_cmodel == CM_MEDIUM
258 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
259 137349171 : && offset < 16*1024*1024)
260 : return true;
261 : /* For CM_KERNEL we know that all object resist in the
262 : negative half of 32bits address space. We may not
263 : accept negative offsets, since they may be just off
264 : and we may accept pretty large positive ones. */
265 199066 : if (ix86_cmodel == CM_KERNEL
266 0 : && offset > 0)
267 : return true;
268 : break;
269 :
270 4790 : case LABEL_REF:
271 : /* These conditions are similar to SYMBOL_REF ones, just the
272 : constraints for code models differ. */
273 4790 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
274 4790 : && offset < 16*1024*1024)
275 : return true;
276 0 : if (ix86_cmodel == CM_KERNEL
277 0 : && offset > 0)
278 : return true;
279 : break;
280 :
281 333830 : case UNSPEC:
282 333830 : switch (XINT (op1, 1))
283 : {
284 : case UNSPEC_DTPOFF:
285 : case UNSPEC_NTPOFF:
286 : return true;
287 : }
288 : break;
289 :
290 : default:
291 : break;
292 : }
293 : }
294 : break;
295 :
296 0 : default:
297 0 : gcc_unreachable ();
298 : }
299 :
300 : return false;
301 : })
302 :
303 : ;; Return true if VALUE can be stored in the zero extended immediate field.
304 5434069764 : (define_predicate "x86_64_zext_immediate_operand"
305 : (match_code "const_int,symbol_ref,label_ref,const")
306 5434069764 : {
307 744107028 : if (ix86_endbr_immediate_operand (op, VOIDmode))
308 4952337312 : return false;
309 4952337312 :
310 744106880 : switch (GET_CODE (op))
311 4952337312 : {
312 5628631423 : case CONST_INT:
313 676294111 : return !(INTVAL (op) & ~HOST_WIDE_INT_C (0xffffffff));
314 :
315 61810575 : case SYMBOL_REF:
316 4952337312 : /* TLS symbols are not constant. */
317 5014147887 : if (SYMBOL_REF_TLS_MODEL (op))
318 271009952 : return false;
319 :
320 : /* Load the external function address via the GOT slot. */
321 61775451 : if (ix86_force_load_from_GOT_p (op))
322 744107028 : return false;
323 :
324 : /* For certain code models, the symbolic references are known to fit. */
325 61775350 : return (ix86_cmodel == CM_SMALL
326 61775350 : || (ix86_cmodel == CM_MEDIUM
327 218 : && !SYMBOL_REF_FAR_ADDR_P (op)));
328 :
329 2151346 : case LABEL_REF:
330 : /* For certain code models, the code is near as well. */
331 2151346 : return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
332 :
333 3850848 : case CONST:
334 : /* We also may accept the offsetted memory references in certain
335 : special cases. */
336 3850848 : if (GET_CODE (XEXP (op, 0)) == PLUS)
337 : {
338 3846181 : rtx op1 = XEXP (XEXP (op, 0), 0);
339 3846181 : rtx op2 = XEXP (XEXP (op, 0), 1);
340 :
341 3846181 : if (ix86_cmodel == CM_LARGE)
342 : return false;
343 3846179 : if (!CONST_INT_P (op2))
344 : return false;
345 :
346 3846179 : HOST_WIDE_INT offset = INTVAL (op2);
347 3846179 : if (trunc_int_for_mode (offset, SImode) != offset)
348 : return false;
349 :
350 3843385 : switch (GET_CODE (op1))
351 : {
352 3842894 : case SYMBOL_REF:
353 : /* TLS symbols are not constant. */
354 3842894 : if (SYMBOL_REF_TLS_MODEL (op1))
355 : return false;
356 :
357 : /* Load the external function address via the GOT slot. */
358 3833572 : if (ix86_force_load_from_GOT_p (op1))
359 : return false;
360 :
361 : /* For small code model we may accept pretty large positive
362 : offsets, since one bit is available for free. Negative
363 : offsets are limited by the size of NULL pointer area
364 : specified by the ABI. */
365 3833566 : if ((ix86_cmodel == CM_SMALL
366 164908 : || (ix86_cmodel == CM_MEDIUM
367 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
368 3833566 : && offset > -0x10000)
369 : return true;
370 : /* ??? For the kernel, we may accept adjustment of
371 : -0x10000000, since we know that it will just convert
372 : negative address space to positive, but perhaps this
373 : is not worthwhile. */
374 : break;
375 :
376 0 : case LABEL_REF:
377 : /* These conditions are similar to SYMBOL_REF ones, just the
378 : constraints for code models differ. */
379 0 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
380 0 : && offset > -0x10000)
381 : return true;
382 : break;
383 :
384 : default:
385 : return false;
386 : }
387 : }
388 : break;
389 :
390 0 : default:
391 0 : gcc_unreachable ();
392 : }
393 : return false;
394 : })
395 :
396 : ;; Return true if VALUE is a constant integer whose negation satisfies
397 991670937 : ;; x86_64_immediate_operand.
398 : (define_predicate "x86_64_neg_const_int_operand"
399 991670937 : (match_code "const_int")
400 : {
401 744140285 : HOST_WIDE_INT val = -UINTVAL (op);
402 15029 : if (mode == DImode && trunc_int_for_mode (val, SImode) != val)
403 744107028 : return false;
404 32560 : if (flag_cf_protection & CF_BRANCH)
405 744107028 : {
406 13928 : unsigned HOST_WIDE_INT endbr = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
407 13928 : if ((val & HOST_WIDE_INT_C (0xffffffff)) == endbr)
408 : return false;
409 744107028 : }
410 744107028 : return true;
411 58162417 : })
412 :
413 : ;; Return true if VALUE is a constant integer whose low and high words satisfy
414 47690 : ;; x86_64_immediate_operand.
415 33257 : (define_predicate "x86_64_hilo_int_operand"
416 80947 : (match_code "const_int,const_wide_int")
417 33257 : {
418 43909675 : switch (GET_CODE (op))
419 : {
420 43858384 : case CONST_INT:
421 43909675 : return x86_64_immediate_operand (op, mode);
422 :
423 51291 : case CONST_WIDE_INT:
424 51291 : gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
425 51291 : return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
426 : DImode)
427 51291 : && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
428 : 1)),
429 : DImode));
430 :
431 0 : default:
432 0 : gcc_unreachable ();
433 : }
434 : })
435 :
436 : ;; Return true if VALUE is a constant integer whose value is
437 44600882 : ;; x86_64_immediate_operand value zero extended from word mode to mode.
438 : (define_predicate "x86_64_dwzext_immediate_operand"
439 44600882 : (match_code "const_int,const_wide_int")
440 : {
441 3742 : if (ix86_endbr_immediate_operand (op, VOIDmode))
442 43909675 : return false;
443 43909675 :
444 3742 : switch (GET_CODE (op))
445 : {
446 1624 : case CONST_INT:
447 1624 : if (!TARGET_64BIT)
448 43909675 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff);
449 1624 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff);
450 :
451 2118 : case CONST_WIDE_INT:
452 5860 : if (!TARGET_64BIT)
453 : return false;
454 2118 : return (CONST_WIDE_INT_NUNITS (op) == 2
455 2118 : && CONST_WIDE_INT_ELT (op, 1) == 0
456 4236 : && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode)
457 2118 : == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0)));
458 :
459 0 : default:
460 0 : gcc_unreachable ();
461 : }
462 : })
463 :
464 : ;; Return true if size of VALUE can be stored in a sign
465 3742 : ;; extended immediate field.
466 : (define_predicate "x86_64_immediate_size_operand"
467 3742 : (and (match_code "symbol_ref")
468 0 : (ior (not (match_test "TARGET_64BIT"))
469 0 : (match_test "ix86_cmodel == CM_SMALL")
470 0 : (match_test "ix86_cmodel == CM_KERNEL"))))
471 0 :
472 : ;; Return true if OP is general operand representable on x86_64.
473 : (define_predicate "x86_64_general_operand"
474 148833115 : (if_then_else (match_test "TARGET_64BIT")
475 148836857 : (ior (match_operand 0 "nonimmediate_operand")
476 3742 : (match_operand 0 "x86_64_immediate_operand"))
477 148833115 : (match_operand 0 "general_operand")))
478 62417451 :
479 : ;; Return true if OP's both words are general operands representable
480 62417451 : ;; on x86_64.
481 : (define_predicate "x86_64_hilo_general_operand"
482 62417451 : (if_then_else (match_test "TARGET_64BIT")
483 : (ior (match_operand 0 "nonimmediate_operand")
484 : (match_operand 0 "x86_64_hilo_int_operand"))
485 : (match_operand 0 "general_operand")))
486 259093 :
487 : ;; Return true if OP is non-VOIDmode general operand representable
488 259093 : ;; on x86_64. This predicate is used in sign-extending conversion
489 : ;; operations that require non-VOIDmode immediate operands.
490 : (define_predicate "x86_64_sext_operand"
491 259093 : (and (match_test "GET_MODE (op) != VOIDmode")
492 : (match_operand 0 "x86_64_general_operand")))
493 :
494 : ;; Return true if OP is non-VOIDmode general operand. This predicate
495 11347 : ;; is used in sign-extending conversion operations that require
496 : ;; non-VOIDmode immediate operands.
497 11347 : (define_predicate "sext_operand"
498 11347 : (and (match_test "GET_MODE (op) != VOIDmode")
499 : (match_operand 0 "general_operand")))
500 :
501 : ;; Return true if OP is representable on x86_64 as zero-extended operand.
502 3570845 : ;; This predicate is used in zero-extending conversion operations that
503 : ;; require non-VOIDmode immediate operands.
504 3570845 : (define_predicate "x86_64_zext_operand"
505 3570845 : (if_then_else (match_test "TARGET_64BIT")
506 : (ior (match_operand 0 "nonimmediate_operand")
507 : (and (match_operand 0 "x86_64_zext_immediate_operand")
508 114072 : (match_test "GET_MODE (op) != VOIDmode")))
509 : (match_operand 0 "nonimmediate_operand")))
510 :
511 : ;; Return true if OP is general operand representable on x86_64
512 2470699 : ;; as either sign extended or zero extended constant.
513 : (define_predicate "x86_64_szext_general_operand"
514 2470699 : (if_then_else (match_test "TARGET_64BIT")
515 : (ior (match_operand 0 "nonimmediate_operand")
516 : (match_operand 0 "x86_64_immediate_operand")
517 : (match_operand 0 "x86_64_zext_immediate_operand"))
518 30090743 : (match_operand 0 "general_operand")))
519 :
520 30090743 : ;; Return true if OP is nonmemory operand representable on x86_64.
521 : (define_predicate "x86_64_nonmemory_operand"
522 30090743 : (if_then_else (match_test "TARGET_64BIT")
523 : (ior (match_operand 0 "register_operand")
524 : (match_operand 0 "x86_64_immediate_operand"))
525 : (match_operand 0 "nonmemory_operand")))
526 19043 :
527 : ;; Return true if OP is nonmemory operand representable on x86_64.
528 19043 : (define_predicate "x86_64_szext_nonmemory_operand"
529 19043 : (if_then_else (match_test "TARGET_64BIT")
530 : (ior (match_operand 0 "register_operand")
531 : (match_operand 0 "x86_64_immediate_operand")
532 : (match_operand 0 "x86_64_zext_immediate_operand"))
533 177260404 : (match_operand 0 "nonmemory_operand")))
534 :
535 : ;; Return true when operand is PIC expression that can be computed by lea
536 : ;; operation.
537 : (define_predicate "pic_32bit_operand"
538 : (match_code "const,symbol_ref,label_ref")
539 : {
540 177260404 : if (!flag_pic)
541 : return false;
542 :
543 : /* Rule out relocations that translate into 64bit constants. */
544 8285524 : if (TARGET_64BIT && GET_CODE (op) == CONST)
545 : {
546 151903 : rtx tmp = XEXP (op, 0);
547 151903 : if (GET_CODE (tmp) == PLUS && CONST_INT_P (XEXP (tmp, 1)))
548 150441 : tmp = XEXP (tmp, 0);
549 151903 : if (GET_CODE (tmp) == UNSPEC
550 1462 : && (XINT (tmp, 1) == UNSPEC_GOTOFF
551 1462 : || XINT (tmp, 1) == UNSPEC_GOT))
552 : return false;
553 : }
554 :
555 8284602 : return symbolic_operand (op, mode);
556 : })
557 :
558 : ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
559 1275763702 : (define_predicate "x86_64_movabs_operand"
560 : (and (match_operand 0 "nonmemory_operand")
561 1275763702 : (not (match_operand 0 "pic_32bit_operand"))))
562 :
563 177260404 : ;; Return true if OP is either a symbol reference or a sum of a symbol
564 177260404 : ;; reference and a constant.
565 177260404 : (define_predicate "symbolic_operand"
566 177260404 : (match_code "symbol_ref,label_ref,const")
567 : {
568 8645057 : switch (GET_CODE (op))
569 : {
570 177260404 : case SYMBOL_REF:
571 177260404 : case LABEL_REF:
572 180147 : return true;
573 :
574 184169 : case CONST:
575 184169 : op = XEXP (op, 0);
576 493884881 : if (SYMBOL_REF_P (op)
577 184169 : || LABEL_REF_P (op)
578 493884881 : || (GET_CODE (op) == UNSPEC
579 8531 : && (XINT (op, 1) == UNSPEC_GOT
580 8531 : || XINT (op, 1) == UNSPEC_GOTOFF
581 : || XINT (op, 1) == UNSPEC_SECREL32
582 8645057 : || XINT (op, 1) == UNSPEC_PCREL
583 : || XINT (op, 1) == UNSPEC_GOTPCREL)))
584 : return true;
585 176307 : if (GET_CODE (op) != PLUS
586 175638 : || !CONST_INT_P (XEXP (op, 1)))
587 : return false;
588 :
589 175638 : op = XEXP (op, 0);
590 175638 : if (SYMBOL_REF_P (op)
591 175638 : || LABEL_REF_P (op))
592 : return true;
593 : /* Only @GOTOFF and @SECREL32 get offsets. */
594 2128 : if (GET_CODE (op) != UNSPEC
595 2128 : || (XINT (op, 1) != UNSPEC_GOTOFF
596 0 : && XINT (op, 1) != UNSPEC_SECREL32))
597 : return false;
598 :
599 2128 : op = XVECEXP (op, 0, 0);
600 2128 : if (SYMBOL_REF_P (op)
601 2128 : || LABEL_REF_P (op))
602 2128 : return true;
603 : return false;
604 :
605 0 : default:
606 0 : gcc_unreachable ();
607 : }
608 : })
609 :
610 : ;; Return true if OP is a symbolic operand that resolves locally.
611 16086593 : (define_predicate "local_symbolic_operand"
612 : (match_code "const,label_ref,symbol_ref")
613 16086593 : {
614 2914515 : if (GET_CODE (op) == CONST
615 16308 : && GET_CODE (XEXP (op, 0)) == PLUS
616 8531 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
617 8531 : op = XEXP (XEXP (op, 0), 0);
618 8645057 :
619 2914515 : if (LABEL_REF_P (op))
620 : return true;
621 :
622 2869541 : if (!SYMBOL_REF_P (op))
623 8645057 : return false;
624 540473 :
625 2859636 : if (SYMBOL_REF_TLS_MODEL (op))
626 : return false;
627 :
628 2914515 : /* Dll-imported symbols are always external. */
629 2859636 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
630 : return false;
631 2859636 : if (SYMBOL_REF_LOCAL_P (op))
632 : return true;
633 :
634 : /* There is, however, a not insubstantial body of code in the rest of
635 : the compiler that assumes it can just stick the results of
636 : ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
637 : /* ??? This is a hack. Should update the body of the compiler to
638 : always create a DECL an invoke targetm.encode_section_info. */
639 93649 : if (strncmp (XSTR (op, 0), internal_label_prefix,
640 : internal_label_prefix_len) == 0)
641 0 : return true;
642 :
643 : return false;
644 : })
645 :
646 : (define_predicate "local_func_symbolic_operand"
647 2923206 : (match_operand 0 "local_symbolic_operand")
648 : {
649 2923206 : if (GET_CODE (op) == CONST
650 0 : && GET_CODE (XEXP (op, 0)) == PLUS
651 0 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
652 0 : op = XEXP (XEXP (op, 0), 0);
653 2914515 :
654 2914527 : if (SYMBOL_REF_P (op)
655 12 : && !SYMBOL_REF_FUNCTION_P (op))
656 0 : return false;
657 :
658 2914515 : return true;
659 2914515 : })
660 2810952 :
661 : ;; Test for a legitimate @GOTOFF operand.
662 30 : ;;
663 : ;; VxWorks does not impose a fixed gap between segments; the run-time
664 42 : ;; gap can be different from the object-file gap. We therefore can't
665 12 : ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
666 : ;; same segment as the GOT. Unfortunately, the flexibility of linker
667 : ;; scripts means that we can't be sure of that in general, so assume
668 : ;; @GOTOFF is not valid on VxWorks, except with the large code model.
669 2923139 : ;; The comments above seem to apply only to VxWorks releases before 7.
670 : (define_predicate "gotoff_operand"
671 2923139 : (and (ior (not (match_test "TARGET_VXWORKS_VAROFF"))
672 : (match_test "ix86_cmodel == CM_LARGE")
673 2923139 : (match_test "ix86_cmodel == CM_LARGE_PIC"))
674 : (match_operand 0 "local_symbolic_operand")))
675 :
676 : ;; Test for various thread-local symbols.
677 30052 : (define_special_predicate "tls_symbolic_operand"
678 : (and (match_code "symbol_ref")
679 30052 : (match_test "SYMBOL_REF_TLS_MODEL (op)")))
680 :
681 : (define_special_predicate "tls_modbase_operand"
682 : (and (match_code "symbol_ref")
683 72 : (match_test "op == ix86_tls_module_base ()")))
684 :
685 144 : (define_predicate "tls_address_pattern"
686 : (and (match_code "set,parallel,unspec,unspec_volatile")
687 236786619 : (match_test "ix86_tls_address_pattern_p (op)")))
688 0 :
689 236786619 : ;; Test for a pc-relative call operand
690 : (define_predicate "constant_call_address_operand"
691 236786619 : (match_code "symbol_ref")
692 371588574 : {
693 134801746 : if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
694 134801735 : || flag_force_indirect_call
695 269602186 : || (TARGET_INDIRECT_BRANCH_REGISTER
696 1022 : && ix86_nopic_noplt_attribute_p (op)))
697 1748 : return false;
698 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
699 236786619 : return false;
700 : return true;
701 : })
702 :
703 : ;; True for any non-virtual and non-eliminable register. Used in places where
704 140438049 : ;; instantiation of such a register may cause the pattern to not be recognized.
705 : (define_predicate "register_no_elim_operand"
706 134801955 : (match_operand 0 "register_operand")
707 275238256 : {
708 97117124 : if (SUBREG_P (op))
709 63071 : op = SUBREG_REG (op);
710 :
711 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
712 20695029 : because it is guaranteed to be reloaded into one. */
713 20695029 : if (MEM_P (op))
714 : return true;
715 :
716 20695029 : return !(op == arg_pointer_rtx
717 20667151 : || op == frame_pointer_rtx
718 20665135 : || VIRTUAL_REGISTER_P (op));
719 : })
720 :
721 : ;; Similarly, but include the stack pointer. This is used
722 24672534 : ;; to prevent esp from being used as an index reg.
723 : (define_predicate "register_no_SP_operand"
724 24672534 : (match_operand 0 "register_operand")
725 20695029 : {
726 332058 : if (SUBREG_P (op))
727 8087 : op = SUBREG_REG (op);
728 :
729 332058 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
730 : because it is guaranteed to be reloaded into one. */
731 332058 : if (MEM_P (op))
732 : return true;
733 :
734 332058 : return !(op == arg_pointer_rtx
735 332058 : || op == frame_pointer_rtx
736 332058 : || op == stack_pointer_rtx
737 332058 : || VIRTUAL_REGISTER_P (op));
738 : })
739 :
740 : ;; P6 processors will jump to the address after the decrement when %esp
741 368862 : ;; is used as a call operand, so they will execute return address as a code.
742 : ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
743 368862 :
744 332058 : (define_predicate "call_register_operand"
745 1833437 : (if_then_else (match_test "TARGET_64BIT")
746 : (match_operand 0 "register_operand")
747 : (match_operand 0 "register_no_SP_operand")))
748 1833437 :
749 17914106 : ;; Return false if this is any eliminable register. Otherwise general_operand.
750 1833437 : (define_predicate "general_no_elim_operand"
751 17914106 : (if_then_else (match_code "reg,subreg")
752 : (match_operand 0 "register_no_elim_operand")
753 : (match_operand 0 "general_operand")))
754 :
755 11584912 : ;; Return false if this is any eliminable register. Otherwise
756 : ;; register_operand or a constant.
757 11584912 : (define_predicate "nonmemory_no_elim_operand"
758 : (ior (match_operand 0 "register_no_elim_operand")
759 : (match_operand 0 "immediate_operand")))
760 :
761 618082 : ;; Test for a valid operand for indirect branch.
762 : (define_predicate "indirect_branch_operand"
763 618082 : (ior (match_operand 0 "register_operand")
764 568559 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
765 568532 : (not (match_test "TARGET_X32"))
766 : (match_operand 0 "memory_operand"))))
767 :
768 : ;; Return true if OP is a memory operands that can be used in sibcalls.
769 23933 : ;; Since sibcall never returns, we can only use call-clobbered register
770 : ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
771 : ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
772 : ;; and *sibcall_value_GOT_32 patterns.
773 : (define_predicate "sibcall_memory_operand"
774 : (match_operand 0 "memory_operand")
775 : {
776 23933 : op = XEXP (op, 0);
777 23933 : if (CONSTANT_P (op))
778 : return true;
779 10428 : if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
780 : {
781 9438 : int regno = REGNO (XEXP (op, 0));
782 9438 : if (!HARD_REGISTER_NUM_P (regno) || call_used_or_fixed_reg_p (regno))
783 : {
784 7718 : op = XEXP (op, 1);
785 7718 : if (GOT32_symbol_operand (op, VOIDmode))
786 : return true;
787 : }
788 : }
789 : return false;
790 : })
791 :
792 : ;; Return true if OP is a GOT memory operand.
793 1371862 : (define_predicate "GOT_memory_operand"
794 : (and (match_operand 0 "memory_operand")
795 1395795 : (match_code "const" "0")
796 23933 : (match_code "unspec" "00")
797 566 : (match_test "XINT (XEXP (XEXP (op, 0), 0), 1) == UNSPEC_GOTPCREL")))
798 :
799 : ;; Test for a valid operand for a call instruction.
800 464 : ;; Allow constant call address operands in Pmode only.
801 48139010 : (define_special_predicate "call_insn_operand"
802 464 : (ior (match_test "constant_call_address_operand
803 54291991 : (op, mode == VOIDmode ? mode : Pmode)")
804 : (match_operand 0 "call_register_operand")
805 837496 : (match_test "satisfies_constraint_Bw (op)")))
806 :
807 : ;; Similarly, but for tail calls, in which we cannot allow memory references.
808 : (define_special_predicate "sibcall_insn_operand"
809 1215980 : (ior (match_test "constant_call_address_operand
810 1375715 : (op, mode == VOIDmode ? mode : Pmode)")
811 1215980 : (match_operand 0 "register_no_elim_operand")
812 122366 : (match_test "satisfies_constraint_Bs (op)")))
813 :
814 : ;; Return true if OP is a 32-bit GOT symbol operand.
815 : (define_predicate "GOT32_symbol_operand"
816 9630 : (and (match_code "const")
817 : (match_code "unspec" "0")
818 9630 : (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_GOT")))
819 0 :
820 : ;; Match exactly zero.
821 : (define_predicate "const0_operand"
822 : (match_code "const_int,const_double,const_vector")
823 134706152 : {
824 134706152 : if (mode == VOIDmode)
825 21209334 : mode = GET_MODE (op);
826 134706152 : return op == CONST0_RTX (mode);
827 : })
828 :
829 : ;; Match one or a vector with all elements equal to one.
830 968565292 : (define_predicate "const1_operand"
831 : (match_code "const_int,const_double,const_vector")
832 968565292 : {
833 11584725 : if (mode == VOIDmode)
834 11523334 : mode = GET_MODE (op);
835 146290877 : return op == CONST1_RTX (mode);
836 134706152 : })
837 134706152 :
838 : ;; Match exactly -1.
839 12835853 : (define_predicate "constm1_operand"
840 : (and (match_code "const_int")
841 147542005 : (match_test "op == constm1_rtx")))
842 134706152 :
843 61165516 : ;; Match 0 or -1.
844 11584725 : (define_predicate "const0_or_m1_operand"
845 11587614 : (ior (match_operand 0 "const0_operand")
846 11584725 : (match_operand 0 "constm1_operand")))
847 2889 :
848 : ;; Match exactly eight.
849 : (define_predicate "const8_operand"
850 11584725 : (and (match_code "const_int")
851 11584725 : (match_test "INTVAL (op) == 8")))
852 10064 :
853 212224 : ;; Match exactly 128.
854 : (define_predicate "const128_operand"
855 27033068 : (and (match_code "const_int")
856 240664992 : (match_test "INTVAL (op) == 128")))
857 27033068 :
858 190957782 : ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
859 : (define_predicate "const_32bit_mask"
860 2855591 : (and (match_code "const_int")
861 1897127 : (match_test "trunc_int_for_mode (INTVAL (op), DImode)
862 4752718 : == HOST_WIDE_INT_C (0xffffffff)")))
863 :
864 : ;; Match 2, 4, or 8. Used for leal multiplicands.
865 : (define_predicate "const248_operand"
866 304657 : (match_code "const_int")
867 : {
868 304657 : HOST_WIDE_INT i = INTVAL (op);
869 304657 : return i == 2 || i == 4 || i == 8;
870 : })
871 :
872 : ;; Match 1, 2, or 3. Used for lea shift amounts.
873 1026949 : (define_predicate "const123_operand"
874 : (match_code "const_int")
875 1026949 : {
876 1252231 : HOST_WIDE_INT i = INTVAL (op);
877 225282 : return i == 1 || i == 2 || i == 3;
878 : })
879 :
880 225282 : ;; Match 2, 3, 6, or 7
881 233694 : (define_predicate "const2367_operand"
882 : (match_code "const_int")
883 233694 : {
884 225282 : HOST_WIDE_INT i = INTVAL (op);
885 0 : return i == 2 || i == 3 || i == 6 || i == 7;
886 : })
887 :
888 0 : ;; Match 1, 2, 4, or 8
889 0 : (define_predicate "const1248_operand"
890 : (match_code "const_int")
891 0 : {
892 110962 : HOST_WIDE_INT i = INTVAL (op);
893 110962 : return i == 1 || i == 2 || i == 4 || i == 8;
894 : })
895 :
896 110962 : ;; Match 3, 5, or 9. Used for leal multiplicands.
897 535179 : (define_predicate "const359_operand"
898 : (match_code "const_int")
899 535179 : {
900 582530 : HOST_WIDE_INT i = INTVAL (op);
901 47351 : return i == 3 || i == 5 || i == 9;
902 : })
903 :
904 47351 : ;; Match 4 or 8 to 11. Used for embedded rounding.
905 220715 : (define_predicate "const_4_or_8_to_11_operand"
906 : (match_code "const_int")
907 220715 : {
908 300689 : HOST_WIDE_INT i = INTVAL (op);
909 79974 : return i == 4 || (i >= 8 && i <= 11);
910 : })
911 :
912 79974 : ;; Match 4 or 8. Used for SAE.
913 79976 : (define_predicate "const48_operand"
914 : (match_code "const_int")
915 79976 : {
916 79974 : HOST_WIDE_INT i = INTVAL (op);
917 64500 : return i == 4 || i == 8;
918 : })
919 :
920 64500 : ;; Match 0 or 1.
921 64500 : (define_predicate "const_0_to_1_operand"
922 : (and (match_code "const_int")
923 64500 : (ior (match_test "op == const0_rtx")
924 293191 : (match_test "op == const1_rtx"))))
925 :
926 : ;; Match 0 to 3.
927 : (define_predicate "const_0_to_3_operand"
928 7536001 : (and (match_code "const_int")
929 14280057 : (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
930 7536001 :
931 : ;; Match 0 to 4.
932 : (define_predicate "const_0_to_4_operand"
933 0 : (and (match_code "const_int")
934 0 : (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
935 0 :
936 : ;; Match 0 to 5.
937 : (define_predicate "const_0_to_5_operand"
938 0 : (and (match_code "const_int")
939 0 : (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
940 0 :
941 : ;; Match 0 to 7.
942 : (define_predicate "const_0_to_7_operand"
943 782743 : (and (match_code "const_int")
944 1565472 : (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
945 782743 :
946 : ;; Match 0 to 15.
947 : (define_predicate "const_0_to_15_operand"
948 79930 : (and (match_code "const_int")
949 159844 : (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
950 79930 :
951 : ;; Match 0 to 31.
952 : (define_predicate "const_0_to_31_operand"
953 54522 : (and (match_code "const_int")
954 108482 : (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
955 54522 :
956 : ;; Match 0 to 63.
957 : (define_predicate "const_0_to_63_operand"
958 26456 : (and (match_code "const_int")
959 51084 : (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
960 26456 :
961 : ;; Match 0 to 127.
962 : (define_predicate "const_0_to_127_operand"
963 10006 : (and (match_code "const_int")
964 19024 : (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
965 10006 :
966 : ;; Match 0 to 255.
967 : (define_predicate "const_0_to_255_operand"
968 8881628 : (and (match_code "const_int")
969 17735707 : (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
970 8881628 :
971 : ;; Match (0 to 255) * 8
972 : (define_predicate "const_0_to_255_mul_8_operand"
973 439874 : (match_code "const_int")
974 : {
975 439874 : unsigned HOST_WIDE_INT val = INTVAL (op);
976 439874 : return val <= 255*8 && val % 8 == 0;
977 : })
978 :
979 : ;; Match 1 to 255 except multiples of 8
980 439876 : (define_predicate "const_0_to_255_not_mul_8_operand"
981 : (match_code "const_int")
982 439876 : {
983 1265951 : unsigned HOST_WIDE_INT val = INTVAL (op);
984 826061 : return val <= 255 && val % 8 != 0;
985 : })
986 :
987 826075 : ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
988 826075 : ;; for shift & compare patterns, as shifting by 0 does not change flags).
989 : (define_predicate "const_1_to_31_operand"
990 826075 : (and (match_code "const_int")
991 871408 : (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
992 :
993 : ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
994 : ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
995 95542 : (define_predicate "const_1_to_63_operand"
996 : (and (match_code "const_int")
997 95542 : (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
998 :
999 : ;; Match 2 or 3.
1000 : (define_predicate "const_2_to_3_operand"
1001 76366 : (and (match_code "const_int")
1002 152732 : (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
1003 76366 :
1004 : ;; Match 4 to 5.
1005 : (define_predicate "const_4_to_5_operand"
1006 5514 : (and (match_code "const_int")
1007 11028 : (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
1008 5514 :
1009 : ;; Match 4 to 7.
1010 : (define_predicate "const_4_to_7_operand"
1011 982200 : (and (match_code "const_int")
1012 1964400 : (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
1013 982200 :
1014 : ;; Match 6 to 7.
1015 : (define_predicate "const_6_to_7_operand"
1016 700 : (and (match_code "const_int")
1017 1400 : (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
1018 700 :
1019 : ;; Match 8 to 9.
1020 : (define_predicate "const_8_to_9_operand"
1021 512 : (and (match_code "const_int")
1022 1024 : (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
1023 512 :
1024 : ;; Match 8 to 11.
1025 : (define_predicate "const_8_to_11_operand"
1026 35409 : (and (match_code "const_int")
1027 70818 : (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
1028 35409 :
1029 : ;; Match 8 to 15.
1030 : (define_predicate "const_8_to_15_operand"
1031 39894 : (and (match_code "const_int")
1032 79788 : (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
1033 39894 :
1034 : ;; Match 10 to 11.
1035 : (define_predicate "const_10_to_11_operand"
1036 267 : (and (match_code "const_int")
1037 534 : (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
1038 267 :
1039 : ;; Match 12 to 13.
1040 : (define_predicate "const_12_to_13_operand"
1041 266 : (and (match_code "const_int")
1042 532 : (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
1043 266 :
1044 : ;; Match 12 to 15.
1045 : (define_predicate "const_12_to_15_operand"
1046 23594 : (and (match_code "const_int")
1047 47188 : (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
1048 23594 :
1049 : ;; Match 14 to 15.
1050 : (define_predicate "const_14_to_15_operand"
1051 266 : (and (match_code "const_int")
1052 532 : (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
1053 266 :
1054 : ;; Match 16 to 19.
1055 : (define_predicate "const_16_to_19_operand"
1056 956 : (and (match_code "const_int")
1057 1912 : (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
1058 956 :
1059 : ;; Match 16 to 31.
1060 : (define_predicate "const_16_to_31_operand"
1061 10409 : (and (match_code "const_int")
1062 20818 : (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
1063 10409 :
1064 : ;; Match 20 to 23.
1065 : (define_predicate "const_20_to_23_operand"
1066 532 : (and (match_code "const_int")
1067 1064 : (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
1068 532 :
1069 : ;; Match 24 to 27.
1070 : (define_predicate "const_24_to_27_operand"
1071 532 : (and (match_code "const_int")
1072 1064 : (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
1073 532 :
1074 : ;; Match 28 to 31.
1075 : (define_predicate "const_28_to_31_operand"
1076 532 : (and (match_code "const_int")
1077 1064 : (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
1078 532 :
1079 : (define_predicate "cmpps_imm_operand"
1080 : (ior (match_operand 0 "const_0_to_7_operand")
1081 4082 : (and (match_test "TARGET_AVX")
1082 : (match_operand 0 "const_0_to_31_operand"))))
1083 60090 :
1084 : ;; True if this is a constant appropriate for an increment or decrement.
1085 100325864 : (define_predicate "incdec_operand"
1086 : (match_code "const_int")
1087 : {
1088 : /* On Pentium4, the inc and dec operations causes extra dependency on flag
1089 : registers, since carry flag is not set. */
1090 100325864 : if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
1091 : return false;
1092 2466757 : return op == const1_rtx || op == constm1_rtx;
1093 : })
1094 :
1095 : ;; True for registers, or const_int_operand, used to vec_setm expander.
1096 124291370 : (define_predicate "vec_setm_sse41_operand"
1097 : (ior (and (match_operand 0 "register_operand")
1098 224618059 : (match_test "TARGET_SSE4_1"))
1099 100325864 : (match_code "const_int")))
1100 :
1101 : (define_predicate "vec_setm_avx2_operand"
1102 : (ior (and (match_operand 0 "register_operand")
1103 1002 : (match_test "TARGET_AVX2"))
1104 0 : (match_code "const_int")))
1105 1298 :
1106 : (define_predicate "vec_setm_mmx_operand"
1107 : (ior (and (match_operand 0 "register_operand")
1108 22 : (match_test "TARGET_SSE4_1")
1109 256 : (match_test "TARGET_MMX_WITH_SSE"))
1110 256 : (match_code "const_int")))
1111 :
1112 : ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
1113 : (define_predicate "reg_or_pm1_operand"
1114 4434608 : (ior (match_operand 0 "register_operand")
1115 : (and (match_code "const_int")
1116 4434608 : (ior (match_test "op == const1_rtx")
1117 261532 : (match_test "op == constm1_rtx")))))
1118 245314 :
1119 : ;; True for registers, or (not: registers). Used to optimize 3-operand
1120 : ;; bitwise operation.
1121 : (define_predicate "regmem_or_bitnot_regmem_operand"
1122 701762 : (ior (match_operand 0 "nonimmediate_operand")
1123 : (and (match_code "not")
1124 701762 : (match_test "nonimmediate_operand (XEXP (op, 0), mode)"))))
1125 28090 :
1126 : ;; True for expressions valid for 3-operand ternlog instructions.
1127 : (define_predicate "ternlog_operand"
1128 : (and (match_code "not,and,ior,xor")
1129 2320220 : (match_test "ix86_ternlog_operand_p (op)")))
1130 250994 :
1131 64779025 : ;; True if OP is acceptable as operand of DImode shift expander.
1132 : (define_predicate "shiftdi_operand"
1133 1367232 : (if_then_else (match_test "TARGET_64BIT")
1134 3687452 : (match_operand 0 "nonimmediate_operand")
1135 2320220 : (match_operand 0 "register_operand")))
1136 1367232 :
1137 2954100 : (define_predicate "ashldi_input_operand"
1138 633880 : (if_then_else (match_test "TARGET_64BIT")
1139 633880 : (match_operand 0 "nonimmediate_operand")
1140 : (match_operand 0 "reg_or_pm1_operand")))
1141 2320220 :
1142 569581 : ;; Return true if OP is a vector load from the constant pool with just
1143 : ;; the first element nonzero.
1144 : (define_predicate "zero_extended_scalar_load_operand"
1145 : (match_code "mem")
1146 : {
1147 569581 : unsigned n_elts;
1148 569581 : op = avoid_constant_pool_reference (op);
1149 :
1150 569581 : if (!CONST_VECTOR_P (op))
1151 : return false;
1152 :
1153 83557 : n_elts = CONST_VECTOR_NUNITS (op);
1154 :
1155 179179 : for (n_elts--; n_elts > 0; n_elts--)
1156 : {
1157 128375 : rtx elt = CONST_VECTOR_ELT (op, n_elts);
1158 256750 : if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
1159 : return false;
1160 : }
1161 : return true;
1162 : })
1163 :
1164 : /* Return true if operand is a float vector constant that is all ones. */
1165 1921590 : (define_predicate "float_vector_all_ones_operand"
1166 : (match_code "const_vector,mem")
1167 569581 : {
1168 1972394 : mode = GET_MODE (op);
1169 50804 : if (!FLOAT_MODE_P (mode)
1170 13362329 : || (MEM_P (op)
1171 11537408 : && (!SYMBOL_REF_P (XEXP (op, 0))
1172 1369833 : || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))))
1173 16217026 : return false;
1174 :
1175 2955226 : if (MEM_P (op))
1176 : {
1177 1130305 : op = get_pool_constant (XEXP (op, 0));
1178 1130305 : if (!CONST_VECTOR_P (op))
1179 : return false;
1180 :
1181 1130301 : if (GET_MODE (op) != mode
1182 5466 : && INTEGRAL_MODE_P (GET_MODE (op))
1183 5466 : && op == CONSTM1_RTX (GET_MODE (op)))
1184 : return true;
1185 : }
1186 :
1187 2955222 : rtx first = XVECEXP (op, 0, 0);
1188 8560934 : for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++)
1189 : {
1190 3771988 : rtx tmp = XVECEXP (op, 0, i);
1191 3771988 : if (!rtx_equal_p (tmp, first))
1192 : return false;
1193 : }
1194 508479 : if (GET_MODE (first) == E_SFmode)
1195 : {
1196 236829 : long l;
1197 236829 : REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1198 236829 : return (l & 0xffffffff) == 0xffffffff;
1199 : }
1200 271650 : else if (GET_MODE (first) == E_DFmode)
1201 : {
1202 264754 : long l[2];
1203 264754 : REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1204 264754 : return ((l[0] & 0xffffffff) == 0xffffffff
1205 264754 : && (l[1] & 0xffffffff) == 0xffffffff);
1206 : }
1207 : else
1208 : return false;
1209 : })
1210 :
1211 : /* Return true if operand is an integral vector constant that is all ones. */
1212 54721027 : (define_predicate "vector_all_ones_operand"
1213 : (and (match_code "const_vector")
1214 68055266 : (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1215 11573254 : (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1216 991499 :
1217 16217026 : /* Return true if operand is a vector constant that is all ones. */
1218 16217026 : (define_predicate "int_float_vector_all_ones_operand"
1219 : (ior (match_operand 0 "vector_all_ones_operand")
1220 8933235 : (match_operand 0 "float_vector_all_ones_operand")
1221 0 : (match_test "op == constm1_rtx")))
1222 8933235 :
1223 16217026 : /* Return true if operand is an 128/256bit all ones vector
1224 3175 : that zero-extends to 256/512bit. */
1225 : (define_predicate "vector_all_ones_zero_extend_half_operand"
1226 11888347 : (match_code "const_vector")
1227 : {
1228 160661261 : mode = GET_MODE (op);
1229 11888347 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1230 170986496 : || (GET_MODE_SIZE (mode) != 32
1231 10025022 : && GET_MODE_SIZE (mode) != 64))
1232 : return false;
1233 :
1234 467736 : int nelts = CONST_VECTOR_NUNITS (op);
1235 540391 : for (int i = 0; i != nelts; i++)
1236 : {
1237 539441 : rtx elt = CONST_VECTOR_ELT (op, i);
1238 539441 : if (i < nelts / 2
1239 1060241 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1240 : return false;
1241 83693 : if (i >= nelts / 2
1242 102334 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1243 : return false;
1244 : }
1245 : return true;
1246 : })
1247 :
1248 : /* Return true if operand is an 128bit all ones vector
1249 162030159 : that zero extends to 512bit. */
1250 : (define_predicate "vector_all_ones_zero_extend_quarter_operand"
1251 11888347 : (match_code "const_vector")
1252 162031109 : {
1253 950 : mode = GET_MODE (op);
1254 11887397 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1255 10324285 : || GET_MODE_SIZE (mode) != 64)
1256 : return false;
1257 11887397 :
1258 167314 : int nelts = CONST_VECTOR_NUNITS (op);
1259 180957 : for (int i = 0; i != nelts; i++)
1260 : {
1261 180869 : rtx elt = CONST_VECTOR_ELT (op, i);
1262 180869 : if (i < nelts / 4
1263 358264 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1264 : return false;
1265 16283 : if (i >= nelts / 4
1266 19757 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1267 : return false;
1268 : }
1269 : return true;
1270 : })
1271 :
1272 : ; Return true when OP is operand acceptable for vector memory operand.
1273 162029209 : ; Only AVX can have misaligned memory operand.
1274 : (define_predicate "vector_memory_operand"
1275 11887397 : (and (match_operand 0 "memory_operand")
1276 163150063 : (ior (match_test "TARGET_AVX")
1277 1120854 : (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1278 :
1279 : ; Return true when OP is register_operand or vector_memory_operand.
1280 : (define_predicate "vector_operand"
1281 19320127 : (ior (match_operand 0 "register_operand")
1282 : (match_operand 0 "vector_memory_operand")))
1283 19320127 :
1284 : ; Return true when OP is register_operand, vector_memory_operand
1285 : ; or const_vector.
1286 : (define_predicate "vector_or_const_vector_operand"
1287 93848 : (ior (match_operand 0 "register_operand")
1288 : (match_operand 0 "vector_memory_operand")
1289 93848 : (match_code "const_vector")))
1290 44105 :
1291 : (define_predicate "bcst_mem_operand"
1292 : (and (match_code "vec_duplicate")
1293 14431 : (and (match_test "TARGET_AVX512F")
1294 165293936 : (ior (match_test "TARGET_AVX512VL")
1295 9034 : (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64")))
1296 150092 : (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))")
1297 13483 : (match_test "GET_MODE (XEXP (op, 0))
1298 40438 : == GET_MODE_INNER (GET_MODE (op))")
1299 165308224 : (match_test "memory_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
1300 5333 :
1301 : ; Return true when OP is bcst_mem_operand or vector_memory_operand.
1302 : (define_predicate "bcst_vector_operand"
1303 : (ior (match_operand 0 "vector_operand")
1304 5296909 : (match_operand 0 "bcst_mem_operand")))
1305 :
1306 5296909 : ;; Return true when OP is either nonimmediate operand, or any
1307 : ;; CONST_VECTOR.
1308 : (define_predicate "nonimmediate_or_const_vector_operand"
1309 : (ior (match_operand 0 "nonimmediate_operand")
1310 88134 : (match_code "const_vector")))
1311 :
1312 88134 : (define_predicate "nonimmediate_or_const_vec_dup_operand"
1313 14222 : (ior (match_operand 0 "nonimmediate_operand")
1314 58 : (match_test "const_vec_duplicate_p (op)")))
1315 58 :
1316 : ;; Return true when OP is either register operand, or any
1317 106 : ;; CONST_VECTOR.
1318 : (define_predicate "reg_or_const_vector_operand"
1319 106 : (ior (match_operand 0 "register_operand")
1320 : (match_code "const_vector")))
1321 251 :
1322 153 : ;; Return true when OP is CONST_VECTOR which can be converted to a
1323 : ;; sign extended 32-bit integer.
1324 : (define_predicate "x86_64_const_vector_operand"
1325 : (match_code "const_vector")
1326 159395 : {
1327 159395 : if (mode == VOIDmode)
1328 0 : mode = GET_MODE (op);
1329 159395 : else if (GET_MODE (op) != mode)
1330 : return false;
1331 375257 : if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1332 : return false;
1333 116376 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op, mode);
1334 116376 : return trunc_int_for_mode (val, SImode) == val;
1335 : })
1336 :
1337 : (define_predicate "nonimmediate_or_x86_64_const_vector_operand"
1338 964448 : (ior (match_operand 0 "nonimmediate_operand")
1339 : (match_operand 0 "x86_64_const_vector_operand")))
1340 159395 :
1341 1047479 : ;; Return true when OP is nonimmediate or standard SSE constant.
1342 83031 : (define_predicate "nonimmediate_or_sse_const_operand"
1343 : (ior (match_operand 0 "nonimmediate_operand")
1344 24610213 : (match_test "standard_sse_constant_p (op, mode)")))
1345 2800233 :
1346 5372 : ;; Return true if OP is a register or a zero.
1347 : (define_predicate "reg_or_0_operand"
1348 5372 : (ior (match_operand 0 "register_operand")
1349 598749 : (match_operand 0 "const0_operand")))
1350 :
1351 598749 : ; Return true when OP is a nonimmediate or zero.
1352 93900912 : (define_predicate "nonimm_or_0_operand"
1353 : (ior (match_operand 0 "nonimmediate_operand")
1354 115710892 : (match_operand 0 "const0_operand")))
1355 125902172 :
1356 : ; Return true when OP is a nonimmediate or zero or all ones.
1357 125902172 : (define_predicate "nonimm_or_0_or_1s_operand"
1358 : (ior (match_operand 0 "nonimmediate_operand")
1359 : (match_operand 0 "const0_operand")
1360 : (match_operand 0 "int_float_vector_all_ones_operand")))
1361 80649 :
1362 : ;; Return true for RTX codes that force SImode address.
1363 80649 : (define_predicate "SImode_address_operand"
1364 : (match_code "subreg,zero_extend,and"))
1365 :
1366 : ;; Return true if op is a valid address for LEA, and does not contain
1367 269702078 : ;; a segment override. Defined as a special predicate to allow
1368 : ;; mode-less const_int operands pass to address_operand.
1369 269702078 : (define_special_predicate "address_no_seg_operand"
1370 179691881 : (match_test "address_operand (op, VOIDmode)")
1371 65786845 : {
1372 66156914 : struct ix86_address parts;
1373 66156914 : int ok;
1374 370069 :
1375 65826340 : if (!CONST_INT_P (op)
1376 62900807 : && mode != VOIDmode
1377 62900807 : && GET_MODE (op) != mode)
1378 370069 : return false;
1379 370069 :
1380 65786781 : ok = ix86_decompose_address (op, &parts);
1381 65786781 : gcc_assert (ok);
1382 65786781 : return parts.seg == ADDR_SPACE_GENERIC;
1383 65786845 : })
1384 :
1385 : ;; Return true if op if a valid base register, displacement or
1386 113905036 : ;; sum of base register and displacement for VSIB addressing.
1387 : (define_predicate "vsib_address_operand"
1388 113944531 : (match_test "address_operand (op, VOIDmode)")
1389 79751 : {
1390 38317 : struct ix86_address parts;
1391 39495 : int ok;
1392 39495 : rtx disp;
1393 :
1394 39495 : ok = ix86_decompose_address (op, &parts);
1395 39495 : gcc_assert (ok);
1396 66161 : if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1397 26666 : return false;
1398 :
1399 : /* VSIB addressing doesn't support (%rip). */
1400 39475 : if (parts.disp)
1401 25616901 : {
1402 7415 : disp = parts.disp;
1403 7415 : if (GET_CODE (disp) == CONST)
1404 : {
1405 148 : disp = XEXP (disp, 0);
1406 148 : if (GET_CODE (disp) == PLUS)
1407 148 : disp = XEXP (disp, 0);
1408 148 : if (GET_CODE (disp) == UNSPEC)
1409 0 : switch (XINT (disp, 1))
1410 : {
1411 : case UNSPEC_GOTPCREL:
1412 : case UNSPEC_PCREL:
1413 : case UNSPEC_GOTNTPOFF:
1414 : return false;
1415 : }
1416 : }
1417 7415 : if (TARGET_64BIT
1418 7415 : && flag_pic
1419 0 : && (SYMBOL_REF_P (disp)
1420 0 : || LABEL_REF_P (disp)))
1421 0 : return false;
1422 : }
1423 :
1424 : return true;
1425 : })
1426 :
1427 : (define_predicate "vsib_mem_operator"
1428 40276 : (match_code "mem"))
1429 :
1430 40276 : ;; Return true if the rtx is known to be at least 32 bits aligned.
1431 : (define_predicate "aligned_operand"
1432 : (match_operand 0 "general_operand")
1433 : {
1434 25616901 : struct ix86_address parts;
1435 25616901 : int ok;
1436 :
1437 : /* Registers and immediate operands are always "aligned". */
1438 25616901 : if (!MEM_P (op))
1439 : return true;
1440 :
1441 : /* All patterns using aligned_operand on memory operands ends up
1442 : in promoting memory operand to 64bit and thus causing memory mismatch. */
1443 8109833 : if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1444 : return false;
1445 :
1446 : /* Don't even try to do any aligned optimizations with volatiles. */
1447 126871 : if (MEM_VOLATILE_P (op))
1448 : return false;
1449 :
1450 120908 : if (MEM_ALIGN (op) >= 32)
1451 : return true;
1452 :
1453 46794 : op = XEXP (op, 0);
1454 :
1455 : /* Pushes and pops are only valid on the stack pointer. */
1456 46794 : if (GET_CODE (op) == PRE_DEC
1457 46794 : || GET_CODE (op) == POST_INC)
1458 : return true;
1459 :
1460 : /* Decode the address. */
1461 46794 : ok = ix86_decompose_address (op, &parts);
1462 46794 : gcc_assert (ok);
1463 :
1464 46794 : if (parts.base && SUBREG_P (parts.base))
1465 0 : parts.base = SUBREG_REG (parts.base);
1466 46794 : if (parts.index && SUBREG_P (parts.index))
1467 0 : parts.index = SUBREG_REG (parts.index);
1468 :
1469 : /* Look for some component that isn't known to be aligned. */
1470 46794 : if (parts.index)
1471 : {
1472 3733 : if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1473 : return false;
1474 : }
1475 43061 : if (parts.base)
1476 : {
1477 36217 : if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1478 : return false;
1479 : }
1480 13249 : if (parts.disp)
1481 : {
1482 13249 : if (!CONST_INT_P (parts.disp)
1483 6503 : || (INTVAL (parts.disp) & 3))
1484 : return false;
1485 : }
1486 :
1487 : /* Didn't find one -- this must be an aligned address. */
1488 : return true;
1489 : })
1490 :
1491 : ;; Return true if OP is memory operand with a displacement.
1492 26095420 : (define_predicate "memory_displacement_operand"
1493 : (match_operand 0 "memory_operand")
1494 51712321 : {
1495 25616901 : struct ix86_address parts;
1496 0 : int ok;
1497 :
1498 0 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1499 0 : gcc_assert (ok);
1500 0 : return parts.disp != NULL_RTX;
1501 : })
1502 :
1503 : ;; Return true if OP is memory operand with a displacement only.
1504 0 : (define_predicate "memory_displacement_only_operand"
1505 : (match_operand 0 "memory_operand")
1506 0 : {
1507 0 : struct ix86_address parts;
1508 38476352 : int ok;
1509 :
1510 38476352 : if (TARGET_64BIT)
1511 38476352 : return false;
1512 :
1513 18939697 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1514 18939697 : gcc_assert (ok);
1515 :
1516 18939697 : if (parts.base || parts.index)
1517 : return false;
1518 :
1519 235513 : return parts.disp != NULL_RTX;
1520 : })
1521 :
1522 : ;; Return true if OP is memory operand that cannot be represented
1523 59663251 : ;; by the modRM array.
1524 : (define_predicate "long_memory_operand"
1525 98139603 : (and (match_operand 0 "memory_operand")
1526 38476352 : (match_test "memory_address_length (op, false)")))
1527 :
1528 : ;; Return true if OP is a comparison operator that can be issued by fcmov.
1529 : (define_predicate "fcmov_comparison_operator"
1530 69086 : (match_operand 0 "comparison_operator")
1531 : {
1532 0 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1533 69086 : enum rtx_code code = GET_CODE (op);
1534 :
1535 69086 : if (inmode == CCFPmode)
1536 8825 : code = ix86_fp_compare_code_to_integer (code);
1537 :
1538 : /* i387 supports just limited amount of conditional codes. */
1539 69086 : switch (code)
1540 : {
1541 1952 : case GEU: case LTU:
1542 1952 : if (inmode == CCCmode || inmode == CCGZmode)
1543 : return true;
1544 : /* FALLTHRU */
1545 6738 : case GTU: case LEU:
1546 6738 : if (inmode == CCmode || inmode == CCFPmode)
1547 : return true;
1548 : return false;
1549 : case ORDERED: case UNORDERED:
1550 : case EQ: case NE:
1551 : return true;
1552 : default:
1553 : return false;
1554 : }
1555 : })
1556 :
1557 : ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1558 69086 : ;; The first set are supported directly; the second set can't be done with
1559 : ;; full IEEE support, i.e. NaNs.
1560 138172 :
1561 69086 : (define_predicate "sse_comparison_operator"
1562 : (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1563 401765 : (and (match_test "TARGET_AVX")
1564 401765 : (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1565 514597 :
1566 : (define_predicate "ix86_comparison_int_operator"
1567 514597 : (match_code "ne,eq,ge,gt,le,lt"))
1568 220192 :
1569 : (define_predicate "ix86_comparison_uns_operator"
1570 220192 : (match_code "ne,eq,geu,gtu,leu,ltu"))
1571 :
1572 220192 : (define_predicate "bt_comparison_operator"
1573 220192 : (match_code "ne,eq"))
1574 220192 :
1575 220192 : (define_predicate "shr_comparison_operator"
1576 220192 : (match_code "gtu,leu"))
1577 220192 :
1578 220192 : (define_predicate "add_comparison_operator"
1579 : (match_code "geu,ltu"))
1580 :
1581 : (define_predicate "ieee_maxmin_comparison_operator"
1582 220192 : (match_code "lt,gt"))
1583 220192 :
1584 : ;; Return true if OP is a valid comparison operator in valid mode.
1585 : (define_predicate "ix86_comparison_operator"
1586 : (match_operand 0 "comparison_operator")
1587 117368 : {
1588 100907825 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1589 117368 : enum rtx_code code = GET_CODE (op);
1590 :
1591 101025193 : if (inmode == CCFPmode)
1592 6903007 : return ix86_trivial_fp_comparison_operator (op, mode);
1593 117368 :
1594 94004818 : switch (code)
1595 117368 : {
1596 72015417 : case EQ: case NE:
1597 71898049 : if (inmode == CCGZmode)
1598 0 : return false;
1599 : return true;
1600 4457784 : case GE: case LT:
1601 4457784 : if (inmode == CCmode || inmode == CCGCmode
1602 2500588 : || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode)
1603 3943118 : return true;
1604 : return false;
1605 7771017 : case GEU: case LTU:
1606 7771017 : if (inmode == CCCmode || inmode == CCGZmode)
1607 : return true;
1608 62766404 : /* FALLTHRU */
1609 10930171 : case GTU: case LEU:
1610 10930171 : if (inmode == CCmode)
1611 9685719 : return true;
1612 51669017 : return false;
1613 3470 : case ORDERED: case UNORDERED:
1614 3470 : if (inmode == CCmode)
1615 3217 : return true;
1616 51669017 : return false;
1617 51669017 : case GT: case LE:
1618 6255298 : if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1619 5488585 : return true;
1620 : return false;
1621 819930 : default:
1622 : return false;
1623 819930 : }
1624 : })
1625 819930 :
1626 819930 : ;; Return true if OP is a valid comparison operator
1627 116383405 : ;; testing carry flag to be set.
1628 : (define_predicate "ix86_carry_flag_operator"
1629 216471300 : (match_code "ltu,unlt")
1630 100907825 : {
1631 1669831 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1632 819930 : enum rtx_code code = GET_CODE (op);
1633 :
1634 849901 : if (inmode == CCFPmode)
1635 11706 : code = ix86_fp_compare_code_to_integer (code);
1636 838195 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1637 : return false;
1638 1362165 :
1639 664217 : return code == LTU;
1640 1362165 : })
1641 1362165 :
1642 1362165 : ;; Return true if OP is a valid comparison operator
1643 3702713 : ;; testing carry flag to be unset.
1644 : (define_predicate "ix86_carry_flag_unset_operator"
1645 3702713 : (match_code "geu,ge")
1646 1362165 : {
1647 1362165 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1648 851605 : enum rtx_code code = GET_CODE (op);
1649 849901 :
1650 1704 : if (inmode == CCFPmode)
1651 68 : code = ix86_fp_compare_code_to_integer (code);
1652 1636 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1653 1348 : return false;
1654 849901 :
1655 425477 : return code == GEU;
1656 1348 : })
1657 1348 :
1658 : ;; Return true if this comparison only requires testing one flag bit.
1659 2597498 : ;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
1660 : (define_predicate "ix86_trivial_fp_comparison_operator"
1661 11975403 : (if_then_else (match_test "TARGET_AVX10_2")
1662 673206 : (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
1663 1704 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
1664 1704 :
1665 1704 : (define_predicate "ix86_trivial_fp_comparison_operator_xf"
1666 102276983 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1667 :
1668 1369158 : ;; Return true if we know how to do this comparison. Others require
1669 1704 : ;; testing more than one flag bit, and we let the generic middle-end
1670 413346 : ;; code do that.
1671 412907 : (define_predicate "ix86_fp_comparison_operator"
1672 2888244 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1673 2888244 : == IX86_FPCMP_ARITH")
1674 411642 : (match_operand 0 "comparison_operator")
1675 9791251 : (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1676 411642 :
1677 9791251 : (define_predicate "ix86_fp_comparison_operator_xf"
1678 1780800 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1679 1369158 : == IX86_FPCMP_ARITH")
1680 : (match_operand 0 "comparison_operator")
1681 : (match_operand 0 "ix86_trivial_fp_comparison_operator_xf")))
1682 411642 :
1683 843883 : ;; Return true if we can perform this comparison on TImode operands.
1684 : (define_predicate "ix86_timode_comparison_operator"
1685 432241 : (if_then_else (match_test "TARGET_64BIT")
1686 : (match_operand 0 "ordered_comparison_operator")
1687 2476602 : (match_operand 0 "bt_comparison_operator")))
1688 :
1689 2476602 : ;; Return true if this is a valid second operand for a TImode comparison.
1690 : (define_predicate "ix86_timode_comparison_operand"
1691 154378 : (if_then_else (match_test "TARGET_64BIT")
1692 : (match_operand 0 "x86_64_general_operand")
1693 : (match_operand 0 "nonimmediate_operand")))
1694 :
1695 2002110 : ;; Nearly general operand, but accept any const_double, since we wish
1696 : ;; to be able to drop them into memory rather than have them get pulled
1697 517014 : ;; into registers.
1698 2519124 : (define_predicate "cmp_fp_expander_operand"
1699 : (ior (match_code "const_double")
1700 : (match_operand 0 "general_operand")))
1701 :
1702 4986592 : ;; Return true if this is a valid binary floating-point operation.
1703 : (define_predicate "binary_fp_operator"
1704 4986592 : (match_code "plus,minus,mult,div"))
1705 :
1706 4977533 : ;; Return true if this is a multiply operation.
1707 4977533 : (define_predicate "mult_operator"
1708 4977533 : (match_code "mult"))
1709 4977533 :
1710 4977533 : ;; Return true if this is a division operation.
1711 : (define_predicate "div_operator"
1712 : (match_code "div"))
1713 :
1714 4977533 : ;; Return true if this is an and, ior or xor operation.
1715 4977533 : (define_predicate "logic_operator"
1716 : (match_code "and,ior,xor"))
1717 :
1718 : ;; Return true if this is an and operation.
1719 17196202 : (define_predicate "and_operator"
1720 : (match_code "and"))
1721 17196202 :
1722 3538624 : ;; Return true if this is a plus, minus, and, ior or xor operation.
1723 : (define_predicate "plusminuslogic_operator"
1724 : (match_code "plus,minus,and,ior,xor"))
1725 :
1726 2753651 : ;; Return true for ARITHMETIC_P.
1727 : (define_predicate "arith_or_logical_operator"
1728 2753651 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1729 927321 : mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1730 :
1731 : ;; Return true for COMMUTATIVE_P.
1732 : (define_predicate "commutative_operator"
1733 0 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1734 :
1735 0 : ;; Return true if OP is a binary operator that can be promoted to wider mode.
1736 : (define_predicate "promotable_binary_operator"
1737 0 : (ior (match_code "plus,minus,and,ior,xor,ashift")
1738 0 : (and (match_code "mult")
1739 25481878 : (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1740 0 :
1741 : (define_predicate "compare_operator"
1742 : (match_code "compare"))
1743 :
1744 7538490 : (define_predicate "extract_high_operator"
1745 0 : (match_code "zero_extract,sign_extract,ashiftrt,lshiftrt")
1746 7538490 : {
1747 0 : return (const8_operand (XEXP (op, 1), VOIDmode)
1748 150041 : && (BINARY_P (op) || const8_operand (XEXP (op, 2), VOIDmode)));
1749 100 : })
1750 :
1751 150141 : ;; Return true if OP is a memory operand, aligned to
1752 0 : ;; less than its natural alignment.
1753 : (define_predicate "misaligned_operand"
1754 150041 : (and (match_code "mem")
1755 6312400 : (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1756 1592069 :
1757 150041 : ;; Return true if OP is a parallel for an mov{d,q,dqa,ps,pd} vec_select,
1758 523966 : ;; where one of the two operands of the vec_concat is const0_operand.
1759 150041 : (define_predicate "movq_parallel"
1760 1953549 : (match_code "parallel")
1761 519960 : {
1762 1803508 : unsigned nelt = XVECLEN (op, 0);
1763 1803508 : unsigned nelt2 = nelt >> 1;
1764 1953549 : unsigned i;
1765 150041 :
1766 1339775 : if (nelt < 2)
1767 : return false;
1768 :
1769 519960 : /* Validate that all of the elements are constants,
1770 519960 : lower halves of permute are lower halves of the first operand,
1771 : upper halves of permute come from any of the second operand. */
1772 15390906 : for (i = 0; i < nelt; ++i)
1773 : {
1774 6388327 : rtx er = XVECEXP (op, 0, i);
1775 2080780 : unsigned HOST_WIDE_INT ei;
1776 4307547 :
1777 2080780 : if (!CONST_INT_P (er))
1778 4307547 : return false;
1779 6388327 : ei = INTVAL (er);
1780 2080780 : if (i < nelt2 && ei != i)
1781 4307547 : return false;
1782 899220 : if (i >= nelt2 && (ei < nelt || ei >= nelt << 1))
1783 4307547 : return false;
1784 4307547 : }
1785 4307547 :
1786 4307547 : return true;
1787 4307547 : })
1788 4307547 :
1789 4307547 : ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1790 5591095 : (define_predicate "vzeroall_operation"
1791 4307547 : (match_code "parallel")
1792 6874643 : {
1793 1283567 : unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1794 0 :
1795 4001 : if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1796 4307547 : return false;
1797 4307547 :
1798 71866 : for (i = 0; i < nregs; i++)
1799 : {
1800 63864 : rtx elt = XVECEXP (op, 0, i+1);
1801 :
1802 4371411 : if (GET_CODE (elt) != SET
1803 4371411 : || GET_CODE (SET_DEST (elt)) != REG
1804 63864 : || GET_MODE (SET_DEST (elt)) != V8SImode
1805 63864 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
1806 127728 : || SET_SRC (elt) != CONST0_RTX (V8SImode))
1807 972641 : return false;
1808 : }
1809 972641 : return true;
1810 : })
1811 330566 :
1812 330566 : ;; return true if OP is a vzeroall pattern.
1813 334567 : (define_predicate "vzeroall_pattern"
1814 330566 : (and (match_code "parallel")
1815 338568 : (match_code "unspec_volatile" "a")
1816 4117 : (match_test "XINT (XVECEXP (op, 0, 0), 1) == UNSPECV_VZEROALL")))
1817 0 :
1818 330566 : ;; return true if OP is a vzeroupper pattern.
1819 330566 : (define_predicate "vzeroupper_pattern"
1820 330566 : (and (match_code "parallel")
1821 4178198 : (match_code "unspec" "b")
1822 4613 : (match_test "XINT (XVECEXP (op, 0, 1), 1) == UNSPEC_CALLEE_ABI")
1823 4178198 : (match_test "INTVAL (XVECEXP (XVECEXP (op, 0, 1), 0, 0)) == ABI_VZEROUPPER")))
1824 0 :
1825 330566 : ;; Return true if OP is an addsub vec_merge operation
1826 : (define_predicate "addsub_vm_operator"
1827 : (match_code "vec_merge")
1828 8463 : {
1829 25490341 : rtx op0, op1;
1830 8463 : int swapped;
1831 25481878 : HOST_WIDE_INT mask;
1832 8463 : int nunits, elt;
1833 :
1834 8463 : op0 = XEXP (op, 0);
1835 8463 : op1 = XEXP (op, 1);
1836 :
1837 : /* Sanity check. */
1838 8463 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1839 : swapped = 0;
1840 4318 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1841 : swapped = 1;
1842 : else
1843 0 : gcc_unreachable ();
1844 :
1845 8463 : mask = INTVAL (XEXP (op, 2));
1846 8463 : nunits = GET_MODE_NUNITS (mode);
1847 :
1848 32713 : for (elt = 0; elt < nunits; elt++)
1849 : {
1850 : /* bit clear: take from op0, set: take from op1 */
1851 24496 : int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1852 :
1853 24496 : if (bit != ((elt & 1) ^ swapped))
1854 : return false;
1855 : }
1856 :
1857 : return true;
1858 : })
1859 :
1860 : ;; Return true if OP is an addsub vec_select/vec_concat operation
1861 8463 : (define_predicate "addsub_vs_operator"
1862 : (and (match_code "vec_select")
1863 8463 : (match_code "vec_concat" "0"))
1864 16680 : {
1865 8217 : rtx op0, op1;
1866 0 : bool swapped;
1867 0 : int nunits, elt;
1868 :
1869 0 : op0 = XEXP (XEXP (op, 0), 0);
1870 0 : op1 = XEXP (XEXP (op, 0), 1);
1871 :
1872 : /* Sanity check. */
1873 0 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1874 : swapped = false;
1875 0 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1876 : swapped = true;
1877 : else
1878 0 : gcc_unreachable ();
1879 :
1880 0 : nunits = GET_MODE_NUNITS (mode);
1881 0 : if (XVECLEN (XEXP (op, 1), 0) != nunits)
1882 : return false;
1883 :
1884 : /* We already checked that permutation is suitable for addsub,
1885 : so only look at the first element of the parallel. */
1886 0 : elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1887 :
1888 0 : return elt == (swapped ? nunits : 0);
1889 : })
1890 :
1891 : ;; Return true if OP is a parallel for an addsub vec_select.
1892 0 : (define_predicate "addsub_vs_parallel"
1893 : (and (match_code "parallel")
1894 0 : (match_code "const_int" "a"))
1895 0 : {
1896 0 : int nelt = XVECLEN (op, 0);
1897 479 : int elt, i;
1898 :
1899 479 : if (nelt < 2)
1900 479 : return false;
1901 :
1902 : /* Check that the permutation is suitable for addsub.
1903 : For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1904 479 : elt = INTVAL (XVECEXP (op, 0, 0));
1905 479 : if (elt == 0)
1906 : {
1907 447 : for (i = 1; i < nelt; ++i)
1908 439 : if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1909 : return false;
1910 : }
1911 40 : else if (elt == nelt)
1912 : {
1913 0 : for (i = 1; i < nelt; ++i)
1914 0 : if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1915 : return false;
1916 : }
1917 : else
1918 : return false;
1919 :
1920 : return true;
1921 : })
1922 :
1923 : ;; Return true if OP is a constant pool in perm{w,d,b} which contains index
1924 479 : ;; match pmov{dw,wb,qd}.
1925 : (define_predicate "permvar_truncate_operand"
1926 479 : (match_code "mem")
1927 958 : {
1928 0 : int nelt = GET_MODE_NUNITS (mode);
1929 16 : int perm[128];
1930 16 : int id;
1931 :
1932 32 : if (!INTEGRAL_MODE_P (mode) || !VECTOR_MODE_P (mode))
1933 : return false;
1934 :
1935 16 : if (nelt < 2)
1936 : return false;
1937 :
1938 16 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1939 : return false;
1940 :
1941 16 : id = exact_log2 (nelt);
1942 :
1943 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
1944 : For example V16HImode to V8HImode
1945 : { 0 2 4 6 8 10 12 14 * * * * * * * * }. */
1946 232 : for (int i = 0; i != nelt / 2; i++)
1947 216 : if ((perm[i] & ((1 << id) - 1)) != i * 2)
1948 : return false;
1949 :
1950 : return true;
1951 : })
1952 :
1953 : ;; Return true if OP is a constant pool in shufb which contains index
1954 49 : ;; match pmovdw.
1955 : (define_predicate "pshufb_truncv4siv4hi_operand"
1956 16 : (match_code "mem")
1957 65 : {
1958 16 : int perm[128];
1959 :
1960 8 : if (mode != E_V16QImode)
1961 : return false;
1962 8 :
1963 8 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1964 : return false;
1965 :
1966 : /* Check that the permutation is suitable for pmovdw.
1967 : For example V4SImode to V4HImode
1968 : { 0 1 4 5 8 9 12 13 * * * * * * * * }.
1969 : index = i % 2 + (i / 2) * 4. */
1970 58 : for (int i = 0; i != 8; i++)
1971 : {
1972 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
1973 52 : if (perm[i] & 128)
1974 : return false;
1975 :
1976 52 : if ((perm[i] & 15) != ((i & 1) + (i & 0xFE) * 2))
1977 : return false;
1978 : }
1979 :
1980 : return true;
1981 : })
1982 :
1983 : ;; Return true if OP is a constant pool in shufb which contains index
1984 11 : ;; match pmovdw.
1985 : (define_predicate "pshufb_truncv8hiv8qi_operand"
1986 8 : (match_code "mem")
1987 17 : {
1988 6 : int perm[128];
1989 :
1990 11 : if (mode != E_V16QImode)
1991 : return false;
1992 11 :
1993 11 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1994 : return false;
1995 :
1996 : /* Check that the permutation is suitable for pmovwb.
1997 : For example V16QImode to V8QImode
1998 : { 0 2 4 6 8 10 12 14 * * * * * * * * }.
1999 : index = i % 2 + (i / 2) * 4. */
2000 57 : for (int i = 0; i != 8; i++)
2001 : {
2002 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
2003 52 : if (perm[i] & 128)
2004 : return false;
2005 :
2006 52 : if ((perm[i] & 15) != i * 2)
2007 : return false;
2008 : }
2009 :
2010 : return true;
2011 : })
2012 :
2013 : ;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select,
2014 14 : ;; where one of the two operands of the vec_concat is const0_operand.
2015 : (define_predicate "pmovzx_parallel"
2016 11 : (and (match_code "parallel")
2017 19 : (match_code "const_int" "a"))
2018 5 : {
2019 1354526 : int nelt = XVECLEN (op, 0);
2020 1354526 : int elt, i;
2021 :
2022 1354526 : if (nelt < 2)
2023 : return false;
2024 :
2025 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
2026 : For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */
2027 1354524 : elt = INTVAL (XVECEXP (op, 0, 0));
2028 1354524 : if (elt == 0)
2029 : {
2030 3146902 : for (i = 1; i < nelt; ++i)
2031 2702574 : if ((i & 1) != 0)
2032 : {
2033 1706207 : if (INTVAL (XVECEXP (op, 0, i)) < nelt)
2034 : return false;
2035 : }
2036 996367 : else if (INTVAL (XVECEXP (op, 0, i)) != i / 2)
2037 : return false;
2038 : }
2039 : else
2040 : return false;
2041 :
2042 : return true;
2043 : })
2044 :
2045 : ;; Return true if OP is a const vector with duplicate value.
2046 1354526 : (define_predicate "const_vector_duplicate_operand"
2047 : (match_code "const_vector")
2048 1354526 : {
2049 2709052 : rtx elt = XVECEXP (op, 0, 0);
2050 0 : int i, nelt = XVECLEN (op, 0);
2051 :
2052 96 : for (i = 1; i < nelt; ++i)
2053 93 : if (!rtx_equal_p (elt, XVECEXP (op, 0, i)))
2054 3 : return false;
2055 : return true;
2056 : })
2057 :
2058 : ;; Return true if OP is a parallel for a vbroadcast permute.
2059 3 : (define_predicate "avx_vbroadcast_operand"
2060 : (and (match_code "parallel")
2061 3 : (match_code "const_int" "a"))
2062 6 : {
2063 3 : rtx elt = XVECEXP (op, 0, 0);
2064 419355 : int i, nelt = XVECLEN (op, 0);
2065 :
2066 : /* Don't bother checking there are the right number of operands,
2067 419355 : merely that they're all identical. */
2068 522150 : for (i = 1; i < nelt; ++i)
2069 275815 : if (XVECEXP (op, 0, i) != elt)
2070 : return false;
2071 : return true;
2072 : })
2073 :
2074 : ;; Return true if OP is a parallel for a vbroadcastf128 permute.
2075 419355 : (define_predicate "avx_vbroadcast128_operand"
2076 : (and (match_code "parallel")
2077 419355 : (match_code "const_int" "a"))
2078 838710 : {
2079 0 : int i, nelt = XVECLEN (op, 0);
2080 1272136 : int half = nelt / 2;
2081 :
2082 2016771 : for (i = 0; i < nelt; ++i)
2083 1272136 : {
2084 2016618 : int index = INTVAL (XVECEXP (op, 0, i));
2085 2016618 : if ((i < half && index != i)
2086 846026 : || (i >= half && index != (i - half)))
2087 : return false;
2088 : }
2089 :
2090 : return true;
2091 : })
2092 :
2093 : ;; Return true if OP is a parallel for a palignr permute.
2094 1272136 : (define_predicate "palignr_operand"
2095 : (and (match_code "parallel")
2096 1272136 : (match_code "const_int" "a"))
2097 2544272 : {
2098 0 : int elt = INTVAL (XVECEXP (op, 0, 0));
2099 27070 : int i, nelt = XVECLEN (op, 0);
2100 :
2101 : /* Check that an order in the permutation is suitable for palignr.
2102 27070 : For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
2103 62336 : for (i = 1; i < nelt; ++i)
2104 58543 : if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
2105 : return false;
2106 : return true;
2107 : })
2108 :
2109 : ;; Return true if OP is a proper third operand to vpblendw256.
2110 27070 : (define_predicate "avx2_pblendw_operand"
2111 : (match_code "const_int")
2112 27070 : {
2113 54140 : HOST_WIDE_INT val = INTVAL (op);
2114 0 : HOST_WIDE_INT low = val & 0xff;
2115 7063 : return val == ((low << 8) | low);
2116 : })
2117 :
2118 7063 : ;; Return true if OP is vector_operand or CONST_VECTOR.
2119 7063 : (define_predicate "general_vector_operand"
2120 : (ior (match_operand 0 "vector_operand")
2121 7063 : (match_code "const_vector")))
2122 7063 :
2123 : ;; Return true if OP is either -1 constant or stored in register.
2124 : (define_predicate "register_or_constm1_operand"
2125 : (ior (match_operand 0 "register_operand")
2126 12810 : (and (match_code "const_int")
2127 0 : (match_test "op == constm1_rtx"))))
2128 12810 :
2129 2413 : ;; Return true if the vector ends with between 12 and 18 register saves using
2130 : ;; RAX as the base address.
2131 : (define_predicate "save_multiple"
2132 223299 : (match_code "parallel")
2133 1324 : {
2134 223299 : const unsigned len = XVECLEN (op, 0);
2135 1324 : unsigned i;
2136 :
2137 : /* Starting from end of vector, count register saves. */
2138 316008 : for (i = 0; i < len; ++i)
2139 : {
2140 316008 : rtx src, dest, addr;
2141 316008 : rtx e = XVECEXP (op, 0, len - 1 - i);
2142 :
2143 316008 : if (GET_CODE (e) != SET)
2144 : break;
2145 :
2146 308963 : src = SET_SRC (e);
2147 308963 : dest = SET_DEST (e);
2148 :
2149 308963 : if (!REG_P (src) || !MEM_P (dest))
2150 : break;
2151 :
2152 92709 : addr = XEXP (dest, 0);
2153 :
2154 : /* Good if dest address is in RAX. */
2155 92709 : if (REG_P (addr) && REGNO (addr) == AX_REG)
2156 4202 : continue;
2157 :
2158 : /* Good if dest address is offset of RAX. */
2159 177014 : if (GET_CODE (addr) == PLUS
2160 88507 : && REG_P (XEXP (addr, 0))
2161 177014 : && REGNO (XEXP (addr, 0)) == AX_REG)
2162 88507 : continue;
2163 :
2164 : break;
2165 : }
2166 223299 : return (i >= 12 && i <= 18);
2167 : })
2168 :
2169 :
2170 223299 : ;; Return true if the vector ends with between 12 and 18 register loads using
2171 : ;; RSI as the base address.
2172 446598 : (define_predicate "restore_multiple"
2173 223299 : (match_code "parallel")
2174 0 : {
2175 7734687 : const unsigned len = XVECLEN (op, 0);
2176 7734687 : unsigned i;
2177 :
2178 7734687 : /* Starting from end of vector, count register restores. */
2179 7841015 : for (i = 0; i < len; ++i)
2180 : {
2181 7841015 : rtx src, dest, addr;
2182 7841015 : rtx e = XVECEXP (op, 0, len - 1 - i);
2183 :
2184 7841015 : if (GET_CODE (e) != SET)
2185 : break;
2186 :
2187 4374431 : src = SET_SRC (e);
2188 4374431 : dest = SET_DEST (e);
2189 :
2190 4374431 : if (!MEM_P (src) || !REG_P (dest))
2191 : break;
2192 :
2193 1296717 : addr = XEXP (src, 0);
2194 :
2195 : /* Good if src address is in RSI. */
2196 1296717 : if (REG_P (addr) && REGNO (addr) == SI_REG)
2197 5129 : continue;
2198 :
2199 : /* Good if src address is offset of RSI. */
2200 1392787 : if (GET_CODE (addr) == PLUS
2201 870195 : && REG_P (XEXP (addr, 0))
2202 2098364 : && REGNO (XEXP (addr, 0)) == SI_REG)
2203 101199 : continue;
2204 :
2205 : break;
2206 : }
2207 7734687 : return (i >= 12 && i <= 18);
2208 : })
2209 :
2210 : ;; Keylocker specific predicates
2211 7734687 : (define_predicate "encodekey128_operation"
2212 : (match_code "parallel")
2213 15469374 : {
2214 7734687 : unsigned i;
2215 0 : rtx elt;
2216 :
2217 108 : if (XVECLEN (op, 0) != 8)
2218 : return false;
2219 108 :
2220 392 : for(i = 0; i < 3; i++)
2221 : {
2222 294 : elt = XVECEXP (op, 0, i + 1);
2223 294 : if (GET_CODE (elt) != SET
2224 294 : || GET_CODE (SET_DEST (elt)) != REG
2225 294 : || GET_MODE (SET_DEST (elt)) != V2DImode
2226 294 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2227 294 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2228 294 : || GET_MODE (SET_SRC (elt)) != V2DImode
2229 294 : || XVECLEN(SET_SRC (elt), 0) != 1
2230 588 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2231 : return false;
2232 : }
2233 :
2234 392 : for(i = 4; i < 7; i++)
2235 : {
2236 294 : elt = XVECEXP (op, 0, i);
2237 294 : if (GET_CODE (elt) != CLOBBER
2238 294 : || GET_MODE (elt) != VOIDmode
2239 294 : || GET_CODE (XEXP (elt, 0)) != REG
2240 294 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2241 588 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2242 : return false;
2243 : }
2244 :
2245 98 : elt = XVECEXP (op, 0, 7);
2246 98 : if (GET_CODE (elt) != CLOBBER
2247 98 : || GET_MODE (elt) != VOIDmode
2248 98 : || GET_CODE (XEXP (elt, 0)) != REG
2249 98 : || GET_MODE (XEXP (elt, 0)) != CCmode
2250 196 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2251 : return false;
2252 : return true;
2253 : })
2254 :
2255 : (define_predicate "encodekey256_operation"
2256 108 : (match_code "parallel")
2257 : {
2258 337 : unsigned i;
2259 108 : rtx elt;
2260 0 :
2261 121 : if (XVECLEN (op, 0) != 9)
2262 : return false;
2263 :
2264 121 : elt = SET_SRC (XVECEXP (op, 0, 0));
2265 112 : elt = XVECEXP (elt, 0, 2);
2266 112 : if (!REG_P (elt)
2267 112 : || REGNO(elt) != GET_SSE_REGNO (1))
2268 : return false;
2269 :
2270 560 : for(i = 0; i < 4; i++)
2271 : {
2272 448 : elt = XVECEXP (op, 0, i + 1);
2273 448 : if (GET_CODE (elt) != SET
2274 448 : || GET_CODE (SET_DEST (elt)) != REG
2275 448 : || GET_MODE (SET_DEST (elt)) != V2DImode
2276 448 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2277 448 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2278 448 : || GET_MODE (SET_SRC (elt)) != V2DImode
2279 448 : || XVECLEN(SET_SRC (elt), 0) != 1
2280 896 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2281 : return false;
2282 : }
2283 :
2284 448 : for(i = 4; i < 7; i++)
2285 : {
2286 336 : elt = XVECEXP (op, 0, i + 1);
2287 336 : if (GET_CODE (elt) != CLOBBER
2288 336 : || GET_MODE (elt) != VOIDmode
2289 336 : || GET_CODE (XEXP (elt, 0)) != REG
2290 336 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2291 672 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2292 : return false;
2293 : }
2294 :
2295 112 : elt = XVECEXP (op, 0, 8);
2296 112 : if (GET_CODE (elt) != CLOBBER
2297 112 : || GET_MODE (elt) != VOIDmode
2298 112 : || GET_CODE (XEXP (elt, 0)) != REG
2299 112 : || GET_MODE (XEXP (elt, 0)) != CCmode
2300 224 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2301 : return false;
2302 : return true;
2303 : })
2304 :
2305 :
2306 121 : (define_predicate "aeswidekl_operation"
2307 : (match_code "parallel")
2308 242 : {
2309 121 : unsigned i;
2310 0 : rtx elt;
2311 :
2312 5796 : for (i = 0; i < 8; i++)
2313 : {
2314 660 : elt = XVECEXP (op, 0, i + 1);
2315 5168 : if (GET_CODE (elt) != SET
2316 5168 : || GET_CODE (SET_DEST (elt)) != REG
2317 5168 : || GET_MODE (SET_DEST (elt)) != V2DImode
2318 5168 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2319 5168 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2320 5168 : || GET_MODE (SET_SRC (elt)) != V2DImode
2321 5168 : || XVECLEN (SET_SRC (elt), 0) != 1
2322 5168 : || !REG_P (XVECEXP (SET_SRC (elt), 0, 0))
2323 10304 : || REGNO (XVECEXP (SET_SRC (elt), 0, 0)) != GET_SSE_REGNO (i))
2324 : return false;
2325 : }
2326 : return true;
2327 : })
2328 :
2329 : ;; Return true if OP is a memory operand that can be also used in APX
2330 660 : ;; EVEX-encoded patterns (i.e. APX NDD/NF) with immediate operand. With
2331 : ;; non-default address space, segment register or address size prefix,
2332 1320 : ;; APX EVEX-encoded instruction length can exceed the 15 byte size limit.
2333 660 : (define_predicate "apx_evex_memory_operand"
2334 0 : (match_operand 0 "memory_operand")
2335 : {
2336 : /* OK if immediate operand size < 4 bytes. */
2337 1686 : if (GET_MODE_SIZE (mode) < 4)
2338 1686 : return true;
2339 :
2340 1527 : bool default_addr = ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (op));
2341 1695 : bool address_size_prefix = TARGET_X32 && Pmode == SImode;
2342 :
2343 1527 : struct ix86_address parts;
2344 1527 : int ok;
2345 :
2346 1527 : op = XEXP (op, 0);
2347 1527 : ok = ix86_decompose_address (op, &parts);
2348 1527 : gcc_assert (ok);
2349 :
2350 1527 : if (default_addr)
2351 : {
2352 : /* Default address space. */
2353 :
2354 : /* Not OK with address size prefix, index register and disp. */
2355 691 : if (address_size_prefix
2356 168 : && parts.index
2357 42 : && parts.disp
2358 42 : && parts.disp != const0_rtx)
2359 : return false;
2360 : }
2361 : else
2362 : {
2363 : /* Non-default address space. */
2364 :
2365 : /* Not OK without base register. */
2366 836 : if (!parts.base)
2367 : return false;
2368 :
2369 : /* Not OK with disp and address size prefix. */
2370 668 : if (address_size_prefix && parts.disp)
2371 : return false;
2372 : }
2373 :
2374 : return true;
2375 : })
2376 :
2377 : ;; Return true if OP is a memory operand which can be used in APX EVEX-encoded
2378 1783 : ;; ADD patterns (i.e. APX NDD/NF) for with register source operand.
2379 : ;; UNSPEC_GOTNTPOFF memory operand is allowed with APX EVEX-encoded ADD only if
2380 3469 : ;; R_X86_64_CODE_6_GOTTPOFF works.
2381 1686 : (define_predicate "apx_evex_add_memory_operand"
2382 : (match_operand 0 "memory_operand")
2383 : {
2384 : /* OK if "add %reg1, name@gottpoff(%rip), %reg2" or
2385 : "{nf} add name@gottpoff(%rip), %reg1" are supported. */
2386 : if (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF)
2387 : return true;
2388 :
2389 : op = XEXP (op, 0);
2390 :
2391 : /* Disallow APX EVEX-encoded ADD with UNSPEC_GOTNTPOFF. */
2392 : if (GET_CODE (op) == CONST
2393 : && GET_CODE (XEXP (op, 0)) == UNSPEC
2394 : && XINT (XEXP (op, 0), 1) == UNSPEC_GOTNTPOFF)
2395 : return false;
2396 :
2397 : return true;
2398 : })
2399 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2400 : /* (content generated from coverage data) */
2401 841 : /* BEGIN: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2402 : /* ... */
2403 841 : /* ... */
2404 841 : /* ... */
2405 : /* END: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2406 : /* ... */
2407 : /* ... */
2408 999734069 : /* BEGIN: function "_Z19lookup_constraint_1PKc" */
2409 : /* ... */
2410 999734069 : /* ... */
2411 : /* ... */
2412 : /* ... */
2413 : /* ... */
2414 0 : /* ... */
2415 0 : /* ... */
2416 0 : /* ... */
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2418 0 : /* ... */
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2424 8263263 : /* ... */
2425 : /* ... */
2426 136199557 : /* ... */
2427 : /* ... */
2428 138501 : /* ... */
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2430 1701121 : /* ... */
2431 : /* ... */
2432 1424384 : /* ... */
2433 : /* ... */
2434 56526211 : /* ... */
2435 : /* ... */
2436 51603321 : /* ... */
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2438 101713869 : /* ... */
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2514 1345530 : /* ... */
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2548 8426733 : /* ... */
2549 8426733 : /* ... */
2550 : /* ... */
2551 : /* ... */
2552 1110922 : /* ... */
2553 : /* ... */
2554 0 : /* ... */
2555 : /* ... */
2556 0 : /* ... */
2557 : /* ... */
2558 0 : /* ... */
2559 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2560 0 : /* (content generated from coverage data) */
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2563 : /* ... */
2564 221566 : /* ... */
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2566 8977 : /* ... */
2567 : /* ... */
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2570 155606 : /* ... */
2571 : /* ... */
2572 268993 : /* ... */
2573 : /* ... */
2574 3386 : /* ... */
2575 : /* ... */
2576 0 : /* ... */
2577 : /* ... */
2578 0 : /* ... */
2579 0 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2580 0 : /* (content generated from coverage data) */
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2603 0 : /* ... */
2604 0 : /* ... */
2605 0 : /* ... */
2606 : /* ... */
2607 : /* ... */
2608 1337 : /* ... */
2609 : /* END: function "_Z19lookup_constraint_1PKc" */
2610 : /* ... */
2611 : /* ... */
2612 : /* ... */
2613 : /* ... */
2614 : /* ... */
2615 : /* ... */
2616 : /* ... */
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2672 : /* ... */
2673 : /* ... */
2674 : /* ... */
2675 : /* ... */
2676 : /* ... */
2677 : /* ... */
2678 : /* ... */
2679 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2680 : /* (content generated from coverage data) */
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2696 : /* ... */
2697 : /* ... */
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2699 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2715 : /* ... */
2716 : /* ... */
2717 : /* ... */
2718 : /* ... */
2719 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2720 : /* (content generated from coverage data) */
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2736 : /* ... */
2737 : /* ... */
2738 : /* ... */
2739 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2740 : /* (content generated from coverage data) */
2741 : /* ... */
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2755 : /* ... */
2756 : /* ... */
2757 : /* ... */
2758 : /* ... */
2759 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2760 : /* (content generated from coverage data) */
2761 : /* ... */
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2894 241545113 : /* ... */
2895 1504625285 : /* ... */
2896 14373 : /* ... */
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2898 1290163 : /* ... */
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2908 107907 : /* ... */
2909 6132959 : /* ... */
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2911 : /* ... */
2912 : /* ... */
2913 : /* END: function "_Z26reg_class_for_constraint_114constraint_num" */
2914 : /* ... */
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2975 : /* ... */
2976 : /* ... */
2977 7217980 : /* END: function "_Z32insn_const_int_ok_for_constraintl14constraint_num" */
2978 : /* ... */
2979 7217980 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2980 : /* (content generated from coverage data) */
2981 1338098 : /* ... */
2982 1338098 : /* ... */
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