Line data Source code
1 : ;; Predicate definitions for IA-32 and x86-64.
2 : ;; Copyright (C) 2004-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;; Return true if OP is either a i387 or SSE fp register.
21 : (define_predicate "any_fp_register_operand"
22 : (and (match_code "reg")
23 133386050 : (match_test "ANY_FP_REGNO_P (REGNO (op))")))
24 40558 :
25 : ;; Return true if OP is an i387 fp register.
26 : (define_predicate "fp_register_operand"
27 : (and (match_code "reg")
28 1542947 : (match_test "STACK_REGNO_P (REGNO (op))")))
29 1454571 :
30 439145303 : ;; True if the operand is a GENERAL class register.
31 : (define_predicate "general_reg_operand"
32 : (and (match_code "reg")
33 274382192 : (match_test "GENERAL_REGNO_P (REGNO (op))")))
34 206026475 :
35 457186403 : ;; True if the operand is an INDEX class register.
36 : (define_predicate "index_reg_operand"
37 : (and (match_code "reg")
38 668515 : (match_test "INDEX_REGNO_P (REGNO (op))")))
39 668440 :
40 669215 : ;; True if the operand is a nonimmediate operand with GENERAL class register.
41 : (define_predicate "nonimmediate_gr_operand"
42 : (if_then_else (match_code "reg")
43 57022363 : (match_test "GENERAL_REGNO_P (REGNO (op))")
44 63305694 : (match_operand 0 "nonimmediate_operand")))
45 79244857 :
46 : ;; True if the operand is a general operand with GENERAL class register.
47 : (define_predicate "general_gr_operand"
48 92477739 : (if_then_else (match_code "reg")
49 40254619 : (match_test "GENERAL_REGNO_P (REGNO (op))")
50 117284578 : (match_operand 0 "general_operand")))
51 :
52 : ;; True if the operand is an MMX register.
53 : (define_predicate "mmx_reg_operand"
54 39877714 : (and (match_code "reg")
55 192 : (match_test "MMX_REGNO_P (REGNO (op))")))
56 39877714 :
57 : ;; Match register operands, but include memory operands for
58 : ;; !TARGET_MMX_WITH_SSE.
59 : (define_predicate "register_mmxmem_operand"
60 633653 : (ior (match_operand 0 "register_operand")
61 12 : (and (not (match_test "TARGET_MMX_WITH_SSE"))
62 633653 : (match_operand 0 "memory_operand"))))
63 :
64 : ;; True if the operand is an SSE register.
65 160309236 : (define_predicate "sse_reg_operand"
66 : (and (match_code "reg")
67 160309236 : (match_test "SSE_REGNO_P (REGNO (op))")))
68 1727449 :
69 : ;; Return true if op is a QImode register.
70 : (define_predicate "any_QIreg_operand"
71 : (and (match_code "reg")
72 8105246 : (match_test "ANY_QI_REGNO_P (REGNO (op))")))
73 3800448 :
74 9665210 : ;; Return true if op is one of QImode registers: %[abcd][hl].
75 : (define_predicate "QIreg_operand"
76 : (and (match_code "reg")
77 2289986 : (match_test "QI_REGNO_P (REGNO (op))")))
78 2161952 :
79 6092482 : ;; Return true if op is a QImode register operand other than %[abcd][hl].
80 : (define_predicate "ext_QIreg_operand"
81 3288844 : (and (match_test "TARGET_64BIT")
82 3289147 : (match_code "reg")
83 954614 : (not (match_test "QI_REGNO_P (REGNO (op))"))))
84 3549672 :
85 : ;; Return true if op is the AX register.
86 : (define_predicate "ax_reg_operand"
87 : (and (match_code "reg")
88 22990573 : (match_test "REGNO (op) == AX_REG")))
89 0 :
90 115872891 : ;; Return true if op is the flags register.
91 : (define_special_predicate "flags_reg_operand"
92 : (and (match_code "reg")
93 114874711 : (match_test "REGNO (op) == FLAGS_REG")))
94 :
95 41366108 : ;; True if the operand is a MASK register.
96 : (define_predicate "mask_reg_operand"
97 9760177 : (and (match_code "reg")
98 4548 : (match_test "MASK_REGNO_P (REGNO (op))")))
99 9764725 :
100 : ;; Return true if op is the block scale register.
101 : (define_special_predicate "bsr0_operand"
102 : (and (match_code "reg")
103 869 : (match_test "REGNO (op) == BSR0_REG")))
104 :
105 291 : ;; Match a DI, SI or HImode register operand.
106 : (define_special_predicate "int248_register_operand"
107 351596 : (and (match_operand 0 "register_operand")
108 591915 : (ior (and (match_test "TARGET_64BIT")
109 351596 : (match_test "GET_MODE (op) == DImode"))
110 262471 : (match_test "GET_MODE (op) == SImode")
111 351596 : (match_test "GET_MODE (op) == HImode"))))
112 :
113 : ;; Match a DI, SI, HI or QImode nonimmediate_operand.
114 : (define_special_predicate "int_nonimmediate_operand"
115 376308 : (and (match_operand 0 "nonimmediate_operand")
116 439542 : (ior (and (match_test "TARGET_64BIT")
117 376308 : (match_test "GET_MODE (op) == DImode"))
118 169887 : (match_test "GET_MODE (op) == SImode")
119 : (match_test "GET_MODE (op) == HImode")
120 376308 : (match_test "GET_MODE (op) == QImode"))))
121 :
122 : ;; Match register operands, but include memory operands for TARGET_SSE_MATH.
123 : (define_predicate "register_ssemem_operand"
124 2877634 : (if_then_else
125 2877634 : (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
126 2877634 : (match_operand 0 "nonimmediate_operand")
127 : (match_operand 0 "register_operand")))
128 :
129 1082571 : ;; Match nonimmediate operands, but exclude memory operands
130 : ;; for TARGET_SSE_MATH if TARGET_MIX_SSE_I387 is not enabled.
131 1082571 : (define_predicate "nonimm_ssenomem_operand"
132 : (if_then_else
133 1082571 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
134 2165142 : (not (match_test "TARGET_MIX_SSE_I387")))
135 : (match_operand 0 "register_operand")
136 : (match_operand 0 "nonimmediate_operand")))
137 :
138 757959 : ;; The above predicate, suitable for x87 arithmetic operators.
139 : (define_predicate "x87nonimm_ssenomem_operand"
140 757959 : (if_then_else
141 757959 : (and (match_test "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH")
142 1515918 : (not (match_test "TARGET_MIX_SSE_I387 && X87_ENABLE_ARITH (mode)")))
143 : (match_operand 0 "register_operand")
144 : (match_operand 0 "nonimmediate_operand")))
145 :
146 34884 : ;; Match register operands, include memory operand for TARGET_SSE4_1.
147 : (define_predicate "register_sse4nonimm_operand"
148 34884 : (if_then_else (match_test "TARGET_SSE4_1")
149 : (match_operand 0 "nonimmediate_operand")
150 : (match_operand 0 "register_operand")))
151 :
152 14090 : ;; Return true if VALUE is symbol reference
153 : (define_predicate "symbol_operand"
154 14090 : (match_code "symbol_ref"))
155 14090 :
156 : ;; Return true if VALUE is an ENDBR opcode in immediate field.
157 : (define_predicate "ix86_endbr_immediate_operand"
158 : (match_code "const_int")
159 6429135273 : {
160 6429135273 : if (flag_cf_protection & CF_BRANCH)
161 : {
162 1208108913 : unsigned HOST_WIDE_INT imm = UINTVAL (op);
163 1208108913 : unsigned HOST_WIDE_INT val = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
164 :
165 1208108913 : if (imm == val)
166 : return true;
167 :
168 : /* NB: Encoding is byte based. */
169 1208108705 : if (TARGET_64BIT)
170 2333592096 : for (; imm >= val; imm >>= 8)
171 1314487791 : if (imm == val)
172 : return true;
173 : }
174 :
175 : return false;
176 : })
177 :
178 : ;; Return true if VALUE can be stored in a sign extended immediate field.
179 8321497723 : (define_predicate "x86_64_immediate_operand"
180 : (match_code "const_int,symbol_ref,label_ref,const")
181 8321497723 : {
182 11396288776 : if (ix86_endbr_immediate_operand (op, VOIDmode))
183 : return false;
184 :
185 4967153252 : if (!TARGET_64BIT)
186 5154088463 : return immediate_operand (op, mode);
187 :
188 4780218292 : switch (GET_CODE (op))
189 : {
190 3921548218 : case CONST_INT:
191 3921548218 : {
192 3921548218 : HOST_WIDE_INT val = INTVAL (op);
193 3921548218 : return trunc_int_for_mode (val, SImode) == val;
194 : }
195 699044350 : case SYMBOL_REF:
196 : /* TLS symbols are not constant. */
197 699044350 : if (SYMBOL_REF_TLS_MODEL (op))
198 : return false;
199 :
200 : /* Load the external function address via the GOT slot. */
201 699008420 : if (ix86_force_load_from_GOT_p (op))
202 : return false;
203 :
204 : /* For certain code models, the symbolic references are known to fit.
205 : in CM_SMALL_PIC model we know it fits if it is local to the shared
206 : library. Don't count TLS SYMBOL_REFs here, since they should fit
207 : only if inside of UNSPEC handled below. */
208 699008318 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
209 699008318 : || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
210 :
211 23773683 : case LABEL_REF:
212 : /* For certain code models, the code is near as well. */
213 23773683 : return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
214 : || ix86_cmodel == CM_KERNEL);
215 :
216 135852041 : case CONST:
217 : /* We also may accept the offsetted memory references in certain
218 : special cases. */
219 135852041 : if (GET_CODE (XEXP (op, 0)) == UNSPEC)
220 739094 : switch (XINT (XEXP (op, 0), 1))
221 : {
222 : case UNSPEC_GOTPCREL:
223 : case UNSPEC_DTPOFF:
224 : case UNSPEC_GOTNTPOFF:
225 : case UNSPEC_NTPOFF:
226 : case UNSPEC_SECREL32:
227 : return true;
228 : default:
229 : break;
230 : }
231 :
232 135114457 : if (GET_CODE (XEXP (op, 0)) == PLUS)
233 : {
234 135112947 : rtx op1 = XEXP (XEXP (op, 0), 0);
235 135112947 : rtx op2 = XEXP (XEXP (op, 0), 1);
236 :
237 135112947 : if (ix86_cmodel == CM_LARGE && GET_CODE (op1) != UNSPEC)
238 : return false;
239 135112942 : if (!CONST_INT_P (op2))
240 : return false;
241 :
242 135112942 : HOST_WIDE_INT offset = INTVAL (op2);
243 135112942 : if (trunc_int_for_mode (offset, SImode) != offset)
244 : return false;
245 :
246 135107632 : switch (GET_CODE (op1))
247 : {
248 134767086 : case SYMBOL_REF:
249 : /* TLS symbols are not constant. */
250 134767086 : if (SYMBOL_REF_TLS_MODEL (op1))
251 : return false;
252 :
253 : /* Load the external function address via the GOT slot. */
254 134756565 : if (ix86_force_load_from_GOT_p (op1))
255 : return false;
256 :
257 : /* For CM_SMALL assume that latest object is 16MB before
258 : end of 31bits boundary. We may also accept pretty
259 : large negative constants knowing that all objects are
260 : in the positive half of address space. */
261 134756559 : if ((ix86_cmodel == CM_SMALL
262 267415 : || (ix86_cmodel == CM_MEDIUM
263 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
264 134756559 : && offset < 16*1024*1024)
265 : return true;
266 : /* For CM_KERNEL we know that all object resist in the
267 : negative half of 32bits address space. We may not
268 : accept negative offsets, since they may be just off
269 : and we may accept pretty large positive ones. */
270 270325 : if (ix86_cmodel == CM_KERNEL
271 0 : && offset > 0)
272 : return true;
273 : break;
274 :
275 6026 : case LABEL_REF:
276 : /* These conditions are similar to SYMBOL_REF ones, just the
277 : constraints for code models differ. */
278 6026 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
279 6026 : && offset < 16*1024*1024)
280 : return true;
281 0 : if (ix86_cmodel == CM_KERNEL
282 0 : && offset > 0)
283 : return true;
284 : break;
285 :
286 334520 : case UNSPEC:
287 334520 : switch (XINT (op1, 1))
288 : {
289 : case UNSPEC_DTPOFF:
290 : case UNSPEC_NTPOFF:
291 : return true;
292 : }
293 : break;
294 :
295 : default:
296 : break;
297 : }
298 : }
299 : break;
300 :
301 0 : default:
302 0 : gcc_unreachable ();
303 : }
304 :
305 : return false;
306 : })
307 :
308 : ;; Return true if VALUE can be stored in the zero extended immediate field.
309 5454421560 : (define_predicate "x86_64_zext_immediate_operand"
310 : (match_code "const_int,symbol_ref,label_ref,const")
311 5454421560 : {
312 748458913 : if (ix86_endbr_immediate_operand (op, VOIDmode))
313 4967153503 : return false;
314 4967153503 :
315 748458765 : switch (GET_CODE (op))
316 4967153503 : {
317 5647485996 : case CONST_INT:
318 680332493 : return !(INTVAL (op) & ~HOST_WIDE_INT_C (0xffffffff));
319 :
320 61805807 : case SYMBOL_REF:
321 4967153503 : /* TLS symbols are not constant. */
322 5028959310 : if (SYMBOL_REF_TLS_MODEL (op))
323 270765754 : return false;
324 :
325 : /* Load the external function address via the GOT slot. */
326 61770748 : if (ix86_force_load_from_GOT_p (op))
327 748458913 : return false;
328 :
329 : /* For certain code models, the symbolic references are known to fit. */
330 61770647 : return (ix86_cmodel == CM_SMALL
331 61770647 : || (ix86_cmodel == CM_MEDIUM
332 218 : && !SYMBOL_REF_FAR_ADDR_P (op)));
333 :
334 2378085 : case LABEL_REF:
335 : /* For certain code models, the code is near as well. */
336 2378085 : return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
337 :
338 3942380 : case CONST:
339 : /* We also may accept the offsetted memory references in certain
340 : special cases. */
341 3942380 : if (GET_CODE (XEXP (op, 0)) == PLUS)
342 : {
343 3937794 : rtx op1 = XEXP (XEXP (op, 0), 0);
344 3937794 : rtx op2 = XEXP (XEXP (op, 0), 1);
345 :
346 3937794 : if (ix86_cmodel == CM_LARGE)
347 : return false;
348 3937792 : if (!CONST_INT_P (op2))
349 : return false;
350 :
351 3937792 : HOST_WIDE_INT offset = INTVAL (op2);
352 3937792 : if (trunc_int_for_mode (offset, SImode) != offset)
353 : return false;
354 :
355 3934998 : switch (GET_CODE (op1))
356 : {
357 3934507 : case SYMBOL_REF:
358 : /* TLS symbols are not constant. */
359 3934507 : if (SYMBOL_REF_TLS_MODEL (op1))
360 : return false;
361 :
362 : /* Load the external function address via the GOT slot. */
363 3925214 : if (ix86_force_load_from_GOT_p (op1))
364 : return false;
365 :
366 : /* For small code model we may accept pretty large positive
367 : offsets, since one bit is available for free. Negative
368 : offsets are limited by the size of NULL pointer area
369 : specified by the ABI. */
370 3925208 : if ((ix86_cmodel == CM_SMALL
371 235155 : || (ix86_cmodel == CM_MEDIUM
372 0 : && !SYMBOL_REF_FAR_ADDR_P (op1)))
373 3925208 : && offset > -0x10000)
374 : return true;
375 : /* ??? For the kernel, we may accept adjustment of
376 : -0x10000000, since we know that it will just convert
377 : negative address space to positive, but perhaps this
378 : is not worthwhile. */
379 : break;
380 :
381 0 : case LABEL_REF:
382 : /* These conditions are similar to SYMBOL_REF ones, just the
383 : constraints for code models differ. */
384 0 : if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
385 0 : && offset > -0x10000)
386 : return true;
387 : break;
388 :
389 : default:
390 : return false;
391 : }
392 : }
393 : break;
394 :
395 0 : default:
396 0 : gcc_unreachable ();
397 : }
398 : return false;
399 : })
400 :
401 : ;; Return true if VALUE is a constant integer whose negation satisfies
402 999042355 : ;; x86_64_immediate_operand.
403 : (define_predicate "x86_64_neg_const_int_operand"
404 999042355 : (match_code "const_int")
405 : {
406 748492688 : HOST_WIDE_INT val = -UINTVAL (op);
407 15913 : if (mode == DImode && trunc_int_for_mode (val, SImode) != val)
408 748458913 : return false;
409 33178 : if (flag_cf_protection & CF_BRANCH)
410 748458913 : {
411 13632 : unsigned HOST_WIDE_INT endbr = TARGET_64BIT ? 0xfa1e0ff3 : 0xfb1e0ff3;
412 13632 : if ((val & HOST_WIDE_INT_C (0xffffffff)) == endbr)
413 0 : return false;
414 748458913 : }
415 748458913 : return true;
416 53973416 : })
417 :
418 : ;; Return true if VALUE is a constant integer whose low and high words satisfy
419 48054 : ;; x86_64_immediate_operand.
420 33775 : (define_predicate "x86_64_hilo_int_operand"
421 81829 : (match_code "const_int,const_wide_int")
422 33775 : {
423 44403140 : switch (GET_CODE (op))
424 : {
425 44349860 : case CONST_INT:
426 44403140 : return x86_64_immediate_operand (op, mode);
427 :
428 53280 : case CONST_WIDE_INT:
429 53280 : gcc_assert (CONST_WIDE_INT_NUNITS (op) == 2);
430 53280 : return (x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op, 0)),
431 : DImode)
432 53280 : && x86_64_immediate_operand (GEN_INT (CONST_WIDE_INT_ELT (op,
433 : 1)),
434 : DImode));
435 :
436 0 : default:
437 0 : gcc_unreachable ();
438 : }
439 : })
440 :
441 : ;; Return true if VALUE is a constant integer whose value is
442 44981787 : ;; x86_64_immediate_operand value zero extended from word mode to mode.
443 : (define_predicate "x86_64_dwzext_immediate_operand"
444 44981787 : (match_code "const_int,const_wide_int")
445 : {
446 3742 : if (ix86_endbr_immediate_operand (op, VOIDmode))
447 44403140 : return false;
448 44403140 :
449 3742 : switch (GET_CODE (op))
450 : {
451 1624 : case CONST_INT:
452 1624 : if (!TARGET_64BIT)
453 44403140 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0xffffffff);
454 1624 : return UINTVAL (op) <= HOST_WIDE_INT_UC (0x7fffffff);
455 :
456 2118 : case CONST_WIDE_INT:
457 5860 : if (!TARGET_64BIT)
458 : return false;
459 2118 : return (CONST_WIDE_INT_NUNITS (op) == 2
460 2118 : && CONST_WIDE_INT_ELT (op, 1) == 0
461 4236 : && (trunc_int_for_mode (CONST_WIDE_INT_ELT (op, 0), SImode)
462 2118 : == (HOST_WIDE_INT) CONST_WIDE_INT_ELT (op, 0)));
463 :
464 0 : default:
465 0 : gcc_unreachable ();
466 : }
467 : })
468 :
469 : ;; Return true if size of VALUE can be stored in a sign
470 3742 : ;; extended immediate field.
471 : (define_predicate "x86_64_immediate_size_operand"
472 3742 : (and (match_code "symbol_ref")
473 0 : (ior (not (match_test "TARGET_64BIT"))
474 0 : (match_test "ix86_cmodel == CM_SMALL")
475 0 : (match_test "ix86_cmodel == CM_KERNEL"))))
476 0 :
477 : ;; Return true if OP is general operand representable on x86_64.
478 : (define_predicate "x86_64_general_operand"
479 150461343 : (if_then_else (match_test "TARGET_64BIT")
480 150465085 : (ior (match_operand 0 "nonimmediate_operand")
481 3742 : (match_operand 0 "x86_64_immediate_operand"))
482 150461343 : (match_operand 0 "general_operand")))
483 63309208 :
484 : ;; Return true if OP's both words are general operands representable
485 63309208 : ;; on x86_64.
486 : (define_predicate "x86_64_hilo_general_operand"
487 63309208 : (if_then_else (match_test "TARGET_64BIT")
488 : (ior (match_operand 0 "nonimmediate_operand")
489 : (match_operand 0 "x86_64_hilo_int_operand"))
490 : (match_operand 0 "general_operand")))
491 280203 :
492 : ;; Return true if OP is non-VOIDmode general operand representable
493 280203 : ;; on x86_64. This predicate is used in sign-extending conversion
494 : ;; operations that require non-VOIDmode immediate operands.
495 : (define_predicate "x86_64_sext_operand"
496 280203 : (and (match_test "GET_MODE (op) != VOIDmode")
497 : (match_operand 0 "x86_64_general_operand")))
498 :
499 : ;; Return true if OP is non-VOIDmode general operand. This predicate
500 11347 : ;; is used in sign-extending conversion operations that require
501 : ;; non-VOIDmode immediate operands.
502 11347 : (define_predicate "sext_operand"
503 11347 : (and (match_test "GET_MODE (op) != VOIDmode")
504 : (match_operand 0 "general_operand")))
505 :
506 : ;; Return true if OP is representable on x86_64 as zero-extended operand.
507 3570694 : ;; This predicate is used in zero-extending conversion operations that
508 : ;; require non-VOIDmode immediate operands.
509 3570694 : (define_predicate "x86_64_zext_operand"
510 3570694 : (if_then_else (match_test "TARGET_64BIT")
511 : (ior (match_operand 0 "nonimmediate_operand")
512 : (and (match_operand 0 "x86_64_zext_immediate_operand")
513 123968 : (match_test "GET_MODE (op) != VOIDmode")))
514 : (match_operand 0 "nonimmediate_operand")))
515 :
516 : ;; Return true if OP is general operand representable on x86_64
517 2479142 : ;; as either sign extended or zero extended constant.
518 : (define_predicate "x86_64_szext_general_operand"
519 2479142 : (if_then_else (match_test "TARGET_64BIT")
520 : (ior (match_operand 0 "nonimmediate_operand")
521 : (match_operand 0 "x86_64_immediate_operand")
522 : (match_operand 0 "x86_64_zext_immediate_operand"))
523 30460792 : (match_operand 0 "general_operand")))
524 :
525 30460792 : ;; Return true if OP is nonmemory operand representable on x86_64.
526 : (define_predicate "x86_64_nonmemory_operand"
527 30460792 : (if_then_else (match_test "TARGET_64BIT")
528 : (ior (match_operand 0 "register_operand")
529 : (match_operand 0 "x86_64_immediate_operand"))
530 : (match_operand 0 "nonmemory_operand")))
531 19011 :
532 : ;; Return true if OP is nonmemory operand representable on x86_64.
533 19011 : (define_predicate "x86_64_szext_nonmemory_operand"
534 19011 : (if_then_else (match_test "TARGET_64BIT")
535 : (ior (match_operand 0 "register_operand")
536 : (match_operand 0 "x86_64_immediate_operand")
537 : (match_operand 0 "x86_64_zext_immediate_operand"))
538 177844303 : (match_operand 0 "nonmemory_operand")))
539 :
540 : ;; Return true when operand is PIC expression that can be computed by lea
541 : ;; operation.
542 : (define_predicate "pic_32bit_operand"
543 : (match_code "const,symbol_ref,label_ref")
544 : {
545 177844303 : if (!flag_pic)
546 : return false;
547 :
548 : /* Rule out relocations that translate into 64bit constants. */
549 20895701 : if (TARGET_64BIT && GET_CODE (op) == CONST)
550 : {
551 190031 : rtx tmp = XEXP (op, 0);
552 190031 : if (GET_CODE (tmp) == PLUS && CONST_INT_P (XEXP (tmp, 1)))
553 188569 : tmp = XEXP (tmp, 0);
554 190031 : if (GET_CODE (tmp) == UNSPEC
555 1462 : && (XINT (tmp, 1) == UNSPEC_GOTOFF
556 1462 : || XINT (tmp, 1) == UNSPEC_GOT))
557 : return false;
558 : }
559 :
560 20894779 : return symbolic_operand (op, mode);
561 : })
562 :
563 : ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
564 1308481909 : (define_predicate "x86_64_movabs_operand"
565 : (and (match_operand 0 "nonmemory_operand")
566 1308481909 : (not (match_operand 0 "pic_32bit_operand"))))
567 :
568 177844303 : ;; Return true if OP is either a symbol reference or a sum of a symbol
569 177844303 : ;; reference and a constant.
570 177844303 : (define_predicate "symbolic_operand"
571 177844303 : (match_code "symbol_ref,label_ref,const")
572 : {
573 21632633 : switch (GET_CODE (op))
574 : {
575 177844303 : case SYMBOL_REF:
576 177844303 : case LABEL_REF:
577 551583 : return true;
578 :
579 226742 : case CONST:
580 226742 : op = XEXP (op, 0);
581 519855124 : if (SYMBOL_REF_P (op)
582 226742 : || LABEL_REF_P (op)
583 519855124 : || (GET_CODE (op) == UNSPEC
584 8398 : && (XINT (op, 1) == UNSPEC_GOT
585 8398 : || XINT (op, 1) == UNSPEC_GOTOFF
586 : || XINT (op, 1) == UNSPEC_SECREL32
587 21632633 : || XINT (op, 1) == UNSPEC_PCREL
588 : || XINT (op, 1) == UNSPEC_GOTPCREL)))
589 : return true;
590 219013 : if (GET_CODE (op) != PLUS
591 218344 : || !CONST_INT_P (XEXP (op, 1)))
592 : return false;
593 :
594 218344 : op = XEXP (op, 0);
595 218344 : if (SYMBOL_REF_P (op)
596 218344 : || LABEL_REF_P (op))
597 : return true;
598 : /* Only @GOTOFF and @SECREL32 get offsets. */
599 2128 : if (GET_CODE (op) != UNSPEC
600 2128 : || (XINT (op, 1) != UNSPEC_GOTOFF
601 0 : && XINT (op, 1) != UNSPEC_SECREL32))
602 : return false;
603 :
604 2128 : op = XVECEXP (op, 0, 0);
605 2128 : if (SYMBOL_REF_P (op)
606 2128 : || LABEL_REF_P (op))
607 2128 : return true;
608 : return false;
609 :
610 0 : default:
611 0 : gcc_unreachable ();
612 : }
613 : })
614 :
615 : ;; Return true if OP is a symbolic operand that resolves locally.
616 31283606 : (define_predicate "local_symbolic_operand"
617 : (match_code "const,label_ref,symbol_ref")
618 31283606 : {
619 2911339 : if (GET_CODE (op) == CONST
620 16163 : && GET_CODE (XEXP (op, 0)) == PLUS
621 8519 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
622 8519 : op = XEXP (XEXP (op, 0), 0);
623 21632633 :
624 2911339 : if (LABEL_REF_P (op))
625 : return true;
626 :
627 2865807 : if (!SYMBOL_REF_P (op))
628 21632633 : return false;
629 1289308 :
630 2856035 : if (SYMBOL_REF_TLS_MODEL (op))
631 : return false;
632 :
633 2911339 : /* Dll-imported symbols are always external. */
634 2856035 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
635 : return false;
636 2856035 : if (SYMBOL_REF_LOCAL_P (op))
637 : return true;
638 :
639 : /* There is, however, a not insubstantial body of code in the rest of
640 : the compiler that assumes it can just stick the results of
641 : ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
642 : /* ??? This is a hack. Should update the body of the compiler to
643 : always create a DECL an invoke targetm.encode_section_info. */
644 93631 : if (strncmp (XSTR (op, 0), internal_label_prefix,
645 : internal_label_prefix_len) == 0)
646 0 : return true;
647 :
648 : return false;
649 : })
650 :
651 : (define_predicate "local_func_symbolic_operand"
652 2920066 : (match_operand 0 "local_symbolic_operand")
653 : {
654 2920066 : if (GET_CODE (op) == CONST
655 0 : && GET_CODE (XEXP (op, 0)) == PLUS
656 0 : && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
657 0 : op = XEXP (XEXP (op, 0), 0);
658 2911339 :
659 2911351 : if (SYMBOL_REF_P (op)
660 12 : && !SYMBOL_REF_FUNCTION_P (op))
661 0 : return false;
662 :
663 2911339 : return true;
664 2911339 : })
665 2807927 :
666 : ;; Test for a legitimate @GOTOFF operand.
667 30 : ;;
668 : ;; VxWorks does not impose a fixed gap between segments; the run-time
669 42 : ;; gap can be different from the object-file gap. We therefore can't
670 12 : ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
671 : ;; same segment as the GOT. Unfortunately, the flexibility of linker
672 : ;; scripts means that we can't be sure of that in general, so assume
673 : ;; @GOTOFF is not valid on VxWorks, except with the large code model.
674 2919999 : ;; The comments above seem to apply only to VxWorks releases before 7.
675 : (define_predicate "gotoff_operand"
676 2919999 : (and (ior (not (match_test "TARGET_VXWORKS_VAROFF"))
677 : (match_test "ix86_cmodel == CM_LARGE")
678 2919999 : (match_test "ix86_cmodel == CM_LARGE_PIC"))
679 : (match_operand 0 "local_symbolic_operand")))
680 :
681 : ;; Test for various thread-local symbols.
682 30001 : (define_special_predicate "tls_symbolic_operand"
683 : (and (match_code "symbol_ref")
684 30001 : (match_test "SYMBOL_REF_TLS_MODEL (op)")))
685 :
686 : (define_special_predicate "tls_modbase_operand"
687 : (and (match_code "symbol_ref")
688 72 : (match_test "op == ix86_tls_module_base ()")))
689 :
690 144 : (define_predicate "tls_address_pattern"
691 : (and (match_code "set,parallel,unspec,unspec_volatile")
692 238666869 : (match_test "ix86_tls_address_pattern_p (op)")))
693 0 :
694 238666869 : ;; Test for a pc-relative call operand
695 : (define_predicate "constant_call_address_operand"
696 238666869 : (match_code "symbol_ref")
697 374265382 : {
698 135598304 : if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC
699 135598293 : || flag_force_indirect_call
700 271195302 : || (TARGET_INDIRECT_BRANCH_REGISTER
701 1022 : && ix86_nopic_noplt_attribute_p (op)))
702 1748 : return false;
703 : if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
704 238666869 : return false;
705 : return true;
706 : })
707 :
708 : ;; True for any non-virtual and non-eliminable register. Used in places where
709 141278657 : ;; instantiation of such a register may cause the pattern to not be recognized.
710 : (define_predicate "register_no_elim_operand"
711 135598513 : (match_operand 0 "register_operand")
712 276875422 : {
713 97721850 : if (SUBREG_P (op))
714 63833 : op = SUBREG_REG (op);
715 :
716 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
717 20722760 : because it is guaranteed to be reloaded into one. */
718 20722760 : if (MEM_P (op))
719 : return true;
720 :
721 20722760 : return !(op == arg_pointer_rtx
722 20694730 : || op == frame_pointer_rtx
723 20692462 : || VIRTUAL_REGISTER_P (op));
724 : })
725 :
726 : ;; Similarly, but include the stack pointer. This is used
727 24706320 : ;; to prevent esp from being used as an index reg.
728 : (define_predicate "register_no_SP_operand"
729 24706320 : (match_operand 0 "register_operand")
730 20722760 : {
731 332320 : if (SUBREG_P (op))
732 7933 : op = SUBREG_REG (op);
733 :
734 332320 : /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
735 : because it is guaranteed to be reloaded into one. */
736 332320 : if (MEM_P (op))
737 : return true;
738 :
739 332320 : return !(op == arg_pointer_rtx
740 332320 : || op == frame_pointer_rtx
741 332320 : || op == stack_pointer_rtx
742 332320 : || VIRTUAL_REGISTER_P (op));
743 : })
744 :
745 : ;; P6 processors will jump to the address after the decrement when %esp
746 369152 : ;; is used as a call operand, so they will execute return address as a code.
747 : ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
748 369152 :
749 332320 : (define_predicate "call_register_operand"
750 1846529 : (if_then_else (match_test "TARGET_64BIT")
751 : (match_operand 0 "register_operand")
752 : (match_operand 0 "register_no_SP_operand")))
753 1846529 :
754 17939557 : ;; Return false if this is any eliminable register. Otherwise general_operand.
755 1846529 : (define_predicate "general_no_elim_operand"
756 17939557 : (if_then_else (match_code "reg,subreg")
757 : (match_operand 0 "register_no_elim_operand")
758 : (match_operand 0 "general_operand")))
759 :
760 11595224 : ;; Return false if this is any eliminable register. Otherwise
761 : ;; register_operand or a constant.
762 11595224 : (define_predicate "nonmemory_no_elim_operand"
763 : (ior (match_operand 0 "register_no_elim_operand")
764 : (match_operand 0 "immediate_operand")))
765 :
766 623023 : ;; Test for a valid operand for indirect branch.
767 : (define_predicate "indirect_branch_operand"
768 623023 : (ior (match_operand 0 "register_operand")
769 570063 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
770 570036 : (not (match_test "TARGET_X32"))
771 : (match_operand 0 "memory_operand"))))
772 :
773 : ;; Return true if OP is a memory operands that can be used in sibcalls.
774 24023 : ;; Since sibcall never returns, we can only use call-clobbered register
775 : ;; as GOT base. Allow GOT slot here only with pseudo register as GOT
776 : ;; base. Properly handle sibcall over GOT slot with *sibcall_GOT_32
777 : ;; and *sibcall_value_GOT_32 patterns.
778 : (define_predicate "sibcall_memory_operand"
779 : (match_operand 0 "memory_operand")
780 : {
781 24023 : op = XEXP (op, 0);
782 24023 : if (CONSTANT_P (op))
783 : return true;
784 10494 : if (GET_CODE (op) == PLUS && REG_P (XEXP (op, 0)))
785 : {
786 9468 : int regno = REGNO (XEXP (op, 0));
787 9468 : if (!HARD_REGISTER_NUM_P (regno) || call_used_or_fixed_reg_p (regno))
788 : {
789 7748 : op = XEXP (op, 1);
790 7748 : if (GOT32_symbol_operand (op, VOIDmode))
791 : return true;
792 : }
793 : }
794 : return false;
795 : })
796 :
797 : ;; Return true if OP is a GOT memory operand.
798 1379355 : (define_predicate "GOT_memory_operand"
799 : (and (match_operand 0 "memory_operand")
800 1403378 : (match_code "const" "0")
801 24023 : (match_code "unspec" "00")
802 566 : (match_test "XINT (XEXP (XEXP (op, 0), 0), 1) == UNSPEC_GOTPCREL")))
803 :
804 : ;; Test for a valid operand for a call instruction.
805 464 : ;; Allow constant call address operands in Pmode only.
806 48467298 : (define_special_predicate "call_insn_operand"
807 464 : (ior (match_test "constant_call_address_operand
808 54629219 : (op, mode == VOIDmode ? mode : Pmode)")
809 : (match_operand 0 "call_register_operand")
810 844630 : (match_test "satisfies_constraint_Bw (op)")))
811 :
812 : ;; Similarly, but for tail calls, in which we cannot allow memory references.
813 : (define_special_predicate "sibcall_insn_operand"
814 1222018 : (ior (match_test "constant_call_address_operand
815 1383443 : (op, mode == VOIDmode ? mode : Pmode)")
816 1222018 : (match_operand 0 "register_no_elim_operand")
817 124059 : (match_test "satisfies_constraint_Bs (op)")))
818 :
819 : ;; Return true if OP is a 32-bit GOT symbol operand.
820 : (define_predicate "GOT32_symbol_operand"
821 9660 : (and (match_code "const")
822 : (match_code "unspec" "0")
823 9660 : (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_GOT")))
824 0 :
825 : ;; Match exactly zero.
826 : (define_predicate "const0_operand"
827 : (match_code "const_int,const_double,const_vector")
828 137964422 : {
829 137964422 : if (mode == VOIDmode)
830 21437384 : mode = GET_MODE (op);
831 137964422 : return op == CONST0_RTX (mode);
832 : })
833 :
834 : ;; Match one or a vector with all elements equal to one.
835 991183413 : (define_predicate "const1_operand"
836 : (match_code "const_int,const_double,const_vector")
837 991183413 : {
838 11259210 : if (mode == VOIDmode)
839 11197510 : mode = GET_MODE (op);
840 149223632 : return op == CONST1_RTX (mode);
841 137964422 : })
842 137964422 :
843 : ;; Match exactly -1.
844 12515032 : (define_predicate "constm1_operand"
845 : (and (match_code "const_int")
846 150479454 : (match_test "op == constm1_rtx")))
847 137964422 :
848 63202401 : ;; Match 0 or -1.
849 11259210 : (define_predicate "const0_or_m1_operand"
850 11262103 : (ior (match_operand 0 "const0_operand")
851 11259210 : (match_operand 0 "constm1_operand")))
852 2893 :
853 : ;; Match exactly eight.
854 : (define_predicate "const8_operand"
855 11259210 : (and (match_code "const_int")
856 11259210 : (match_test "INTVAL (op) == 8")))
857 9998 :
858 208509 : ;; Match exactly 128.
859 : (define_predicate "const128_operand"
860 27606677 : (and (match_code "const_int")
861 243933654 : (match_test "INTVAL (op) == 128")))
862 27606677 :
863 193272839 : ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
864 : (define_predicate "const_32bit_mask"
865 2891481 : (and (match_code "const_int")
866 1920986 : (match_test "trunc_int_for_mode (INTVAL (op), DImode)
867 4812467 : == HOST_WIDE_INT_C (0xffffffff)")))
868 :
869 : ;; Match 2, 4, or 8. Used for leal multiplicands.
870 : (define_predicate "const248_operand"
871 300613 : (match_code "const_int")
872 : {
873 300613 : HOST_WIDE_INT i = INTVAL (op);
874 300613 : return i == 2 || i == 4 || i == 8;
875 : })
876 :
877 : ;; Match 1, 2, or 3. Used for lea shift amounts.
878 1024572 : (define_predicate "const123_operand"
879 : (match_code "const_int")
880 1024572 : {
881 1251648 : HOST_WIDE_INT i = INTVAL (op);
882 227076 : return i == 1 || i == 2 || i == 3;
883 : })
884 :
885 227076 : ;; Match 2, 3, 6, or 7
886 235494 : (define_predicate "const2367_operand"
887 : (match_code "const_int")
888 235494 : {
889 227076 : HOST_WIDE_INT i = INTVAL (op);
890 0 : return i == 2 || i == 3 || i == 6 || i == 7;
891 : })
892 :
893 0 : ;; Match 1, 2, 4, or 8
894 0 : (define_predicate "const1248_operand"
895 : (match_code "const_int")
896 0 : {
897 109830 : HOST_WIDE_INT i = INTVAL (op);
898 109830 : return i == 1 || i == 2 || i == 4 || i == 8;
899 : })
900 :
901 109830 : ;; Match 3, 5, or 9. Used for leal multiplicands.
902 536251 : (define_predicate "const359_operand"
903 : (match_code "const_int")
904 536251 : {
905 583061 : HOST_WIDE_INT i = INTVAL (op);
906 46810 : return i == 3 || i == 5 || i == 9;
907 : })
908 :
909 46810 : ;; Match 4 or 8 to 11. Used for embedded rounding.
910 222897 : (define_predicate "const_4_or_8_to_11_operand"
911 : (match_code "const_int")
912 222897 : {
913 302895 : HOST_WIDE_INT i = INTVAL (op);
914 79998 : return i == 4 || (i >= 8 && i <= 11);
915 : })
916 :
917 79998 : ;; Match 4 or 8. Used for SAE.
918 80000 : (define_predicate "const48_operand"
919 : (match_code "const_int")
920 80000 : {
921 79998 : HOST_WIDE_INT i = INTVAL (op);
922 65756 : return i == 4 || i == 8;
923 : })
924 :
925 65756 : ;; Match 0 or 1.
926 65756 : (define_predicate "const_0_to_1_operand"
927 : (and (match_code "const_int")
928 65756 : (ior (match_test "op == const0_rtx")
929 299190 : (match_test "op == const1_rtx"))))
930 :
931 : ;; Match 0 to 3.
932 : (define_predicate "const_0_to_3_operand"
933 7921850 : (and (match_code "const_int")
934 15045694 : (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
935 7921850 :
936 : ;; Match 0 to 4.
937 : (define_predicate "const_0_to_4_operand"
938 0 : (and (match_code "const_int")
939 0 : (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
940 0 :
941 : ;; Match 0 to 5.
942 : (define_predicate "const_0_to_5_operand"
943 0 : (and (match_code "const_int")
944 0 : (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
945 0 :
946 : ;; Match 0 to 7.
947 : (define_predicate "const_0_to_7_operand"
948 782604 : (and (match_code "const_int")
949 1565194 : (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
950 782604 :
951 : ;; Match 0 to 15.
952 : (define_predicate "const_0_to_15_operand"
953 81647 : (and (match_code "const_int")
954 163278 : (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
955 81647 :
956 : ;; Match 0 to 31.
957 : (define_predicate "const_0_to_31_operand"
958 54389 : (and (match_code "const_int")
959 108220 : (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
960 54389 :
961 : ;; Match 0 to 63.
962 : (define_predicate "const_0_to_63_operand"
963 26862 : (and (match_code "const_int")
964 51879 : (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
965 26862 :
966 : ;; Match 0 to 127.
967 : (define_predicate "const_0_to_127_operand"
968 9807 : (and (match_code "const_int")
969 18630 : (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
970 9807 :
971 : ;; Match 0 to 255.
972 : (define_predicate "const_0_to_255_operand"
973 8820067 : (and (match_code "const_int")
974 17612479 : (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
975 8820067 :
976 : ;; Match (0 to 255) * 8
977 : (define_predicate "const_0_to_255_mul_8_operand"
978 544355 : (match_code "const_int")
979 : {
980 544355 : unsigned HOST_WIDE_INT val = INTVAL (op);
981 544355 : return val <= 255*8 && val % 8 == 0;
982 : })
983 :
984 : ;; Match 1 to 255 except multiples of 8
985 544357 : (define_predicate "const_0_to_255_not_mul_8_operand"
986 : (match_code "const_int")
987 544357 : {
988 9 : unsigned HOST_WIDE_INT val = INTVAL (op);
989 935678 : return val <= 255 && val % 8 != 0;
990 : })
991 :
992 935692 : ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
993 935692 : ;; for shift & compare patterns, as shifting by 0 does not change flags).
994 : (define_predicate "const_1_to_31_operand"
995 935692 : (and (match_code "const_int")
996 732137 : (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
997 :
998 : ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
999 : ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
1000 99894 : (define_predicate "const_1_to_63_operand"
1001 : (and (match_code "const_int")
1002 99894 : (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
1003 :
1004 : ;; Match 2 or 3.
1005 : (define_predicate "const_2_to_3_operand"
1006 74716 : (and (match_code "const_int")
1007 149432 : (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
1008 74716 :
1009 : ;; Match 4 to 5.
1010 : (define_predicate "const_4_to_5_operand"
1011 5510 : (and (match_code "const_int")
1012 11020 : (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
1013 5510 :
1014 : ;; Match 4 to 7.
1015 : (define_predicate "const_4_to_7_operand"
1016 1112128 : (and (match_code "const_int")
1017 2224256 : (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
1018 1112128 :
1019 : ;; Match 6 to 7.
1020 : (define_predicate "const_6_to_7_operand"
1021 700 : (and (match_code "const_int")
1022 1400 : (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
1023 700 :
1024 : ;; Match 8 to 9.
1025 : (define_predicate "const_8_to_9_operand"
1026 513 : (and (match_code "const_int")
1027 1026 : (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
1028 513 :
1029 : ;; Match 8 to 11.
1030 : (define_predicate "const_8_to_11_operand"
1031 35441 : (and (match_code "const_int")
1032 70882 : (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
1033 35441 :
1034 : ;; Match 8 to 15.
1035 : (define_predicate "const_8_to_15_operand"
1036 39970 : (and (match_code "const_int")
1037 79940 : (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
1038 39970 :
1039 : ;; Match 10 to 11.
1040 : (define_predicate "const_10_to_11_operand"
1041 267 : (and (match_code "const_int")
1042 534 : (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
1043 267 :
1044 : ;; Match 12 to 13.
1045 : (define_predicate "const_12_to_13_operand"
1046 266 : (and (match_code "const_int")
1047 532 : (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
1048 266 :
1049 : ;; Match 12 to 15.
1050 : (define_predicate "const_12_to_15_operand"
1051 23658 : (and (match_code "const_int")
1052 47316 : (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
1053 23658 :
1054 : ;; Match 14 to 15.
1055 : (define_predicate "const_14_to_15_operand"
1056 266 : (and (match_code "const_int")
1057 532 : (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
1058 266 :
1059 : ;; Match 16 to 19.
1060 : (define_predicate "const_16_to_19_operand"
1061 924 : (and (match_code "const_int")
1062 1848 : (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
1063 924 :
1064 : ;; Match 16 to 31.
1065 : (define_predicate "const_16_to_31_operand"
1066 10153 : (and (match_code "const_int")
1067 20306 : (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
1068 10153 :
1069 : ;; Match 20 to 23.
1070 : (define_predicate "const_20_to_23_operand"
1071 532 : (and (match_code "const_int")
1072 1064 : (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
1073 532 :
1074 : ;; Match 24 to 27.
1075 : (define_predicate "const_24_to_27_operand"
1076 532 : (and (match_code "const_int")
1077 1064 : (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
1078 532 :
1079 : ;; Match 28 to 31.
1080 : (define_predicate "const_28_to_31_operand"
1081 532 : (and (match_code "const_int")
1082 1064 : (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
1083 532 :
1084 : (define_predicate "cmpps_imm_operand"
1085 : (ior (match_operand 0 "const_0_to_7_operand")
1086 4044 : (and (match_test "TARGET_AVX")
1087 : (match_operand 0 "const_0_to_31_operand"))))
1088 60214 :
1089 : ;; True if this is a constant appropriate for an increment or decrement.
1090 102512894 : (define_predicate "incdec_operand"
1091 : (match_code "const_int")
1092 : {
1093 : /* On Pentium4, the inc and dec operations causes extra dependency on flag
1094 : registers, since carry flag is not set. */
1095 102512894 : if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
1096 : return false;
1097 2622084 : return op == const1_rtx || op == constm1_rtx;
1098 : })
1099 :
1100 : ;; True for registers, or const_int_operand, used to vec_setm expander.
1101 127390883 : (define_predicate "vec_setm_sse41_operand"
1102 : (ior (and (match_operand 0 "register_operand")
1103 229904846 : (match_test "TARGET_SSE4_1"))
1104 102512894 : (match_code "const_int")))
1105 :
1106 : (define_predicate "vec_setm_avx2_operand"
1107 : (ior (and (match_operand 0 "register_operand")
1108 1240 : (match_test "TARGET_AVX2"))
1109 0 : (match_code "const_int")))
1110 1544 :
1111 : (define_predicate "vec_setm_mmx_operand"
1112 : (ior (and (match_operand 0 "register_operand")
1113 22 : (match_test "TARGET_SSE4_1")
1114 269 : (match_test "TARGET_MMX_WITH_SSE"))
1115 269 : (match_code "const_int")))
1116 :
1117 : ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
1118 : (define_predicate "reg_or_pm1_operand"
1119 4378539 : (ior (match_operand 0 "register_operand")
1120 : (and (match_code "const_int")
1121 4378539 : (ior (match_test "op == const1_rtx")
1122 259854 : (match_test "op == constm1_rtx")))))
1123 243520 :
1124 : ;; True for registers, or (not: registers). Used to optimize 3-operand
1125 : ;; bitwise operation.
1126 : (define_predicate "regmem_or_bitnot_regmem_operand"
1127 705748 : (ior (match_operand 0 "nonimmediate_operand")
1128 : (and (match_code "not")
1129 705748 : (match_test "nonimmediate_operand (XEXP (op, 0), mode)"))))
1130 28947 :
1131 : ;; True for expressions valid for 3-operand ternlog instructions.
1132 : (define_predicate "ternlog_operand"
1133 : (and (match_code "not,and,ior,xor")
1134 2322023 : (match_test "ix86_ternlog_operand_p (op)")))
1135 252275 :
1136 65965748 : ;; True if OP is acceptable as operand of DImode shift expander.
1137 : (define_predicate "shiftdi_operand"
1138 1366310 : (if_then_else (match_test "TARGET_64BIT")
1139 3688333 : (match_operand 0 "nonimmediate_operand")
1140 2322023 : (match_operand 0 "register_operand")))
1141 1366310 :
1142 2957179 : (define_predicate "ashldi_input_operand"
1143 635156 : (if_then_else (match_test "TARGET_64BIT")
1144 635156 : (match_operand 0 "nonimmediate_operand")
1145 : (match_operand 0 "reg_or_pm1_operand")))
1146 2322023 :
1147 573438 : ;; Return true if OP is a vector load from the constant pool with just
1148 : ;; the first element nonzero.
1149 : (define_predicate "zero_extended_scalar_load_operand"
1150 : (match_code "mem")
1151 : {
1152 573438 : unsigned n_elts;
1153 573438 : op = avoid_constant_pool_reference (op);
1154 :
1155 573438 : if (!CONST_VECTOR_P (op))
1156 : return false;
1157 :
1158 84365 : n_elts = CONST_VECTOR_NUNITS (op);
1159 :
1160 180206 : for (n_elts--; n_elts > 0; n_elts--)
1161 : {
1162 129361 : rtx elt = CONST_VECTOR_ELT (op, n_elts);
1163 258722 : if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
1164 : return false;
1165 : }
1166 : return true;
1167 : })
1168 :
1169 : /* Return true if operand is a float vector constant that is all ones. */
1170 1959824 : (define_predicate "float_vector_all_ones_operand"
1171 : (match_code "const_vector,mem")
1172 573438 : {
1173 2010669 : mode = GET_MODE (op);
1174 50845 : if (!FLOAT_MODE_P (mode)
1175 13418564 : || (MEM_P (op)
1176 11563911 : && (!SYMBOL_REF_P (XEXP (op, 0))
1177 1387576 : || !CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))))
1178 16288774 : return false;
1179 :
1180 2999728 : if (MEM_P (op))
1181 : {
1182 1145075 : op = get_pool_constant (XEXP (op, 0));
1183 1145075 : if (!CONST_VECTOR_P (op))
1184 : return false;
1185 :
1186 1145071 : if (GET_MODE (op) != mode
1187 5875 : && INTEGRAL_MODE_P (GET_MODE (op))
1188 5875 : && op == CONSTM1_RTX (GET_MODE (op)))
1189 : return true;
1190 : }
1191 :
1192 2999724 : rtx first = XVECEXP (op, 0, 0);
1193 8695612 : for (int i = 1; i != GET_MODE_NUNITS (GET_MODE (op)); i++)
1194 : {
1195 3823269 : rtx tmp = XVECEXP (op, 0, i);
1196 3823269 : if (!rtx_equal_p (tmp, first))
1197 : return false;
1198 : }
1199 524537 : if (GET_MODE (first) == E_SFmode)
1200 : {
1201 245099 : long l;
1202 245099 : REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1203 245099 : return (l & 0xffffffff) == 0xffffffff;
1204 : }
1205 279438 : else if (GET_MODE (first) == E_DFmode)
1206 : {
1207 272484 : long l[2];
1208 272484 : REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (first), l);
1209 272484 : return ((l[0] & 0xffffffff) == 0xffffffff
1210 272484 : && (l[1] & 0xffffffff) == 0xffffffff);
1211 : }
1212 : else
1213 : return false;
1214 : })
1215 :
1216 : /* Return true if operand is an integral vector constant that is all ones. */
1217 55321231 : (define_predicate "vector_all_ones_operand"
1218 : (and (match_code "const_vector")
1219 68852017 : (match_test "INTEGRAL_MODE_P (GET_MODE (op))")
1220 11740231 : (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
1221 1077297 :
1222 16288774 : /* Return true if operand is a vector constant that is all ones. */
1223 16288774 : (define_predicate "int_float_vector_all_ones_operand"
1224 : (ior (match_operand 0 "vector_all_ones_operand")
1225 9156096 : (match_operand 0 "float_vector_all_ones_operand")
1226 0 : (match_test "op == constm1_rtx")))
1227 9156096 :
1228 16288774 : /* Return true if operand is an 128/256bit all ones vector
1229 3072 : that zero-extends to 256/512bit. */
1230 : (define_predicate "vector_all_ones_zero_extend_half_operand"
1231 11996578 : (match_code "const_vector")
1232 : {
1233 176218749 : mode = GET_MODE (op);
1234 11996578 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1235 186622732 : || (GET_MODE_SIZE (mode) != 32
1236 10103702 : && GET_MODE_SIZE (mode) != 64))
1237 : return false;
1238 :
1239 468299 : int nelts = CONST_VECTOR_NUNITS (op);
1240 540966 : for (int i = 0; i != nelts; i++)
1241 : {
1242 539958 : rtx elt = CONST_VECTOR_ELT (op, i);
1243 539958 : if (i < nelts / 2
1244 1061182 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1245 : return false;
1246 83690 : if (i >= nelts / 2
1247 102424 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1248 : return false;
1249 : }
1250 : return true;
1251 : })
1252 :
1253 : /* Return true if operand is an 128bit all ones vector
1254 177298720 : that zero extends to 512bit. */
1255 : (define_predicate "vector_all_ones_zero_extend_quarter_operand"
1256 11996578 : (match_code "const_vector")
1257 177299728 : {
1258 1008 : mode = GET_MODE (op);
1259 11995570 : if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT
1260 10402975 : || GET_MODE_SIZE (mode) != 64)
1261 : return false;
1262 11995570 :
1263 167799 : int nelts = CONST_VECTOR_NUNITS (op);
1264 181490 : for (int i = 0; i != nelts; i++)
1265 : {
1266 181398 : rtx elt = CONST_VECTOR_ELT (op, i);
1267 181398 : if (i < nelts / 4
1268 359286 : && elt != CONSTM1_RTX (GET_MODE_INNER (mode)))
1269 : return false;
1270 16331 : if (i >= nelts / 4
1271 19841 : && elt != CONST0_RTX (GET_MODE_INNER (mode)))
1272 : return false;
1273 : }
1274 : return true;
1275 : })
1276 :
1277 : ; Return true when OP is operand acceptable for vector memory operand.
1278 177297712 : ; Only AVX can have misaligned memory operand.
1279 : (define_predicate "vector_memory_operand"
1280 11995570 : (and (match_operand 0 "memory_operand")
1281 178418021 : (ior (match_test "TARGET_AVX")
1282 1120309 : (match_test "MEM_ALIGN (op) >= GET_MODE_ALIGNMENT (mode)"))))
1283 :
1284 : ; Return true when OP is register_operand or vector_memory_operand.
1285 : (define_predicate "vector_operand"
1286 19991521 : (ior (match_operand 0 "register_operand")
1287 : (match_operand 0 "vector_memory_operand")))
1288 19991521 :
1289 : ; Return true when OP is register_operand, vector_memory_operand
1290 : ; or const_vector.
1291 : (define_predicate "vector_or_const_vector_operand"
1292 95164 : (ior (match_operand 0 "register_operand")
1293 : (match_operand 0 "vector_memory_operand")
1294 95164 : (match_code "const_vector")))
1295 44466 :
1296 : (define_predicate "bcst_mem_operand"
1297 : (and (match_code "vec_duplicate")
1298 14442 : (and (match_test "TARGET_AVX512F")
1299 167093116 : (ior (match_test "TARGET_AVX512VL")
1300 9032 : (match_test "GET_MODE_SIZE (GET_MODE (op)) == 64")))
1301 151696 : (match_test "VALID_BCST_MODE_P (GET_MODE_INNER (GET_MODE (op)))")
1302 13496 : (match_test "GET_MODE (XEXP (op, 0))
1303 40477 : == GET_MODE_INNER (GET_MODE (op))")
1304 167107426 : (match_test "memory_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
1305 5341 :
1306 : ; Return true when OP is bcst_mem_operand or vector_memory_operand.
1307 : (define_predicate "bcst_vector_operand"
1308 : (ior (match_operand 0 "vector_operand")
1309 5370146 : (match_operand 0 "bcst_mem_operand")))
1310 :
1311 5370146 : ;; Return true when OP is either nonimmediate operand, or any
1312 : ;; CONST_VECTOR.
1313 : (define_predicate "nonimmediate_or_const_vector_operand"
1314 : (ior (match_operand 0 "nonimmediate_operand")
1315 89026 : (match_code "const_vector")))
1316 :
1317 89026 : (define_predicate "nonimmediate_or_const_vec_dup_operand"
1318 14269 : (ior (match_operand 0 "nonimmediate_operand")
1319 46 : (match_test "const_vec_duplicate_p (op)")))
1320 46 :
1321 : ;; Return true when OP is either register operand, or any
1322 94 : ;; CONST_VECTOR.
1323 : (define_predicate "reg_or_const_vector_operand"
1324 94 : (ior (match_operand 0 "register_operand")
1325 : (match_code "const_vector")))
1326 260 :
1327 153 : ;; Return true when OP is CONST_VECTOR which can be converted to a
1328 : ;; sign extended 32-bit integer.
1329 : (define_predicate "x86_64_const_vector_operand"
1330 : (match_code "const_vector")
1331 160385 : {
1332 160385 : if (mode == VOIDmode)
1333 0 : mode = GET_MODE (op);
1334 160385 : else if (GET_MODE (op) != mode)
1335 : return false;
1336 377250 : if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1337 : return false;
1338 117363 : HOST_WIDE_INT val = ix86_convert_const_vector_to_integer (op, mode);
1339 117363 : return trunc_int_for_mode (val, SImode) == val;
1340 : })
1341 :
1342 : (define_predicate "nonimmediate_or_x86_64_const_vector_operand"
1343 983043 : (ior (match_operand 0 "nonimmediate_operand")
1344 : (match_operand 0 "x86_64_const_vector_operand")))
1345 160385 :
1346 1066753 : ;; Return true when OP is nonimmediate or standard SSE constant.
1347 83710 : (define_predicate "nonimmediate_or_sse_const_operand"
1348 : (ior (match_operand 0 "nonimmediate_operand")
1349 25313443 : (match_test "standard_sse_constant_p (op, mode)")))
1350 2816179 :
1351 6581 : ;; Return true if OP is a register or a zero.
1352 : (define_predicate "reg_or_0_operand"
1353 6581 : (ior (match_operand 0 "register_operand")
1354 404116 : (match_operand 0 "const0_operand")))
1355 :
1356 404116 : ; Return true when OP is a nonimmediate or zero.
1357 95110116 : (define_predicate "nonimm_or_0_operand"
1358 : (ior (match_operand 0 "nonimmediate_operand")
1359 117607380 : (match_operand 0 "const0_operand")))
1360 126653286 :
1361 : ; Return true when OP is a nonimmediate or zero or all ones.
1362 126653286 : (define_predicate "nonimm_or_0_or_1s_operand"
1363 : (ior (match_operand 0 "nonimmediate_operand")
1364 : (match_operand 0 "const0_operand")
1365 : (match_operand 0 "int_float_vector_all_ones_operand")))
1366 82230 :
1367 : ;; Return true for RTX codes that force SImode address.
1368 82230 : (define_predicate "SImode_address_operand"
1369 : (match_code "subreg,zero_extend,and"))
1370 :
1371 : ;; Return true if op is a valid address for LEA, and does not contain
1372 273198368 : ;; a segment override. Defined as a special predicate to allow
1373 : ;; mode-less const_int operands pass to address_operand.
1374 273198368 : (define_special_predicate "address_no_seg_operand"
1375 182960382 : (match_test "address_operand (op, VOIDmode)")
1376 66983697 : {
1377 67359813 : struct ix86_address parts;
1378 67359813 : int ok;
1379 376116 :
1380 67022155 : if (!CONST_INT_P (op)
1381 64073065 : && mode != VOIDmode
1382 64073065 : && GET_MODE (op) != mode)
1383 376116 : return false;
1384 376116 :
1385 66983633 : ok = ix86_decompose_address (op, &parts);
1386 66983633 : gcc_assert (ok);
1387 66983633 : return parts.seg == ADDR_SPACE_GENERIC;
1388 66983697 : })
1389 :
1390 : ;; Return true if op if a valid base register, displacement or
1391 115976685 : ;; sum of base register and displacement for VSIB addressing.
1392 : (define_predicate "vsib_address_operand"
1393 116015143 : (match_test "address_operand (op, VOIDmode)")
1394 77677 : {
1395 37748 : struct ix86_address parts;
1396 38458 : int ok;
1397 38458 : rtx disp;
1398 :
1399 38458 : ok = ix86_decompose_address (op, &parts);
1400 38458 : gcc_assert (ok);
1401 64520 : if (parts.index || parts.seg != ADDR_SPACE_GENERIC)
1402 26062 : return false;
1403 :
1404 : /* VSIB addressing doesn't support (%rip). */
1405 38438 : if (parts.disp)
1406 25853035 : {
1407 6386 : disp = parts.disp;
1408 6386 : if (GET_CODE (disp) == CONST)
1409 : {
1410 148 : disp = XEXP (disp, 0);
1411 148 : if (GET_CODE (disp) == PLUS)
1412 148 : disp = XEXP (disp, 0);
1413 148 : if (GET_CODE (disp) == UNSPEC)
1414 0 : switch (XINT (disp, 1))
1415 : {
1416 : case UNSPEC_GOTPCREL:
1417 : case UNSPEC_PCREL:
1418 : case UNSPEC_GOTNTPOFF:
1419 : return false;
1420 : }
1421 : }
1422 6386 : if (TARGET_64BIT
1423 6386 : && flag_pic
1424 0 : && (SYMBOL_REF_P (disp)
1425 0 : || LABEL_REF_P (disp)))
1426 0 : return false;
1427 : }
1428 :
1429 : return true;
1430 : })
1431 :
1432 : (define_predicate "vsib_mem_operator"
1433 39239 : (match_code "mem"))
1434 :
1435 39239 : ;; Return true if the rtx is known to be at least 32 bits aligned.
1436 : (define_predicate "aligned_operand"
1437 : (match_operand 0 "general_operand")
1438 : {
1439 25853035 : struct ix86_address parts;
1440 25853035 : int ok;
1441 :
1442 : /* Registers and immediate operands are always "aligned". */
1443 25853035 : if (!MEM_P (op))
1444 : return true;
1445 :
1446 : /* All patterns using aligned_operand on memory operands ends up
1447 : in promoting memory operand to 64bit and thus causing memory mismatch. */
1448 8242531 : if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1449 : return false;
1450 :
1451 : /* Don't even try to do any aligned optimizations with volatiles. */
1452 124679 : if (MEM_VOLATILE_P (op))
1453 : return false;
1454 :
1455 118734 : if (MEM_ALIGN (op) >= 32)
1456 : return true;
1457 :
1458 46109 : op = XEXP (op, 0);
1459 :
1460 : /* Pushes and pops are only valid on the stack pointer. */
1461 46109 : if (GET_CODE (op) == PRE_DEC
1462 46109 : || GET_CODE (op) == POST_INC)
1463 : return true;
1464 :
1465 : /* Decode the address. */
1466 46109 : ok = ix86_decompose_address (op, &parts);
1467 46109 : gcc_assert (ok);
1468 :
1469 46109 : if (parts.base && SUBREG_P (parts.base))
1470 0 : parts.base = SUBREG_REG (parts.base);
1471 46109 : if (parts.index && SUBREG_P (parts.index))
1472 0 : parts.index = SUBREG_REG (parts.index);
1473 :
1474 : /* Look for some component that isn't known to be aligned. */
1475 46109 : if (parts.index)
1476 : {
1477 3272 : if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1478 : return false;
1479 : }
1480 42837 : if (parts.base)
1481 : {
1482 35855 : if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1483 : return false;
1484 : }
1485 13392 : if (parts.disp)
1486 : {
1487 13392 : if (!CONST_INT_P (parts.disp)
1488 6508 : || (INTVAL (parts.disp) & 3))
1489 13120 : return false;
1490 : }
1491 :
1492 : /* Didn't find one -- this must be an aligned address. */
1493 : return true;
1494 : })
1495 :
1496 : ;; Return true if OP is memory operand with a displacement.
1497 26354136 : (define_predicate "memory_displacement_operand"
1498 : (match_operand 0 "memory_operand")
1499 52207171 : {
1500 25853035 : struct ix86_address parts;
1501 0 : int ok;
1502 :
1503 0 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1504 0 : gcc_assert (ok);
1505 0 : return parts.disp != NULL_RTX;
1506 : })
1507 :
1508 : ;; Return true if OP is memory operand with a displacement only.
1509 0 : (define_predicate "memory_displacement_only_operand"
1510 : (match_operand 0 "memory_operand")
1511 0 : {
1512 0 : struct ix86_address parts;
1513 38807949 : int ok;
1514 :
1515 38807949 : if (TARGET_64BIT)
1516 38807949 : return false;
1517 :
1518 19137470 : ok = ix86_decompose_address (XEXP (op, 0), &parts);
1519 19137470 : gcc_assert (ok);
1520 :
1521 19137470 : if (parts.base || parts.index)
1522 : return false;
1523 :
1524 238622 : return parts.disp != NULL_RTX;
1525 : })
1526 :
1527 : ;; Return true if OP is memory operand that cannot be represented
1528 60240821 : ;; by the modRM array.
1529 : (define_predicate "long_memory_operand"
1530 99048770 : (and (match_operand 0 "memory_operand")
1531 38807949 : (match_test "memory_address_length (op, false)")))
1532 :
1533 : ;; Return true if OP is a comparison operator that can be issued by fcmov.
1534 : (define_predicate "fcmov_comparison_operator"
1535 69309 : (match_operand 0 "comparison_operator")
1536 : {
1537 0 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1538 69309 : enum rtx_code code = GET_CODE (op);
1539 :
1540 69309 : if (inmode == CCFPmode)
1541 9054 : code = ix86_fp_compare_code_to_integer (code);
1542 :
1543 : /* i387 supports just limited amount of conditional codes. */
1544 69309 : switch (code)
1545 : {
1546 1986 : case GEU: case LTU:
1547 1986 : if (inmode == CCCmode || inmode == CCGZmode)
1548 : return true;
1549 : /* FALLTHRU */
1550 6966 : case GTU: case LEU:
1551 6966 : if (inmode == CCmode || inmode == CCFPmode)
1552 : return true;
1553 : return false;
1554 : case ORDERED: case UNORDERED:
1555 : case EQ: case NE:
1556 : return true;
1557 : default:
1558 : return false;
1559 : }
1560 : })
1561 :
1562 : ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1563 69309 : ;; The first set are supported directly; the second set can't be done with
1564 : ;; full IEEE support, i.e. NaNs.
1565 138618 :
1566 69309 : (define_predicate "sse_comparison_operator"
1567 : (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1568 398784 : (and (match_test "TARGET_AVX")
1569 398784 : (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1570 514732 :
1571 : (define_predicate "ix86_comparison_int_operator"
1572 514732 : (match_code "ne,eq,ge,gt,le,lt"))
1573 216614 :
1574 : (define_predicate "ix86_comparison_uns_operator"
1575 216614 : (match_code "ne,eq,geu,gtu,leu,ltu"))
1576 :
1577 216614 : (define_predicate "bt_comparison_operator"
1578 216614 : (match_code "ne,eq"))
1579 216614 :
1580 216614 : (define_predicate "shr_comparison_operator"
1581 216614 : (match_code "gtu,leu"))
1582 216614 :
1583 216614 : (define_predicate "add_comparison_operator"
1584 : (match_code "geu,ltu"))
1585 :
1586 : (define_predicate "ieee_maxmin_comparison_operator"
1587 216614 : (match_code "lt,gt"))
1588 216614 :
1589 : ;; Return true if OP is a valid comparison operator in valid mode.
1590 : (define_predicate "ix86_comparison_operator"
1591 : (match_operand 0 "comparison_operator")
1592 111691 : {
1593 101809645 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1594 111691 : enum rtx_code code = GET_CODE (op);
1595 :
1596 101921336 : if (inmode == CCFPmode)
1597 6933912 : return ix86_trivial_fp_comparison_operator (op, mode);
1598 111691 :
1599 94875733 : switch (code)
1600 111691 : {
1601 72645591 : case EQ: case NE:
1602 72533900 : if (inmode == CCGZmode)
1603 0 : return false;
1604 : return true;
1605 4445979 : case GE: case LT:
1606 4445979 : if (inmode == CCmode || inmode == CCGCmode
1607 2477163 : || inmode == CCGOCmode || inmode == CCNOmode || inmode == CCGZmode)
1608 3932825 : return true;
1609 : return false;
1610 7845439 : case GEU: case LTU:
1611 7845439 : if (inmode == CCCmode || inmode == CCGZmode)
1612 : return true;
1613 63537225 : /* FALLTHRU */
1614 11016979 : case GTU: case LEU:
1615 11016979 : if (inmode == CCmode)
1616 9753018 : return true;
1617 52232508 : return false;
1618 3497 : case ORDERED: case UNORDERED:
1619 3497 : if (inmode == CCmode)
1620 3312 : return true;
1621 52232508 : return false;
1622 52232508 : case GT: case LE:
1623 6381543 : if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1624 5597312 : return true;
1625 : return false;
1626 834812 : default:
1627 : return false;
1628 834812 : }
1629 : })
1630 834812 :
1631 834812 : ;; Return true if OP is a valid comparison operator
1632 117427053 : ;; testing carry flag to be set.
1633 : (define_predicate "ix86_carry_flag_operator"
1634 218401886 : (match_code "ltu,unlt")
1635 101809645 : {
1636 1726421 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1637 834812 : enum rtx_code code = GET_CODE (op);
1638 :
1639 891609 : if (inmode == CCFPmode)
1640 14559 : code = ix86_fp_compare_code_to_integer (code);
1641 1379723 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1642 : return false;
1643 1379723 :
1644 694381 : return code == LTU;
1645 1379723 : })
1646 1379723 :
1647 1379723 : ;; Return true if OP is a valid comparison operator
1648 3765426 : ;; testing carry flag to be unset.
1649 : (define_predicate "ix86_carry_flag_unset_operator"
1650 3765426 : (match_code "geu,ge")
1651 1379723 : {
1652 1379723 : machine_mode inmode = GET_MODE (XEXP (op, 0));
1653 893751 : enum rtx_code code = GET_CODE (op);
1654 891609 :
1655 2142 : if (inmode == CCFPmode)
1656 93 : code = ix86_fp_compare_code_to_integer (code);
1657 : else if (inmode != CCmode && inmode != CCCmode && inmode != CCGZmode)
1658 1428 : return false;
1659 891609 :
1660 431466 : return code == GEU;
1661 1428 : })
1662 1428 :
1663 : ;; Return true if this comparison only requires testing one flag bit.
1664 2612156 : ;; VCOMX/VUCOMX set ZF, SF, OF, differently from COMI/UCOMI.
1665 : (define_predicate "ix86_trivial_fp_comparison_operator"
1666 12045273 : (if_then_else (match_test "TARGET_AVX10_2")
1667 671770 : (match_code "gt,ge,unlt,unle,eq,uneq,ne,ltgt,ordered,unordered")
1668 2142 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered")))
1669 2142 :
1670 2142 : (define_predicate "ix86_trivial_fp_comparison_operator_xf"
1671 103185020 : (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1672 :
1673 1375375 : ;; Return true if we know how to do this comparison. Others require
1674 2142 : ;; testing more than one flag bit, and we let the generic middle-end
1675 414606 : ;; code do that.
1676 414003 : (define_predicate "ix86_fp_comparison_operator"
1677 2913811 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1678 2913811 : == IX86_FPCMP_ARITH")
1679 412464 : (match_operand 0 "comparison_operator")
1680 9847723 : (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1681 412464 :
1682 9847723 : (define_predicate "ix86_fp_comparison_operator_xf"
1683 1787839 : (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1684 1375375 : == IX86_FPCMP_ARITH")
1685 : (match_operand 0 "comparison_operator")
1686 : (match_operand 0 "ix86_trivial_fp_comparison_operator_xf")))
1687 412464 :
1688 846448 : ;; Return true if we can perform this comparison on TImode operands.
1689 : (define_predicate "ix86_timode_comparison_operator"
1690 433984 : (if_then_else (match_test "TARGET_64BIT")
1691 : (match_operand 0 "ordered_comparison_operator")
1692 2501347 : (match_operand 0 "bt_comparison_operator")))
1693 :
1694 2501347 : ;; Return true if this is a valid second operand for a TImode comparison.
1695 : (define_predicate "ix86_timode_comparison_operand"
1696 154912 : (if_then_else (match_test "TARGET_64BIT")
1697 : (match_operand 0 "x86_64_general_operand")
1698 : (match_operand 0 "nonimmediate_operand")))
1699 :
1700 2035890 : ;; Nearly general operand, but accept any const_double, since we wish
1701 : ;; to be able to drop them into memory rather than have them get pulled
1702 518381 : ;; into registers.
1703 2554271 : (define_predicate "cmp_fp_expander_operand"
1704 : (ior (match_code "const_double")
1705 : (match_operand 0 "general_operand")))
1706 :
1707 4959890 : ;; Return true if this is a valid binary floating-point operation.
1708 : (define_predicate "binary_fp_operator"
1709 4959890 : (match_code "plus,minus,mult,div"))
1710 :
1711 4950813 : ;; Return true if this is a multiply operation.
1712 4950813 : (define_predicate "mult_operator"
1713 4950813 : (match_code "mult"))
1714 4950813 :
1715 4950813 : ;; Return true if this is a division operation.
1716 : (define_predicate "div_operator"
1717 : (match_code "div"))
1718 :
1719 4950813 : ;; Return true if this is an and, ior or xor operation.
1720 4950813 : (define_predicate "logic_operator"
1721 : (match_code "and,ior,xor"))
1722 :
1723 : ;; Return true if this is an and operation.
1724 16995857 : (define_predicate "and_operator"
1725 : (match_code "and"))
1726 16995857 :
1727 3408462 : ;; Return true if this is a plus, minus, and, ior or xor operation.
1728 : (define_predicate "plusminuslogic_operator"
1729 : (match_code "plus,minus,and,ior,xor"))
1730 :
1731 2708712 : ;; Return true for ARITHMETIC_P.
1732 : (define_predicate "arith_or_logical_operator"
1733 2708712 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1734 909086 : mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1735 :
1736 : ;; Return true for COMMUTATIVE_P.
1737 : (define_predicate "commutative_operator"
1738 0 : (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1739 :
1740 0 : ;; Return true if OP is a binary operator that can be promoted to wider mode.
1741 : (define_predicate "promotable_binary_operator"
1742 0 : (ior (match_code "plus,minus,and,ior,xor,ashift")
1743 0 : (and (match_code "mult")
1744 25589504 : (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1745 0 :
1746 : (define_predicate "compare_operator"
1747 : (match_code "compare"))
1748 :
1749 7600563 : (define_predicate "extract_high_operator"
1750 0 : (match_code "zero_extract,sign_extract,ashiftrt,lshiftrt")
1751 7600563 : {
1752 0 : return (const8_operand (XEXP (op, 1), VOIDmode)
1753 147692 : && (BINARY_P (op) || const8_operand (XEXP (op, 2), VOIDmode)));
1754 100 : })
1755 :
1756 147792 : ;; Return true if OP is a memory operand, aligned to
1757 0 : ;; less than its natural alignment.
1758 : (define_predicate "misaligned_operand"
1759 147692 : (and (match_code "mem")
1760 6345663 : (match_test "MEM_ALIGN (op) < GET_MODE_BITSIZE (mode)")))
1761 1601196 :
1762 147692 : ;; Return true if OP is a parallel for an mov{d,q,dqa,ps,pd} vec_select,
1763 541826 : ;; where one of the two operands of the vec_concat is const0_operand.
1764 147692 : (define_predicate "movq_parallel"
1765 2102991 : (match_code "parallel")
1766 537307 : {
1767 1955299 : unsigned nelt = XVECLEN (op, 0);
1768 1955299 : unsigned nelt2 = nelt >> 1;
1769 2102991 : unsigned i;
1770 147692 :
1771 1472886 : if (nelt < 2)
1772 : return false;
1773 :
1774 537307 : /* Validate that all of the elements are constants,
1775 537307 : lower halves of permute are lower halves of the first operand,
1776 : upper halves of permute come from any of the second operand. */
1777 15916666 : for (i = 0; i < nelt; ++i)
1778 : {
1779 6815178 : rtx er = XVECEXP (op, 0, i);
1780 2473612 : unsigned HOST_WIDE_INT ei;
1781 4341566 :
1782 2473612 : if (!CONST_INT_P (er))
1783 4341566 : return false;
1784 6815178 : ei = INTVAL (er);
1785 2473612 : if (i < nelt2 && ei != i)
1786 4341566 : return false;
1787 1216826 : if (i >= nelt2 && (ei < nelt || ei >= nelt << 1))
1788 4341566 : return false;
1789 4341566 : }
1790 4341566 :
1791 4341566 : return true;
1792 4341566 : })
1793 4341566 :
1794 4341566 : ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1795 5759558 : (define_predicate "vzeroall_operation"
1796 4341566 : (match_code "parallel")
1797 7177550 : {
1798 1418011 : unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1799 0 :
1800 3896 : if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1801 4341566 : return false;
1802 4341566 :
1803 69976 : for (i = 0; i < nregs; i++)
1804 : {
1805 62184 : rtx elt = XVECEXP (op, 0, i+1);
1806 :
1807 4403750 : if (GET_CODE (elt) != SET
1808 4403750 : || GET_CODE (SET_DEST (elt)) != REG
1809 62184 : || GET_MODE (SET_DEST (elt)) != V8SImode
1810 62184 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
1811 124368 : || SET_SRC (elt) != CONST0_RTX (V8SImode))
1812 979812 : return false;
1813 : }
1814 979812 : return true;
1815 : })
1816 328791 :
1817 328791 : ;; return true if OP is a vzeroall pattern.
1818 332687 : (define_predicate "vzeroall_pattern"
1819 328791 : (and (match_code "parallel")
1820 336583 : (match_code "unspec_volatile" "a")
1821 4009 : (match_test "XINT (XVECEXP (op, 0, 0), 1) == UNSPECV_VZEROALL")))
1822 0 :
1823 328791 : ;; return true if OP is a vzeroupper pattern.
1824 328791 : (define_predicate "vzeroupper_pattern"
1825 328791 : (and (match_code "parallel")
1826 4215719 : (match_code "unspec" "b")
1827 4610 : (match_test "XINT (XVECEXP (op, 0, 1), 1) == UNSPEC_CALLEE_ABI")
1828 4215719 : (match_test "INTVAL (XVECEXP (XVECEXP (op, 0, 1), 0, 0)) == ABI_VZEROUPPER")))
1829 0 :
1830 328791 : ;; Return true if OP is an addsub vec_merge operation
1831 : (define_predicate "addsub_vm_operator"
1832 : (match_code "vec_merge")
1833 8491 : {
1834 25597995 : rtx op0, op1;
1835 8491 : int swapped;
1836 25589504 : HOST_WIDE_INT mask;
1837 8491 : int nunits, elt;
1838 :
1839 8491 : op0 = XEXP (op, 0);
1840 8491 : op1 = XEXP (op, 1);
1841 :
1842 : /* Sanity check. */
1843 8491 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1844 : swapped = 0;
1845 4334 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1846 : swapped = 1;
1847 : else
1848 0 : gcc_unreachable ();
1849 :
1850 8491 : mask = INTVAL (XEXP (op, 2));
1851 8491 : nunits = GET_MODE_NUNITS (mode);
1852 :
1853 32847 : for (elt = 0; elt < nunits; elt++)
1854 : {
1855 : /* bit clear: take from op0, set: take from op1 */
1856 24602 : int bit = !(mask & (HOST_WIDE_INT_1U << elt));
1857 :
1858 24602 : if (bit != ((elt & 1) ^ swapped))
1859 : return false;
1860 : }
1861 :
1862 : return true;
1863 : })
1864 :
1865 : ;; Return true if OP is an addsub vec_select/vec_concat operation
1866 8491 : (define_predicate "addsub_vs_operator"
1867 : (and (match_code "vec_select")
1868 8491 : (match_code "vec_concat" "0"))
1869 16736 : {
1870 8245 : rtx op0, op1;
1871 0 : bool swapped;
1872 0 : int nunits, elt;
1873 :
1874 0 : op0 = XEXP (XEXP (op, 0), 0);
1875 0 : op1 = XEXP (XEXP (op, 0), 1);
1876 :
1877 : /* Sanity check. */
1878 0 : if (GET_CODE (op0) == MINUS && GET_CODE (op1) == PLUS)
1879 : swapped = false;
1880 0 : else if (GET_CODE (op0) == PLUS && GET_CODE (op1) == MINUS)
1881 : swapped = true;
1882 : else
1883 0 : gcc_unreachable ();
1884 :
1885 0 : nunits = GET_MODE_NUNITS (mode);
1886 0 : if (XVECLEN (XEXP (op, 1), 0) != nunits)
1887 : return false;
1888 :
1889 : /* We already checked that permutation is suitable for addsub,
1890 : so only look at the first element of the parallel. */
1891 0 : elt = INTVAL (XVECEXP (XEXP (op, 1), 0, 0));
1892 :
1893 0 : return elt == (swapped ? nunits : 0);
1894 : })
1895 :
1896 : ;; Return true if OP is a parallel for an addsub vec_select.
1897 0 : (define_predicate "addsub_vs_parallel"
1898 : (and (match_code "parallel")
1899 0 : (match_code "const_int" "a"))
1900 0 : {
1901 0 : int nelt = XVECLEN (op, 0);
1902 493 : int elt, i;
1903 :
1904 493 : if (nelt < 2)
1905 493 : return false;
1906 :
1907 : /* Check that the permutation is suitable for addsub.
1908 : For example, { 0 9 2 11 4 13 6 15 } or { 8 1 10 3 12 5 14 7 }. */
1909 493 : elt = INTVAL (XVECEXP (op, 0, 0));
1910 493 : if (elt == 0)
1911 : {
1912 447 : for (i = 1; i < nelt; ++i)
1913 439 : if (INTVAL (XVECEXP (op, 0, i)) != (i + (i & 1) * nelt))
1914 : return false;
1915 : }
1916 54 : else if (elt == nelt)
1917 : {
1918 0 : for (i = 1; i < nelt; ++i)
1919 0 : if (INTVAL (XVECEXP (op, 0, i)) != (elt + i - (i & 1) * nelt))
1920 : return false;
1921 : }
1922 : else
1923 : return false;
1924 :
1925 : return true;
1926 : })
1927 :
1928 : ;; Return true if OP is a constant pool in perm{w,d,b} which contains index
1929 493 : ;; match pmov{dw,wb,qd}.
1930 : (define_predicate "permvar_truncate_operand"
1931 493 : (match_code "mem")
1932 986 : {
1933 0 : int nelt = GET_MODE_NUNITS (mode);
1934 16 : int perm[128];
1935 16 : int id;
1936 :
1937 32 : if (!INTEGRAL_MODE_P (mode) || !VECTOR_MODE_P (mode))
1938 : return false;
1939 :
1940 16 : if (nelt < 2)
1941 : return false;
1942 :
1943 16 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1944 : return false;
1945 :
1946 16 : id = exact_log2 (nelt);
1947 :
1948 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
1949 : For example V16HImode to V8HImode
1950 : { 0 2 4 6 8 10 12 14 * * * * * * * * }. */
1951 232 : for (int i = 0; i != nelt / 2; i++)
1952 216 : if ((perm[i] & ((1 << id) - 1)) != i * 2)
1953 : return false;
1954 :
1955 : return true;
1956 : })
1957 :
1958 : ;; Return true if OP is a constant pool in shufb which contains index
1959 49 : ;; match pmovdw.
1960 : (define_predicate "pshufb_truncv4siv4hi_operand"
1961 16 : (match_code "mem")
1962 65 : {
1963 16 : int perm[128];
1964 :
1965 8 : if (mode != E_V16QImode)
1966 : return false;
1967 8 :
1968 8 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1969 : return false;
1970 :
1971 : /* Check that the permutation is suitable for pmovdw.
1972 : For example V4SImode to V4HImode
1973 : { 0 1 4 5 8 9 12 13 * * * * * * * * }.
1974 : index = i % 2 + (i / 2) * 4. */
1975 58 : for (int i = 0; i != 8; i++)
1976 : {
1977 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
1978 52 : if (perm[i] & 128)
1979 : return false;
1980 :
1981 52 : if ((perm[i] & 15) != ((i & 1) + (i & 0xFE) * 2))
1982 : return false;
1983 : }
1984 :
1985 : return true;
1986 : })
1987 :
1988 : ;; Return true if OP is a constant pool in shufb which contains index
1989 11 : ;; match pmovdw.
1990 : (define_predicate "pshufb_truncv8hiv8qi_operand"
1991 8 : (match_code "mem")
1992 17 : {
1993 6 : int perm[128];
1994 :
1995 11 : if (mode != E_V16QImode)
1996 : return false;
1997 11 :
1998 11 : if (!ix86_extract_perm_from_pool_constant (&perm[0], op))
1999 : return false;
2000 :
2001 : /* Check that the permutation is suitable for pmovwb.
2002 : For example V16QImode to V8QImode
2003 : { 0 2 4 6 8 10 12 14 * * * * * * * * }.
2004 : index = i % 2 + (i / 2) * 4. */
2005 57 : for (int i = 0; i != 8; i++)
2006 : {
2007 : /* if (SRC2[(i * 8)+7] = 1) then DEST[(i*8)+7..(i*8)+0] := 0; */
2008 52 : if (perm[i] & 128)
2009 : return false;
2010 :
2011 52 : if ((perm[i] & 15) != i * 2)
2012 : return false;
2013 : }
2014 :
2015 : return true;
2016 : })
2017 :
2018 : ;; Return true if OP is a parallel for an pmovz{bw,wd,dq} vec_select,
2019 14 : ;; where one of the two operands of the vec_concat is const0_operand.
2020 : (define_predicate "pmovzx_parallel"
2021 11 : (and (match_code "parallel")
2022 19 : (match_code "const_int" "a"))
2023 5 : {
2024 1489603 : int nelt = XVECLEN (op, 0);
2025 1489603 : int elt, i;
2026 :
2027 1489603 : if (nelt < 2)
2028 : return false;
2029 :
2030 : /* Check that the permutation is suitable for pmovz{bw,wd,dq}.
2031 : For example { 0 16 1 17 2 18 3 19 4 20 5 21 6 22 7 23 }. */
2032 1489601 : elt = INTVAL (XVECEXP (op, 0, 0));
2033 1489601 : if (elt == 0)
2034 : {
2035 3453711 : for (i = 1; i < nelt; ++i)
2036 2959669 : if ((i & 1) != 0)
2037 : {
2038 1898517 : if (INTVAL (XVECEXP (op, 0, i)) < nelt)
2039 : return false;
2040 : }
2041 1061152 : else if (INTVAL (XVECEXP (op, 0, i)) != i / 2)
2042 : return false;
2043 : }
2044 : else
2045 : return false;
2046 :
2047 : return true;
2048 : })
2049 :
2050 : ;; Return true if OP is a parallel for an insertps vec_select,
2051 1489603 : ;; where one of the two operands of the vec_concat is const0_operand.
2052 : (define_predicate "insertps_parallel"
2053 1489603 : (and (match_code "parallel")
2054 2979206 : (match_code "const_int" "a"))
2055 0 : {
2056 12762 : int i;
2057 :
2058 12762 : if (XVECLEN (op, 0) != 4)
2059 12762 : return false;
2060 :
2061 : /* One element in [0..3], and the other 3 in [4..7]. */
2062 : bool found = false;
2063 41134 : for (i = 0; i < 4; ++i)
2064 39515 : if (INTVAL (XVECEXP (op, 0, i)) < 4)
2065 : {
2066 23905 : if (found)
2067 : return false;
2068 : found = true;
2069 : }
2070 :
2071 : return found;
2072 : })
2073 :
2074 : ;; Return true if OP is a const vector with duplicate value.
2075 12762 : (define_predicate "const_vector_duplicate_operand"
2076 : (match_code "const_vector")
2077 12762 : {
2078 25524 : rtx elt = XVECEXP (op, 0, 0);
2079 0 : int i, nelt = XVECLEN (op, 0);
2080 :
2081 96 : for (i = 1; i < nelt; ++i)
2082 93 : if (!rtx_equal_p (elt, XVECEXP (op, 0, i)))
2083 3 : return false;
2084 : return true;
2085 : })
2086 :
2087 : ;; Return true if OP is a parallel for a vbroadcast permute.
2088 3 : (define_predicate "avx_vbroadcast_operand"
2089 : (and (match_code "parallel")
2090 3 : (match_code "const_int" "a"))
2091 6 : {
2092 3 : rtx elt = XVECEXP (op, 0, 0);
2093 439079 : int i, nelt = XVECLEN (op, 0);
2094 :
2095 : /* Don't bother checking there are the right number of operands,
2096 439079 : merely that they're all identical. */
2097 550334 : for (i = 1; i < nelt; ++i)
2098 285452 : if (XVECEXP (op, 0, i) != elt)
2099 : return false;
2100 : return true;
2101 : })
2102 :
2103 : ;; Return true if OP is a parallel for a vbroadcastf128 permute.
2104 439079 : (define_predicate "avx_vbroadcast128_operand"
2105 : (and (match_code "parallel")
2106 439079 : (match_code "const_int" "a"))
2107 878158 : {
2108 0 : int i, nelt = XVECLEN (op, 0);
2109 1406280 : int half = nelt / 2;
2110 :
2111 2343238 : for (i = 0; i < nelt; ++i)
2112 1406280 : {
2113 2343088 : int index = INTVAL (XVECEXP (op, 0, i));
2114 2343088 : if ((i < half && index != i)
2115 1097631 : || (i >= half && index != (i - half)))
2116 : return false;
2117 : }
2118 :
2119 : return true;
2120 : })
2121 :
2122 : ;; Return true if OP is a parallel for a palignr permute.
2123 1406280 : (define_predicate "palignr_operand"
2124 : (and (match_code "parallel")
2125 1406280 : (match_code "const_int" "a"))
2126 2812560 : {
2127 0 : int elt = INTVAL (XVECEXP (op, 0, 0));
2128 27263 : int i, nelt = XVECLEN (op, 0);
2129 :
2130 : /* Check that an order in the permutation is suitable for palignr.
2131 27263 : For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */
2132 62800 : for (i = 1; i < nelt; ++i)
2133 58963 : if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt))
2134 : return false;
2135 : return true;
2136 : })
2137 :
2138 : ;; Return true if OP is a proper third operand to vpblendw256.
2139 27263 : (define_predicate "avx2_pblendw_operand"
2140 : (match_code "const_int")
2141 27263 : {
2142 54526 : HOST_WIDE_INT val = INTVAL (op);
2143 0 : HOST_WIDE_INT low = val & 0xff;
2144 7035 : return val == ((low << 8) | low);
2145 : })
2146 :
2147 7035 : ;; Return true if OP is vector_operand or CONST_VECTOR.
2148 7035 : (define_predicate "general_vector_operand"
2149 : (ior (match_operand 0 "vector_operand")
2150 7035 : (match_code "const_vector")))
2151 7035 :
2152 : ;; Return true if OP is either -1 constant or stored in register.
2153 : (define_predicate "register_or_constm1_operand"
2154 : (ior (match_operand 0 "register_operand")
2155 13176 : (and (match_code "const_int")
2156 0 : (match_test "op == constm1_rtx"))))
2157 13176 :
2158 2471 : ;; Return true if the vector ends with between 12 and 18 register saves using
2159 : ;; RAX as the base address.
2160 : (define_predicate "save_multiple"
2161 225505 : (match_code "parallel")
2162 1324 : {
2163 225505 : const unsigned len = XVECLEN (op, 0);
2164 1324 : unsigned i;
2165 :
2166 : /* Starting from end of vector, count register saves. */
2167 318214 : for (i = 0; i < len; ++i)
2168 : {
2169 318214 : rtx src, dest, addr;
2170 318214 : rtx e = XVECEXP (op, 0, len - 1 - i);
2171 :
2172 318214 : if (GET_CODE (e) != SET)
2173 : break;
2174 :
2175 311169 : src = SET_SRC (e);
2176 311169 : dest = SET_DEST (e);
2177 :
2178 311169 : if (!REG_P (src) || !MEM_P (dest))
2179 : break;
2180 :
2181 92709 : addr = XEXP (dest, 0);
2182 :
2183 : /* Good if dest address is in RAX. */
2184 92709 : if (REG_P (addr) && REGNO (addr) == AX_REG)
2185 4202 : continue;
2186 :
2187 : /* Good if dest address is offset of RAX. */
2188 177014 : if (GET_CODE (addr) == PLUS
2189 88507 : && REG_P (XEXP (addr, 0))
2190 177014 : && REGNO (XEXP (addr, 0)) == AX_REG)
2191 88507 : continue;
2192 :
2193 : break;
2194 : }
2195 225505 : return (i >= 12 && i <= 18);
2196 : })
2197 :
2198 :
2199 225505 : ;; Return true if the vector ends with between 12 and 18 register loads using
2200 : ;; RSI as the base address.
2201 451010 : (define_predicate "restore_multiple"
2202 225505 : (match_code "parallel")
2203 0 : {
2204 7821125 : const unsigned len = XVECLEN (op, 0);
2205 7821125 : unsigned i;
2206 :
2207 7821125 : /* Starting from end of vector, count register restores. */
2208 7927453 : for (i = 0; i < len; ++i)
2209 : {
2210 7927453 : rtx src, dest, addr;
2211 7927453 : rtx e = XVECEXP (op, 0, len - 1 - i);
2212 :
2213 7927453 : if (GET_CODE (e) != SET)
2214 : break;
2215 :
2216 4444594 : src = SET_SRC (e);
2217 4444594 : dest = SET_DEST (e);
2218 :
2219 4444594 : if (!MEM_P (src) || !REG_P (dest))
2220 : break;
2221 :
2222 1333409 : addr = XEXP (src, 0);
2223 :
2224 : /* Good if src address is in RSI. */
2225 1333409 : if (REG_P (addr) && REGNO (addr) == SI_REG)
2226 5129 : continue;
2227 :
2228 : /* Good if src address is offset of RSI. */
2229 1429479 : if (GET_CODE (addr) == PLUS
2230 897772 : && REG_P (XEXP (addr, 0))
2231 2162145 : && REGNO (XEXP (addr, 0)) == SI_REG)
2232 101199 : continue;
2233 :
2234 : break;
2235 : }
2236 7821125 : return (i >= 12 && i <= 18);
2237 : })
2238 :
2239 : ;; Keylocker specific predicates
2240 7821125 : (define_predicate "encodekey128_operation"
2241 : (match_code "parallel")
2242 15642250 : {
2243 7821125 : unsigned i;
2244 0 : rtx elt;
2245 :
2246 108 : if (XVECLEN (op, 0) != 8)
2247 : return false;
2248 108 :
2249 392 : for(i = 0; i < 3; i++)
2250 : {
2251 294 : elt = XVECEXP (op, 0, i + 1);
2252 294 : if (GET_CODE (elt) != SET
2253 294 : || GET_CODE (SET_DEST (elt)) != REG
2254 294 : || GET_MODE (SET_DEST (elt)) != V2DImode
2255 294 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2256 294 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2257 294 : || GET_MODE (SET_SRC (elt)) != V2DImode
2258 294 : || XVECLEN(SET_SRC (elt), 0) != 1
2259 588 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2260 : return false;
2261 : }
2262 :
2263 392 : for(i = 4; i < 7; i++)
2264 : {
2265 294 : elt = XVECEXP (op, 0, i);
2266 294 : if (GET_CODE (elt) != CLOBBER
2267 294 : || GET_MODE (elt) != VOIDmode
2268 294 : || GET_CODE (XEXP (elt, 0)) != REG
2269 294 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2270 588 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2271 : return false;
2272 : }
2273 :
2274 98 : elt = XVECEXP (op, 0, 7);
2275 98 : if (GET_CODE (elt) != CLOBBER
2276 98 : || GET_MODE (elt) != VOIDmode
2277 98 : || GET_CODE (XEXP (elt, 0)) != REG
2278 98 : || GET_MODE (XEXP (elt, 0)) != CCmode
2279 196 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2280 0 : return false;
2281 : return true;
2282 : })
2283 :
2284 : (define_predicate "encodekey256_operation"
2285 108 : (match_code "parallel")
2286 : {
2287 337 : unsigned i;
2288 108 : rtx elt;
2289 0 :
2290 121 : if (XVECLEN (op, 0) != 9)
2291 : return false;
2292 :
2293 121 : elt = SET_SRC (XVECEXP (op, 0, 0));
2294 112 : elt = XVECEXP (elt, 0, 2);
2295 112 : if (!REG_P (elt)
2296 112 : || REGNO(elt) != GET_SSE_REGNO (1))
2297 : return false;
2298 :
2299 560 : for(i = 0; i < 4; i++)
2300 : {
2301 448 : elt = XVECEXP (op, 0, i + 1);
2302 448 : if (GET_CODE (elt) != SET
2303 448 : || GET_CODE (SET_DEST (elt)) != REG
2304 448 : || GET_MODE (SET_DEST (elt)) != V2DImode
2305 448 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2306 448 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2307 448 : || GET_MODE (SET_SRC (elt)) != V2DImode
2308 448 : || XVECLEN(SET_SRC (elt), 0) != 1
2309 896 : || XVECEXP(SET_SRC (elt), 0, 0) != const0_rtx)
2310 : return false;
2311 : }
2312 :
2313 448 : for(i = 4; i < 7; i++)
2314 : {
2315 336 : elt = XVECEXP (op, 0, i + 1);
2316 336 : if (GET_CODE (elt) != CLOBBER
2317 336 : || GET_MODE (elt) != VOIDmode
2318 336 : || GET_CODE (XEXP (elt, 0)) != REG
2319 336 : || GET_MODE (XEXP (elt, 0)) != V2DImode
2320 672 : || REGNO (XEXP (elt, 0)) != GET_SSE_REGNO (i))
2321 : return false;
2322 : }
2323 :
2324 112 : elt = XVECEXP (op, 0, 8);
2325 112 : if (GET_CODE (elt) != CLOBBER
2326 112 : || GET_MODE (elt) != VOIDmode
2327 112 : || GET_CODE (XEXP (elt, 0)) != REG
2328 112 : || GET_MODE (XEXP (elt, 0)) != CCmode
2329 224 : || REGNO (XEXP (elt, 0)) != FLAGS_REG)
2330 0 : return false;
2331 : return true;
2332 : })
2333 :
2334 :
2335 121 : (define_predicate "aeswidekl_operation"
2336 : (match_code "parallel")
2337 242 : {
2338 121 : unsigned i;
2339 0 : rtx elt;
2340 :
2341 5796 : for (i = 0; i < 8; i++)
2342 : {
2343 660 : elt = XVECEXP (op, 0, i + 1);
2344 5168 : if (GET_CODE (elt) != SET
2345 5168 : || GET_CODE (SET_DEST (elt)) != REG
2346 5168 : || GET_MODE (SET_DEST (elt)) != V2DImode
2347 5168 : || REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
2348 5168 : || GET_CODE (SET_SRC (elt)) != UNSPEC_VOLATILE
2349 5168 : || GET_MODE (SET_SRC (elt)) != V2DImode
2350 5168 : || XVECLEN (SET_SRC (elt), 0) != 1
2351 5168 : || !REG_P (XVECEXP (SET_SRC (elt), 0, 0))
2352 10304 : || REGNO (XVECEXP (SET_SRC (elt), 0, 0)) != GET_SSE_REGNO (i))
2353 : return false;
2354 : }
2355 : return true;
2356 : })
2357 :
2358 : ;; Return true if OP is a memory operand that can be also used in APX
2359 660 : ;; EVEX-encoded patterns (i.e. APX NDD/NF) with immediate operand. With
2360 : ;; non-default address space, segment register or address size prefix,
2361 1320 : ;; APX EVEX-encoded instruction length can exceed the 15 byte size limit.
2362 660 : (define_predicate "apx_evex_memory_operand"
2363 0 : (match_operand 0 "memory_operand")
2364 : {
2365 : /* OK if immediate operand size < 4 bytes. */
2366 1686 : if (GET_MODE_SIZE (mode) < 4)
2367 1686 : return true;
2368 :
2369 1527 : bool default_addr = ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (op));
2370 1695 : bool address_size_prefix = TARGET_X32 && Pmode == SImode;
2371 :
2372 1527 : struct ix86_address parts;
2373 1527 : int ok;
2374 :
2375 1527 : op = XEXP (op, 0);
2376 1527 : ok = ix86_decompose_address (op, &parts);
2377 1527 : gcc_assert (ok);
2378 :
2379 1527 : if (default_addr)
2380 : {
2381 : /* Default address space. */
2382 :
2383 : /* Not OK with address size prefix, index register and disp. */
2384 691 : if (address_size_prefix
2385 168 : && parts.index
2386 42 : && parts.disp
2387 42 : && parts.disp != const0_rtx)
2388 42 : return false;
2389 : }
2390 : else
2391 : {
2392 : /* Non-default address space. */
2393 :
2394 : /* Not OK without base register. */
2395 836 : if (!parts.base)
2396 : return false;
2397 :
2398 : /* Not OK with disp and address size prefix. */
2399 668 : if (address_size_prefix && parts.disp)
2400 0 : return false;
2401 : }
2402 :
2403 : return true;
2404 : })
2405 :
2406 : ;; Return true if OP is a memory operand which can be used in APX EVEX-encoded
2407 1804 : ;; ADD patterns (i.e. APX NDD/NF) for with register source operand.
2408 : ;; UNSPEC_GOTNTPOFF memory operand is allowed with APX EVEX-encoded ADD only if
2409 3490 : ;; R_X86_64_CODE_6_GOTTPOFF works.
2410 1686 : (define_predicate "apx_evex_add_memory_operand"
2411 : (match_operand 0 "memory_operand")
2412 : {
2413 : /* OK if "add %reg1, name@gottpoff(%rip), %reg2" or
2414 : "{nf} add name@gottpoff(%rip), %reg1" are supported. */
2415 : if (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF)
2416 : return true;
2417 :
2418 : op = XEXP (op, 0);
2419 :
2420 : /* Disallow APX EVEX-encoded ADD with UNSPEC_GOTNTPOFF. */
2421 : if (GET_CODE (op) == CONST
2422 : && GET_CODE (XEXP (op, 0)) == UNSPEC
2423 : && XINT (XEXP (op, 0), 1) == UNSPEC_GOTNTPOFF)
2424 : return false;
2425 :
2426 : return true;
2427 : })
2428 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2429 : /* (content generated from coverage data) */
2430 848 : /* BEGIN: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2431 : /* ... */
2432 848 : /* ... */
2433 848 : /* ... */
2434 : /* END: function "_Z27apx_evex_add_memory_operandP7rtx_def12machine_mode" */
2435 : /* ... */
2436 : /* ... */
2437 1007202535 : /* BEGIN: function "_Z19lookup_constraint_1PKc" */
2438 : /* ... */
2439 1007202535 : /* ... */
2440 : /* ... */
2441 : /* ... */
2442 : /* ... */
2443 0 : /* ... */
2444 0 : /* ... */
2445 0 : /* ... */
2446 0 : /* ... */
2447 0 : /* ... */
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2449 597213193 : /* (content generated from coverage data) */
2450 597213193 : /* ... */
2451 : /* ... */
2452 : /* ... */
2453 8692461 : /* ... */
2454 : /* ... */
2455 136584542 : /* ... */
2456 : /* ... */
2457 136889 : /* ... */
2458 : /* ... */
2459 1719912 : /* ... */
2460 : /* ... */
2461 1430963 : /* ... */
2462 : /* ... */
2463 56858135 : /* ... */
2464 : /* ... */
2465 51902276 : /* ... */
2466 : /* ... */
2467 102923637 : /* ... */
2468 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2469 39586055 : /* (content generated from coverage data) */
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2521 5444 : /* ... */
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2523 341594 : /* ... */
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2525 2716877 : /* ... */
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2527 272293 : /* ... */
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2529 1418 : /* (content generated from coverage data) */
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2541 9632027 : /* ... */
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2543 1351884 : /* ... */
2544 : /* ... */
2545 1372893 : /* ... */
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2547 19928 : /* ... */
2548 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2549 196134431 : /* (content generated from coverage data) */
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2551 1186707 : /* ... */
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2553 142380758 : /* ... */
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2555 3150243 : /* ... */
2556 : /* ... */
2557 474067 : /* ... */
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2561 0 : /* ... */
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2564 0 : /* ... */
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2567 0 : /* ... */
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2576 0 : /* ... */
2577 8714200 : /* ... */
2578 8714200 : /* ... */
2579 : /* ... */
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2581 1345877 : /* ... */
2582 : /* ... */
2583 0 : /* ... */
2584 : /* ... */
2585 0 : /* ... */
2586 : /* ... */
2587 0 : /* ... */
2588 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2589 0 : /* (content generated from coverage data) */
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2592 : /* ... */
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2594 : /* ... */
2595 8285 : /* ... */
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2597 6175696 : /* ... */
2598 : /* ... */
2599 157021 : /* ... */
2600 : /* ... */
2601 268036 : /* ... */
2602 : /* ... */
2603 3440 : /* ... */
2604 : /* ... */
2605 0 : /* ... */
2606 : /* ... */
2607 0 : /* ... */
2608 0 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2632 0 : /* ... */
2633 0 : /* ... */
2634 0 : /* ... */
2635 : /* ... */
2636 : /* ... */
2637 1337 : /* ... */
2638 : /* END: function "_Z19lookup_constraint_1PKc" */
2639 : /* ... */
2640 : /* ... */
2641 : /* ... */
2642 : /* ... */
2643 : /* ... */
2644 : /* ... */
2645 : /* ... */
2646 : /* ... */
2647 : /* ... */
2648 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2662 : /* ... */
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2681 : /* ... */
2682 : /* ... */
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2684 : /* ... */
2685 : /* ... */
2686 : /* ... */
2687 : /* ... */
2688 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2689 : /* (content generated from coverage data) */
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2691 : /* ... */
2692 : /* ... */
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2694 : /* ... */
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2696 : /* ... */
2697 : /* ... */
2698 : /* ... */
2699 : /* ... */
2700 : /* ... */
2701 : /* ... */
2702 : /* ... */
2703 : /* ... */
2704 : /* ... */
2705 : /* ... */
2706 : /* ... */
2707 : /* ... */
2708 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2709 : /* (content generated from coverage data) */
2710 : /* ... */
2711 : /* ... */
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2713 : /* ... */
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2720 : /* ... */
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2722 : /* ... */
2723 : /* ... */
2724 : /* ... */
2725 : /* ... */
2726 : /* ... */
2727 : /* ... */
2728 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2729 : /* (content generated from coverage data) */
2730 : /* ... */
2731 : /* ... */
2732 : /* ... */
2733 : /* ... */
2734 : /* ... */
2735 : /* ... */
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2738 : /* ... */
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2740 : /* ... */
2741 : /* ... */
2742 : /* ... */
2743 : /* ... */
2744 : /* ... */
2745 : /* ... */
2746 : /* ... */
2747 : /* ... */
2748 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
2749 : /* (content generated from coverage data) */
2750 : /* ... */
2751 : /* ... */
2752 : /* ... */
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2754 : /* ... */
2755 : /* ... */
2756 : /* ... */
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2900 7387334152 : /* BEGIN: function "_Z26reg_class_for_constraint_114constraint_num" */
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2902 7387334152 : /* ... */
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2906 136128052 : /* ... */
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2923 243765407 : /* ... */
2924 1517227606 : /* ... */
2925 14356 : /* ... */
2926 9631252 : /* ... */
2927 1296384 : /* ... */
2928 0 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
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2937 129965 : /* ... */
2938 6174917 : /* ... */
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2940 : /* ... */
2941 : /* ... */
2942 : /* END: function "_Z26reg_class_for_constraint_114constraint_num" */
2943 : /* ... */
2944 : /* ... */
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3005 : /* ... */
3006 7212084 : /* END: function "_Z32insn_const_int_ok_for_constraintl14constraint_num" */
3007 : /* ... */
3008 7212084 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/predicates.md not long enough */
3009 : /* (content generated from coverage data) */
3010 1343850 : /* ... */
3011 1343850 : /* ... */
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