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1 : : ;; GCC machine description for AVX512F instructions
2 : : ;; Copyright (C) 2013-2024 Free Software Foundation, Inc.
3 : : ;;
4 : : ;; This file is part of GCC.
5 : : ;;
6 : : ;; GCC is free software; you can redistribute it and/or modify
7 : : ;; it under the terms of the GNU General Public License as published by
8 : : ;; the Free Software Foundation; either version 3, or (at your option)
9 : : ;; any later version.
10 : : ;;
11 : : ;; GCC is distributed in the hope that it will be useful,
12 : : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : : ;; GNU General Public License for more details.
15 : : ;;
16 : : ;; You should have received a copy of the GNU General Public License
17 : : ;; along with GCC; see the file COPYING3. If not see
18 : : ;; <http://www.gnu.org/licenses/>.
19 : :
20 : : ;; Some iterators for extending subst as much as possible
21 : : ;; All vectors (Use it for destination)
22 : : (define_mode_iterator SUBST_V
23 : : [V64QI V32QI V16QI
24 : : V32HI V16HI V8HI
25 : : V16SI V8SI V4SI
26 : : V8DI V4DI V2DI
27 : : V32HF V16HF V8HF
28 : : V32BF V16BF V8BF
29 : : V16SF V8SF V4SF
30 : : V8DF V4DF V2DF])
31 : :
32 : : (define_mode_iterator SUBST_CV
33 : : [V32HF V16HF V8HF])
34 : :
35 : : (define_mode_iterator SUBST_S
36 : : [QI HI SI DI])
37 : :
38 : : (define_mode_iterator SUBST_A
39 : : [V64QI V32QI V16QI
40 : : V32HI V16HI V8HI
41 : : V16SI V8SI V4SI
42 : : V8DI V4DI V2DI
43 : : V32HF V16HF V8HF
44 : : V16SF V8SF V4SF
45 : : V8DF V4DF V2DF
46 : : QI HI SI DI SF DF])
47 : :
48 : : (define_subst_attr "mask_name" "mask" "" "_mask")
49 : : (define_subst_attr "maskc_name" "maskc" "" "_mask")
50 : : (define_subst_attr "mask_applied" "mask" "false" "true")
51 : : (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
52 : : (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
53 : : (define_subst_attr "maskc_operand3" "maskc" "" "%{%4%}%N3")
54 : : (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
55 : : (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
56 : : (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
57 : : (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
58 : : (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
59 : : (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
60 : : (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
61 : : (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
62 : : (define_subst_attr "mask_codefor" "mask" "*" "")
63 : : (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
64 : : (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
65 : : (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
66 : : (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
67 : : (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
68 : : (define_subst_attr "mask_prefix" "mask" "vex" "evex")
69 : : (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
70 : : (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex")
71 : : (define_subst_attr "bcst_mask_prefix3" "mask" "orig,maybe_evex" "evex,evex")
72 : : (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex")
73 : : (define_subst_attr "bcst_mask_prefix4" "mask" "orig,orig,maybe_evex" "evex,evex,evex")
74 : : (define_subst_attr "mask_expand_op3" "mask" "3" "5")
75 : : (define_subst_attr "mask3_dest_false_dep_for_glc_cond" "mask" "1" "operands[3] == CONST0_RTX(<MODE>mode)")
76 : : (define_subst_attr "mask4_dest_false_dep_for_glc_cond" "mask" "1" "operands[4] == CONST0_RTX(<MODE>mode)")
77 : : (define_subst_attr "mask6_dest_false_dep_for_glc_cond" "mask" "1" "operands[6] == CONST0_RTX(<MODE>mode)")
78 : : (define_subst_attr "mask10_dest_false_dep_for_glc_cond" "mask" "1" "operands[10] == CONST0_RTX(<MODE>mode)")
79 : : (define_subst_attr "maskc_dest_false_dep_for_glc_cond" "maskc" "1" "operands[3] == CONST0_RTX(<MODE>mode)")
80 : :
81 : : (define_subst "mask"
82 : : [(set (match_operand:SUBST_V 0)
83 : : (match_operand:SUBST_V 1))]
84 : 187245 : "TARGET_AVX512F"
85 : : [(set (match_dup 0)
86 : : (vec_merge:SUBST_V
87 : : (match_dup 1)
88 : : (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
89 : : (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
90 : :
91 : : (define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask")
92 : : (define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}")
93 : : (define_subst "merge_mask"
94 : : [(set (match_operand:SUBST_V 0)
95 : : (match_operand:SUBST_V 1))]
96 : 0 : "TARGET_AVX512F"
97 : : [(set (match_dup 0)
98 : : (vec_merge:SUBST_V
99 : : (match_dup 1)
100 : : (match_dup 0)
101 : : (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))])
102 : :
103 : : (define_subst "maskc"
104 : : [(set (match_operand:SUBST_CV 0)
105 : : (match_operand:SUBST_CV 1))]
106 : 2442 : "TARGET_AVX512F"
107 : : [(set (match_dup 0)
108 : : (vec_merge:SUBST_CV
109 : : (match_dup 1)
110 : : (match_operand:SUBST_CV 2 "nonimm_or_0_operand" "0C")
111 : : (unspec:<avx512fmaskmode>
112 : : [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
113 : : UNSPEC_COMPLEX_MASK)))])
114 : :
115 : : (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
116 : : (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
117 : : (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
118 : :
119 : : (define_subst "mask_scalar_merge"
120 : : [(set (match_operand:SUBST_S 0)
121 : : (match_operand:SUBST_S 1))]
122 : 16529 : "TARGET_AVX512F"
123 : : [(set (match_dup 0)
124 : : (and:SUBST_S
125 : : (match_dup 1)
126 : : (match_operand:SUBST_S 3 "register_operand" "Yk")))])
127 : :
128 : : (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
129 : : (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
130 : : (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
131 : : (define_subst_attr "sd_mask_codefor" "sd" "*" "")
132 : : (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
133 : :
134 : : (define_subst "sd"
135 : : [(set (match_operand:SUBST_V 0)
136 : : (match_operand:SUBST_V 1))]
137 : : ""
138 : : [(set (match_dup 0)
139 : : (vec_merge:SUBST_V
140 : : (match_dup 1)
141 : : (match_operand:SUBST_V 2 "const0_operand")
142 : : (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
143 : : ])
144 : :
145 : : (define_subst_attr "maskz_scalar_name" "maskz_scalar" "" "_maskz_1")
146 : : (define_subst_attr "maskz_scalar_op5" "maskz_scalar" "" "%{%6%}%N5")
147 : :
148 : : (define_subst "maskz_scalar"
149 : : [(set (match_operand:SUBST_V 0)
150 : : (vec_merge:SUBST_V
151 : : (match_operand:SUBST_V 1)
152 : : (match_operand:SUBST_V 2)
153 : : (const_int 1)))]
154 : 14 : "TARGET_AVX512F"
155 : : [(set (match_dup 0)
156 : : (vec_merge:SUBST_V
157 : : (vec_merge:SUBST_V
158 : 16 : (match_dup 1)
159 : 16 : (match_operand:SUBST_V 3 "const0_operand")
160 : 16 : (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
161 : : (match_dup 2)
162 : : (const_int 1)))])
163 : : (define_subst_attr "sdc_maskz_name" "sdc" "" "_maskz_1")
164 : : (define_subst_attr "sdc_mask_op4" "sdc" "" "%{%5%}%N4")
165 : : (define_subst_attr "sdc_mask_op5" "sdc" "" "%{%6%}%N5")
166 : : (define_subst_attr "sdc_mask_mode512bit_condition" "sdc" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
167 : :
168 : : (define_subst "sdc"
169 : : [(set (match_operand:SUBST_CV 0)
170 : : (match_operand:SUBST_CV 1))]
171 : : ""
172 : : [(set (match_dup 0)
173 : : (vec_merge:SUBST_CV
174 : : (match_dup 1)
175 : : (match_operand:SUBST_CV 2 "const0_operand")
176 : : (unspec:<avx512fmaskmode>
177 : : [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
178 : : UNSPEC_COMPLEX_MASK)))
179 : : ])
180 : :
181 : : (define_subst_attr "round_name" "round" "" "_round")
182 : : (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
183 : : (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
184 : : (define_subst_attr "round_maskc_operand3" "maskc" "%R3" "%R5")
185 : : (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
186 : : (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
187 : : (define_subst_attr "round_sdc_mask_operand4" "sdc" "%R4" "%R6")
188 : : (define_subst_attr "round_op2" "round" "" "%R2")
189 : : (define_subst_attr "round_op3" "round" "" "%R3")
190 : : (define_subst_attr "round_op4" "round" "" "%R4")
191 : : (define_subst_attr "round_op5" "round" "" "%R5")
192 : : (define_subst_attr "round_op6" "round" "" "%R6")
193 : : (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
194 : : (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
195 : : (define_subst_attr "round_maskc_op3" "round" "" "<round_maskc_operand3>")
196 : : (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
197 : : (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
198 : : (define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>")
199 : : (define_subst_attr "round_constraint" "round" "vm" "v")
200 : : (define_subst_attr "round_suff" "round" "{y}" "")
201 : : (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
202 : : (define_subst_attr "round_qq2pssuff" "round" "<qq2pssuff>" "")
203 : : (define_subst_attr "round_pd2udqsuff" "round" "<pd2udqsuff>" "")
204 : : (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
205 : : (define_subst_attr "round_constraint2" "round" "m" "v")
206 : : (define_subst_attr "round_constraint3" "round" "rm" "r")
207 : : (define_subst_attr "round_constraint4" "round" "vBm" "v")
208 : : (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
209 : : (define_subst_attr "bcst_round_nimm_predicate" "round" "bcst_vector_operand" "register_operand")
210 : : (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
211 : : (define_subst_attr "round_prefix" "round" "vex" "evex")
212 : : (define_subst_attr "round_mode_condition" "round" "1" "((<MODE>mode == V16SFmode
213 : : || <MODE>mode == V8DFmode
214 : : || <MODE>mode == V8DImode
215 : : || <MODE>mode == V16SImode
216 : : || <MODE>mode == V32HImode
217 : : || <MODE>mode == V32HFmode)
218 : : || (TARGET_AVX10_2_256
219 : : && (<MODE>mode == V8SFmode
220 : : || <MODE>mode == V4DFmode
221 : : || <MODE>mode == V4DImode
222 : : || <MODE>mode == V8SImode
223 : : || <MODE>mode == V16HImode
224 : : || <MODE>mode == V16HFmode)))")
225 : : (define_subst_attr "round_applied" "round" "false" "true")
226 : :
227 : : (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
228 : : (define_subst_attr "round_codefor" "round" "*" "")
229 : : (define_subst_attr "round_opnum" "round" "5" "6")
230 : :
231 : : (define_subst "round"
232 : : [(set (match_operand:SUBST_A 0)
233 : : (match_operand:SUBST_A 1))]
234 : 66578 : "TARGET_AVX512F"
235 : : [(set (match_dup 0)
236 : 136 : (unspec:SUBST_A [(match_dup 1)
237 : 136 : (match_operand:SI 2 "const_4_or_8_to_11_operand")]
238 : 873 : UNSPEC_EMBEDDED_ROUNDING))
239 : 3183 : ])
240 : 767 :
241 : 1617 : (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
242 : 2343 : (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
243 : : (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
244 : 2091 : (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
245 : 2091 : (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
246 : 726 : (define_subst_attr "round_saeonly_maskz_scalar_operand5" "maskz_scalar" "%r5" "%r7")
247 : 679 : (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
248 : 679 : (define_subst_attr "round_saeonly_sdc_mask_operand5" "sdc" "%r5" "%r7")
249 : 679 : (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
250 : : (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
251 : : (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
252 : : (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
253 : : (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
254 : : (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
255 : : (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
256 : : (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
257 : : (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
258 : : (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
259 : : (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
260 : : (define_subst_attr "round_saeonly_maskz_scalar_op5" "round_saeonly" "" "<round_saeonly_maskz_scalar_operand5>")
261 : : (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
262 : : (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
263 : : (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
264 : : (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
265 : : (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
266 : : (define_subst_attr "round_saeonly_suff" "round_saeonly" "{y}" "")
267 : : (define_subst_attr "round_saeonly_mode_condition" "round_saeonly" "1" "((<MODE>mode == V16SFmode
268 : : || <MODE>mode == V8DFmode
269 : : || <MODE>mode == V8DImode
270 : : || <MODE>mode == V16SImode
271 : : || <MODE>mode == V32HImode
272 : : || <MODE>mode == V32HFmode)
273 : : || (TARGET_AVX10_2_256
274 : : && (<MODE>mode == V8SFmode
275 : : || <MODE>mode == V4DFmode
276 : : || <MODE>mode == V4DImode
277 : : || <MODE>mode == V8SImode
278 : : || <MODE>mode == V16HImode
279 : : || <MODE>mode == V16HFmode)))")
280 : : (define_subst_attr "round_saeonly_applied" "round_saeonly" "false" "true")
281 : :
282 : :
283 : : (define_subst "round_saeonly"
284 : : [(set (match_operand:SUBST_A 0)
285 : : (match_operand:SUBST_A 1))]
286 : 42230 : "TARGET_AVX512F"
287 : : [(set (match_dup 0)
288 : : (unspec:SUBST_A [(match_dup 1)
289 : : (match_operand:SI 2 "const48_operand")]
290 : 951 : UNSPEC_EMBEDDED_ROUNDING))
291 : 951 : ])
292 : 491 :
293 : : (define_subst "round_saeonly"
294 : : [(set (match_operand:CCFP 0)
295 : : (match_operand:CCFP 1))]
296 : 20 : "TARGET_AVX512F"
297 : : [(set (match_dup 0)
298 : : (unspec:CCFP [(match_dup 1)
299 : : (match_operand:SI 2 "const48_operand")]
300 : : UNSPEC_EMBEDDED_ROUNDING))
301 : : ])
302 : :
303 : : (define_subst_attr "round_expand_name" "round_expand" "" "_round")
304 : : (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
305 : : (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
306 : : (define_subst_attr "round_embedded_complex" "round_expand" "0" "!(CONST_INT_P (operands[5])
307 : : && (INTVAL (operands[5])
308 : : == NO_ROUND))")
309 : :
310 : : (define_subst "round_expand"
311 : : [(match_operand:SUBST_V 0)
312 : : (match_operand:SUBST_V 1)
313 : : (match_operand:SUBST_V 2)
314 : : (match_operand:SUBST_V 3)
315 : : (match_operand:SUBST_S 4)]
316 : : "TARGET_AVX512F"
317 : : [(match_dup 0)
318 : : (match_dup 1)
319 : : (match_dup 2)
320 : : (match_dup 3)
321 : : (match_dup 4)
322 : : (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
323 : :
324 : : (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
325 : : (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
326 : : (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
327 : :
328 : : (define_subst "round_saeonly_expand"
329 : : [(match_operand:SUBST_V 0)
330 : : (match_operand:SUBST_V 1)
331 : : (match_operand:SUBST_V 2)
332 : : (match_operand:SUBST_A 3)
333 : : (match_operand:SI 4)
334 : : (match_operand:SUBST_S 5)]
335 : : "TARGET_AVX512F"
336 : : [(match_dup 0)
337 : : (match_dup 1)
338 : : (match_dup 2)
339 : : (match_dup 3)
340 : : (match_dup 4)
341 : : (match_dup 5)
342 : : (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
343 : :
344 : : (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
345 : : (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
346 : :
347 : : (define_subst "mask_expand4"
348 : : [(match_operand:SUBST_V 0)
349 : : (match_operand:SUBST_V 1)
350 : : (match_operand:SUBST_V 2)
351 : : (match_operand:SI 3)]
352 : : "TARGET_AVX512VL"
353 : : [(match_dup 0)
354 : : (match_dup 1)
355 : : (match_dup 2)
356 : : (match_dup 3)
357 : : (match_operand:SUBST_V 4 "nonimm_or_0_operand")
358 : : (match_operand:<avx512fmaskmode> 5 "register_operand")])
359 : :
360 : : (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
361 : : (define_subst_attr "mask_scalarcz_name" "mask_scalarcz" "" "_maskz")
362 : : (define_subst_attr "mask_scalarc_name" "mask_scalarc" "" "_mask")
363 : : (define_subst_attr "mask_scalarc_operand3" "mask_scalarc" "" "%{%4%}%N3")
364 : : (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3")
365 : : (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4")
366 : : (define_subst_attr "mask_scalarcz_operand4" "mask_scalarcz" "" "%{%5%}%N4")
367 : : (define_subst_attr "mask_scalar4_dest_false_dep_for_glc_cond" "mask_scalar" "1" "operands[4] == CONST0_RTX(<MODE>mode)")
368 : : (define_subst_attr "mask_scalarc_dest_false_dep_for_glc_cond" "mask_scalarc" "1" "operands[3] == CONST0_RTX(V8HFmode)")
369 : : (define_subst_attr "mask_scalar_operand_arg34" "mask_scalar" "" ", operands[3], operands[4]")
370 : : (define_subst_attr "mask_scalar_expand_op3" "mask_scalar" "3" "5")
371 : :
372 : : (define_subst "mask_scalar"
373 : : [(set (match_operand:SUBST_V 0)
374 : : (vec_merge:SUBST_V
375 : : (match_operand:SUBST_V 1)
376 : : (match_operand:SUBST_V 2)
377 : : (const_int 1)))]
378 : 9890 : "TARGET_AVX512F"
379 : : [(set (match_dup 0)
380 : : (vec_merge:SUBST_V
381 : : (vec_merge:SUBST_V
382 : 1141 : (match_dup 1)
383 : 1141 : (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C")
384 : 387 : (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
385 : : (match_dup 2)
386 : : (const_int 1)))])
387 : :
388 : : (define_subst "mask_scalarcz"
389 : : [(set (match_operand:SUBST_CV 0)
390 : : (vec_merge:SUBST_CV
391 : : (match_operand:SUBST_CV 1)
392 : : (match_operand:SUBST_CV 2)
393 : : (const_int 3)))]
394 : 438 : "TARGET_AVX512F"
395 : : [(set (match_dup 0)
396 : : (vec_merge:SUBST_CV
397 : : (vec_merge:SUBST_CV
398 : : (match_dup 1)
399 : : (match_operand:SUBST_CV 3 "const0_operand")
400 : : (unspec:<avx512fmaskmode>
401 : : [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
402 : : UNSPEC_COMPLEX_MASK))
403 : : (match_dup 2)
404 : : (const_int 3)))])
405 : :
406 : : (define_subst "mask_scalarc"
407 : : [(set (match_operand:SUBST_CV 0)
408 : : (vec_merge:SUBST_CV
409 : : (match_operand:SUBST_CV 1)
410 : : (match_operand:SUBST_CV 2)
411 : : (const_int 3)))]
412 : 992 : "TARGET_AVX512F"
413 : : [(set (match_dup 0)
414 : : (vec_merge:SUBST_CV
415 : : (vec_merge:SUBST_CV
416 : : (match_dup 1)
417 : : (match_operand:SUBST_CV 3 "nonimm_or_0_operand" "0C")
418 : : (unspec:<avx512fmaskmode>
419 : : [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
420 : : UNSPEC_COMPLEX_MASK))
421 : : (match_dup 2)
422 : : (const_int 3)))])
423 : :
424 : : (define_subst_attr "round_scalar_name" "round_scalar" "" "_round")
425 : : (define_subst_attr "round_scalarcz_name" "round_scalarcz" "" "_round")
426 : : (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5")
427 : : (define_subst_attr "round_scalarc_mask_operand3" "mask_scalarc" "%R3" "%R5")
428 : : (define_subst_attr "round_scalarcz_mask_operand4" "mask_scalarcz" "%R4" "%R6")
429 : : (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>")
430 : : (define_subst_attr "round_scalarc_mask_op3" "round_scalarcz" "" "<round_scalarc_mask_operand3>")
431 : : (define_subst_attr "round_scalarcz_mask_op4" "round_scalarcz" "" "<round_scalarcz_mask_operand4>")
432 : : (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v")
433 : : (define_subst_attr "round_scalarcz_constraint" "round_scalarcz" "vm" "v")
434 : : (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex")
435 : : (define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand")
436 : : (define_subst_attr "round_scalarcz_nimm_predicate" "round_scalarcz" "vector_operand" "register_operand")
437 : :
438 : : (define_subst "round_scalar"
439 : : [(set (match_operand:SUBST_V 0)
440 : : (vec_merge:SUBST_V
441 : : (match_operand:SUBST_V 1)
442 : : (match_operand:SUBST_V 2)
443 : : (const_int 1)))]
444 : 3803 : "TARGET_AVX512F"
445 : : [(set (match_dup 0)
446 : : (unspec:SUBST_V [
447 : : (vec_merge:SUBST_V
448 : 354 : (match_dup 1)
449 : 354 : (match_dup 2)
450 : : (const_int 1))
451 : : (match_operand:SI 3 "const_4_or_8_to_11_operand")]
452 : : UNSPEC_EMBEDDED_ROUNDING))])
453 : :
454 : : (define_subst "round_scalarcz"
455 : : [(set (match_operand:SUBST_V 0)
456 : : (vec_merge:SUBST_V
457 : : (match_operand:SUBST_V 1)
458 : : (match_operand:SUBST_V 2)
459 : : (const_int 3)))]
460 : 1916 : "TARGET_AVX512F"
461 : : [(set (match_dup 0)
462 : : (unspec:SUBST_V [
463 : : (vec_merge:SUBST_V
464 : : (match_dup 1)
465 : : (match_dup 2)
466 : : (const_int 3))
467 : : (match_operand:SI 3 "const_4_or_8_to_11_operand")]
468 : : UNSPEC_EMBEDDED_ROUNDING))])
469 : :
470 : : (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round")
471 : : (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5")
472 : : (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6")
473 : : (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>")
474 : : (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>")
475 : : (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v")
476 : : (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex")
477 : : (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand")
478 : : (define_subst_attr "round_saeonly_scalar_mask_arg3" "round_saeonly_scalar" "" ", operands[<mask_scalar_expand_op3>]")
479 : :
480 : : (define_subst "round_saeonly_scalar"
481 : : [(set (match_operand:SUBST_V 0)
482 : : (vec_merge:SUBST_V
483 : : (match_operand:SUBST_V 1)
484 : : (match_operand:SUBST_V 2)
485 : : (const_int 1)))]
486 : 3791 : "TARGET_AVX512F"
487 : : [(set (match_dup 0)
488 : : (unspec:SUBST_V [
489 : : (vec_merge:SUBST_V
490 : 2197 : (match_dup 1)
491 : 2197 : (match_dup 2)
492 : 113 : (const_int 1))
493 : : (match_operand:SI 3 "const48_operand")]
494 : : UNSPEC_EMBEDDED_ROUNDING))])
495 : :
496 : : (define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1")
497 : : (define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4")
498 : :
499 : : (define_subst "maskz_half"
500 : : [(set (match_operand:SUBST_V 0)
501 : : (match_operand:SUBST_V 1))]
502 : : ""
503 : : [(set (match_dup 0)
504 : : (vec_merge:SUBST_V
505 : : (match_dup 1)
506 : : (match_operand:SUBST_V 2 "const0_operand")
507 : : (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))])
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