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1 : : ;; GCC machine description for AVX512F instructions
2 : : ;; Copyright (C) 2013-2024 Free Software Foundation, Inc.
3 : : ;;
4 : : ;; This file is part of GCC.
5 : : ;;
6 : : ;; GCC is free software; you can redistribute it and/or modify
7 : : ;; it under the terms of the GNU General Public License as published by
8 : : ;; the Free Software Foundation; either version 3, or (at your option)
9 : : ;; any later version.
10 : : ;;
11 : : ;; GCC is distributed in the hope that it will be useful,
12 : : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : : ;; GNU General Public License for more details.
15 : : ;;
16 : : ;; You should have received a copy of the GNU General Public License
17 : : ;; along with GCC; see the file COPYING3. If not see
18 : : ;; <http://www.gnu.org/licenses/>.
19 : :
20 : : ;; Some iterators for extending subst as much as possible
21 : : ;; All vectors (Use it for destination)
22 : : (define_mode_iterator SUBST_V
23 : : [V64QI V32QI V16QI
24 : : V32HI V16HI V8HI
25 : : V16SI V8SI V4SI
26 : : V8DI V4DI V2DI
27 : : V32HF V16HF V8HF
28 : : V32BF V16BF V8BF
29 : : V16SF V8SF V4SF
30 : : V8DF V4DF V2DF])
31 : :
32 : : (define_mode_iterator SUBST_CV
33 : : [V32HF V16HF V8HF])
34 : :
35 : : (define_mode_iterator SUBST_S
36 : : [QI HI SI DI])
37 : :
38 : : (define_mode_iterator SUBST_A
39 : : [V64QI V32QI V16QI
40 : : V32HI V16HI V8HI
41 : : V16SI V8SI V4SI
42 : : V8DI V4DI V2DI
43 : : V32HF V16HF V8HF
44 : : V16SF V8SF V4SF
45 : : V8DF V4DF V2DF
46 : : QI HI SI DI SF DF])
47 : :
48 : : (define_subst_attr "mask_name" "mask" "" "_mask")
49 : : (define_subst_attr "maskc_name" "maskc" "" "_mask")
50 : : (define_subst_attr "mask_applied" "mask" "false" "true")
51 : : (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
52 : : (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
53 : : (define_subst_attr "maskc_operand3" "maskc" "" "%{%4%}%N3")
54 : : (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
55 : : (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
56 : : (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
57 : : (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
58 : : (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
59 : : (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
60 : : (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
61 : : (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
62 : : (define_subst_attr "mask_codefor" "mask" "*" "")
63 : : (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
64 : : (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
65 : : (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
66 : : (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
67 : : (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
68 : : (define_subst_attr "mask_prefix" "mask" "vex" "evex")
69 : : (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
70 : : (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex")
71 : : (define_subst_attr "bcst_mask_prefix3" "mask" "orig,maybe_evex" "evex,evex")
72 : : (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex")
73 : : (define_subst_attr "bcst_mask_prefix4" "mask" "orig,orig,maybe_evex" "evex,evex,evex")
74 : : (define_subst_attr "mask_expand_op3" "mask" "3" "5")
75 : : (define_subst_attr "mask3_dest_false_dep_for_glc_cond" "mask" "1" "operands[3] == CONST0_RTX(<MODE>mode)")
76 : : (define_subst_attr "mask4_dest_false_dep_for_glc_cond" "mask" "1" "operands[4] == CONST0_RTX(<MODE>mode)")
77 : : (define_subst_attr "mask6_dest_false_dep_for_glc_cond" "mask" "1" "operands[6] == CONST0_RTX(<MODE>mode)")
78 : : (define_subst_attr "mask10_dest_false_dep_for_glc_cond" "mask" "1" "operands[10] == CONST0_RTX(<MODE>mode)")
79 : : (define_subst_attr "maskc_dest_false_dep_for_glc_cond" "maskc" "1" "operands[3] == CONST0_RTX(<MODE>mode)")
80 : :
81 : : (define_subst "mask"
82 : : [(set (match_operand:SUBST_V 0)
83 : : (match_operand:SUBST_V 1))]
84 : 106301 : "TARGET_AVX512F"
85 : : [(set (match_dup 0)
86 : : (vec_merge:SUBST_V
87 : : (match_dup 1)
88 : : (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
89 : : (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
90 : :
91 : : (define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask")
92 : : (define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}")
93 : : (define_subst "merge_mask"
94 : : [(set (match_operand:SUBST_V 0)
95 : : (match_operand:SUBST_V 1))]
96 : 0 : "TARGET_AVX512F"
97 : : [(set (match_dup 0)
98 : : (vec_merge:SUBST_V
99 : : (match_dup 1)
100 : : (match_dup 0)
101 : : (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))])
102 : :
103 : : (define_subst "maskc"
104 : : [(set (match_operand:SUBST_CV 0)
105 : : (match_operand:SUBST_CV 1))]
106 : 1356 : "TARGET_AVX512F"
107 : : [(set (match_dup 0)
108 : : (vec_merge:SUBST_CV
109 : : (match_dup 1)
110 : : (match_operand:SUBST_CV 2 "nonimm_or_0_operand" "0C")
111 : : (unspec:<avx512fmaskmode>
112 : : [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
113 : : UNSPEC_COMPLEX_MASK)))])
114 : :
115 : : (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
116 : : (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
117 : : (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
118 : :
119 : : (define_subst "mask_scalar_merge"
120 : : [(set (match_operand:SUBST_S 0)
121 : : (match_operand:SUBST_S 1))]
122 : 9679 : "TARGET_AVX512F"
123 : : [(set (match_dup 0)
124 : : (and:SUBST_S
125 : : (match_dup 1)
126 : : (match_operand:SUBST_S 3 "register_operand" "Yk")))])
127 : :
128 : : (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
129 : : (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
130 : : (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
131 : : (define_subst_attr "sd_mask_codefor" "sd" "*" "")
132 : : (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
133 : :
134 : : (define_subst "sd"
135 : : [(set (match_operand:SUBST_V 0)
136 : : (match_operand:SUBST_V 1))]
137 : : ""
138 : : [(set (match_dup 0)
139 : : (vec_merge:SUBST_V
140 : : (match_dup 1)
141 : : (match_operand:SUBST_V 2 "const0_operand")
142 : : (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
143 : : ])
144 : :
145 : : (define_subst_attr "maskz_scalar_name" "maskz_scalar" "" "_maskz_1")
146 : : (define_subst_attr "maskz_scalar_op5" "maskz_scalar" "" "%{%6%}%N5")
147 : :
148 : : (define_subst "maskz_scalar"
149 : : [(set (match_operand:SUBST_V 0)
150 : : (vec_merge:SUBST_V
151 : : (match_operand:SUBST_V 1)
152 : : (match_operand:SUBST_V 2)
153 : : (const_int 1)))]
154 : 10 : "TARGET_AVX512F"
155 : : [(set (match_dup 0)
156 : : (vec_merge:SUBST_V
157 : : (vec_merge:SUBST_V
158 : 11 : (match_dup 1)
159 : 11 : (match_operand:SUBST_V 3 "const0_operand")
160 : 11 : (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
161 : : (match_dup 2)
162 : : (const_int 1)))])
163 : : (define_subst_attr "sdc_maskz_name" "sdc" "" "_maskz_1")
164 : : (define_subst_attr "sdc_mask_op4" "sdc" "" "%{%5%}%N4")
165 : : (define_subst_attr "sdc_mask_op5" "sdc" "" "%{%6%}%N5")
166 : : (define_subst_attr "sdc_mask_mode512bit_condition" "sdc" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
167 : :
168 : : (define_subst "sdc"
169 : : [(set (match_operand:SUBST_CV 0)
170 : : (match_operand:SUBST_CV 1))]
171 : : ""
172 : : [(set (match_dup 0)
173 : : (vec_merge:SUBST_CV
174 : : (match_dup 1)
175 : : (match_operand:SUBST_CV 2 "const0_operand")
176 : : (unspec:<avx512fmaskmode>
177 : : [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
178 : : UNSPEC_COMPLEX_MASK)))
179 : : ])
180 : :
181 : : (define_subst_attr "round_name" "round" "" "_round")
182 : : (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
183 : : (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
184 : : (define_subst_attr "round_maskc_operand3" "maskc" "%R3" "%R5")
185 : : (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
186 : : (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
187 : : (define_subst_attr "round_sdc_mask_operand4" "sdc" "%R4" "%R6")
188 : : (define_subst_attr "round_op2" "round" "" "%R2")
189 : : (define_subst_attr "round_op3" "round" "" "%R3")
190 : : (define_subst_attr "round_op4" "round" "" "%R4")
191 : : (define_subst_attr "round_op5" "round" "" "%R5")
192 : : (define_subst_attr "round_op6" "round" "" "%R6")
193 : : (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
194 : : (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
195 : : (define_subst_attr "round_maskc_op3" "round" "" "<round_maskc_operand3>")
196 : : (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
197 : : (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
198 : : (define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>")
199 : : (define_subst_attr "round_constraint" "round" "vm" "v")
200 : : (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "")
201 : : (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v")
202 : : (define_subst_attr "round_constraint2" "round" "m" "v")
203 : : (define_subst_attr "round_constraint3" "round" "rm" "r")
204 : : (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
205 : : (define_subst_attr "bcst_round_nimm_predicate" "round" "bcst_vector_operand" "register_operand")
206 : : (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
207 : : (define_subst_attr "round_prefix" "round" "vex" "evex")
208 : : (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
209 : : || <MODE>mode == V8DFmode
210 : : || <MODE>mode == V8DImode
211 : : || <MODE>mode == V16SImode
212 : : || <MODE>mode == V32HFmode)")
213 : :
214 : : (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
215 : : (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
216 : : (define_subst_attr "round_codefor" "round" "*" "")
217 : : (define_subst_attr "round_opnum" "round" "5" "6")
218 : :
219 : : (define_subst "round"
220 : : [(set (match_operand:SUBST_A 0)
221 : : (match_operand:SUBST_A 1))]
222 : 30301 : "TARGET_AVX512F"
223 : : [(set (match_dup 0)
224 : : (unspec:SUBST_A [(match_dup 1)
225 : 622 : (match_operand:SI 2 "const_4_or_8_to_11_operand")]
226 : 1834 : UNSPEC_EMBEDDED_ROUNDING))
227 : 1834 : ])
228 : 1166 :
229 : 622 : (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
230 : 1158 : (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
231 : 204 : (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
232 : 536 : (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
233 : 536 : (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
234 : 602 : (define_subst_attr "round_saeonly_maskz_scalar_operand5" "maskz_scalar" "%r5" "%r7")
235 : : (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
236 : : (define_subst_attr "round_saeonly_sdc_mask_operand5" "sdc" "%r5" "%r7")
237 : : (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
238 : : (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
239 : : (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
240 : : (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
241 : : (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
242 : : (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
243 : : (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
244 : : (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
245 : : (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
246 : : (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
247 : : (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
248 : : (define_subst_attr "round_saeonly_maskz_scalar_op5" "round_saeonly" "" "<round_saeonly_maskz_scalar_operand5>")
249 : : (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
250 : : (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
251 : : (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
252 : : (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
253 : : (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
254 : : (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
255 : : || <MODE>mode == V8DFmode
256 : : || <MODE>mode == V8DImode
257 : : || <MODE>mode == V16SImode
258 : : || <MODE>mode == V32HFmode)")
259 : :
260 : : (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
261 : :
262 : : (define_subst "round_saeonly"
263 : : [(set (match_operand:SUBST_A 0)
264 : : (match_operand:SUBST_A 1))]
265 : 18107 : "TARGET_AVX512F"
266 : : [(set (match_dup 0)
267 : : (unspec:SUBST_A [(match_dup 1)
268 : : (match_operand:SI 2 "const48_operand")]
269 : 623 : UNSPEC_EMBEDDED_ROUNDING))
270 : 623 : ])
271 : 345 :
272 : : (define_subst "round_saeonly"
273 : : [(set (match_operand:CCFP 0)
274 : : (match_operand:CCFP 1))]
275 : : "TARGET_AVX512F"
276 : : [(set (match_dup 0)
277 : : (unspec:CCFP [(match_dup 1)
278 : : (match_operand:SI 2 "const48_operand")]
279 : : UNSPEC_EMBEDDED_ROUNDING))
280 : : ])
281 : :
282 : : (define_subst_attr "round_expand_name" "round_expand" "" "_round")
283 : : (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
284 : : (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
285 : : (define_subst_attr "round_embedded_complex" "round_expand" "0" "!(CONST_INT_P (operands[5])
286 : : && (INTVAL (operands[5])
287 : : == NO_ROUND))")
288 : :
289 : : (define_subst "round_expand"
290 : : [(match_operand:SUBST_V 0)
291 : : (match_operand:SUBST_V 1)
292 : : (match_operand:SUBST_V 2)
293 : : (match_operand:SUBST_V 3)
294 : : (match_operand:SUBST_S 4)]
295 : : "TARGET_AVX512F"
296 : : [(match_dup 0)
297 : : (match_dup 1)
298 : : (match_dup 2)
299 : : (match_dup 3)
300 : : (match_dup 4)
301 : : (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
302 : :
303 : : (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
304 : : (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
305 : : (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
306 : :
307 : : (define_subst "round_saeonly_expand"
308 : : [(match_operand:SUBST_V 0)
309 : : (match_operand:SUBST_V 1)
310 : : (match_operand:SUBST_V 2)
311 : : (match_operand:SUBST_A 3)
312 : : (match_operand:SI 4)
313 : : (match_operand:SUBST_S 5)]
314 : : "TARGET_AVX512F"
315 : : [(match_dup 0)
316 : : (match_dup 1)
317 : : (match_dup 2)
318 : : (match_dup 3)
319 : : (match_dup 4)
320 : : (match_dup 5)
321 : : (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
322 : :
323 : : (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
324 : : (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
325 : :
326 : : (define_subst "mask_expand4"
327 : : [(match_operand:SUBST_V 0)
328 : : (match_operand:SUBST_V 1)
329 : : (match_operand:SUBST_V 2)
330 : : (match_operand:SI 3)]
331 : : "TARGET_AVX512VL"
332 : : [(match_dup 0)
333 : : (match_dup 1)
334 : : (match_dup 2)
335 : : (match_dup 3)
336 : : (match_operand:SUBST_V 4 "nonimm_or_0_operand")
337 : : (match_operand:<avx512fmaskmode> 5 "register_operand")])
338 : :
339 : : (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
340 : : (define_subst_attr "mask_scalarcz_name" "mask_scalarcz" "" "_maskz")
341 : : (define_subst_attr "mask_scalarc_name" "mask_scalarc" "" "_mask")
342 : : (define_subst_attr "mask_scalarc_operand3" "mask_scalarc" "" "%{%4%}%N3")
343 : : (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3")
344 : : (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4")
345 : : (define_subst_attr "mask_scalarcz_operand4" "mask_scalarcz" "" "%{%5%}%N4")
346 : : (define_subst_attr "mask_scalar4_dest_false_dep_for_glc_cond" "mask_scalar" "1" "operands[4] == CONST0_RTX(<MODE>mode)")
347 : : (define_subst_attr "mask_scalarc_dest_false_dep_for_glc_cond" "mask_scalarc" "1" "operands[3] == CONST0_RTX(V8HFmode)")
348 : :
349 : : (define_subst "mask_scalar"
350 : : [(set (match_operand:SUBST_V 0)
351 : : (vec_merge:SUBST_V
352 : : (match_operand:SUBST_V 1)
353 : : (match_operand:SUBST_V 2)
354 : : (const_int 1)))]
355 : 6156 : "TARGET_AVX512F"
356 : : [(set (match_dup 0)
357 : : (vec_merge:SUBST_V
358 : : (vec_merge:SUBST_V
359 : 788 : (match_dup 1)
360 : 788 : (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C")
361 : 290 : (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
362 : : (match_dup 2)
363 : : (const_int 1)))])
364 : :
365 : : (define_subst "mask_scalarcz"
366 : : [(set (match_operand:SUBST_CV 0)
367 : : (vec_merge:SUBST_CV
368 : : (match_operand:SUBST_CV 1)
369 : : (match_operand:SUBST_CV 2)
370 : : (const_int 3)))]
371 : 308 : "TARGET_AVX512F"
372 : : [(set (match_dup 0)
373 : : (vec_merge:SUBST_CV
374 : : (vec_merge:SUBST_CV
375 : : (match_dup 1)
376 : : (match_operand:SUBST_CV 3 "const0_operand")
377 : : (unspec:<avx512fmaskmode>
378 : : [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
379 : : UNSPEC_COMPLEX_MASK))
380 : : (match_dup 2)
381 : : (const_int 3)))])
382 : :
383 : : (define_subst "mask_scalarc"
384 : : [(set (match_operand:SUBST_CV 0)
385 : : (vec_merge:SUBST_CV
386 : : (match_operand:SUBST_CV 1)
387 : : (match_operand:SUBST_CV 2)
388 : : (const_int 3)))]
389 : 618 : "TARGET_AVX512F"
390 : : [(set (match_dup 0)
391 : : (vec_merge:SUBST_CV
392 : : (vec_merge:SUBST_CV
393 : : (match_dup 1)
394 : : (match_operand:SUBST_CV 3 "nonimm_or_0_operand" "0C")
395 : : (unspec:<avx512fmaskmode>
396 : : [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
397 : : UNSPEC_COMPLEX_MASK))
398 : : (match_dup 2)
399 : : (const_int 3)))])
400 : :
401 : : (define_subst_attr "round_scalar_name" "round_scalar" "" "_round")
402 : : (define_subst_attr "round_scalarcz_name" "round_scalarcz" "" "_round")
403 : : (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5")
404 : : (define_subst_attr "round_scalarc_mask_operand3" "mask_scalarc" "%R3" "%R5")
405 : : (define_subst_attr "round_scalarcz_mask_operand4" "mask_scalarcz" "%R4" "%R6")
406 : : (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>")
407 : : (define_subst_attr "round_scalarc_mask_op3" "round_scalarcz" "" "<round_scalarc_mask_operand3>")
408 : : (define_subst_attr "round_scalarcz_mask_op4" "round_scalarcz" "" "<round_scalarcz_mask_operand4>")
409 : : (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v")
410 : : (define_subst_attr "round_scalarcz_constraint" "round_scalarcz" "vm" "v")
411 : : (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex")
412 : : (define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand")
413 : : (define_subst_attr "round_scalarcz_nimm_predicate" "round_scalarcz" "vector_operand" "register_operand")
414 : :
415 : : (define_subst "round_scalar"
416 : : [(set (match_operand:SUBST_V 0)
417 : : (vec_merge:SUBST_V
418 : : (match_operand:SUBST_V 1)
419 : : (match_operand:SUBST_V 2)
420 : : (const_int 1)))]
421 : 2581 : "TARGET_AVX512F"
422 : : [(set (match_dup 0)
423 : : (unspec:SUBST_V [
424 : : (vec_merge:SUBST_V
425 : 242 : (match_dup 1)
426 : 242 : (match_dup 2)
427 : : (const_int 1))
428 : : (match_operand:SI 3 "const_4_or_8_to_11_operand")]
429 : : UNSPEC_EMBEDDED_ROUNDING))])
430 : :
431 : : (define_subst "round_scalarcz"
432 : : [(set (match_operand:SUBST_V 0)
433 : : (vec_merge:SUBST_V
434 : : (match_operand:SUBST_V 1)
435 : : (match_operand:SUBST_V 2)
436 : : (const_int 3)))]
437 : 1247 : "TARGET_AVX512F"
438 : : [(set (match_dup 0)
439 : : (unspec:SUBST_V [
440 : : (vec_merge:SUBST_V
441 : : (match_dup 1)
442 : : (match_dup 2)
443 : : (const_int 3))
444 : : (match_operand:SI 3 "const_4_or_8_to_11_operand")]
445 : : UNSPEC_EMBEDDED_ROUNDING))])
446 : :
447 : : (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round")
448 : : (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5")
449 : : (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6")
450 : : (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>")
451 : : (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>")
452 : : (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v")
453 : : (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex")
454 : : (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand")
455 : :
456 : : (define_subst "round_saeonly_scalar"
457 : : [(set (match_operand:SUBST_V 0)
458 : : (vec_merge:SUBST_V
459 : : (match_operand:SUBST_V 1)
460 : : (match_operand:SUBST_V 2)
461 : : (const_int 1)))]
462 : 2499 : "TARGET_AVX512F"
463 : : [(set (match_dup 0)
464 : : (unspec:SUBST_V [
465 : : (vec_merge:SUBST_V
466 : 1361 : (match_dup 1)
467 : 1361 : (match_dup 2)
468 : 86 : (const_int 1))
469 : : (match_operand:SI 3 "const48_operand")]
470 : : UNSPEC_EMBEDDED_ROUNDING))])
471 : :
472 : : (define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1")
473 : : (define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4")
474 : :
475 : : (define_subst "maskz_half"
476 : : [(set (match_operand:SUBST_V 0)
477 : : (match_operand:SUBST_V 1))]
478 : : ""
479 : : [(set (match_dup 0)
480 : : (vec_merge:SUBST_V
481 : : (match_dup 1)
482 : : (match_operand:SUBST_V 2 "const0_operand")
483 : : (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))])
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