Line data Source code
1 : /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "tree.h"
28 : #include "predict.h"
29 : #include "memmodel.h"
30 : #include "tm_p.h"
31 : #include "insn-config.h"
32 : #include "regs.h"
33 : #include "regset.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "addresses.h"
37 : #include "reload.h"
38 : #include "print-rtl.h"
39 :
40 : /* The flags is set up every time when we calculate pseudo register
41 : classes through function ira_set_pseudo_classes. */
42 : static bool pseudo_classes_defined_p = false;
43 :
44 : /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
45 : static bool allocno_p;
46 :
47 : /* Number of elements in array `costs'. */
48 : static int cost_elements_num;
49 :
50 : /* The `costs' struct records the cost of using hard registers of each
51 : class considered for the calculation and of using memory for each
52 : allocno or pseudo. */
53 : struct costs
54 : {
55 : int mem_cost;
56 : /* Costs for register classes start here. We process only some
57 : allocno classes. */
58 : int cost[1];
59 : };
60 :
61 : #define max_struct_costs_size \
62 : (this_target_ira_int->x_max_struct_costs_size)
63 : #define init_cost \
64 : (this_target_ira_int->x_init_cost)
65 : #define temp_costs \
66 : (this_target_ira_int->x_temp_costs)
67 : #define op_costs \
68 : (this_target_ira_int->x_op_costs)
69 : #define this_op_costs \
70 : (this_target_ira_int->x_this_op_costs)
71 :
72 : /* Costs of each class for each allocno or pseudo. */
73 : static struct costs *costs;
74 :
75 : /* Accumulated costs of each class for each allocno. */
76 : static struct costs *total_allocno_costs;
77 :
78 : /* It is the current size of struct costs. */
79 : static size_t struct_costs_size;
80 :
81 : /* Return pointer to structure containing costs of allocno or pseudo
82 : with given NUM in array ARR. */
83 : #define COSTS(arr, num) \
84 : ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
85 :
86 : /* Return index in COSTS when processing reg with REGNO. */
87 : #define COST_INDEX(regno) (allocno_p \
88 : ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
89 : : (int) regno)
90 :
91 : /* Record register class preferences of each allocno or pseudo. Null
92 : value means no preferences. It happens on the 1st iteration of the
93 : cost calculation. */
94 : static enum reg_class *pref;
95 :
96 : /* Allocated buffers for pref. */
97 : static enum reg_class *pref_buffer;
98 :
99 : /* Record allocno class of each allocno with the same regno. */
100 : static enum reg_class *regno_aclass;
101 :
102 : /* Record cost gains for not allocating a register with an invariant
103 : equivalence. */
104 : static int *regno_equiv_gains;
105 :
106 : /* Execution frequency of the current insn. */
107 : static int frequency;
108 :
109 :
110 :
111 : /* Info about reg classes whose costs are calculated for a pseudo. */
112 : struct cost_classes
113 : {
114 : /* Number of the cost classes in the subsequent array. */
115 : int num;
116 : /* Container of the cost classes. */
117 : enum reg_class classes[N_REG_CLASSES];
118 : /* Map reg class -> index of the reg class in the previous array.
119 : -1 if it is not a cost class. */
120 : int index[N_REG_CLASSES];
121 : /* Map hard regno index of first class in array CLASSES containing
122 : the hard regno, -1 otherwise. */
123 : int hard_regno_index[FIRST_PSEUDO_REGISTER];
124 : };
125 :
126 : /* Types of pointers to the structure above. */
127 : typedef struct cost_classes *cost_classes_t;
128 : typedef const struct cost_classes *const_cost_classes_t;
129 :
130 : /* Info about cost classes for each pseudo. */
131 : static cost_classes_t *regno_cost_classes;
132 :
133 : /* Helper for cost_classes hashing. */
134 :
135 : struct cost_classes_hasher : pointer_hash <cost_classes>
136 : {
137 : static inline hashval_t hash (const cost_classes *);
138 : static inline bool equal (const cost_classes *, const cost_classes *);
139 : static inline void remove (cost_classes *);
140 : };
141 :
142 : /* Returns hash value for cost classes info HV. */
143 : inline hashval_t
144 107924049 : cost_classes_hasher::hash (const cost_classes *hv)
145 : {
146 107924049 : return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0);
147 : }
148 :
149 : /* Compares cost classes info HV1 and HV2. */
150 : inline bool
151 99970227 : cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2)
152 : {
153 99970227 : return (hv1->num == hv2->num
154 99970227 : && memcmp (hv1->classes, hv2->classes,
155 51516938 : sizeof (enum reg_class) * hv1->num) == 0);
156 : }
157 :
158 : /* Delete cost classes info V from the hash table. */
159 : inline void
160 5986001 : cost_classes_hasher::remove (cost_classes *v)
161 : {
162 5986001 : ira_free (v);
163 5986001 : }
164 :
165 : /* Hash table of unique cost classes. */
166 : static hash_table<cost_classes_hasher> *cost_classes_htab;
167 :
168 : /* Map allocno class -> cost classes for pseudo of given allocno
169 : class. */
170 : static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES];
171 :
172 : /* Map mode -> cost classes for pseudo of give mode. */
173 : static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE];
174 :
175 : /* Cost classes that include all classes in ira_important_classes. */
176 : static cost_classes all_cost_classes;
177 :
178 : /* Use the array of classes in CLASSES_PTR to fill out the rest of
179 : the structure. */
180 : static void
181 7490041 : complete_cost_classes (cost_classes_t classes_ptr)
182 : {
183 262151435 : for (int i = 0; i < N_REG_CLASSES; i++)
184 254661394 : classes_ptr->index[i] = -1;
185 696573813 : for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++)
186 689083772 : classes_ptr->hard_regno_index[i] = -1;
187 155171869 : for (int i = 0; i < classes_ptr->num; i++)
188 : {
189 147681828 : enum reg_class cl = classes_ptr->classes[i];
190 147681828 : classes_ptr->index[cl] = i;
191 1709049841 : for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--)
192 : {
193 1561368013 : unsigned int hard_regno = ira_class_hard_regs[cl][j];
194 1561368013 : if (classes_ptr->hard_regno_index[hard_regno] < 0)
195 297228418 : classes_ptr->hard_regno_index[hard_regno] = i;
196 : }
197 : }
198 7490041 : }
199 :
200 : /* Initialize info about the cost classes for each pseudo. */
201 : static void
202 1504040 : initiate_regno_cost_classes (void)
203 : {
204 1504040 : int size = sizeof (cost_classes_t) * max_reg_num ();
205 :
206 1504040 : regno_cost_classes = (cost_classes_t *) ira_allocate (size);
207 1504040 : memset (regno_cost_classes, 0, size);
208 1504040 : memset (cost_classes_aclass_cache, 0,
209 : sizeof (cost_classes_t) * N_REG_CLASSES);
210 1504040 : memset (cost_classes_mode_cache, 0,
211 : sizeof (cost_classes_t) * MAX_MACHINE_MODE);
212 1504040 : cost_classes_htab = new hash_table<cost_classes_hasher> (200);
213 1504040 : all_cost_classes.num = ira_important_classes_num;
214 48234349 : for (int i = 0; i < ira_important_classes_num; i++)
215 46730309 : all_cost_classes.classes[i] = ira_important_classes[i];
216 1504040 : complete_cost_classes (&all_cost_classes);
217 1504040 : }
218 :
219 : /* Create new cost classes from cost classes FROM and set up members
220 : index and hard_regno_index. Return the new classes. The function
221 : implements some common code of two functions
222 : setup_regno_cost_classes_by_aclass and
223 : setup_regno_cost_classes_by_mode. */
224 : static cost_classes_t
225 5986001 : setup_cost_classes (cost_classes_t from)
226 : {
227 5986001 : cost_classes_t classes_ptr;
228 :
229 5986001 : classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes));
230 5986001 : classes_ptr->num = from->num;
231 106937520 : for (int i = 0; i < from->num; i++)
232 100951519 : classes_ptr->classes[i] = from->classes[i];
233 5986001 : complete_cost_classes (classes_ptr);
234 5986001 : return classes_ptr;
235 : }
236 :
237 : /* Return a version of FULL that only considers registers in REGS that are
238 : valid for mode MODE. Both FULL and the returned class are globally
239 : allocated. */
240 : static cost_classes_t
241 53439944 : restrict_cost_classes (cost_classes_t full, machine_mode mode,
242 : const_hard_reg_set regs)
243 : {
244 53439944 : static struct cost_classes narrow;
245 53439944 : int map[N_REG_CLASSES];
246 53439944 : narrow.num = 0;
247 1556640591 : for (int i = 0; i < full->num; i++)
248 : {
249 : /* Assume that we'll drop the class. */
250 1503200647 : map[i] = -1;
251 :
252 : /* Ignore classes that are too small for the mode. */
253 1503200647 : enum reg_class cl = full->classes[i];
254 1503200647 : if (!contains_reg_of_mode[cl][mode])
255 301842652 : continue;
256 :
257 : /* Calculate the set of registers in CL that belong to REGS and
258 : are valid for MODE. */
259 1220137916 : HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs;
260 2440275832 : valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode]
261 1220137916 : | ira_no_alloc_regs);
262 2440275832 : if (hard_reg_set_empty_p (valid_for_cl))
263 18779921 : continue;
264 :
265 : /* Don't use this class if the set of valid registers is a subset
266 : of an existing class. For example, suppose we have two classes
267 : GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
268 : that the mode changes allowed by FR_REGS are not as general as
269 : the mode changes allowed by GR_REGS.
270 :
271 : In this situation, the mode changes for GR_AND_FR_REGS could
272 : either be seen as the union or the intersection of the mode
273 : changes allowed by the two subclasses. The justification for
274 : the union-based definition would be that, if you want a mode
275 : change that's only allowed by GR_REGS, you can pick a register
276 : from the GR_REGS subclass. The justification for the
277 : intersection-based definition would be that every register
278 : from the class would allow the mode change.
279 :
280 : However, if we have a register that needs to be in GR_REGS,
281 : using GR_AND_FR_REGS with the intersection-based definition
282 : would be too pessimistic, since it would bring in restrictions
283 : that only apply to FR_REGS. Conversely, if we have a register
284 : that needs to be in FR_REGS, using GR_AND_FR_REGS with the
285 : union-based definition would lose the extra restrictions
286 : placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
287 : for cases where GR_REGS and FP_REGS are both valid. */
288 : int pos;
289 12237732365 : for (pos = 0; pos < narrow.num; ++pos)
290 : {
291 11455937991 : enum reg_class cl2 = narrow.classes[pos];
292 22911875982 : if (hard_reg_set_subset_p (valid_for_cl, reg_class_contents[cl2]))
293 : break;
294 : }
295 1201357995 : map[i] = pos;
296 1201357995 : if (pos == narrow.num)
297 : {
298 : /* If several classes are equivalent, prefer to use the one
299 : that was chosen as the allocno class. */
300 781794374 : enum reg_class cl2 = ira_allocno_class_translate[cl];
301 781794374 : if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2])
302 781794374 : cl = cl2;
303 781794374 : narrow.classes[narrow.num++] = cl;
304 : }
305 : }
306 53439944 : if (narrow.num == full->num)
307 : return full;
308 :
309 53439123 : cost_classes **slot = cost_classes_htab->find_slot (&narrow, INSERT);
310 53439123 : if (*slot == NULL)
311 : {
312 4072126 : cost_classes_t classes = setup_cost_classes (&narrow);
313 : /* Map equivalent classes to the representative that we chose above. */
314 130755607 : for (int i = 0; i < ira_important_classes_num; i++)
315 : {
316 126683481 : enum reg_class cl = ira_important_classes[i];
317 126683481 : int index = full->index[cl];
318 126683481 : if (index >= 0)
319 112655399 : classes->index[cl] = map[index];
320 : }
321 4072126 : *slot = classes;
322 : }
323 53439123 : return *slot;
324 : }
325 :
326 : /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
327 : This function is used when we know an initial approximation of
328 : allocno class of the pseudo already, e.g. on the second iteration
329 : of class cost calculation or after class cost calculation in
330 : register-pressure sensitive insn scheduling or register-pressure
331 : sensitive loop-invariant motion. */
332 : static void
333 48488505 : setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass)
334 : {
335 48488505 : static struct cost_classes classes;
336 48488505 : cost_classes_t classes_ptr;
337 48488505 : enum reg_class cl;
338 48488505 : int i;
339 48488505 : cost_classes **slot;
340 48488505 : HARD_REG_SET temp, temp2;
341 48488505 : bool exclude_p;
342 :
343 48488505 : if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL)
344 : {
345 4054439 : temp = reg_class_contents[aclass] & ~ira_no_alloc_regs;
346 : /* We exclude classes from consideration which are subsets of
347 : ACLASS only if ACLASS is an uniform class. */
348 4054439 : exclude_p = ira_uniform_class_p[aclass];
349 4054439 : classes.num = 0;
350 130141870 : for (i = 0; i < ira_important_classes_num; i++)
351 : {
352 126087431 : cl = ira_important_classes[i];
353 126087431 : if (exclude_p)
354 : {
355 : /* Exclude non-uniform classes which are subsets of
356 : ACLASS. */
357 89905665 : temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs;
358 179811330 : if (hard_reg_set_subset_p (temp2, temp) && cl != aclass)
359 10629354 : continue;
360 : }
361 115458077 : classes.classes[classes.num++] = cl;
362 : }
363 4054439 : slot = cost_classes_htab->find_slot (&classes, INSERT);
364 4054439 : if (*slot == NULL)
365 : {
366 1913875 : classes_ptr = setup_cost_classes (&classes);
367 1913875 : *slot = classes_ptr;
368 : }
369 4054439 : classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot;
370 : }
371 48488505 : if (regno_reg_rtx[regno] != NULL_RTX)
372 : {
373 : /* Restrict the classes to those that are valid for REGNO's mode
374 : (which might for example exclude singleton classes if the mode
375 : requires two registers). Also restrict the classes to those that
376 : are valid for subregs of REGNO. */
377 47899864 : const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno);
378 47899864 : if (!valid_regs)
379 46516338 : valid_regs = ®_class_contents[ALL_REGS];
380 47899864 : classes_ptr = restrict_cost_classes (classes_ptr,
381 47899864 : PSEUDO_REGNO_MODE (regno),
382 : *valid_regs);
383 : }
384 48488505 : regno_cost_classes[regno] = classes_ptr;
385 48488505 : }
386 :
387 : /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
388 : decrease number of cost classes for the pseudo, if hard registers
389 : of some important classes cannot hold a value of MODE. So the
390 : pseudo cannot get hard register of some important classes and cost
391 : calculation for such important classes is only wasting CPU
392 : time. */
393 : static void
394 66421123 : setup_regno_cost_classes_by_mode (int regno, machine_mode mode)
395 : {
396 66421123 : if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno))
397 1805341 : regno_cost_classes[regno] = restrict_cost_classes (&all_cost_classes,
398 : mode, *valid_regs);
399 : else
400 : {
401 64615782 : if (cost_classes_mode_cache[mode] == NULL)
402 3734739 : cost_classes_mode_cache[mode]
403 3734739 : = restrict_cost_classes (&all_cost_classes, mode,
404 3734739 : reg_class_contents[ALL_REGS]);
405 64615782 : regno_cost_classes[regno] = cost_classes_mode_cache[mode];
406 : }
407 66421123 : }
408 :
409 : /* Finalize info about the cost classes for each pseudo. */
410 : static void
411 1504040 : finish_regno_cost_classes (void)
412 : {
413 1504040 : ira_free (regno_cost_classes);
414 1504040 : delete cost_classes_htab;
415 1504040 : cost_classes_htab = NULL;
416 1504040 : }
417 :
418 :
419 :
420 : /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
421 : TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
422 : be a pseudo register. */
423 : static int
424 376843412 : copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p,
425 : secondary_reload_info *prev_sri)
426 : {
427 376843412 : secondary_reload_info sri;
428 376843412 : reg_class_t secondary_class = NO_REGS;
429 :
430 : /* If X is a SCRATCH, there is actually nothing to move since we are
431 : assuming optimal allocation. */
432 376843412 : if (GET_CODE (x) == SCRATCH)
433 : return 0;
434 :
435 : /* Get the class we will actually use for a reload. */
436 376833855 : rclass = targetm.preferred_reload_class (x, rclass);
437 :
438 : /* If we need a secondary reload for an intermediate, the cost is
439 : that to load the input into the intermediate register, then to
440 : copy it. */
441 376833855 : sri.prev_sri = prev_sri;
442 376833855 : sri.extra_cost = 0;
443 : /* PR 68770: Secondary reload might examine the t_icode field. */
444 376833855 : sri.t_icode = CODE_FOR_nothing;
445 :
446 376833855 : secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);
447 :
448 376833855 : if (secondary_class != NO_REGS)
449 : {
450 172888 : ira_init_register_move_cost_if_necessary (mode);
451 172888 : return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass]
452 172888 : + sri.extra_cost
453 172888 : + copy_cost (x, mode, secondary_class, to_p, &sri));
454 : }
455 :
456 : /* For memory, use the memory move cost, for (hard) registers, use
457 : the cost to move between the register classes, and use 2 for
458 : everything else (constants). */
459 376660967 : if (MEM_P (x) || rclass == NO_REGS)
460 235718038 : return sri.extra_cost
461 235718038 : + ira_memory_move_cost[mode][(int) rclass][to_p != 0];
462 140942929 : else if (REG_P (x))
463 : {
464 45268324 : reg_class_t x_class = REGNO_REG_CLASS (REGNO (x));
465 :
466 45268324 : ira_init_register_move_cost_if_necessary (mode);
467 45268324 : return (sri.extra_cost
468 45268324 : + ira_register_move_cost[mode][(int) x_class][(int) rclass]);
469 : }
470 : else
471 : /* If this is a constant, we may eventually want to call rtx_cost
472 : here. */
473 95674605 : return sri.extra_cost + COSTS_N_INSNS (1);
474 : }
475 :
476 :
477 :
478 : /* Record the cost of using memory or hard registers of various
479 : classes for the operands in INSN.
480 :
481 : N_ALTS is the number of alternatives.
482 : N_OPS is the number of operands.
483 : OPS is an array of the operands.
484 : MODES are the modes of the operands, in case any are VOIDmode.
485 : CONSTRAINTS are the constraints to use for the operands. This array
486 : is modified by this procedure.
487 :
488 : This procedure works alternative by alternative. For each
489 : alternative we assume that we will be able to allocate all allocnos
490 : to their ideal register class and calculate the cost of using that
491 : alternative. Then we compute, for each operand that is a
492 : pseudo-register, the cost of having the allocno allocated to each
493 : register class and using it in that alternative. To this cost is
494 : added the cost of the alternative.
495 :
496 : The cost of each class for this insn is its lowest cost among all
497 : the alternatives. */
498 : static void
499 138897817 : record_reg_classes (int n_alts, int n_ops, rtx *ops,
500 : machine_mode *modes, const char **constraints,
501 : rtx_insn *insn, enum reg_class *pref)
502 : {
503 138897817 : int alt;
504 138897817 : int i, j, k;
505 138897817 : int insn_allows_mem[MAX_RECOG_OPERANDS];
506 138897817 : move_table *move_in_cost, *move_out_cost;
507 138897817 : short (*mem_cost)[2];
508 138897817 : const char *p;
509 :
510 138897817 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
511 : {
512 0 : fprintf (ira_dump_file, " Processing insn %u", INSN_UID (insn));
513 0 : if (INSN_CODE (insn) >= 0
514 0 : && (p = get_insn_name (INSN_CODE (insn))) != NULL)
515 0 : fprintf (ira_dump_file, " {%s}", p);
516 0 : fprintf (ira_dump_file, " (freq=%d)\n",
517 0 : REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
518 0 : dump_insn_slim (ira_dump_file, insn);
519 : }
520 :
521 457334750 : for (i = 0; i < n_ops; i++)
522 318436933 : insn_allows_mem[i] = 0;
523 :
524 : /* Process each alternative, each time minimizing an operand's cost
525 : with the cost for each operand in that alternative. */
526 138897817 : alternative_mask preferred = get_preferred_alternatives (insn);
527 1561476467 : for (alt = 0; alt < n_alts; alt++)
528 : {
529 1422578650 : enum reg_class classes[MAX_RECOG_OPERANDS];
530 1422578650 : int allows_mem[MAX_RECOG_OPERANDS];
531 1422578650 : enum reg_class rclass;
532 1422578650 : int alt_fail = 0;
533 1422578650 : int alt_cost = 0, op_cost_add;
534 :
535 1422578650 : if (!TEST_BIT (preferred, alt))
536 : {
537 1446601141 : for (i = 0; i < recog_data.n_operands; i++)
538 2001943162 : constraints[i] = skip_alternative (constraints[i]);
539 :
540 929680536 : continue;
541 : }
542 :
543 976949090 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
544 : {
545 0 : fprintf (ira_dump_file, " Alt %d:", alt);
546 0 : for (i = 0; i < n_ops; i++)
547 : {
548 0 : p = constraints[i];
549 0 : if (*p == '\0')
550 0 : continue;
551 0 : fprintf (ira_dump_file, " (%d) ", i);
552 0 : for (; *p != '\0' && *p != ',' && *p != '#'; p++)
553 0 : fputc (*p, ira_dump_file);
554 : }
555 0 : fprintf (ira_dump_file, "\n");
556 : }
557 :
558 2318776672 : for (i = 0; i < n_ops; i++)
559 : {
560 1825878558 : unsigned char c;
561 1825878558 : const char *p = constraints[i];
562 1825878558 : rtx op = ops[i];
563 1825878558 : machine_mode mode = modes[i];
564 1825878558 : int allows_addr = 0;
565 1825878558 : int win = 0;
566 :
567 : /* Initially show we know nothing about the register class. */
568 1825878558 : classes[i] = NO_REGS;
569 1825878558 : allows_mem[i] = 0;
570 :
571 : /* If this operand has no constraints at all, we can
572 : conclude nothing about it since anything is valid. */
573 1825878558 : if (*p == 0)
574 : {
575 29246276 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
576 3 : memset (this_op_costs[i], 0, struct_costs_size);
577 29246276 : continue;
578 : }
579 :
580 : /* If this alternative is only relevant when this operand
581 : matches a previous operand, we do different things
582 : depending on whether this operand is a allocno-reg or not.
583 : We must process any modifiers for the operand before we
584 : can make this test. */
585 1898241944 : while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
586 101609662 : p++;
587 :
588 1796632282 : if (p[0] >= '0' && p[0] <= '0' + i)
589 : {
590 : /* Copy class and whether memory is allowed from the
591 : matching alternative. Then perform any needed cost
592 : computations and/or adjustments. */
593 95643040 : j = p[0] - '0';
594 95643040 : classes[i] = classes[j];
595 95643040 : allows_mem[i] = allows_mem[j];
596 95643040 : if (allows_mem[i])
597 45476391 : insn_allows_mem[i] = 1;
598 :
599 95643040 : if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
600 : {
601 : /* If this matches the other operand, we have no
602 : added cost and we win. */
603 49192993 : if (rtx_equal_p (ops[j], op))
604 1796632282 : win = 1;
605 : /* If we can put the other operand into a register,
606 : add to the cost of this alternative the cost to
607 : copy this operand to the register used for the
608 : other operand. */
609 33518319 : else if (classes[j] != NO_REGS)
610 : {
611 33353908 : alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
612 33353908 : win = 1;
613 : }
614 : }
615 46450047 : else if (! REG_P (ops[j])
616 46450047 : || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
617 : {
618 : /* This op is an allocno but the one it matches is
619 : not. */
620 :
621 : /* If we can't put the other operand into a
622 : register, this alternative can't be used. */
623 :
624 159297 : if (classes[j] == NO_REGS)
625 : {
626 1796632282 : alt_fail = 1;
627 : }
628 : else
629 : /* Otherwise, add to the cost of this alternative the cost
630 : to copy the other operand to the hard register used for
631 : this operand. */
632 : {
633 149273 : alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
634 : }
635 : }
636 : else
637 : {
638 : /* The costs of this operand are not the same as the
639 : other operand since move costs are not symmetric.
640 : Moreover, if we cannot tie them, this alternative
641 : needs to do a copy, which is one insn. */
642 46290750 : struct costs *pp = this_op_costs[i];
643 46290750 : int *pp_costs = pp->cost;
644 46290750 : cost_classes_t cost_classes_ptr
645 46290750 : = regno_cost_classes[REGNO (op)];
646 46290750 : enum reg_class *cost_classes = cost_classes_ptr->classes;
647 46290750 : bool in_p = recog_data.operand_type[i] != OP_OUT;
648 46290750 : bool out_p = recog_data.operand_type[i] != OP_IN;
649 46290750 : enum reg_class op_class = classes[i];
650 :
651 46290750 : ira_init_register_move_cost_if_necessary (mode);
652 46290750 : if (! in_p)
653 : {
654 59313 : ira_assert (out_p);
655 59313 : if (op_class == NO_REGS)
656 : {
657 0 : mem_cost = ira_memory_move_cost[mode];
658 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
659 : {
660 0 : rclass = cost_classes[k];
661 0 : pp_costs[k] = mem_cost[rclass][0] * frequency;
662 : }
663 : }
664 : else
665 : {
666 59313 : move_out_cost = ira_may_move_out_cost[mode];
667 821010 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
668 : {
669 761697 : rclass = cost_classes[k];
670 761697 : pp_costs[k]
671 761697 : = move_out_cost[op_class][rclass] * frequency;
672 : }
673 : }
674 : }
675 46231437 : else if (! out_p)
676 : {
677 46231437 : ira_assert (in_p);
678 46231437 : if (op_class == NO_REGS)
679 : {
680 432582 : mem_cost = ira_memory_move_cost[mode];
681 6322512 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
682 : {
683 5889930 : rclass = cost_classes[k];
684 5889930 : pp_costs[k] = mem_cost[rclass][1] * frequency;
685 : }
686 : }
687 : else
688 : {
689 45798855 : move_in_cost = ira_may_move_in_cost[mode];
690 691485509 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
691 : {
692 645686654 : rclass = cost_classes[k];
693 645686654 : pp_costs[k]
694 645686654 : = move_in_cost[rclass][op_class] * frequency;
695 : }
696 : }
697 : }
698 : else
699 : {
700 0 : if (op_class == NO_REGS)
701 : {
702 0 : mem_cost = ira_memory_move_cost[mode];
703 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
704 : {
705 0 : rclass = cost_classes[k];
706 0 : pp_costs[k] = ((mem_cost[rclass][0]
707 0 : + mem_cost[rclass][1])
708 0 : * frequency);
709 : }
710 : }
711 : else
712 : {
713 0 : move_in_cost = ira_may_move_in_cost[mode];
714 0 : move_out_cost = ira_may_move_out_cost[mode];
715 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
716 : {
717 0 : rclass = cost_classes[k];
718 0 : pp_costs[k] = ((move_in_cost[rclass][op_class]
719 0 : + move_out_cost[op_class][rclass])
720 0 : * frequency);
721 : }
722 : }
723 : }
724 :
725 46290750 : if (op_class == NO_REGS)
726 : /* Although we don't need insn to reload from
727 : memory, still accessing memory is usually more
728 : expensive than a register. */
729 432582 : pp->mem_cost = frequency;
730 : else
731 : /* If the alternative actually allows memory, make
732 : things a bit cheaper since we won't need an
733 : extra insn to load it. */
734 45858168 : pp->mem_cost
735 45858168 : = ((out_p
736 45858168 : ? ira_memory_move_cost[mode][op_class][0] : 0)
737 45858168 : + (in_p
738 45858168 : ? ira_memory_move_cost[mode][op_class][1] : 0)
739 45858168 : - allows_mem[i]) * frequency;
740 :
741 : /* If we have assigned a class to this allocno in
742 : our first pass, add a cost to this alternative
743 : corresponding to what we would add if this
744 : allocno were not in the appropriate class. */
745 46290750 : if (pref)
746 : {
747 17551434 : enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
748 :
749 17551434 : if (pref_class == NO_REGS)
750 : {
751 605924 : if (op_class != NO_REGS)
752 602845 : alt_cost
753 602845 : += ((out_p
754 602845 : ? ira_memory_move_cost[mode][op_class][0]
755 : : 0)
756 602845 : + (in_p
757 602845 : ? ira_memory_move_cost[mode][op_class][1]
758 : : 0));
759 : }
760 16945510 : else if (op_class == NO_REGS)
761 172592 : alt_cost
762 172592 : += ((out_p
763 172592 : ? ira_memory_move_cost[mode][pref_class][0]
764 : : 0)
765 172592 : + (in_p
766 172592 : ? ira_memory_move_cost[mode][pref_class][1]
767 : : 0));
768 16772918 : else if (ira_reg_class_intersect
769 16772918 : [pref_class][op_class] == NO_REGS)
770 142843 : alt_cost += (ira_register_move_cost
771 142843 : [mode][pref_class][op_class]);
772 : }
773 46290750 : if (REGNO (ops[i]) != REGNO (ops[j])
774 46290750 : && ! find_reg_note (insn, REG_DEAD, op))
775 12989131 : alt_cost += 2;
776 :
777 46290750 : p++;
778 : }
779 : }
780 :
781 : /* Scan all the constraint letters. See if the operand
782 : matches any of the constraints. Collect the valid
783 : register classes and see if this operand accepts
784 : memory. */
785 4335800755 : while ((c = *p))
786 : {
787 4269790879 : switch (c)
788 : {
789 316782477 : case '*':
790 : /* Ignore the next letter for this pass. */
791 316782477 : c = *++p;
792 316782477 : break;
793 :
794 0 : case '^':
795 0 : alt_cost += 2;
796 0 : break;
797 :
798 503933010 : case '?':
799 503933010 : alt_cost += 2;
800 503933010 : break;
801 :
802 12663761 : case 'g':
803 12663761 : if (MEM_P (op)
804 12663761 : || (CONSTANT_P (op)
805 5102033 : && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
806 : win = 1;
807 12663761 : insn_allows_mem[i] = allows_mem[i] = 1;
808 12663761 : classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS];
809 12663761 : break;
810 :
811 3436411631 : default:
812 3436411631 : enum constraint_num cn = lookup_constraint (p);
813 3436411631 : enum reg_class cl;
814 3436411631 : switch (get_constraint_type (cn))
815 : {
816 2793141826 : case CT_REGISTER:
817 2793141826 : cl = reg_class_for_constraint (cn);
818 997938189 : if (cl != NO_REGS)
819 987373463 : classes[i] = ira_reg_class_subunion[classes[i]][cl];
820 : break;
821 :
822 4759172 : case CT_CONST_INT:
823 4759172 : if (CONST_INT_P (op)
824 4759172 : && insn_const_int_ok_for_constraint (INTVAL (op), cn))
825 : win = 1;
826 : break;
827 :
828 275034110 : case CT_MEMORY:
829 275034110 : case CT_RELAXED_MEMORY:
830 : /* Every MEM can be reloaded to fit. */
831 275034110 : insn_allows_mem[i] = allows_mem[i] = 1;
832 275034110 : if (MEM_P (op))
833 79463358 : win = 1;
834 : break;
835 :
836 39541490 : case CT_SPECIAL_MEMORY:
837 39541490 : insn_allows_mem[i] = allows_mem[i] = 1;
838 39541490 : if (MEM_P (extract_mem_from_operand (op))
839 39541490 : && constraint_satisfied_p (op, cn))
840 : win = 1;
841 : break;
842 :
843 1152922 : case CT_ADDRESS:
844 : /* Every address can be reloaded to fit. */
845 1152922 : allows_addr = 1;
846 1152922 : if (address_operand (op, GET_MODE (op))
847 1152922 : || constraint_satisfied_p (op, cn))
848 : win = 1;
849 : /* We know this operand is an address, so we
850 : want it to be allocated to a hard register
851 : that can be the base of an address,
852 : i.e. BASE_REG_CLASS. */
853 1152922 : classes[i]
854 2305844 : = ira_reg_class_subunion[classes[i]]
855 1152922 : [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
856 1152922 : ADDRESS, SCRATCH)];
857 1152922 : break;
858 :
859 322782111 : case CT_FIXED_FORM:
860 322782111 : if (constraint_satisfied_p (op, cn))
861 4269790879 : win = 1;
862 : break;
863 : }
864 : break;
865 : }
866 4269790879 : p += CONSTRAINT_LEN (c, p);
867 4269790879 : if (c == ',')
868 : break;
869 : }
870 :
871 1796632282 : constraints[i] = p;
872 :
873 1796632282 : if (alt_fail)
874 : break;
875 :
876 : /* How we account for this operand now depends on whether it
877 : is a pseudo register or not. If it is, we first check if
878 : any register classes are valid. If not, we ignore this
879 : alternative, since we want to assume that all allocnos get
880 : allocated for register preferencing. If some register
881 : class is valid, compute the costs of moving the allocno
882 : into that class. */
883 1796622258 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
884 : {
885 811778781 : if (classes[i] == NO_REGS && ! allows_mem[i])
886 : {
887 : /* We must always fail if the operand is a REG, but
888 : we did not find a suitable class and memory is
889 : not allowed.
890 :
891 : Otherwise we may perform an uninitialized read
892 : from this_op_costs after the `continue' statement
893 : below. */
894 : alt_fail = 1;
895 : }
896 : else
897 : {
898 609230327 : unsigned int regno = REGNO (op);
899 609230327 : struct costs *pp = this_op_costs[i];
900 609230327 : int *pp_costs = pp->cost;
901 609230327 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
902 609230327 : enum reg_class *cost_classes = cost_classes_ptr->classes;
903 609230327 : bool in_p = recog_data.operand_type[i] != OP_OUT;
904 609230327 : bool out_p = recog_data.operand_type[i] != OP_IN;
905 609230327 : enum reg_class op_class = classes[i];
906 :
907 609230327 : ira_init_register_move_cost_if_necessary (mode);
908 609230327 : if (! in_p)
909 : {
910 389426618 : ira_assert (out_p);
911 389426618 : if (op_class == NO_REGS)
912 : {
913 71707414 : mem_cost = ira_memory_move_cost[mode];
914 1108133231 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
915 : {
916 1036425817 : rclass = cost_classes[k];
917 1036425817 : pp_costs[k] = mem_cost[rclass][0] * frequency;
918 : }
919 : }
920 : else
921 : {
922 317719204 : move_out_cost = ira_may_move_out_cost[mode];
923 4815687022 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
924 : {
925 4497967818 : rclass = cost_classes[k];
926 4497967818 : pp_costs[k]
927 4497967818 : = move_out_cost[op_class][rclass] * frequency;
928 : }
929 : }
930 : }
931 219803709 : else if (! out_p)
932 : {
933 219790544 : ira_assert (in_p);
934 219790544 : if (op_class == NO_REGS)
935 : {
936 16405941 : mem_cost = ira_memory_move_cost[mode];
937 241808991 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
938 : {
939 225403050 : rclass = cost_classes[k];
940 225403050 : pp_costs[k] = mem_cost[rclass][1] * frequency;
941 : }
942 : }
943 : else
944 : {
945 203384603 : move_in_cost = ira_may_move_in_cost[mode];
946 2986472849 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
947 : {
948 2783088246 : rclass = cost_classes[k];
949 2783088246 : pp_costs[k]
950 2783088246 : = move_in_cost[rclass][op_class] * frequency;
951 : }
952 : }
953 : }
954 : else
955 : {
956 13165 : if (op_class == NO_REGS)
957 : {
958 0 : mem_cost = ira_memory_move_cost[mode];
959 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
960 : {
961 0 : rclass = cost_classes[k];
962 0 : pp_costs[k] = ((mem_cost[rclass][0]
963 0 : + mem_cost[rclass][1])
964 0 : * frequency);
965 : }
966 : }
967 : else
968 : {
969 13165 : move_in_cost = ira_may_move_in_cost[mode];
970 13165 : move_out_cost = ira_may_move_out_cost[mode];
971 155368 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
972 : {
973 142203 : rclass = cost_classes[k];
974 142203 : pp_costs[k] = ((move_in_cost[rclass][op_class]
975 142203 : + move_out_cost[op_class][rclass])
976 142203 : * frequency);
977 : }
978 : }
979 : }
980 :
981 609230327 : if (op_class == NO_REGS)
982 : /* Although we don't need insn to reload from
983 : memory, still accessing memory is usually more
984 : expensive than a register. */
985 88113355 : pp->mem_cost = frequency;
986 : else
987 : /* If the alternative actually allows memory, make
988 : things a bit cheaper since we won't need an
989 : extra insn to load it. */
990 521116972 : pp->mem_cost
991 521116972 : = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)
992 521116972 : + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)
993 521116972 : - allows_mem[i]) * frequency;
994 : /* If we have assigned a class to this allocno in
995 : our first pass, add a cost to this alternative
996 : corresponding to what we would add if this
997 : allocno were not in the appropriate class. */
998 609230327 : if (pref)
999 : {
1000 222457580 : enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
1001 :
1002 222457580 : if (pref_class == NO_REGS)
1003 : {
1004 4206845 : if (op_class != NO_REGS)
1005 3396917 : alt_cost
1006 3396917 : += ((out_p
1007 3396917 : ? ira_memory_move_cost[mode][op_class][0]
1008 : : 0)
1009 3396917 : + (in_p
1010 3396917 : ? ira_memory_move_cost[mode][op_class][1]
1011 : : 0));
1012 : }
1013 218250735 : else if (op_class == NO_REGS)
1014 30066895 : alt_cost
1015 30066895 : += ((out_p
1016 30066895 : ? ira_memory_move_cost[mode][pref_class][0]
1017 : : 0)
1018 30066895 : + (in_p
1019 30066895 : ? ira_memory_move_cost[mode][pref_class][1]
1020 : : 0));
1021 188183840 : else if (ira_reg_class_intersect[pref_class][op_class]
1022 : == NO_REGS)
1023 40151439 : alt_cost += (ira_register_move_cost
1024 40151439 : [mode][pref_class][op_class]);
1025 : }
1026 : }
1027 : }
1028 :
1029 : /* Otherwise, if this alternative wins, either because we
1030 : have already determined that or if we have a hard
1031 : register of the proper class, there is no cost for this
1032 : alternative. */
1033 984843477 : else if (win || (REG_P (op)
1034 234552536 : && reg_fits_class_p (op, classes[i],
1035 234552536 : 0, GET_MODE (op))))
1036 : ;
1037 :
1038 : /* If registers are valid, the cost of this alternative
1039 : includes copying the object to and/or from a
1040 : register. */
1041 645365318 : else if (classes[i] != NO_REGS)
1042 : {
1043 343167319 : if (recog_data.operand_type[i] != OP_OUT)
1044 183188120 : alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
1045 :
1046 343167319 : if (recog_data.operand_type[i] != OP_IN)
1047 159979223 : alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
1048 : }
1049 : /* The only other way this alternative can be used is if
1050 : this is a constant that could be placed into memory. */
1051 302197999 : else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1052 20705501 : alt_cost += ira_memory_move_cost[mode][classes[i]][1];
1053 : else
1054 : alt_fail = 1;
1055 :
1056 : if (alt_fail)
1057 : break;
1058 : }
1059 :
1060 976949090 : if (alt_fail)
1061 : {
1062 : /* The loop above might have exited early once the failure
1063 : was seen. Skip over the constraints for the remaining
1064 : operands. */
1065 484050976 : i += 1;
1066 775701189 : for (; i < n_ops; ++i)
1067 583300426 : constraints[i] = skip_alternative (constraints[i]);
1068 484050976 : continue;
1069 : }
1070 :
1071 492898114 : op_cost_add = alt_cost * frequency;
1072 : /* Finally, update the costs with the information we've
1073 : calculated about this alternative. */
1074 1594547360 : for (i = 0; i < n_ops; i++)
1075 1101649246 : if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1076 : {
1077 465447409 : int old_cost;
1078 465447409 : bool cost_change_p = false;
1079 465447409 : struct costs *pp = op_costs[i], *qq = this_op_costs[i];
1080 465447409 : int *pp_costs = pp->cost, *qq_costs = qq->cost;
1081 465447409 : int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1082 465447409 : cost_classes_t cost_classes_ptr
1083 465447409 : = regno_cost_classes[REGNO (ops[i])];
1084 :
1085 465447409 : old_cost = pp->mem_cost;
1086 465447409 : pp->mem_cost = MIN (old_cost,
1087 : (qq->mem_cost + op_cost_add) * scale);
1088 :
1089 465447409 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1090 0 : && pp->mem_cost < old_cost)
1091 : {
1092 0 : cost_change_p = true;
1093 0 : fprintf (ira_dump_file, " op %d(r=%u) new costs MEM:%d",
1094 : i, REGNO(ops[i]), pp->mem_cost);
1095 : }
1096 6957595350 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1097 : {
1098 6492147941 : old_cost = pp_costs[k];
1099 6492147941 : pp_costs[k]
1100 6492147941 : = MIN (old_cost, (qq_costs[k] + op_cost_add) * scale);
1101 6492147941 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1102 0 : && pp_costs[k] < old_cost)
1103 : {
1104 0 : if (!cost_change_p)
1105 0 : fprintf (ira_dump_file, " op %d(r=%u) new costs",
1106 : i, REGNO(ops[i]));
1107 0 : cost_change_p = true;
1108 0 : fprintf (ira_dump_file, " %s:%d",
1109 0 : reg_class_names[cost_classes_ptr->classes[k]],
1110 : pp_costs[k]);
1111 : }
1112 : }
1113 465447409 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1114 0 : && cost_change_p)
1115 0 : fprintf (ira_dump_file, "\n");
1116 : }
1117 : }
1118 :
1119 138897817 : if (allocno_p)
1120 444778427 : for (i = 0; i < n_ops; i++)
1121 : {
1122 309681560 : ira_allocno_t a;
1123 309681560 : rtx op = ops[i];
1124 :
1125 309681560 : if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1126 180364466 : continue;
1127 129317094 : a = ira_curr_regno_allocno_map [REGNO (op)];
1128 129317094 : if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0)
1129 11997678 : ALLOCNO_BAD_SPILL_P (a) = true;
1130 : }
1131 :
1132 138897817 : }
1133 :
1134 :
1135 :
1136 : /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1137 : static inline bool
1138 135184 : ok_for_index_p_nonstrict (rtx reg)
1139 : {
1140 135184 : unsigned regno = REGNO (reg);
1141 :
1142 135184 : return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
1143 : }
1144 :
1145 : /* A version of regno_ok_for_base_p for use here, when all
1146 : pseudo-registers should count as OK. Arguments as for
1147 : regno_ok_for_base_p. */
1148 : static inline bool
1149 137500 : ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
1150 : enum rtx_code outer_code, enum rtx_code index_code)
1151 : {
1152 137500 : unsigned regno = REGNO (reg);
1153 :
1154 1158 : if (regno >= FIRST_PSEUDO_REGISTER)
1155 : return true;
1156 1158 : return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
1157 : }
1158 :
1159 : /* Record the pseudo registers we must reload into hard registers in a
1160 : subexpression of a memory address, X.
1161 :
1162 : If CONTEXT is 0, we are looking at the base part of an address,
1163 : otherwise we are looking at the index part.
1164 :
1165 : MODE and AS are the mode and address space of the memory reference;
1166 : OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1167 : These four arguments are passed down to base_reg_class.
1168 :
1169 : SCALE is twice the amount to multiply the cost by (it is twice so
1170 : we can represent half-cost adjustments). */
1171 : static void
1172 94012182 : record_address_regs (machine_mode mode, addr_space_t as, rtx x,
1173 : int context, enum rtx_code outer_code,
1174 : enum rtx_code index_code, int scale)
1175 : {
1176 94012182 : enum rtx_code code = GET_CODE (x);
1177 94012182 : enum reg_class rclass;
1178 :
1179 94012182 : if (context == 1)
1180 : rclass = INDEX_REG_CLASS;
1181 : else
1182 86688333 : rclass = base_reg_class (mode, as, outer_code, index_code);
1183 :
1184 94012182 : switch (code)
1185 : {
1186 : case CONST_INT:
1187 : case CONST:
1188 : case PC:
1189 : case SYMBOL_REF:
1190 : case LABEL_REF:
1191 : return;
1192 :
1193 33075585 : case PLUS:
1194 : /* When we have an address that is a sum, we must determine
1195 : whether registers are "base" or "index" regs. If there is a
1196 : sum of two registers, we must choose one to be the "base".
1197 : Luckily, we can use the REG_POINTER to make a good choice
1198 : most of the time. We only need to do this on machines that
1199 : can have two registers in an address and where the base and
1200 : index register classes are different.
1201 :
1202 : ??? This code used to set REGNO_POINTER_FLAG in some cases,
1203 : but that seems bogus since it should only be set when we are
1204 : sure the register is being used as a pointer. */
1205 33075585 : {
1206 33075585 : rtx arg0 = XEXP (x, 0);
1207 33075585 : rtx arg1 = XEXP (x, 1);
1208 33075585 : enum rtx_code code0 = GET_CODE (arg0);
1209 33075585 : enum rtx_code code1 = GET_CODE (arg1);
1210 :
1211 : /* Look inside subregs. */
1212 33075585 : if (code0 == SUBREG)
1213 11899 : arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1214 33075585 : if (code1 == SUBREG)
1215 4800 : arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1216 :
1217 : /* If index registers do not appear, or coincide with base registers,
1218 : just record registers in any non-constant operands. We
1219 : assume here, as well as in the tests below, that all
1220 : addresses are in canonical form. */
1221 66151170 : if (MAX_REGS_PER_ADDRESS == 1
1222 33075585 : || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH))
1223 : {
1224 0 : record_address_regs (mode, as, arg0, context, PLUS, code1, scale);
1225 0 : if (! CONSTANT_P (arg1))
1226 0 : record_address_regs (mode, as, arg1, context, PLUS, code0, scale);
1227 : }
1228 :
1229 : /* If the second operand is a constant integer, it doesn't
1230 : change what class the first operand must be. */
1231 33075585 : else if (CONST_SCALAR_INT_P (arg1))
1232 29453332 : record_address_regs (mode, as, arg0, context, PLUS, code1, scale);
1233 : /* If the second operand is a symbolic constant, the first
1234 : operand must be an index register. */
1235 3622253 : else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1236 931316 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale);
1237 : /* If both operands are registers but one is already a hard
1238 : register of index or reg-base class, give the other the
1239 : class that the hard register is not. */
1240 2690937 : else if (code0 == REG && code1 == REG
1241 1492871 : && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1242 2826385 : && (ok_for_base_p_nonstrict (arg0, mode, as, PLUS, REG)
1243 134300 : || ok_for_index_p_nonstrict (arg0)))
1244 3444 : record_address_regs (mode, as, arg1,
1245 3444 : ok_for_base_p_nonstrict (arg0, mode, as,
1246 : PLUS, REG) ? 1 : 0,
1247 : PLUS, REG, scale);
1248 2689789 : else if (code0 == REG && code1 == REG
1249 1491723 : && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1250 2690683 : && (ok_for_base_p_nonstrict (arg1, mode, as, PLUS, REG)
1251 884 : || ok_for_index_p_nonstrict (arg1)))
1252 30 : record_address_regs (mode, as, arg0,
1253 30 : ok_for_base_p_nonstrict (arg1, mode, as,
1254 : PLUS, REG) ? 1 : 0,
1255 : PLUS, REG, scale);
1256 : /* If one operand is known to be a pointer, it must be the
1257 : base with the other operand the index. Likewise if the
1258 : other operand is a MULT. */
1259 2689779 : else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT)
1260 : {
1261 1278825 : record_address_regs (mode, as, arg0, 0, PLUS, code1, scale);
1262 1278825 : record_address_regs (mode, as, arg1, 1, PLUS, code0, scale);
1263 : }
1264 1410954 : else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT)
1265 : {
1266 1040302 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale);
1267 1040302 : record_address_regs (mode, as, arg1, 0, PLUS, code0, scale);
1268 : }
1269 : /* Otherwise, count equal chances that each might be a base or
1270 : index register. This case should be rare. */
1271 : else
1272 : {
1273 370652 : record_address_regs (mode, as, arg0, 0, PLUS, code1, scale / 2);
1274 370652 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale / 2);
1275 370652 : record_address_regs (mode, as, arg1, 0, PLUS, code0, scale / 2);
1276 370652 : record_address_regs (mode, as, arg1, 1, PLUS, code0, scale / 2);
1277 : }
1278 : }
1279 : break;
1280 :
1281 : /* Double the importance of an allocno that is incremented or
1282 : decremented, since it would take two extra insns if it ends
1283 : up in the wrong place. */
1284 165588 : case POST_MODIFY:
1285 165588 : case PRE_MODIFY:
1286 165588 : record_address_regs (mode, as, XEXP (x, 0), 0, code,
1287 165588 : GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
1288 165588 : if (REG_P (XEXP (XEXP (x, 1), 1)))
1289 0 : record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), 1, code, REG,
1290 : 2 * scale);
1291 : break;
1292 :
1293 3366118 : case POST_INC:
1294 3366118 : case PRE_INC:
1295 3366118 : case POST_DEC:
1296 3366118 : case PRE_DEC:
1297 : /* Double the importance of an allocno that is incremented or
1298 : decremented, since it would take two extra insns if it ends
1299 : up in the wrong place. */
1300 3366118 : record_address_regs (mode, as, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
1301 3366118 : break;
1302 :
1303 45077772 : case REG:
1304 45077772 : {
1305 45077772 : struct costs *pp;
1306 45077772 : int *pp_costs;
1307 45077772 : enum reg_class i;
1308 45077772 : int k, regno, add_cost;
1309 45077772 : cost_classes_t cost_classes_ptr;
1310 45077772 : enum reg_class *cost_classes;
1311 45077772 : move_table *move_in_cost;
1312 :
1313 45077772 : if (REGNO (x) < FIRST_PSEUDO_REGISTER)
1314 : break;
1315 :
1316 20771991 : regno = REGNO (x);
1317 20771991 : if (allocno_p)
1318 20394886 : ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true;
1319 20771991 : pp = COSTS (costs, COST_INDEX (regno));
1320 20771991 : add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2;
1321 20771991 : if (INT_MAX - add_cost < pp->mem_cost)
1322 0 : pp->mem_cost = INT_MAX;
1323 : else
1324 20771991 : pp->mem_cost += add_cost;
1325 20771991 : cost_classes_ptr = regno_cost_classes[regno];
1326 20771991 : cost_classes = cost_classes_ptr->classes;
1327 20771991 : pp_costs = pp->cost;
1328 20771991 : ira_init_register_move_cost_if_necessary (Pmode);
1329 20771991 : move_in_cost = ira_may_move_in_cost[Pmode];
1330 335656540 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1331 : {
1332 314884549 : i = cost_classes[k];
1333 314884549 : add_cost = (move_in_cost[i][rclass] * scale) / 2;
1334 314884549 : if (INT_MAX - add_cost < pp_costs[k])
1335 14447 : pp_costs[k] = INT_MAX;
1336 : else
1337 314870102 : pp_costs[k] += add_cost;
1338 : }
1339 : }
1340 : break;
1341 :
1342 2197272 : default:
1343 2197272 : {
1344 2197272 : const char *fmt = GET_RTX_FORMAT (code);
1345 2197272 : int i;
1346 6086516 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1347 3889244 : if (fmt[i] == 'e')
1348 3873942 : record_address_regs (mode, as, XEXP (x, i), context, code, SCRATCH,
1349 : scale);
1350 : }
1351 : }
1352 : }
1353 :
1354 :
1355 :
1356 : /* Calculate the costs of insn operands. */
1357 : static void
1358 139755027 : record_operand_costs (rtx_insn *insn, enum reg_class *pref)
1359 : {
1360 139755027 : const char *constraints[MAX_RECOG_OPERANDS];
1361 139755027 : machine_mode modes[MAX_RECOG_OPERANDS];
1362 139755027 : rtx set;
1363 139755027 : int i;
1364 :
1365 139755027 : if ((set = single_set (insn)) != NULL_RTX
1366 : /* In rare cases the single set insn might have less 2 operands
1367 : as the source can be a fixed special reg. */
1368 132155879 : && recog_data.n_operands > 1
1369 127181800 : && recog_data.operand[0] == SET_DEST (set)
1370 244111721 : && recog_data.operand[1] == SET_SRC (set))
1371 : {
1372 75711831 : int regno, other_regno;
1373 75711831 : rtx dest = SET_DEST (set);
1374 75711831 : rtx src = SET_SRC (set);
1375 :
1376 75711831 : if (GET_CODE (dest) == SUBREG
1377 77709351 : && known_eq (GET_MODE_SIZE (GET_MODE (dest)),
1378 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
1379 : dest = SUBREG_REG (dest);
1380 75711831 : if (GET_CODE (src) == SUBREG
1381 78532095 : && known_eq (GET_MODE_SIZE (GET_MODE (src)),
1382 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
1383 : src = SUBREG_REG (src);
1384 35688969 : if (REG_P (src) && REG_P (dest)
1385 96834084 : && (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
1386 14636417 : && (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER)
1387 9996130 : || ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER
1388 9967854 : && (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER)))
1389 : {
1390 17583683 : machine_mode mode = GET_MODE (SET_SRC (set)), cost_mode = mode;
1391 17583683 : machine_mode hard_reg_mode = GET_MODE(regno_reg_rtx[other_regno]);
1392 35167366 : poly_int64 pmode_size = GET_MODE_SIZE (mode);
1393 35167366 : poly_int64 phard_reg_mode_size = GET_MODE_SIZE (hard_reg_mode);
1394 17583683 : HOST_WIDE_INT mode_size, hard_reg_mode_size;
1395 17583683 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1396 17583683 : enum reg_class *cost_classes = cost_classes_ptr->classes;
1397 17583683 : reg_class_t rclass, hard_reg_class, bigger_hard_reg_class;
1398 17583683 : int cost_factor = 1, cost, k;
1399 17583683 : move_table *move_costs;
1400 17583683 : bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src));
1401 :
1402 17583683 : hard_reg_class = REGNO_REG_CLASS (other_regno);
1403 17583683 : bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class];
1404 : /* Target code may return any cost for mode which does not fit the
1405 : hard reg class (e.g. DImode for AREG on i386). Check this and use
1406 : a bigger class to get the right cost. */
1407 17583683 : if (bigger_hard_reg_class != NO_REGS
1408 17583683 : && ! ira_hard_reg_in_set_p (other_regno, mode,
1409 : reg_class_contents[hard_reg_class]))
1410 : hard_reg_class = bigger_hard_reg_class;
1411 17583683 : ira_init_register_move_cost_if_necessary (mode);
1412 17583683 : ira_init_register_move_cost_if_necessary (hard_reg_mode);
1413 : /* Use smaller movement cost for natural hard reg mode or its mode as
1414 : operand. */
1415 17583683 : if (pmode_size.is_constant (&mode_size)
1416 17583683 : && phard_reg_mode_size.is_constant (&hard_reg_mode_size))
1417 : {
1418 : /* Assume we are moving in the natural modes: */
1419 17583683 : cost_factor = mode_size / hard_reg_mode_size;
1420 17583683 : if (mode_size % hard_reg_mode_size != 0)
1421 3808893 : cost_factor++;
1422 17583683 : if (cost_factor
1423 17583683 : * (ira_register_move_cost
1424 17583683 : [hard_reg_mode][hard_reg_class][hard_reg_class])
1425 : < (ira_register_move_cost
1426 17583683 : [mode][hard_reg_class][hard_reg_class]))
1427 0 : cost_mode = hard_reg_mode;
1428 : else
1429 : cost_factor = 1;
1430 : }
1431 17583683 : move_costs = ira_register_move_cost[cost_mode];
1432 17583683 : i = regno == (int) REGNO (src) ? 1 : 0;
1433 330414858 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1434 : {
1435 312831175 : rclass = cost_classes[k];
1436 625662350 : cost = (i == 0
1437 312831175 : ? move_costs[hard_reg_class][rclass]
1438 199564577 : : move_costs[rclass][hard_reg_class]);
1439 312831175 : cost *= cost_factor;
1440 312831175 : op_costs[i]->cost[k] = cost * frequency;
1441 : /* If this insn is a single set copying operand 1 to
1442 : operand 0 and one operand is an allocno with the
1443 : other a hard reg or an allocno that prefers a hard
1444 : register that is in its own register class then we
1445 : may want to adjust the cost of that register class to
1446 : -1.
1447 :
1448 : Avoid the adjustment if the source does not die to
1449 : avoid stressing of register allocator by preferencing
1450 : two colliding registers into single class. */
1451 312831175 : if (dead_p
1452 253528143 : && TEST_HARD_REG_BIT (reg_class_contents[rclass], other_regno)
1453 312831175 : && (reg_class_size[(int) rclass]
1454 : == (ira_reg_class_max_nregs
1455 104761758 : [(int) rclass][(int) GET_MODE(src)])))
1456 : {
1457 13314405 : if (reg_class_size[rclass] == 1)
1458 13161584 : op_costs[i]->cost[k] = -frequency;
1459 152821 : else if (in_hard_reg_set_p (reg_class_contents[rclass],
1460 : GET_MODE(src), other_regno))
1461 124909 : op_costs[i]->cost[k] = -frequency;
1462 : }
1463 : }
1464 17583683 : op_costs[i]->mem_cost
1465 17583683 : = ira_memory_move_cost[mode][hard_reg_class][i] * frequency;
1466 17583683 : return;
1467 : }
1468 : }
1469 :
1470 389653762 : for (i = 0; i < recog_data.n_operands; i++)
1471 : {
1472 267482418 : constraints[i] = recog_data.constraints[i];
1473 267482418 : modes[i] = recog_data.operand_mode[i];
1474 : }
1475 :
1476 : /* If we get here, we are set up to record the costs of all the
1477 : operands for this insn. Start by initializing the costs. Then
1478 : handle any address registers. Finally record the desired classes
1479 : for any allocnos, doing it twice if some pair of operands are
1480 : commutative. */
1481 389653762 : for (i = 0; i < recog_data.n_operands; i++)
1482 : {
1483 267482418 : rtx op_mem = extract_mem_from_operand (recog_data.operand[i]);
1484 267482418 : memcpy (op_costs[i], init_cost, struct_costs_size);
1485 :
1486 267482418 : if (GET_CODE (recog_data.operand[i]) == SUBREG)
1487 5079400 : recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
1488 :
1489 267482418 : if (MEM_P (op_mem))
1490 44406899 : record_address_regs (GET_MODE (op_mem),
1491 44406899 : MEM_ADDR_SPACE (op_mem),
1492 : XEXP (op_mem, 0),
1493 : 0, MEM, SCRATCH, frequency * 2);
1494 223075519 : else if (constraints[i][0] == 'p'
1495 446146950 : || (insn_extra_address_constraint
1496 223071431 : (lookup_constraint (constraints[i]))))
1497 1152911 : record_address_regs (VOIDmode, ADDR_SPACE_GENERIC,
1498 : recog_data.operand[i], 0, ADDRESS, SCRATCH,
1499 : frequency * 2);
1500 : }
1501 :
1502 : /* Check for commutative in a separate loop so everything will have
1503 : been initialized. We must do this even if one operand is a
1504 : constant--see addsi3 in m68k.md. */
1505 268394592 : for (i = 0; i < (int) recog_data.n_operands - 1; i++)
1506 146223248 : if (constraints[i][0] == '%')
1507 : {
1508 : const char *xconstraints[MAX_RECOG_OPERANDS];
1509 : int j;
1510 :
1511 : /* Handle commutative operands by swapping the
1512 : constraints. We assume the modes are the same. */
1513 67680988 : for (j = 0; j < recog_data.n_operands; j++)
1514 50954515 : xconstraints[j] = constraints[j];
1515 :
1516 16726473 : xconstraints[i] = constraints[i+1];
1517 16726473 : xconstraints[i+1] = constraints[i];
1518 16726473 : record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1519 : recog_data.operand, modes,
1520 : xconstraints, insn, pref);
1521 : }
1522 122171344 : record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1523 : recog_data.operand, modes,
1524 : constraints, insn, pref);
1525 : }
1526 :
1527 :
1528 :
1529 : /* Process one insn INSN. Scan it and record each time it would save
1530 : code to put a certain allocnos in a certain class. Return the last
1531 : insn processed, so that the scan can be continued from there. */
1532 : static rtx_insn *
1533 284990043 : scan_one_insn (rtx_insn *insn)
1534 : {
1535 284990043 : enum rtx_code pat_code;
1536 284990043 : rtx set, note;
1537 284990043 : int i, k;
1538 284990043 : bool counted_mem;
1539 :
1540 284990043 : if (!NONDEBUG_INSN_P (insn))
1541 : return insn;
1542 :
1543 141143797 : pat_code = GET_CODE (PATTERN (insn));
1544 141143797 : if (pat_code == ASM_INPUT)
1545 : return insn;
1546 :
1547 : /* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead
1548 : and initialize the register move costs of mode M.
1549 :
1550 : The pseudo may be related to another pseudo via a copy (implicit or
1551 : explicit) and if there are no mode M uses/sets of the original
1552 : pseudo, then we may leave the register move costs uninitialized for
1553 : mode M. */
1554 141139963 : if (pat_code == USE || pat_code == CLOBBER)
1555 : {
1556 1384936 : rtx x = XEXP (PATTERN (insn), 0);
1557 1384936 : if (GET_CODE (x) == REG
1558 1371519 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1559 1417414 : && have_regs_of_mode[GET_MODE (x)])
1560 32477 : ira_init_register_move_cost_if_necessary (GET_MODE (x));
1561 1384936 : return insn;
1562 : }
1563 :
1564 139755027 : counted_mem = false;
1565 139755027 : set = single_set (insn);
1566 139755027 : extract_insn (insn);
1567 :
1568 : /* If this insn loads a parameter from its stack slot, then it
1569 : represents a savings, rather than a cost, if the parameter is
1570 : stored in memory. Record this fact.
1571 :
1572 : Similarly if we're loading other constants from memory (constant
1573 : pool, TOC references, small data areas, etc) and this is the only
1574 : assignment to the destination pseudo.
1575 :
1576 : Don't do this if SET_SRC (set) isn't a general operand, if it is
1577 : a memory requiring special instructions to load it, decreasing
1578 : mem_cost might result in it being loaded using the specialized
1579 : instruction into a register, then stored into stack and loaded
1580 : again from the stack. See PR52208.
1581 :
1582 : Don't do this if SET_SRC (set) has side effect. See PR56124. */
1583 132155879 : if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set))
1584 17307907 : && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX
1585 4889331 : && ((MEM_P (XEXP (note, 0))
1586 4444789 : && !side_effects_p (SET_SRC (set)))
1587 444542 : || (CONSTANT_P (XEXP (note, 0))
1588 444534 : && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)),
1589 : XEXP (note, 0))
1590 152846 : && REG_N_SETS (REGNO (SET_DEST (set))) == 1))
1591 4597635 : && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))
1592 : /* LRA does not use equiv with a symbol for PIC code. */
1593 144352617 : && (! ira_use_lra_p || ! pic_offset_table_rtx
1594 334174 : || ! contains_symbol_ref_p (XEXP (note, 0))))
1595 : {
1596 4540056 : enum reg_class cl = GENERAL_REGS;
1597 4540056 : rtx reg = SET_DEST (set);
1598 4540056 : int num = COST_INDEX (REGNO (reg));
1599 : /* Costs for NO_REGS are used in cost calculation on the
1600 : 1st pass when the preferred register classes are not
1601 : known yet. In this case we take the best scenario when
1602 : mode can't be put into GENERAL_REGS. */
1603 4540056 : if (!targetm.hard_regno_mode_ok (ira_class_hard_regs[cl][0],
1604 4540056 : GET_MODE (reg)))
1605 1260938 : cl = NO_REGS;
1606 :
1607 4540056 : COSTS (costs, num)->mem_cost
1608 4540056 : -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency;
1609 9080112 : record_address_regs (GET_MODE (SET_SRC (set)),
1610 9080112 : MEM_ADDR_SPACE (SET_SRC (set)),
1611 4540056 : XEXP (SET_SRC (set), 0), 0, MEM, SCRATCH,
1612 : frequency * 2);
1613 4540056 : counted_mem = true;
1614 : }
1615 :
1616 139755027 : record_operand_costs (insn, pref);
1617 :
1618 139755027 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1619 : {
1620 0 : const char *p;
1621 0 : fprintf (ira_dump_file, " Final costs after insn %u", INSN_UID (insn));
1622 0 : if (INSN_CODE (insn) >= 0
1623 0 : && (p = get_insn_name (INSN_CODE (insn))) != NULL)
1624 0 : fprintf (ira_dump_file, " {%s}", p);
1625 0 : fprintf (ira_dump_file, " (freq=%d)\n",
1626 0 : REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
1627 0 : dump_insn_slim (ira_dump_file, insn);
1628 : }
1629 :
1630 : /* Now add the cost for each operand to the total costs for its
1631 : allocno. */
1632 442404811 : for (i = 0; i < recog_data.n_operands; i++)
1633 : {
1634 302649784 : rtx op = recog_data.operand[i];
1635 :
1636 302649784 : if (GET_CODE (op) == SUBREG)
1637 33413 : op = SUBREG_REG (op);
1638 302649784 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1639 : {
1640 123081293 : int regno = REGNO (op);
1641 123081293 : struct costs *p = COSTS (costs, COST_INDEX (regno));
1642 123081293 : struct costs *q = op_costs[i];
1643 123081293 : int *p_costs = p->cost, *q_costs = q->cost;
1644 123081293 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1645 123081293 : int add_cost = 0;
1646 :
1647 : /* If the already accounted for the memory "cost" above, don't
1648 : do so again. */
1649 123081293 : if (!counted_mem)
1650 : {
1651 118541237 : add_cost = q->mem_cost;
1652 118541237 : if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost)
1653 0 : p->mem_cost = INT_MAX;
1654 : else
1655 118541237 : p->mem_cost += add_cost;
1656 : }
1657 123081293 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1658 : {
1659 0 : fprintf (ira_dump_file, " op %d(r=%u) MEM:%d(+%d)",
1660 : i, REGNO(op), p->mem_cost, add_cost);
1661 : }
1662 1827502200 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1663 : {
1664 1704420907 : add_cost = q_costs[k];
1665 1704420907 : if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
1666 0 : p_costs[k] = INT_MAX;
1667 : else
1668 1704420907 : p_costs[k] += add_cost;
1669 1704420907 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1670 : {
1671 0 : fprintf (ira_dump_file, " %s:%d(+%d)",
1672 0 : reg_class_names[cost_classes_ptr->classes[k]],
1673 0 : p_costs[k], add_cost);
1674 : }
1675 : }
1676 123081293 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1677 0 : fprintf (ira_dump_file, "\n");
1678 : }
1679 : }
1680 : return insn;
1681 : }
1682 :
1683 :
1684 :
1685 : /* Print allocnos costs to the dump file. */
1686 : static void
1687 127 : print_allocno_costs (void)
1688 : {
1689 127 : int k;
1690 127 : ira_allocno_t a;
1691 127 : ira_allocno_iterator ai;
1692 :
1693 127 : ira_assert (allocno_p);
1694 127 : fprintf (ira_dump_file, "\n");
1695 1341 : FOR_EACH_ALLOCNO (a, ai)
1696 : {
1697 1214 : int i, rclass;
1698 1214 : basic_block bb;
1699 1214 : int regno = ALLOCNO_REGNO (a);
1700 1214 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1701 1214 : enum reg_class *cost_classes = cost_classes_ptr->classes;
1702 :
1703 1214 : i = ALLOCNO_NUM (a);
1704 1214 : fprintf (ira_dump_file, " a%d(r%d,", i, regno);
1705 1214 : if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
1706 0 : fprintf (ira_dump_file, "b%d", bb->index);
1707 : else
1708 1214 : fprintf (ira_dump_file, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
1709 1214 : fprintf (ira_dump_file, ") costs:");
1710 19725 : for (k = 0; k < cost_classes_ptr->num; k++)
1711 : {
1712 17297 : rclass = cost_classes[k];
1713 17297 : fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass],
1714 17297 : COSTS (costs, i)->cost[k]);
1715 17297 : if (flag_ira_region == IRA_REGION_ALL
1716 17297 : || flag_ira_region == IRA_REGION_MIXED)
1717 13698 : fprintf (ira_dump_file, ",%d",
1718 13698 : COSTS (total_allocno_costs, i)->cost[k]);
1719 : }
1720 1214 : fprintf (ira_dump_file, " MEM:%i", COSTS (costs, i)->mem_cost);
1721 1214 : if (flag_ira_region == IRA_REGION_ALL
1722 1214 : || flag_ira_region == IRA_REGION_MIXED)
1723 1004 : fprintf (ira_dump_file, ",%d",
1724 1004 : COSTS (total_allocno_costs, i)->mem_cost);
1725 1214 : fprintf (ira_dump_file, "\n");
1726 : }
1727 127 : }
1728 :
1729 : /* Print pseudo costs to the dump file. */
1730 : static void
1731 16 : print_pseudo_costs (void)
1732 : {
1733 16 : int regno, k;
1734 16 : int rclass;
1735 16 : cost_classes_t cost_classes_ptr;
1736 16 : enum reg_class *cost_classes;
1737 :
1738 16 : ira_assert (! allocno_p);
1739 16 : fprintf (ira_dump_file, "\n");
1740 764 : for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1741 : {
1742 748 : if (REG_N_REFS (regno) <= 0)
1743 444 : continue;
1744 304 : cost_classes_ptr = regno_cost_classes[regno];
1745 304 : cost_classes = cost_classes_ptr->classes;
1746 304 : fprintf (ira_dump_file, " r%d costs:", regno);
1747 5904 : for (k = 0; k < cost_classes_ptr->num; k++)
1748 : {
1749 5296 : rclass = cost_classes[k];
1750 5296 : fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass],
1751 5296 : COSTS (costs, regno)->cost[k]);
1752 : }
1753 304 : fprintf (ira_dump_file, " MEM:%i\n", COSTS (costs, regno)->mem_cost);
1754 : }
1755 16 : }
1756 :
1757 : /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1758 : costs. */
1759 : static void
1760 25329423 : process_bb_for_costs (basic_block bb)
1761 : {
1762 25329423 : rtx_insn *insn;
1763 :
1764 25329423 : frequency = REG_FREQ_FROM_BB (bb);
1765 25329423 : if (frequency == 0)
1766 0 : frequency = 1;
1767 310319466 : FOR_BB_INSNS (bb, insn)
1768 284990043 : insn = scan_one_insn (insn);
1769 25329423 : }
1770 :
1771 : /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1772 : costs. */
1773 : static void
1774 28259155 : process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node)
1775 : {
1776 28259155 : basic_block bb;
1777 :
1778 28259155 : bb = loop_tree_node->bb;
1779 28259155 : if (bb != NULL)
1780 24640715 : process_bb_for_costs (bb);
1781 28259155 : }
1782 :
1783 : /* Return true if all autoinc rtx in X change only a register and memory is
1784 : valid. */
1785 : static bool
1786 53045504 : validate_autoinc_and_mem_addr_p (rtx x)
1787 : {
1788 53045504 : enum rtx_code code = GET_CODE (x);
1789 53045504 : if (GET_RTX_CLASS (code) == RTX_AUTOINC)
1790 382875 : return REG_P (XEXP (x, 0));
1791 52662629 : const char *fmt = GET_RTX_FORMAT (code);
1792 130702212 : for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1793 79370829 : if (fmt[i] == 'e')
1794 : {
1795 43264601 : if (!validate_autoinc_and_mem_addr_p (XEXP (x, i)))
1796 : return false;
1797 : }
1798 36106228 : else if (fmt[i] == 'E')
1799 : {
1800 2864455 : for (int j = 0; j < XVECLEN (x, i); j++)
1801 1933109 : if (!validate_autoinc_and_mem_addr_p (XVECEXP (x, i, j)))
1802 : return false;
1803 : }
1804 : /* Check memory after checking autoinc to guarantee that autoinc is already
1805 : valid for machine-dependent code checking memory address. */
1806 51331383 : return (!MEM_P (x)
1807 109687228 : || memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
1808 8149419 : MEM_ADDR_SPACE (x)));
1809 : }
1810 :
1811 : /* Check that reg REGNO in INSN can be changed by TO (which is an invariant
1812 : equiv when INVARIANT_P is true). Return true in case the result insn would
1813 : be valid one. */
1814 : static bool
1815 7847794 : equiv_can_be_consumed_p (int regno, rtx to, rtx_insn *insn, bool invariant_p)
1816 : {
1817 7847794 : validate_replace_src_group (regno_reg_rtx[regno], to, insn);
1818 : /* We can change register to equivalent memory in autoinc rtl. Some code
1819 : including verify_changes assumes that autoinc contains only a register.
1820 : So check this first. */
1821 7847794 : bool res = validate_autoinc_and_mem_addr_p (PATTERN (insn));
1822 7847794 : if (res)
1823 6722837 : res = verify_changes (0);
1824 7847794 : cancel_changes (0);
1825 7847794 : if (!res && invariant_p)
1826 : {
1827 : /* Here we use more expensive code for the invariant because we need to
1828 : simplify the result insn as the invariant can be arithmetic rtx
1829 : inserted into another arithmetic rtx, e.g. into memory address. */
1830 585262 : rtx pat = PATTERN (insn);
1831 585262 : int code = INSN_CODE (insn);
1832 585262 : PATTERN (insn) = copy_rtx (pat);
1833 1170524 : PATTERN (insn)
1834 585262 : = simplify_replace_rtx (PATTERN (insn), regno_reg_rtx[regno], to);
1835 585262 : res = !insn_invalid_p (insn, false);
1836 585262 : PATTERN (insn) = pat;
1837 585262 : INSN_CODE (insn) = code;
1838 : }
1839 7847794 : return res;
1840 : }
1841 :
1842 : /* Return true if X contains a pseudo with equivalence. In this case also
1843 : return the pseudo through parameter REG. If the pseudo is a part of subreg,
1844 : return the subreg through parameter SUBREG. */
1845 :
1846 : static bool
1847 273286302 : get_equiv_regno (rtx x, int ®no, rtx &subreg)
1848 : {
1849 273286302 : subreg = NULL_RTX;
1850 273286302 : if (GET_CODE (x) == SUBREG)
1851 : {
1852 2151471 : subreg = x;
1853 2151471 : x = SUBREG_REG (x);
1854 : }
1855 273286302 : if (REG_P (x)
1856 273286302 : && (ira_reg_equiv[REGNO (x)].memory != NULL
1857 81763406 : || ira_reg_equiv[REGNO (x)].invariant != NULL
1858 79412621 : || ira_reg_equiv[REGNO (x)].constant != NULL))
1859 : {
1860 10281886 : regno = REGNO (x);
1861 10281886 : return true;
1862 : }
1863 263004416 : RTX_CODE code = GET_CODE (x);
1864 263004416 : const char *fmt = GET_RTX_FORMAT (code);
1865 :
1866 614719283 : for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1867 366805079 : if (fmt[i] == 'e')
1868 : {
1869 202548125 : if (get_equiv_regno (XEXP (x, i), regno, subreg))
1870 : return true;
1871 : }
1872 164256954 : else if (fmt[i] == 'E')
1873 : {
1874 23545510 : for (int j = 0; j < XVECLEN (x, i); j++)
1875 16375356 : if (get_equiv_regno (XVECEXP (x, i, j), regno, subreg))
1876 : return true;
1877 : }
1878 : return false;
1879 : }
1880 :
1881 : /* A pass through the current function insns. Calculate costs of using
1882 : equivalences for pseudos and store them in regno_equiv_gains. */
1883 :
1884 : static void
1885 961509 : calculate_equiv_gains (void)
1886 : {
1887 961509 : basic_block bb;
1888 961509 : int regno, freq, cost;
1889 961509 : rtx subreg;
1890 961509 : rtx_insn *insn;
1891 961509 : machine_mode mode;
1892 961509 : enum reg_class rclass;
1893 961509 : bitmap_head equiv_pseudos;
1894 :
1895 961509 : ira_assert (allocno_p);
1896 961509 : bitmap_initialize (&equiv_pseudos, ®_obstack);
1897 47729718 : for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1898 46768209 : if (ira_reg_equiv[regno].init_insns != NULL
1899 4177185 : && (ira_reg_equiv[regno].memory != NULL
1900 1438848 : || ira_reg_equiv[regno].invariant != NULL
1901 631723 : || (ira_reg_equiv[regno].constant != NULL
1902 : /* Ignore complicated constants which probably will be placed
1903 : in memory: */
1904 631723 : && GET_CODE (ira_reg_equiv[regno].constant) != CONST_DOUBLE
1905 : && GET_CODE (ira_reg_equiv[regno].constant) != CONST_VECTOR
1906 : && GET_CODE (ira_reg_equiv[regno].constant) != LABEL_REF)))
1907 : {
1908 : rtx_insn_list *x;
1909 7514067 : for (x = ira_reg_equiv[regno].init_insns; x != NULL; x = x->next ())
1910 : {
1911 4010798 : insn = x->insn ();
1912 4010798 : rtx set = single_set (insn);
1913 :
1914 4010798 : if (set == NULL_RTX || SET_DEST (set) != regno_reg_rtx[regno])
1915 : break;
1916 3503269 : bb = BLOCK_FOR_INSN (insn);
1917 3503269 : ira_curr_regno_allocno_map
1918 3503269 : = ira_bb_nodes[bb->index].parent->regno_allocno_map;
1919 3503269 : mode = PSEUDO_REGNO_MODE (regno);
1920 3503269 : rclass = pref[COST_INDEX (regno)];
1921 3503269 : ira_init_register_move_cost_if_necessary (mode);
1922 3503269 : if (ira_reg_equiv[regno].memory != NULL)
1923 2230808 : cost = ira_memory_move_cost[mode][rclass][1];
1924 : else
1925 1272461 : cost = ira_register_move_cost[mode][rclass][rclass];
1926 3503269 : freq = REG_FREQ_FROM_BB (bb);
1927 3503269 : regno_equiv_gains[regno] += cost * freq;
1928 : }
1929 4010798 : if (x != NULL)
1930 : /* We found complicated equiv or reverse equiv mem=reg. Ignore
1931 : them. */
1932 507529 : regno_equiv_gains[regno] = 0;
1933 : else
1934 3503269 : bitmap_set_bit (&equiv_pseudos, regno);
1935 : }
1936 :
1937 11279761 : FOR_EACH_BB_FN (bb, cfun)
1938 : {
1939 10318252 : freq = REG_FREQ_FROM_BB (bb);
1940 10318252 : ira_curr_regno_allocno_map
1941 10318252 : = ira_bb_nodes[bb->index].parent->regno_allocno_map;
1942 132590386 : FOR_BB_INSNS (bb, insn)
1943 : {
1944 235889430 : if (!NONDEBUG_INSN_P (insn)
1945 54362821 : || !get_equiv_regno (PATTERN (insn), regno, subreg)
1946 132554020 : || !bitmap_bit_p (&equiv_pseudos, regno))
1947 113617296 : continue;
1948 :
1949 8654838 : if (ira_reg_equiv[regno].invariant != NULL)
1950 : {
1951 2350785 : rtx_insn_list *x = ira_reg_equiv[regno].init_insns;
1952 3894526 : for (; x != NULL; x = x->next ())
1953 2350785 : if (insn == x->insn ())
1954 : break;
1955 2350785 : if (x != NULL)
1956 807044 : continue; /* skip equiv init insn for invariant */
1957 : }
1958 :
1959 7847794 : rtx subst = ira_reg_equiv[regno].memory;
1960 :
1961 7847794 : if (subst == NULL)
1962 2577790 : subst = ira_reg_equiv[regno].constant;
1963 2577790 : if (subst == NULL)
1964 1543741 : subst = ira_reg_equiv[regno].invariant;
1965 1543741 : ira_assert (subst != NULL);
1966 7847794 : mode = PSEUDO_REGNO_MODE (regno);
1967 7847794 : ira_init_register_move_cost_if_necessary (mode);
1968 7847794 : bool consumed_p
1969 15695588 : = equiv_can_be_consumed_p (regno, subst, insn,
1970 7847794 : subst == ira_reg_equiv[regno].invariant);
1971 :
1972 7847794 : rclass = pref[COST_INDEX (regno)];
1973 7847794 : if (MEM_P (subst)
1974 : /* If it is a change of constant into double for example, the
1975 : result constant probably will be placed in memory. */
1976 2577790 : || (ira_reg_equiv[regno].invariant == NULL
1977 1034049 : && subreg != NULL_RTX
1978 1146 : && !INTEGRAL_MODE_P (GET_MODE (subreg))))
1979 7915969 : cost = ira_memory_move_cost[mode][rclass][1] + (consumed_p ? 0 : 1);
1980 2577729 : else if (consumed_p)
1981 1526794 : continue;
1982 : else
1983 1050935 : cost = ira_register_move_cost[mode][rclass][rclass];
1984 6321000 : regno_equiv_gains[regno] -= cost * freq;
1985 : }
1986 : }
1987 961509 : bitmap_clear (&equiv_pseudos);
1988 961509 : }
1989 :
1990 : /* Find costs of register classes and memory for allocnos or pseudos
1991 : and their best costs. Set up preferred, alternative and allocno
1992 : classes for pseudos. */
1993 : static void
1994 1504040 : find_costs_and_classes (void)
1995 : {
1996 1504040 : int i, k, start, max_cost_classes_num;
1997 1504040 : int pass;
1998 1504040 : basic_block bb;
1999 1504040 : enum reg_class *regno_best_class, new_class;
2000 :
2001 1504040 : init_recog ();
2002 1504040 : regno_best_class
2003 1504040 : = (enum reg_class *) ira_allocate (max_reg_num ()
2004 : * sizeof (enum reg_class));
2005 68224249 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2006 66720209 : regno_best_class[i] = NO_REGS;
2007 2978497 : if (!resize_reg_info () && allocno_p
2008 2978454 : && pseudo_classes_defined_p && flag_expensive_optimizations)
2009 : {
2010 48 : ira_allocno_t a;
2011 48 : ira_allocno_iterator ai;
2012 :
2013 48 : pref = pref_buffer;
2014 48 : max_cost_classes_num = 1;
2015 1637 : FOR_EACH_ALLOCNO (a, ai)
2016 : {
2017 1589 : pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
2018 1589 : setup_regno_cost_classes_by_aclass
2019 1589 : (ALLOCNO_REGNO (a), pref[ALLOCNO_NUM (a)]);
2020 1589 : max_cost_classes_num
2021 1589 : = MAX (max_cost_classes_num,
2022 : regno_cost_classes[ALLOCNO_REGNO (a)]->num);
2023 : }
2024 48 : start = 1;
2025 : }
2026 : else
2027 : {
2028 1503992 : pref = NULL;
2029 1503992 : max_cost_classes_num = ira_important_classes_num;
2030 68221491 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2031 66717499 : if (regno_reg_rtx[i] != NULL_RTX)
2032 66421123 : setup_regno_cost_classes_by_mode (i, PSEUDO_REGNO_MODE (i));
2033 : else
2034 296376 : setup_regno_cost_classes_by_aclass (i, ALL_REGS);
2035 : start = 0;
2036 : }
2037 1504040 : if (allocno_p)
2038 : /* Clear the flag for the next compiled function. */
2039 1474414 : pseudo_classes_defined_p = false;
2040 : /* Normally we scan the insns once and determine the best class to
2041 : use for each allocno. However, if -fexpensive-optimizations are
2042 : on, we do so twice, the second time using the tentative best
2043 : classes to guide the selection. */
2044 3999115 : for (pass = start; pass <= flag_expensive_optimizations; pass++)
2045 : {
2046 2495075 : if ((!allocno_p || internal_flag_ira_verbose > 0) && ira_dump_file)
2047 143 : fprintf (ira_dump_file,
2048 : "\nPass %i for finding pseudo/allocno costs\n\n", pass);
2049 :
2050 2495075 : if (pass != start)
2051 : {
2052 991035 : max_cost_classes_num = 1;
2053 49181575 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2054 : {
2055 48190540 : setup_regno_cost_classes_by_aclass (i, regno_best_class[i]);
2056 48190540 : max_cost_classes_num
2057 48190540 : = MAX (max_cost_classes_num, regno_cost_classes[i]->num);
2058 : }
2059 : }
2060 :
2061 2495075 : struct_costs_size
2062 2495075 : = sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1);
2063 : /* Zero out our accumulation of the cost of each class for each
2064 : allocno. */
2065 2495075 : memset (costs, 0, cost_elements_num * struct_costs_size);
2066 :
2067 2495075 : if (allocno_p)
2068 : {
2069 : /* Scan the instructions and record each time it would save code
2070 : to put a certain allocno in a certain class. */
2071 2435875 : ira_traverse_loop_tree (true, ira_loop_tree_root,
2072 : process_bb_node_for_costs, NULL);
2073 :
2074 2435875 : memcpy (total_allocno_costs, costs,
2075 2435875 : max_struct_costs_size * ira_allocnos_num);
2076 : }
2077 : else
2078 : {
2079 59200 : basic_block bb;
2080 :
2081 747908 : FOR_EACH_BB_FN (bb, cfun)
2082 688708 : process_bb_for_costs (bb);
2083 : }
2084 :
2085 2495075 : if (pass == 0)
2086 1503992 : pref = pref_buffer;
2087 :
2088 2495075 : if (ira_use_lra_p && allocno_p && pass == 1)
2089 : /* It is a pass through all insns. So do it once and only for RA (not
2090 : for insn scheduler) when we already found preferable pseudo register
2091 : classes on the previous pass. */
2092 961509 : calculate_equiv_gains ();
2093 :
2094 : /* Now for each allocno look at how desirable each class is and
2095 : find which class is preferred. */
2096 117405824 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2097 : {
2098 114910749 : ira_allocno_t a, parent_a;
2099 114910749 : int rclass, a_num, parent_a_num, add_cost;
2100 114910749 : ira_loop_tree_node_t parent;
2101 114910749 : int best_cost, allocno_cost;
2102 114910749 : enum reg_class best, alt_class;
2103 114910749 : cost_classes_t cost_classes_ptr = regno_cost_classes[i];
2104 114910749 : enum reg_class *cost_classes;
2105 114910749 : int *i_costs = temp_costs->cost;
2106 114910749 : int i_mem_cost;
2107 114910749 : int equiv_savings = regno_equiv_gains[i];
2108 :
2109 114910749 : if (! allocno_p)
2110 : {
2111 2851690 : if (regno_reg_rtx[i] == NULL_RTX)
2112 4608 : continue;
2113 2847082 : memcpy (temp_costs, COSTS (costs, i), struct_costs_size);
2114 2847082 : i_mem_cost = temp_costs->mem_cost;
2115 2847082 : cost_classes = cost_classes_ptr->classes;
2116 : }
2117 : else
2118 : {
2119 112059059 : if (ira_regno_allocno_map[i] == NULL)
2120 65687444 : continue;
2121 46371615 : memset (temp_costs, 0, struct_costs_size);
2122 46371615 : i_mem_cost = 0;
2123 46371615 : cost_classes = cost_classes_ptr->classes;
2124 : /* Find cost of all allocnos with the same regno. */
2125 46371615 : for (a = ira_regno_allocno_map[i];
2126 103532218 : a != NULL;
2127 57160603 : a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2128 : {
2129 57160603 : int *a_costs, *p_costs;
2130 :
2131 57160603 : a_num = ALLOCNO_NUM (a);
2132 57160603 : if ((flag_ira_region == IRA_REGION_ALL
2133 57160603 : || flag_ira_region == IRA_REGION_MIXED)
2134 44659827 : && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL
2135 17571519 : && (parent_a = parent->regno_allocno_map[i]) != NULL
2136 : /* There are no caps yet. */
2137 67949170 : && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
2138 10788567 : (a)->border_allocnos,
2139 : ALLOCNO_NUM (a)))
2140 : {
2141 : /* Propagate costs to upper levels in the region
2142 : tree. */
2143 10781737 : parent_a_num = ALLOCNO_NUM (parent_a);
2144 10781737 : a_costs = COSTS (total_allocno_costs, a_num)->cost;
2145 10781737 : p_costs = COSTS (total_allocno_costs, parent_a_num)->cost;
2146 156144578 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2147 : {
2148 145362841 : add_cost = a_costs[k];
2149 145362841 : if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
2150 0 : p_costs[k] = INT_MAX;
2151 : else
2152 145362841 : p_costs[k] += add_cost;
2153 : }
2154 10781737 : add_cost = COSTS (total_allocno_costs, a_num)->mem_cost;
2155 10781737 : if (add_cost > 0
2156 5158553 : && (INT_MAX - add_cost
2157 : < COSTS (total_allocno_costs,
2158 5158553 : parent_a_num)->mem_cost))
2159 0 : COSTS (total_allocno_costs, parent_a_num)->mem_cost
2160 0 : = INT_MAX;
2161 : else
2162 10781737 : COSTS (total_allocno_costs, parent_a_num)->mem_cost
2163 10781737 : += add_cost;
2164 :
2165 10781737 : if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2166 0 : COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0;
2167 : }
2168 57160603 : a_costs = COSTS (costs, a_num)->cost;
2169 848617593 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2170 : {
2171 791456990 : add_cost = a_costs[k];
2172 791456990 : if (add_cost > 0 && INT_MAX - add_cost < i_costs[k])
2173 0 : i_costs[k] = INT_MAX;
2174 : else
2175 791456990 : i_costs[k] += add_cost;
2176 : }
2177 57160603 : add_cost = COSTS (costs, a_num)->mem_cost;
2178 57160603 : if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost)
2179 : i_mem_cost = INT_MAX;
2180 : else
2181 57160603 : i_mem_cost += add_cost;
2182 : }
2183 : }
2184 49218697 : if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2185 : i_mem_cost = 0;
2186 49191493 : else if (ira_use_lra_p)
2187 : {
2188 49191493 : if (equiv_savings > 0)
2189 : {
2190 511447 : i_mem_cost = 0;
2191 511447 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
2192 0 : fprintf (ira_dump_file,
2193 : " Use MEM for r%d as the equiv savings is %d\n",
2194 : i, equiv_savings);
2195 : }
2196 : }
2197 0 : else if (equiv_savings < 0)
2198 0 : i_mem_cost = -equiv_savings;
2199 0 : else if (equiv_savings > 0)
2200 : {
2201 0 : i_mem_cost = 0;
2202 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2203 0 : i_costs[k] += equiv_savings;
2204 : }
2205 :
2206 49218697 : best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2207 49218697 : best = ALL_REGS;
2208 49218697 : alt_class = NO_REGS;
2209 : /* Find best common class for all allocnos with the same
2210 : regno. */
2211 743893908 : for (k = 0; k < cost_classes_ptr->num; k++)
2212 : {
2213 694675211 : rclass = cost_classes[k];
2214 694675211 : if (i_costs[k] < best_cost)
2215 : {
2216 : best_cost = i_costs[k];
2217 : best = (enum reg_class) rclass;
2218 : }
2219 634281781 : else if (i_costs[k] == best_cost)
2220 301515760 : best = ira_reg_class_subunion[best][rclass];
2221 694675211 : if (pass == flag_expensive_optimizations
2222 : /* We still prefer registers to memory even at this
2223 : stage if their costs are the same. We will make
2224 : a final decision during assigning hard registers
2225 : when we have all info including more accurate
2226 : costs which might be affected by assigning hard
2227 : registers to other pseudos because the pseudos
2228 : involved in moves can be coalesced. */
2229 398325894 : && i_costs[k] <= i_mem_cost
2230 275363781 : && (reg_class_size[reg_class_subunion[alt_class][rclass]]
2231 275363781 : > reg_class_size[alt_class]))
2232 694675211 : alt_class = reg_class_subunion[alt_class][rclass];
2233 : }
2234 49218697 : alt_class = ira_allocno_class_translate[alt_class];
2235 49218697 : if (best_cost > i_mem_cost
2236 49218697 : && ! non_spilled_static_chain_regno_p (i))
2237 749144 : regno_aclass[i] = NO_REGS;
2238 48469553 : else if (!optimize && !targetm.class_likely_spilled_p (best))
2239 : /* Registers in the alternative class are likely to need
2240 : longer or slower sequences than registers in the best class.
2241 : When optimizing we make some effort to use the best class
2242 : over the alternative class where possible, but at -O0 we
2243 : effectively give the alternative class equal weight.
2244 : We then run the risk of using slower alternative registers
2245 : when plenty of registers from the best class are still free.
2246 : This is especially true because live ranges tend to be very
2247 : short in -O0 code and so register pressure tends to be low.
2248 :
2249 : Avoid that by ignoring the alternative class if the best
2250 : class has plenty of registers.
2251 :
2252 : The union class arrays give important classes and only
2253 : part of it are allocno classes. So translate them into
2254 : allocno classes. */
2255 9522628 : regno_aclass[i] = ira_allocno_class_translate[best];
2256 : else
2257 : {
2258 : /* Make the common class the biggest class of best and
2259 : alt_class. Translate the common class into an
2260 : allocno class too. */
2261 38946925 : regno_aclass[i] = (ira_allocno_class_translate
2262 38946925 : [ira_reg_class_superunion[best][alt_class]]);
2263 38946925 : ira_assert (regno_aclass[i] != NO_REGS
2264 : && ira_reg_allocno_class_p[regno_aclass[i]]);
2265 : }
2266 49218697 : if (pic_offset_table_rtx != NULL
2267 49218697 : && i == (int) REGNO (pic_offset_table_rtx))
2268 : {
2269 : /* For some targets, integer pseudos can be assigned to fp
2270 : regs. As we don't want reload pic offset table pseudo, we
2271 : should avoid using non-integer regs. */
2272 82123 : regno_aclass[i]
2273 82123 : = ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS];
2274 82123 : alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS];
2275 : }
2276 98437394 : if ((new_class
2277 98437394 : = (reg_class) (targetm.ira_change_pseudo_allocno_class
2278 49218697 : (i, regno_aclass[i], best))) != regno_aclass[i])
2279 : {
2280 0 : regno_aclass[i] = new_class;
2281 0 : if (hard_reg_set_subset_p (reg_class_contents[new_class],
2282 0 : reg_class_contents[best]))
2283 0 : best = new_class;
2284 0 : if (hard_reg_set_subset_p (reg_class_contents[new_class],
2285 0 : reg_class_contents[alt_class]))
2286 0 : alt_class = new_class;
2287 : }
2288 49218697 : if (pass == flag_expensive_optimizations)
2289 : {
2290 30965801 : if (best_cost > i_mem_cost
2291 : /* Do not assign NO_REGS to static chain pointer
2292 : pseudo when non-local goto is used. */
2293 30965801 : && ! non_spilled_static_chain_regno_p (i))
2294 : best = alt_class = NO_REGS;
2295 30493530 : else if (best == alt_class)
2296 21483288 : alt_class = NO_REGS;
2297 30965801 : setup_reg_classes (i, best, alt_class, regno_aclass[i]);
2298 30965801 : if ((!allocno_p || internal_flag_ira_verbose > 2)
2299 30965801 : && ira_dump_file != NULL)
2300 969 : fprintf (ira_dump_file,
2301 : " r%d: preferred %s, alternative %s, allocno %s\n",
2302 969 : i, reg_class_names[best], reg_class_names[alt_class],
2303 969 : reg_class_names[regno_aclass[i]]);
2304 : }
2305 49218697 : regno_best_class[i] = best;
2306 49218697 : if (! allocno_p)
2307 : {
2308 5694164 : pref[i] = (best_cost > i_mem_cost
2309 2797 : && ! non_spilled_static_chain_regno_p (i)
2310 2847082 : ? NO_REGS : best);
2311 2847082 : continue;
2312 : }
2313 46371615 : for (a = ira_regno_allocno_map[i];
2314 103532218 : a != NULL;
2315 57160603 : a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2316 : {
2317 57160603 : enum reg_class aclass = regno_aclass[i];
2318 57160603 : int a_num = ALLOCNO_NUM (a);
2319 57160603 : int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost;
2320 57160603 : int *a_costs = COSTS (costs, a_num)->cost;
2321 :
2322 57160603 : if (aclass == NO_REGS)
2323 : best = NO_REGS;
2324 : else
2325 : {
2326 : /* Finding best class which is subset of the common
2327 : class. */
2328 : best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2329 : allocno_cost = best_cost;
2330 : best = ALL_REGS;
2331 835170903 : for (k = 0; k < cost_classes_ptr->num; k++)
2332 : {
2333 778980072 : rclass = cost_classes[k];
2334 778980072 : if (! ira_class_subset_p[rclass][aclass])
2335 373448960 : continue;
2336 405531112 : if (total_a_costs[k] < best_cost)
2337 : {
2338 60875192 : best_cost = total_a_costs[k];
2339 60875192 : allocno_cost = a_costs[k];
2340 60875192 : best = (enum reg_class) rclass;
2341 : }
2342 344655920 : else if (total_a_costs[k] == best_cost)
2343 : {
2344 282777140 : best = ira_reg_class_subunion[best][rclass];
2345 282777140 : allocno_cost = MAX (allocno_cost, a_costs[k]);
2346 : }
2347 : }
2348 56190831 : ALLOCNO_CLASS_COST (a) = allocno_cost;
2349 : }
2350 57160603 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL
2351 1214 : && (pass == 0 || pref[a_num] != best))
2352 : {
2353 777 : fprintf (ira_dump_file, " a%d (r%d,", a_num, i);
2354 777 : if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
2355 0 : fprintf (ira_dump_file, "b%d", bb->index);
2356 : else
2357 777 : fprintf (ira_dump_file, "l%d",
2358 : ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
2359 777 : fprintf (ira_dump_file, ") best %s, allocno %s\n",
2360 777 : reg_class_names[best],
2361 777 : reg_class_names[aclass]);
2362 : }
2363 57160603 : pref[a_num] = best;
2364 57160603 : if (pass == flag_expensive_optimizations && best != aclass
2365 7461361 : && ira_class_hard_regs_num[best] > 0
2366 7461361 : && (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)]
2367 : >= ira_class_hard_regs_num[best]))
2368 : {
2369 6746177 : int ind = cost_classes_ptr->index[aclass];
2370 :
2371 6746177 : ira_assert (ind >= 0);
2372 6746177 : ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a));
2373 6746177 : ira_add_allocno_pref (a, ira_class_hard_regs[best][0],
2374 6746177 : (a_costs[ind] - ALLOCNO_CLASS_COST (a))
2375 : / (ira_register_move_cost
2376 6746177 : [ALLOCNO_MODE (a)][best][aclass]));
2377 133925528 : for (k = 0; k < cost_classes_ptr->num; k++)
2378 120433174 : if (ira_class_subset_p[cost_classes[k]][best])
2379 6746177 : a_costs[k] = a_costs[ind];
2380 : }
2381 : }
2382 : }
2383 :
2384 2495075 : if (internal_flag_ira_verbose > 4 && ira_dump_file)
2385 : {
2386 143 : if (allocno_p)
2387 127 : print_allocno_costs ();
2388 : else
2389 16 : print_pseudo_costs ();
2390 143 : fprintf (ira_dump_file,"\n");
2391 : }
2392 : }
2393 1504040 : ira_free (regno_best_class);
2394 1504040 : }
2395 :
2396 :
2397 :
2398 : /* Process moves involving hard regs to modify allocno hard register
2399 : costs. We can do this only after determining allocno class. If a
2400 : hard register forms a register class, then moves with the hard
2401 : register are already taken into account in class costs for the
2402 : allocno. */
2403 : static void
2404 12560608 : process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node)
2405 : {
2406 12560608 : int i, freq, src_regno, dst_regno, hard_regno, a_regno;
2407 12560608 : bool to_p;
2408 12560608 : ira_allocno_t a, curr_a;
2409 12560608 : ira_loop_tree_node_t curr_loop_tree_node;
2410 12560608 : enum reg_class rclass;
2411 12560608 : basic_block bb;
2412 12560608 : rtx_insn *insn;
2413 12560608 : rtx set, src, dst;
2414 :
2415 12560608 : bb = loop_tree_node->bb;
2416 12560608 : if (bb == NULL)
2417 : return;
2418 10905814 : freq = REG_FREQ_FROM_BB (bb);
2419 8522594 : if (freq == 0)
2420 2009604 : freq = 1;
2421 138285942 : FOR_BB_INSNS (bb, insn)
2422 : {
2423 127380128 : if (!NONDEBUG_INSN_P (insn))
2424 69241542 : continue;
2425 58138586 : set = single_set (insn);
2426 58138586 : if (set == NULL_RTX)
2427 3840596 : continue;
2428 54297990 : dst = SET_DEST (set);
2429 54297990 : src = SET_SRC (set);
2430 54297990 : if (! REG_P (dst) || ! REG_P (src))
2431 45253546 : continue;
2432 9044444 : dst_regno = REGNO (dst);
2433 9044444 : src_regno = REGNO (src);
2434 9044444 : if (dst_regno >= FIRST_PSEUDO_REGISTER
2435 9044444 : && src_regno < FIRST_PSEUDO_REGISTER)
2436 : {
2437 2975887 : hard_regno = src_regno;
2438 2975887 : a = ira_curr_regno_allocno_map[dst_regno];
2439 2975887 : to_p = true;
2440 : }
2441 7441291 : else if (src_regno >= FIRST_PSEUDO_REGISTER
2442 6068557 : && dst_regno < FIRST_PSEUDO_REGISTER)
2443 : {
2444 4695823 : hard_regno = dst_regno;
2445 4695823 : a = ira_curr_regno_allocno_map[src_regno];
2446 4695823 : to_p = false;
2447 : }
2448 : else
2449 1372734 : continue;
2450 14871229 : if (reg_class_size[(int) REGNO_REG_CLASS (hard_regno)]
2451 : == (ira_reg_class_max_nregs
2452 7671710 : [REGNO_REG_CLASS (hard_regno)][(int) ALLOCNO_MODE(a)]))
2453 : /* If the class can provide only one hard reg to the allocno,
2454 : we processed the insn record_operand_costs already and we
2455 : actually updated the hard reg cost there. */
2456 7199519 : continue;
2457 472191 : rclass = ALLOCNO_CLASS (a);
2458 472191 : if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno))
2459 22372 : continue;
2460 449819 : i = ira_class_hard_reg_index[rclass][hard_regno];
2461 449819 : if (i < 0)
2462 6878 : continue;
2463 442941 : a_regno = ALLOCNO_REGNO (a);
2464 442941 : for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a);
2465 975125 : curr_loop_tree_node != NULL;
2466 532184 : curr_loop_tree_node = curr_loop_tree_node->parent)
2467 532184 : if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL)
2468 461739 : ira_add_allocno_pref (curr_a, hard_regno, freq);
2469 442941 : {
2470 442941 : int cost;
2471 442941 : enum reg_class hard_reg_class;
2472 442941 : machine_mode mode;
2473 :
2474 442941 : mode = ALLOCNO_MODE (a);
2475 442941 : hard_reg_class = REGNO_REG_CLASS (hard_regno);
2476 442941 : ira_init_register_move_cost_if_necessary (mode);
2477 442941 : cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass]
2478 245409 : : ira_register_move_cost[mode][rclass][hard_reg_class]) * freq;
2479 442941 : ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass,
2480 : ALLOCNO_CLASS_COST (a));
2481 442941 : ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a),
2482 : rclass, 0);
2483 442941 : ALLOCNO_HARD_REG_COSTS (a)[i] -= cost;
2484 442941 : ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost;
2485 442941 : ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a),
2486 : ALLOCNO_HARD_REG_COSTS (a)[i]);
2487 : }
2488 : }
2489 : }
2490 :
2491 : /* After we find hard register and memory costs for allocnos, define
2492 : its class and modify hard register cost because insns moving
2493 : allocno to/from hard registers. */
2494 : static void
2495 1474414 : setup_allocno_class_and_costs (void)
2496 : {
2497 1474414 : int i, j, n, regno, hard_regno, num;
2498 1474414 : int *reg_costs;
2499 1474414 : enum reg_class aclass, rclass;
2500 1474414 : ira_allocno_t a;
2501 1474414 : ira_allocno_iterator ai;
2502 1474414 : cost_classes_t cost_classes_ptr;
2503 :
2504 1474414 : ira_assert (allocno_p);
2505 36605892 : FOR_EACH_ALLOCNO (a, ai)
2506 : {
2507 35131478 : i = ALLOCNO_NUM (a);
2508 35131478 : regno = ALLOCNO_REGNO (a);
2509 35131478 : aclass = regno_aclass[regno];
2510 35131478 : cost_classes_ptr = regno_cost_classes[regno];
2511 35131478 : ira_assert (pref[i] == NO_REGS || aclass != NO_REGS);
2512 35131478 : ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost;
2513 35131478 : ira_set_allocno_class (a, aclass);
2514 35131478 : if (aclass == NO_REGS)
2515 676733 : continue;
2516 34454745 : if (optimize && ALLOCNO_CLASS (a) != pref[i])
2517 : {
2518 5561075 : n = ira_class_hard_regs_num[aclass];
2519 5561075 : ALLOCNO_HARD_REG_COSTS (a)
2520 5561075 : = reg_costs = ira_allocate_cost_vector (aclass);
2521 99446950 : for (j = n - 1; j >= 0; j--)
2522 : {
2523 93885875 : hard_regno = ira_class_hard_regs[aclass][j];
2524 93885875 : if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], hard_regno))
2525 15182614 : reg_costs[j] = ALLOCNO_CLASS_COST (a);
2526 : else
2527 : {
2528 78703261 : rclass = REGNO_REG_CLASS (hard_regno);
2529 78703261 : num = cost_classes_ptr->index[rclass];
2530 78703261 : if (num < 0)
2531 : {
2532 278417 : num = cost_classes_ptr->hard_regno_index[hard_regno];
2533 278417 : ira_assert (num >= 0);
2534 : }
2535 78703261 : reg_costs[j] = COSTS (costs, i)->cost[num];
2536 : }
2537 : }
2538 : }
2539 : }
2540 1474414 : if (optimize)
2541 1041492 : ira_traverse_loop_tree (true, ira_loop_tree_root,
2542 : process_bb_node_for_hard_reg_moves, NULL);
2543 1474414 : }
2544 :
2545 :
2546 :
2547 : /* Function called once during compiler work. */
2548 : void
2549 210981 : ira_init_costs_once (void)
2550 : {
2551 210981 : int i;
2552 :
2553 210981 : init_cost = NULL;
2554 6540411 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2555 : {
2556 6329430 : op_costs[i] = NULL;
2557 6329430 : this_op_costs[i] = NULL;
2558 : }
2559 210981 : temp_costs = NULL;
2560 210981 : }
2561 :
2562 : /* Free allocated temporary cost vectors. */
2563 : void
2564 792858 : target_ira_int::free_ira_costs ()
2565 : {
2566 792858 : int i;
2567 :
2568 792858 : free (x_init_cost);
2569 792858 : x_init_cost = NULL;
2570 24578598 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2571 : {
2572 23785740 : free (x_op_costs[i]);
2573 23785740 : free (x_this_op_costs[i]);
2574 23785740 : x_op_costs[i] = x_this_op_costs[i] = NULL;
2575 : }
2576 792858 : free (x_temp_costs);
2577 792858 : x_temp_costs = NULL;
2578 792858 : }
2579 :
2580 : /* This is called each time register related information is
2581 : changed. */
2582 : void
2583 216330 : ira_init_costs (void)
2584 : {
2585 216330 : int i;
2586 :
2587 216330 : this_target_ira_int->free_ira_costs ();
2588 216330 : max_struct_costs_size
2589 216330 : = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1);
2590 : /* Don't use ira_allocate because vectors live through several IRA
2591 : calls. */
2592 216330 : init_cost = (struct costs *) xmalloc (max_struct_costs_size);
2593 216330 : init_cost->mem_cost = 1000000;
2594 6924944 : for (i = 0; i < ira_important_classes_num; i++)
2595 6708614 : init_cost->cost[i] = 1000000;
2596 6706230 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2597 : {
2598 6489900 : op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2599 6489900 : this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2600 : }
2601 216330 : temp_costs = (struct costs *) xmalloc (max_struct_costs_size);
2602 216330 : }
2603 :
2604 :
2605 :
2606 : /* Common initialization function for ira_costs and
2607 : ira_set_pseudo_classes. */
2608 : static void
2609 1504040 : init_costs (void)
2610 : {
2611 1504040 : init_subregs_of_mode ();
2612 3008080 : costs = (struct costs *) ira_allocate (max_struct_costs_size
2613 1504040 : * cost_elements_num);
2614 3008080 : pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2615 1504040 : * cost_elements_num);
2616 4512120 : regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2617 1504040 : * max_reg_num ());
2618 1504040 : regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ());
2619 1504040 : memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ());
2620 1504040 : }
2621 :
2622 : /* Common finalization function for ira_costs and
2623 : ira_set_pseudo_classes. */
2624 : static void
2625 1504040 : finish_costs (void)
2626 : {
2627 1504040 : finish_subregs_of_mode ();
2628 1504040 : ira_free (regno_equiv_gains);
2629 1504040 : ira_free (regno_aclass);
2630 1504040 : ira_free (pref_buffer);
2631 1504040 : ira_free (costs);
2632 1504040 : }
2633 :
2634 : /* Entry function which defines register class, memory and hard
2635 : register costs for each allocno. */
2636 : void
2637 1474414 : ira_costs (void)
2638 : {
2639 1474414 : allocno_p = true;
2640 1474414 : cost_elements_num = ira_allocnos_num;
2641 1474414 : init_costs ();
2642 2948828 : total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size
2643 1474414 : * ira_allocnos_num);
2644 1474414 : initiate_regno_cost_classes ();
2645 1474414 : if (!ira_use_lra_p)
2646 : /* Process equivs in reload to update costs through hook
2647 : ira_adjust_equiv_reg_cost. */
2648 0 : calculate_elim_costs_all_insns ();
2649 1474414 : find_costs_and_classes ();
2650 1474414 : setup_allocno_class_and_costs ();
2651 1474414 : finish_regno_cost_classes ();
2652 1474414 : finish_costs ();
2653 1474414 : ira_free (total_allocno_costs);
2654 1474414 : }
2655 :
2656 : /* Entry function which defines classes for pseudos.
2657 : Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2658 : void
2659 29626 : ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file)
2660 : {
2661 29626 : FILE *saved_file = ira_dump_file;
2662 29626 : allocno_p = false;
2663 29626 : internal_flag_ira_verbose = flag_ira_verbose;
2664 29626 : ira_dump_file = dump_file;
2665 29626 : cost_elements_num = max_reg_num ();
2666 29626 : init_costs ();
2667 29626 : initiate_regno_cost_classes ();
2668 29626 : find_costs_and_classes ();
2669 29626 : finish_regno_cost_classes ();
2670 29626 : if (define_pseudo_classes)
2671 101 : pseudo_classes_defined_p = true;
2672 :
2673 29626 : finish_costs ();
2674 29626 : ira_dump_file = saved_file;
2675 29626 : }
2676 :
2677 :
2678 :
2679 : /* Change hard register costs for allocnos which lives through
2680 : function calls. This is called only when we found all intersected
2681 : calls during building allocno live ranges. */
2682 : void
2683 1474414 : ira_tune_allocno_costs (void)
2684 : {
2685 1474414 : int j, n, regno;
2686 1474414 : int cost, min_cost, *reg_costs;
2687 1474414 : enum reg_class aclass;
2688 1474414 : machine_mode mode;
2689 1474414 : ira_allocno_t a;
2690 1474414 : ira_allocno_iterator ai;
2691 1474414 : ira_allocno_object_iterator oi;
2692 1474414 : ira_object_t obj;
2693 1474414 : bool skip_p;
2694 :
2695 37800071 : FOR_EACH_ALLOCNO (a, ai)
2696 : {
2697 36325657 : aclass = ALLOCNO_CLASS (a);
2698 36325657 : if (aclass == NO_REGS)
2699 643907 : continue;
2700 35681750 : mode = ALLOCNO_MODE (a);
2701 35681750 : n = ira_class_hard_regs_num[aclass];
2702 35681750 : min_cost = INT_MAX;
2703 35681750 : if (ALLOCNO_CALLS_CROSSED_NUM (a)
2704 35681750 : != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a))
2705 : {
2706 3563067 : ira_allocate_and_set_costs
2707 3563067 : (&ALLOCNO_HARD_REG_COSTS (a), aclass,
2708 : ALLOCNO_CLASS_COST (a));
2709 3563067 : reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2710 51665259 : for (j = n - 1; j >= 0; j--)
2711 : {
2712 48102192 : regno = ira_class_hard_regs[aclass][j];
2713 48102192 : skip_p = false;
2714 86513057 : FOR_EACH_ALLOCNO_OBJECT (a, obj, oi)
2715 : {
2716 49495473 : if (ira_hard_reg_set_intersection_p (regno, mode,
2717 : OBJECT_CONFLICT_HARD_REGS
2718 : (obj)))
2719 : {
2720 : skip_p = true;
2721 : break;
2722 : }
2723 : }
2724 48102192 : if (skip_p)
2725 11084608 : continue;
2726 37017584 : cost = 0;
2727 37017584 : if (ira_need_caller_save_p (a, regno))
2728 19061763 : cost += ira_caller_save_cost (a);
2729 : #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2730 : {
2731 : auto rclass = REGNO_REG_CLASS (regno);
2732 : cost += ((ira_memory_move_cost[mode][rclass][0]
2733 : + ira_memory_move_cost[mode][rclass][1])
2734 : * ALLOCNO_FREQ (a)
2735 : * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2);
2736 : }
2737 : #endif
2738 37017584 : if (INT_MAX - cost < reg_costs[j])
2739 0 : reg_costs[j] = INT_MAX;
2740 : else
2741 37017584 : reg_costs[j] += cost;
2742 37017584 : if (min_cost > reg_costs[j])
2743 48102192 : min_cost = reg_costs[j];
2744 : }
2745 : }
2746 3563067 : if (min_cost != INT_MAX)
2747 3547251 : ALLOCNO_CLASS_COST (a) = min_cost;
2748 :
2749 : /* Some targets allow pseudos to be allocated to unaligned sequences
2750 : of hard registers. However, selecting an unaligned sequence can
2751 : unnecessarily restrict later allocations. So increase the cost of
2752 : unaligned hard regs to encourage the use of aligned hard regs. */
2753 35681750 : {
2754 35681750 : const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)];
2755 :
2756 35681750 : if (nregs > 1)
2757 : {
2758 1308275 : ira_allocate_and_set_costs
2759 1308275 : (&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a));
2760 1308275 : reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2761 29341803 : for (j = n - 1; j >= 0; j--)
2762 : {
2763 28033528 : regno = ira_non_ordered_class_hard_regs[aclass][j];
2764 28033528 : if ((regno % nregs) != 0)
2765 : {
2766 13779484 : int index = ira_class_hard_reg_index[aclass][regno];
2767 13779484 : ira_assert (index != -1);
2768 13779484 : reg_costs[index] += ALLOCNO_FREQ (a);
2769 : }
2770 : }
2771 : }
2772 : }
2773 : }
2774 1474414 : }
2775 :
2776 : /* A hook from the reload pass. Add COST to the estimated gain for eliminating
2777 : REGNO with its equivalence. If COST is zero, record that no such
2778 : elimination is possible. */
2779 :
2780 : void
2781 0 : ira_adjust_equiv_reg_cost (unsigned regno, int cost)
2782 : {
2783 0 : ira_assert (!ira_use_lra_p);
2784 0 : if (cost == 0)
2785 0 : regno_equiv_gains[regno] = 0;
2786 : else
2787 0 : regno_equiv_gains[regno] += cost;
2788 0 : }
2789 :
2790 : void
2791 258746 : ira_costs_cc_finalize (void)
2792 : {
2793 258746 : this_target_ira_int->free_ira_costs ();
2794 258746 : }
|
