Line data Source code
1 : /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "tree.h"
28 : #include "predict.h"
29 : #include "memmodel.h"
30 : #include "tm_p.h"
31 : #include "insn-config.h"
32 : #include "regs.h"
33 : #include "regset.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "addresses.h"
37 : #include "reload.h"
38 : #include "print-rtl.h"
39 :
40 : /* The flags is set up every time when we calculate pseudo register
41 : classes through function ira_set_pseudo_classes. */
42 : static bool pseudo_classes_defined_p = false;
43 :
44 : /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
45 : static bool allocno_p;
46 :
47 : /* Number of elements in array `costs'. */
48 : static int cost_elements_num;
49 :
50 : /* The `costs' struct records the cost of using hard registers of each
51 : class considered for the calculation and of using memory for each
52 : allocno or pseudo. */
53 : struct costs
54 : {
55 : int mem_cost;
56 : /* Costs for register classes start here. We process only some
57 : allocno classes. */
58 : int cost[1];
59 : };
60 :
61 : #define max_struct_costs_size \
62 : (this_target_ira_int->x_max_struct_costs_size)
63 : #define init_cost \
64 : (this_target_ira_int->x_init_cost)
65 : #define temp_costs \
66 : (this_target_ira_int->x_temp_costs)
67 : #define op_costs \
68 : (this_target_ira_int->x_op_costs)
69 : #define this_op_costs \
70 : (this_target_ira_int->x_this_op_costs)
71 :
72 : /* Costs of each class for each allocno or pseudo. */
73 : static struct costs *costs;
74 :
75 : /* Accumulated costs of each class for each allocno. */
76 : static struct costs *total_allocno_costs;
77 :
78 : /* It is the current size of struct costs. */
79 : static size_t struct_costs_size;
80 :
81 : /* Return pointer to structure containing costs of allocno or pseudo
82 : with given NUM in array ARR. */
83 : #define COSTS(arr, num) \
84 : ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
85 :
86 : /* Return index in COSTS when processing reg with REGNO. */
87 : #define COST_INDEX(regno) (allocno_p \
88 : ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
89 : : (int) regno)
90 :
91 : /* Record register class preferences of each allocno or pseudo. Null
92 : value means no preferences. It happens on the 1st iteration of the
93 : cost calculation. */
94 : static enum reg_class *pref;
95 :
96 : /* Allocated buffers for pref. */
97 : static enum reg_class *pref_buffer;
98 :
99 : /* Record allocno class of each allocno with the same regno. */
100 : static enum reg_class *regno_aclass;
101 :
102 : /* Record cost gains for not allocating a register with an invariant
103 : equivalence. */
104 : static int *regno_equiv_gains;
105 :
106 : /* Execution frequency of the current insn. */
107 : static int frequency;
108 :
109 :
110 :
111 : /* Info about reg classes whose costs are calculated for a pseudo. */
112 : struct cost_classes
113 : {
114 : /* Number of the cost classes in the subsequent array. */
115 : int num;
116 : /* Container of the cost classes. */
117 : enum reg_class classes[N_REG_CLASSES];
118 : /* Map reg class -> index of the reg class in the previous array.
119 : -1 if it is not a cost class. */
120 : int index[N_REG_CLASSES];
121 : /* Map hard regno index of first class in array CLASSES containing
122 : the hard regno, -1 otherwise. */
123 : int hard_regno_index[FIRST_PSEUDO_REGISTER];
124 : };
125 :
126 : /* Types of pointers to the structure above. */
127 : typedef struct cost_classes *cost_classes_t;
128 : typedef const struct cost_classes *const_cost_classes_t;
129 :
130 : /* Info about cost classes for each pseudo. */
131 : static cost_classes_t *regno_cost_classes;
132 :
133 : /* Helper for cost_classes hashing. */
134 :
135 : struct cost_classes_hasher : pointer_hash <cost_classes>
136 : {
137 : static inline hashval_t hash (const cost_classes *);
138 : static inline bool equal (const cost_classes *, const cost_classes *);
139 : static inline void remove (cost_classes *);
140 : };
141 :
142 : /* Returns hash value for cost classes info HV. */
143 : inline hashval_t
144 108559768 : cost_classes_hasher::hash (const cost_classes *hv)
145 : {
146 108559768 : return iterative_hash (&hv->classes, sizeof (enum reg_class) * hv->num, 0);
147 : }
148 :
149 : /* Compares cost classes info HV1 and HV2. */
150 : inline bool
151 100583991 : cost_classes_hasher::equal (const cost_classes *hv1, const cost_classes *hv2)
152 : {
153 100583991 : return (hv1->num == hv2->num
154 100583991 : && memcmp (hv1->classes, hv2->classes,
155 51814754 : sizeof (enum reg_class) * hv1->num) == 0);
156 : }
157 :
158 : /* Delete cost classes info V from the hash table. */
159 : inline void
160 5988832 : cost_classes_hasher::remove (cost_classes *v)
161 : {
162 5988832 : ira_free (v);
163 5988832 : }
164 :
165 : /* Hash table of unique cost classes. */
166 : static hash_table<cost_classes_hasher> *cost_classes_htab;
167 :
168 : /* Map allocno class -> cost classes for pseudo of given allocno
169 : class. */
170 : static cost_classes_t cost_classes_aclass_cache[N_REG_CLASSES];
171 :
172 : /* Map mode -> cost classes for pseudo of give mode. */
173 : static cost_classes_t cost_classes_mode_cache[MAX_MACHINE_MODE];
174 :
175 : /* Cost classes that include all classes in ira_important_classes. */
176 : static cost_classes all_cost_classes;
177 :
178 : /* Use the array of classes in CLASSES_PTR to fill out the rest of
179 : the structure. */
180 : static void
181 7489652 : complete_cost_classes (cost_classes_t classes_ptr)
182 : {
183 262137820 : for (int i = 0; i < N_REG_CLASSES; i++)
184 254648168 : classes_ptr->index[i] = -1;
185 696537636 : for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++)
186 689047984 : classes_ptr->hard_regno_index[i] = -1;
187 155135263 : for (int i = 0; i < classes_ptr->num; i++)
188 : {
189 147645611 : enum reg_class cl = classes_ptr->classes[i];
190 147645611 : classes_ptr->index[cl] = i;
191 1708700737 : for (int j = ira_class_hard_regs_num[cl] - 1; j >= 0; j--)
192 : {
193 1561055126 : unsigned int hard_regno = ira_class_hard_regs[cl][j];
194 1561055126 : if (classes_ptr->hard_regno_index[hard_regno] < 0)
195 297115878 : classes_ptr->hard_regno_index[hard_regno] = i;
196 : }
197 : }
198 7489652 : }
199 :
200 : /* Initialize info about the cost classes for each pseudo. */
201 : static void
202 1500820 : initiate_regno_cost_classes (void)
203 : {
204 1500820 : int size = sizeof (cost_classes_t) * max_reg_num ();
205 :
206 1500820 : regno_cost_classes = (cost_classes_t *) ira_allocate (size);
207 1500820 : memset (regno_cost_classes, 0, size);
208 1500820 : memset (cost_classes_aclass_cache, 0,
209 : sizeof (cost_classes_t) * N_REG_CLASSES);
210 1500820 : memset (cost_classes_mode_cache, 0,
211 : sizeof (cost_classes_t) * MAX_MACHINE_MODE);
212 1500820 : cost_classes_htab = new hash_table<cost_classes_hasher> (200);
213 1500820 : all_cost_classes.num = ira_important_classes_num;
214 48131181 : for (int i = 0; i < ira_important_classes_num; i++)
215 46630361 : all_cost_classes.classes[i] = ira_important_classes[i];
216 1500820 : complete_cost_classes (&all_cost_classes);
217 1500820 : }
218 :
219 : /* Create new cost classes from cost classes FROM and set up members
220 : index and hard_regno_index. Return the new classes. The function
221 : implements some common code of two functions
222 : setup_regno_cost_classes_by_aclass and
223 : setup_regno_cost_classes_by_mode. */
224 : static cost_classes_t
225 5988832 : setup_cost_classes (cost_classes_t from)
226 : {
227 5988832 : cost_classes_t classes_ptr;
228 :
229 5988832 : classes_ptr = (cost_classes_t) ira_allocate (sizeof (struct cost_classes));
230 5988832 : classes_ptr->num = from->num;
231 107004082 : for (int i = 0; i < from->num; i++)
232 101015250 : classes_ptr->classes[i] = from->classes[i];
233 5988832 : complete_cost_classes (classes_ptr);
234 5988832 : return classes_ptr;
235 : }
236 :
237 : /* Return a version of FULL that only considers registers in REGS that are
238 : valid for mode MODE. Both FULL and the returned class are globally
239 : allocated. */
240 : static cost_classes_t
241 53721260 : restrict_cost_classes (cost_classes_t full, machine_mode mode,
242 : const_hard_reg_set regs)
243 : {
244 53721260 : static struct cost_classes narrow;
245 53721260 : int map[N_REG_CLASSES];
246 53721260 : narrow.num = 0;
247 1564148920 : for (int i = 0; i < full->num; i++)
248 : {
249 : /* Assume that we'll drop the class. */
250 1510427660 : map[i] = -1;
251 :
252 : /* Ignore classes that are too small for the mode. */
253 1510427660 : enum reg_class cl = full->classes[i];
254 1510427660 : if (!contains_reg_of_mode[cl][mode])
255 302856011 : continue;
256 :
257 : /* Calculate the set of registers in CL that belong to REGS and
258 : are valid for MODE. */
259 1226311800 : HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs;
260 2452623600 : valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode]
261 1226311800 : | ira_no_alloc_regs);
262 2452623600 : if (hard_reg_set_empty_p (valid_for_cl))
263 18740151 : continue;
264 :
265 : /* Don't use this class if the set of valid registers is a subset
266 : of an existing class. For example, suppose we have two classes
267 : GR_REGS and FR_REGS and a union class GR_AND_FR_REGS. Suppose
268 : that the mode changes allowed by FR_REGS are not as general as
269 : the mode changes allowed by GR_REGS.
270 :
271 : In this situation, the mode changes for GR_AND_FR_REGS could
272 : either be seen as the union or the intersection of the mode
273 : changes allowed by the two subclasses. The justification for
274 : the union-based definition would be that, if you want a mode
275 : change that's only allowed by GR_REGS, you can pick a register
276 : from the GR_REGS subclass. The justification for the
277 : intersection-based definition would be that every register
278 : from the class would allow the mode change.
279 :
280 : However, if we have a register that needs to be in GR_REGS,
281 : using GR_AND_FR_REGS with the intersection-based definition
282 : would be too pessimistic, since it would bring in restrictions
283 : that only apply to FR_REGS. Conversely, if we have a register
284 : that needs to be in FR_REGS, using GR_AND_FR_REGS with the
285 : union-based definition would lose the extra restrictions
286 : placed on FR_REGS. GR_AND_FR_REGS is therefore only useful
287 : for cases where GR_REGS and FP_REGS are both valid. */
288 : int pos;
289 12300202156 : for (pos = 0; pos < narrow.num; ++pos)
290 : {
291 11514307113 : enum reg_class cl2 = narrow.classes[pos];
292 23028614226 : if (hard_reg_set_subset_p (valid_for_cl, reg_class_contents[cl2]))
293 : break;
294 : }
295 1207571649 : map[i] = pos;
296 1207571649 : if (pos == narrow.num)
297 : {
298 : /* If several classes are equivalent, prefer to use the one
299 : that was chosen as the allocno class. */
300 785895043 : enum reg_class cl2 = ira_allocno_class_translate[cl];
301 785895043 : if (ira_class_hard_regs_num[cl] == ira_class_hard_regs_num[cl2])
302 785895043 : cl = cl2;
303 785895043 : narrow.classes[narrow.num++] = cl;
304 : }
305 : }
306 53721260 : if (narrow.num == full->num)
307 : return full;
308 :
309 53720409 : cost_classes **slot = cost_classes_htab->find_slot (&narrow, INSERT);
310 53720409 : if (*slot == NULL)
311 : {
312 4072116 : cost_classes_t classes = setup_cost_classes (&narrow);
313 : /* Map equivalent classes to the representative that we chose above. */
314 130754574 : for (int i = 0; i < ira_important_classes_num; i++)
315 : {
316 126682458 : enum reg_class cl = ira_important_classes[i];
317 126682458 : int index = full->index[cl];
318 126682458 : if (index >= 0)
319 112677268 : classes->index[cl] = map[index];
320 : }
321 4072116 : *slot = classes;
322 : }
323 53720409 : return *slot;
324 : }
325 :
326 : /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
327 : This function is used when we know an initial approximation of
328 : allocno class of the pseudo already, e.g. on the second iteration
329 : of class cost calculation or after class cost calculation in
330 : register-pressure sensitive insn scheduling or register-pressure
331 : sensitive loop-invariant motion. */
332 : static void
333 48798754 : setup_regno_cost_classes_by_aclass (int regno, enum reg_class aclass)
334 : {
335 48798754 : static struct cost_classes classes;
336 48798754 : cost_classes_t classes_ptr;
337 48798754 : enum reg_class cl;
338 48798754 : int i;
339 48798754 : cost_classes **slot;
340 48798754 : HARD_REG_SET temp, temp2;
341 48798754 : bool exclude_p;
342 :
343 48798754 : if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL)
344 : {
345 4073838 : temp = reg_class_contents[aclass] & ~ira_no_alloc_regs;
346 : /* We exclude classes from consideration which are subsets of
347 : ACLASS only if ACLASS is an uniform class. */
348 4073838 : exclude_p = ira_uniform_class_p[aclass];
349 4073838 : classes.num = 0;
350 130762246 : for (i = 0; i < ira_important_classes_num; i++)
351 : {
352 126688408 : cl = ira_important_classes[i];
353 126688408 : if (exclude_p)
354 : {
355 : /* Exclude non-uniform classes which are subsets of
356 : ACLASS. */
357 90268918 : temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs;
358 180537836 : if (hard_reg_set_subset_p (temp2, temp) && cl != aclass)
359 10625134 : continue;
360 : }
361 116063274 : classes.classes[classes.num++] = cl;
362 : }
363 4073838 : slot = cost_classes_htab->find_slot (&classes, INSERT);
364 4073838 : if (*slot == NULL)
365 : {
366 1916716 : classes_ptr = setup_cost_classes (&classes);
367 1916716 : *slot = classes_ptr;
368 : }
369 4073838 : classes_ptr = cost_classes_aclass_cache[aclass] = (cost_classes_t) *slot;
370 : }
371 48798754 : if (regno_reg_rtx[regno] != NULL_RTX)
372 : {
373 : /* Restrict the classes to those that are valid for REGNO's mode
374 : (which might for example exclude singleton classes if the mode
375 : requires two registers). Also restrict the classes to those that
376 : are valid for subregs of REGNO. */
377 48209250 : const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno);
378 48209250 : if (!valid_regs)
379 46855585 : valid_regs = ®_class_contents[ALL_REGS];
380 48209250 : classes_ptr = restrict_cost_classes (classes_ptr,
381 48209250 : PSEUDO_REGNO_MODE (regno),
382 : *valid_regs);
383 : }
384 48798754 : regno_cost_classes[regno] = classes_ptr;
385 48798754 : }
386 :
387 : /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
388 : decrease number of cost classes for the pseudo, if hard registers
389 : of some important classes cannot hold a value of MODE. So the
390 : pseudo cannot get hard register of some important classes and cost
391 : calculation for such important classes is only wasting CPU
392 : time. */
393 : static void
394 66617587 : setup_regno_cost_classes_by_mode (int regno, machine_mode mode)
395 : {
396 66617587 : if (const HARD_REG_SET *valid_regs = valid_mode_changes_for_regno (regno))
397 1773142 : regno_cost_classes[regno] = restrict_cost_classes (&all_cost_classes,
398 : mode, *valid_regs);
399 : else
400 : {
401 64844445 : if (cost_classes_mode_cache[mode] == NULL)
402 3738868 : cost_classes_mode_cache[mode]
403 3738868 : = restrict_cost_classes (&all_cost_classes, mode,
404 3738868 : reg_class_contents[ALL_REGS]);
405 64844445 : regno_cost_classes[regno] = cost_classes_mode_cache[mode];
406 : }
407 66617587 : }
408 :
409 : /* Finalize info about the cost classes for each pseudo. */
410 : static void
411 1500820 : finish_regno_cost_classes (void)
412 : {
413 1500820 : ira_free (regno_cost_classes);
414 1500820 : delete cost_classes_htab;
415 1500820 : cost_classes_htab = NULL;
416 1500820 : }
417 :
418 :
419 :
420 : /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
421 : TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
422 : be a pseudo register. */
423 : static int
424 377652142 : copy_cost (rtx x, machine_mode mode, reg_class_t rclass, bool to_p,
425 : secondary_reload_info *prev_sri)
426 : {
427 377652142 : secondary_reload_info sri;
428 377652142 : reg_class_t secondary_class = NO_REGS;
429 :
430 : /* If X is a SCRATCH, there is actually nothing to move since we are
431 : assuming optimal allocation. */
432 377652142 : if (GET_CODE (x) == SCRATCH)
433 : return 0;
434 :
435 : /* Get the class we will actually use for a reload. */
436 377642597 : rclass = targetm.preferred_reload_class (x, rclass);
437 :
438 : /* If we need a secondary reload for an intermediate, the cost is
439 : that to load the input into the intermediate register, then to
440 : copy it. */
441 377642597 : sri.prev_sri = prev_sri;
442 377642597 : sri.extra_cost = 0;
443 : /* PR 68770: Secondary reload might examine the t_icode field. */
444 377642597 : sri.t_icode = CODE_FOR_nothing;
445 :
446 377642597 : secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri);
447 :
448 377642597 : if (secondary_class != NO_REGS)
449 : {
450 115704 : ira_init_register_move_cost_if_necessary (mode);
451 115704 : return (ira_register_move_cost[mode][(int) secondary_class][(int) rclass]
452 115704 : + sri.extra_cost
453 115704 : + copy_cost (x, mode, secondary_class, to_p, &sri));
454 : }
455 :
456 : /* For memory, use the memory move cost, for (hard) registers, use
457 : the cost to move between the register classes, and use 2 for
458 : everything else (constants). */
459 377526893 : if (MEM_P (x) || rclass == NO_REGS)
460 236069789 : return sri.extra_cost
461 236069789 : + ira_memory_move_cost[mode][(int) rclass][to_p != 0];
462 141457104 : else if (REG_P (x))
463 : {
464 45145148 : reg_class_t x_class = REGNO_REG_CLASS (REGNO (x));
465 :
466 45145148 : ira_init_register_move_cost_if_necessary (mode);
467 45145148 : return (sri.extra_cost
468 45145148 : + ira_register_move_cost[mode][(int) x_class][(int) rclass]);
469 : }
470 : else
471 : /* If this is a constant, we may eventually want to call rtx_cost
472 : here. */
473 96311956 : return sri.extra_cost + COSTS_N_INSNS (1);
474 : }
475 :
476 :
477 :
478 : /* Record the cost of using memory or hard registers of various
479 : classes for the operands in INSN.
480 :
481 : N_ALTS is the number of alternatives.
482 : N_OPS is the number of operands.
483 : OPS is an array of the operands.
484 : MODES are the modes of the operands, in case any are VOIDmode.
485 : CONSTRAINTS are the constraints to use for the operands. This array
486 : is modified by this procedure.
487 :
488 : This procedure works alternative by alternative. For each
489 : alternative we assume that we will be able to allocate all allocnos
490 : to their ideal register class and calculate the cost of using that
491 : alternative. Then we compute, for each operand that is a
492 : pseudo-register, the cost of having the allocno allocated to each
493 : register class and using it in that alternative. To this cost is
494 : added the cost of the alternative.
495 :
496 : The cost of each class for this insn is its lowest cost among all
497 : the alternatives. */
498 : static void
499 139519230 : record_reg_classes (int n_alts, int n_ops, rtx *ops,
500 : machine_mode *modes, const char **constraints,
501 : rtx_insn *insn, enum reg_class *pref)
502 : {
503 139519230 : int alt;
504 139519230 : int i, j, k;
505 139519230 : int insn_allows_mem[MAX_RECOG_OPERANDS];
506 139519230 : move_table *move_in_cost, *move_out_cost;
507 139519230 : short (*mem_cost)[2];
508 139519230 : const char *p;
509 :
510 139519230 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
511 : {
512 0 : fprintf (ira_dump_file, " Processing insn %u", INSN_UID (insn));
513 0 : if (INSN_CODE (insn) >= 0
514 0 : && (p = get_insn_name (INSN_CODE (insn))) != NULL)
515 0 : fprintf (ira_dump_file, " {%s}", p);
516 0 : fprintf (ira_dump_file, " (freq=%d)\n",
517 0 : REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
518 0 : dump_insn_slim (ira_dump_file, insn);
519 : }
520 :
521 459406272 : for (i = 0; i < n_ops; i++)
522 319887042 : insn_allows_mem[i] = 0;
523 :
524 : /* Process each alternative, each time minimizing an operand's cost
525 : with the cost for each operand in that alternative. */
526 139519230 : alternative_mask preferred = get_preferred_alternatives (insn);
527 1566403283 : for (alt = 0; alt < n_alts; alt++)
528 : {
529 1426884053 : enum reg_class classes[MAX_RECOG_OPERANDS];
530 1426884053 : int allows_mem[MAX_RECOG_OPERANDS];
531 1426884053 : enum reg_class rclass;
532 1426884053 : int alt_fail = 0;
533 1426884053 : int alt_cost = 0, op_cost_add;
534 :
535 1426884053 : if (!TEST_BIT (preferred, alt))
536 : {
537 1450838674 : for (i = 0; i < recog_data.n_operands; i++)
538 2008081146 : constraints[i] = skip_alternative (constraints[i]);
539 :
540 931792042 : continue;
541 : }
542 :
543 980085952 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
544 : {
545 0 : fprintf (ira_dump_file, " Alt %d:", alt);
546 0 : for (i = 0; i < n_ops; i++)
547 : {
548 0 : p = constraints[i];
549 0 : if (*p == '\0')
550 0 : continue;
551 0 : fprintf (ira_dump_file, " (%d) ", i);
552 0 : for (; *p != '\0' && *p != ',' && *p != '#'; p++)
553 0 : fputc (*p, ira_dump_file);
554 : }
555 0 : fprintf (ira_dump_file, "\n");
556 : }
557 :
558 2327620641 : for (i = 0; i < n_ops; i++)
559 : {
560 1832528630 : unsigned char c;
561 1832528630 : const char *p = constraints[i];
562 1832528630 : rtx op = ops[i];
563 1832528630 : machine_mode mode = modes[i];
564 1832528630 : int allows_addr = 0;
565 1832528630 : int win = 0;
566 :
567 : /* Initially show we know nothing about the register class. */
568 1832528630 : classes[i] = NO_REGS;
569 1832528630 : allows_mem[i] = 0;
570 :
571 : /* If this operand has no constraints at all, we can
572 : conclude nothing about it since anything is valid. */
573 1832528630 : if (*p == 0)
574 : {
575 29267742 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
576 3 : memset (this_op_costs[i], 0, struct_costs_size);
577 29267742 : continue;
578 : }
579 :
580 : /* If this alternative is only relevant when this operand
581 : matches a previous operand, we do different things
582 : depending on whether this operand is a allocno-reg or not.
583 : We must process any modifiers for the operand before we
584 : can make this test. */
585 1905400617 : while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
586 102139729 : p++;
587 :
588 1803260888 : if (p[0] >= '0' && p[0] <= '0' + i)
589 : {
590 : /* Copy class and whether memory is allowed from the
591 : matching alternative. Then perform any needed cost
592 : computations and/or adjustments. */
593 96320511 : j = p[0] - '0';
594 96320511 : classes[i] = classes[j];
595 96320511 : allows_mem[i] = allows_mem[j];
596 96320511 : if (allows_mem[i])
597 45802634 : insn_allows_mem[i] = 1;
598 :
599 96320511 : if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
600 : {
601 : /* If this matches the other operand, we have no
602 : added cost and we win. */
603 49328891 : if (rtx_equal_p (ops[j], op))
604 1803260888 : win = 1;
605 : /* If we can put the other operand into a register,
606 : add to the cost of this alternative the cost to
607 : copy this operand to the register used for the
608 : other operand. */
609 33673075 : else if (classes[j] != NO_REGS)
610 : {
611 33512282 : alt_cost += copy_cost (op, mode, classes[j], 1, NULL);
612 33512282 : win = 1;
613 : }
614 : }
615 46991620 : else if (! REG_P (ops[j])
616 46991620 : || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
617 : {
618 : /* This op is an allocno but the one it matches is
619 : not. */
620 :
621 : /* If we can't put the other operand into a
622 : register, this alternative can't be used. */
623 :
624 181691 : if (classes[j] == NO_REGS)
625 : {
626 1803260888 : alt_fail = 1;
627 : }
628 : else
629 : /* Otherwise, add to the cost of this alternative the cost
630 : to copy the other operand to the hard register used for
631 : this operand. */
632 : {
633 171683 : alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL);
634 : }
635 : }
636 : else
637 : {
638 : /* The costs of this operand are not the same as the
639 : other operand since move costs are not symmetric.
640 : Moreover, if we cannot tie them, this alternative
641 : needs to do a copy, which is one insn. */
642 46809929 : struct costs *pp = this_op_costs[i];
643 46809929 : int *pp_costs = pp->cost;
644 46809929 : cost_classes_t cost_classes_ptr
645 46809929 : = regno_cost_classes[REGNO (op)];
646 46809929 : enum reg_class *cost_classes = cost_classes_ptr->classes;
647 46809929 : bool in_p = recog_data.operand_type[i] != OP_OUT;
648 46809929 : bool out_p = recog_data.operand_type[i] != OP_IN;
649 46809929 : enum reg_class op_class = classes[i];
650 :
651 46809929 : ira_init_register_move_cost_if_necessary (mode);
652 46809929 : if (! in_p)
653 : {
654 60977 : ira_assert (out_p);
655 60977 : if (op_class == NO_REGS)
656 : {
657 0 : mem_cost = ira_memory_move_cost[mode];
658 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
659 : {
660 0 : rclass = cost_classes[k];
661 0 : pp_costs[k] = mem_cost[rclass][0] * frequency;
662 : }
663 : }
664 : else
665 : {
666 60977 : move_out_cost = ira_may_move_out_cost[mode];
667 844672 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
668 : {
669 783695 : rclass = cost_classes[k];
670 783695 : pp_costs[k]
671 783695 : = move_out_cost[op_class][rclass] * frequency;
672 : }
673 : }
674 : }
675 46748952 : else if (! out_p)
676 : {
677 46748952 : ira_assert (in_p);
678 46748952 : if (op_class == NO_REGS)
679 : {
680 427165 : mem_cost = ira_memory_move_cost[mode];
681 6216417 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
682 : {
683 5789252 : rclass = cost_classes[k];
684 5789252 : pp_costs[k] = mem_cost[rclass][1] * frequency;
685 : }
686 : }
687 : else
688 : {
689 46321787 : move_in_cost = ira_may_move_in_cost[mode];
690 698643443 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
691 : {
692 652321656 : rclass = cost_classes[k];
693 652321656 : pp_costs[k]
694 652321656 : = move_in_cost[rclass][op_class] * frequency;
695 : }
696 : }
697 : }
698 : else
699 : {
700 0 : if (op_class == NO_REGS)
701 : {
702 0 : mem_cost = ira_memory_move_cost[mode];
703 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
704 : {
705 0 : rclass = cost_classes[k];
706 0 : pp_costs[k] = ((mem_cost[rclass][0]
707 0 : + mem_cost[rclass][1])
708 0 : * frequency);
709 : }
710 : }
711 : else
712 : {
713 0 : move_in_cost = ira_may_move_in_cost[mode];
714 0 : move_out_cost = ira_may_move_out_cost[mode];
715 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
716 : {
717 0 : rclass = cost_classes[k];
718 0 : pp_costs[k] = ((move_in_cost[rclass][op_class]
719 0 : + move_out_cost[op_class][rclass])
720 0 : * frequency);
721 : }
722 : }
723 : }
724 :
725 : /* If the alternative actually allows memory, make
726 : things a bit cheaper since we won't need an extra
727 : insn to load it. */
728 46809929 : pp->mem_cost
729 46809929 : = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)
730 46809929 : + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)
731 46809929 : - allows_mem[i]) * frequency;
732 :
733 : /* If we have assigned a class to this allocno in
734 : our first pass, add a cost to this alternative
735 : corresponding to what we would add if this
736 : allocno were not in the appropriate class. */
737 46809929 : if (pref)
738 : {
739 17836391 : enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
740 :
741 17836391 : if (pref_class == NO_REGS)
742 634694 : alt_cost
743 634694 : += ((out_p
744 : ? ira_memory_move_cost[mode][op_class][0] : 0)
745 : + (in_p
746 : ? ira_memory_move_cost[mode][op_class][1]
747 : : 0));
748 17201697 : else if (ira_reg_class_intersect
749 17201697 : [pref_class][op_class] == NO_REGS)
750 314791 : alt_cost
751 314791 : += ira_register_move_cost[mode][pref_class][op_class];
752 : }
753 46809929 : if (REGNO (ops[i]) != REGNO (ops[j])
754 46809929 : && ! find_reg_note (insn, REG_DEAD, op))
755 13196511 : alt_cost += 2;
756 :
757 46809929 : p++;
758 : }
759 : }
760 :
761 : /* Scan all the constraint letters. See if the operand
762 : matches any of the constraints. Collect the valid
763 : register classes and see if this operand accepts
764 : memory. */
765 4350752925 : while ((c = *p))
766 : {
767 4284356544 : switch (c)
768 : {
769 317410413 : case '*':
770 : /* Ignore the next letter for this pass. */
771 317410413 : c = *++p;
772 317410413 : break;
773 :
774 0 : case '^':
775 0 : alt_cost += 2;
776 0 : break;
777 :
778 504631429 : case '?':
779 504631429 : alt_cost += 2;
780 504631429 : break;
781 :
782 12669270 : case 'g':
783 12669270 : if (MEM_P (op)
784 12669270 : || (CONSTANT_P (op)
785 5120343 : && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))))
786 : win = 1;
787 12669270 : insn_allows_mem[i] = allows_mem[i] = 1;
788 12669270 : classes[i] = ira_reg_class_subunion[classes[i]][GENERAL_REGS];
789 12669270 : break;
790 :
791 3449645432 : default:
792 3449645432 : enum constraint_num cn = lookup_constraint (p);
793 3449645432 : enum reg_class cl;
794 3449645432 : switch (get_constraint_type (cn))
795 : {
796 2804031826 : case CT_REGISTER:
797 2804031826 : cl = reg_class_for_constraint (cn);
798 1002226827 : if (cl != NO_REGS)
799 991636075 : classes[i] = ira_reg_class_subunion[classes[i]][cl];
800 : break;
801 :
802 4786651 : case CT_CONST_INT:
803 4786651 : if (CONST_INT_P (op)
804 4786651 : && insn_const_int_ok_for_constraint (INTVAL (op), cn))
805 : win = 1;
806 : break;
807 :
808 276146745 : case CT_MEMORY:
809 276146745 : case CT_RELAXED_MEMORY:
810 : /* Every MEM can be reloaded to fit. */
811 276146745 : insn_allows_mem[i] = allows_mem[i] = 1;
812 276146745 : if (MEM_P (op))
813 79687817 : win = 1;
814 : break;
815 :
816 39577035 : case CT_SPECIAL_MEMORY:
817 39577035 : insn_allows_mem[i] = allows_mem[i] = 1;
818 39577035 : if (MEM_P (extract_mem_from_operand (op))
819 39577035 : && constraint_satisfied_p (op, cn))
820 : win = 1;
821 : break;
822 :
823 1161753 : case CT_ADDRESS:
824 : /* Every address can be reloaded to fit. */
825 1161753 : allows_addr = 1;
826 1161753 : if (address_operand (op, GET_MODE (op))
827 1161753 : || constraint_satisfied_p (op, cn))
828 : win = 1;
829 : /* We know this operand is an address, so we
830 : want it to be allocated to a hard register
831 : that can be the base of an address,
832 : i.e. BASE_REG_CLASS. */
833 1161753 : classes[i]
834 2323506 : = ira_reg_class_subunion[classes[i]]
835 1161753 : [base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
836 1161753 : ADDRESS, SCRATCH)];
837 1161753 : break;
838 :
839 323941422 : case CT_FIXED_FORM:
840 323941422 : if (constraint_satisfied_p (op, cn))
841 4284356544 : win = 1;
842 : break;
843 : }
844 : break;
845 : }
846 4284356544 : p += CONSTRAINT_LEN (c, p);
847 4284356544 : if (c == ',')
848 : break;
849 : }
850 :
851 1803260888 : constraints[i] = p;
852 :
853 1803260888 : if (alt_fail)
854 : break;
855 :
856 : /* How we account for this operand now depends on whether it
857 : is a pseudo register or not. If it is, we first check if
858 : any register classes are valid. If not, we ignore this
859 : alternative, since we want to assume that all allocnos get
860 : allocated for register preferencing. If some register
861 : class is valid, compute the costs of moving the allocno
862 : into that class. */
863 1803250880 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
864 : {
865 817081981 : if (classes[i] == NO_REGS && ! allows_mem[i])
866 : {
867 : /* We must always fail if the operand is a REG, but
868 : we did not find a suitable class and memory is
869 : not allowed.
870 :
871 : Otherwise we may perform an uninitialized read
872 : from this_op_costs after the `continue' statement
873 : below. */
874 : alt_fail = 1;
875 : }
876 : else
877 : {
878 613520521 : unsigned int regno = REGNO (op);
879 613520521 : struct costs *pp = this_op_costs[i];
880 613520521 : int *pp_costs = pp->cost;
881 613520521 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
882 613520521 : enum reg_class *cost_classes = cost_classes_ptr->classes;
883 613520521 : bool in_p = recog_data.operand_type[i] != OP_OUT;
884 613520521 : bool out_p = recog_data.operand_type[i] != OP_IN;
885 613520521 : enum reg_class op_class = classes[i];
886 :
887 613520521 : ira_init_register_move_cost_if_necessary (mode);
888 613520521 : if (! in_p)
889 : {
890 392580073 : ira_assert (out_p);
891 392580073 : if (op_class == NO_REGS)
892 : {
893 72091468 : mem_cost = ira_memory_move_cost[mode];
894 1114292227 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
895 : {
896 1042200759 : rclass = cost_classes[k];
897 1042200759 : pp_costs[k] = mem_cost[rclass][0] * frequency;
898 : }
899 : }
900 : else
901 : {
902 320488605 : move_out_cost = ira_may_move_out_cost[mode];
903 4853181838 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
904 : {
905 4532693233 : rclass = cost_classes[k];
906 4532693233 : pp_costs[k]
907 4532693233 : = move_out_cost[op_class][rclass] * frequency;
908 : }
909 : }
910 : }
911 220940448 : else if (! out_p)
912 : {
913 220927495 : ira_assert (in_p);
914 220927495 : if (op_class == NO_REGS)
915 : {
916 16383315 : mem_cost = ira_memory_move_cost[mode];
917 241925438 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
918 : {
919 225542123 : rclass = cost_classes[k];
920 225542123 : pp_costs[k] = mem_cost[rclass][1] * frequency;
921 : }
922 : }
923 : else
924 : {
925 204544180 : move_in_cost = ira_may_move_in_cost[mode];
926 3005863011 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
927 : {
928 2801318831 : rclass = cost_classes[k];
929 2801318831 : pp_costs[k]
930 2801318831 : = move_in_cost[rclass][op_class] * frequency;
931 : }
932 : }
933 : }
934 : else
935 : {
936 12953 : if (op_class == NO_REGS)
937 : {
938 0 : mem_cost = ira_memory_move_cost[mode];
939 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
940 : {
941 0 : rclass = cost_classes[k];
942 0 : pp_costs[k] = ((mem_cost[rclass][0]
943 0 : + mem_cost[rclass][1])
944 0 : * frequency);
945 : }
946 : }
947 : else
948 : {
949 12953 : move_in_cost = ira_may_move_in_cost[mode];
950 12953 : move_out_cost = ira_may_move_out_cost[mode];
951 152907 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
952 : {
953 139954 : rclass = cost_classes[k];
954 139954 : pp_costs[k] = ((move_in_cost[rclass][op_class]
955 139954 : + move_out_cost[op_class][rclass])
956 139954 : * frequency);
957 : }
958 : }
959 : }
960 :
961 613520521 : if (op_class == NO_REGS)
962 : /* Although we don't need insn to reload from
963 : memory, still accessing memory is usually more
964 : expensive than a register. */
965 88474783 : pp->mem_cost = frequency;
966 : else
967 : /* If the alternative actually allows memory, make
968 : things a bit cheaper since we won't need an
969 : extra insn to load it. */
970 525045738 : pp->mem_cost
971 525045738 : = ((out_p ? ira_memory_move_cost[mode][op_class][0] : 0)
972 525045738 : + (in_p ? ira_memory_move_cost[mode][op_class][1] : 0)
973 525045738 : - allows_mem[i]) * frequency;
974 : /* If we have assigned a class to this allocno in
975 : our first pass, add a cost to this alternative
976 : corresponding to what we would add if this
977 : allocno were not in the appropriate class. */
978 613520521 : if (pref)
979 : {
980 225072055 : enum reg_class pref_class = pref[COST_INDEX (REGNO (op))];
981 :
982 225072055 : if (pref_class == NO_REGS)
983 : {
984 4358120 : if (op_class != NO_REGS)
985 3523310 : alt_cost
986 3523310 : += ((out_p
987 3523310 : ? ira_memory_move_cost[mode][op_class][0]
988 : : 0)
989 3523310 : + (in_p
990 3523310 : ? ira_memory_move_cost[mode][op_class][1]
991 : : 0));
992 : }
993 220713935 : else if (op_class == NO_REGS)
994 30300393 : alt_cost
995 30300393 : += ((out_p
996 30300393 : ? ira_memory_move_cost[mode][pref_class][1]
997 : : 0)
998 30300393 : + (in_p
999 30300393 : ? ira_memory_move_cost[mode][pref_class][0]
1000 : : 0));
1001 190413542 : else if (ira_reg_class_intersect[pref_class][op_class]
1002 : == NO_REGS)
1003 40328932 : alt_cost += (ira_register_move_cost
1004 40328932 : [mode][pref_class][op_class]);
1005 : }
1006 : }
1007 : }
1008 :
1009 : /* Otherwise, if this alternative wins, either because we
1010 : have already determined that or if we have a hard
1011 : register of the proper class, there is no cost for this
1012 : alternative. */
1013 986168899 : else if (win || (REG_P (op)
1014 233857360 : && reg_fits_class_p (op, classes[i],
1015 233857360 : 0, GET_MODE (op))))
1016 : ;
1017 :
1018 : /* If registers are valid, the cost of this alternative
1019 : includes copying the object to and/or from a
1020 : register. */
1021 646124228 : else if (classes[i] != NO_REGS)
1022 : {
1023 343852449 : if (recog_data.operand_type[i] != OP_OUT)
1024 184299349 : alt_cost += copy_cost (op, mode, classes[i], 1, NULL);
1025 :
1026 343852449 : if (recog_data.operand_type[i] != OP_IN)
1027 159553124 : alt_cost += copy_cost (op, mode, classes[i], 0, NULL);
1028 : }
1029 : /* The only other way this alternative can be used is if
1030 : this is a constant that could be placed into memory. */
1031 302271779 : else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1032 20849306 : alt_cost += ira_memory_move_cost[mode][classes[i]][1];
1033 : else
1034 : alt_fail = 1;
1035 :
1036 : if (alt_fail)
1037 : break;
1038 : }
1039 :
1040 980085952 : if (alt_fail)
1041 : {
1042 : /* The loop above might have exited early once the failure
1043 : was seen. Skip over the constraints for the remaining
1044 : operands. */
1045 484993941 : i += 1;
1046 777321668 : for (; i < n_ops; ++i)
1047 584655454 : constraints[i] = skip_alternative (constraints[i]);
1048 484993941 : continue;
1049 : }
1050 :
1051 495092011 : op_cost_add = alt_cost * frequency;
1052 : /* Finally, update the costs with the information we've
1053 : calculated about this alternative. */
1054 1601843390 : for (i = 0; i < n_ops; i++)
1055 1106751379 : if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1056 : {
1057 468829735 : int old_cost;
1058 468829735 : bool cost_change_p = false;
1059 468829735 : struct costs *pp = op_costs[i], *qq = this_op_costs[i];
1060 468829735 : int *pp_costs = pp->cost, *qq_costs = qq->cost;
1061 468829735 : int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1062 468829735 : cost_classes_t cost_classes_ptr
1063 468829735 : = regno_cost_classes[REGNO (ops[i])];
1064 :
1065 468829735 : old_cost = pp->mem_cost;
1066 468829735 : pp->mem_cost = MIN (old_cost,
1067 : (qq->mem_cost + op_cost_add) * scale);
1068 :
1069 468829735 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1070 0 : && pp->mem_cost < old_cost)
1071 : {
1072 0 : cost_change_p = true;
1073 0 : fprintf (ira_dump_file, " op %d(r=%u) new costs MEM:%d",
1074 : i, REGNO(ops[i]), pp->mem_cost);
1075 : }
1076 7005915906 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1077 : {
1078 6537086171 : old_cost = pp_costs[k];
1079 6537086171 : pp_costs[k]
1080 6537086171 : = MIN (old_cost, (qq_costs[k] + op_cost_add) * scale);
1081 6537086171 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1082 0 : && pp_costs[k] < old_cost)
1083 : {
1084 0 : if (!cost_change_p)
1085 0 : fprintf (ira_dump_file, " op %d(r=%u) new costs",
1086 : i, REGNO(ops[i]));
1087 0 : cost_change_p = true;
1088 0 : fprintf (ira_dump_file, " %s:%d",
1089 0 : reg_class_names[cost_classes_ptr->classes[k]],
1090 : pp_costs[k]);
1091 : }
1092 : }
1093 468829735 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5
1094 0 : && cost_change_p)
1095 0 : fprintf (ira_dump_file, "\n");
1096 : }
1097 : }
1098 :
1099 139519230 : if (allocno_p)
1100 446937868 : for (i = 0; i < n_ops; i++)
1101 : {
1102 311194387 : ira_allocno_t a;
1103 311194387 : rtx op = ops[i];
1104 :
1105 311194387 : if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER)
1106 180934367 : continue;
1107 130260020 : a = ira_curr_regno_allocno_map [REGNO (op)];
1108 130260020 : if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0)
1109 12059146 : ALLOCNO_BAD_SPILL_P (a) = true;
1110 : }
1111 :
1112 139519230 : }
1113 :
1114 :
1115 :
1116 : /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
1117 : static inline bool
1118 145602 : ok_for_index_p_nonstrict (rtx reg)
1119 : {
1120 145602 : unsigned regno = REGNO (reg);
1121 :
1122 145602 : return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
1123 : }
1124 :
1125 : /* A version of regno_ok_for_base_p for use here, when all
1126 : pseudo-registers should count as OK. Arguments as for
1127 : regno_ok_for_base_p. */
1128 : static inline bool
1129 147942 : ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as,
1130 : enum rtx_code outer_code, enum rtx_code index_code)
1131 : {
1132 147942 : unsigned regno = REGNO (reg);
1133 :
1134 1170 : if (regno >= FIRST_PSEUDO_REGISTER)
1135 : return true;
1136 1170 : return ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
1137 : }
1138 :
1139 : /* Record the pseudo registers we must reload into hard registers in a
1140 : subexpression of a memory address, X.
1141 :
1142 : If CONTEXT is 0, we are looking at the base part of an address,
1143 : otherwise we are looking at the index part.
1144 :
1145 : MODE and AS are the mode and address space of the memory reference;
1146 : OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1147 : These four arguments are passed down to base_reg_class.
1148 :
1149 : SCALE is twice the amount to multiply the cost by (it is twice so
1150 : we can represent half-cost adjustments). */
1151 : static void
1152 94191672 : record_address_regs (machine_mode mode, addr_space_t as, rtx x,
1153 : int context, enum rtx_code outer_code,
1154 : enum rtx_code index_code, int scale)
1155 : {
1156 94191672 : enum rtx_code code = GET_CODE (x);
1157 94191672 : enum reg_class rclass;
1158 :
1159 94191672 : if (context == 1)
1160 : rclass = INDEX_REG_CLASS;
1161 : else
1162 86847766 : rclass = base_reg_class (mode, as, outer_code, index_code);
1163 :
1164 94191672 : switch (code)
1165 : {
1166 : case CONST_INT:
1167 : case CONST:
1168 : case PC:
1169 : case SYMBOL_REF:
1170 : case LABEL_REF:
1171 : return;
1172 :
1173 33106574 : case PLUS:
1174 : /* When we have an address that is a sum, we must determine
1175 : whether registers are "base" or "index" regs. If there is a
1176 : sum of two registers, we must choose one to be the "base".
1177 : Luckily, we can use the REG_POINTER to make a good choice
1178 : most of the time. We only need to do this on machines that
1179 : can have two registers in an address and where the base and
1180 : index register classes are different.
1181 :
1182 : ??? This code used to set REGNO_POINTER_FLAG in some cases,
1183 : but that seems bogus since it should only be set when we are
1184 : sure the register is being used as a pointer. */
1185 33106574 : {
1186 33106574 : rtx arg0 = XEXP (x, 0);
1187 33106574 : rtx arg1 = XEXP (x, 1);
1188 33106574 : enum rtx_code code0 = GET_CODE (arg0);
1189 33106574 : enum rtx_code code1 = GET_CODE (arg1);
1190 :
1191 : /* Look inside subregs. */
1192 33106574 : if (code0 == SUBREG)
1193 13848 : arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1194 33106574 : if (code1 == SUBREG)
1195 5408 : arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1196 :
1197 : /* If index registers do not appear, or coincide with base registers,
1198 : just record registers in any non-constant operands. We
1199 : assume here, as well as in the tests below, that all
1200 : addresses are in canonical form. */
1201 66213148 : if (MAX_REGS_PER_ADDRESS == 1
1202 33106574 : || INDEX_REG_CLASS == base_reg_class (VOIDmode, as, PLUS, SCRATCH))
1203 : {
1204 0 : record_address_regs (mode, as, arg0, context, PLUS, code1, scale);
1205 0 : if (! CONSTANT_P (arg1))
1206 0 : record_address_regs (mode, as, arg1, context, PLUS, code0, scale);
1207 : }
1208 :
1209 : /* If the second operand is a constant integer, it doesn't
1210 : change what class the first operand must be. */
1211 33106574 : else if (CONST_SCALAR_INT_P (arg1))
1212 29480763 : record_address_regs (mode, as, arg0, context, PLUS, code1, scale);
1213 : /* If the second operand is a symbolic constant, the first
1214 : operand must be an index register. */
1215 3625811 : else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1216 931582 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale);
1217 : /* If both operands are registers but one is already a hard
1218 : register of index or reg-base class, give the other the
1219 : class that the hard register is not. */
1220 2694229 : else if (code0 == REG && code1 == REG
1221 1494355 : && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1222 2840176 : && (ok_for_base_p_nonstrict (arg0, mode, as, PLUS, REG)
1223 144787 : || ok_for_index_p_nonstrict (arg0)))
1224 3480 : record_address_regs (mode, as, arg1,
1225 3480 : ok_for_base_p_nonstrict (arg0, mode, as,
1226 : PLUS, REG) ? 1 : 0,
1227 : PLUS, REG, scale);
1228 2693069 : else if (code0 == REG && code1 == REG
1229 1493195 : && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1230 2693894 : && (ok_for_base_p_nonstrict (arg1, mode, as, PLUS, REG)
1231 815 : || ok_for_index_p_nonstrict (arg1)))
1232 30 : record_address_regs (mode, as, arg0,
1233 30 : ok_for_base_p_nonstrict (arg1, mode, as,
1234 : PLUS, REG) ? 1 : 0,
1235 : PLUS, REG, scale);
1236 : /* If one operand is known to be a pointer, it must be the
1237 : base with the other operand the index. Likewise if the
1238 : other operand is a MULT. */
1239 2693059 : else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT)
1240 : {
1241 1272671 : record_address_regs (mode, as, arg0, 0, PLUS, code1, scale);
1242 1272671 : record_address_regs (mode, as, arg1, 1, PLUS, code0, scale);
1243 : }
1244 1420388 : else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT)
1245 : {
1246 1043737 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale);
1247 1043737 : record_address_regs (mode, as, arg1, 0, PLUS, code0, scale);
1248 : }
1249 : /* Otherwise, count equal chances that each might be a base or
1250 : index register. This case should be rare. */
1251 : else
1252 : {
1253 376651 : record_address_regs (mode, as, arg0, 0, PLUS, code1, scale / 2);
1254 376651 : record_address_regs (mode, as, arg0, 1, PLUS, code1, scale / 2);
1255 376651 : record_address_regs (mode, as, arg1, 0, PLUS, code0, scale / 2);
1256 376651 : record_address_regs (mode, as, arg1, 1, PLUS, code0, scale / 2);
1257 : }
1258 : }
1259 : break;
1260 :
1261 : /* Double the importance of an allocno that is incremented or
1262 : decremented, since it would take two extra insns if it ends
1263 : up in the wrong place. */
1264 164833 : case POST_MODIFY:
1265 164833 : case PRE_MODIFY:
1266 164833 : record_address_regs (mode, as, XEXP (x, 0), 0, code,
1267 164833 : GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale);
1268 164833 : if (REG_P (XEXP (XEXP (x, 1), 1)))
1269 0 : record_address_regs (mode, as, XEXP (XEXP (x, 1), 1), 1, code, REG,
1270 : 2 * scale);
1271 : break;
1272 :
1273 3358597 : case POST_INC:
1274 3358597 : case PRE_INC:
1275 3358597 : case POST_DEC:
1276 3358597 : case PRE_DEC:
1277 : /* Double the importance of an allocno that is incremented or
1278 : decremented, since it would take two extra insns if it ends
1279 : up in the wrong place. */
1280 3358597 : record_address_regs (mode, as, XEXP (x, 0), 0, code, SCRATCH, 2 * scale);
1281 3358597 : break;
1282 :
1283 45173051 : case REG:
1284 45173051 : {
1285 45173051 : struct costs *pp;
1286 45173051 : int *pp_costs;
1287 45173051 : enum reg_class i;
1288 45173051 : int k, regno, add_cost;
1289 45173051 : cost_classes_t cost_classes_ptr;
1290 45173051 : enum reg_class *cost_classes;
1291 45173051 : move_table *move_in_cost;
1292 :
1293 45173051 : if (REGNO (x) < FIRST_PSEUDO_REGISTER)
1294 : break;
1295 :
1296 20886271 : regno = REGNO (x);
1297 20886271 : if (allocno_p)
1298 20512908 : ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) = true;
1299 20886271 : pp = COSTS (costs, COST_INDEX (regno));
1300 20886271 : add_cost = (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2;
1301 20886271 : if (INT_MAX - add_cost < pp->mem_cost)
1302 0 : pp->mem_cost = INT_MAX;
1303 : else
1304 20886271 : pp->mem_cost += add_cost;
1305 20886271 : cost_classes_ptr = regno_cost_classes[regno];
1306 20886271 : cost_classes = cost_classes_ptr->classes;
1307 20886271 : pp_costs = pp->cost;
1308 20886271 : ira_init_register_move_cost_if_necessary (Pmode);
1309 20886271 : move_in_cost = ira_may_move_in_cost[Pmode];
1310 337482933 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1311 : {
1312 316596662 : i = cost_classes[k];
1313 316596662 : add_cost = (move_in_cost[i][rclass] * scale) / 2;
1314 316596662 : if (INT_MAX - add_cost < pp_costs[k])
1315 14447 : pp_costs[k] = INT_MAX;
1316 : else
1317 316582215 : pp_costs[k] += add_cost;
1318 : }
1319 : }
1320 : break;
1321 :
1322 2206787 : default:
1323 2206787 : {
1324 2206787 : const char *fmt = GET_RTX_FORMAT (code);
1325 2206787 : int i;
1326 6110534 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1327 3903747 : if (fmt[i] == 'e')
1328 3888477 : record_address_regs (mode, as, XEXP (x, i), context, code, SCRATCH,
1329 : scale);
1330 : }
1331 : }
1332 : }
1333 :
1334 :
1335 :
1336 : /* Calculate the costs of insn operands. */
1337 : static void
1338 140392339 : record_operand_costs (rtx_insn *insn, enum reg_class *pref)
1339 : {
1340 140392339 : const char *constraints[MAX_RECOG_OPERANDS];
1341 140392339 : machine_mode modes[MAX_RECOG_OPERANDS];
1342 140392339 : rtx set;
1343 140392339 : int i;
1344 :
1345 140392339 : if ((set = single_set (insn)) != NULL_RTX
1346 : /* In rare cases the single set insn might have less 2 operands
1347 : as the source can be a fixed special reg. */
1348 132796896 : && recog_data.n_operands > 1
1349 127766866 : && recog_data.operand[0] == SET_DEST (set)
1350 245146020 : && recog_data.operand[1] == SET_SRC (set))
1351 : {
1352 75936406 : int regno, other_regno;
1353 75936406 : rtx dest = SET_DEST (set);
1354 75936406 : rtx src = SET_SRC (set);
1355 :
1356 75936406 : if (GET_CODE (dest) == SUBREG
1357 77790446 : && known_eq (GET_MODE_SIZE (GET_MODE (dest)),
1358 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
1359 : dest = SUBREG_REG (dest);
1360 75936406 : if (GET_CODE (src) == SUBREG
1361 78765572 : && known_eq (GET_MODE_SIZE (GET_MODE (src)),
1362 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
1363 : src = SUBREG_REG (src);
1364 35746390 : if (REG_P (src) && REG_P (dest)
1365 97181089 : && (((regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
1366 14728839 : && (other_regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER)
1367 10031564 : || ((regno = REGNO (dest)) >= FIRST_PSEUDO_REGISTER
1368 10001834 : && (other_regno = REGNO (src)) < FIRST_PSEUDO_REGISTER)))
1369 : {
1370 17699233 : machine_mode mode = GET_MODE (SET_SRC (set)), cost_mode = mode;
1371 17699233 : machine_mode hard_reg_mode = GET_MODE(regno_reg_rtx[other_regno]);
1372 35398466 : poly_int64 pmode_size = GET_MODE_SIZE (mode);
1373 35398466 : poly_int64 phard_reg_mode_size = GET_MODE_SIZE (hard_reg_mode);
1374 17699233 : HOST_WIDE_INT mode_size, hard_reg_mode_size;
1375 17699233 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1376 17699233 : enum reg_class *cost_classes = cost_classes_ptr->classes;
1377 17699233 : reg_class_t rclass, hard_reg_class, bigger_hard_reg_class;
1378 17699233 : int cost_factor = 1, cost, k;
1379 17699233 : move_table *move_costs;
1380 17699233 : bool dead_p = find_regno_note (insn, REG_DEAD, REGNO (src));
1381 :
1382 17699233 : hard_reg_class = REGNO_REG_CLASS (other_regno);
1383 17699233 : bigger_hard_reg_class = ira_pressure_class_translate[hard_reg_class];
1384 : /* Target code may return any cost for mode which does not fit the
1385 : hard reg class (e.g. DImode for AREG on i386). Check this and use
1386 : a bigger class to get the right cost. */
1387 17699233 : if (bigger_hard_reg_class != NO_REGS
1388 17699233 : && ! ira_hard_reg_in_set_p (other_regno, mode,
1389 : reg_class_contents[hard_reg_class]))
1390 : hard_reg_class = bigger_hard_reg_class;
1391 17699233 : ira_init_register_move_cost_if_necessary (mode);
1392 17699233 : ira_init_register_move_cost_if_necessary (hard_reg_mode);
1393 : /* Use smaller movement cost for natural hard reg mode or its mode as
1394 : operand. */
1395 17699233 : if (pmode_size.is_constant (&mode_size)
1396 17699233 : && phard_reg_mode_size.is_constant (&hard_reg_mode_size))
1397 : {
1398 : /* Assume we are moving in the natural modes: */
1399 17699233 : cost_factor = mode_size / hard_reg_mode_size;
1400 17699233 : if (mode_size % hard_reg_mode_size != 0)
1401 3824597 : cost_factor++;
1402 17699233 : if (cost_factor
1403 17699233 : * (ira_register_move_cost
1404 17699233 : [hard_reg_mode][hard_reg_class][hard_reg_class])
1405 : < (ira_register_move_cost
1406 17699233 : [mode][hard_reg_class][hard_reg_class]))
1407 0 : cost_mode = hard_reg_mode;
1408 : else
1409 : cost_factor = 1;
1410 : }
1411 17699233 : move_costs = ira_register_move_cost[cost_mode];
1412 17699233 : i = regno == (int) REGNO (src) ? 1 : 0;
1413 332650721 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1414 : {
1415 314951488 : rclass = cost_classes[k];
1416 629902976 : cost = (i == 0
1417 314951488 : ? move_costs[hard_reg_class][rclass]
1418 201145659 : : move_costs[rclass][hard_reg_class]);
1419 314951488 : cost *= cost_factor;
1420 314951488 : op_costs[i]->cost[k] = cost * frequency;
1421 : /* If this insn is a single set copying operand 1 to
1422 : operand 0 and one operand is an allocno with the
1423 : other a hard reg or an allocno that prefers a hard
1424 : register that is in its own register class then we
1425 : may want to adjust the cost of that register class to
1426 : -1.
1427 :
1428 : Avoid the adjustment if the source does not die to
1429 : avoid stressing of register allocator by preferencing
1430 : two colliding registers into single class. */
1431 314951488 : if (dead_p
1432 255116699 : && TEST_HARD_REG_BIT (reg_class_contents[rclass], other_regno)
1433 314951488 : && (reg_class_size[(int) rclass]
1434 : == (ira_reg_class_max_nregs
1435 105423609 : [(int) rclass][(int) GET_MODE(src)])))
1436 : {
1437 13388319 : if (reg_class_size[rclass] == 1)
1438 13235518 : op_costs[i]->cost[k] = -frequency;
1439 152801 : else if (in_hard_reg_set_p (reg_class_contents[rclass],
1440 : GET_MODE(src), other_regno))
1441 124879 : op_costs[i]->cost[k] = -frequency;
1442 : }
1443 : }
1444 17699233 : op_costs[i]->mem_cost
1445 17699233 : = ira_memory_move_cost[mode][hard_reg_class][i] * frequency;
1446 17699233 : return;
1447 : }
1448 : }
1449 :
1450 391325621 : for (i = 0; i < recog_data.n_operands; i++)
1451 : {
1452 268632515 : constraints[i] = recog_data.constraints[i];
1453 268632515 : modes[i] = recog_data.operand_mode[i];
1454 : }
1455 :
1456 : /* If we get here, we are set up to record the costs of all the
1457 : operands for this insn. Start by initializing the costs. Then
1458 : handle any address registers. Finally record the desired classes
1459 : for any allocnos, doing it twice if some pair of operands are
1460 : commutative. */
1461 391325621 : for (i = 0; i < recog_data.n_operands; i++)
1462 : {
1463 268632515 : rtx op_mem = extract_mem_from_operand (recog_data.operand[i]);
1464 268632515 : memcpy (op_costs[i], init_cost, struct_costs_size);
1465 :
1466 268632515 : if (GET_CODE (recog_data.operand[i]) == SUBREG)
1467 5005469 : recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
1468 :
1469 268632515 : if (MEM_P (op_mem))
1470 44505932 : record_address_regs (GET_MODE (op_mem),
1471 44505932 : MEM_ADDR_SPACE (op_mem),
1472 : XEXP (op_mem, 0),
1473 : 0, MEM, SCRATCH, frequency * 2);
1474 224126583 : else if (constraints[i][0] == 'p'
1475 448249054 : || (insn_extra_address_constraint
1476 224122471 : (lookup_constraint (constraints[i]))))
1477 1161742 : record_address_regs (VOIDmode, ADDR_SPACE_GENERIC,
1478 : recog_data.operand[i], 0, ADDRESS, SCRATCH,
1479 : frequency * 2);
1480 : }
1481 :
1482 : /* Check for commutative in a separate loop so everything will have
1483 : been initialized. We must do this even if one operand is a
1484 : constant--see addsi3 in m68k.md. */
1485 269539924 : for (i = 0; i < (int) recog_data.n_operands - 1; i++)
1486 146846818 : if (constraints[i][0] == '%')
1487 : {
1488 : const char *xconstraints[MAX_RECOG_OPERANDS];
1489 : int j;
1490 :
1491 : /* Handle commutative operands by swapping the
1492 : constraints. We assume the modes are the same. */
1493 68080651 : for (j = 0; j < recog_data.n_operands; j++)
1494 51254527 : xconstraints[j] = constraints[j];
1495 :
1496 16826124 : xconstraints[i] = constraints[i+1];
1497 16826124 : xconstraints[i+1] = constraints[i];
1498 16826124 : record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1499 : recog_data.operand, modes,
1500 : xconstraints, insn, pref);
1501 : }
1502 122693106 : record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
1503 : recog_data.operand, modes,
1504 : constraints, insn, pref);
1505 : }
1506 :
1507 :
1508 :
1509 : /* Process one insn INSN. Scan it and record each time it would save
1510 : code to put a certain allocnos in a certain class. Return the last
1511 : insn processed, so that the scan can be continued from there. */
1512 : static rtx_insn *
1513 287403962 : scan_one_insn (rtx_insn *insn)
1514 : {
1515 287403962 : enum rtx_code pat_code;
1516 287403962 : rtx set, note;
1517 287403962 : int i, k;
1518 287403962 : bool counted_mem;
1519 :
1520 287403962 : if (!NONDEBUG_INSN_P (insn))
1521 : return insn;
1522 :
1523 141780027 : pat_code = GET_CODE (PATTERN (insn));
1524 141780027 : if (pat_code == ASM_INPUT)
1525 : return insn;
1526 :
1527 : /* If INSN is a USE/CLOBBER of a pseudo in a mode M then go ahead
1528 : and initialize the register move costs of mode M.
1529 :
1530 : The pseudo may be related to another pseudo via a copy (implicit or
1531 : explicit) and if there are no mode M uses/sets of the original
1532 : pseudo, then we may leave the register move costs uninitialized for
1533 : mode M. */
1534 141776193 : if (pat_code == USE || pat_code == CLOBBER)
1535 : {
1536 1383854 : rtx x = XEXP (PATTERN (insn), 0);
1537 1383854 : if (GET_CODE (x) == REG
1538 1370459 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
1539 1413901 : && have_regs_of_mode[GET_MODE (x)])
1540 30046 : ira_init_register_move_cost_if_necessary (GET_MODE (x));
1541 1383854 : return insn;
1542 : }
1543 :
1544 140392339 : counted_mem = false;
1545 140392339 : set = single_set (insn);
1546 140392339 : extract_insn (insn);
1547 :
1548 : /* If this insn loads a parameter from its stack slot, then it
1549 : represents a savings, rather than a cost, if the parameter is
1550 : stored in memory. Record this fact.
1551 :
1552 : Similarly if we're loading other constants from memory (constant
1553 : pool, TOC references, small data areas, etc) and this is the only
1554 : assignment to the destination pseudo.
1555 :
1556 : Don't do this if SET_SRC (set) isn't a general operand, if it is
1557 : a memory requiring special instructions to load it, decreasing
1558 : mem_cost might result in it being loaded using the specialized
1559 : instruction into a register, then stored into stack and loaded
1560 : again from the stack. See PR52208.
1561 :
1562 : Don't do this if SET_SRC (set) has side effect. See PR56124. */
1563 132796896 : if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set))
1564 17406983 : && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX
1565 4963160 : && ((MEM_P (XEXP (note, 0))
1566 4462387 : && !side_effects_p (SET_SRC (set)))
1567 500773 : || (CONSTANT_P (XEXP (note, 0))
1568 500765 : && targetm.legitimate_constant_p (GET_MODE (SET_DEST (set)),
1569 : XEXP (note, 0))
1570 154172 : && REG_N_SETS (REGNO (SET_DEST (set))) == 1))
1571 4616559 : && general_operand (SET_SRC (set), GET_MODE (SET_SRC (set)))
1572 : /* LRA does not use equiv with a symbol for PIC code. */
1573 145008853 : && (! ira_use_lra_p || ! pic_offset_table_rtx
1574 328684 : || ! contains_symbol_ref_p (XEXP (note, 0))))
1575 : {
1576 4559156 : enum reg_class cl = GENERAL_REGS;
1577 4559156 : rtx reg = SET_DEST (set);
1578 4559156 : int num = COST_INDEX (REGNO (reg));
1579 : /* Costs for NO_REGS are used in cost calculation on the
1580 : 1st pass when the preferred register classes are not
1581 : known yet. In this case we take the best scenario when
1582 : mode can't be put into GENERAL_REGS. */
1583 4559156 : if (!targetm.hard_regno_mode_ok (ira_class_hard_regs[cl][0],
1584 4559156 : GET_MODE (reg)))
1585 1251322 : cl = NO_REGS;
1586 :
1587 4559156 : COSTS (costs, num)->mem_cost
1588 4559156 : -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency;
1589 9118312 : record_address_regs (GET_MODE (SET_SRC (set)),
1590 9118312 : MEM_ADDR_SPACE (SET_SRC (set)),
1591 4559156 : XEXP (SET_SRC (set), 0), 0, MEM, SCRATCH,
1592 : frequency * 2);
1593 4559156 : counted_mem = true;
1594 : }
1595 :
1596 140392339 : record_operand_costs (insn, pref);
1597 :
1598 140392339 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1599 : {
1600 0 : const char *p;
1601 0 : fprintf (ira_dump_file, " Final costs after insn %u", INSN_UID (insn));
1602 0 : if (INSN_CODE (insn) >= 0
1603 0 : && (p = get_insn_name (INSN_CODE (insn))) != NULL)
1604 0 : fprintf (ira_dump_file, " {%s}", p);
1605 0 : fprintf (ira_dump_file, " (freq=%d)\n",
1606 0 : REG_FREQ_FROM_BB (BLOCK_FOR_INSN (insn)));
1607 0 : dump_insn_slim (ira_dump_file, insn);
1608 : }
1609 :
1610 : /* Now add the cost for each operand to the total costs for its
1611 : allocno. */
1612 444423320 : for (i = 0; i < recog_data.n_operands; i++)
1613 : {
1614 304030981 : rtx op = recog_data.operand[i];
1615 :
1616 304030981 : if (GET_CODE (op) == SUBREG)
1617 33173 : op = SUBREG_REG (op);
1618 304030981 : if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1619 : {
1620 123871533 : int regno = REGNO (op);
1621 123871533 : struct costs *p = COSTS (costs, COST_INDEX (regno));
1622 123871533 : struct costs *q = op_costs[i];
1623 123871533 : int *p_costs = p->cost, *q_costs = q->cost;
1624 123871533 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1625 123871533 : int add_cost = 0;
1626 :
1627 : /* If the already accounted for the memory "cost" above, don't
1628 : do so again. */
1629 123871533 : if (!counted_mem)
1630 : {
1631 119312377 : add_cost = q->mem_cost;
1632 119312377 : if (add_cost > 0 && INT_MAX - add_cost < p->mem_cost)
1633 0 : p->mem_cost = INT_MAX;
1634 : else
1635 119312377 : p->mem_cost += add_cost;
1636 : }
1637 123871533 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1638 : {
1639 0 : fprintf (ira_dump_file, " op %d(r=%u) MEM:%d(+%d)",
1640 : i, REGNO(op), p->mem_cost, add_cost);
1641 : }
1642 1839231583 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
1643 : {
1644 1715360050 : add_cost = q_costs[k];
1645 1715360050 : if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
1646 0 : p_costs[k] = INT_MAX;
1647 : else
1648 1715360050 : p_costs[k] += add_cost;
1649 1715360050 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1650 : {
1651 0 : fprintf (ira_dump_file, " %s:%d(+%d)",
1652 0 : reg_class_names[cost_classes_ptr->classes[k]],
1653 0 : p_costs[k], add_cost);
1654 : }
1655 : }
1656 123871533 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
1657 0 : fprintf (ira_dump_file, "\n");
1658 : }
1659 : }
1660 : return insn;
1661 : }
1662 :
1663 :
1664 :
1665 : /* Print allocnos costs to the dump file. */
1666 : static void
1667 127 : print_allocno_costs (void)
1668 : {
1669 127 : int k;
1670 127 : ira_allocno_t a;
1671 127 : ira_allocno_iterator ai;
1672 :
1673 127 : ira_assert (allocno_p);
1674 127 : fprintf (ira_dump_file, "\n");
1675 1341 : FOR_EACH_ALLOCNO (a, ai)
1676 : {
1677 1214 : int i, rclass;
1678 1214 : basic_block bb;
1679 1214 : int regno = ALLOCNO_REGNO (a);
1680 1214 : cost_classes_t cost_classes_ptr = regno_cost_classes[regno];
1681 1214 : enum reg_class *cost_classes = cost_classes_ptr->classes;
1682 :
1683 1214 : i = ALLOCNO_NUM (a);
1684 1214 : fprintf (ira_dump_file, " a%d(r%d,", i, regno);
1685 1214 : if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
1686 0 : fprintf (ira_dump_file, "b%d", bb->index);
1687 : else
1688 1214 : fprintf (ira_dump_file, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
1689 1214 : fprintf (ira_dump_file, ") costs:");
1690 19725 : for (k = 0; k < cost_classes_ptr->num; k++)
1691 : {
1692 17297 : rclass = cost_classes[k];
1693 17297 : fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass],
1694 17297 : COSTS (costs, i)->cost[k]);
1695 17297 : if (flag_ira_region == IRA_REGION_ALL
1696 17297 : || flag_ira_region == IRA_REGION_MIXED)
1697 13698 : fprintf (ira_dump_file, ",%d",
1698 13698 : COSTS (total_allocno_costs, i)->cost[k]);
1699 : }
1700 1214 : fprintf (ira_dump_file, " MEM:%i", COSTS (costs, i)->mem_cost);
1701 1214 : if (flag_ira_region == IRA_REGION_ALL
1702 1214 : || flag_ira_region == IRA_REGION_MIXED)
1703 1004 : fprintf (ira_dump_file, ",%d",
1704 1004 : COSTS (total_allocno_costs, i)->mem_cost);
1705 1214 : fprintf (ira_dump_file, "\n");
1706 : }
1707 127 : }
1708 :
1709 : /* Print pseudo costs to the dump file. */
1710 : static void
1711 16 : print_pseudo_costs (void)
1712 : {
1713 16 : int regno, k;
1714 16 : int rclass;
1715 16 : cost_classes_t cost_classes_ptr;
1716 16 : enum reg_class *cost_classes;
1717 :
1718 16 : ira_assert (! allocno_p);
1719 16 : fprintf (ira_dump_file, "\n");
1720 764 : for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1721 : {
1722 748 : if (REG_N_REFS (regno) <= 0)
1723 444 : continue;
1724 304 : cost_classes_ptr = regno_cost_classes[regno];
1725 304 : cost_classes = cost_classes_ptr->classes;
1726 304 : fprintf (ira_dump_file, " r%d costs:", regno);
1727 5904 : for (k = 0; k < cost_classes_ptr->num; k++)
1728 : {
1729 5296 : rclass = cost_classes[k];
1730 5296 : fprintf (ira_dump_file, " %s:%d", reg_class_names[rclass],
1731 5296 : COSTS (costs, regno)->cost[k]);
1732 : }
1733 304 : fprintf (ira_dump_file, " MEM:%i\n", COSTS (costs, regno)->mem_cost);
1734 : }
1735 16 : }
1736 :
1737 : /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1738 : costs. */
1739 : static void
1740 25510195 : process_bb_for_costs (basic_block bb)
1741 : {
1742 25510195 : rtx_insn *insn;
1743 :
1744 25510195 : frequency = REG_FREQ_FROM_BB (bb);
1745 25510195 : if (frequency == 0)
1746 0 : frequency = 1;
1747 312914157 : FOR_BB_INSNS (bb, insn)
1748 287403962 : insn = scan_one_insn (insn);
1749 25510195 : }
1750 :
1751 : /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1752 : costs. */
1753 : static void
1754 28452746 : process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node)
1755 : {
1756 28452746 : basic_block bb;
1757 :
1758 28452746 : bb = loop_tree_node->bb;
1759 28452746 : if (bb != NULL)
1760 24825387 : process_bb_for_costs (bb);
1761 28452746 : }
1762 :
1763 : /* Return true if all autoinc rtx in X change only a register and memory is
1764 : valid. */
1765 : static bool
1766 53529556 : validate_autoinc_and_mem_addr_p (rtx x)
1767 : {
1768 53529556 : enum rtx_code code = GET_CODE (x);
1769 53529556 : if (GET_RTX_CLASS (code) == RTX_AUTOINC)
1770 382550 : return REG_P (XEXP (x, 0));
1771 53147006 : const char *fmt = GET_RTX_FORMAT (code);
1772 131962708 : for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1773 80149852 : if (fmt[i] == 'e')
1774 : {
1775 43639711 : if (!validate_autoinc_and_mem_addr_p (XEXP (x, i)))
1776 : return false;
1777 : }
1778 36510141 : else if (fmt[i] == 'E')
1779 : {
1780 2905121 : for (int j = 0; j < XVECLEN (x, i); j++)
1781 1961082 : if (!validate_autoinc_and_mem_addr_p (XVECEXP (x, i, j)))
1782 : return false;
1783 : }
1784 : /* Check memory after checking autoinc to guarantee that autoinc is already
1785 : valid for machine-dependent code checking memory address. */
1786 51812856 : return (!MEM_P (x)
1787 110752490 : || memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
1788 8251162 : MEM_ADDR_SPACE (x)));
1789 : }
1790 :
1791 : /* Check that reg REGNO in INSN can be changed by TO (which is an invariant
1792 : equiv when INVARIANT_P is true). Return true in case the result insn would
1793 : be valid one. */
1794 : static bool
1795 7928763 : equiv_can_be_consumed_p (int regno, rtx to, rtx_insn *insn, bool invariant_p)
1796 : {
1797 7928763 : validate_replace_src_group (regno_reg_rtx[regno], to, insn);
1798 : /* We can change register to equivalent memory in autoinc rtl. Some code
1799 : including verify_changes assumes that autoinc contains only a register.
1800 : So check this first. */
1801 7928763 : bool res = validate_autoinc_and_mem_addr_p (PATTERN (insn));
1802 7928763 : if (res)
1803 6804379 : res = verify_changes (0);
1804 7928763 : cancel_changes (0);
1805 7928763 : if (!res && invariant_p)
1806 : {
1807 : /* Here we use more expensive code for the invariant because we need to
1808 : simplify the result insn as the invariant can be arithmetic rtx
1809 : inserted into another arithmetic rtx, e.g. into memory address. */
1810 580542 : rtx pat = PATTERN (insn);
1811 580542 : int code = INSN_CODE (insn);
1812 580542 : PATTERN (insn) = copy_rtx (pat);
1813 1161084 : PATTERN (insn)
1814 580542 : = simplify_replace_rtx (PATTERN (insn), regno_reg_rtx[regno], to);
1815 580542 : res = !insn_invalid_p (insn, false);
1816 580542 : PATTERN (insn) = pat;
1817 580542 : INSN_CODE (insn) = code;
1818 : }
1819 7928763 : return res;
1820 : }
1821 :
1822 : /* Return true if X contains a pseudo with equivalence. In this case also
1823 : return the pseudo through parameter REG. If the pseudo is a part of subreg,
1824 : return the subreg through parameter SUBREG. */
1825 :
1826 : static bool
1827 275371537 : get_equiv_regno (rtx x, int ®no, rtx &subreg)
1828 : {
1829 275371537 : subreg = NULL_RTX;
1830 275371537 : if (GET_CODE (x) == SUBREG)
1831 : {
1832 2118393 : subreg = x;
1833 2118393 : x = SUBREG_REG (x);
1834 : }
1835 275371537 : if (REG_P (x)
1836 275371537 : && (ira_reg_equiv[REGNO (x)].memory != NULL
1837 82431103 : || ira_reg_equiv[REGNO (x)].invariant != NULL
1838 80090395 : || ira_reg_equiv[REGNO (x)].constant != NULL))
1839 : {
1840 10368866 : regno = REGNO (x);
1841 10368866 : return true;
1842 : }
1843 265002671 : RTX_CODE code = GET_CODE (x);
1844 265002671 : const char *fmt = GET_RTX_FORMAT (code);
1845 :
1846 619209975 : for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1847 369418002 : if (fmt[i] == 'e')
1848 : {
1849 204044953 : if (get_equiv_regno (XEXP (x, i), regno, subreg))
1850 : return true;
1851 : }
1852 165373049 : else if (fmt[i] == 'E')
1853 : {
1854 23791463 : for (int j = 0; j < XVECLEN (x, i); j++)
1855 16552528 : if (get_equiv_regno (XVECEXP (x, i, j), regno, subreg))
1856 : return true;
1857 : }
1858 : return false;
1859 : }
1860 :
1861 : /* A pass through the current function insns. Calculate costs of using
1862 : equivalences for pseudos and store them in regno_equiv_gains. */
1863 :
1864 : static void
1865 963944 : calculate_equiv_gains (void)
1866 : {
1867 963944 : basic_block bb;
1868 963944 : int regno, freq, cost;
1869 963944 : rtx subreg;
1870 963944 : rtx_insn *insn;
1871 963944 : machine_mode mode;
1872 963944 : enum reg_class rclass;
1873 963944 : bitmap_head equiv_pseudos;
1874 :
1875 963944 : ira_assert (allocno_p);
1876 963944 : bitmap_initialize (&equiv_pseudos, ®_obstack);
1877 48050536 : for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--)
1878 47086592 : if (ira_reg_equiv[regno].init_insns != NULL
1879 4215503 : && (ira_reg_equiv[regno].memory != NULL
1880 1448419 : || ira_reg_equiv[regno].invariant != NULL
1881 643554 : || (ira_reg_equiv[regno].constant != NULL
1882 : /* Ignore complicated constants which probably will be placed
1883 : in memory: */
1884 643554 : && GET_CODE (ira_reg_equiv[regno].constant) != CONST_DOUBLE
1885 : && GET_CODE (ira_reg_equiv[regno].constant) != CONST_VECTOR
1886 : && GET_CODE (ira_reg_equiv[regno].constant) != LABEL_REF)))
1887 : {
1888 : rtx_insn_list *x;
1889 7588681 : for (x = ira_reg_equiv[regno].init_insns; x != NULL; x = x->next ())
1890 : {
1891 4049095 : insn = x->insn ();
1892 4049095 : rtx set = single_set (insn);
1893 :
1894 4049095 : if (set == NULL_RTX || SET_DEST (set) != regno_reg_rtx[regno])
1895 : break;
1896 3539586 : bb = BLOCK_FOR_INSN (insn);
1897 3539586 : ira_curr_regno_allocno_map
1898 3539586 : = ira_bb_nodes[bb->index].parent->regno_allocno_map;
1899 3539586 : mode = PSEUDO_REGNO_MODE (regno);
1900 3539586 : rclass = pref[COST_INDEX (regno)];
1901 3539586 : ira_init_register_move_cost_if_necessary (mode);
1902 3539586 : if (ira_reg_equiv[regno].memory != NULL)
1903 2257575 : cost = ira_memory_move_cost[mode][rclass][1];
1904 : else
1905 1282011 : cost = ira_register_move_cost[mode][rclass][rclass];
1906 3539586 : freq = REG_FREQ_FROM_BB (bb);
1907 3539586 : regno_equiv_gains[regno] += cost * freq;
1908 : }
1909 4049095 : if (x != NULL)
1910 : /* We found complicated equiv or reverse equiv mem=reg. Ignore
1911 : them. */
1912 509509 : regno_equiv_gains[regno] = 0;
1913 : else
1914 3539586 : bitmap_set_bit (&equiv_pseudos, regno);
1915 : }
1916 :
1917 11385684 : FOR_EACH_BB_FN (bb, cfun)
1918 : {
1919 10421740 : freq = REG_FREQ_FROM_BB (bb);
1920 10421740 : ira_curr_regno_allocno_map
1921 10421740 : = ira_bb_nodes[bb->index].parent->regno_allocno_map;
1922 134029379 : FOR_BB_INSNS (bb, insn)
1923 : {
1924 238481731 : if (!NONDEBUG_INSN_P (insn)
1925 54774056 : || !get_equiv_regno (PATTERN (insn), regno, subreg)
1926 133976505 : || !bitmap_bit_p (&equiv_pseudos, regno))
1927 114874092 : continue;
1928 :
1929 8733547 : if (ira_reg_equiv[regno].invariant != NULL)
1930 : {
1931 2340708 : rtx_insn_list *x = ira_reg_equiv[regno].init_insns;
1932 3876632 : for (; x != NULL; x = x->next ())
1933 2340708 : if (insn == x->insn ())
1934 : break;
1935 2340708 : if (x != NULL)
1936 804784 : continue; /* skip equiv init insn for invariant */
1937 : }
1938 :
1939 7928763 : rtx subst = ira_reg_equiv[regno].memory;
1940 :
1941 7928763 : if (subst == NULL)
1942 2590188 : subst = ira_reg_equiv[regno].constant;
1943 2590188 : if (subst == NULL)
1944 1535924 : subst = ira_reg_equiv[regno].invariant;
1945 1535924 : ira_assert (subst != NULL);
1946 7928763 : mode = PSEUDO_REGNO_MODE (regno);
1947 7928763 : ira_init_register_move_cost_if_necessary (mode);
1948 7928763 : bool consumed_p
1949 15857526 : = equiv_can_be_consumed_p (regno, subst, insn,
1950 7928763 : subst == ira_reg_equiv[regno].invariant);
1951 :
1952 7928763 : rclass = pref[COST_INDEX (regno)];
1953 7928763 : if (MEM_P (subst)
1954 : /* If it is a change of constant into double for example, the
1955 : result constant probably will be placed in memory. */
1956 2590188 : || (ira_reg_equiv[regno].invariant == NULL
1957 1054264 : && subreg != NULL_RTX
1958 1147 : && !INTEGRAL_MODE_P (GET_MODE (subreg))))
1959 8021057 : cost = ira_memory_move_cost[mode][rclass][1] + (consumed_p ? 0 : 1);
1960 2590127 : else if (consumed_p)
1961 1529368 : continue;
1962 : else
1963 1060759 : cost = ira_register_move_cost[mode][rclass][rclass];
1964 6399395 : regno_equiv_gains[regno] -= cost * freq;
1965 : }
1966 : }
1967 963944 : bitmap_clear (&equiv_pseudos);
1968 963944 : }
1969 :
1970 : /* Find costs of register classes and memory for allocnos or pseudos
1971 : and their best costs. Set up preferred, alternative and allocno
1972 : classes for pseudos. */
1973 : static void
1974 1500820 : find_costs_and_classes (void)
1975 : {
1976 1500820 : int i, k, start, max_cost_classes_num;
1977 1500820 : int pass;
1978 1500820 : basic_block bb;
1979 1500820 : enum reg_class *regno_best_class, new_class;
1980 :
1981 1500820 : init_recog ();
1982 1500820 : regno_best_class
1983 1500820 : = (enum reg_class *) ira_allocate (max_reg_num ()
1984 : * sizeof (enum reg_class));
1985 68417866 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
1986 66917046 : regno_best_class[i] = NO_REGS;
1987 2972225 : if (!resize_reg_info () && allocno_p
1988 2972182 : && pseudo_classes_defined_p && flag_expensive_optimizations)
1989 : {
1990 48 : ira_allocno_t a;
1991 48 : ira_allocno_iterator ai;
1992 :
1993 48 : pref = pref_buffer;
1994 48 : max_cost_classes_num = 1;
1995 1559 : FOR_EACH_ALLOCNO (a, ai)
1996 : {
1997 1511 : pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a));
1998 1511 : setup_regno_cost_classes_by_aclass
1999 1511 : (ALLOCNO_REGNO (a), pref[ALLOCNO_NUM (a)]);
2000 1511 : max_cost_classes_num
2001 1511 : = MAX (max_cost_classes_num,
2002 : regno_cost_classes[ALLOCNO_REGNO (a)]->num);
2003 : }
2004 48 : start = 1;
2005 : }
2006 : else
2007 : {
2008 1500772 : pref = NULL;
2009 1500772 : max_cost_classes_num = ira_important_classes_num;
2010 68415155 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2011 66914383 : if (regno_reg_rtx[i] != NULL_RTX)
2012 66617587 : setup_regno_cost_classes_by_mode (i, PSEUDO_REGNO_MODE (i));
2013 : else
2014 296796 : setup_regno_cost_classes_by_aclass (i, ALL_REGS);
2015 : start = 0;
2016 : }
2017 1500820 : if (allocno_p)
2018 : /* Clear the flag for the next compiled function. */
2019 1471362 : pseudo_classes_defined_p = false;
2020 : /* Normally we scan the insns once and determine the best class to
2021 : use for each allocno. However, if -fexpensive-optimizations are
2022 : on, we do so twice, the second time using the tentative best
2023 : classes to guide the selection. */
2024 3994942 : for (pass = start; pass <= flag_expensive_optimizations; pass++)
2025 : {
2026 2494122 : if ((!allocno_p || internal_flag_ira_verbose > 0) && ira_dump_file)
2027 143 : fprintf (ira_dump_file,
2028 : "\nPass %i for finding pseudo/allocno costs\n\n", pass);
2029 :
2030 2494122 : if (pass != start)
2031 : {
2032 993302 : max_cost_classes_num = 1;
2033 49493749 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2034 : {
2035 48500447 : setup_regno_cost_classes_by_aclass (i, regno_best_class[i]);
2036 48500447 : max_cost_classes_num
2037 48500447 : = MAX (max_cost_classes_num, regno_cost_classes[i]->num);
2038 : }
2039 : }
2040 :
2041 2494122 : struct_costs_size
2042 2494122 : = sizeof (struct costs) + sizeof (int) * (max_cost_classes_num - 1);
2043 : /* Zero out our accumulation of the cost of each class for each
2044 : allocno. */
2045 2494122 : memset (costs, 0, cost_elements_num * struct_costs_size);
2046 :
2047 2494122 : if (allocno_p)
2048 : {
2049 : /* Scan the instructions and record each time it would save code
2050 : to put a certain allocno in a certain class. */
2051 2435258 : ira_traverse_loop_tree (true, ira_loop_tree_root,
2052 : process_bb_node_for_costs, NULL);
2053 :
2054 2435258 : memcpy (total_allocno_costs, costs,
2055 2435258 : max_struct_costs_size * ira_allocnos_num);
2056 : }
2057 : else
2058 : {
2059 58864 : basic_block bb;
2060 :
2061 743672 : FOR_EACH_BB_FN (bb, cfun)
2062 684808 : process_bb_for_costs (bb);
2063 : }
2064 :
2065 2494122 : if (pass == 0)
2066 1500772 : pref = pref_buffer;
2067 :
2068 2494122 : if (ira_use_lra_p && allocno_p && pass == 1)
2069 : /* It is a pass through all insns. So do it once and only for RA (not
2070 : for insn scheduler) when we already found preferable pseudo register
2071 : classes on the previous pass. */
2072 963944 : calculate_equiv_gains ();
2073 :
2074 : /* Now for each allocno look at how desirable each class is and
2075 : find which class is preferred. */
2076 117911615 : for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--)
2077 : {
2078 115417493 : ira_allocno_t a, parent_a;
2079 115417493 : int rclass, a_num, parent_a_num, add_cost;
2080 115417493 : ira_loop_tree_node_t parent;
2081 115417493 : int best_cost, allocno_cost;
2082 115417493 : enum reg_class best, alt_class;
2083 115417493 : cost_classes_t cost_classes_ptr = regno_cost_classes[i];
2084 115417493 : enum reg_class *cost_classes;
2085 115417493 : int *i_costs = temp_costs->cost;
2086 115417493 : int i_mem_cost;
2087 115417493 : int equiv_savings = regno_equiv_gains[i];
2088 :
2089 115417493 : if (! allocno_p)
2090 : {
2091 2834642 : if (regno_reg_rtx[i] == NULL_RTX)
2092 4606 : continue;
2093 2830036 : memcpy (temp_costs, COSTS (costs, i), struct_costs_size);
2094 2830036 : i_mem_cost = temp_costs->mem_cost;
2095 2830036 : cost_classes = cost_classes_ptr->classes;
2096 : }
2097 : else
2098 : {
2099 112582851 : if (ira_regno_allocno_map[i] == NULL)
2100 66005711 : continue;
2101 46577140 : memset (temp_costs, 0, struct_costs_size);
2102 46577140 : i_mem_cost = 0;
2103 46577140 : cost_classes = cost_classes_ptr->classes;
2104 : /* Find cost of all allocnos with the same regno. */
2105 46577140 : for (a = ira_regno_allocno_map[i];
2106 104023724 : a != NULL;
2107 57446584 : a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2108 : {
2109 57446584 : int *a_costs, *p_costs;
2110 :
2111 57446584 : a_num = ALLOCNO_NUM (a);
2112 57446584 : if ((flag_ira_region == IRA_REGION_ALL
2113 57446584 : || flag_ira_region == IRA_REGION_MIXED)
2114 45017482 : && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL
2115 17728137 : && (parent_a = parent->regno_allocno_map[i]) != NULL
2116 : /* There are no caps yet. */
2117 68315541 : && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
2118 10868957 : (a)->border_allocnos,
2119 : ALLOCNO_NUM (a)))
2120 : {
2121 : /* Propagate costs to upper levels in the region
2122 : tree. */
2123 10862309 : parent_a_num = ALLOCNO_NUM (parent_a);
2124 10862309 : a_costs = COSTS (total_allocno_costs, a_num)->cost;
2125 10862309 : p_costs = COSTS (total_allocno_costs, parent_a_num)->cost;
2126 157437433 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2127 : {
2128 146575124 : add_cost = a_costs[k];
2129 146575124 : if (add_cost > 0 && INT_MAX - add_cost < p_costs[k])
2130 0 : p_costs[k] = INT_MAX;
2131 : else
2132 146575124 : p_costs[k] += add_cost;
2133 : }
2134 10862309 : add_cost = COSTS (total_allocno_costs, a_num)->mem_cost;
2135 10862309 : if (add_cost > 0
2136 5177173 : && (INT_MAX - add_cost
2137 : < COSTS (total_allocno_costs,
2138 5177173 : parent_a_num)->mem_cost))
2139 0 : COSTS (total_allocno_costs, parent_a_num)->mem_cost
2140 0 : = INT_MAX;
2141 : else
2142 10862309 : COSTS (total_allocno_costs, parent_a_num)->mem_cost
2143 10862309 : += add_cost;
2144 :
2145 10862309 : if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2146 0 : COSTS (total_allocno_costs, parent_a_num)->mem_cost = 0;
2147 : }
2148 57446584 : a_costs = COSTS (costs, a_num)->cost;
2149 853028523 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2150 : {
2151 795581939 : add_cost = a_costs[k];
2152 795581939 : if (add_cost > 0 && INT_MAX - add_cost < i_costs[k])
2153 0 : i_costs[k] = INT_MAX;
2154 : else
2155 795581939 : i_costs[k] += add_cost;
2156 : }
2157 57446584 : add_cost = COSTS (costs, a_num)->mem_cost;
2158 57446584 : if (add_cost > 0 && INT_MAX - add_cost < i_mem_cost)
2159 : i_mem_cost = INT_MAX;
2160 : else
2161 57446584 : i_mem_cost += add_cost;
2162 : }
2163 : }
2164 49407176 : if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
2165 : i_mem_cost = 0;
2166 49379034 : else if (ira_use_lra_p)
2167 : {
2168 49379034 : if (equiv_savings > 0)
2169 : {
2170 509793 : i_mem_cost = 0;
2171 509793 : if (ira_dump_file != NULL && internal_flag_ira_verbose > 5)
2172 0 : fprintf (ira_dump_file,
2173 : " Use MEM for r%d as the equiv savings is %d\n",
2174 : i, equiv_savings);
2175 : }
2176 : }
2177 0 : else if (equiv_savings < 0)
2178 0 : i_mem_cost = -equiv_savings;
2179 0 : else if (equiv_savings > 0)
2180 : {
2181 0 : i_mem_cost = 0;
2182 0 : for (k = cost_classes_ptr->num - 1; k >= 0; k--)
2183 0 : i_costs[k] += equiv_savings;
2184 : }
2185 :
2186 49407176 : best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2187 49407176 : best = ALL_REGS;
2188 49407176 : alt_class = NO_REGS;
2189 : /* Find best common class for all allocnos with the same
2190 : regno. */
2191 746693830 : for (k = 0; k < cost_classes_ptr->num; k++)
2192 : {
2193 697286654 : rclass = cost_classes[k];
2194 697286654 : if (i_costs[k] < best_cost)
2195 : {
2196 : best_cost = i_costs[k];
2197 : best = (enum reg_class) rclass;
2198 : }
2199 636662118 : else if (i_costs[k] == best_cost)
2200 302424769 : best = ira_reg_class_subunion[best][rclass];
2201 697286654 : if (pass == flag_expensive_optimizations
2202 : /* We still prefer registers to memory even at this
2203 : stage if their costs are the same. We will make
2204 : a final decision during assigning hard registers
2205 : when we have all info including more accurate
2206 : costs which might be affected by assigning hard
2207 : registers to other pseudos because the pseudos
2208 : involved in moves can be coalesced. */
2209 398515744 : && i_costs[k] <= i_mem_cost
2210 275108644 : && (reg_class_size[reg_class_subunion[alt_class][rclass]]
2211 275108644 : > reg_class_size[alt_class]))
2212 697286654 : alt_class = reg_class_subunion[alt_class][rclass];
2213 : }
2214 49407176 : alt_class = ira_allocno_class_translate[alt_class];
2215 49407176 : if (best_cost > i_mem_cost
2216 49407176 : && ! non_spilled_static_chain_regno_p (i))
2217 772717 : regno_aclass[i] = NO_REGS;
2218 48634459 : else if (!optimize && !targetm.class_likely_spilled_p (best))
2219 : /* Registers in the alternative class are likely to need
2220 : longer or slower sequences than registers in the best class.
2221 : When optimizing we make some effort to use the best class
2222 : over the alternative class where possible, but at -O0 we
2223 : effectively give the alternative class equal weight.
2224 : We then run the risk of using slower alternative registers
2225 : when plenty of registers from the best class are still free.
2226 : This is especially true because live ranges tend to be very
2227 : short in -O0 code and so register pressure tends to be low.
2228 :
2229 : Avoid that by ignoring the alternative class if the best
2230 : class has plenty of registers.
2231 :
2232 : The union class arrays give important classes and only
2233 : part of it are allocno classes. So translate them into
2234 : allocno classes. */
2235 9477307 : regno_aclass[i] = ira_allocno_class_translate[best];
2236 : else
2237 : {
2238 : /* Make the common class the biggest class of best and
2239 : alt_class. Translate the common class into an
2240 : allocno class too. */
2241 39157152 : regno_aclass[i] = (ira_allocno_class_translate
2242 39157152 : [ira_reg_class_superunion[best][alt_class]]);
2243 39157152 : ira_assert (regno_aclass[i] != NO_REGS
2244 : && ira_reg_allocno_class_p[regno_aclass[i]]);
2245 : }
2246 49407176 : if (pic_offset_table_rtx != NULL
2247 49407176 : && i == (int) REGNO (pic_offset_table_rtx))
2248 : {
2249 : /* For some targets, integer pseudos can be assigned to fp
2250 : regs. As we don't want reload pic offset table pseudo, we
2251 : should avoid using non-integer regs. */
2252 81699 : regno_aclass[i]
2253 81699 : = ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS];
2254 81699 : alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS];
2255 : }
2256 98814352 : if ((new_class
2257 98814352 : = (reg_class) (targetm.ira_change_pseudo_allocno_class
2258 49407176 : (i, regno_aclass[i], best))) != regno_aclass[i])
2259 : {
2260 0 : regno_aclass[i] = new_class;
2261 0 : if (hard_reg_set_subset_p (reg_class_contents[new_class],
2262 0 : reg_class_contents[best]))
2263 0 : best = new_class;
2264 0 : if (hard_reg_set_subset_p (reg_class_contents[new_class],
2265 0 : reg_class_contents[alt_class]))
2266 0 : alt_class = new_class;
2267 : }
2268 49407176 : if (pass == flag_expensive_optimizations)
2269 : {
2270 31024899 : if (best_cost > i_mem_cost
2271 : /* Do not assign NO_REGS to static chain pointer
2272 : pseudo when non-local goto is used. */
2273 31024899 : && ! non_spilled_static_chain_regno_p (i))
2274 : best = alt_class = NO_REGS;
2275 30538484 : else if (best == alt_class)
2276 21507523 : alt_class = NO_REGS;
2277 31024899 : setup_reg_classes (i, best, alt_class, regno_aclass[i]);
2278 31024899 : if ((!allocno_p || internal_flag_ira_verbose > 2)
2279 31024899 : && ira_dump_file != NULL)
2280 969 : fprintf (ira_dump_file,
2281 : " r%d: preferred %s, alternative %s, allocno %s\n",
2282 969 : i, reg_class_names[best], reg_class_names[alt_class],
2283 969 : reg_class_names[regno_aclass[i]]);
2284 : }
2285 49407176 : regno_best_class[i] = best;
2286 49407176 : if (! allocno_p)
2287 : {
2288 5660072 : pref[i] = (best_cost > i_mem_cost
2289 2793 : && ! non_spilled_static_chain_regno_p (i)
2290 2830036 : ? NO_REGS : best);
2291 2830036 : continue;
2292 : }
2293 46577140 : for (a = ira_regno_allocno_map[i];
2294 104023724 : a != NULL;
2295 57446584 : a = ALLOCNO_NEXT_REGNO_ALLOCNO (a))
2296 : {
2297 57446584 : enum reg_class aclass = regno_aclass[i];
2298 57446584 : int a_num = ALLOCNO_NUM (a);
2299 57446584 : int *total_a_costs = COSTS (total_allocno_costs, a_num)->cost;
2300 57446584 : int *a_costs = COSTS (costs, a_num)->cost;
2301 :
2302 57446584 : if (aclass == NO_REGS)
2303 : best = NO_REGS;
2304 : else
2305 : {
2306 : /* Finding best class which is subset of the common
2307 : class. */
2308 : best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
2309 : allocno_cost = best_cost;
2310 : best = ALL_REGS;
2311 839285844 : for (k = 0; k < cost_classes_ptr->num; k++)
2312 : {
2313 782832241 : rclass = cost_classes[k];
2314 782832241 : if (! ira_class_subset_p[rclass][aclass])
2315 375369998 : continue;
2316 407462243 : if (total_a_costs[k] < best_cost)
2317 : {
2318 61155263 : best_cost = total_a_costs[k];
2319 61155263 : allocno_cost = a_costs[k];
2320 61155263 : best = (enum reg_class) rclass;
2321 : }
2322 346306980 : else if (total_a_costs[k] == best_cost)
2323 : {
2324 284209041 : best = ira_reg_class_subunion[best][rclass];
2325 284209041 : allocno_cost = MAX (allocno_cost, a_costs[k]);
2326 : }
2327 : }
2328 56453603 : ALLOCNO_CLASS_COST (a) = allocno_cost;
2329 : }
2330 57446584 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL
2331 1214 : && (pass == 0 || pref[a_num] != best))
2332 : {
2333 777 : fprintf (ira_dump_file, " a%d (r%d,", a_num, i);
2334 777 : if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL)
2335 0 : fprintf (ira_dump_file, "b%d", bb->index);
2336 : else
2337 777 : fprintf (ira_dump_file, "l%d",
2338 : ALLOCNO_LOOP_TREE_NODE (a)->loop_num);
2339 777 : fprintf (ira_dump_file, ") best %s, allocno %s\n",
2340 777 : reg_class_names[best],
2341 777 : reg_class_names[aclass]);
2342 : }
2343 57446584 : pref[a_num] = best;
2344 57446584 : if (pass == flag_expensive_optimizations && best != aclass
2345 7477018 : && ira_class_hard_regs_num[best] > 0
2346 7477018 : && (ira_reg_class_max_nregs[best][ALLOCNO_MODE (a)]
2347 : >= ira_class_hard_regs_num[best]))
2348 : {
2349 6767404 : int ind = cost_classes_ptr->index[aclass];
2350 :
2351 6767404 : ira_assert (ind >= 0);
2352 6767404 : ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a));
2353 6767404 : ira_add_allocno_pref (a, ira_class_hard_regs[best][0],
2354 6767404 : (a_costs[ind] - ALLOCNO_CLASS_COST (a))
2355 : / (ira_register_move_cost
2356 6767404 : [ALLOCNO_MODE (a)][best][aclass]));
2357 134397208 : for (k = 0; k < cost_classes_ptr->num; k++)
2358 120862400 : if (ira_class_subset_p[cost_classes[k]][best])
2359 6767404 : a_costs[k] = a_costs[ind];
2360 : }
2361 : }
2362 : }
2363 :
2364 2494122 : if (internal_flag_ira_verbose > 4 && ira_dump_file)
2365 : {
2366 143 : if (allocno_p)
2367 127 : print_allocno_costs ();
2368 : else
2369 16 : print_pseudo_costs ();
2370 143 : fprintf (ira_dump_file,"\n");
2371 : }
2372 : }
2373 1500820 : ira_free (regno_best_class);
2374 1500820 : }
2375 :
2376 :
2377 :
2378 : /* Process moves involving hard regs to modify allocno hard register
2379 : costs. We can do this only after determining allocno class. If a
2380 : hard register forms a register class, then moves with the hard
2381 : register are already taken into account in class costs for the
2382 : allocno. */
2383 : static void
2384 12669981 : process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node)
2385 : {
2386 12669981 : int i, freq, src_regno, dst_regno, hard_regno, a_regno;
2387 12669981 : bool to_p;
2388 12669981 : ira_allocno_t a, curr_a;
2389 12669981 : ira_loop_tree_node_t curr_loop_tree_node;
2390 12669981 : enum reg_class rclass;
2391 12669981 : basic_block bb;
2392 12669981 : rtx_insn *insn;
2393 12669981 : rtx set, src, dst;
2394 :
2395 12669981 : bb = loop_tree_node->bb;
2396 12669981 : if (bb == NULL)
2397 : return;
2398 11008286 : freq = REG_FREQ_FROM_BB (bb);
2399 8628267 : if (freq == 0)
2400 2008088 : freq = 1;
2401 139707221 : FOR_BB_INSNS (bb, insn)
2402 : {
2403 128698935 : if (!NONDEBUG_INSN_P (insn))
2404 70164376 : continue;
2405 58534559 : set = single_set (insn);
2406 58534559 : if (set == NULL_RTX)
2407 3845328 : continue;
2408 54689231 : dst = SET_DEST (set);
2409 54689231 : src = SET_SRC (set);
2410 54689231 : if (! REG_P (dst) || ! REG_P (src))
2411 45568380 : continue;
2412 9120851 : dst_regno = REGNO (dst);
2413 9120851 : src_regno = REGNO (src);
2414 9120851 : if (dst_regno >= FIRST_PSEUDO_REGISTER
2415 9120851 : && src_regno < FIRST_PSEUDO_REGISTER)
2416 : {
2417 2992746 : hard_regno = src_regno;
2418 2992746 : a = ira_curr_regno_allocno_map[dst_regno];
2419 2992746 : to_p = true;
2420 : }
2421 7508572 : else if (src_regno >= FIRST_PSEUDO_REGISTER
2422 6128105 : && dst_regno < FIRST_PSEUDO_REGISTER)
2423 : {
2424 4747638 : hard_regno = dst_regno;
2425 4747638 : a = ira_curr_regno_allocno_map[src_regno];
2426 4747638 : to_p = false;
2427 : }
2428 : else
2429 1380467 : continue;
2430 15002497 : if (reg_class_size[(int) REGNO_REG_CLASS (hard_regno)]
2431 : == (ira_reg_class_max_nregs
2432 7740384 : [REGNO_REG_CLASS (hard_regno)][(int) ALLOCNO_MODE(a)]))
2433 : /* If the class can provide only one hard reg to the allocno,
2434 : we processed the insn record_operand_costs already and we
2435 : actually updated the hard reg cost there. */
2436 7262113 : continue;
2437 478271 : rclass = ALLOCNO_CLASS (a);
2438 478271 : if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno))
2439 23082 : continue;
2440 455189 : i = ira_class_hard_reg_index[rclass][hard_regno];
2441 455189 : if (i < 0)
2442 7298 : continue;
2443 447891 : a_regno = ALLOCNO_REGNO (a);
2444 447891 : for (curr_loop_tree_node = ALLOCNO_LOOP_TREE_NODE (a);
2445 984814 : curr_loop_tree_node != NULL;
2446 536923 : curr_loop_tree_node = curr_loop_tree_node->parent)
2447 536923 : if ((curr_a = curr_loop_tree_node->regno_allocno_map[a_regno]) != NULL)
2448 466460 : ira_add_allocno_pref (curr_a, hard_regno, freq);
2449 447891 : {
2450 447891 : int cost;
2451 447891 : enum reg_class hard_reg_class;
2452 447891 : machine_mode mode;
2453 :
2454 447891 : mode = ALLOCNO_MODE (a);
2455 447891 : hard_reg_class = REGNO_REG_CLASS (hard_regno);
2456 447891 : ira_init_register_move_cost_if_necessary (mode);
2457 447891 : cost = (to_p ? ira_register_move_cost[mode][hard_reg_class][rclass]
2458 249595 : : ira_register_move_cost[mode][rclass][hard_reg_class]) * freq;
2459 447891 : ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass,
2460 : ALLOCNO_CLASS_COST (a));
2461 447891 : ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a),
2462 : rclass, 0);
2463 447891 : ALLOCNO_HARD_REG_COSTS (a)[i] -= cost;
2464 447891 : ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost;
2465 447891 : ALLOCNO_CLASS_COST (a) = MIN (ALLOCNO_CLASS_COST (a),
2466 : ALLOCNO_HARD_REG_COSTS (a)[i]);
2467 : }
2468 : }
2469 : }
2470 :
2471 : /* After we find hard register and memory costs for allocnos, define
2472 : its class and modify hard register cost because insns moving
2473 : allocno to/from hard registers. */
2474 : static void
2475 1471362 : setup_allocno_class_and_costs (void)
2476 : {
2477 1471362 : int i, j, n, regno, hard_regno, num;
2478 1471362 : int *reg_costs;
2479 1471362 : enum reg_class aclass, rclass;
2480 1471362 : ira_allocno_t a;
2481 1471362 : ira_allocno_iterator ai;
2482 1471362 : cost_classes_t cost_classes_ptr;
2483 :
2484 1471362 : ira_assert (allocno_p);
2485 36709999 : FOR_EACH_ALLOCNO (a, ai)
2486 : {
2487 35238637 : i = ALLOCNO_NUM (a);
2488 35238637 : regno = ALLOCNO_REGNO (a);
2489 35238637 : aclass = regno_aclass[regno];
2490 35238637 : cost_classes_ptr = regno_cost_classes[regno];
2491 35238637 : ira_assert (pref[i] == NO_REGS || aclass != NO_REGS);
2492 35238637 : ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost;
2493 35238637 : ira_set_allocno_class (a, aclass);
2494 35238637 : if (aclass == NO_REGS)
2495 690374 : continue;
2496 34548263 : if (optimize && ALLOCNO_CLASS (a) != pref[i])
2497 : {
2498 5595749 : n = ira_class_hard_regs_num[aclass];
2499 5595749 : ALLOCNO_HARD_REG_COSTS (a)
2500 5595749 : = reg_costs = ira_allocate_cost_vector (aclass);
2501 99960124 : for (j = n - 1; j >= 0; j--)
2502 : {
2503 94364375 : hard_regno = ira_class_hard_regs[aclass][j];
2504 94364375 : if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], hard_regno))
2505 15149165 : reg_costs[j] = ALLOCNO_CLASS_COST (a);
2506 : else
2507 : {
2508 79215210 : rclass = REGNO_REG_CLASS (hard_regno);
2509 79215210 : num = cost_classes_ptr->index[rclass];
2510 79215210 : if (num < 0)
2511 : {
2512 280419 : num = cost_classes_ptr->hard_regno_index[hard_regno];
2513 280419 : ira_assert (num >= 0);
2514 : }
2515 79215210 : reg_costs[j] = COSTS (costs, i)->cost[num];
2516 : }
2517 : }
2518 : }
2519 : }
2520 1471362 : if (optimize)
2521 1043685 : ira_traverse_loop_tree (true, ira_loop_tree_root,
2522 : process_bb_node_for_hard_reg_moves, NULL);
2523 1471362 : }
2524 :
2525 :
2526 :
2527 : /* Function called once during compiler work. */
2528 : void
2529 209218 : ira_init_costs_once (void)
2530 : {
2531 209218 : int i;
2532 :
2533 209218 : init_cost = NULL;
2534 6485758 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2535 : {
2536 6276540 : op_costs[i] = NULL;
2537 6276540 : this_op_costs[i] = NULL;
2538 : }
2539 209218 : temp_costs = NULL;
2540 209218 : }
2541 :
2542 : /* Free allocated temporary cost vectors. */
2543 : void
2544 788929 : target_ira_int::free_ira_costs ()
2545 : {
2546 788929 : int i;
2547 :
2548 788929 : free (x_init_cost);
2549 788929 : x_init_cost = NULL;
2550 24456799 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2551 : {
2552 23667870 : free (x_op_costs[i]);
2553 23667870 : free (x_this_op_costs[i]);
2554 23667870 : x_op_costs[i] = x_this_op_costs[i] = NULL;
2555 : }
2556 788929 : free (x_temp_costs);
2557 788929 : x_temp_costs = NULL;
2558 788929 : }
2559 :
2560 : /* This is called each time register related information is
2561 : changed. */
2562 : void
2563 214527 : ira_init_costs (void)
2564 : {
2565 214527 : int i;
2566 :
2567 214527 : this_target_ira_int->free_ira_costs ();
2568 214527 : max_struct_costs_size
2569 214527 : = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1);
2570 : /* Don't use ira_allocate because vectors live through several IRA
2571 : calls. */
2572 214527 : init_cost = (struct costs *) xmalloc (max_struct_costs_size);
2573 214527 : init_cost->mem_cost = 1000000;
2574 6867325 : for (i = 0; i < ira_important_classes_num; i++)
2575 6652798 : init_cost->cost[i] = 1000000;
2576 6650337 : for (i = 0; i < MAX_RECOG_OPERANDS; i++)
2577 : {
2578 6435810 : op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2579 6435810 : this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size);
2580 : }
2581 214527 : temp_costs = (struct costs *) xmalloc (max_struct_costs_size);
2582 214527 : }
2583 :
2584 :
2585 :
2586 : /* Common initialization function for ira_costs and
2587 : ira_set_pseudo_classes. */
2588 : static void
2589 1500820 : init_costs (void)
2590 : {
2591 1500820 : init_subregs_of_mode ();
2592 3001640 : costs = (struct costs *) ira_allocate (max_struct_costs_size
2593 1500820 : * cost_elements_num);
2594 3001640 : pref_buffer = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2595 1500820 : * cost_elements_num);
2596 4502460 : regno_aclass = (enum reg_class *) ira_allocate (sizeof (enum reg_class)
2597 1500820 : * max_reg_num ());
2598 1500820 : regno_equiv_gains = (int *) ira_allocate (sizeof (int) * max_reg_num ());
2599 1500820 : memset (regno_equiv_gains, 0, sizeof (int) * max_reg_num ());
2600 1500820 : }
2601 :
2602 : /* Common finalization function for ira_costs and
2603 : ira_set_pseudo_classes. */
2604 : static void
2605 1500820 : finish_costs (void)
2606 : {
2607 1500820 : finish_subregs_of_mode ();
2608 1500820 : ira_free (regno_equiv_gains);
2609 1500820 : ira_free (regno_aclass);
2610 1500820 : ira_free (pref_buffer);
2611 1500820 : ira_free (costs);
2612 1500820 : }
2613 :
2614 : /* Entry function which defines register class, memory and hard
2615 : register costs for each allocno. */
2616 : void
2617 1471362 : ira_costs (void)
2618 : {
2619 1471362 : allocno_p = true;
2620 1471362 : cost_elements_num = ira_allocnos_num;
2621 1471362 : init_costs ();
2622 2942724 : total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size
2623 1471362 : * ira_allocnos_num);
2624 1471362 : initiate_regno_cost_classes ();
2625 1471362 : if (!ira_use_lra_p)
2626 : /* Process equivs in reload to update costs through hook
2627 : ira_adjust_equiv_reg_cost. */
2628 0 : calculate_elim_costs_all_insns ();
2629 1471362 : find_costs_and_classes ();
2630 1471362 : setup_allocno_class_and_costs ();
2631 1471362 : finish_regno_cost_classes ();
2632 1471362 : finish_costs ();
2633 1471362 : ira_free (total_allocno_costs);
2634 1471362 : }
2635 :
2636 : /* Entry function which defines classes for pseudos.
2637 : Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2638 : void
2639 29458 : ira_set_pseudo_classes (bool define_pseudo_classes, FILE *dump_file)
2640 : {
2641 29458 : FILE *saved_file = ira_dump_file;
2642 29458 : allocno_p = false;
2643 29458 : internal_flag_ira_verbose = flag_ira_verbose;
2644 29458 : ira_dump_file = dump_file;
2645 29458 : cost_elements_num = max_reg_num ();
2646 29458 : init_costs ();
2647 29458 : initiate_regno_cost_classes ();
2648 29458 : find_costs_and_classes ();
2649 29458 : finish_regno_cost_classes ();
2650 29458 : if (define_pseudo_classes)
2651 101 : pseudo_classes_defined_p = true;
2652 :
2653 29458 : finish_costs ();
2654 29458 : ira_dump_file = saved_file;
2655 29458 : }
2656 :
2657 :
2658 :
2659 : /* Change hard register costs for allocnos which lives through
2660 : function calls. This is called only when we found all intersected
2661 : calls during building allocno live ranges. */
2662 : void
2663 1471362 : ira_tune_allocno_costs (void)
2664 : {
2665 1471362 : int j, n, regno;
2666 1471362 : int cost, min_cost, *reg_costs;
2667 1471362 : enum reg_class aclass;
2668 1471362 : machine_mode mode;
2669 1471362 : ira_allocno_t a;
2670 1471362 : ira_allocno_iterator ai;
2671 1471362 : ira_allocno_object_iterator oi;
2672 1471362 : ira_object_t obj;
2673 1471362 : bool skip_p;
2674 :
2675 37930378 : FOR_EACH_ALLOCNO (a, ai)
2676 : {
2677 36459016 : aclass = ALLOCNO_CLASS (a);
2678 36459016 : if (aclass == NO_REGS)
2679 659420 : continue;
2680 35799596 : mode = ALLOCNO_MODE (a);
2681 35799596 : n = ira_class_hard_regs_num[aclass];
2682 35799596 : min_cost = INT_MAX;
2683 35799596 : if (ALLOCNO_CALLS_CROSSED_NUM (a)
2684 35799596 : != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a))
2685 : {
2686 3589289 : ira_allocate_and_set_costs
2687 3589289 : (&ALLOCNO_HARD_REG_COSTS (a), aclass,
2688 : ALLOCNO_CLASS_COST (a));
2689 3589289 : reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2690 52190157 : for (j = n - 1; j >= 0; j--)
2691 : {
2692 48600868 : regno = ira_class_hard_regs[aclass][j];
2693 48600868 : skip_p = false;
2694 87402104 : FOR_EACH_ALLOCNO_OBJECT (a, obj, oi)
2695 : {
2696 50006381 : if (ira_hard_reg_set_intersection_p (regno, mode,
2697 : OBJECT_CONFLICT_HARD_REGS
2698 : (obj)))
2699 : {
2700 : skip_p = true;
2701 : break;
2702 : }
2703 : }
2704 48600868 : if (skip_p)
2705 11205145 : continue;
2706 37395723 : cost = 0;
2707 37395723 : if (ira_need_caller_save_p (a, regno))
2708 19265432 : cost += ira_caller_save_cost (a);
2709 : #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2710 : {
2711 : auto rclass = REGNO_REG_CLASS (regno);
2712 : cost += ((ira_memory_move_cost[mode][rclass][0]
2713 : + ira_memory_move_cost[mode][rclass][1])
2714 : * ALLOCNO_FREQ (a)
2715 : * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2);
2716 : }
2717 : #endif
2718 37395723 : if (INT_MAX - cost < reg_costs[j])
2719 0 : reg_costs[j] = INT_MAX;
2720 : else
2721 37395723 : reg_costs[j] += cost;
2722 37395723 : if (min_cost > reg_costs[j])
2723 48600868 : min_cost = reg_costs[j];
2724 : }
2725 : }
2726 3589289 : if (min_cost != INT_MAX)
2727 3573525 : ALLOCNO_CLASS_COST (a) = min_cost;
2728 :
2729 : /* Some targets allow pseudos to be allocated to unaligned sequences
2730 : of hard registers. However, selecting an unaligned sequence can
2731 : unnecessarily restrict later allocations. So increase the cost of
2732 : unaligned hard regs to encourage the use of aligned hard regs. */
2733 35799596 : {
2734 35799596 : const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)];
2735 :
2736 35799596 : if (nregs > 1)
2737 : {
2738 1305832 : ira_allocate_and_set_costs
2739 1305832 : (&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a));
2740 1305832 : reg_costs = ALLOCNO_HARD_REG_COSTS (a);
2741 29210277 : for (j = n - 1; j >= 0; j--)
2742 : {
2743 27904445 : regno = ira_non_ordered_class_hard_regs[aclass][j];
2744 27904445 : if ((regno % nregs) != 0)
2745 : {
2746 13712637 : int index = ira_class_hard_reg_index[aclass][regno];
2747 13712637 : ira_assert (index != -1);
2748 13712637 : reg_costs[index] += ALLOCNO_FREQ (a);
2749 : }
2750 : }
2751 : }
2752 : }
2753 : }
2754 1471362 : }
2755 :
2756 : /* A hook from the reload pass. Add COST to the estimated gain for eliminating
2757 : REGNO with its equivalence. If COST is zero, record that no such
2758 : elimination is possible. */
2759 :
2760 : void
2761 0 : ira_adjust_equiv_reg_cost (unsigned regno, int cost)
2762 : {
2763 0 : ira_assert (!ira_use_lra_p);
2764 0 : if (cost == 0)
2765 0 : regno_equiv_gains[regno] = 0;
2766 : else
2767 0 : regno_equiv_gains[regno] += cost;
2768 0 : }
2769 :
2770 : void
2771 256621 : ira_costs_cc_finalize (void)
2772 : {
2773 256621 : this_target_ira_int->free_ira_costs ();
2774 256621 : }
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