Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 37541019 : make_hard_regno_live (int regno)
98 : {
99 37541019 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 35292131 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 15148934 : make_hard_regno_dead (int regno)
106 : {
107 15148934 : unsigned int i;
108 280429799 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 265280865 : ira_object_t obj = ira_object_id_map[i];
111 :
112 266955782 : if (ignore_reg_for_conflicts != NULL_RTX
113 174258736 : && REGNO (ignore_reg_for_conflicts)
114 174258736 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1674917 : continue;
116 :
117 263605948 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 263605948 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 15148934 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 15148934 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 243639331 : make_object_live (ira_object_t obj)
127 : {
128 243639331 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 243639331 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 243639331 : if (lr == NULL
132 206662576 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 54871342 : ira_add_live_range_to_object (obj, curr_point, -1);
134 243639331 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 251045511 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 251045511 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 251045511 : int start, i;
143 251045511 : enum reg_class aclass, pclass, cl;
144 251045511 : live_range_t p;
145 :
146 251045511 : aclass = ALLOCNO_CLASS (a);
147 251045511 : pclass = ira_pressure_class_translate[aclass];
148 2464502240 : for (i = 0;
149 2464502240 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2213456729 : if (! ira_reg_pressure_class_p[cl])
153 1967457657 : continue;
154 245999072 : if (high_pressure_start_point[cl] < 0)
155 74497918 : continue;
156 171501154 : p = OBJECT_LIVE_RANGES (obj);
157 171501154 : ira_assert (p != NULL);
158 171501154 : start = (high_pressure_start_point[cl] > p->start
159 171501154 : ? high_pressure_start_point[cl] : p->start);
160 171501154 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 251045511 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 243639331 : make_object_dead (ira_object_t obj)
168 : {
169 243639331 : live_range_t lr;
170 243639331 : int regno;
171 243639331 : int ignore_regno = -1;
172 243639331 : int ignore_total_regno = -1;
173 243639331 : int end_regno = -1;
174 :
175 243639331 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 243639331 : if (ignore_reg_for_conflicts != NULL_RTX
180 243639331 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3452951 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3452951 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6905902 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3452951 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 521855 : ignore_regno = end_regno;
189 3452951 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 521855 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 974557324 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 246570427 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 246570427 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2931096 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 246570427 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2931096 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 243639331 : lr = OBJECT_LIVE_RANGES (obj);
205 243639331 : ira_assert (lr != NULL);
206 243639331 : lr->finish = curr_point;
207 243639331 : update_allocno_pressure_excess_length (obj);
208 243639331 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 260382404 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 260382404 : int i;
222 260382404 : enum reg_class cl;
223 :
224 2555310132 : for (i = 0;
225 2555310132 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2294927728 : if (! ira_reg_pressure_class_p[cl])
229 2039327606 : continue;
230 255600122 : curr_reg_pressure[cl] += n;
231 255600122 : if (high_pressure_start_point[cl] < 0
232 106343340 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1798745 : high_pressure_start_point[cl] = curr_point;
234 255600122 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 220696648 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 260382404 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 52814005 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 52814005 : int i;
248 52814005 : unsigned int j;
249 52814005 : enum reg_class cl;
250 52814005 : bool set_p = false;
251 :
252 52814005 : for (i = 0;
253 512731909 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 459917904 : if (! ira_reg_pressure_class_p[cl])
257 407601341 : continue;
258 52316563 : curr_reg_pressure[cl] -= nregs;
259 52316563 : ira_assert (curr_reg_pressure[cl] >= 0);
260 52316563 : if (high_pressure_start_point[cl] >= 0
261 4754272 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 459917904 : set_p = true;
263 : }
264 52814005 : if (set_p)
265 : {
266 7888237 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7406180 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4587406 : for (i = 0;
269 5069463 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4587406 : if (! ira_reg_pressure_class_p[cl])
273 4105349 : continue;
274 482057 : if (high_pressure_start_point[cl] >= 0
275 482057 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 482057 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 52814005 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 121532 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 121532 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 121532 : ira_object_t obj;
288 :
289 121532 : if (a == NULL)
290 : return false;
291 121532 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 121532 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 121532 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 228552530 : mark_pseudo_regno_live (int regno)
303 : {
304 228552530 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 228552530 : enum reg_class pclass;
306 228552530 : int i, n, nregs;
307 :
308 228552530 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 228552530 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 228552530 : n = ALLOCNO_NUM_OBJECTS (a);
315 228552530 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 228552530 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 228552530 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69887607 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 526992667 : for (i = 0; i < n; i++)
325 : {
326 298440137 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 298440137 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 55119445 : continue;
330 :
331 243320692 : inc_register_pressure (pclass, nregs);
332 243320692 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 851682 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 851682 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 851682 : int n;
344 851682 : enum reg_class pclass;
345 851682 : ira_object_t obj;
346 :
347 851682 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 851682 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 851682 : n = ALLOCNO_NUM_OBJECTS (a);
354 851682 : if (n == 1)
355 : {
356 38125 : mark_pseudo_regno_live (regno);
357 38125 : return;
358 : }
359 :
360 813557 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 813557 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 813557 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 813557 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 318639 : inc_register_pressure (pclass, 1);
369 318639 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 103948860 : mark_hard_reg_live (rtx reg)
377 : {
378 103948860 : int regno = REGNO (reg);
379 :
380 103948860 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 31623079 : int last = END_REGNO (reg);
383 31623079 : enum reg_class aclass, pclass;
384 :
385 63246158 : while (regno < last)
386 : {
387 31623079 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 31623079 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 16743073 : aclass = ira_hard_regno_allocno_class[regno];
391 16743073 : pclass = ira_pressure_class_translate[aclass];
392 16743073 : inc_register_pressure (pclass, 1);
393 16743073 : make_hard_regno_live (regno);
394 : }
395 31623079 : regno++;
396 : }
397 : }
398 103948860 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 87911999 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 87911999 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1270985 : mark_pseudo_regno_subword_live (regno,
409 851682 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 87060317 : mark_pseudo_regno_live (regno);
413 87911999 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 189998273 : mark_ref_live (df_ref ref)
418 : {
419 189998273 : rtx reg = DF_REF_REG (ref);
420 189998273 : rtx orig_reg = reg;
421 :
422 189998273 : if (GET_CODE (reg) == SUBREG)
423 3041487 : reg = SUBREG_REG (reg);
424 :
425 189998273 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 86049413 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 103948860 : mark_hard_reg_live (reg);
429 189998273 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 36044180 : mark_pseudo_regno_dead (int regno)
435 : {
436 36044180 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 36044180 : int n, i, nregs;
438 36044180 : enum reg_class cl;
439 :
440 36044180 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 36044180 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 36044180 : n = ALLOCNO_NUM_OBJECTS (a);
447 36044180 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 36044180 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 36044180 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1287338 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 73375698 : for (i = 0; i < n; i++)
456 : {
457 37331518 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 37331518 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3548 : continue;
460 :
461 37327970 : dec_register_pressure (cl, nregs);
462 37327970 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 341234 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 341234 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 341234 : int n;
473 341234 : enum reg_class cl;
474 341234 : ira_object_t obj;
475 :
476 341234 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 341234 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 341234 : n = ALLOCNO_NUM_OBJECTS (a);
483 341234 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 337101 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 337101 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 337101 : obj = ALLOCNO_OBJECT (a, subword);
492 337101 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 337101 : dec_register_pressure (cl, 1);
496 337101 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 47324948 : mark_hard_reg_dead (rtx reg)
503 : {
504 47324948 : int regno = REGNO (reg);
505 :
506 47324948 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 15150952 : int last = END_REGNO (reg);
509 15150952 : enum reg_class aclass, pclass;
510 :
511 30301904 : while (regno < last)
512 : {
513 15150952 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 15148934 : aclass = ira_hard_regno_allocno_class[regno];
516 15148934 : pclass = ira_pressure_class_translate[aclass];
517 15148934 : dec_register_pressure (pclass, 1);
518 15148934 : make_hard_regno_dead (regno);
519 : }
520 15150952 : regno++;
521 : }
522 : }
523 47324948 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 36385414 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 36385414 : if (read_modify_subreg_p (orig_reg))
532 : {
533 512224 : mark_pseudo_regno_subword_dead (regno,
534 341234 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 36044180 : mark_pseudo_regno_dead (regno);
538 36385414 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 81852012 : mark_ref_dead (df_ref def)
544 : {
545 81852012 : rtx reg = DF_REF_REG (def);
546 81852012 : rtx orig_reg = reg;
547 :
548 81852012 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 81852012 : if (GET_CODE (reg) == SUBREG)
552 918905 : reg = SUBREG_REG (reg);
553 :
554 81852012 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 81852012 : && (GET_CODE (orig_reg) != SUBREG
556 331943 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 331943 : || !read_modify_subreg_p (orig_reg)))
558 4236 : return;
559 :
560 81847776 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 34522828 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 47324948 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2893038 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2893038 : rtx orig_reg = reg;
577 2893038 : ira_allocno_t a;
578 :
579 2893038 : if (GET_CODE (reg) == SUBREG)
580 84438 : reg = SUBREG_REG (reg);
581 :
582 2893038 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 1023802 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 1023802 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 931293 : if (advance_p)
590 886628 : curr_point++;
591 :
592 931293 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 931293 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 931293 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 931293 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 931293 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 2939915 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 2939915 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2877531 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2877531 : if (use < recog_data.n_operands - 1
624 1114817 : && recog_data.constraints[use][0] == '%')
625 6461 : advance_p
626 6461 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2877531 : if (use >= 1
629 2877231 : && recog_data.constraints[use - 1][0] == '%')
630 9046 : advance_p
631 9046 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14501218 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14501218 : int use, use_match;
662 14501218 : ira_allocno_t a;
663 14501218 : enum reg_class use_cl, acl;
664 14501218 : bool advance_p;
665 14501218 : rtx dreg = recog_data.operand[def];
666 14501218 : rtx orig_dreg = dreg;
667 :
668 14501218 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14501218 : if (GET_CODE (dreg) == SUBREG)
672 112463 : dreg = SUBREG_REG (dreg);
673 :
674 14501218 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 12285017 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 12285017 : acl = ALLOCNO_CLASS (a);
679 12285017 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 12086749 : advance_p = true;
683 :
684 12086749 : int n_operands = recog_data.n_operands;
685 12086749 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 50035487 : for (use = 0; use < n_operands; use++)
687 : {
688 37948738 : int alt1;
689 :
690 37948738 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 12245360 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 37714372 : if (op_alt[use].matches == def
701 25703378 : || (for_tie_p
702 13439698 : && rtx_equal_p (recog_data.operand[use],
703 13439698 : recog_data.operand[op_alt[def].matched])))
704 12010994 : continue;
705 :
706 13692384 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 12006829 : use_cl = op_alt[use].cl;
710 12006829 : if (use_cl == NO_REGS)
711 4813475 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 8878909 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 1015203 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 21112435 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 18172521 : if (!TEST_BIT (preferred_alternatives, alt1))
730 8754868 : continue;
731 9417653 : const operand_alternative *op_alt1
732 9417653 : = &recog_op_alt[alt1 * n_operands];
733 9417653 : if (op_alt1[use].matches == def
734 7560726 : || (use < n_operands - 1
735 2837995 : && recog_data.constraints[use][0] == '%'
736 8117 : && op_alt1[use + 1].matches == def)
737 7560726 : || (use >= 1
738 7559204 : && recog_data.constraints[use - 1][0] == '%'
739 3072153 : && op_alt1[use - 1].matches == def))
740 : break;
741 4499275 : if (for_tie_p
742 4289042 : && !op_alt1[def].earlyclobber
743 4287882 : && op_alt1[def].matched < 0
744 25088 : && alternative_class (op_alt1, def) != NO_REGS
745 4524363 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 7863706 : if (alt1 < recog_data.n_alternatives)
750 4923792 : continue;
751 :
752 2939914 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 2939914 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 84652659 : make_early_clobber_and_input_conflicts (void)
779 : {
780 84652659 : int alt;
781 84652659 : int def, def_match;
782 84652659 : enum reg_class def_cl;
783 :
784 84652659 : int n_alternatives = recog_data.n_alternatives;
785 84652659 : int n_operands = recog_data.n_operands;
786 84652659 : const operand_alternative *op_alt = recog_op_alt;
787 1168035978 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1083383319 : if (TEST_BIT (preferred_alternatives, alt))
789 391051518 : for (def = 0; def < n_operands; def++)
790 : {
791 269885065 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 255629452 : def_cl = op_alt[def].cl;
795 255629452 : if (def_cl != NO_REGS)
796 : {
797 213640633 : if (op_alt[def].earlyclobber)
798 140573 : check_and_make_def_conflict (alt, def, def_cl, false);
799 213500060 : else if (op_alt[def].matched >= 0
800 213500060 : && !targetm.class_likely_spilled_p (def_cl))
801 14324119 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 269885065 : if ((def_match = op_alt[def].matches) >= 0
805 269885065 : && (op_alt[def_match].earlyclobber
806 15011730 : || op_alt[def].earlyclobber))
807 : {
808 36526 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 36526 : def_cl = op_alt[def_match].cl;
812 36526 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 84652659 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 95375163 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 95375163 : df_ref def;
823 95375163 : bool set_p = false;
824 :
825 685874795 : FOR_EACH_INSN_DEF (def, insn)
826 590499632 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 21883768 : rtx dreg = DF_REF_REG (def);
829 :
830 21883768 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 21883768 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 146108 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 21737660 : if (live_p)
839 10868830 : mark_ref_live (def);
840 : else
841 10868830 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 95375163 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the class of the hard register.
850 : Otherwise it returns NO_REGS. */
851 : static enum reg_class
852 179101050 : single_reg_class (const char *constraints, rtx op, rtx equiv_const)
853 : {
854 179101050 : int c;
855 179101050 : enum reg_class cl, next_cl;
856 179101050 : enum constraint_num cn;
857 :
858 179101050 : cl = NO_REGS;
859 179101050 : alternative_mask preferred = preferred_alternatives;
860 932702401 : while ((c = *constraints))
861 : {
862 918556544 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 918556544 : else if (c == ',')
865 251015125 : preferred >>= 1;
866 667541419 : else if (preferred & 1)
867 201628385 : switch (c)
868 : {
869 : case 'g':
870 : return NO_REGS;
871 :
872 181466965 : default:
873 : /* ??? Is this the best way to handle memory constraints? */
874 181466965 : cn = lookup_constraint (constraints);
875 181466965 : if (insn_extra_memory_constraint (cn)
876 169339501 : || insn_extra_special_memory_constraint (cn)
877 : || insn_extra_relaxed_memory_constraint (cn)
878 350806464 : || insn_extra_address_constraint (cn))
879 : return NO_REGS;
880 168760525 : if (constraint_satisfied_p (op, cn)
881 168760525 : || (equiv_const != NULL_RTX
882 0 : && CONSTANT_P (equiv_const)
883 0 : && constraint_satisfied_p (equiv_const, cn)))
884 14745682 : return NO_REGS;
885 154014843 : next_cl = reg_class_for_constraint (cn);
886 122561670 : if (next_cl == NO_REGS)
887 : break;
888 119342635 : if (cl == NO_REGS
889 119342635 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
890 994388 : : (ira_class_singleton[cl][GET_MODE (op)]
891 994388 : != ira_class_singleton[next_cl][GET_MODE (op)]))
892 : return NO_REGS;
893 : cl = next_cl;
894 : break;
895 :
896 12985787 : case '0': case '1': case '2': case '3': case '4':
897 12985787 : case '5': case '6': case '7': case '8': case '9':
898 12985787 : {
899 12985787 : char *end;
900 12985787 : unsigned long dup = strtoul (constraints, &end, 10);
901 12985787 : constraints = end;
902 12985787 : next_cl
903 12985787 : = single_reg_class (recog_data.constraints[dup],
904 : recog_data.operand[dup], NULL_RTX);
905 12985787 : if (cl == NO_REGS
906 12985787 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
907 18907 : : (ira_class_singleton[cl][GET_MODE (op)]
908 18907 : != ira_class_singleton[next_cl][GET_MODE (op)]))
909 12757789 : return NO_REGS;
910 227998 : cl = next_cl;
911 227998 : continue;
912 227998 : }
913 : }
914 753373353 : constraints += CONSTRAINT_LEN (c, constraints);
915 : }
916 : return cl;
917 : }
918 :
919 : /* The function checks that operand OP_NUM of the current insn can use
920 : only one hard register. If it is so, the function returns the
921 : class of the hard register. Otherwise it returns NO_REGS. */
922 : static enum reg_class
923 181383906 : single_reg_operand_class (int op_num)
924 : {
925 181383906 : if (op_num < 0 || recog_data.n_alternatives == 0)
926 : return NO_REGS;
927 166115263 : return single_reg_class (recog_data.constraints[op_num],
928 166115263 : recog_data.operand[op_num], NULL_RTX);
929 : }
930 :
931 : /* The function sets up hard register set *SET to hard registers which
932 : might be used by insn reloads because the constraints are too
933 : strict. */
934 : void
935 27618 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
936 : alternative_mask preferred)
937 : {
938 27618 : int i, c, regno = 0;
939 27618 : enum reg_class cl;
940 27618 : rtx op;
941 27618 : machine_mode mode;
942 :
943 27618 : CLEAR_HARD_REG_SET (*set);
944 85293 : for (i = 0; i < recog_data.n_operands; i++)
945 : {
946 57675 : op = recog_data.operand[i];
947 :
948 57675 : if (GET_CODE (op) == SUBREG)
949 1090 : op = SUBREG_REG (op);
950 :
951 57675 : if (GET_CODE (op) == SCRATCH
952 57675 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
953 : {
954 38713 : const char *p = recog_data.constraints[i];
955 :
956 77426 : mode = (GET_CODE (op) == SCRATCH
957 38713 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
958 38713 : cl = NO_REGS;
959 38713 : for (alternative_mask curr_preferred = preferred;
960 1424326 : (c = *p);
961 1385613 : p += CONSTRAINT_LEN (c, p))
962 1385613 : if (c == '#')
963 0 : curr_preferred &= ~ALTERNATIVE_BIT (0);
964 1385613 : else if (c == ',')
965 472439 : curr_preferred >>= 1;
966 913174 : else if (curr_preferred & 1)
967 : {
968 570611 : cl = reg_class_for_constraint (lookup_constraint (p));
969 246845 : if (cl != NO_REGS)
970 : {
971 : /* There is no register pressure problem if all of the
972 : regs in this class are fixed. */
973 243157 : int regno = ira_class_singleton[cl][mode];
974 243157 : if (regno >= 0)
975 1599 : add_to_hard_reg_set (set, mode, regno);
976 : }
977 327454 : else if (c == '{')
978 : {
979 0 : int regno = decode_hard_reg_constraint (p);
980 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
981 0 : add_to_hard_reg_set (set, mode, regno);
982 : }
983 : }
984 : }
985 : }
986 27618 : }
987 : /* Processes input operands, if IN_P, or output operands otherwise of
988 : the current insn with FREQ to find allocno which can use only one
989 : hard register and makes other currently living allocnos conflicting
990 : with the hard register. */
991 : static void
992 169305318 : process_single_reg_class_operands (bool in_p, int freq)
993 : {
994 169305318 : int i, regno;
995 169305318 : unsigned int px;
996 169305318 : enum reg_class cl;
997 169305318 : rtx operand;
998 169305318 : ira_allocno_t operand_a, a;
999 :
1000 531913680 : for (i = 0; i < recog_data.n_operands; i++)
1001 : {
1002 362608362 : operand = recog_data.operand[i];
1003 362608362 : if (in_p && recog_data.operand_type[i] != OP_IN
1004 61777465 : && recog_data.operand_type[i] != OP_INOUT)
1005 61697740 : continue;
1006 181304181 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1007 119606441 : && recog_data.operand_type[i] != OP_INOUT)
1008 119526716 : continue;
1009 181383906 : cl = single_reg_operand_class (i);
1010 181383906 : if (cl == NO_REGS)
1011 180624472 : continue;
1012 :
1013 759434 : operand_a = NULL;
1014 :
1015 759434 : if (GET_CODE (operand) == SUBREG)
1016 59546 : operand = SUBREG_REG (operand);
1017 :
1018 759434 : if (REG_P (operand)
1019 759434 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1020 : {
1021 754884 : enum reg_class aclass;
1022 :
1023 754884 : operand_a = ira_curr_regno_allocno_map[regno];
1024 754884 : aclass = ALLOCNO_CLASS (operand_a);
1025 754884 : if (ira_class_subset_p[cl][aclass])
1026 : {
1027 : /* View the desired allocation of OPERAND as:
1028 :
1029 : (REG:YMODE YREGNO),
1030 :
1031 : a simplification of:
1032 :
1033 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1034 746527 : machine_mode ymode, xmode;
1035 746527 : int xregno, yregno;
1036 746527 : poly_int64 offset;
1037 :
1038 746527 : xmode = recog_data.operand_mode[i];
1039 746527 : xregno = ira_class_singleton[cl][xmode];
1040 746527 : gcc_assert (xregno >= 0);
1041 746527 : ymode = ALLOCNO_MODE (operand_a);
1042 746527 : offset = subreg_lowpart_offset (ymode, xmode);
1043 746527 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1044 746527 : if (yregno >= 0
1045 746527 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1046 : {
1047 746527 : int cost;
1048 :
1049 746527 : ira_allocate_and_set_costs
1050 746527 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1051 : aclass, 0);
1052 746527 : ira_init_register_move_cost_if_necessary (xmode);
1053 1493054 : cost = freq * (in_p
1054 746527 : ? ira_register_move_cost[xmode][aclass][cl]
1055 432834 : : ira_register_move_cost[xmode][cl][aclass]);
1056 746527 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1057 746527 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1058 : }
1059 : }
1060 : }
1061 :
1062 29762183 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1063 : {
1064 29002749 : ira_object_t obj = ira_object_id_map[px];
1065 29002749 : a = OBJECT_ALLOCNO (obj);
1066 29002749 : if (a != operand_a)
1067 : {
1068 : /* We could increase costs of A instead of making it
1069 : conflicting with the hard register. But it works worse
1070 : because it will be spilled in reload in anyway. */
1071 112849520 : OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1072 29002749 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1073 : }
1074 : }
1075 : }
1076 169305318 : }
1077 :
1078 : /* Go through the operands of the extracted insn looking for operand
1079 : alternatives that apply a register filter. Record any such filters
1080 : in the operand's allocno. */
1081 : static void
1082 84652659 : process_register_constraint_filters ()
1083 : {
1084 265956840 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1085 : {
1086 181304181 : rtx op = recog_data.operand[opno];
1087 181304181 : if (SUBREG_P (op))
1088 3001775 : op = SUBREG_REG (op);
1089 181304181 : if (REG_P (op) && !HARD_REGISTER_P (op))
1090 : {
1091 74855643 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1092 1067413106 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1093 : {
1094 992557463 : if (!TEST_BIT (preferred_alternatives, alt))
1095 868657163 : continue;
1096 :
1097 123900300 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1098 123900300 : auto cl = alternative_class (op_alt, opno);
1099 : /* The two extremes are easy:
1100 :
1101 : - We should record the filter if CL matches the
1102 : allocno class.
1103 :
1104 : - We should ignore the filter if CL and the allocno class
1105 : are disjoint. We'll either pick a different alternative
1106 : or reload the operand.
1107 :
1108 : Things are trickier if the classes overlap. However:
1109 :
1110 : - If the allocno class includes registers that are not
1111 : in CL, some choices of hard register will need a reload
1112 : anyway. It isn't obvious that reloads due to filters
1113 : are worse than reloads due to regnos being outside CL.
1114 :
1115 : - Conversely, if the allocno class is a subset of CL,
1116 : any allocation will satisfy the class requirement.
1117 : We should try to make sure it satisfies the filter
1118 : requirement too. This is useful if, for example,
1119 : an allocno needs to be in "low" registers to satisfy
1120 : some uses, and its allocno class is therefore those
1121 : low registers, but the allocno is elsewhere allowed
1122 : to be in any even-numbered register. Picking an
1123 : even-numbered low register satisfies both types of use. */
1124 123900300 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1125 29051488 : continue;
1126 :
1127 94848812 : auto filters = alternative_register_filters (op_alt, opno);
1128 94848812 : if (!filters)
1129 94848812 : continue;
1130 :
1131 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1132 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1133 : }
1134 : }
1135 : }
1136 84652659 : }
1137 :
1138 : /* Append a dependent filter ID with mode MODE, referenced allocno
1139 : REF_ALLOCNO, hardreg REF_HARD_REGNO, and REF_MODE to allocno A. */
1140 :
1141 : void
1142 0 : ira_add_dependent_filter (ira_allocno_t a, int id,
1143 : machine_mode mode, ira_allocno_t ref_allocno,
1144 : unsigned int ref_hard_regno, machine_mode ref_mode)
1145 : {
1146 : /* Check if we already have the filter that should be added.
1147 : This is a linear search and the assumption is that we'll never
1148 : have more than a handful of dependent filters. Right now, the
1149 : maximum is 32 (see gensupport.cc). */
1150 0 : for (auto *filter = ALLOCNO_DEPENDENT_FILTERS (a);
1151 0 : filter;
1152 0 : filter = filter->next)
1153 0 : if (filter->id == id
1154 0 : && filter->ref_allocno == ref_allocno
1155 0 : && filter->ref_hard_regno == ref_hard_regno
1156 0 : && filter->mode == mode
1157 0 : && filter->ref_mode == ref_mode)
1158 : return;
1159 :
1160 0 : auto *filter = (ira_dependent_filter *)
1161 0 : ira_allocate (sizeof (ira_dependent_filter));
1162 0 : filter->id = id;
1163 0 : filter->ref_allocno = ref_allocno;
1164 0 : filter->ref_hard_regno = ref_hard_regno;
1165 0 : filter->mode = mode;
1166 0 : filter->ref_mode = ref_mode;
1167 0 : filter->next = ALLOCNO_DEPENDENT_FILTERS (a);
1168 0 : ALLOCNO_DEPENDENT_FILTERS (a) = filter;
1169 : }
1170 :
1171 : /* Walk the operand alternatives of the current insn. For each
1172 : operand with a dependent-filter constraint, add one
1173 : ira_dependent_filter in the appropriate allocno. */
1174 :
1175 : static void
1176 0 : process_dependent_filters ()
1177 : {
1178 0 : if (!NUM_DEPENDENT_FILTERS)
1179 0 : return;
1180 :
1181 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1182 : {
1183 : rtx op = recog_data.operand[opno];
1184 : if (SUBREG_P (op))
1185 : op = SUBREG_REG (op);
1186 : if (!REG_P (op) || HARD_REGISTER_P (op))
1187 : continue;
1188 :
1189 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1190 :
1191 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1192 : {
1193 : if (!TEST_BIT (preferred_alternatives, alt))
1194 : continue;
1195 :
1196 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1197 : auto cl = alternative_class (op_alt, opno);
1198 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1199 : continue;
1200 :
1201 : auto dep_filter_mask = alternative_dependent_filters (op_alt, opno);
1202 : if (!dep_filter_mask)
1203 : continue;
1204 :
1205 : for (int id = 0; id < NUM_DEPENDENT_FILTERS; ++id)
1206 : {
1207 : if (!(dep_filter_mask & (1U << id)))
1208 : continue;
1209 :
1210 : int ref_opno = get_dependent_filter_ref (id);
1211 : if (ref_opno < 0 || ref_opno >= recog_data.n_operands)
1212 : continue;
1213 : rtx ref_op = recog_data.operand[ref_opno];
1214 : if (SUBREG_P (ref_op))
1215 : ref_op = SUBREG_REG (ref_op);
1216 : if (!REG_P (ref_op))
1217 : continue;
1218 :
1219 : ira_allocno_t ref_a = NULL;
1220 : unsigned int ref_hard_regno = INVALID_REGNUM;
1221 : if (HARD_REGISTER_P (ref_op))
1222 : ref_hard_regno = REGNO (ref_op);
1223 : else
1224 : ref_a = ira_curr_regno_allocno_map[REGNO (ref_op)];
1225 :
1226 : ira_add_dependent_filter (a, id, GET_MODE (op),
1227 : ref_a, ref_hard_regno,
1228 : GET_MODE (ref_op));
1229 : }
1230 : }
1231 : }
1232 : }
1233 :
1234 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1235 : we find a SET rtx that we can use to deduce that a register can be cheaply
1236 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1237 : static rtx
1238 6110291 : find_call_crossed_cheap_reg (rtx_insn *insn)
1239 : {
1240 6110291 : rtx cheap_reg = NULL_RTX;
1241 6110291 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1242 :
1243 17938495 : while (exp != NULL)
1244 : {
1245 11981933 : rtx x = XEXP (exp, 0);
1246 11981933 : if (GET_CODE (x) == SET)
1247 : {
1248 : exp = x;
1249 : break;
1250 : }
1251 11828204 : exp = XEXP (exp, 1);
1252 : }
1253 6110291 : if (exp != NULL)
1254 : {
1255 153729 : basic_block bb = BLOCK_FOR_INSN (insn);
1256 153729 : rtx reg = SET_SRC (exp);
1257 153729 : rtx_insn *prev = PREV_INSN (insn);
1258 307475 : while (prev && !(INSN_P (prev)
1259 153729 : && BLOCK_FOR_INSN (prev) != bb))
1260 : {
1261 153746 : if (NONDEBUG_INSN_P (prev))
1262 : {
1263 153729 : rtx set = single_set (prev);
1264 :
1265 153729 : if (set && rtx_equal_p (SET_DEST (set), reg))
1266 : {
1267 153729 : rtx src = SET_SRC (set);
1268 121943 : if (!REG_P (src) || HARD_REGISTER_P (src)
1269 275261 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1270 : break;
1271 32716 : if (!modified_between_p (src, prev, insn))
1272 6110291 : cheap_reg = src;
1273 : break;
1274 : }
1275 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1276 : {
1277 0 : rtx dest = SET_DEST (set);
1278 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1279 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1280 : break;
1281 0 : if (!modified_between_p (dest, prev, insn))
1282 6110291 : cheap_reg = dest;
1283 : break;
1284 : }
1285 :
1286 0 : if (reg_set_p (reg, prev))
1287 : break;
1288 : }
1289 17 : prev = PREV_INSN (prev);
1290 : }
1291 : }
1292 6110291 : return cheap_reg;
1293 : }
1294 :
1295 : /* Determine whether INSN is a register to register copy of the type where
1296 : we do not need to make the source and destiniation registers conflict.
1297 : If this is a copy instruction, then return the source reg. Otherwise,
1298 : return NULL_RTX. */
1299 : rtx
1300 309949438 : non_conflicting_reg_copy_p (rtx_insn *insn)
1301 : {
1302 : /* Reload has issues with overlapping pseudos being assigned to the
1303 : same hard register, so don't allow it. See PR87600 for details. */
1304 309949438 : if (!targetm.lra_p ())
1305 : return NULL_RTX;
1306 :
1307 309949438 : rtx set = single_set (insn);
1308 :
1309 : /* Disallow anything other than a simple register to register copy
1310 : that has no side effects. */
1311 309949438 : if (set == NULL_RTX
1312 294586926 : || !REG_P (SET_DEST (set))
1313 216707933 : || !REG_P (SET_SRC (set))
1314 382874415 : || side_effects_p (set))
1315 237024461 : return NULL_RTX;
1316 :
1317 72924977 : int dst_regno = REGNO (SET_DEST (set));
1318 72924977 : int src_regno = REGNO (SET_SRC (set));
1319 72924977 : machine_mode mode = GET_MODE (SET_DEST (set));
1320 :
1321 : /* By definition, a register does not conflict with itself, therefore we
1322 : do not have to handle it specially. Returning NULL_RTX now, helps
1323 : simplify the callers of this function. */
1324 72924977 : if (dst_regno == src_regno)
1325 : return NULL_RTX;
1326 :
1327 : /* Computing conflicts for register pairs is difficult to get right, so
1328 : for now, disallow it. */
1329 72924977 : if ((HARD_REGISTER_NUM_P (dst_regno)
1330 20033408 : && hard_regno_nregs (dst_regno, mode) != 1)
1331 92792235 : || (HARD_REGISTER_NUM_P (src_regno)
1332 10505607 : && hard_regno_nregs (src_regno, mode) != 1))
1333 : return NULL_RTX;
1334 :
1335 : return SET_SRC (set);
1336 : }
1337 :
1338 : #ifdef EH_RETURN_DATA_REGNO
1339 :
1340 : /* Add EH return hard registers as conflict hard registers to allocnos
1341 : living at end of BB. For most allocnos it is already done in
1342 : process_bb_node_lives when we processing input edges but it does
1343 : not work when and EH edge is edge out of the current region. This
1344 : function covers such out of region edges. */
1345 : static void
1346 14629460 : process_out_of_region_eh_regs (basic_block bb)
1347 : {
1348 14629460 : edge e;
1349 14629460 : edge_iterator ei;
1350 14629460 : unsigned int i;
1351 14629460 : bitmap_iterator bi;
1352 14629460 : bool eh_p = false;
1353 :
1354 35511168 : FOR_EACH_EDGE (e, ei, bb->succs)
1355 20881708 : if ((e->flags & EDGE_EH)
1356 20881708 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1357 : eh_p = true;
1358 :
1359 14629460 : if (! eh_p)
1360 14621555 : return;
1361 :
1362 106710 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1363 : {
1364 98805 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1365 204212 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1366 : {
1367 105407 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1368 421628 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1369 105407 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1370 : }
1371 : }
1372 : }
1373 :
1374 : #endif
1375 :
1376 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1377 : static void
1378 3736519 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1379 : function_abi callee_abi)
1380 : {
1381 3736519 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1382 3736519 : rtx_code_label *landing_label;
1383 3736519 : basic_block landing_bb;
1384 :
1385 7941056 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1386 : {
1387 6708340 : if ((landing_label = lp->landing_pad) != NULL
1388 6708340 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1389 13416629 : && (region->type != ERT_CLEANUP
1390 5213042 : || bitmap_bit_p (df_get_live_in (landing_bb),
1391 : ALLOCNO_REGNO (a))))
1392 : {
1393 2503803 : HARD_REG_SET new_conflict_regs
1394 2503803 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1395 10015212 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1396 2503803 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1397 2503803 : return;
1398 : }
1399 : }
1400 : }
1401 :
1402 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1403 : update allocno live ranges, allocno hard register conflicts,
1404 : intersected calls, and register pressure info for allocnos for the
1405 : basic block for and regions containing the basic block. */
1406 : static void
1407 16744023 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1408 : {
1409 16744023 : int i, freq;
1410 16744023 : unsigned int j, k;
1411 16744023 : basic_block bb;
1412 16744023 : rtx_insn *insn;
1413 16744023 : bitmap_iterator bi;
1414 16744023 : bitmap reg_live_out;
1415 16744023 : unsigned int px;
1416 16744023 : bool set_p;
1417 :
1418 16744023 : bb = loop_tree_node->bb;
1419 16744023 : if (bb != NULL)
1420 : {
1421 71980778 : for (i = 0; i < ira_pressure_classes_num; i++)
1422 : {
1423 57351318 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1424 57351318 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1425 : }
1426 14629460 : curr_bb_node = loop_tree_node;
1427 14629460 : reg_live_out = df_get_live_out (bb);
1428 14629460 : sparseset_clear (objects_live);
1429 29258920 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1430 14629460 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1431 14629460 : hard_reg_set_iterator hrsi;
1432 14629460 : k = 0;
1433 15758855 : EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)
1434 : {
1435 1129395 : enum reg_class aclass, pclass, cl;
1436 :
1437 1129395 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];
1438 1129395 : pclass = ira_pressure_class_translate[aclass];
1439 10719546 : for (j = 0;
1440 10719546 : (cl = ira_reg_class_super_classes[pclass][j])
1441 10719546 : != LIM_REG_CLASSES;
1442 : j++)
1443 : {
1444 9590151 : if (! ira_reg_pressure_class_p[cl])
1445 8460756 : continue;
1446 1129395 : curr_reg_pressure[cl]++;
1447 1129395 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1448 1129395 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1449 1129395 : ira_assert (curr_reg_pressure[cl]
1450 : <= ira_class_hard_regs_num[cl]);
1451 : }
1452 : }
1453 156083548 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1454 141454088 : mark_pseudo_regno_live (j);
1455 :
1456 : #ifdef EH_RETURN_DATA_REGNO
1457 14629460 : process_out_of_region_eh_regs (bb);
1458 : #endif
1459 :
1460 14629460 : freq = REG_FREQ_FROM_BB (bb);
1461 8704974 : if (freq == 0)
1462 2053768 : freq = 1;
1463 :
1464 : /* Invalidate all allocno_saved_at_call entries. */
1465 14629460 : last_call_num++;
1466 :
1467 : /* Scan the code of this basic block, noting which allocnos and
1468 : hard regs are born or die.
1469 :
1470 : Note that this loop treats uninitialized values as live until
1471 : the beginning of the block. For example, if an instruction
1472 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1473 : set, FOO will remain live until the beginning of the block.
1474 : Likewise if FOO is not set at all. This is unnecessarily
1475 : pessimistic, but it probably doesn't matter much in practice. */
1476 178048395 : FOR_BB_INSNS_REVERSE (bb, insn)
1477 : {
1478 163418935 : ira_allocno_t a;
1479 163418935 : df_ref def, use;
1480 163418935 : bool call_p;
1481 :
1482 163418935 : if (!NONDEBUG_INSN_P (insn))
1483 78766276 : continue;
1484 :
1485 84652659 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1486 1477 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1487 1477 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1488 : curr_point);
1489 :
1490 84652659 : call_p = CALL_P (insn);
1491 84652659 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1492 :
1493 : /* Mark each defined value as live. We need to do this for
1494 : unused values because they still conflict with quantities
1495 : that are live at the time of the definition.
1496 :
1497 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1498 : references represent the effect of the called function
1499 : on a call-clobbered register. Marking the register as
1500 : live would stop us from allocating it to a call-crossing
1501 : allocno. */
1502 653625251 : FOR_EACH_INSN_DEF (def, insn)
1503 568972592 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1504 70983182 : mark_ref_live (def);
1505 :
1506 : /* If INSN has multiple outputs, then any value used in one
1507 : of the outputs conflicts with the other outputs. Model this
1508 : by making the used value live during the output phase.
1509 :
1510 : It is unsafe to use !single_set here since it will ignore
1511 : an unused output. Just because an output is unused does
1512 : not mean the compiler can assume the side effect will not
1513 : occur. Consider if ALLOCNO appears in the address of an
1514 : output and we reload the output. If we allocate ALLOCNO
1515 : to the same hard register as an unused output we could
1516 : set the hard register before the output reload insn. */
1517 84652659 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1518 1858736 : FOR_EACH_INSN_USE (use, insn)
1519 : {
1520 1463046 : int i;
1521 1463046 : rtx reg;
1522 :
1523 1463046 : reg = DF_REF_REG (use);
1524 4653070 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1525 : {
1526 3584197 : rtx set;
1527 :
1528 3584197 : set = XVECEXP (PATTERN (insn), 0, i);
1529 3584197 : if (GET_CODE (set) == SET
1530 3584197 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1531 : {
1532 : /* After the previous loop, this is a no-op if
1533 : REG is contained within SET_DEST (SET). */
1534 394173 : mark_ref_live (use);
1535 394173 : break;
1536 : }
1537 : }
1538 : }
1539 :
1540 84652659 : preferred_alternatives = ira_setup_alts (insn);
1541 84652659 : process_register_constraint_filters ();
1542 84652659 : process_dependent_filters ();
1543 84652659 : process_single_reg_class_operands (false, freq);
1544 :
1545 84652659 : if (call_p)
1546 : {
1547 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1548 : there, try to find a pseudo that is live across the call but
1549 : can be cheaply reconstructed from the return value. */
1550 6110291 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1551 6110291 : if (cheap_reg != NULL_RTX)
1552 32716 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1553 :
1554 6110291 : last_call_num++;
1555 6110291 : sparseset_clear (allocnos_processed);
1556 : /* The current set of live allocnos are live across the call. */
1557 470658436 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1558 : {
1559 229218927 : ira_object_t obj = ira_object_id_map[i];
1560 229218927 : a = OBJECT_ALLOCNO (obj);
1561 229218927 : int num = ALLOCNO_NUM (a);
1562 229218927 : function_abi callee_abi = insn_callee_abi (insn);
1563 :
1564 : /* Don't allocate allocnos that cross setjmps or any
1565 : call, if this function receives a nonlocal
1566 : goto. */
1567 229218927 : if (cfun->has_nonlocal_label
1568 229218927 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1569 229216358 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1570 : != NULL_RTX)))
1571 : {
1572 10929 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1573 229218927 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1574 : }
1575 229218927 : eh_region r;
1576 229218927 : if (can_throw_internal (insn)
1577 229218927 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1578 3736519 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1579 229218927 : if (sparseset_bit_p (allocnos_processed, num))
1580 104021992 : continue;
1581 125196935 : sparseset_set_bit (allocnos_processed, num);
1582 :
1583 125196935 : if (allocno_saved_at_call[num] != last_call_num)
1584 : /* Here we are mimicking caller-save.cc behavior
1585 : which does not save hard register at a call if
1586 : it was saved on previous call in the same basic
1587 : block and the hard register was not mentioned
1588 : between the two calls. */
1589 40299814 : ALLOCNO_CALL_FREQ (a) += freq;
1590 : /* Mark it as saved at the next call. */
1591 125196935 : allocno_saved_at_call[num] = last_call_num + 1;
1592 125196935 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1593 125196935 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1594 125196935 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1595 125196935 : |= callee_abi.full_and_partial_reg_clobbers ();
1596 125196935 : if (cheap_reg != NULL_RTX
1597 125196935 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1598 32716 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1599 : }
1600 : }
1601 :
1602 : /* See which defined values die here. Note that we include
1603 : the call insn in the lifetimes of these values, so we don't
1604 : mistakenly consider, for e.g. an addressing mode with a
1605 : side-effect like a post-increment fetching the address,
1606 : that the use happens before the call, and the def to happen
1607 : after the call: we believe both to happen before the actual
1608 : call. (We don't handle return-values here.) */
1609 653625251 : FOR_EACH_INSN_DEF (def, insn)
1610 568972592 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1611 70983182 : mark_ref_dead (def);
1612 :
1613 84652659 : make_early_clobber_and_input_conflicts ();
1614 :
1615 84652659 : curr_point++;
1616 :
1617 : /* Mark each used value as live. */
1618 186785983 : FOR_EACH_INSN_USE (use, insn)
1619 102133324 : mark_ref_live (use);
1620 :
1621 84652659 : process_single_reg_class_operands (true, freq);
1622 :
1623 84652659 : set_p = mark_hard_reg_early_clobbers (insn, true);
1624 :
1625 84652659 : if (set_p)
1626 : {
1627 10722504 : mark_hard_reg_early_clobbers (insn, false);
1628 :
1629 : /* Mark each hard reg as live again. For example, a
1630 : hard register can be in clobber and in an insn
1631 : input. */
1632 26232582 : FOR_EACH_INSN_USE (use, insn)
1633 : {
1634 15510078 : rtx ureg = DF_REF_REG (use);
1635 :
1636 15510078 : if (GET_CODE (ureg) == SUBREG)
1637 328161 : ureg = SUBREG_REG (ureg);
1638 15510078 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1639 9891314 : continue;
1640 :
1641 5618764 : mark_ref_live (use);
1642 : }
1643 : }
1644 :
1645 84652659 : curr_point++;
1646 : }
1647 14629460 : ignore_reg_for_conflicts = NULL_RTX;
1648 :
1649 14629460 : if (bb_has_eh_pred (bb))
1650 222936 : for (j = 0; ; ++j)
1651 : {
1652 668808 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1653 445872 : if (regno == INVALID_REGNUM)
1654 : break;
1655 445872 : make_hard_regno_live (regno);
1656 445872 : }
1657 :
1658 : /* Allocnos can't go in stack regs at the start of a basic block
1659 : that is reached by an abnormal edge. Likewise for registers
1660 : that are at least partly call clobbered, because caller-save,
1661 : fixup_abnormal_edges and possibly the table driven EH machinery
1662 : are not quite ready to handle such allocnos live across such
1663 : edges. */
1664 14629460 : if (bb_has_abnormal_pred (bb))
1665 : {
1666 : #ifdef STACK_REGS
1667 724612 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1668 : {
1669 499235 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1670 :
1671 499235 : ALLOCNO_NO_STACK_REG_P (a) = true;
1672 499235 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1673 : }
1674 2028393 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1675 1803016 : make_hard_regno_live (px);
1676 : #endif
1677 : /* No need to record conflicts for call clobbered regs if we
1678 : have nonlocal labels around, as we don't ever try to
1679 : allocate such regs in this case. */
1680 225377 : if (!cfun->has_nonlocal_label
1681 225377 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1682 20732211 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1683 20509284 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1684 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1685 : /* We should create a conflict of PIC pseudo with
1686 : PIC hard reg as PIC hard reg can have a wrong
1687 : value after jump described by the abnormal edge.
1688 : In this case we cannot allocate PIC hard reg to
1689 : PIC pseudo as PIC pseudo will also have a wrong
1690 : value. This code is not critical as LRA can fix
1691 : it but it is better to have the right allocation
1692 : earlier. */
1693 20648633 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1694 222927 : && pic_offset_table_rtx != NULL_RTX
1695 6303 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1696 : #endif
1697 : )
1698 18549058 : make_hard_regno_live (px);
1699 : }
1700 :
1701 220603720 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1702 205974260 : make_object_dead (ira_object_id_map[i]);
1703 :
1704 14629460 : curr_point++;
1705 :
1706 : }
1707 : /* Propagate register pressure to upper loop tree nodes. */
1708 16744023 : if (loop_tree_node != ira_loop_tree_root)
1709 75037128 : for (i = 0; i < ira_pressure_classes_num; i++)
1710 : {
1711 59798055 : enum reg_class pclass;
1712 :
1713 59798055 : pclass = ira_pressure_classes[i];
1714 59798055 : if (loop_tree_node->reg_pressure[pclass]
1715 59798055 : > loop_tree_node->parent->reg_pressure[pclass])
1716 4241055 : loop_tree_node->parent->reg_pressure[pclass]
1717 4241055 : = loop_tree_node->reg_pressure[pclass];
1718 : }
1719 16744023 : }
1720 :
1721 : /* Create and set up IRA_START_POINT_RANGES and
1722 : IRA_FINISH_POINT_RANGES. */
1723 : static void
1724 3170464 : create_start_finish_chains (void)
1725 : {
1726 3170464 : ira_object_t obj;
1727 3170464 : ira_object_iterator oi;
1728 3170464 : live_range_t r;
1729 :
1730 3170464 : ira_start_point_ranges
1731 3170464 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1732 3170464 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1733 3170464 : ira_finish_point_ranges
1734 3170464 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1735 3170464 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1736 81344656 : FOR_EACH_OBJECT (obj, oi)
1737 184771696 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1738 : {
1739 106597504 : r->start_next = ira_start_point_ranges[r->start];
1740 106597504 : ira_start_point_ranges[r->start] = r;
1741 106597504 : r->finish_next = ira_finish_point_ranges[r->finish];
1742 106597504 : ira_finish_point_ranges[r->finish] = r;
1743 : }
1744 3170464 : }
1745 :
1746 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1747 : new live ranges and program points were added as a result if new
1748 : insn generation. */
1749 : void
1750 1665514 : ira_rebuild_start_finish_chains (void)
1751 : {
1752 1665514 : ira_free (ira_finish_point_ranges);
1753 1665514 : ira_free (ira_start_point_ranges);
1754 1665514 : create_start_finish_chains ();
1755 1665514 : }
1756 :
1757 : /* Compress allocno live ranges by removing program points where
1758 : nothing happens. */
1759 : static void
1760 1504950 : remove_some_program_points_and_update_live_ranges (void)
1761 : {
1762 1504950 : unsigned i;
1763 1504950 : int n;
1764 1504950 : int *map;
1765 1504950 : ira_object_t obj;
1766 1504950 : ira_object_iterator oi;
1767 1504950 : live_range_t r, prev_r, next_r;
1768 1504950 : sbitmap_iterator sbi;
1769 1504950 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1770 :
1771 1504950 : auto_sbitmap born (ira_max_point);
1772 1504950 : auto_sbitmap dead (ira_max_point);
1773 1504950 : bitmap_clear (born);
1774 1504950 : bitmap_clear (dead);
1775 36073845 : FOR_EACH_OBJECT (obj, oi)
1776 88458872 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1777 : {
1778 53889977 : ira_assert (r->start <= r->finish);
1779 53889977 : bitmap_set_bit (born, r->start);
1780 53889977 : bitmap_set_bit (dead, r->finish);
1781 : }
1782 :
1783 1504950 : auto_sbitmap born_or_dead (ira_max_point);
1784 1504950 : bitmap_ior (born_or_dead, born, dead);
1785 1504950 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1786 1504950 : n = -1;
1787 1504950 : prev_born_p = prev_dead_p = false;
1788 67576831 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1789 : {
1790 64566931 : born_p = bitmap_bit_p (born, i);
1791 64566931 : dead_p = bitmap_bit_p (dead, i);
1792 64566931 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1793 58393188 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1794 16277666 : map[i] = n;
1795 : else
1796 48289265 : map[i] = ++n;
1797 64566931 : prev_born_p = born_p;
1798 64566931 : prev_dead_p = dead_p;
1799 : }
1800 :
1801 1504950 : n++;
1802 1504950 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1803 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1804 95 : ira_max_point, n, 100 * n / ira_max_point);
1805 1504950 : ira_max_point = n;
1806 :
1807 36073845 : FOR_EACH_OBJECT (obj, oi)
1808 88458872 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1809 : {
1810 53889977 : next_r = r->next;
1811 53889977 : r->start = map[r->start];
1812 53889977 : r->finish = map[r->finish];
1813 53889977 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1814 : {
1815 41234654 : prev_r = r;
1816 41234654 : continue;
1817 : }
1818 12655323 : prev_r->start = r->start;
1819 12655323 : prev_r->next = next_r;
1820 12655323 : ira_finish_live_range (r);
1821 : }
1822 :
1823 1504950 : ira_free (map);
1824 1504950 : }
1825 :
1826 : /* Print live ranges R to file F. */
1827 : void
1828 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1829 : {
1830 3234 : for (; r != NULL; r = r->next)
1831 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1832 1466 : fprintf (f, "\n");
1833 1466 : }
1834 :
1835 : DEBUG_FUNCTION void
1836 0 : debug (live_range &ref)
1837 : {
1838 0 : ira_print_live_range_list (stderr, &ref);
1839 0 : }
1840 :
1841 : DEBUG_FUNCTION void
1842 0 : debug (live_range *ptr)
1843 : {
1844 0 : if (ptr)
1845 0 : debug (*ptr);
1846 : else
1847 0 : fprintf (stderr, "<nil>\n");
1848 0 : }
1849 :
1850 : /* Print live ranges R to stderr. */
1851 : void
1852 0 : ira_debug_live_range_list (live_range_t r)
1853 : {
1854 0 : ira_print_live_range_list (stderr, r);
1855 0 : }
1856 :
1857 : /* Print live ranges of object OBJ to file F. */
1858 : static void
1859 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1860 : {
1861 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1862 0 : }
1863 :
1864 : /* Print live ranges of allocno A to file F. */
1865 : static void
1866 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1867 : {
1868 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1869 1328 : int i;
1870 :
1871 2656 : for (i = 0; i < n; i++)
1872 : {
1873 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1874 1328 : if (n > 1)
1875 0 : fprintf (f, " [%d]", i);
1876 1328 : fprintf (f, "):");
1877 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1878 : }
1879 1328 : }
1880 :
1881 : /* Print live ranges of allocno A to stderr. */
1882 : void
1883 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1884 : {
1885 0 : print_allocno_live_ranges (stderr, a);
1886 0 : }
1887 :
1888 : /* Print live ranges of all allocnos to file F. */
1889 : static void
1890 190 : print_live_ranges (FILE *f)
1891 : {
1892 190 : ira_allocno_t a;
1893 190 : ira_allocno_iterator ai;
1894 :
1895 1518 : FOR_EACH_ALLOCNO (a, ai)
1896 1328 : print_allocno_live_ranges (f, a);
1897 190 : }
1898 :
1899 : /* Print live ranges of all allocnos to stderr. */
1900 : void
1901 0 : ira_debug_live_ranges (void)
1902 : {
1903 0 : print_live_ranges (stderr);
1904 0 : }
1905 :
1906 : /* The main entry function creates live ranges, set up
1907 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1908 : calculate register pressure info. */
1909 : void
1910 1504950 : ira_create_allocno_live_ranges (void)
1911 : {
1912 1504950 : objects_live = sparseset_alloc (ira_objects_num);
1913 1504950 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1914 1504950 : curr_point = 0;
1915 1504950 : last_call_num = 0;
1916 1504950 : allocno_saved_at_call
1917 1504950 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1918 1504950 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1919 1504950 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1920 : process_bb_node_lives);
1921 1504950 : ira_max_point = curr_point;
1922 1504950 : create_start_finish_chains ();
1923 1504950 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1924 95 : print_live_ranges (ira_dump_file);
1925 : /* Clean up. */
1926 1504950 : ira_free (allocno_saved_at_call);
1927 1504950 : sparseset_free (objects_live);
1928 1504950 : sparseset_free (allocnos_processed);
1929 1504950 : }
1930 :
1931 : /* Compress allocno live ranges. */
1932 : void
1933 1504950 : ira_compress_allocno_live_ranges (void)
1934 : {
1935 1504950 : remove_some_program_points_and_update_live_ranges ();
1936 1504950 : ira_rebuild_start_finish_chains ();
1937 1504950 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1938 : {
1939 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1940 95 : print_live_ranges (ira_dump_file);
1941 : }
1942 1504950 : }
1943 :
1944 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1945 : void
1946 1504950 : ira_finish_allocno_live_ranges (void)
1947 : {
1948 1504950 : ira_free (ira_finish_point_ranges);
1949 1504950 : ira_free (ira_start_point_ranges);
1950 1504950 : }
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