Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 37948733 : make_hard_regno_live (int regno)
98 : {
99 37948733 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 0 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 15246186 : make_hard_regno_dead (int regno)
106 : {
107 15246186 : unsigned int i;
108 281188376 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 265942190 : ira_object_t obj = ira_object_id_map[i];
111 :
112 267658622 : if (ignore_reg_for_conflicts != NULL_RTX
113 174755837 : && REGNO (ignore_reg_for_conflicts)
114 174755837 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1716432 : continue;
116 :
117 264225758 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 264225758 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 15246186 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 15246186 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 244649080 : make_object_live (ira_object_t obj)
127 : {
128 244649080 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 244649080 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 244649080 : if (lr == NULL
132 207242813 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 55443830 : ira_add_live_range_to_object (obj, curr_point, -1);
134 244649080 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 252214294 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 252214294 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 252214294 : int start, i;
143 252214294 : enum reg_class aclass, pclass, cl;
144 252214294 : live_range_t p;
145 :
146 252214294 : aclass = ALLOCNO_CLASS (a);
147 252214294 : pclass = ira_pressure_class_translate[aclass];
148 2475644127 : for (i = 0;
149 2475644127 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2223429833 : if (! ira_reg_pressure_class_p[cl])
153 1976304035 : continue;
154 247125798 : if (high_pressure_start_point[cl] < 0)
155 75494202 : continue;
156 171631596 : p = OBJECT_LIVE_RANGES (obj);
157 171631596 : ira_assert (p != NULL);
158 171631596 : start = (high_pressure_start_point[cl] > p->start
159 171631596 : ? high_pressure_start_point[cl] : p->start);
160 171631596 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 252214294 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 244649080 : make_object_dead (ira_object_t obj)
168 : {
169 244649080 : live_range_t lr;
170 244649080 : int regno;
171 244649080 : int ignore_regno = -1;
172 244649080 : int ignore_total_regno = -1;
173 244649080 : int end_regno = -1;
174 :
175 244649080 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 244649080 : if (ignore_reg_for_conflicts != NULL_RTX
180 244649080 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3479409 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3479409 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6958818 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3479409 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 525780 : ignore_regno = end_regno;
189 3479409 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 525780 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 978596320 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 247602709 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 247602709 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2953629 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 247602709 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2953629 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 244649080 : lr = OBJECT_LIVE_RANGES (obj);
205 244649080 : ira_assert (lr != NULL);
206 244649080 : lr->finish = curr_point;
207 244649080 : update_allocno_pressure_excess_length (obj);
208 244649080 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 261499217 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 261499217 : int i;
222 261499217 : enum reg_class cl;
223 :
224 2565953345 : for (i = 0;
225 2565953345 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2304454128 : if (! ira_reg_pressure_class_p[cl])
229 2047769940 : continue;
230 256684188 : curr_reg_pressure[cl] += n;
231 256684188 : if (high_pressure_start_point[cl] < 0
232 107416325 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1805820 : high_pressure_start_point[cl] = curr_point;
234 256684188 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 221378538 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 261499217 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 53376920 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 53376920 : int i;
248 53376920 : unsigned int j;
249 53376920 : enum reg_class cl;
250 53376920 : bool set_p = false;
251 :
252 53376920 : for (i = 0;
253 518057879 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 464680959 : if (! ira_reg_pressure_class_p[cl])
257 411811840 : continue;
258 52869119 : curr_reg_pressure[cl] -= nregs;
259 52869119 : ira_assert (curr_reg_pressure[cl] >= 0);
260 52869119 : if (high_pressure_start_point[cl] >= 0
261 4799752 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 464680959 : set_p = true;
263 : }
264 53376920 : if (set_p)
265 : {
266 8056127 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7565214 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4666327 : for (i = 0;
269 5157240 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4666327 : if (! ira_reg_pressure_class_p[cl])
273 4175414 : continue;
274 490913 : if (high_pressure_start_point[cl] >= 0
275 490913 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 490913 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 53376920 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 122868 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 122868 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 122868 : ira_object_t obj;
288 :
289 122868 : if (a == NULL)
290 : return false;
291 122868 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 122868 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 122868 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 230120592 : mark_pseudo_regno_live (int regno)
303 : {
304 230120592 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 230120592 : enum reg_class pclass;
306 230120592 : int i, n, nregs;
307 :
308 230120592 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 230120592 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 230120592 : n = ALLOCNO_NUM_OBJECTS (a);
315 230120592 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 230120592 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 230120592 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69959516 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 530200700 : for (i = 0; i < n; i++)
325 : {
326 300080108 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 300080108 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 55757918 : continue;
330 :
331 244322190 : inc_register_pressure (pclass, nregs);
332 244322190 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 868493 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 868493 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 868493 : int n;
344 868493 : enum reg_class pclass;
345 868493 : ira_object_t obj;
346 :
347 868493 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 868493 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 868493 : n = ALLOCNO_NUM_OBJECTS (a);
354 868493 : if (n == 1)
355 : {
356 40605 : mark_pseudo_regno_live (regno);
357 40605 : return;
358 : }
359 :
360 827888 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 827888 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 827888 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 827888 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 326890 : inc_register_pressure (pclass, 1);
369 326890 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 104506851 : mark_hard_reg_live (rtx reg)
377 : {
378 104506851 : int regno = REGNO (reg);
379 :
380 104506851 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 31830975 : int last = END_REGNO (reg);
383 31830975 : enum reg_class aclass, pclass;
384 :
385 63661950 : while (regno < last)
386 : {
387 31830975 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 31830975 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 16850137 : aclass = ira_hard_regno_allocno_class[regno];
391 16850137 : pclass = ira_pressure_class_translate[aclass];
392 16850137 : inc_register_pressure (pclass, 1);
393 16850137 : make_hard_regno_live (regno);
394 : }
395 31830975 : regno++;
396 : }
397 : }
398 104506851 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 88911167 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 88911167 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1296606 : mark_pseudo_regno_subword_live (regno,
409 868493 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 88042674 : mark_pseudo_regno_live (regno);
413 88911167 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 191540678 : mark_ref_live (df_ref ref)
418 : {
419 191540678 : rtx reg = DF_REF_REG (ref);
420 191540678 : rtx orig_reg = reg;
421 :
422 191540678 : if (GET_CODE (reg) == SUBREG)
423 3095793 : reg = SUBREG_REG (reg);
424 :
425 191540678 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 87033827 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 104506851 : mark_hard_reg_live (reg);
429 191540678 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 36483933 : mark_pseudo_regno_dead (int regno)
435 : {
436 36483933 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 36483933 : int n, i, nregs;
438 36483933 : enum reg_class cl;
439 :
440 36483933 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 36483933 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 36483933 : n = ALLOCNO_NUM_OBJECTS (a);
447 36483933 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 36483933 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 36483933 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1308178 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 74276044 : for (i = 0; i < n; i++)
456 : {
457 37792111 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 37792111 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3647 : continue;
460 :
461 37788464 : dec_register_pressure (cl, nregs);
462 37788464 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 347137 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 347137 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 347137 : int n;
473 347137 : enum reg_class cl;
474 347137 : ira_object_t obj;
475 :
476 347137 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 347137 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 347137 : n = ALLOCNO_NUM_OBJECTS (a);
483 347137 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 342270 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 342270 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 342270 : obj = ALLOCNO_OBJECT (a, subword);
492 342270 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 342270 : dec_register_pressure (cl, 1);
496 342270 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 47580929 : mark_hard_reg_dead (rtx reg)
503 : {
504 47580929 : int regno = REGNO (reg);
505 :
506 47580929 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 15248204 : int last = END_REGNO (reg);
509 15248204 : enum reg_class aclass, pclass;
510 :
511 30496408 : while (regno < last)
512 : {
513 15248204 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 15246186 : aclass = ira_hard_regno_allocno_class[regno];
516 15246186 : pclass = ira_pressure_class_translate[aclass];
517 15246186 : dec_register_pressure (pclass, 1);
518 15246186 : make_hard_regno_dead (regno);
519 : }
520 15248204 : regno++;
521 : }
522 : }
523 47580929 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 36831070 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 36831070 : if (read_modify_subreg_p (orig_reg))
532 : {
533 522219 : mark_pseudo_regno_subword_dead (regno,
534 347137 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 36483933 : mark_pseudo_regno_dead (regno);
538 36831070 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 82538905 : mark_ref_dead (df_ref def)
544 : {
545 82538905 : rtx reg = DF_REF_REG (def);
546 82538905 : rtx orig_reg = reg;
547 :
548 82538905 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 82538905 : if (GET_CODE (reg) == SUBREG)
552 931689 : reg = SUBREG_REG (reg);
553 :
554 82538905 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 82538905 : && (GET_CODE (orig_reg) != SUBREG
556 335709 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 335709 : || !read_modify_subreg_p (orig_reg)))
558 : return;
559 :
560 82534659 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 34953730 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 47580929 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2922304 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2922304 : rtx orig_reg = reg;
577 2922304 : ira_allocno_t a;
578 :
579 2922304 : if (GET_CODE (reg) == SUBREG)
580 86060 : reg = SUBREG_REG (reg);
581 :
582 2922304 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 1016260 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 1016260 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 938670 : if (advance_p)
590 893855 : curr_point++;
591 :
592 938670 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 938670 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 938670 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 938670 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 938670 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 2971583 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 2971583 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2906821 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2906821 : if (use < recog_data.n_operands - 1
624 1136955 : && recog_data.constraints[use][0] == '%')
625 6449 : advance_p
626 6449 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2906821 : if (use >= 1
629 2906525 : && recog_data.constraints[use - 1][0] == '%')
630 9034 : advance_p
631 9034 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14610908 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14610908 : int use, use_match;
662 14610908 : ira_allocno_t a;
663 14610908 : enum reg_class use_cl, acl;
664 14610908 : bool advance_p;
665 14610908 : rtx dreg = recog_data.operand[def];
666 14610908 : rtx orig_dreg = dreg;
667 :
668 14610908 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14610908 : if (GET_CODE (dreg) == SUBREG)
672 111858 : dreg = SUBREG_REG (dreg);
673 :
674 14610908 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 12391925 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 12391925 : acl = ALLOCNO_CLASS (a);
679 12391925 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 12194969 : advance_p = true;
683 :
684 12194969 : int n_operands = recog_data.n_operands;
685 12194969 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 50489402 : for (use = 0; use < n_operands; use++)
687 : {
688 38294433 : int alt1;
689 :
690 38294433 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 12358374 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 38050920 : if (op_alt[use].matches == def
701 25936059 : || (for_tie_p
702 13559167 : && rtx_equal_p (recog_data.operand[use],
703 13559167 : recog_data.operand[op_alt[def].matched])))
704 12114861 : continue;
705 :
706 13821198 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 12106278 : use_cl = op_alt[use].cl;
710 12106278 : if (use_cl == NO_REGS)
711 4805582 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 9015616 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 1013767 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 21219036 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 18247454 : if (!TEST_BIT (preferred_alternatives, alt1))
730 8725967 : continue;
731 9521487 : const operand_alternative *op_alt1
732 9521487 : = &recog_op_alt[alt1 * n_operands];
733 9521487 : if (op_alt1[use].matches == def
734 7620726 : || (use < n_operands - 1
735 2864309 : && recog_data.constraints[use][0] == '%'
736 8105 : && op_alt1[use + 1].matches == def)
737 7620726 : || (use >= 1
738 7619208 : && recog_data.constraints[use - 1][0] == '%'
739 3132784 : && op_alt1[use - 1].matches == def))
740 : break;
741 4498632 : if (for_tie_p
742 4279134 : && !op_alt1[def].earlyclobber
743 4277962 : && op_alt1[def].matched < 0
744 29409 : && alternative_class (op_alt1, def) != NO_REGS
745 4528041 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 8001849 : if (alt1 < recog_data.n_alternatives)
750 5030267 : continue;
751 :
752 2971582 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 2971582 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 85362739 : make_early_clobber_and_input_conflicts (void)
779 : {
780 85362739 : int alt;
781 85362739 : int def, def_match;
782 85362739 : enum reg_class def_cl;
783 :
784 85362739 : int n_alternatives = recog_data.n_alternatives;
785 85362739 : int n_operands = recog_data.n_operands;
786 85362739 : const operand_alternative *op_alt = recog_op_alt;
787 1180118198 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1094755459 : if (TEST_BIT (preferred_alternatives, alt))
789 393003150 : for (def = 0; def < n_operands; def++)
790 : {
791 271271715 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 256884850 : def_cl = op_alt[def].cl;
795 256884850 : if (def_cl != NO_REGS)
796 : {
797 214917285 : if (op_alt[def].earlyclobber)
798 145482 : check_and_make_def_conflict (alt, def, def_cl, false);
799 214771803 : else if (op_alt[def].matched >= 0
800 214771803 : && !targetm.class_likely_spilled_p (def_cl))
801 14425702 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 271271715 : if ((def_match = op_alt[def].matches) >= 0
805 271271715 : && (op_alt[def_match].earlyclobber
806 15128492 : || op_alt[def].earlyclobber))
807 : {
808 39724 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 39724 : def_cl = op_alt[def_match].cl;
812 39724 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 85362739 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 96141193 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 96141193 : df_ref def;
823 96141193 : bool set_p = false;
824 :
825 690525277 : FOR_EACH_INSN_DEF (def, insn)
826 594384084 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 22004337 : rtx dreg = DF_REF_REG (def);
829 :
830 22004337 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 22004337 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 154425 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 21849912 : if (live_p)
839 10924956 : mark_ref_live (def);
840 : else
841 10924956 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 96141193 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the class of the hard register.
850 : Otherwise it returns NO_REGS. */
851 : static enum reg_class
852 180645732 : single_reg_class (const char *constraints, rtx op, rtx equiv_const)
853 : {
854 180645732 : int c;
855 180645732 : enum reg_class cl, next_cl;
856 180645732 : enum constraint_num cn;
857 :
858 180645732 : cl = NO_REGS;
859 180645732 : alternative_mask preferred = preferred_alternatives;
860 944762470 : while ((c = *constraints))
861 : {
862 930472712 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 930472712 : else if (c == ',')
865 254758353 : preferred >>= 1;
866 675714359 : else if (preferred & 1)
867 203474661 : switch (c)
868 : {
869 : case 'g':
870 : return NO_REGS;
871 :
872 183194950 : default:
873 : /* ??? Is this the best way to handle memory constraints? */
874 183194950 : cn = lookup_constraint (constraints);
875 183194950 : if (insn_extra_memory_constraint (cn)
876 170981991 : || insn_extra_special_memory_constraint (cn)
877 : || insn_extra_relaxed_memory_constraint (cn)
878 354176939 : || insn_extra_address_constraint (cn))
879 : return NO_REGS;
880 170398324 : if (constraint_satisfied_p (op, cn)
881 170398324 : || (equiv_const != NULL_RTX
882 0 : && CONSTANT_P (equiv_const)
883 0 : && constraint_satisfied_p (equiv_const, cn)))
884 : return NO_REGS;
885 155599056 : next_cl = reg_class_for_constraint (cn);
886 123762471 : if (next_cl == NO_REGS)
887 : break;
888 120515375 : if (cl == NO_REGS
889 120515375 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
890 1003910 : : (ira_class_singleton[cl][GET_MODE (op)]
891 1003910 : != ira_class_singleton[next_cl][GET_MODE (op)]))
892 : return NO_REGS;
893 : cl = next_cl;
894 : break;
895 :
896 13067592 : case '0': case '1': case '2': case '3': case '4':
897 13067592 : case '5': case '6': case '7': case '8': case '9':
898 13067592 : {
899 13067592 : char *end;
900 13067592 : unsigned long dup = strtoul (constraints, &end, 10);
901 13067592 : constraints = end;
902 13067592 : next_cl
903 13067592 : = single_reg_class (recog_data.constraints[dup],
904 : recog_data.operand[dup], NULL_RTX);
905 13067592 : if (cl == NO_REGS
906 13067592 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
907 19144 : : (ira_class_singleton[cl][GET_MODE (op)]
908 19144 : != ira_class_singleton[next_cl][GET_MODE (op)]))
909 12834838 : return NO_REGS;
910 232754 : cl = next_cl;
911 232754 : continue;
912 232754 : }
913 : }
914 763883984 : constraints += CONSTRAINT_LEN (c, constraints);
915 : }
916 : return cl;
917 : }
918 :
919 : /* The function checks that operand OP_NUM of the current insn can use
920 : only one hard register. If it is so, the function returns the
921 : class of the hard register. Otherwise it returns NO_REGS. */
922 : static enum reg_class
923 182948658 : single_reg_operand_class (int op_num)
924 : {
925 182948658 : if (op_num < 0 || recog_data.n_alternatives == 0)
926 : return NO_REGS;
927 167578140 : return single_reg_class (recog_data.constraints[op_num],
928 167578140 : recog_data.operand[op_num], NULL_RTX);
929 : }
930 :
931 : /* The function sets up hard register set *SET to hard registers which
932 : might be used by insn reloads because the constraints are too
933 : strict. */
934 : void
935 27776 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
936 : alternative_mask preferred)
937 : {
938 27776 : int i, c, regno = 0;
939 27776 : enum reg_class cl;
940 27776 : rtx op;
941 27776 : machine_mode mode;
942 :
943 27776 : CLEAR_HARD_REG_SET (*set);
944 85808 : for (i = 0; i < recog_data.n_operands; i++)
945 : {
946 58032 : op = recog_data.operand[i];
947 :
948 58032 : if (GET_CODE (op) == SUBREG)
949 1057 : op = SUBREG_REG (op);
950 :
951 58032 : if (GET_CODE (op) == SCRATCH
952 58032 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
953 : {
954 38961 : const char *p = recog_data.constraints[i];
955 :
956 77922 : mode = (GET_CODE (op) == SCRATCH
957 38961 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
958 38961 : cl = NO_REGS;
959 38961 : for (alternative_mask curr_preferred = preferred;
960 1426644 : (c = *p);
961 1387683 : p += CONSTRAINT_LEN (c, p))
962 1387683 : if (c == '#')
963 0 : curr_preferred &= ~ALTERNATIVE_BIT (0);
964 1387683 : else if (c == ',')
965 473190 : curr_preferred >>= 1;
966 914493 : else if (curr_preferred & 1)
967 : {
968 571443 : cl = reg_class_for_constraint (lookup_constraint (p));
969 247299 : if (cl != NO_REGS)
970 : {
971 : /* There is no register pressure problem if all of the
972 : regs in this class are fixed. */
973 243603 : int regno = ira_class_singleton[cl][mode];
974 243603 : if (regno >= 0)
975 1647 : add_to_hard_reg_set (set, mode, regno);
976 : }
977 327840 : else if (c == '{')
978 : {
979 0 : int regno = decode_hard_reg_constraint (p);
980 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
981 0 : add_to_hard_reg_set (set, mode, regno);
982 : }
983 : }
984 : }
985 : }
986 27776 : }
987 : /* Processes input operands, if IN_P, or output operands otherwise of
988 : the current insn with FREQ to find allocno which can use only one
989 : hard register and makes other currently living allocnos conflicting
990 : with the hard register. */
991 : static void
992 170725478 : process_single_reg_class_operands (bool in_p, int freq)
993 : {
994 170725478 : int i, regno;
995 170725478 : unsigned int px;
996 170725478 : enum reg_class cl;
997 170725478 : rtx operand;
998 170725478 : ira_allocno_t operand_a, a;
999 :
1000 536462864 : for (i = 0; i < recog_data.n_operands; i++)
1001 : {
1002 365737386 : operand = recog_data.operand[i];
1003 365737386 : if (in_p && recog_data.operand_type[i] != OP_IN
1004 62352778 : && recog_data.operand_type[i] != OP_INOUT)
1005 62272813 : continue;
1006 182868693 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1007 120595880 : && recog_data.operand_type[i] != OP_INOUT)
1008 120515915 : continue;
1009 182948658 : cl = single_reg_operand_class (i);
1010 182948658 : if (cl == NO_REGS)
1011 182169717 : continue;
1012 :
1013 778941 : operand_a = NULL;
1014 :
1015 778941 : if (GET_CODE (operand) == SUBREG)
1016 59646 : operand = SUBREG_REG (operand);
1017 :
1018 778941 : if (REG_P (operand)
1019 778941 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1020 : {
1021 774380 : enum reg_class aclass;
1022 :
1023 774380 : operand_a = ira_curr_regno_allocno_map[regno];
1024 774380 : aclass = ALLOCNO_CLASS (operand_a);
1025 774380 : if (ira_class_subset_p[cl][aclass])
1026 : {
1027 : /* View the desired allocation of OPERAND as:
1028 :
1029 : (REG:YMODE YREGNO),
1030 :
1031 : a simplification of:
1032 :
1033 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1034 766022 : machine_mode ymode, xmode;
1035 766022 : int xregno, yregno;
1036 766022 : poly_int64 offset;
1037 :
1038 766022 : xmode = recog_data.operand_mode[i];
1039 766022 : xregno = ira_class_singleton[cl][xmode];
1040 766022 : gcc_assert (xregno >= 0);
1041 766022 : ymode = ALLOCNO_MODE (operand_a);
1042 766022 : offset = subreg_lowpart_offset (ymode, xmode);
1043 766022 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1044 766022 : if (yregno >= 0
1045 766022 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1046 : {
1047 766022 : int cost;
1048 :
1049 766022 : ira_allocate_and_set_costs
1050 766022 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1051 : aclass, 0);
1052 766022 : ira_init_register_move_cost_if_necessary (xmode);
1053 1532044 : cost = freq * (in_p
1054 766022 : ? ira_register_move_cost[xmode][aclass][cl]
1055 444726 : : ira_register_move_cost[xmode][cl][aclass]);
1056 766022 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1057 766022 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1058 : }
1059 : }
1060 : }
1061 :
1062 31265214 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1063 : {
1064 30486273 : ira_object_t obj = ira_object_id_map[px];
1065 30486273 : a = OBJECT_ALLOCNO (obj);
1066 30486273 : if (a != operand_a)
1067 : {
1068 : /* We could increase costs of A instead of making it
1069 : conflicting with the hard register. But it works worse
1070 : because it will be spilled in reload in anyway. */
1071 118694280 : OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1072 30486273 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1073 : }
1074 : }
1075 : }
1076 170725478 : }
1077 :
1078 : /* Go through the operands of the extracted insn looking for operand
1079 : alternatives that apply a register filter. Record any such filters
1080 : in the operand's allocno. */
1081 : static void
1082 85362739 : process_register_constraint_filters ()
1083 : {
1084 268231432 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1085 : {
1086 182868693 : rtx op = recog_data.operand[opno];
1087 182868693 : if (SUBREG_P (op))
1088 3055408 : op = SUBREG_REG (op);
1089 182868693 : if (REG_P (op) && !HARD_REGISTER_P (op))
1090 : {
1091 75764203 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1092 1083699195 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1093 : {
1094 1007934992 : if (!TEST_BIT (preferred_alternatives, alt))
1095 882785591 : continue;
1096 :
1097 125149401 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1098 125149401 : auto cl = alternative_class (op_alt, opno);
1099 : /* The two extremes are easy:
1100 :
1101 : - We should record the filter if CL matches the
1102 : allocno class.
1103 :
1104 : - We should ignore the filter if CL and the allocno class
1105 : are disjoint. We'll either pick a different alternative
1106 : or reload the operand.
1107 :
1108 : Things are trickier if the classes overlap. However:
1109 :
1110 : - If the allocno class includes registers that are not
1111 : in CL, some choices of hard register will need a reload
1112 : anyway. It isn't obvious that reloads due to filters
1113 : are worse than reloads due to regnos being outside CL.
1114 :
1115 : - Conversely, if the allocno class is a subset of CL,
1116 : any allocation will satisfy the class requirement.
1117 : We should try to make sure it satisfies the filter
1118 : requirement too. This is useful if, for example,
1119 : an allocno needs to be in "low" registers to satisfy
1120 : some uses, and its allocno class is therefore those
1121 : low registers, but the allocno is elsewhere allowed
1122 : to be in any even-numbered register. Picking an
1123 : even-numbered low register satisfies both types of use. */
1124 125149401 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1125 29352513 : continue;
1126 :
1127 95796888 : auto filters = alternative_register_filters (op_alt, opno);
1128 95796888 : if (!filters)
1129 95796888 : continue;
1130 :
1131 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1132 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1133 : }
1134 : }
1135 : }
1136 85362739 : }
1137 :
1138 : /* Append a dependent filter ID with mode MODE, referenced allocno
1139 : REF_ALLOCNO, hardreg REF_HARD_REGNO, and REF_MODE to allocno A. */
1140 :
1141 : void
1142 0 : ira_add_dependent_filter (ira_allocno_t a, int id,
1143 : machine_mode mode, ira_allocno_t ref_allocno,
1144 : unsigned int ref_hard_regno, machine_mode ref_mode)
1145 : {
1146 : /* Check if we already have the filter that should be added.
1147 : This is a linear search and the assumption is that we'll never
1148 : have more than a handful of dependent filters. Right now, the
1149 : maximum is 32 (see gensupport.cc). */
1150 0 : for (auto *filter = ALLOCNO_DEPENDENT_FILTERS (a);
1151 0 : filter;
1152 0 : filter = filter->next)
1153 0 : if (filter->id == id
1154 0 : && filter->ref_allocno == ref_allocno
1155 0 : && filter->ref_hard_regno == ref_hard_regno
1156 0 : && filter->mode == mode
1157 0 : && filter->ref_mode == ref_mode)
1158 : return;
1159 :
1160 0 : auto *filter = (ira_dependent_filter *)
1161 0 : ira_allocate (sizeof (ira_dependent_filter));
1162 0 : filter->id = id;
1163 0 : filter->ref_allocno = ref_allocno;
1164 0 : filter->ref_hard_regno = ref_hard_regno;
1165 0 : filter->mode = mode;
1166 0 : filter->ref_mode = ref_mode;
1167 0 : filter->next = ALLOCNO_DEPENDENT_FILTERS (a);
1168 0 : ALLOCNO_DEPENDENT_FILTERS (a) = filter;
1169 : }
1170 :
1171 : /* Walk the operand alternatives of the current insn. For each
1172 : operand with a dependent-filter constraint, add one
1173 : ira_dependent_filter in the appropriate allocno. */
1174 :
1175 : static void
1176 0 : process_dependent_filters ()
1177 : {
1178 0 : if (!NUM_DEPENDENT_FILTERS)
1179 0 : return;
1180 :
1181 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1182 : {
1183 : rtx op = recog_data.operand[opno];
1184 : if (SUBREG_P (op))
1185 : op = SUBREG_REG (op);
1186 : if (!REG_P (op) || HARD_REGISTER_P (op))
1187 : continue;
1188 :
1189 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1190 :
1191 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1192 : {
1193 : if (!TEST_BIT (preferred_alternatives, alt))
1194 : continue;
1195 :
1196 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1197 : auto cl = alternative_class (op_alt, opno);
1198 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1199 : continue;
1200 :
1201 : auto dep_filter_mask = alternative_dependent_filters (op_alt, opno);
1202 : if (!dep_filter_mask)
1203 : continue;
1204 :
1205 : for (int id = 0; id < NUM_DEPENDENT_FILTERS; ++id)
1206 : {
1207 : if (!(dep_filter_mask & (1U << id)))
1208 : continue;
1209 :
1210 : int ref_opno = get_dependent_filter_ref (id);
1211 : if (ref_opno < 0 || ref_opno >= recog_data.n_operands)
1212 : continue;
1213 : rtx ref_op = recog_data.operand[ref_opno];
1214 : if (SUBREG_P (ref_op))
1215 : ref_op = SUBREG_REG (ref_op);
1216 : if (!REG_P (ref_op))
1217 : continue;
1218 :
1219 : ira_allocno_t ref_a = NULL;
1220 : unsigned int ref_hard_regno = INVALID_REGNUM;
1221 : if (HARD_REGISTER_P (ref_op))
1222 : ref_hard_regno = REGNO (ref_op);
1223 : else
1224 : ref_a = ira_curr_regno_allocno_map[REGNO (ref_op)];
1225 :
1226 : ira_add_dependent_filter (a, id, GET_MODE (op),
1227 : ref_a, ref_hard_regno,
1228 : GET_MODE (ref_op));
1229 : }
1230 : }
1231 : }
1232 : }
1233 :
1234 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1235 : we find a SET rtx that we can use to deduce that a register can be cheaply
1236 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1237 : static rtx
1238 6148305 : find_call_crossed_cheap_reg (rtx_insn *insn)
1239 : {
1240 6148305 : rtx cheap_reg = NULL_RTX;
1241 6148305 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1242 :
1243 18043537 : while (exp != NULL)
1244 : {
1245 12050218 : rtx x = XEXP (exp, 0);
1246 12050218 : if (GET_CODE (x) == SET)
1247 : {
1248 : exp = x;
1249 : break;
1250 : }
1251 11895232 : exp = XEXP (exp, 1);
1252 : }
1253 6148305 : if (exp != NULL)
1254 : {
1255 154986 : basic_block bb = BLOCK_FOR_INSN (insn);
1256 154986 : rtx reg = SET_SRC (exp);
1257 154986 : rtx_insn *prev = PREV_INSN (insn);
1258 309991 : while (prev && !(INSN_P (prev)
1259 154986 : && BLOCK_FOR_INSN (prev) != bb))
1260 : {
1261 155005 : if (NONDEBUG_INSN_P (prev))
1262 : {
1263 154986 : rtx set = single_set (prev);
1264 :
1265 154986 : if (set && rtx_equal_p (SET_DEST (set), reg))
1266 : {
1267 154986 : rtx src = SET_SRC (set);
1268 123279 : if (!REG_P (src) || HARD_REGISTER_P (src)
1269 277854 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1270 : break;
1271 33345 : if (!modified_between_p (src, prev, insn))
1272 6148305 : cheap_reg = src;
1273 : break;
1274 : }
1275 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1276 : {
1277 0 : rtx dest = SET_DEST (set);
1278 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1279 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1280 : break;
1281 0 : if (!modified_between_p (dest, prev, insn))
1282 6148305 : cheap_reg = dest;
1283 : break;
1284 : }
1285 :
1286 0 : if (reg_set_p (reg, prev))
1287 : break;
1288 : }
1289 19 : prev = PREV_INSN (prev);
1290 : }
1291 : }
1292 6148305 : return cheap_reg;
1293 : }
1294 :
1295 : /* Determine whether INSN is a register to register copy of the type where
1296 : we do not need to make the source and destiniation registers conflict.
1297 : If this is a copy instruction, then return the source reg. Otherwise,
1298 : return NULL_RTX. */
1299 : rtx
1300 313589977 : non_conflicting_reg_copy_p (rtx_insn *insn)
1301 : {
1302 : /* Reload has issues with overlapping pseudos being assigned to the
1303 : same hard register, so don't allow it. See PR87600 for details. */
1304 313589977 : if (!targetm.lra_p ())
1305 : return NULL_RTX;
1306 :
1307 313589977 : rtx set = single_set (insn);
1308 :
1309 : /* Disallow anything other than a simple register to register copy
1310 : that has no side effects. */
1311 313589977 : if (set == NULL_RTX
1312 298142770 : || !REG_P (SET_DEST (set))
1313 219612410 : || !REG_P (SET_SRC (set))
1314 387749494 : || side_effects_p (set))
1315 : return NULL_RTX;
1316 :
1317 74159517 : int dst_regno = REGNO (SET_DEST (set));
1318 74159517 : int src_regno = REGNO (SET_SRC (set));
1319 74159517 : machine_mode mode = GET_MODE (SET_DEST (set));
1320 :
1321 : /* By definition, a register does not conflict with itself, therefore we
1322 : do not have to handle it specially. Returning NULL_RTX now, helps
1323 : simplify the callers of this function. */
1324 74159517 : if (dst_regno == src_regno)
1325 : return NULL_RTX;
1326 :
1327 : /* Computing conflicts for register pairs is difficult to get right, so
1328 : for now, disallow it. */
1329 74159517 : if ((HARD_REGISTER_NUM_P (dst_regno)
1330 20472594 : && hard_regno_nregs (dst_regno, mode) != 1)
1331 94465260 : || (HARD_REGISTER_NUM_P (src_regno)
1332 10643378 : && hard_regno_nregs (src_regno, mode) != 1))
1333 311778 : return NULL_RTX;
1334 :
1335 : return SET_SRC (set);
1336 : }
1337 :
1338 : #ifdef EH_RETURN_DATA_REGNO
1339 :
1340 : /* Add EH return hard registers as conflict hard registers to allocnos
1341 : living at end of BB. For most allocnos it is already done in
1342 : process_bb_node_lives when we processing input edges but it does
1343 : not work when and EH edge is edge out of the current region. This
1344 : function covers such out of region edges. */
1345 : static void
1346 14730260 : process_out_of_region_eh_regs (basic_block bb)
1347 : {
1348 14730260 : edge e;
1349 14730260 : edge_iterator ei;
1350 14730260 : unsigned int i;
1351 14730260 : bitmap_iterator bi;
1352 14730260 : bool eh_p = false;
1353 :
1354 35756945 : FOR_EACH_EDGE (e, ei, bb->succs)
1355 21026685 : if ((e->flags & EDGE_EH)
1356 21026685 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1357 21026685 : eh_p = true;
1358 :
1359 14730260 : if (! eh_p)
1360 14721246 : return;
1361 :
1362 133546 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1363 : {
1364 124532 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1365 255567 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1366 : {
1367 131035 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1368 524140 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1369 131035 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1370 : }
1371 : }
1372 : }
1373 :
1374 : #endif
1375 :
1376 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1377 : static void
1378 3789879 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1379 : function_abi callee_abi)
1380 : {
1381 3789879 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1382 3789879 : rtx_code_label *landing_label;
1383 3789879 : basic_block landing_bb;
1384 :
1385 8009769 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1386 : {
1387 6739592 : if ((landing_label = lp->landing_pad) != NULL
1388 6739592 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1389 13479133 : && (region->type != ERT_CLEANUP
1390 5241778 : || bitmap_bit_p (df_get_live_in (landing_bb),
1391 : ALLOCNO_REGNO (a))))
1392 : {
1393 2519702 : HARD_REG_SET new_conflict_regs
1394 2519702 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1395 10078808 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1396 2519702 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1397 2519702 : return;
1398 : }
1399 : }
1400 : }
1401 :
1402 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1403 : update allocno live ranges, allocno hard register conflicts,
1404 : intersected calls, and register pressure info for allocnos for the
1405 : basic block for and regions containing the basic block. */
1406 : static void
1407 16862739 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1408 : {
1409 16862739 : int i, freq;
1410 16862739 : unsigned int j, k;
1411 16862739 : basic_block bb;
1412 16862739 : rtx_insn *insn;
1413 16862739 : bitmap_iterator bi;
1414 16862739 : bitmap reg_live_out;
1415 16862739 : unsigned int px;
1416 16862739 : bool set_p;
1417 :
1418 16862739 : bb = loop_tree_node->bb;
1419 16862739 : if (bb != NULL)
1420 : {
1421 72487534 : for (i = 0; i < ira_pressure_classes_num; i++)
1422 : {
1423 57757274 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1424 57757274 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1425 : }
1426 14730260 : curr_bb_node = loop_tree_node;
1427 14730260 : reg_live_out = df_get_live_out (bb);
1428 14730260 : sparseset_clear (objects_live);
1429 29460520 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1430 14730260 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1431 14730260 : hard_reg_set_iterator hrsi;
1432 14730260 : k = 0;
1433 15870548 : EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)
1434 : {
1435 1140288 : enum reg_class aclass, pclass, cl;
1436 :
1437 1140288 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];
1438 1140288 : pclass = ira_pressure_class_translate[aclass];
1439 10815226 : for (j = 0;
1440 10815226 : (cl = ira_reg_class_super_classes[pclass][j])
1441 10815226 : != LIM_REG_CLASSES;
1442 : j++)
1443 : {
1444 9674938 : if (! ira_reg_pressure_class_p[cl])
1445 8534650 : continue;
1446 1140288 : curr_reg_pressure[cl]++;
1447 1140288 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1448 1140288 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1449 1140288 : ira_assert (curr_reg_pressure[cl]
1450 : <= ira_class_hard_regs_num[cl]);
1451 : }
1452 : }
1453 156767573 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1454 142037313 : mark_pseudo_regno_live (j);
1455 :
1456 : #ifdef EH_RETURN_DATA_REGNO
1457 14730260 : process_out_of_region_eh_regs (bb);
1458 : #endif
1459 :
1460 14730260 : freq = REG_FREQ_FROM_BB (bb);
1461 8778796 : if (freq == 0)
1462 2065762 : freq = 1;
1463 :
1464 : /* Invalidate all allocno_saved_at_call entries. */
1465 14730260 : last_call_num++;
1466 :
1467 : /* Scan the code of this basic block, noting which allocnos and
1468 : hard regs are born or die.
1469 :
1470 : Note that this loop treats uninitialized values as live until
1471 : the beginning of the block. For example, if an instruction
1472 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1473 : set, FOO will remain live until the beginning of the block.
1474 : Likewise if FOO is not set at all. This is unnecessarily
1475 : pessimistic, but it probably doesn't matter much in practice. */
1476 180827344 : FOR_BB_INSNS_REVERSE (bb, insn)
1477 : {
1478 166097084 : ira_allocno_t a;
1479 166097084 : df_ref def, use;
1480 166097084 : bool call_p;
1481 :
1482 166097084 : if (!NONDEBUG_INSN_P (insn))
1483 80734345 : continue;
1484 :
1485 85362739 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1486 1477 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1487 1477 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1488 : curr_point);
1489 :
1490 85362739 : call_p = CALL_P (insn);
1491 85362739 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1492 :
1493 : /* Mark each defined value as live. We need to do this for
1494 : unused values because they still conflict with quantities
1495 : that are live at the time of the definition.
1496 :
1497 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1498 : references represent the effect of the called function
1499 : on a call-clobbered register. Marking the register as
1500 : live would stop us from allocating it to a call-crossing
1501 : allocno. */
1502 658089799 : FOR_EACH_INSN_DEF (def, insn)
1503 572727060 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1504 71613949 : mark_ref_live (def);
1505 :
1506 : /* If INSN has multiple outputs, then any value used in one
1507 : of the outputs conflicts with the other outputs. Model this
1508 : by making the used value live during the output phase.
1509 :
1510 : It is unsafe to use !single_set here since it will ignore
1511 : an unused output. Just because an output is unused does
1512 : not mean the compiler can assume the side effect will not
1513 : occur. Consider if ALLOCNO appears in the address of an
1514 : output and we reload the output. If we allocate ALLOCNO
1515 : to the same hard register as an unused output we could
1516 : set the hard register before the output reload insn. */
1517 85362739 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1518 1867967 : FOR_EACH_INSN_USE (use, insn)
1519 : {
1520 1469876 : int i;
1521 1469876 : rtx reg;
1522 :
1523 1469876 : reg = DF_REF_REG (use);
1524 4679716 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1525 : {
1526 3606691 : rtx set;
1527 :
1528 3606691 : set = XVECEXP (PATTERN (insn), 0, i);
1529 3606691 : if (GET_CODE (set) == SET
1530 3606691 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1531 : {
1532 : /* After the previous loop, this is a no-op if
1533 : REG is contained within SET_DEST (SET). */
1534 396851 : mark_ref_live (use);
1535 396851 : break;
1536 : }
1537 : }
1538 : }
1539 :
1540 85362739 : preferred_alternatives = ira_setup_alts (insn);
1541 85362739 : process_register_constraint_filters ();
1542 85362739 : process_dependent_filters ();
1543 85362739 : process_single_reg_class_operands (false, freq);
1544 :
1545 85362739 : if (call_p)
1546 : {
1547 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1548 : there, try to find a pseudo that is live across the call but
1549 : can be cheaply reconstructed from the return value. */
1550 6148305 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1551 6148305 : if (cheap_reg != NULL_RTX)
1552 33345 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1553 :
1554 6148305 : last_call_num++;
1555 6148305 : sparseset_clear (allocnos_processed);
1556 : /* The current set of live allocnos are live across the call. */
1557 471115488 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1558 : {
1559 229409439 : ira_object_t obj = ira_object_id_map[i];
1560 229409439 : a = OBJECT_ALLOCNO (obj);
1561 229409439 : int num = ALLOCNO_NUM (a);
1562 229409439 : function_abi callee_abi = insn_callee_abi (insn);
1563 :
1564 : /* Don't allocate allocnos that cross setjmps or any
1565 : call, if this function receives a nonlocal
1566 : goto. */
1567 229409439 : if (cfun->has_nonlocal_label
1568 229409439 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1569 229406865 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1570 : != NULL_RTX)))
1571 : {
1572 14660 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1573 229409439 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1574 : }
1575 229409439 : eh_region r;
1576 229409439 : if (can_throw_internal (insn)
1577 229409439 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1578 3789879 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1579 229409439 : if (sparseset_bit_p (allocnos_processed, num))
1580 104025212 : continue;
1581 125384227 : sparseset_set_bit (allocnos_processed, num);
1582 :
1583 125384227 : if (allocno_saved_at_call[num] != last_call_num)
1584 : /* Here we are mimicking caller-save.cc behavior
1585 : which does not save hard register at a call if
1586 : it was saved on previous call in the same basic
1587 : block and the hard register was not mentioned
1588 : between the two calls. */
1589 40480659 : ALLOCNO_CALL_FREQ (a) += freq;
1590 : /* Mark it as saved at the next call. */
1591 125384227 : allocno_saved_at_call[num] = last_call_num + 1;
1592 125384227 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1593 125384227 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1594 125384227 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1595 125384227 : |= callee_abi.full_and_partial_reg_clobbers ();
1596 125384227 : if (cheap_reg != NULL_RTX
1597 125384227 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1598 33345 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1599 : }
1600 : }
1601 :
1602 : /* See which defined values die here. Note that we include
1603 : the call insn in the lifetimes of these values, so we don't
1604 : mistakenly consider, for e.g. an addressing mode with a
1605 : side-effect like a post-increment fetching the address,
1606 : that the use happens before the call, and the def to happen
1607 : after the call: we believe both to happen before the actual
1608 : call. (We don't handle return-values here.) */
1609 658089799 : FOR_EACH_INSN_DEF (def, insn)
1610 572727060 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1611 71613949 : mark_ref_dead (def);
1612 :
1613 85362739 : make_early_clobber_and_input_conflicts ();
1614 :
1615 85362739 : curr_point++;
1616 :
1617 : /* Mark each used value as live. */
1618 188335528 : FOR_EACH_INSN_USE (use, insn)
1619 102972789 : mark_ref_live (use);
1620 :
1621 85362739 : process_single_reg_class_operands (true, freq);
1622 :
1623 85362739 : set_p = mark_hard_reg_early_clobbers (insn, true);
1624 :
1625 85362739 : if (set_p)
1626 : {
1627 10778454 : mark_hard_reg_early_clobbers (insn, false);
1628 :
1629 : /* Mark each hard reg as live again. For example, a
1630 : hard register can be in clobber and in an insn
1631 : input. */
1632 26438685 : FOR_EACH_INSN_USE (use, insn)
1633 : {
1634 15660231 : rtx ureg = DF_REF_REG (use);
1635 :
1636 15660231 : if (GET_CODE (ureg) == SUBREG)
1637 332652 : ureg = SUBREG_REG (ureg);
1638 15660231 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1639 10028098 : continue;
1640 :
1641 5632133 : mark_ref_live (use);
1642 : }
1643 : }
1644 :
1645 85362739 : curr_point++;
1646 : }
1647 14730260 : ignore_reg_for_conflicts = NULL_RTX;
1648 :
1649 14730260 : if (bb_has_eh_pred (bb))
1650 226170 : for (j = 0; ; ++j)
1651 : {
1652 678510 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1653 452340 : if (regno == INVALID_REGNUM)
1654 : break;
1655 452340 : make_hard_regno_live (regno);
1656 452340 : }
1657 :
1658 : /* Allocnos can't go in stack regs at the start of a basic block
1659 : that is reached by an abnormal edge. Likewise for registers
1660 : that are at least partly call clobbered, because caller-save,
1661 : fixup_abnormal_edges and possibly the table driven EH machinery
1662 : are not quite ready to handle such allocnos live across such
1663 : edges. */
1664 14730260 : if (bb_has_abnormal_pred (bb))
1665 : {
1666 : #ifdef STACK_REGS
1667 732297 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1668 : {
1669 503702 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1670 :
1671 503702 : ALLOCNO_NO_STACK_REG_P (a) = true;
1672 503702 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1673 : }
1674 2057355 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1675 1828760 : make_hard_regno_live (px);
1676 : #endif
1677 : /* No need to record conflicts for call clobbered regs if we
1678 : have nonlocal labels around, as we don't ever try to
1679 : allocate such regs in this case. */
1680 228595 : if (!cfun->has_nonlocal_label
1681 228595 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1682 21032973 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1683 20806812 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1684 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1685 : /* We should create a conflict of PIC pseudo with
1686 : PIC hard reg as PIC hard reg can have a wrong
1687 : value after jump described by the abnormal edge.
1688 : In this case we cannot allocate PIC hard reg to
1689 : PIC pseudo as PIC pseudo will also have a wrong
1690 : value. This code is not critical as LRA can fix
1691 : it but it is better to have the right allocation
1692 : earlier. */
1693 20946203 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1694 226161 : && pic_offset_table_rtx != NULL_RTX
1695 6307 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1696 : #endif
1697 : )
1698 18817496 : make_hard_regno_live (px);
1699 : }
1700 :
1701 221248606 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1702 206518346 : make_object_dead (ira_object_id_map[i]);
1703 :
1704 14730260 : curr_point++;
1705 :
1706 : }
1707 : /* Propagate register pressure to upper loop tree nodes. */
1708 16862739 : if (loop_tree_node != ira_loop_tree_root)
1709 75583357 : for (i = 0; i < ira_pressure_classes_num; i++)
1710 : {
1711 60235739 : enum reg_class pclass;
1712 :
1713 60235739 : pclass = ira_pressure_classes[i];
1714 60235739 : if (loop_tree_node->reg_pressure[pclass]
1715 60235739 : > loop_tree_node->parent->reg_pressure[pclass])
1716 4277307 : loop_tree_node->parent->reg_pressure[pclass]
1717 4277307 : = loop_tree_node->reg_pressure[pclass];
1718 : }
1719 16862739 : }
1720 :
1721 : /* Create and set up IRA_START_POINT_RANGES and
1722 : IRA_FINISH_POINT_RANGES. */
1723 : static void
1724 3191560 : create_start_finish_chains (void)
1725 : {
1726 3191560 : ira_object_t obj;
1727 3191560 : ira_object_iterator oi;
1728 3191560 : live_range_t r;
1729 :
1730 3191560 : ira_start_point_ranges
1731 3191560 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1732 3191560 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1733 3191560 : ira_finish_point_ranges
1734 3191560 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1735 3191560 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1736 82205934 : FOR_EACH_OBJECT (obj, oi)
1737 186732826 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1738 : {
1739 107718452 : r->start_next = ira_start_point_ranges[r->start];
1740 107718452 : ira_start_point_ranges[r->start] = r;
1741 107718452 : r->finish_next = ira_finish_point_ranges[r->finish];
1742 107718452 : ira_finish_point_ranges[r->finish] = r;
1743 : }
1744 3191560 : }
1745 :
1746 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1747 : new live ranges and program points were added as a result if new
1748 : insn generation. */
1749 : void
1750 1676439 : ira_rebuild_start_finish_chains (void)
1751 : {
1752 1676439 : ira_free (ira_finish_point_ranges);
1753 1676439 : ira_free (ira_start_point_ranges);
1754 1676439 : create_start_finish_chains ();
1755 1676439 : }
1756 :
1757 : /* Compress allocno live ranges by removing program points where
1758 : nothing happens. */
1759 : static void
1760 1515121 : remove_some_program_points_and_update_live_ranges (void)
1761 : {
1762 1515121 : unsigned i;
1763 1515121 : int n;
1764 1515121 : int *map;
1765 1515121 : ira_object_t obj;
1766 1515121 : ira_object_iterator oi;
1767 1515121 : live_range_t r, prev_r, next_r;
1768 1515121 : sbitmap_iterator sbi;
1769 1515121 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1770 :
1771 1515121 : auto_sbitmap born (ira_max_point);
1772 1515121 : auto_sbitmap dead (ira_max_point);
1773 1515121 : bitmap_clear (born);
1774 1515121 : bitmap_clear (dead);
1775 36457019 : FOR_EACH_OBJECT (obj, oi)
1776 89367566 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1777 : {
1778 54425668 : ira_assert (r->start <= r->finish);
1779 54425668 : bitmap_set_bit (born, r->start);
1780 54425668 : bitmap_set_bit (dead, r->finish);
1781 : }
1782 :
1783 1515121 : auto_sbitmap born_or_dead (ira_max_point);
1784 1515121 : bitmap_ior (born_or_dead, born, dead);
1785 1515121 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1786 1515121 : n = -1;
1787 1515121 : prev_born_p = prev_dead_p = false;
1788 68369012 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1789 : {
1790 65338770 : born_p = bitmap_bit_p (born, i);
1791 65338770 : dead_p = bitmap_bit_p (dead, i);
1792 65338770 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1793 59081543 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1794 16539243 : map[i] = n;
1795 : else
1796 48799527 : map[i] = ++n;
1797 65338770 : prev_born_p = born_p;
1798 65338770 : prev_dead_p = dead_p;
1799 : }
1800 :
1801 1515121 : n++;
1802 1515121 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1803 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1804 95 : ira_max_point, n, 100 * n / ira_max_point);
1805 1515121 : ira_max_point = n;
1806 :
1807 36457019 : FOR_EACH_OBJECT (obj, oi)
1808 89367566 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1809 : {
1810 54425668 : next_r = r->next;
1811 54425668 : r->start = map[r->start];
1812 54425668 : r->finish = map[r->finish];
1813 54425668 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1814 : {
1815 41693532 : prev_r = r;
1816 41693532 : continue;
1817 : }
1818 12732136 : prev_r->start = r->start;
1819 12732136 : prev_r->next = next_r;
1820 12732136 : ira_finish_live_range (r);
1821 : }
1822 :
1823 1515121 : ira_free (map);
1824 1515121 : }
1825 :
1826 : /* Print live ranges R to file F. */
1827 : void
1828 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1829 : {
1830 3234 : for (; r != NULL; r = r->next)
1831 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1832 1466 : fprintf (f, "\n");
1833 1466 : }
1834 :
1835 : DEBUG_FUNCTION void
1836 0 : debug (live_range &ref)
1837 : {
1838 0 : ira_print_live_range_list (stderr, &ref);
1839 0 : }
1840 :
1841 : DEBUG_FUNCTION void
1842 0 : debug (live_range *ptr)
1843 : {
1844 0 : if (ptr)
1845 0 : debug (*ptr);
1846 : else
1847 0 : fprintf (stderr, "<nil>\n");
1848 0 : }
1849 :
1850 : /* Print live ranges R to stderr. */
1851 : void
1852 0 : ira_debug_live_range_list (live_range_t r)
1853 : {
1854 0 : ira_print_live_range_list (stderr, r);
1855 0 : }
1856 :
1857 : /* Print live ranges of object OBJ to file F. */
1858 : static void
1859 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1860 : {
1861 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1862 0 : }
1863 :
1864 : /* Print live ranges of allocno A to file F. */
1865 : static void
1866 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1867 : {
1868 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1869 1328 : int i;
1870 :
1871 2656 : for (i = 0; i < n; i++)
1872 : {
1873 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1874 1328 : if (n > 1)
1875 0 : fprintf (f, " [%d]", i);
1876 1328 : fprintf (f, "):");
1877 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1878 : }
1879 1328 : }
1880 :
1881 : /* Print live ranges of allocno A to stderr. */
1882 : void
1883 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1884 : {
1885 0 : print_allocno_live_ranges (stderr, a);
1886 0 : }
1887 :
1888 : /* Print live ranges of all allocnos to file F. */
1889 : static void
1890 190 : print_live_ranges (FILE *f)
1891 : {
1892 190 : ira_allocno_t a;
1893 190 : ira_allocno_iterator ai;
1894 :
1895 1518 : FOR_EACH_ALLOCNO (a, ai)
1896 1328 : print_allocno_live_ranges (f, a);
1897 190 : }
1898 :
1899 : /* Print live ranges of all allocnos to stderr. */
1900 : void
1901 0 : ira_debug_live_ranges (void)
1902 : {
1903 0 : print_live_ranges (stderr);
1904 0 : }
1905 :
1906 : /* The main entry function creates live ranges, set up
1907 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1908 : calculate register pressure info. */
1909 : void
1910 1515121 : ira_create_allocno_live_ranges (void)
1911 : {
1912 1515121 : objects_live = sparseset_alloc (ira_objects_num);
1913 1515121 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1914 1515121 : curr_point = 0;
1915 1515121 : last_call_num = 0;
1916 1515121 : allocno_saved_at_call
1917 1515121 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1918 1515121 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1919 1515121 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1920 : process_bb_node_lives);
1921 1515121 : ira_max_point = curr_point;
1922 1515121 : create_start_finish_chains ();
1923 1515121 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1924 95 : print_live_ranges (ira_dump_file);
1925 : /* Clean up. */
1926 1515121 : ira_free (allocno_saved_at_call);
1927 1515121 : sparseset_free (objects_live);
1928 1515121 : sparseset_free (allocnos_processed);
1929 1515121 : }
1930 :
1931 : /* Compress allocno live ranges. */
1932 : void
1933 1515121 : ira_compress_allocno_live_ranges (void)
1934 : {
1935 1515121 : remove_some_program_points_and_update_live_ranges ();
1936 1515121 : ira_rebuild_start_finish_chains ();
1937 1515121 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1938 : {
1939 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1940 95 : print_live_ranges (ira_dump_file);
1941 : }
1942 1515121 : }
1943 :
1944 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1945 : void
1946 1515121 : ira_finish_allocno_live_ranges (void)
1947 : {
1948 1515121 : ira_free (ira_finish_point_ranges);
1949 1515121 : ira_free (ira_start_point_ranges);
1950 1515121 : }
|
