Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 37300467 : make_hard_regno_live (int regno)
98 : {
99 37300467 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 35202671 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 16345764 : make_hard_regno_dead (int regno)
106 : {
107 16345764 : unsigned int i;
108 280125141 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 263779377 : ira_object_t obj = ira_object_id_map[i];
111 :
112 265394792 : if (ignore_reg_for_conflicts != NULL_RTX
113 172713367 : && REGNO (ignore_reg_for_conflicts)
114 172713367 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1615415 : continue;
116 :
117 262163962 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 262163962 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 16345764 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 16345764 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 241707077 : make_object_live (ira_object_t obj)
127 : {
128 241707077 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 241707077 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 241707077 : if (lr == NULL
132 205063051 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 54496169 : ira_add_live_range_to_object (obj, curr_point, -1);
134 241707077 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 248933811 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 248933811 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 248933811 : int start, i;
143 248933811 : enum reg_class aclass, pclass, cl;
144 248933811 : live_range_t p;
145 :
146 248933811 : aclass = ALLOCNO_CLASS (a);
147 248933811 : pclass = ira_pressure_class_translate[aclass];
148 2445871249 : for (i = 0;
149 2445871249 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2196937438 : if (! ira_reg_pressure_class_p[cl])
153 1952714297 : continue;
154 244223141 : if (high_pressure_start_point[cl] < 0)
155 73958722 : continue;
156 170264419 : p = OBJECT_LIVE_RANGES (obj);
157 170264419 : ira_assert (p != NULL);
158 170264419 : start = (high_pressure_start_point[cl] > p->start
159 170264419 : ? high_pressure_start_point[cl] : p->start);
160 170264419 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 248933811 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 241707077 : make_object_dead (ira_object_t obj)
168 : {
169 241707077 : live_range_t lr;
170 241707077 : int regno;
171 241707077 : int ignore_regno = -1;
172 241707077 : int ignore_total_regno = -1;
173 241707077 : int end_regno = -1;
174 :
175 241707077 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 241707077 : if (ignore_reg_for_conflicts != NULL_RTX
180 241707077 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3416274 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3416274 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6832548 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3416274 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 523770 : ignore_regno = end_regno;
189 3416274 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 523770 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 966828308 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 244599581 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 244599581 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2892504 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 244599581 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2892504 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 241707077 : lr = OBJECT_LIVE_RANGES (obj);
205 241707077 : ira_assert (lr != NULL);
206 241707077 : lr->finish = curr_point;
207 241707077 : update_allocno_pressure_excess_length (obj);
208 241707077 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 259613434 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 259613434 : int i;
222 259613434 : enum reg_class cl;
223 :
224 2546019155 : for (i = 0;
225 2546019155 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2286405721 : if (! ira_reg_pressure_class_p[cl])
229 2031258607 : continue;
230 255147114 : curr_reg_pressure[cl] += n;
231 255147114 : if (high_pressure_start_point[cl] < 0
232 106212211 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1735311 : high_pressure_start_point[cl] = curr_point;
234 255147114 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 219590040 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 259613434 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 53591345 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 53591345 : int i;
248 53591345 : unsigned int j;
249 53591345 : enum reg_class cl;
250 53591345 : bool set_p = false;
251 :
252 53591345 : for (i = 0;
253 516530746 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 462939401 : if (! ira_reg_pressure_class_p[cl])
257 409829818 : continue;
258 53109583 : curr_reg_pressure[cl] -= nregs;
259 53109583 : ira_assert (curr_reg_pressure[cl] >= 0);
260 53109583 : if (high_pressure_start_point[cl] >= 0
261 4586576 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 462939401 : set_p = true;
263 : }
264 53591345 : if (set_p)
265 : {
266 7701076 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7226734 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4506267 : for (i = 0;
269 4980609 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4506267 : if (! ira_reg_pressure_class_p[cl])
273 4031925 : continue;
274 474342 : if (high_pressure_start_point[cl] >= 0
275 474342 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 474342 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 53591345 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 114726 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 114726 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 114726 : ira_object_t obj;
288 :
289 114726 : if (a == NULL)
290 : return false;
291 114726 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 114726 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 114726 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 226104173 : mark_pseudo_regno_live (int regno)
303 : {
304 226104173 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 226104173 : enum reg_class pclass;
306 226104173 : int i, n, nregs;
307 :
308 226104173 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 226104173 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 226104173 : n = ALLOCNO_NUM_OBJECTS (a);
315 226104173 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 226104173 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 226104173 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69840138 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 522048484 : for (i = 0; i < n; i++)
325 : {
326 295944311 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 295944311 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 54557309 : continue;
330 :
331 241387002 : inc_register_pressure (pclass, nregs);
332 241387002 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 851146 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 851146 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 851146 : int n;
344 851146 : enum reg_class pclass;
345 851146 : ira_object_t obj;
346 :
347 851146 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 851146 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 851146 : n = ALLOCNO_NUM_OBJECTS (a);
354 851146 : if (n == 1)
355 : {
356 38000 : mark_pseudo_regno_live (regno);
357 38000 : return;
358 : }
359 :
360 813146 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 813146 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 813146 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 813146 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 320075 : inc_register_pressure (pclass, 1);
369 320075 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 104065013 : mark_hard_reg_live (rtx reg)
377 : {
378 104065013 : int regno = REGNO (reg);
379 :
380 104065013 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 32665903 : int last = END_REGNO (reg);
383 32665903 : enum reg_class aclass, pclass;
384 :
385 65331806 : while (regno < last)
386 : {
387 32665903 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 32665903 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 17906357 : aclass = ira_hard_regno_allocno_class[regno];
391 17906357 : pclass = ira_pressure_class_translate[aclass];
392 17906357 : inc_register_pressure (pclass, 1);
393 17906357 : make_hard_regno_live (regno);
394 : }
395 32665903 : regno++;
396 : }
397 : }
398 104065013 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 86906525 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 86906525 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1270727 : mark_pseudo_regno_subword_live (regno,
409 851146 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 86055379 : mark_pseudo_regno_live (regno);
413 86906525 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 189159736 : mark_ref_live (df_ref ref)
418 : {
419 189159736 : rtx reg = DF_REF_REG (ref);
420 189159736 : rtx orig_reg = reg;
421 :
422 189159736 : if (GET_CODE (reg) == SUBREG)
423 2904304 : reg = SUBREG_REG (reg);
424 :
425 189159736 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 85094723 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 104065013 : mark_hard_reg_live (reg);
429 189159736 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 35640021 : mark_pseudo_regno_dead (int regno)
435 : {
436 35640021 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 35640021 : int n, i, nregs;
438 35640021 : enum reg_class cl;
439 :
440 35640021 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 35640021 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 35640021 : n = ALLOCNO_NUM_OBJECTS (a);
447 35640021 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 35640021 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 35640021 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1273932 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 72553974 : for (i = 0; i < n; i++)
456 : {
457 36913953 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 36913953 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3511 : continue;
460 :
461 36910442 : dec_register_pressure (cl, nregs);
462 36910442 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 339272 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 339272 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 339272 : int n;
473 339272 : enum reg_class cl;
474 339272 : ira_object_t obj;
475 :
476 339272 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 339272 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 339272 : n = ALLOCNO_NUM_OBJECTS (a);
483 339272 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 335139 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 335139 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 335139 : obj = ALLOCNO_OBJECT (a, subword);
492 335139 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 335139 : dec_register_pressure (cl, 1);
496 335139 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 48093723 : mark_hard_reg_dead (rtx reg)
503 : {
504 48093723 : int regno = REGNO (reg);
505 :
506 48093723 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 16347782 : int last = END_REGNO (reg);
509 16347782 : enum reg_class aclass, pclass;
510 :
511 32695564 : while (regno < last)
512 : {
513 16347782 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 16345764 : aclass = ira_hard_regno_allocno_class[regno];
516 16345764 : pclass = ira_pressure_class_translate[aclass];
517 16345764 : dec_register_pressure (pclass, 1);
518 16345764 : make_hard_regno_dead (regno);
519 : }
520 16347782 : regno++;
521 : }
522 : }
523 48093723 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 35979293 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 35979293 : if (read_modify_subreg_p (orig_reg))
532 : {
533 509399 : mark_pseudo_regno_subword_dead (regno,
534 339272 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 35640021 : mark_pseudo_regno_dead (regno);
538 35979293 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 82265396 : mark_ref_dead (df_ref def)
544 : {
545 82265396 : rtx reg = DF_REF_REG (def);
546 82265396 : rtx orig_reg = reg;
547 :
548 82265396 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 82265396 : if (GET_CODE (reg) == SUBREG)
552 865506 : reg = SUBREG_REG (reg);
553 :
554 82265396 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 82265396 : && (GET_CODE (orig_reg) != SUBREG
556 329473 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 329473 : || !read_modify_subreg_p (orig_reg)))
558 4182 : return;
559 :
560 82261214 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 34167491 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 48093723 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2790221 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2790221 : rtx orig_reg = reg;
577 2790221 : ira_allocno_t a;
578 :
579 2790221 : if (GET_CODE (reg) == SUBREG)
580 75020 : reg = SUBREG_REG (reg);
581 :
582 2790221 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 995344 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 995344 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 905901 : if (advance_p)
590 861355 : curr_point++;
591 :
592 905901 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 905901 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 905901 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 905901 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 905901 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 2836788 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 2836788 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2774728 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2774728 : if (use < recog_data.n_operands - 1
624 1041071 : && recog_data.constraints[use][0] == '%')
625 6455 : advance_p
626 6455 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2774728 : if (use >= 1
629 2774470 : && recog_data.constraints[use - 1][0] == '%')
630 9038 : advance_p
631 9038 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14240871 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14240871 : int use, use_match;
662 14240871 : ira_allocno_t a;
663 14240871 : enum reg_class use_cl, acl;
664 14240871 : bool advance_p;
665 14240871 : rtx dreg = recog_data.operand[def];
666 14240871 : rtx orig_dreg = dreg;
667 :
668 14240871 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14240871 : if (GET_CODE (dreg) == SUBREG)
672 111831 : dreg = SUBREG_REG (dreg);
673 :
674 14240871 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 12039239 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 12039239 : acl = ALLOCNO_CLASS (a);
679 12039239 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 11844014 : advance_p = true;
683 :
684 11844014 : int n_operands = recog_data.n_operands;
685 11844014 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 48986081 : for (use = 0; use < n_operands; use++)
687 : {
688 37142067 : int alt1;
689 :
690 37142067 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 11990848 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 36928717 : if (op_alt[use].matches == def
701 25151219 : || (for_tie_p
702 13140635 : && rtx_equal_p (recog_data.operand[use],
703 13140635 : recog_data.operand[op_alt[def].matched])))
704 11777498 : continue;
705 :
706 13373721 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 11770612 : use_cl = op_alt[use].cl;
710 11770612 : if (use_cl == NO_REGS)
711 4744393 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 8629328 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 983756 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 19333108 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 16496321 : if (!TEST_BIT (preferred_alternatives, alt1))
730 7427601 : continue;
731 9068720 : const operand_alternative *op_alt1
732 9068720 : = &recog_op_alt[alt1 * n_operands];
733 9068720 : if (op_alt1[use].matches == def
734 7310167 : || (use < n_operands - 1
735 2656216 : && recog_data.constraints[use][0] == '%'
736 8111 : && op_alt1[use + 1].matches == def)
737 7310167 : || (use >= 1
738 7308687 : && recog_data.constraints[use - 1][0] == '%'
739 3055531 : && op_alt1[use - 1].matches == def))
740 : break;
741 4265330 : if (for_tie_p
742 4065665 : && !op_alt1[def].earlyclobber
743 4064505 : && op_alt1[def].matched < 0
744 21874 : && alternative_class (op_alt1, def) != NO_REGS
745 4287204 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 7645572 : if (alt1 < recog_data.n_alternatives)
750 4808785 : continue;
751 :
752 2836787 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 2836787 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 83501673 : make_early_clobber_and_input_conflicts (void)
779 : {
780 83501673 : int alt;
781 83501673 : int def, def_match;
782 83501673 : enum reg_class def_cl;
783 :
784 83501673 : int n_alternatives = recog_data.n_alternatives;
785 83501673 : int n_operands = recog_data.n_operands;
786 83501673 : const operand_alternative *op_alt = recog_op_alt;
787 1136550732 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1053049059 : if (TEST_BIT (preferred_alternatives, alt))
789 385071056 : for (def = 0; def < n_operands; def++)
790 : {
791 265739916 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 251859488 : def_cl = op_alt[def].cl;
795 251859488 : if (def_cl != NO_REGS)
796 : {
797 210277250 : if (op_alt[def].earlyclobber)
798 130303 : check_and_make_def_conflict (alt, def, def_cl, false);
799 210146947 : else if (op_alt[def].matched >= 0
800 210146947 : && !targetm.class_likely_spilled_p (def_cl))
801 14074488 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 265739916 : if ((def_match = op_alt[def].matches) >= 0
805 265739916 : && (op_alt[def_match].earlyclobber
806 14747414 : || op_alt[def].earlyclobber))
807 : {
808 36080 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 36080 : def_cl = op_alt[def_match].cl;
812 36080 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 83501673 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 94135132 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 94135132 : df_ref def;
823 94135132 : bool set_p = false;
824 :
825 676605329 : FOR_EACH_INSN_DEF (def, insn)
826 582470197 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 23167952 : rtx dreg = DF_REF_REG (def);
829 :
830 23167952 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 23167952 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 144822 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 23023130 : if (live_p)
839 11511565 : mark_ref_live (def);
840 : else
841 11511565 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 94135132 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the class of the hard register.
850 : Otherwise it returns NO_REGS. */
851 : static enum reg_class
852 176466381 : single_reg_class (const char *constraints, rtx op, rtx equiv_const)
853 : {
854 176466381 : int c;
855 176466381 : enum reg_class cl, next_cl;
856 176466381 : enum constraint_num cn;
857 :
858 176466381 : cl = NO_REGS;
859 176466381 : alternative_mask preferred = preferred_alternatives;
860 916980149 : while ((c = *constraints))
861 : {
862 903222925 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 903222925 : else if (c == ',')
865 246904442 : preferred >>= 1;
866 656318483 : else if (preferred & 1)
867 199032705 : switch (c)
868 : {
869 : case 'g':
870 : return NO_REGS;
871 :
872 179104916 : default:
873 : /* ??? Is this the best way to handle memory constraints? */
874 179104916 : cn = lookup_constraint (constraints);
875 179104916 : if (insn_extra_memory_constraint (cn)
876 167075817 : || insn_extra_special_memory_constraint (cn)
877 : || insn_extra_relaxed_memory_constraint (cn)
878 346180731 : || insn_extra_address_constraint (cn))
879 : return NO_REGS;
880 166483497 : if (constraint_satisfied_p (op, cn)
881 166483497 : || (equiv_const != NULL_RTX
882 0 : && CONSTANT_P (equiv_const)
883 0 : && constraint_satisfied_p (equiv_const, cn)))
884 14547989 : return NO_REGS;
885 151935508 : next_cl = reg_class_for_constraint (cn);
886 120756148 : if (next_cl == NO_REGS)
887 : break;
888 117547437 : if (cl == NO_REGS
889 117547437 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
890 995294 : : (ira_class_singleton[cl][GET_MODE (op)]
891 995294 : != ira_class_singleton[next_cl][GET_MODE (op)]))
892 : return NO_REGS;
893 : cl = next_cl;
894 : break;
895 :
896 12770339 : case '0': case '1': case '2': case '3': case '4':
897 12770339 : case '5': case '6': case '7': case '8': case '9':
898 12770339 : {
899 12770339 : char *end;
900 12770339 : unsigned long dup = strtoul (constraints, &end, 10);
901 12770339 : constraints = end;
902 12770339 : next_cl
903 12770339 : = single_reg_class (recog_data.constraints[dup],
904 : recog_data.operand[dup], NULL_RTX);
905 12770339 : if (cl == NO_REGS
906 12770339 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
907 15686 : : (ira_class_singleton[cl][GET_MODE (op)]
908 15686 : != ira_class_singleton[next_cl][GET_MODE (op)]))
909 12558581 : return NO_REGS;
910 211758 : cl = next_cl;
911 211758 : continue;
912 211758 : }
913 : }
914 740302010 : constraints += CONSTRAINT_LEN (c, constraints);
915 : }
916 : return cl;
917 : }
918 :
919 : /* The function checks that operand OP_NUM of the current insn can use
920 : only one hard register. If it is so, the function returns the
921 : class of the hard register. Otherwise it returns NO_REGS. */
922 : static enum reg_class
923 178823108 : single_reg_operand_class (int op_num)
924 : {
925 178823108 : if (op_num < 0 || recog_data.n_alternatives == 0)
926 : return NO_REGS;
927 163696042 : return single_reg_class (recog_data.constraints[op_num],
928 163696042 : recog_data.operand[op_num], NULL_RTX);
929 : }
930 :
931 : /* The function sets up hard register set *SET to hard registers which
932 : might be used by insn reloads because the constraints are too
933 : strict. */
934 : void
935 27251 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
936 : alternative_mask preferred)
937 : {
938 27251 : int i, c, regno = 0;
939 27251 : enum reg_class cl;
940 27251 : rtx op;
941 27251 : machine_mode mode;
942 :
943 27251 : CLEAR_HARD_REG_SET (*set);
944 85564 : for (i = 0; i < recog_data.n_operands; i++)
945 : {
946 58313 : op = recog_data.operand[i];
947 :
948 58313 : if (GET_CODE (op) == SUBREG)
949 1264 : op = SUBREG_REG (op);
950 :
951 58313 : if (GET_CODE (op) == SCRATCH
952 58313 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
953 : {
954 39772 : const char *p = recog_data.constraints[i];
955 :
956 79544 : mode = (GET_CODE (op) == SCRATCH
957 39772 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
958 39772 : cl = NO_REGS;
959 1427985 : for (; (c = *p); p += CONSTRAINT_LEN (c, p))
960 1388213 : if (c == '#')
961 0 : preferred &= ~ALTERNATIVE_BIT (0);
962 1388213 : else if (c == ',')
963 469378 : preferred >>= 1;
964 918835 : else if (preferred & 1)
965 : {
966 699889 : cl = reg_class_for_constraint (lookup_constraint (p));
967 307773 : if (cl != NO_REGS)
968 : {
969 : /* There is no register pressure problem if all of the
970 : regs in this class are fixed. */
971 280405 : int regno = ira_class_singleton[cl][mode];
972 280405 : if (regno >= 0)
973 2008 : add_to_hard_reg_set (set, mode, regno);
974 : }
975 419484 : else if (c == '{')
976 : {
977 0 : int regno = decode_hard_reg_constraint (p);
978 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
979 0 : add_to_hard_reg_set (set, mode, regno);
980 : }
981 : }
982 : }
983 : }
984 27251 : }
985 : /* Processes input operands, if IN_P, or output operands otherwise of
986 : the current insn with FREQ to find allocno which can use only one
987 : hard register and makes other currently living allocnos conflicting
988 : with the hard register. */
989 : static void
990 167003346 : process_single_reg_class_operands (bool in_p, int freq)
991 : {
992 167003346 : int i, regno;
993 167003346 : unsigned int px;
994 167003346 : enum reg_class cl;
995 167003346 : rtx operand;
996 167003346 : ira_allocno_t operand_a, a;
997 :
998 524490082 : for (i = 0; i < recog_data.n_operands; i++)
999 : {
1000 357486736 : operand = recog_data.operand[i];
1001 357486736 : if (in_p && recog_data.operand_type[i] != OP_IN
1002 60958932 : && recog_data.operand_type[i] != OP_INOUT)
1003 60879192 : continue;
1004 178743368 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1005 117864176 : && recog_data.operand_type[i] != OP_INOUT)
1006 117784436 : continue;
1007 178823108 : cl = single_reg_operand_class (i);
1008 178823108 : if (cl == NO_REGS)
1009 178110627 : continue;
1010 :
1011 712481 : operand_a = NULL;
1012 :
1013 712481 : if (GET_CODE (operand) == SUBREG)
1014 57928 : operand = SUBREG_REG (operand);
1015 :
1016 712481 : if (REG_P (operand)
1017 712481 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1018 : {
1019 707957 : enum reg_class aclass;
1020 :
1021 707957 : operand_a = ira_curr_regno_allocno_map[regno];
1022 707957 : aclass = ALLOCNO_CLASS (operand_a);
1023 707957 : if (ira_class_subset_p[cl][aclass])
1024 : {
1025 : /* View the desired allocation of OPERAND as:
1026 :
1027 : (REG:YMODE YREGNO),
1028 :
1029 : a simplification of:
1030 :
1031 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1032 701941 : machine_mode ymode, xmode;
1033 701941 : int xregno, yregno;
1034 701941 : poly_int64 offset;
1035 :
1036 701941 : xmode = recog_data.operand_mode[i];
1037 701941 : xregno = ira_class_singleton[cl][xmode];
1038 701941 : gcc_assert (xregno >= 0);
1039 701941 : ymode = ALLOCNO_MODE (operand_a);
1040 701941 : offset = subreg_lowpart_offset (ymode, xmode);
1041 701941 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1042 701941 : if (yregno >= 0
1043 701941 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1044 : {
1045 701941 : int cost;
1046 :
1047 701941 : ira_allocate_and_set_costs
1048 701941 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1049 : aclass, 0);
1050 701941 : ira_init_register_move_cost_if_necessary (xmode);
1051 1403882 : cost = freq * (in_p
1052 701941 : ? ira_register_move_cost[xmode][aclass][cl]
1053 406390 : : ira_register_move_cost[xmode][cl][aclass]);
1054 701941 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1055 701941 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1056 : }
1057 : }
1058 : }
1059 :
1060 29141678 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1061 : {
1062 28429197 : ira_object_t obj = ira_object_id_map[px];
1063 28429197 : a = OBJECT_ALLOCNO (obj);
1064 28429197 : if (a != operand_a)
1065 : {
1066 : /* We could increase costs of A instead of making it
1067 : conflicting with the hard register. But it works worse
1068 : because it will be spilled in reload in anyway. */
1069 110745732 : OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1070 28429197 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1071 : }
1072 : }
1073 : }
1074 167003346 : }
1075 :
1076 : /* Go through the operands of the extracted insn looking for operand
1077 : alternatives that apply a register filter. Record any such filters
1078 : in the operand's allocno. */
1079 : static void
1080 83501673 : process_register_constraint_filters ()
1081 : {
1082 262245041 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1083 : {
1084 178743368 : rtx op = recog_data.operand[opno];
1085 178743368 : if (SUBREG_P (op))
1086 2865894 : op = SUBREG_REG (op);
1087 178743368 : if (REG_P (op) && !HARD_REGISTER_P (op))
1088 : {
1089 73879374 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1090 1032049102 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1091 : {
1092 958169728 : if (!TEST_BIT (preferred_alternatives, alt))
1093 835942408 : continue;
1094 :
1095 122227320 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1096 122227320 : auto cl = alternative_class (op_alt, opno);
1097 : /* The two extremes are easy:
1098 :
1099 : - We should record the filter if CL matches the
1100 : allocno class.
1101 :
1102 : - We should ignore the filter if CL and the allocno class
1103 : are disjoint. We'll either pick a different alternative
1104 : or reload the operand.
1105 :
1106 : Things are trickier if the classes overlap. However:
1107 :
1108 : - If the allocno class includes registers that are not
1109 : in CL, some choices of hard register will need a reload
1110 : anyway. It isn't obvious that reloads due to filters
1111 : are worse than reloads due to regnos being outside CL.
1112 :
1113 : - Conversely, if the allocno class is a subset of CL,
1114 : any allocation will satisfy the class requirement.
1115 : We should try to make sure it satisfies the filter
1116 : requirement too. This is useful if, for example,
1117 : an allocno needs to be in "low" registers to satisfy
1118 : some uses, and its allocno class is therefore those
1119 : low registers, but the allocno is elsewhere allowed
1120 : to be in any even-numbered register. Picking an
1121 : even-numbered low register satisfies both types of use. */
1122 122227320 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1123 28538808 : continue;
1124 :
1125 93688512 : auto filters = alternative_register_filters (op_alt, opno);
1126 93688512 : if (!filters)
1127 93688512 : continue;
1128 :
1129 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1130 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1131 : }
1132 : }
1133 : }
1134 83501673 : }
1135 :
1136 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1137 : we find a SET rtx that we can use to deduce that a register can be cheaply
1138 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1139 : static rtx
1140 5958427 : find_call_crossed_cheap_reg (rtx_insn *insn)
1141 : {
1142 5958427 : rtx cheap_reg = NULL_RTX;
1143 5958427 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1144 :
1145 18269701 : while (exp != NULL)
1146 : {
1147 12458188 : rtx x = XEXP (exp, 0);
1148 12458188 : if (GET_CODE (x) == SET)
1149 : {
1150 : exp = x;
1151 : break;
1152 : }
1153 12311274 : exp = XEXP (exp, 1);
1154 : }
1155 5958427 : if (exp != NULL)
1156 : {
1157 146914 : basic_block bb = BLOCK_FOR_INSN (insn);
1158 146914 : rtx reg = SET_SRC (exp);
1159 146914 : rtx_insn *prev = PREV_INSN (insn);
1160 293844 : while (prev && !(INSN_P (prev)
1161 146914 : && BLOCK_FOR_INSN (prev) != bb))
1162 : {
1163 146930 : if (NONDEBUG_INSN_P (prev))
1164 : {
1165 146914 : rtx set = single_set (prev);
1166 :
1167 146914 : if (set && rtx_equal_p (SET_DEST (set), reg))
1168 : {
1169 146914 : rtx src = SET_SRC (set);
1170 115132 : if (!REG_P (src) || HARD_REGISTER_P (src)
1171 261640 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1172 : break;
1173 29954 : if (!modified_between_p (src, prev, insn))
1174 5958427 : cheap_reg = src;
1175 : break;
1176 : }
1177 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1178 : {
1179 0 : rtx dest = SET_DEST (set);
1180 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1181 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1182 : break;
1183 0 : if (!modified_between_p (dest, prev, insn))
1184 5958427 : cheap_reg = dest;
1185 : break;
1186 : }
1187 :
1188 0 : if (reg_set_p (reg, prev))
1189 : break;
1190 : }
1191 16 : prev = PREV_INSN (prev);
1192 : }
1193 : }
1194 5958427 : return cheap_reg;
1195 : }
1196 :
1197 : /* Determine whether INSN is a register to register copy of the type where
1198 : we do not need to make the source and destiniation registers conflict.
1199 : If this is a copy instruction, then return the source reg. Otherwise,
1200 : return NULL_RTX. */
1201 : rtx
1202 304834335 : non_conflicting_reg_copy_p (rtx_insn *insn)
1203 : {
1204 : /* Reload has issues with overlapping pseudos being assigned to the
1205 : same hard register, so don't allow it. See PR87600 for details. */
1206 304834335 : if (!targetm.lra_p ())
1207 : return NULL_RTX;
1208 :
1209 304834335 : rtx set = single_set (insn);
1210 :
1211 : /* Disallow anything other than a simple register to register copy
1212 : that has no side effects. */
1213 304834335 : if (set == NULL_RTX
1214 289889330 : || !REG_P (SET_DEST (set))
1215 212855943 : || !REG_P (SET_SRC (set))
1216 376181593 : || side_effects_p (set))
1217 233487077 : return NULL_RTX;
1218 :
1219 71347258 : int dst_regno = REGNO (SET_DEST (set));
1220 71347258 : int src_regno = REGNO (SET_SRC (set));
1221 71347258 : machine_mode mode = GET_MODE (SET_DEST (set));
1222 :
1223 : /* By definition, a register does not conflict with itself, therefore we
1224 : do not have to handle it specially. Returning NULL_RTX now, helps
1225 : simplify the callers of this function. */
1226 71347258 : if (dst_regno == src_regno)
1227 : return NULL_RTX;
1228 :
1229 : /* Computing conflicts for register pairs is difficult to get right, so
1230 : for now, disallow it. */
1231 71347258 : if ((HARD_REGISTER_NUM_P (dst_regno)
1232 19402908 : && hard_regno_nregs (dst_regno, mode) != 1)
1233 90586976 : || (HARD_REGISTER_NUM_P (src_regno)
1234 10431263 : && hard_regno_nregs (src_regno, mode) != 1))
1235 : return NULL_RTX;
1236 :
1237 : return SET_SRC (set);
1238 : }
1239 :
1240 : #ifdef EH_RETURN_DATA_REGNO
1241 :
1242 : /* Add EH return hard registers as conflict hard registers to allocnos
1243 : living at end of BB. For most allocnos it is already done in
1244 : process_bb_node_lives when we processing input edges but it does
1245 : not work when and EH edge is edge out of the current region. This
1246 : function covers such out of region edges. */
1247 : static void
1248 14434092 : process_out_of_region_eh_regs (basic_block bb)
1249 : {
1250 14434092 : edge e;
1251 14434092 : edge_iterator ei;
1252 14434092 : unsigned int i;
1253 14434092 : bitmap_iterator bi;
1254 14434092 : bool eh_p = false;
1255 :
1256 35071245 : FOR_EACH_EDGE (e, ei, bb->succs)
1257 20637153 : if ((e->flags & EDGE_EH)
1258 20637153 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1259 : eh_p = true;
1260 :
1261 14434092 : if (! eh_p)
1262 14426354 : return;
1263 :
1264 98882 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1265 : {
1266 91144 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1267 184493 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1268 : {
1269 93349 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1270 373396 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1271 93349 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1272 : }
1273 : }
1274 : }
1275 :
1276 : #endif
1277 :
1278 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1279 : static void
1280 3375389 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1281 : function_abi callee_abi)
1282 : {
1283 3375389 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1284 3375389 : rtx_code_label *landing_label;
1285 3375389 : basic_block landing_bb;
1286 :
1287 6611404 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1288 : {
1289 5561756 : if ((landing_label = lp->landing_pad) != NULL
1290 5561756 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1291 11123463 : && (region->type != ERT_CLEANUP
1292 4069470 : || bitmap_bit_p (df_get_live_in (landing_bb),
1293 : ALLOCNO_REGNO (a))))
1294 : {
1295 2325741 : HARD_REG_SET new_conflict_regs
1296 2325741 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1297 9302964 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1298 2325741 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1299 2325741 : return;
1300 : }
1301 : }
1302 : }
1303 :
1304 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1305 : update allocno live ranges, allocno hard register conflicts,
1306 : intersected calls, and register pressure info for allocnos for the
1307 : basic block for and regions containing the basic block. */
1308 : static void
1309 16532317 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1310 : {
1311 16532317 : int i, freq;
1312 16532317 : unsigned int j;
1313 16532317 : basic_block bb;
1314 16532317 : rtx_insn *insn;
1315 16532317 : bitmap_iterator bi;
1316 16532317 : bitmap reg_live_out;
1317 16532317 : unsigned int px;
1318 16532317 : bool set_p;
1319 :
1320 16532317 : bb = loop_tree_node->bb;
1321 16532317 : if (bb != NULL)
1322 : {
1323 71004492 : for (i = 0; i < ira_pressure_classes_num; i++)
1324 : {
1325 56570400 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1326 56570400 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1327 : }
1328 14434092 : curr_bb_node = loop_tree_node;
1329 14434092 : reg_live_out = df_get_live_out (bb);
1330 14434092 : sparseset_clear (objects_live);
1331 28868184 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1332 14434092 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1333 1342370556 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1334 1327936464 : if (TEST_HARD_REG_BIT (hard_regs_live, i))
1335 : {
1336 1104390 : enum reg_class aclass, pclass, cl;
1337 :
1338 1104390 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)];
1339 1104390 : pclass = ira_pressure_class_translate[aclass];
1340 10471768 : for (j = 0;
1341 10471768 : (cl = ira_reg_class_super_classes[pclass][j])
1342 10471768 : != LIM_REG_CLASSES;
1343 : j++)
1344 : {
1345 9367378 : if (! ira_reg_pressure_class_p[cl])
1346 8262988 : continue;
1347 1104390 : curr_reg_pressure[cl]++;
1348 1104390 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1349 1104390 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1350 1104390 : ira_assert (curr_reg_pressure[cl]
1351 : <= ira_class_hard_regs_num[cl]);
1352 : }
1353 : }
1354 154444886 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1355 140010794 : mark_pseudo_regno_live (j);
1356 :
1357 : #ifdef EH_RETURN_DATA_REGNO
1358 14434092 : process_out_of_region_eh_regs (bb);
1359 : #endif
1360 :
1361 14434092 : freq = REG_FREQ_FROM_BB (bb);
1362 8598642 : if (freq == 0)
1363 2007081 : freq = 1;
1364 :
1365 : /* Invalidate all allocno_saved_at_call entries. */
1366 14434092 : last_call_num++;
1367 :
1368 : /* Scan the code of this basic block, noting which allocnos and
1369 : hard regs are born or die.
1370 :
1371 : Note that this loop treats uninitialized values as live until
1372 : the beginning of the block. For example, if an instruction
1373 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1374 : set, FOO will remain live until the beginning of the block.
1375 : Likewise if FOO is not set at all. This is unnecessarily
1376 : pessimistic, but it probably doesn't matter much in practice. */
1377 173018945 : FOR_BB_INSNS_REVERSE (bb, insn)
1378 : {
1379 158584853 : ira_allocno_t a;
1380 158584853 : df_ref def, use;
1381 158584853 : bool call_p;
1382 :
1383 158584853 : if (!NONDEBUG_INSN_P (insn))
1384 75083180 : continue;
1385 :
1386 83501673 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1387 1479 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1388 1479 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1389 : curr_point);
1390 :
1391 83501673 : call_p = CALL_P (insn);
1392 83501673 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1393 :
1394 : /* Mark each defined value as live. We need to do this for
1395 : unused values because they still conflict with quantities
1396 : that are live at the time of the definition.
1397 :
1398 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1399 : references represent the effect of the called function
1400 : on a call-clobbered register. Marking the register as
1401 : live would stop us from allocating it to a call-crossing
1402 : allocno. */
1403 639248987 : FOR_EACH_INSN_DEF (def, insn)
1404 555747314 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1405 70753831 : mark_ref_live (def);
1406 :
1407 : /* If INSN has multiple outputs, then any value used in one
1408 : of the outputs conflicts with the other outputs. Model this
1409 : by making the used value live during the output phase.
1410 :
1411 : It is unsafe to use !single_set here since it will ignore
1412 : an unused output. Just because an output is unused does
1413 : not mean the compiler can assume the side effect will not
1414 : occur. Consider if ALLOCNO appears in the address of an
1415 : output and we reload the output. If we allocate ALLOCNO
1416 : to the same hard register as an unused output we could
1417 : set the hard register before the output reload insn. */
1418 83501673 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1419 1771991 : FOR_EACH_INSN_USE (use, insn)
1420 : {
1421 1392412 : int i;
1422 1392412 : rtx reg;
1423 :
1424 1392412 : reg = DF_REF_REG (use);
1425 4384403 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1426 : {
1427 3366972 : rtx set;
1428 :
1429 3366972 : set = XVECEXP (PATTERN (insn), 0, i);
1430 3366972 : if (GET_CODE (set) == SET
1431 3366972 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1432 : {
1433 : /* After the previous loop, this is a no-op if
1434 : REG is contained within SET_DEST (SET). */
1435 374981 : mark_ref_live (use);
1436 374981 : break;
1437 : }
1438 : }
1439 : }
1440 :
1441 83501673 : preferred_alternatives = ira_setup_alts (insn);
1442 83501673 : process_register_constraint_filters ();
1443 83501673 : process_single_reg_class_operands (false, freq);
1444 :
1445 83501673 : if (call_p)
1446 : {
1447 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1448 : there, try to find a pseudo that is live across the call but
1449 : can be cheaply reconstructed from the return value. */
1450 5958427 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1451 5958427 : if (cheap_reg != NULL_RTX)
1452 29954 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1453 :
1454 5958427 : last_call_num++;
1455 5958427 : sparseset_clear (allocnos_processed);
1456 : /* The current set of live allocnos are live across the call. */
1457 468471882 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1458 : {
1459 228277514 : ira_object_t obj = ira_object_id_map[i];
1460 228277514 : a = OBJECT_ALLOCNO (obj);
1461 228277514 : int num = ALLOCNO_NUM (a);
1462 228277514 : function_abi callee_abi = insn_callee_abi (insn);
1463 :
1464 : /* Don't allocate allocnos that cross setjmps or any
1465 : call, if this function receives a nonlocal
1466 : goto. */
1467 228277514 : if (cfun->has_nonlocal_label
1468 228277514 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1469 228274945 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1470 : != NULL_RTX)))
1471 : {
1472 10788 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1473 228277514 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1474 : }
1475 228277514 : eh_region r;
1476 228277514 : if (can_throw_internal (insn)
1477 228277514 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1478 3375389 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1479 228277514 : if (sparseset_bit_p (allocnos_processed, num))
1480 104011669 : continue;
1481 124265845 : sparseset_set_bit (allocnos_processed, num);
1482 :
1483 124265845 : if (allocno_saved_at_call[num] != last_call_num)
1484 : /* Here we are mimicking caller-save.cc behavior
1485 : which does not save hard register at a call if
1486 : it was saved on previous call in the same basic
1487 : block and the hard register was not mentioned
1488 : between the two calls. */
1489 39508709 : ALLOCNO_CALL_FREQ (a) += freq;
1490 : /* Mark it as saved at the next call. */
1491 124265845 : allocno_saved_at_call[num] = last_call_num + 1;
1492 124265845 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1493 124265845 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1494 124265845 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1495 124265845 : |= callee_abi.full_and_partial_reg_clobbers ();
1496 124265845 : if (cheap_reg != NULL_RTX
1497 124265845 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1498 29954 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1499 : }
1500 : }
1501 :
1502 : /* See which defined values die here. Note that we include
1503 : the call insn in the lifetimes of these values, so we don't
1504 : mistakenly consider, for e.g. an addressing mode with a
1505 : side-effect like a post-increment fetching the address,
1506 : that the use happens before the call, and the def to happen
1507 : after the call: we believe both to happen before the actual
1508 : call. (We don't handle return-values here.) */
1509 639248987 : FOR_EACH_INSN_DEF (def, insn)
1510 555747314 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1511 70753831 : mark_ref_dead (def);
1512 :
1513 83501673 : make_early_clobber_and_input_conflicts ();
1514 :
1515 83501673 : curr_point++;
1516 :
1517 : /* Mark each used value as live. */
1518 184098146 : FOR_EACH_INSN_USE (use, insn)
1519 100596473 : mark_ref_live (use);
1520 :
1521 83501673 : process_single_reg_class_operands (true, freq);
1522 :
1523 83501673 : set_p = mark_hard_reg_early_clobbers (insn, true);
1524 :
1525 83501673 : if (set_p)
1526 : {
1527 10633459 : mark_hard_reg_early_clobbers (insn, false);
1528 :
1529 : /* Mark each hard reg as live again. For example, a
1530 : hard register can be in clobber and in an insn
1531 : input. */
1532 26272669 : FOR_EACH_INSN_USE (use, insn)
1533 : {
1534 15639210 : rtx ureg = DF_REF_REG (use);
1535 :
1536 15639210 : if (GET_CODE (ureg) == SUBREG)
1537 311195 : ureg = SUBREG_REG (ureg);
1538 15639210 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1539 9716324 : continue;
1540 :
1541 5922886 : mark_ref_live (use);
1542 : }
1543 : }
1544 :
1545 83501673 : curr_point++;
1546 : }
1547 14434092 : ignore_reg_for_conflicts = NULL_RTX;
1548 :
1549 14434092 : if (bb_has_eh_pred (bb))
1550 207846 : for (j = 0; ; ++j)
1551 : {
1552 623538 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1553 415692 : if (regno == INVALID_REGNUM)
1554 : break;
1555 415692 : make_hard_regno_live (regno);
1556 415692 : }
1557 :
1558 : /* Allocnos can't go in stack regs at the start of a basic block
1559 : that is reached by an abnormal edge. Likewise for registers
1560 : that are at least partly call clobbered, because caller-save,
1561 : fixup_abnormal_edges and possibly the table driven EH machinery
1562 : are not quite ready to handle such allocnos live across such
1563 : edges. */
1564 14434092 : if (bb_has_abnormal_pred (bb))
1565 : {
1566 : #ifdef STACK_REGS
1567 651049 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1568 : {
1569 440786 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1570 :
1571 440786 : ALLOCNO_NO_STACK_REG_P (a) = true;
1572 440786 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1573 : }
1574 1892367 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1575 1682104 : make_hard_regno_live (px);
1576 : #endif
1577 : /* No need to record conflicts for call clobbered regs if we
1578 : have nonlocal labels around, as we don't ever try to
1579 : allocate such regs in this case. */
1580 210263 : if (!cfun->has_nonlocal_label
1581 210263 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1582 19328841 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1583 19121004 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1584 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1585 : /* We should create a conflict of PIC pseudo with
1586 : PIC hard reg as PIC hard reg can have a wrong
1587 : value after jump described by the abnormal edge.
1588 : In this case we cannot allocate PIC hard reg to
1589 : PIC pseudo as PIC pseudo will also have a wrong
1590 : value. This code is not critical as LRA can fix
1591 : it but it is better to have the right allocation
1592 : earlier. */
1593 19259709 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1594 207837 : && pic_offset_table_rtx != NULL_RTX
1595 6213 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1596 : #endif
1597 : )
1598 17296314 : make_hard_regno_live (px);
1599 : }
1600 :
1601 218895588 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1602 204461496 : make_object_dead (ira_object_id_map[i]);
1603 :
1604 14434092 : curr_point++;
1605 :
1606 : }
1607 : /* Propagate register pressure to upper loop tree nodes. */
1608 16532317 : if (loop_tree_node != ira_loop_tree_root)
1609 74099204 : for (i = 0; i < ira_pressure_classes_num; i++)
1610 : {
1611 59047834 : enum reg_class pclass;
1612 :
1613 59047834 : pclass = ira_pressure_classes[i];
1614 59047834 : if (loop_tree_node->reg_pressure[pclass]
1615 59047834 : > loop_tree_node->parent->reg_pressure[pclass])
1616 4227713 : loop_tree_node->parent->reg_pressure[pclass]
1617 4227713 : = loop_tree_node->reg_pressure[pclass];
1618 : }
1619 16532317 : }
1620 :
1621 : /* Create and set up IRA_START_POINT_RANGES and
1622 : IRA_FINISH_POINT_RANGES. */
1623 : static void
1624 3122034 : create_start_finish_chains (void)
1625 : {
1626 3122034 : ira_object_t obj;
1627 3122034 : ira_object_iterator oi;
1628 3122034 : live_range_t r;
1629 :
1630 3122034 : ira_start_point_ranges
1631 3122034 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1632 3122034 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1633 3122034 : ira_finish_point_ranges
1634 3122034 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1635 3122034 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1636 80625564 : FOR_EACH_OBJECT (obj, oi)
1637 183576576 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1638 : {
1639 106073046 : r->start_next = ira_start_point_ranges[r->start];
1640 106073046 : ira_start_point_ranges[r->start] = r;
1641 106073046 : r->finish_next = ira_finish_point_ranges[r->finish];
1642 106073046 : ira_finish_point_ranges[r->finish] = r;
1643 : }
1644 3122034 : }
1645 :
1646 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1647 : new live ranges and program points were added as a result if new
1648 : insn generation. */
1649 : void
1650 1641087 : ira_rebuild_start_finish_chains (void)
1651 : {
1652 1641087 : ira_free (ira_finish_point_ranges);
1653 1641087 : ira_free (ira_start_point_ranges);
1654 1641087 : create_start_finish_chains ();
1655 1641087 : }
1656 :
1657 : /* Compress allocno live ranges by removing program points where
1658 : nothing happens. */
1659 : static void
1660 1480947 : remove_some_program_points_and_update_live_ranges (void)
1661 : {
1662 1480947 : unsigned i;
1663 1480947 : int n;
1664 1480947 : int *map;
1665 1480947 : ira_object_t obj;
1666 1480947 : ira_object_iterator oi;
1667 1480947 : live_range_t r, prev_r, next_r;
1668 1480947 : sbitmap_iterator sbi;
1669 1480947 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1670 :
1671 1480947 : auto_sbitmap born (ira_max_point);
1672 1480947 : auto_sbitmap dead (ira_max_point);
1673 1480947 : bitmap_clear (born);
1674 1480947 : bitmap_clear (dead);
1675 35645776 : FOR_EACH_OBJECT (obj, oi)
1676 87636160 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1677 : {
1678 53471331 : ira_assert (r->start <= r->finish);
1679 53471331 : bitmap_set_bit (born, r->start);
1680 53471331 : bitmap_set_bit (dead, r->finish);
1681 : }
1682 :
1683 1480947 : auto_sbitmap born_or_dead (ira_max_point);
1684 1480947 : bitmap_ior (born_or_dead, born, dead);
1685 1480947 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1686 1480947 : n = -1;
1687 1480947 : prev_born_p = prev_dead_p = false;
1688 66847814 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1689 : {
1690 63885920 : born_p = bitmap_bit_p (born, i);
1691 63885920 : dead_p = bitmap_bit_p (dead, i);
1692 63885920 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1693 57759984 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1694 16152968 : map[i] = n;
1695 : else
1696 47732952 : map[i] = ++n;
1697 63885920 : prev_born_p = born_p;
1698 63885920 : prev_dead_p = dead_p;
1699 : }
1700 :
1701 1480947 : n++;
1702 1480947 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1703 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1704 95 : ira_max_point, n, 100 * n / ira_max_point);
1705 1480947 : ira_max_point = n;
1706 :
1707 35645776 : FOR_EACH_OBJECT (obj, oi)
1708 87636160 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1709 : {
1710 53471331 : next_r = r->next;
1711 53471331 : r->start = map[r->start];
1712 53471331 : r->finish = map[r->finish];
1713 53471331 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1714 : {
1715 40901251 : prev_r = r;
1716 40901251 : continue;
1717 : }
1718 12570080 : prev_r->start = r->start;
1719 12570080 : prev_r->next = next_r;
1720 12570080 : ira_finish_live_range (r);
1721 : }
1722 :
1723 1480947 : ira_free (map);
1724 1480947 : }
1725 :
1726 : /* Print live ranges R to file F. */
1727 : void
1728 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1729 : {
1730 3234 : for (; r != NULL; r = r->next)
1731 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1732 1466 : fprintf (f, "\n");
1733 1466 : }
1734 :
1735 : DEBUG_FUNCTION void
1736 0 : debug (live_range &ref)
1737 : {
1738 0 : ira_print_live_range_list (stderr, &ref);
1739 0 : }
1740 :
1741 : DEBUG_FUNCTION void
1742 0 : debug (live_range *ptr)
1743 : {
1744 0 : if (ptr)
1745 0 : debug (*ptr);
1746 : else
1747 0 : fprintf (stderr, "<nil>\n");
1748 0 : }
1749 :
1750 : /* Print live ranges R to stderr. */
1751 : void
1752 0 : ira_debug_live_range_list (live_range_t r)
1753 : {
1754 0 : ira_print_live_range_list (stderr, r);
1755 0 : }
1756 :
1757 : /* Print live ranges of object OBJ to file F. */
1758 : static void
1759 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1760 : {
1761 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1762 0 : }
1763 :
1764 : /* Print live ranges of allocno A to file F. */
1765 : static void
1766 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1767 : {
1768 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1769 1328 : int i;
1770 :
1771 2656 : for (i = 0; i < n; i++)
1772 : {
1773 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1774 1328 : if (n > 1)
1775 0 : fprintf (f, " [%d]", i);
1776 1328 : fprintf (f, "):");
1777 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1778 : }
1779 1328 : }
1780 :
1781 : /* Print live ranges of allocno A to stderr. */
1782 : void
1783 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1784 : {
1785 0 : print_allocno_live_ranges (stderr, a);
1786 0 : }
1787 :
1788 : /* Print live ranges of all allocnos to file F. */
1789 : static void
1790 190 : print_live_ranges (FILE *f)
1791 : {
1792 190 : ira_allocno_t a;
1793 190 : ira_allocno_iterator ai;
1794 :
1795 1518 : FOR_EACH_ALLOCNO (a, ai)
1796 1328 : print_allocno_live_ranges (f, a);
1797 190 : }
1798 :
1799 : /* Print live ranges of all allocnos to stderr. */
1800 : void
1801 0 : ira_debug_live_ranges (void)
1802 : {
1803 0 : print_live_ranges (stderr);
1804 0 : }
1805 :
1806 : /* The main entry function creates live ranges, set up
1807 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1808 : calculate register pressure info. */
1809 : void
1810 1480947 : ira_create_allocno_live_ranges (void)
1811 : {
1812 1480947 : objects_live = sparseset_alloc (ira_objects_num);
1813 1480947 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1814 1480947 : curr_point = 0;
1815 1480947 : last_call_num = 0;
1816 1480947 : allocno_saved_at_call
1817 1480947 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1818 1480947 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1819 1480947 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1820 : process_bb_node_lives);
1821 1480947 : ira_max_point = curr_point;
1822 1480947 : create_start_finish_chains ();
1823 1480947 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1824 95 : print_live_ranges (ira_dump_file);
1825 : /* Clean up. */
1826 1480947 : ira_free (allocno_saved_at_call);
1827 1480947 : sparseset_free (objects_live);
1828 1480947 : sparseset_free (allocnos_processed);
1829 1480947 : }
1830 :
1831 : /* Compress allocno live ranges. */
1832 : void
1833 1480947 : ira_compress_allocno_live_ranges (void)
1834 : {
1835 1480947 : remove_some_program_points_and_update_live_ranges ();
1836 1480947 : ira_rebuild_start_finish_chains ();
1837 1480947 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1838 : {
1839 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1840 95 : print_live_ranges (ira_dump_file);
1841 : }
1842 1480947 : }
1843 :
1844 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1845 : void
1846 1480947 : ira_finish_allocno_live_ranges (void)
1847 : {
1848 1480947 : ira_free (ira_finish_point_ranges);
1849 1480947 : ira_free (ira_start_point_ranges);
1850 1480947 : }
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