Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 37532483 : make_hard_regno_live (int regno)
98 : {
99 37532483 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 35399287 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 16263933 : make_hard_regno_dead (int regno)
106 : {
107 16263933 : unsigned int i;
108 279766158 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 263502225 : ira_object_t obj = ira_object_id_map[i];
111 :
112 265110550 : if (ignore_reg_for_conflicts != NULL_RTX
113 172553917 : && REGNO (ignore_reg_for_conflicts)
114 172553917 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1608325 : continue;
116 :
117 261893900 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 261893900 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 16263933 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 16263933 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 241316757 : make_object_live (ira_object_t obj)
127 : {
128 241316757 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 241316757 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 241316757 : if (lr == NULL
132 204923707 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 54107158 : ira_add_live_range_to_object (obj, curr_point, -1);
134 241316757 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 248534657 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 248534657 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 248534657 : int start, i;
143 248534657 : enum reg_class aclass, pclass, cl;
144 248534657 : live_range_t p;
145 :
146 248534657 : aclass = ALLOCNO_CLASS (a);
147 248534657 : pclass = ira_pressure_class_translate[aclass];
148 2441152506 : for (i = 0;
149 2441152506 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2192617849 : if (! ira_reg_pressure_class_p[cl])
153 1948933512 : continue;
154 243684337 : if (high_pressure_start_point[cl] < 0)
155 72958633 : continue;
156 170725704 : p = OBJECT_LIVE_RANGES (obj);
157 170725704 : ira_assert (p != NULL);
158 170725704 : start = (high_pressure_start_point[cl] > p->start
159 170725704 : ? high_pressure_start_point[cl] : p->start);
160 170725704 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 248534657 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 241316757 : make_object_dead (ira_object_t obj)
168 : {
169 241316757 : live_range_t lr;
170 241316757 : int regno;
171 241316757 : int ignore_regno = -1;
172 241316757 : int ignore_total_regno = -1;
173 241316757 : int end_regno = -1;
174 :
175 241316757 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 241316757 : if (ignore_reg_for_conflicts != NULL_RTX
180 241316757 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3408861 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3408861 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6817722 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3408861 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 520288 : ignore_regno = end_regno;
189 3408861 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 520288 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 965267028 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 244205330 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 244205330 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2888573 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 244205330 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2888573 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 241316757 : lr = OBJECT_LIVE_RANGES (obj);
205 241316757 : ira_assert (lr != NULL);
206 241316757 : lr->finish = curr_point;
207 241316757 : update_allocno_pressure_excess_length (obj);
208 241316757 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 259125646 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 259125646 : int i;
222 259125646 : enum reg_class cl;
223 :
224 2540472284 : for (i = 0;
225 2540472284 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2281346638 : if (! ira_reg_pressure_class_p[cl])
229 2026819229 : continue;
230 254527409 : curr_reg_pressure[cl] += n;
231 254527409 : if (high_pressure_start_point[cl] < 0
232 105445565 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1761064 : high_pressure_start_point[cl] = curr_point;
234 254527409 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 219234154 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 259125646 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 53145370 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 53145370 : int i;
248 53145370 : unsigned int j;
249 53145370 : enum reg_class cl;
250 53145370 : bool set_p = false;
251 :
252 53145370 : for (i = 0;
253 512220939 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 459075569 : if (! ira_reg_pressure_class_p[cl])
257 406406066 : continue;
258 52669503 : curr_reg_pressure[cl] -= nregs;
259 52669503 : ira_assert (curr_reg_pressure[cl] >= 0);
260 52669503 : if (high_pressure_start_point[cl] >= 0
261 4608932 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 459075569 : set_p = true;
263 : }
264 53145370 : if (set_p)
265 : {
266 7692084 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7217900 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4508778 : for (i = 0;
269 4982962 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4508778 : if (! ira_reg_pressure_class_p[cl])
273 4034594 : continue;
274 474184 : if (high_pressure_start_point[cl] >= 0
275 474184 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 474184 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 53145370 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 115252 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 115252 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 115252 : ira_object_t obj;
288 :
289 115252 : if (a == NULL)
290 : return false;
291 115252 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 115252 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 115252 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 225347025 : mark_pseudo_regno_live (int regno)
303 : {
304 225347025 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 225347025 : enum reg_class pclass;
306 225347025 : int i, n, nregs;
307 :
308 225347025 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 225347025 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 225347025 : n = ALLOCNO_NUM_OBJECTS (a);
315 225347025 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 225347025 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 225347025 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69795271 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 520489321 : for (i = 0; i < n; i++)
325 : {
326 295142296 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 295142296 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 54133573 : continue;
330 :
331 241008723 : inc_register_pressure (pclass, nregs);
332 241008723 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 825044 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 825044 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 825044 : int n;
344 825044 : enum reg_class pclass;
345 825044 : ira_object_t obj;
346 :
347 825044 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 825044 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 825044 : n = ALLOCNO_NUM_OBJECTS (a);
354 825044 : if (n == 1)
355 : {
356 37560 : mark_pseudo_regno_live (regno);
357 37560 : return;
358 : }
359 :
360 787484 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 787484 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 787484 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 787484 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 308034 : inc_register_pressure (pclass, 1);
369 308034 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 103521579 : mark_hard_reg_live (rtx reg)
377 : {
378 103521579 : int regno = REGNO (reg);
379 :
380 103521579 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 32486606 : int last = END_REGNO (reg);
383 32486606 : enum reg_class aclass, pclass;
384 :
385 64973212 : while (regno < last)
386 : {
387 32486606 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 32486606 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 17808889 : aclass = ira_hard_regno_allocno_class[regno];
391 17808889 : pclass = ira_pressure_class_translate[aclass];
392 17808889 : inc_register_pressure (pclass, 1);
393 17808889 : make_hard_regno_live (regno);
394 : }
395 32486606 : regno++;
396 : }
397 : }
398 103521579 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 86174361 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 86174361 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1230491 : mark_pseudo_regno_subword_live (regno,
409 825044 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 85349317 : mark_pseudo_regno_live (regno);
413 86174361 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 187922726 : mark_ref_live (df_ref ref)
418 : {
419 187922726 : rtx reg = DF_REF_REG (ref);
420 187922726 : rtx orig_reg = reg;
421 :
422 187922726 : if (GET_CODE (reg) == SUBREG)
423 2903357 : reg = SUBREG_REG (reg);
424 :
425 187922726 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 84401147 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 103521579 : mark_hard_reg_live (reg);
429 187922726 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 35285593 : mark_pseudo_regno_dead (int regno)
435 : {
436 35285593 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 35285593 : int n, i, nregs;
438 35285593 : enum reg_class cl;
439 :
440 35285593 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 35285593 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 35285593 : n = ALLOCNO_NUM_OBJECTS (a);
447 35285593 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 35285593 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 35285593 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1269725 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 71840911 : for (i = 0; i < n; i++)
456 : {
457 36555318 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 36555318 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3542 : continue;
460 :
461 36551776 : dec_register_pressure (cl, nregs);
462 36551776 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 333792 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 333792 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 333792 : int n;
473 333792 : enum reg_class cl;
474 333792 : ira_object_t obj;
475 :
476 333792 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 333792 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 333792 : n = ALLOCNO_NUM_OBJECTS (a);
483 333792 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 329661 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 329661 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 329661 : obj = ALLOCNO_OBJECT (a, subword);
492 329661 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 329661 : dec_register_pressure (cl, 1);
496 329661 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 47752934 : mark_hard_reg_dead (rtx reg)
503 : {
504 47752934 : int regno = REGNO (reg);
505 :
506 47752934 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 16265951 : int last = END_REGNO (reg);
509 16265951 : enum reg_class aclass, pclass;
510 :
511 32531902 : while (regno < last)
512 : {
513 16265951 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 16263933 : aclass = ira_hard_regno_allocno_class[regno];
516 16263933 : pclass = ira_pressure_class_translate[aclass];
517 16263933 : dec_register_pressure (pclass, 1);
518 16263933 : make_hard_regno_dead (regno);
519 : }
520 16265951 : regno++;
521 : }
522 : }
523 47752934 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 35619385 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 35619385 : if (read_modify_subreg_p (orig_reg))
532 : {
533 500819 : mark_pseudo_regno_subword_dead (regno,
534 333792 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 35285593 : mark_pseudo_regno_dead (regno);
538 35619385 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 81603285 : mark_ref_dead (df_ref def)
544 : {
545 81603285 : rtx reg = DF_REF_REG (def);
546 81603285 : rtx orig_reg = reg;
547 :
548 81603285 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 81603285 : if (GET_CODE (reg) == SUBREG)
552 893997 : reg = SUBREG_REG (reg);
553 :
554 81603285 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 81603285 : && (GET_CODE (orig_reg) != SUBREG
556 324653 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 324653 : || !read_modify_subreg_p (orig_reg)))
558 4180 : return;
559 :
560 81599105 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 33846171 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 47752934 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2757549 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2757549 : rtx orig_reg = reg;
577 2757549 : ira_allocno_t a;
578 :
579 2757549 : if (GET_CODE (reg) == SUBREG)
580 73438 : reg = SUBREG_REG (reg);
581 :
582 2757549 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 976368 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 976368 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 886607 : if (advance_p)
590 842047 : curr_point++;
591 :
592 886607 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 886607 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 886607 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 886607 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 886607 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 2804138 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 2804138 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2742008 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2742008 : if (use < recog_data.n_operands - 1
624 1030578 : && recog_data.constraints[use][0] == '%')
625 6479 : advance_p
626 6479 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2742008 : if (use >= 1
629 2741722 : && recog_data.constraints[use - 1][0] == '%')
630 9062 : advance_p
631 9062 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14087496 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14087496 : int use, use_match;
662 14087496 : ira_allocno_t a;
663 14087496 : enum reg_class use_cl, acl;
664 14087496 : bool advance_p;
665 14087496 : rtx dreg = recog_data.operand[def];
666 14087496 : rtx orig_dreg = dreg;
667 :
668 14087496 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14087496 : if (GET_CODE (dreg) == SUBREG)
672 111532 : dreg = SUBREG_REG (dreg);
673 :
674 14087496 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 11885379 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 11885379 : acl = ALLOCNO_CLASS (a);
679 11885379 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 11694785 : advance_p = true;
683 :
684 11694785 : int n_operands = recog_data.n_operands;
685 11694785 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 48380260 : for (use = 0; use < n_operands; use++)
687 : {
688 36685475 : int alt1;
689 :
690 36685475 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 11840729 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 36473580 : if (op_alt[use].matches == def
701 24844746 : || (for_tie_p
702 12984353 : && rtx_equal_p (recog_data.operand[use],
703 12984353 : recog_data.operand[op_alt[def].matched])))
704 11628834 : continue;
705 :
706 13215912 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 11623166 : use_cl = op_alt[use].cl;
710 11623166 : if (use_cl == NO_REGS)
711 4707269 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 8508643 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 969685 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 19079772 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 16275635 : if (!TEST_BIT (preferred_alternatives, alt1))
730 7326162 : continue;
731 8949473 : const operand_alternative *op_alt1
732 8949473 : = &recog_op_alt[alt1 * n_operands];
733 8949473 : if (op_alt1[use].matches == def
734 7212456 : || (use < n_operands - 1
735 2632401 : && recog_data.constraints[use][0] == '%'
736 8135 : && op_alt1[use + 1].matches == def)
737 7212456 : || (use >= 1
738 7210948 : && recog_data.constraints[use - 1][0] == '%'
739 3003116 : && op_alt1[use - 1].matches == def))
740 : break;
741 4220058 : if (for_tie_p
742 4022427 : && !op_alt1[def].earlyclobber
743 4021267 : && op_alt1[def].matched < 0
744 21945 : && alternative_class (op_alt1, def) != NO_REGS
745 4242003 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 7538958 : if (alt1 < recog_data.n_alternatives)
750 4734821 : continue;
751 :
752 2804137 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 2804137 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 82927247 : make_early_clobber_and_input_conflicts (void)
779 : {
780 82927247 : int alt;
781 82927247 : int def, def_match;
782 82927247 : enum reg_class def_cl;
783 :
784 82927247 : int n_alternatives = recog_data.n_alternatives;
785 82927247 : int n_operands = recog_data.n_operands;
786 82927247 : const operand_alternative *op_alt = recog_op_alt;
787 1128998738 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1046071491 : if (TEST_BIT (preferred_alternatives, alt))
789 382281226 : for (def = 0; def < n_operands; def++)
790 : {
791 263804654 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 249951029 : def_cl = op_alt[def].cl;
795 249951029 : if (def_cl != NO_REGS)
796 : {
797 208749926 : if (op_alt[def].earlyclobber)
798 129336 : check_and_make_def_conflict (alt, def, def_cl, false);
799 208620590 : else if (op_alt[def].matched >= 0
800 208620590 : && !targetm.class_likely_spilled_p (def_cl))
801 13922989 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 263804654 : if ((def_match = op_alt[def].matches) >= 0
805 263804654 : && (op_alt[def_match].earlyclobber
806 14591723 : || op_alt[def].earlyclobber))
807 : {
808 35171 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 35171 : def_cl = op_alt[def_match].cl;
812 35171 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 82927247 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 93452779 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 93452779 : df_ref def;
823 93452779 : bool set_p = false;
824 :
825 674394370 : FOR_EACH_INSN_DEF (def, insn)
826 580941591 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 22947546 : rtx dreg = DF_REF_REG (def);
829 :
830 22947546 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 22947546 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 140270 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 22807276 : if (live_p)
839 11403638 : mark_ref_live (def);
840 : else
841 11403638 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 93452779 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the class of the hard register.
850 : Otherwise it returns NO_REGS. */
851 : static enum reg_class
852 175249994 : single_reg_class (const char *constraints, rtx op, rtx equiv_const)
853 : {
854 175249994 : int c;
855 175249994 : enum reg_class cl, next_cl;
856 175249994 : enum constraint_num cn;
857 :
858 175249994 : cl = NO_REGS;
859 175249994 : alternative_mask preferred = preferred_alternatives;
860 911686949 : while ((c = *constraints))
861 : {
862 897949047 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 897949047 : else if (c == ',')
865 245563270 : preferred >>= 1;
866 652385777 : else if (preferred & 1)
867 197475645 : switch (c)
868 : {
869 : case 'g':
870 : return NO_REGS;
871 :
872 177734304 : default:
873 : /* ??? Is this the best way to handle memory constraints? */
874 177734304 : cn = lookup_constraint (constraints);
875 177734304 : if (insn_extra_memory_constraint (cn)
876 165745285 : || insn_extra_special_memory_constraint (cn)
877 : || insn_extra_relaxed_memory_constraint (cn)
878 343479587 : || insn_extra_address_constraint (cn))
879 : return NO_REGS;
880 165160067 : if (constraint_satisfied_p (op, cn)
881 165160067 : || (equiv_const != NULL_RTX
882 0 : && CONSTANT_P (equiv_const)
883 0 : && constraint_satisfied_p (equiv_const, cn)))
884 14451275 : return NO_REGS;
885 150708792 : next_cl = reg_class_for_constraint (cn);
886 119866241 : if (next_cl == NO_REGS)
887 : break;
888 116668502 : if (cl == NO_REGS
889 116668502 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
890 980574 : : (ira_class_singleton[cl][GET_MODE (op)]
891 980574 : != ira_class_singleton[next_cl][GET_MODE (op)]))
892 : return NO_REGS;
893 : cl = next_cl;
894 : break;
895 :
896 12647892 : case '0': case '1': case '2': case '3': case '4':
897 12647892 : case '5': case '6': case '7': case '8': case '9':
898 12647892 : {
899 12647892 : char *end;
900 12647892 : unsigned long dup = strtoul (constraints, &end, 10);
901 12647892 : constraints = end;
902 12647892 : next_cl
903 12647892 : = single_reg_class (recog_data.constraints[dup],
904 : recog_data.operand[dup], NULL_RTX);
905 12647892 : if (cl == NO_REGS
906 12647892 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
907 15744 : : (ira_class_singleton[cl][GET_MODE (op)]
908 15744 : != ira_class_singleton[next_cl][GET_MODE (op)]))
909 12434747 : return NO_REGS;
910 213145 : cl = next_cl;
911 213145 : continue;
912 213145 : }
913 : }
914 736223810 : constraints += CONSTRAINT_LEN (c, constraints);
915 : }
916 : return cl;
917 : }
918 :
919 : /* The function checks that operand OP_NUM of the current insn can use
920 : only one hard register. If it is so, the function returns the
921 : class of the hard register. Otherwise it returns NO_REGS. */
922 : static enum reg_class
923 177606452 : single_reg_operand_class (int op_num)
924 : {
925 177606452 : if (op_num < 0 || recog_data.n_alternatives == 0)
926 : return NO_REGS;
927 162602102 : return single_reg_class (recog_data.constraints[op_num],
928 162602102 : recog_data.operand[op_num], NULL_RTX);
929 : }
930 :
931 : /* The function sets up hard register set *SET to hard registers which
932 : might be used by insn reloads because the constraints are too
933 : strict. */
934 : void
935 28134 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
936 : alternative_mask preferred)
937 : {
938 28134 : int i, c, regno = 0;
939 28134 : enum reg_class cl;
940 28134 : rtx op;
941 28134 : machine_mode mode;
942 :
943 28134 : CLEAR_HARD_REG_SET (*set);
944 87186 : for (i = 0; i < recog_data.n_operands; i++)
945 : {
946 59052 : op = recog_data.operand[i];
947 :
948 59052 : if (GET_CODE (op) == SUBREG)
949 1266 : op = SUBREG_REG (op);
950 :
951 59052 : if (GET_CODE (op) == SCRATCH
952 59052 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
953 : {
954 39817 : const char *p = recog_data.constraints[i];
955 :
956 79634 : mode = (GET_CODE (op) == SCRATCH
957 39817 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
958 39817 : cl = NO_REGS;
959 39817 : for (alternative_mask curr_preferred = preferred;
960 1428729 : (c = *p);
961 1388912 : p += CONSTRAINT_LEN (c, p))
962 1388912 : if (c == '#')
963 0 : curr_preferred &= ~ALTERNATIVE_BIT (0);
964 1388912 : else if (c == ',')
965 469550 : curr_preferred >>= 1;
966 919362 : else if (curr_preferred & 1)
967 : {
968 577071 : cl = reg_class_for_constraint (lookup_constraint (p));
969 249731 : if (cl != NO_REGS)
970 : {
971 : /* There is no register pressure problem if all of the
972 : regs in this class are fixed. */
973 245618 : int regno = ira_class_singleton[cl][mode];
974 245618 : if (regno >= 0)
975 1837 : add_to_hard_reg_set (set, mode, regno);
976 : }
977 331453 : else if (c == '{')
978 : {
979 0 : int regno = decode_hard_reg_constraint (p);
980 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
981 0 : add_to_hard_reg_set (set, mode, regno);
982 : }
983 : }
984 : }
985 : }
986 28134 : }
987 : /* Processes input operands, if IN_P, or output operands otherwise of
988 : the current insn with FREQ to find allocno which can use only one
989 : hard register and makes other currently living allocnos conflicting
990 : with the hard register. */
991 : static void
992 165854494 : process_single_reg_class_operands (bool in_p, int freq)
993 : {
994 165854494 : int i, regno;
995 165854494 : unsigned int px;
996 165854494 : enum reg_class cl;
997 165854494 : rtx operand;
998 165854494 : ira_allocno_t operand_a, a;
999 :
1000 520908160 : for (i = 0; i < recog_data.n_operands; i++)
1001 : {
1002 355053666 : operand = recog_data.operand[i];
1003 355053666 : if (in_p && recog_data.operand_type[i] != OP_IN
1004 60539825 : && recog_data.operand_type[i] != OP_INOUT)
1005 60460206 : continue;
1006 177526833 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1007 117066627 : && recog_data.operand_type[i] != OP_INOUT)
1008 116987008 : continue;
1009 177606452 : cl = single_reg_operand_class (i);
1010 177606452 : if (cl == NO_REGS)
1011 176892910 : continue;
1012 :
1013 713542 : operand_a = NULL;
1014 :
1015 713542 : if (GET_CODE (operand) == SUBREG)
1016 57618 : operand = SUBREG_REG (operand);
1017 :
1018 713542 : if (REG_P (operand)
1019 713542 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1020 : {
1021 709016 : enum reg_class aclass;
1022 :
1023 709016 : operand_a = ira_curr_regno_allocno_map[regno];
1024 709016 : aclass = ALLOCNO_CLASS (operand_a);
1025 709016 : if (ira_class_subset_p[cl][aclass])
1026 : {
1027 : /* View the desired allocation of OPERAND as:
1028 :
1029 : (REG:YMODE YREGNO),
1030 :
1031 : a simplification of:
1032 :
1033 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1034 702730 : machine_mode ymode, xmode;
1035 702730 : int xregno, yregno;
1036 702730 : poly_int64 offset;
1037 :
1038 702730 : xmode = recog_data.operand_mode[i];
1039 702730 : xregno = ira_class_singleton[cl][xmode];
1040 702730 : gcc_assert (xregno >= 0);
1041 702730 : ymode = ALLOCNO_MODE (operand_a);
1042 702730 : offset = subreg_lowpart_offset (ymode, xmode);
1043 702730 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1044 702730 : if (yregno >= 0
1045 702730 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1046 : {
1047 702730 : int cost;
1048 :
1049 702730 : ira_allocate_and_set_costs
1050 702730 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1051 : aclass, 0);
1052 702730 : ira_init_register_move_cost_if_necessary (xmode);
1053 1405460 : cost = freq * (in_p
1054 702730 : ? ira_register_move_cost[xmode][aclass][cl]
1055 406746 : : ira_register_move_cost[xmode][cl][aclass]);
1056 702730 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1057 702730 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1058 : }
1059 : }
1060 : }
1061 :
1062 29128793 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1063 : {
1064 28415251 : ira_object_t obj = ira_object_id_map[px];
1065 28415251 : a = OBJECT_ALLOCNO (obj);
1066 28415251 : if (a != operand_a)
1067 : {
1068 : /* We could increase costs of A instead of making it
1069 : conflicting with the hard register. But it works worse
1070 : because it will be spilled in reload in anyway. */
1071 110687664 : OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1072 28415251 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1073 : }
1074 : }
1075 : }
1076 165854494 : }
1077 :
1078 : /* Go through the operands of the extracted insn looking for operand
1079 : alternatives that apply a register filter. Record any such filters
1080 : in the operand's allocno. */
1081 : static void
1082 82927247 : process_register_constraint_filters ()
1083 : {
1084 260454080 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1085 : {
1086 177526833 : rtx op = recog_data.operand[opno];
1087 177526833 : if (SUBREG_P (op))
1088 2867026 : op = SUBREG_REG (op);
1089 177526833 : if (REG_P (op) && !HARD_REGISTER_P (op))
1090 : {
1091 73222214 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1092 1023458403 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1093 : {
1094 950236189 : if (!TEST_BIT (preferred_alternatives, alt))
1095 829131205 : continue;
1096 :
1097 121104984 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1098 121104984 : auto cl = alternative_class (op_alt, opno);
1099 : /* The two extremes are easy:
1100 :
1101 : - We should record the filter if CL matches the
1102 : allocno class.
1103 :
1104 : - We should ignore the filter if CL and the allocno class
1105 : are disjoint. We'll either pick a different alternative
1106 : or reload the operand.
1107 :
1108 : Things are trickier if the classes overlap. However:
1109 :
1110 : - If the allocno class includes registers that are not
1111 : in CL, some choices of hard register will need a reload
1112 : anyway. It isn't obvious that reloads due to filters
1113 : are worse than reloads due to regnos being outside CL.
1114 :
1115 : - Conversely, if the allocno class is a subset of CL,
1116 : any allocation will satisfy the class requirement.
1117 : We should try to make sure it satisfies the filter
1118 : requirement too. This is useful if, for example,
1119 : an allocno needs to be in "low" registers to satisfy
1120 : some uses, and its allocno class is therefore those
1121 : low registers, but the allocno is elsewhere allowed
1122 : to be in any even-numbered register. Picking an
1123 : even-numbered low register satisfies both types of use. */
1124 121104984 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1125 28377232 : continue;
1126 :
1127 92727752 : auto filters = alternative_register_filters (op_alt, opno);
1128 92727752 : if (!filters)
1129 92727752 : continue;
1130 :
1131 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1132 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1133 : }
1134 : }
1135 : }
1136 82927247 : }
1137 :
1138 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1139 : we find a SET rtx that we can use to deduce that a register can be cheaply
1140 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1141 : static rtx
1142 5949307 : find_call_crossed_cheap_reg (rtx_insn *insn)
1143 : {
1144 5949307 : rtx cheap_reg = NULL_RTX;
1145 5949307 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1146 :
1147 18183412 : while (exp != NULL)
1148 : {
1149 12381548 : rtx x = XEXP (exp, 0);
1150 12381548 : if (GET_CODE (x) == SET)
1151 : {
1152 : exp = x;
1153 : break;
1154 : }
1155 12234105 : exp = XEXP (exp, 1);
1156 : }
1157 5949307 : if (exp != NULL)
1158 : {
1159 147443 : basic_block bb = BLOCK_FOR_INSN (insn);
1160 147443 : rtx reg = SET_SRC (exp);
1161 147443 : rtx_insn *prev = PREV_INSN (insn);
1162 294902 : while (prev && !(INSN_P (prev)
1163 147443 : && BLOCK_FOR_INSN (prev) != bb))
1164 : {
1165 147459 : if (NONDEBUG_INSN_P (prev))
1166 : {
1167 147443 : rtx set = single_set (prev);
1168 :
1169 147443 : if (set && rtx_equal_p (SET_DEST (set), reg))
1170 : {
1171 147443 : rtx src = SET_SRC (set);
1172 115658 : if (!REG_P (src) || HARD_REGISTER_P (src)
1173 262695 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1174 : break;
1175 31598 : if (!modified_between_p (src, prev, insn))
1176 5949307 : cheap_reg = src;
1177 : break;
1178 : }
1179 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1180 : {
1181 0 : rtx dest = SET_DEST (set);
1182 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1183 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1184 : break;
1185 0 : if (!modified_between_p (dest, prev, insn))
1186 5949307 : cheap_reg = dest;
1187 : break;
1188 : }
1189 :
1190 0 : if (reg_set_p (reg, prev))
1191 : break;
1192 : }
1193 16 : prev = PREV_INSN (prev);
1194 : }
1195 : }
1196 5949307 : return cheap_reg;
1197 : }
1198 :
1199 : /* Determine whether INSN is a register to register copy of the type where
1200 : we do not need to make the source and destiniation registers conflict.
1201 : If this is a copy instruction, then return the source reg. Otherwise,
1202 : return NULL_RTX. */
1203 : rtx
1204 303790912 : non_conflicting_reg_copy_p (rtx_insn *insn)
1205 : {
1206 : /* Reload has issues with overlapping pseudos being assigned to the
1207 : same hard register, so don't allow it. See PR87600 for details. */
1208 303790912 : if (!targetm.lra_p ())
1209 : return NULL_RTX;
1210 :
1211 303790912 : rtx set = single_set (insn);
1212 :
1213 : /* Disallow anything other than a simple register to register copy
1214 : that has no side effects. */
1215 303790912 : if (set == NULL_RTX
1216 288866963 : || !REG_P (SET_DEST (set))
1217 211854498 : || !REG_P (SET_SRC (set))
1218 375014266 : || side_effects_p (set))
1219 232567558 : return NULL_RTX;
1220 :
1221 71223354 : int dst_regno = REGNO (SET_DEST (set));
1222 71223354 : int src_regno = REGNO (SET_SRC (set));
1223 71223354 : machine_mode mode = GET_MODE (SET_DEST (set));
1224 :
1225 : /* By definition, a register does not conflict with itself, therefore we
1226 : do not have to handle it specially. Returning NULL_RTX now, helps
1227 : simplify the callers of this function. */
1228 71223354 : if (dst_regno == src_regno)
1229 : return NULL_RTX;
1230 :
1231 : /* Computing conflicts for register pairs is difficult to get right, so
1232 : for now, disallow it. */
1233 71223354 : if ((HARD_REGISTER_NUM_P (dst_regno)
1234 19244605 : && hard_regno_nregs (dst_regno, mode) != 1)
1235 90305668 : || (HARD_REGISTER_NUM_P (src_regno)
1236 10433174 : && hard_regno_nregs (src_regno, mode) != 1))
1237 : return NULL_RTX;
1238 :
1239 : return SET_SRC (set);
1240 : }
1241 :
1242 : #ifdef EH_RETURN_DATA_REGNO
1243 :
1244 : /* Add EH return hard registers as conflict hard registers to allocnos
1245 : living at end of BB. For most allocnos it is already done in
1246 : process_bb_node_lives when we processing input edges but it does
1247 : not work when and EH edge is edge out of the current region. This
1248 : function covers such out of region edges. */
1249 : static void
1250 14323178 : process_out_of_region_eh_regs (basic_block bb)
1251 : {
1252 14323178 : edge e;
1253 14323178 : edge_iterator ei;
1254 14323178 : unsigned int i;
1255 14323178 : bitmap_iterator bi;
1256 14323178 : bool eh_p = false;
1257 :
1258 34795110 : FOR_EACH_EDGE (e, ei, bb->succs)
1259 20471932 : if ((e->flags & EDGE_EH)
1260 20471932 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1261 : eh_p = true;
1262 :
1263 14323178 : if (! eh_p)
1264 14315618 : return;
1265 :
1266 92956 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1267 : {
1268 85396 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1269 175710 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1270 : {
1271 90314 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1272 361256 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1273 90314 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1274 : }
1275 : }
1276 : }
1277 :
1278 : #endif
1279 :
1280 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1281 : static void
1282 3470894 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1283 : function_abi callee_abi)
1284 : {
1285 3470894 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1286 3470894 : rtx_code_label *landing_label;
1287 3470894 : basic_block landing_bb;
1288 :
1289 7067598 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1290 : {
1291 5988385 : if ((landing_label = lp->landing_pad) != NULL
1292 5988385 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1293 11976719 : && (region->type != ERT_CLEANUP
1294 4496494 : || bitmap_bit_p (df_get_live_in (landing_bb),
1295 : ALLOCNO_REGNO (a))))
1296 : {
1297 2391681 : HARD_REG_SET new_conflict_regs
1298 2391681 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1299 9566724 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1300 2391681 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1301 2391681 : return;
1302 : }
1303 : }
1304 : }
1305 :
1306 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1307 : update allocno live ranges, allocno hard register conflicts,
1308 : intersected calls, and register pressure info for allocnos for the
1309 : basic block for and regions containing the basic block. */
1310 : static void
1311 16411039 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1312 : {
1313 16411039 : int i, freq;
1314 16411039 : unsigned int j;
1315 16411039 : basic_block bb;
1316 16411039 : rtx_insn *insn;
1317 16411039 : bitmap_iterator bi;
1318 16411039 : bitmap reg_live_out;
1319 16411039 : unsigned int px;
1320 16411039 : bool set_p;
1321 :
1322 16411039 : bb = loop_tree_node->bb;
1323 16411039 : if (bb != NULL)
1324 : {
1325 70451050 : for (i = 0; i < ira_pressure_classes_num; i++)
1326 : {
1327 56127872 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1328 56127872 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1329 : }
1330 14323178 : curr_bb_node = loop_tree_node;
1331 14323178 : reg_live_out = df_get_live_out (bb);
1332 14323178 : sparseset_clear (objects_live);
1333 28646356 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1334 14323178 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1335 1332055554 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1336 1317732376 : if (TEST_HARD_REG_BIT (hard_regs_live, i))
1337 : {
1338 1110288 : enum reg_class aclass, pclass, cl;
1339 :
1340 1110288 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)];
1341 1110288 : pclass = ira_pressure_class_translate[aclass];
1342 10531288 : for (j = 0;
1343 10531288 : (cl = ira_reg_class_super_classes[pclass][j])
1344 10531288 : != LIM_REG_CLASSES;
1345 : j++)
1346 : {
1347 9421000 : if (! ira_reg_pressure_class_p[cl])
1348 8310712 : continue;
1349 1110288 : curr_reg_pressure[cl]++;
1350 1110288 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1351 1110288 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1352 1110288 : ira_assert (curr_reg_pressure[cl]
1353 : <= ira_class_hard_regs_num[cl]);
1354 : }
1355 : }
1356 154283326 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1357 139960148 : mark_pseudo_regno_live (j);
1358 :
1359 : #ifdef EH_RETURN_DATA_REGNO
1360 14323178 : process_out_of_region_eh_regs (bb);
1361 : #endif
1362 :
1363 14323178 : freq = REG_FREQ_FROM_BB (bb);
1364 8523448 : if (freq == 0)
1365 2009652 : freq = 1;
1366 :
1367 : /* Invalidate all allocno_saved_at_call entries. */
1368 14323178 : last_call_num++;
1369 :
1370 : /* Scan the code of this basic block, noting which allocnos and
1371 : hard regs are born or die.
1372 :
1373 : Note that this loop treats uninitialized values as live until
1374 : the beginning of the block. For example, if an instruction
1375 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1376 : set, FOO will remain live until the beginning of the block.
1377 : Likewise if FOO is not set at all. This is unnecessarily
1378 : pessimistic, but it probably doesn't matter much in practice. */
1379 171844965 : FOR_BB_INSNS_REVERSE (bb, insn)
1380 : {
1381 157521787 : ira_allocno_t a;
1382 157521787 : df_ref def, use;
1383 157521787 : bool call_p;
1384 :
1385 157521787 : if (!NONDEBUG_INSN_P (insn))
1386 74594540 : continue;
1387 :
1388 82927247 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1389 1479 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1390 1479 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1391 : curr_point);
1392 :
1393 82927247 : call_p = CALL_P (insn);
1394 82927247 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1395 :
1396 : /* Mark each defined value as live. We need to do this for
1397 : unused values because they still conflict with quantities
1398 : that are live at the time of the definition.
1399 :
1400 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1401 : references represent the effect of the called function
1402 : on a call-clobbered register. Marking the register as
1403 : live would stop us from allocating it to a call-crossing
1404 : allocno. */
1405 637361795 : FOR_EACH_INSN_DEF (def, insn)
1406 554434548 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1407 70199647 : mark_ref_live (def);
1408 :
1409 : /* If INSN has multiple outputs, then any value used in one
1410 : of the outputs conflicts with the other outputs. Model this
1411 : by making the used value live during the output phase.
1412 :
1413 : It is unsafe to use !single_set here since it will ignore
1414 : an unused output. Just because an output is unused does
1415 : not mean the compiler can assume the side effect will not
1416 : occur. Consider if ALLOCNO appears in the address of an
1417 : output and we reload the output. If we allocate ALLOCNO
1418 : to the same hard register as an unused output we could
1419 : set the hard register before the output reload insn. */
1420 82927247 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1421 1771324 : FOR_EACH_INSN_USE (use, insn)
1422 : {
1423 1392732 : int i;
1424 1392732 : rtx reg;
1425 :
1426 1392732 : reg = DF_REF_REG (use);
1427 4394661 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1428 : {
1429 3380050 : rtx set;
1430 :
1431 3380050 : set = XVECEXP (PATTERN (insn), 0, i);
1432 3380050 : if (GET_CODE (set) == SET
1433 3380050 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1434 : {
1435 : /* After the previous loop, this is a no-op if
1436 : REG is contained within SET_DEST (SET). */
1437 378121 : mark_ref_live (use);
1438 378121 : break;
1439 : }
1440 : }
1441 : }
1442 :
1443 82927247 : preferred_alternatives = ira_setup_alts (insn);
1444 82927247 : process_register_constraint_filters ();
1445 82927247 : process_single_reg_class_operands (false, freq);
1446 :
1447 82927247 : if (call_p)
1448 : {
1449 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1450 : there, try to find a pseudo that is live across the call but
1451 : can be cheaply reconstructed from the return value. */
1452 5949307 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1453 5949307 : if (cheap_reg != NULL_RTX)
1454 31598 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1455 :
1456 5949307 : last_call_num++;
1457 5949307 : sparseset_clear (allocnos_processed);
1458 : /* The current set of live allocnos are live across the call. */
1459 468613870 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1460 : {
1461 228357628 : ira_object_t obj = ira_object_id_map[i];
1462 228357628 : a = OBJECT_ALLOCNO (obj);
1463 228357628 : int num = ALLOCNO_NUM (a);
1464 228357628 : function_abi callee_abi = insn_callee_abi (insn);
1465 :
1466 : /* Don't allocate allocnos that cross setjmps or any
1467 : call, if this function receives a nonlocal
1468 : goto. */
1469 228357628 : if (cfun->has_nonlocal_label
1470 228357628 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1471 228355059 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1472 : != NULL_RTX)))
1473 : {
1474 10788 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1475 228357628 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1476 : }
1477 228357628 : eh_region r;
1478 228357628 : if (can_throw_internal (insn)
1479 228357628 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1480 3470894 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1481 228357628 : if (sparseset_bit_p (allocnos_processed, num))
1482 103987504 : continue;
1483 124370124 : sparseset_set_bit (allocnos_processed, num);
1484 :
1485 124370124 : if (allocno_saved_at_call[num] != last_call_num)
1486 : /* Here we are mimicking caller-save.cc behavior
1487 : which does not save hard register at a call if
1488 : it was saved on previous call in the same basic
1489 : block and the hard register was not mentioned
1490 : between the two calls. */
1491 39622562 : ALLOCNO_CALL_FREQ (a) += freq;
1492 : /* Mark it as saved at the next call. */
1493 124370124 : allocno_saved_at_call[num] = last_call_num + 1;
1494 124370124 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1495 124370124 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1496 124370124 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1497 124370124 : |= callee_abi.full_and_partial_reg_clobbers ();
1498 124370124 : if (cheap_reg != NULL_RTX
1499 124370124 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1500 31598 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1501 : }
1502 : }
1503 :
1504 : /* See which defined values die here. Note that we include
1505 : the call insn in the lifetimes of these values, so we don't
1506 : mistakenly consider, for e.g. an addressing mode with a
1507 : side-effect like a post-increment fetching the address,
1508 : that the use happens before the call, and the def to happen
1509 : after the call: we believe both to happen before the actual
1510 : call. (We don't handle return-values here.) */
1511 637361795 : FOR_EACH_INSN_DEF (def, insn)
1512 554434548 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1513 70199647 : mark_ref_dead (def);
1514 :
1515 82927247 : make_early_clobber_and_input_conflicts ();
1516 :
1517 82927247 : curr_point++;
1518 :
1519 : /* Mark each used value as live. */
1520 182949826 : FOR_EACH_INSN_USE (use, insn)
1521 100022579 : mark_ref_live (use);
1522 :
1523 82927247 : process_single_reg_class_operands (true, freq);
1524 :
1525 82927247 : set_p = mark_hard_reg_early_clobbers (insn, true);
1526 :
1527 82927247 : if (set_p)
1528 : {
1529 10525532 : mark_hard_reg_early_clobbers (insn, false);
1530 :
1531 : /* Mark each hard reg as live again. For example, a
1532 : hard register can be in clobber and in an insn
1533 : input. */
1534 26018400 : FOR_EACH_INSN_USE (use, insn)
1535 : {
1536 15492868 : rtx ureg = DF_REF_REG (use);
1537 :
1538 15492868 : if (GET_CODE (ureg) == SUBREG)
1539 303749 : ureg = SUBREG_REG (ureg);
1540 15492868 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1541 9574127 : continue;
1542 :
1543 5918741 : mark_ref_live (use);
1544 : }
1545 : }
1546 :
1547 82927247 : curr_point++;
1548 : }
1549 14323178 : ignore_reg_for_conflicts = NULL_RTX;
1550 :
1551 14323178 : if (bb_has_eh_pred (bb))
1552 211386 : for (j = 0; ; ++j)
1553 : {
1554 634158 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1555 422772 : if (regno == INVALID_REGNUM)
1556 : break;
1557 422772 : make_hard_regno_live (regno);
1558 422772 : }
1559 :
1560 : /* Allocnos can't go in stack regs at the start of a basic block
1561 : that is reached by an abnormal edge. Likewise for registers
1562 : that are at least partly call clobbered, because caller-save,
1563 : fixup_abnormal_edges and possibly the table driven EH machinery
1564 : are not quite ready to handle such allocnos live across such
1565 : edges. */
1566 14323178 : if (bb_has_abnormal_pred (bb))
1567 : {
1568 : #ifdef STACK_REGS
1569 673342 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1570 : {
1571 459539 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1572 :
1573 459539 : ALLOCNO_NO_STACK_REG_P (a) = true;
1574 459539 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1575 : }
1576 1924227 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1577 1710424 : make_hard_regno_live (px);
1578 : #endif
1579 : /* No need to record conflicts for call clobbered regs if we
1580 : have nonlocal labels around, as we don't ever try to
1581 : allocate such regs in this case. */
1582 213803 : if (!cfun->has_nonlocal_label
1583 213803 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1584 19658061 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1585 19446684 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1586 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1587 : /* We should create a conflict of PIC pseudo with
1588 : PIC hard reg as PIC hard reg can have a wrong
1589 : value after jump described by the abnormal edge.
1590 : In this case we cannot allocate PIC hard reg to
1591 : PIC pseudo as PIC pseudo will also have a wrong
1592 : value. This code is not critical as LRA can fix
1593 : it but it is better to have the right allocation
1594 : earlier. */
1595 19586005 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1596 211377 : && pic_offset_table_rtx != NULL_RTX
1597 6301 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1598 : #endif
1599 : )
1600 17590398 : make_hard_regno_live (px);
1601 : }
1602 :
1603 218758498 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1604 204435320 : make_object_dead (ira_object_id_map[i]);
1605 :
1606 14323178 : curr_point++;
1607 :
1608 : }
1609 : /* Propagate register pressure to upper loop tree nodes. */
1610 16411039 : if (loop_tree_node != ira_loop_tree_root)
1611 73526779 : for (i = 0; i < ira_pressure_classes_num; i++)
1612 : {
1613 58590154 : enum reg_class pclass;
1614 :
1615 58590154 : pclass = ira_pressure_classes[i];
1616 58590154 : if (loop_tree_node->reg_pressure[pclass]
1617 58590154 : > loop_tree_node->parent->reg_pressure[pclass])
1618 4202165 : loop_tree_node->parent->reg_pressure[pclass]
1619 4202165 : = loop_tree_node->reg_pressure[pclass];
1620 : }
1621 16411039 : }
1622 :
1623 : /* Create and set up IRA_START_POINT_RANGES and
1624 : IRA_FINISH_POINT_RANGES. */
1625 : static void
1626 3108735 : create_start_finish_chains (void)
1627 : {
1628 3108735 : ira_object_t obj;
1629 3108735 : ira_object_iterator oi;
1630 3108735 : live_range_t r;
1631 :
1632 3108735 : ira_start_point_ranges
1633 3108735 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1634 3108735 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1635 3108735 : ira_finish_point_ranges
1636 3108735 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1637 3108735 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1638 80138830 : FOR_EACH_OBJECT (obj, oi)
1639 182402483 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1640 : {
1641 105372388 : r->start_next = ira_start_point_ranges[r->start];
1642 105372388 : ira_start_point_ranges[r->start] = r;
1643 105372388 : r->finish_next = ira_finish_point_ranges[r->finish];
1644 105372388 : ira_finish_point_ranges[r->finish] = r;
1645 : }
1646 3108735 : }
1647 :
1648 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1649 : new live ranges and program points were added as a result if new
1650 : insn generation. */
1651 : void
1652 1634321 : ira_rebuild_start_finish_chains (void)
1653 : {
1654 1634321 : ira_free (ira_finish_point_ranges);
1655 1634321 : ira_free (ira_start_point_ranges);
1656 1634321 : create_start_finish_chains ();
1657 1634321 : }
1658 :
1659 : /* Compress allocno live ranges by removing program points where
1660 : nothing happens. */
1661 : static void
1662 1474414 : remove_some_program_points_and_update_live_ranges (void)
1663 : {
1664 1474414 : unsigned i;
1665 1474414 : int n;
1666 1474414 : int *map;
1667 1474414 : ira_object_t obj;
1668 1474414 : ira_object_iterator oi;
1669 1474414 : live_range_t r, prev_r, next_r;
1670 1474414 : sbitmap_iterator sbi;
1671 1474414 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1672 :
1673 1474414 : auto_sbitmap born (ira_max_point);
1674 1474414 : auto_sbitmap dead (ira_max_point);
1675 1474414 : bitmap_clear (born);
1676 1474414 : bitmap_clear (dead);
1677 35410622 : FOR_EACH_OBJECT (obj, oi)
1678 87030821 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1679 : {
1680 53094613 : ira_assert (r->start <= r->finish);
1681 53094613 : bitmap_set_bit (born, r->start);
1682 53094613 : bitmap_set_bit (dead, r->finish);
1683 : }
1684 :
1685 1474414 : auto_sbitmap born_or_dead (ira_max_point);
1686 1474414 : bitmap_ior (born_or_dead, born, dead);
1687 1474414 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1688 1474414 : n = -1;
1689 1474414 : prev_born_p = prev_dead_p = false;
1690 66230787 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1691 : {
1692 63281959 : born_p = bitmap_bit_p (born, i);
1693 63281959 : dead_p = bitmap_bit_p (dead, i);
1694 63281959 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1695 57227916 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1696 15951623 : map[i] = n;
1697 : else
1698 47330336 : map[i] = ++n;
1699 63281959 : prev_born_p = born_p;
1700 63281959 : prev_dead_p = dead_p;
1701 : }
1702 :
1703 1474414 : n++;
1704 1474414 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1705 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1706 95 : ira_max_point, n, 100 * n / ira_max_point);
1707 1474414 : ira_max_point = n;
1708 :
1709 35410622 : FOR_EACH_OBJECT (obj, oi)
1710 87030821 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1711 : {
1712 53094613 : next_r = r->next;
1713 53094613 : r->start = map[r->start];
1714 53094613 : r->finish = map[r->finish];
1715 53094613 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1716 : {
1717 40585441 : prev_r = r;
1718 40585441 : continue;
1719 : }
1720 12509172 : prev_r->start = r->start;
1721 12509172 : prev_r->next = next_r;
1722 12509172 : ira_finish_live_range (r);
1723 : }
1724 :
1725 1474414 : ira_free (map);
1726 1474414 : }
1727 :
1728 : /* Print live ranges R to file F. */
1729 : void
1730 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1731 : {
1732 3234 : for (; r != NULL; r = r->next)
1733 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1734 1466 : fprintf (f, "\n");
1735 1466 : }
1736 :
1737 : DEBUG_FUNCTION void
1738 0 : debug (live_range &ref)
1739 : {
1740 0 : ira_print_live_range_list (stderr, &ref);
1741 0 : }
1742 :
1743 : DEBUG_FUNCTION void
1744 0 : debug (live_range *ptr)
1745 : {
1746 0 : if (ptr)
1747 0 : debug (*ptr);
1748 : else
1749 0 : fprintf (stderr, "<nil>\n");
1750 0 : }
1751 :
1752 : /* Print live ranges R to stderr. */
1753 : void
1754 0 : ira_debug_live_range_list (live_range_t r)
1755 : {
1756 0 : ira_print_live_range_list (stderr, r);
1757 0 : }
1758 :
1759 : /* Print live ranges of object OBJ to file F. */
1760 : static void
1761 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1762 : {
1763 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1764 0 : }
1765 :
1766 : /* Print live ranges of allocno A to file F. */
1767 : static void
1768 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1769 : {
1770 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1771 1328 : int i;
1772 :
1773 2656 : for (i = 0; i < n; i++)
1774 : {
1775 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1776 1328 : if (n > 1)
1777 0 : fprintf (f, " [%d]", i);
1778 1328 : fprintf (f, "):");
1779 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1780 : }
1781 1328 : }
1782 :
1783 : /* Print live ranges of allocno A to stderr. */
1784 : void
1785 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1786 : {
1787 0 : print_allocno_live_ranges (stderr, a);
1788 0 : }
1789 :
1790 : /* Print live ranges of all allocnos to file F. */
1791 : static void
1792 190 : print_live_ranges (FILE *f)
1793 : {
1794 190 : ira_allocno_t a;
1795 190 : ira_allocno_iterator ai;
1796 :
1797 1518 : FOR_EACH_ALLOCNO (a, ai)
1798 1328 : print_allocno_live_ranges (f, a);
1799 190 : }
1800 :
1801 : /* Print live ranges of all allocnos to stderr. */
1802 : void
1803 0 : ira_debug_live_ranges (void)
1804 : {
1805 0 : print_live_ranges (stderr);
1806 0 : }
1807 :
1808 : /* The main entry function creates live ranges, set up
1809 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1810 : calculate register pressure info. */
1811 : void
1812 1474414 : ira_create_allocno_live_ranges (void)
1813 : {
1814 1474414 : objects_live = sparseset_alloc (ira_objects_num);
1815 1474414 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1816 1474414 : curr_point = 0;
1817 1474414 : last_call_num = 0;
1818 1474414 : allocno_saved_at_call
1819 1474414 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1820 1474414 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1821 1474414 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1822 : process_bb_node_lives);
1823 1474414 : ira_max_point = curr_point;
1824 1474414 : create_start_finish_chains ();
1825 1474414 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1826 95 : print_live_ranges (ira_dump_file);
1827 : /* Clean up. */
1828 1474414 : ira_free (allocno_saved_at_call);
1829 1474414 : sparseset_free (objects_live);
1830 1474414 : sparseset_free (allocnos_processed);
1831 1474414 : }
1832 :
1833 : /* Compress allocno live ranges. */
1834 : void
1835 1474414 : ira_compress_allocno_live_ranges (void)
1836 : {
1837 1474414 : remove_some_program_points_and_update_live_ranges ();
1838 1474414 : ira_rebuild_start_finish_chains ();
1839 1474414 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1840 : {
1841 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1842 95 : print_live_ranges (ira_dump_file);
1843 : }
1844 1474414 : }
1845 :
1846 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1847 : void
1848 1474414 : ira_finish_allocno_live_ranges (void)
1849 : {
1850 1474414 : ira_free (ira_finish_point_ranges);
1851 1474414 : ira_free (ira_start_point_ranges);
1852 1474414 : }
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