Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 37257430 : make_hard_regno_live (int regno)
98 : {
99 37257430 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 35160352 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 16318799 : make_hard_regno_dead (int regno)
106 : {
107 16318799 : unsigned int i;
108 279833078 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 263514279 : ira_object_t obj = ira_object_id_map[i];
111 :
112 265120403 : if (ignore_reg_for_conflicts != NULL_RTX
113 172514459 : && REGNO (ignore_reg_for_conflicts)
114 172514459 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1606124 : continue;
116 :
117 261908155 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 261908155 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 16318799 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 16318799 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 240802089 : make_object_live (ira_object_t obj)
127 : {
128 240802089 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 240802089 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 240802089 : if (lr == NULL
132 204276592 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 54215144 : ira_add_live_range_to_object (obj, curr_point, -1);
134 240802089 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 248043624 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 248043624 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 248043624 : int start, i;
143 248043624 : enum reg_class aclass, pclass, cl;
144 248043624 : live_range_t p;
145 :
146 248043624 : aclass = ALLOCNO_CLASS (a);
147 248043624 : pclass = ira_pressure_class_translate[aclass];
148 2437843873 : for (i = 0;
149 2437843873 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2189800249 : if (! ira_reg_pressure_class_p[cl])
153 1946438999 : continue;
154 243361250 : if (high_pressure_start_point[cl] < 0)
155 72658138 : continue;
156 170703112 : p = OBJECT_LIVE_RANGES (obj);
157 170703112 : ira_assert (p != NULL);
158 170703112 : start = (high_pressure_start_point[cl] > p->start
159 170703112 : ? high_pressure_start_point[cl] : p->start);
160 170703112 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 248043624 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 240802089 : make_object_dead (ira_object_t obj)
168 : {
169 240802089 : live_range_t lr;
170 240802089 : int regno;
171 240802089 : int ignore_regno = -1;
172 240802089 : int ignore_total_regno = -1;
173 240802089 : int end_regno = -1;
174 :
175 240802089 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 240802089 : if (ignore_reg_for_conflicts != NULL_RTX
180 240802089 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3403419 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3403419 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6806838 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3403419 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 520118 : ignore_regno = end_regno;
189 3403419 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 520118 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 963208356 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 243685390 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 243685390 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2883301 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 243685390 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2883301 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 240802089 : lr = OBJECT_LIVE_RANGES (obj);
205 240802089 : ira_assert (lr != NULL);
206 240802089 : lr->finish = curr_point;
207 240802089 : update_allocno_pressure_excess_length (obj);
208 240802089 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 258673424 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 258673424 : int i;
222 258673424 : enum reg_class cl;
223 :
224 2537398110 : for (i = 0;
225 2537398110 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2278724686 : if (! ira_reg_pressure_class_p[cl])
229 2024494343 : continue;
230 254230343 : curr_reg_pressure[cl] += n;
231 254230343 : if (high_pressure_start_point[cl] < 0
232 105051981 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1749187 : high_pressure_start_point[cl] = curr_point;
234 254230343 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 218776171 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 258673424 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 53318244 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 53318244 : int i;
248 53318244 : unsigned int j;
249 53318244 : enum reg_class cl;
250 53318244 : bool set_p = false;
251 :
252 53318244 : for (i = 0;
253 513956490 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 460638246 : if (! ira_reg_pressure_class_p[cl])
257 407791973 : continue;
258 52846273 : curr_reg_pressure[cl] -= nregs;
259 52846273 : ira_assert (curr_reg_pressure[cl] >= 0);
260 52846273 : if (high_pressure_start_point[cl] >= 0
261 4623176 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 460638246 : set_p = true;
263 : }
264 53318244 : if (set_p)
265 : {
266 7714248 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7241535 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4494636 : for (i = 0;
269 4967349 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4494636 : if (! ira_reg_pressure_class_p[cl])
273 4021923 : continue;
274 472713 : if (high_pressure_start_point[cl] >= 0
275 472713 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 472713 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 53318244 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 115496 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 115496 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 115496 : ira_object_t obj;
288 :
289 115496 : if (a == NULL)
290 : return false;
291 115496 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 115496 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 115496 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 224828065 : mark_pseudo_regno_live (int regno)
303 : {
304 224828065 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 224828065 : enum reg_class pclass;
306 224828065 : int i, n, nregs;
307 :
308 224828065 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 224828065 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 224828065 : n = ALLOCNO_NUM_OBJECTS (a);
315 224828065 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 224828065 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 224828065 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69816885 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 519473015 : for (i = 0; i < n; i++)
325 : {
326 294644950 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 294644950 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 54155441 : continue;
330 :
331 240489509 : inc_register_pressure (pclass, nregs);
332 240489509 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 835773 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 835773 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 835773 : int n;
344 835773 : enum reg_class pclass;
345 835773 : ira_object_t obj;
346 :
347 835773 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 835773 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 835773 : n = ALLOCNO_NUM_OBJECTS (a);
354 835773 : if (n == 1)
355 : {
356 37879 : mark_pseudo_regno_live (regno);
357 37879 : return;
358 : }
359 :
360 797894 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 797894 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 797894 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 797894 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 312580 : inc_register_pressure (pclass, 1);
369 312580 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 103881266 : mark_hard_reg_live (rtx reg)
377 : {
378 103881266 : int regno = REGNO (reg);
379 :
380 103881266 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 32605879 : int last = END_REGNO (reg);
383 32605879 : enum reg_class aclass, pclass;
384 :
385 65211758 : while (regno < last)
386 : {
387 32605879 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 32605879 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 17871335 : aclass = ira_hard_regno_allocno_class[regno];
391 17871335 : pclass = ira_pressure_class_translate[aclass];
392 17871335 : inc_register_pressure (pclass, 1);
393 17871335 : make_hard_regno_live (regno);
394 : }
395 32605879 : regno++;
396 : }
397 : }
398 103881266 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 86336355 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 86336355 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1247742 : mark_pseudo_regno_subword_live (regno,
409 835773 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 85500582 : mark_pseudo_regno_live (regno);
413 86336355 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 188407933 : mark_ref_live (df_ref ref)
418 : {
419 188407933 : rtx reg = DF_REF_REG (ref);
420 188407933 : rtx orig_reg = reg;
421 :
422 188407933 : if (GET_CODE (reg) == SUBREG)
423 2909765 : reg = SUBREG_REG (reg);
424 :
425 188407933 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 84526667 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 103881266 : mark_hard_reg_live (reg);
429 188407933 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 35393214 : mark_pseudo_regno_dead (int regno)
435 : {
436 35393214 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 35393214 : int n, i, nregs;
438 35393214 : enum reg_class cl;
439 :
440 35393214 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 35393214 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 35393214 : n = ALLOCNO_NUM_OBJECTS (a);
447 35393214 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 35393214 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 35393214 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1276009 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 72062437 : for (i = 0; i < n; i++)
456 : {
457 36669223 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 36669223 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3552 : continue;
460 :
461 36665671 : dec_register_pressure (cl, nregs);
462 36665671 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 337900 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 337900 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 337900 : int n;
473 337900 : enum reg_class cl;
474 337900 : ira_object_t obj;
475 :
476 337900 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 337900 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 337900 : n = ALLOCNO_NUM_OBJECTS (a);
483 337900 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 333774 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 333774 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 333774 : obj = ALLOCNO_OBJECT (a, subword);
492 333774 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 333774 : dec_register_pressure (cl, 1);
496 333774 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 47926343 : mark_hard_reg_dead (rtx reg)
503 : {
504 47926343 : int regno = REGNO (reg);
505 :
506 47926343 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 16320817 : int last = END_REGNO (reg);
509 16320817 : enum reg_class aclass, pclass;
510 :
511 32641634 : while (regno < last)
512 : {
513 16320817 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 16318799 : aclass = ira_hard_regno_allocno_class[regno];
516 16318799 : pclass = ira_pressure_class_translate[aclass];
517 16318799 : dec_register_pressure (pclass, 1);
518 16318799 : make_hard_regno_dead (regno);
519 : }
520 16320817 : regno++;
521 : }
522 : }
523 47926343 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 35731114 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 35731114 : if (read_modify_subreg_p (orig_reg))
532 : {
533 506803 : mark_pseudo_regno_subword_dead (regno,
534 337900 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 35393214 : mark_pseudo_regno_dead (regno);
538 35731114 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 81851935 : mark_ref_dead (df_ref def)
544 : {
545 81851935 : rtx reg = DF_REF_REG (def);
546 81851935 : rtx orig_reg = reg;
547 :
548 81851935 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 81851935 : if (GET_CODE (reg) == SUBREG)
552 898845 : reg = SUBREG_REG (reg);
553 :
554 81851935 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 81851935 : && (GET_CODE (orig_reg) != SUBREG
556 328771 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 328771 : || !read_modify_subreg_p (orig_reg)))
558 4166 : return;
559 :
560 81847769 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 33921426 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 47926343 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2802940 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2802940 : rtx orig_reg = reg;
577 2802940 : ira_allocno_t a;
578 :
579 2802940 : if (GET_CODE (reg) == SUBREG)
580 75578 : reg = SUBREG_REG (reg);
581 :
582 2802940 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 996005 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 996005 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 904844 : if (advance_p)
590 860206 : curr_point++;
591 :
592 904844 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 904844 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 904844 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 904844 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 904844 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 2849626 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 2849626 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2787277 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2787277 : if (use < recog_data.n_operands - 1
624 1063260 : && recog_data.constraints[use][0] == '%')
625 6539 : advance_p
626 6539 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2787277 : if (use >= 1
629 2786976 : && recog_data.constraints[use - 1][0] == '%')
630 9124 : advance_p
631 9124 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14215635 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14215635 : int use, use_match;
662 14215635 : ira_allocno_t a;
663 14215635 : enum reg_class use_cl, acl;
664 14215635 : bool advance_p;
665 14215635 : rtx dreg = recog_data.operand[def];
666 14215635 : rtx orig_dreg = dreg;
667 :
668 14215635 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14215635 : if (GET_CODE (dreg) == SUBREG)
672 112015 : dreg = SUBREG_REG (dreg);
673 :
674 14215635 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 12009345 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 12009345 : acl = ALLOCNO_CLASS (a);
679 12009345 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 11818370 : advance_p = true;
683 :
684 11818370 : int n_operands = recog_data.n_operands;
685 11818370 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 48907437 : for (use = 0; use < n_operands; use++)
687 : {
688 37089067 : int alt1;
689 :
690 37089067 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 11964775 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 36876485 : if (op_alt[use].matches == def
701 25124292 : || (for_tie_p
702 13139880 : && rtx_equal_p (recog_data.operand[use],
703 13139880 : recog_data.operand[op_alt[def].matched])))
704 11752193 : continue;
705 :
706 13372099 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 11742762 : use_cl = op_alt[use].cl;
710 11742762 : if (use_cl == NO_REGS)
711 4716846 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 8655253 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 981898 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 20468428 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 17618803 : if (!TEST_BIT (preferred_alternatives, alt1))
730 8472540 : continue;
731 9146263 : const operand_alternative *op_alt1
732 9146263 : = &recog_op_alt[alt1 * n_operands];
733 9146263 : if (op_alt1[use].matches == def
734 7342079 : || (use < n_operands - 1
735 2709730 : && recog_data.constraints[use][0] == '%'
736 8195 : && op_alt1[use + 1].matches == def)
737 7342079 : || (use >= 1
738 7340556 : && recog_data.constraints[use - 1][0] == '%'
739 3024919 : && op_alt1[use - 1].matches == def))
740 : break;
741 4327940 : if (for_tie_p
742 4129983 : && !op_alt1[def].earlyclobber
743 4128823 : && op_alt1[def].matched < 0
744 24074 : && alternative_class (op_alt1, def) != NO_REGS
745 4352014 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 7673355 : if (alt1 < recog_data.n_alternatives)
750 4823730 : continue;
751 :
752 2849625 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 2849625 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 83033873 : make_early_clobber_and_input_conflicts (void)
779 : {
780 83033873 : int alt;
781 83033873 : int def, def_match;
782 83033873 : enum reg_class def_cl;
783 :
784 83033873 : int n_alternatives = recog_data.n_alternatives;
785 83033873 : int n_operands = recog_data.n_operands;
786 83033873 : const operand_alternative *op_alt = recog_op_alt;
787 1141594021 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1058560148 : if (TEST_BIT (preferred_alternatives, alt))
789 383291278 : for (def = 0; def < n_operands; def++)
790 : {
791 264542024 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 250627586 : def_cl = op_alt[def].cl;
795 250627586 : if (def_cl != NO_REGS)
796 : {
797 209259403 : if (op_alt[def].earlyclobber)
798 129733 : check_and_make_def_conflict (alt, def, def_cl, false);
799 209129670 : else if (op_alt[def].matched >= 0
800 209129670 : && !targetm.class_likely_spilled_p (def_cl))
801 14050788 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 264542024 : if ((def_match = op_alt[def].matches) >= 0
805 264542024 : && (op_alt[def_match].earlyclobber
806 14722866 : || op_alt[def].earlyclobber))
807 : {
808 35114 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 35114 : def_cl = op_alt[def_match].cl;
812 35114 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 83033873 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 93619023 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 93619023 : df_ref def;
823 93619023 : bool set_p = false;
824 :
825 676068750 : FOR_EACH_INSN_DEF (def, insn)
826 582449727 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 23068883 : rtx dreg = DF_REF_REG (def);
829 :
830 23068883 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 23068883 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 142107 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 22926776 : if (live_p)
839 11463388 : mark_ref_live (def);
840 : else
841 11463388 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 93619023 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the class of the hard register.
850 : Otherwise it returns NO_REGS. */
851 : static enum reg_class
852 175728898 : single_reg_class (const char *constraints, rtx op, rtx equiv_const)
853 : {
854 175728898 : int c;
855 175728898 : enum reg_class cl, next_cl;
856 175728898 : enum constraint_num cn;
857 :
858 175728898 : cl = NO_REGS;
859 175728898 : alternative_mask preferred = preferred_alternatives;
860 912673023 : while ((c = *constraints))
861 : {
862 898889513 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 898889513 : else if (c == ',')
865 245596504 : preferred >>= 1;
866 653293009 : else if (preferred & 1)
867 198174001 : switch (c)
868 : {
869 : case 'g':
870 : return NO_REGS;
871 :
872 178293376 : default:
873 : /* ??? Is this the best way to handle memory constraints? */
874 178293376 : cn = lookup_constraint (constraints);
875 178293376 : if (insn_extra_memory_constraint (cn)
876 166300538 : || insn_extra_special_memory_constraint (cn)
877 : || insn_extra_relaxed_memory_constraint (cn)
878 344593912 : || insn_extra_address_constraint (cn))
879 : return NO_REGS;
880 165718339 : if (constraint_satisfied_p (op, cn)
881 165718339 : || (equiv_const != NULL_RTX
882 0 : && CONSTANT_P (equiv_const)
883 0 : && constraint_satisfied_p (equiv_const, cn)))
884 14488528 : return NO_REGS;
885 151229811 : next_cl = reg_class_for_constraint (cn);
886 120151399 : if (next_cl == NO_REGS)
887 : break;
888 116939076 : if (cl == NO_REGS
889 116939076 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
890 989194 : : (ira_class_singleton[cl][GET_MODE (op)]
891 989194 : != ira_class_singleton[next_cl][GET_MODE (op)]))
892 : return NO_REGS;
893 : cl = next_cl;
894 : break;
895 :
896 12735044 : case '0': case '1': case '2': case '3': case '4':
897 12735044 : case '5': case '6': case '7': case '8': case '9':
898 12735044 : {
899 12735044 : char *end;
900 12735044 : unsigned long dup = strtoul (constraints, &end, 10);
901 12735044 : constraints = end;
902 12735044 : next_cl
903 12735044 : = single_reg_class (recog_data.constraints[dup],
904 : recog_data.operand[dup], NULL_RTX);
905 12735044 : if (cl == NO_REGS
906 12735044 : ? ira_class_singleton[next_cl][GET_MODE (op)] < 0
907 17900 : : (ira_class_singleton[cl][GET_MODE (op)]
908 17900 : != ira_class_singleton[next_cl][GET_MODE (op)]))
909 12521115 : return NO_REGS;
910 213929 : cl = next_cl;
911 213929 : continue;
912 213929 : }
913 : }
914 736730196 : constraints += CONSTRAINT_LEN (c, constraints);
915 : }
916 : return cl;
917 : }
918 :
919 : /* The function checks that operand OP_NUM of the current insn can use
920 : only one hard register. If it is so, the function returns the
921 : class of the hard register. Otherwise it returns NO_REGS. */
922 : static enum reg_class
923 177919115 : single_reg_operand_class (int op_num)
924 : {
925 177919115 : if (op_num < 0 || recog_data.n_alternatives == 0)
926 : return NO_REGS;
927 162993854 : return single_reg_class (recog_data.constraints[op_num],
928 162993854 : recog_data.operand[op_num], NULL_RTX);
929 : }
930 :
931 : /* The function sets up hard register set *SET to hard registers which
932 : might be used by insn reloads because the constraints are too
933 : strict. */
934 : void
935 27877 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
936 : alternative_mask preferred)
937 : {
938 27877 : int i, c, regno = 0;
939 27877 : enum reg_class cl;
940 27877 : rtx op;
941 27877 : machine_mode mode;
942 :
943 27877 : CLEAR_HARD_REG_SET (*set);
944 86257 : for (i = 0; i < recog_data.n_operands; i++)
945 : {
946 58380 : op = recog_data.operand[i];
947 :
948 58380 : if (GET_CODE (op) == SUBREG)
949 1208 : op = SUBREG_REG (op);
950 :
951 58380 : if (GET_CODE (op) == SCRATCH
952 58380 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
953 : {
954 39304 : const char *p = recog_data.constraints[i];
955 :
956 78608 : mode = (GET_CODE (op) == SCRATCH
957 39304 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
958 39304 : cl = NO_REGS;
959 39304 : for (alternative_mask curr_preferred = preferred;
960 1433473 : (c = *p);
961 1394169 : p += CONSTRAINT_LEN (c, p))
962 1394169 : if (c == '#')
963 0 : curr_preferred &= ~ALTERNATIVE_BIT (0);
964 1394169 : else if (c == ',')
965 475216 : curr_preferred >>= 1;
966 918953 : else if (curr_preferred & 1)
967 : {
968 575119 : cl = reg_class_for_constraint (lookup_constraint (p));
969 249077 : if (cl != NO_REGS)
970 : {
971 : /* There is no register pressure problem if all of the
972 : regs in this class are fixed. */
973 244960 : int regno = ira_class_singleton[cl][mode];
974 244960 : if (regno >= 0)
975 1835 : add_to_hard_reg_set (set, mode, regno);
976 : }
977 330159 : else if (c == '{')
978 : {
979 0 : int regno = decode_hard_reg_constraint (p);
980 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
981 0 : add_to_hard_reg_set (set, mode, regno);
982 : }
983 : }
984 : }
985 : }
986 27877 : }
987 : /* Processes input operands, if IN_P, or output operands otherwise of
988 : the current insn with FREQ to find allocno which can use only one
989 : hard register and makes other currently living allocnos conflicting
990 : with the hard register. */
991 : static void
992 166067746 : process_single_reg_class_operands (bool in_p, int freq)
993 : {
994 166067746 : int i, regno;
995 166067746 : unsigned int px;
996 166067746 : enum reg_class cl;
997 166067746 : rtx operand;
998 166067746 : ira_allocno_t operand_a, a;
999 :
1000 521746810 : for (i = 0; i < recog_data.n_operands; i++)
1001 : {
1002 355679064 : operand = recog_data.operand[i];
1003 355679064 : if (in_p && recog_data.operand_type[i] != OP_IN
1004 60677979 : && recog_data.operand_type[i] != OP_INOUT)
1005 60598396 : continue;
1006 177839532 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1007 117241136 : && recog_data.operand_type[i] != OP_INOUT)
1008 117161553 : continue;
1009 177919115 : cl = single_reg_operand_class (i);
1010 177919115 : if (cl == NO_REGS)
1011 177202518 : continue;
1012 :
1013 716597 : operand_a = NULL;
1014 :
1015 716597 : if (GET_CODE (operand) == SUBREG)
1016 57605 : operand = SUBREG_REG (operand);
1017 :
1018 716597 : if (REG_P (operand)
1019 716597 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1020 : {
1021 712060 : enum reg_class aclass;
1022 :
1023 712060 : operand_a = ira_curr_regno_allocno_map[regno];
1024 712060 : aclass = ALLOCNO_CLASS (operand_a);
1025 712060 : if (ira_class_subset_p[cl][aclass])
1026 : {
1027 : /* View the desired allocation of OPERAND as:
1028 :
1029 : (REG:YMODE YREGNO),
1030 :
1031 : a simplification of:
1032 :
1033 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1034 705608 : machine_mode ymode, xmode;
1035 705608 : int xregno, yregno;
1036 705608 : poly_int64 offset;
1037 :
1038 705608 : xmode = recog_data.operand_mode[i];
1039 705608 : xregno = ira_class_singleton[cl][xmode];
1040 705608 : gcc_assert (xregno >= 0);
1041 705608 : ymode = ALLOCNO_MODE (operand_a);
1042 705608 : offset = subreg_lowpart_offset (ymode, xmode);
1043 705608 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1044 705608 : if (yregno >= 0
1045 705608 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1046 : {
1047 705608 : int cost;
1048 :
1049 705608 : ira_allocate_and_set_costs
1050 705608 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1051 : aclass, 0);
1052 705608 : ira_init_register_move_cost_if_necessary (xmode);
1053 1411216 : cost = freq * (in_p
1054 705608 : ? ira_register_move_cost[xmode][aclass][cl]
1055 408752 : : ira_register_move_cost[xmode][cl][aclass]);
1056 705608 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1057 705608 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1058 : }
1059 : }
1060 : }
1061 :
1062 29156766 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1063 : {
1064 28440169 : ira_object_t obj = ira_object_id_map[px];
1065 28440169 : a = OBJECT_ALLOCNO (obj);
1066 28440169 : if (a != operand_a)
1067 : {
1068 : /* We could increase costs of A instead of making it
1069 : conflicting with the hard register. But it works worse
1070 : because it will be spilled in reload in anyway. */
1071 110775096 : OBJECT_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1072 28440169 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= reg_class_contents[cl];
1073 : }
1074 : }
1075 : }
1076 166067746 : }
1077 :
1078 : /* Go through the operands of the extracted insn looking for operand
1079 : alternatives that apply a register filter. Record any such filters
1080 : in the operand's allocno. */
1081 : static void
1082 83033873 : process_register_constraint_filters ()
1083 : {
1084 260873405 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1085 : {
1086 177839532 : rtx op = recog_data.operand[opno];
1087 177839532 : if (SUBREG_P (op))
1088 2873226 : op = SUBREG_REG (op);
1089 177839532 : if (REG_P (op) && !HARD_REGISTER_P (op))
1090 : {
1091 73423805 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1092 1042906829 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1093 : {
1094 969483024 : if (!TEST_BIT (preferred_alternatives, alt))
1095 848009320 : continue;
1096 :
1097 121473704 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1098 121473704 : auto cl = alternative_class (op_alt, opno);
1099 : /* The two extremes are easy:
1100 :
1101 : - We should record the filter if CL matches the
1102 : allocno class.
1103 :
1104 : - We should ignore the filter if CL and the allocno class
1105 : are disjoint. We'll either pick a different alternative
1106 : or reload the operand.
1107 :
1108 : Things are trickier if the classes overlap. However:
1109 :
1110 : - If the allocno class includes registers that are not
1111 : in CL, some choices of hard register will need a reload
1112 : anyway. It isn't obvious that reloads due to filters
1113 : are worse than reloads due to regnos being outside CL.
1114 :
1115 : - Conversely, if the allocno class is a subset of CL,
1116 : any allocation will satisfy the class requirement.
1117 : We should try to make sure it satisfies the filter
1118 : requirement too. This is useful if, for example,
1119 : an allocno needs to be in "low" registers to satisfy
1120 : some uses, and its allocno class is therefore those
1121 : low registers, but the allocno is elsewhere allowed
1122 : to be in any even-numbered register. Picking an
1123 : even-numbered low register satisfies both types of use. */
1124 121473704 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1125 28451107 : continue;
1126 :
1127 93022597 : auto filters = alternative_register_filters (op_alt, opno);
1128 93022597 : if (!filters)
1129 93022597 : continue;
1130 :
1131 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1132 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1133 : }
1134 : }
1135 : }
1136 83033873 : }
1137 :
1138 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1139 : we find a SET rtx that we can use to deduce that a register can be cheaply
1140 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1141 : static rtx
1142 5963612 : find_call_crossed_cheap_reg (rtx_insn *insn)
1143 : {
1144 5963612 : rtx cheap_reg = NULL_RTX;
1145 5963612 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1146 :
1147 18243690 : while (exp != NULL)
1148 : {
1149 12427753 : rtx x = XEXP (exp, 0);
1150 12427753 : if (GET_CODE (x) == SET)
1151 : {
1152 : exp = x;
1153 : break;
1154 : }
1155 12280078 : exp = XEXP (exp, 1);
1156 : }
1157 5963612 : if (exp != NULL)
1158 : {
1159 147675 : basic_block bb = BLOCK_FOR_INSN (insn);
1160 147675 : rtx reg = SET_SRC (exp);
1161 147675 : rtx_insn *prev = PREV_INSN (insn);
1162 295366 : while (prev && !(INSN_P (prev)
1163 147675 : && BLOCK_FOR_INSN (prev) != bb))
1164 : {
1165 147691 : if (NONDEBUG_INSN_P (prev))
1166 : {
1167 147675 : rtx set = single_set (prev);
1168 :
1169 147675 : if (set && rtx_equal_p (SET_DEST (set), reg))
1170 : {
1171 147675 : rtx src = SET_SRC (set);
1172 115908 : if (!REG_P (src) || HARD_REGISTER_P (src)
1173 263171 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1174 : break;
1175 31882 : if (!modified_between_p (src, prev, insn))
1176 5963612 : cheap_reg = src;
1177 : break;
1178 : }
1179 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1180 : {
1181 0 : rtx dest = SET_DEST (set);
1182 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1183 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1184 : break;
1185 0 : if (!modified_between_p (dest, prev, insn))
1186 5963612 : cheap_reg = dest;
1187 : break;
1188 : }
1189 :
1190 0 : if (reg_set_p (reg, prev))
1191 : break;
1192 : }
1193 16 : prev = PREV_INSN (prev);
1194 : }
1195 : }
1196 5963612 : return cheap_reg;
1197 : }
1198 :
1199 : /* Determine whether INSN is a register to register copy of the type where
1200 : we do not need to make the source and destiniation registers conflict.
1201 : If this is a copy instruction, then return the source reg. Otherwise,
1202 : return NULL_RTX. */
1203 : rtx
1204 302689050 : non_conflicting_reg_copy_p (rtx_insn *insn)
1205 : {
1206 : /* Reload has issues with overlapping pseudos being assigned to the
1207 : same hard register, so don't allow it. See PR87600 for details. */
1208 302689050 : if (!targetm.lra_p ())
1209 : return NULL_RTX;
1210 :
1211 302689050 : rtx set = single_set (insn);
1212 :
1213 : /* Disallow anything other than a simple register to register copy
1214 : that has no side effects. */
1215 302689050 : if (set == NULL_RTX
1216 287734340 : || !REG_P (SET_DEST (set))
1217 211284490 : || !REG_P (SET_SRC (set))
1218 373589593 : || side_effects_p (set))
1219 231788507 : return NULL_RTX;
1220 :
1221 70900543 : int dst_regno = REGNO (SET_DEST (set));
1222 70900543 : int src_regno = REGNO (SET_SRC (set));
1223 70900543 : machine_mode mode = GET_MODE (SET_DEST (set));
1224 :
1225 : /* By definition, a register does not conflict with itself, therefore we
1226 : do not have to handle it specially. Returning NULL_RTX now, helps
1227 : simplify the callers of this function. */
1228 70900543 : if (dst_regno == src_regno)
1229 : return NULL_RTX;
1230 :
1231 : /* Computing conflicts for register pairs is difficult to get right, so
1232 : for now, disallow it. */
1233 70900543 : if ((HARD_REGISTER_NUM_P (dst_regno)
1234 19143970 : && hard_regno_nregs (dst_regno, mode) != 1)
1235 89879965 : || (HARD_REGISTER_NUM_P (src_regno)
1236 10353376 : && hard_regno_nregs (src_regno, mode) != 1))
1237 : return NULL_RTX;
1238 :
1239 : return SET_SRC (set);
1240 : }
1241 :
1242 : #ifdef EH_RETURN_DATA_REGNO
1243 :
1244 : /* Add EH return hard registers as conflict hard registers to allocnos
1245 : living at end of BB. For most allocnos it is already done in
1246 : process_bb_node_lives when we processing input edges but it does
1247 : not work when and EH edge is edge out of the current region. This
1248 : function covers such out of region edges. */
1249 : static void
1250 14292350 : process_out_of_region_eh_regs (basic_block bb)
1251 : {
1252 14292350 : edge e;
1253 14292350 : edge_iterator ei;
1254 14292350 : unsigned int i;
1255 14292350 : bitmap_iterator bi;
1256 14292350 : bool eh_p = false;
1257 :
1258 34702269 : FOR_EACH_EDGE (e, ei, bb->succs)
1259 20409919 : if ((e->flags & EDGE_EH)
1260 20409919 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1261 : eh_p = true;
1262 :
1263 14292350 : if (! eh_p)
1264 14285859 : return;
1265 :
1266 77345 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1267 : {
1268 70854 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1269 146558 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1270 : {
1271 75704 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1272 302816 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1273 75704 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1274 : }
1275 : }
1276 : }
1277 :
1278 : #endif
1279 :
1280 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1281 : static void
1282 3371463 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1283 : function_abi callee_abi)
1284 : {
1285 3371463 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1286 3371463 : rtx_code_label *landing_label;
1287 3371463 : basic_block landing_bb;
1288 :
1289 6619191 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1290 : {
1291 5562144 : if ((landing_label = lp->landing_pad) != NULL
1292 5562144 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1293 11124237 : && (region->type != ERT_CLEANUP
1294 4072077 : || bitmap_bit_p (df_get_live_in (landing_bb),
1295 : ALLOCNO_REGNO (a))))
1296 : {
1297 2314416 : HARD_REG_SET new_conflict_regs
1298 2314416 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1299 9257664 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1300 2314416 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1301 2314416 : return;
1302 : }
1303 : }
1304 : }
1305 :
1306 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1307 : update allocno live ranges, allocno hard register conflicts,
1308 : intersected calls, and register pressure info for allocnos for the
1309 : basic block for and regions containing the basic block. */
1310 : static void
1311 16391307 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1312 : {
1313 16391307 : int i, freq;
1314 16391307 : unsigned int j, k;
1315 16391307 : basic_block bb;
1316 16391307 : rtx_insn *insn;
1317 16391307 : bitmap_iterator bi;
1318 16391307 : bitmap reg_live_out;
1319 16391307 : unsigned int px;
1320 16391307 : bool set_p;
1321 :
1322 16391307 : bb = loop_tree_node->bb;
1323 16391307 : if (bb != NULL)
1324 : {
1325 70295672 : for (i = 0; i < ira_pressure_classes_num; i++)
1326 : {
1327 56003322 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1328 56003322 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1329 : }
1330 14292350 : curr_bb_node = loop_tree_node;
1331 14292350 : reg_live_out = df_get_live_out (bb);
1332 14292350 : sparseset_clear (objects_live);
1333 28584700 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1334 14292350 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1335 14292350 : hard_reg_set_iterator hrsi;
1336 14292350 : k = 0;
1337 15404905 : EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)
1338 : {
1339 1112555 : enum reg_class aclass, pclass, cl;
1340 :
1341 1112555 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];
1342 1112555 : pclass = ira_pressure_class_translate[aclass];
1343 10549225 : for (j = 0;
1344 10549225 : (cl = ira_reg_class_super_classes[pclass][j])
1345 10549225 : != LIM_REG_CLASSES;
1346 : j++)
1347 : {
1348 9436670 : if (! ira_reg_pressure_class_p[cl])
1349 8324115 : continue;
1350 1112555 : curr_reg_pressure[cl]++;
1351 1112555 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1352 1112555 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1353 1112555 : ira_assert (curr_reg_pressure[cl]
1354 : <= ira_class_hard_regs_num[cl]);
1355 : }
1356 : }
1357 153581954 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1358 139289604 : mark_pseudo_regno_live (j);
1359 :
1360 : #ifdef EH_RETURN_DATA_REGNO
1361 14292350 : process_out_of_region_eh_regs (bb);
1362 : #endif
1363 :
1364 14292350 : freq = REG_FREQ_FROM_BB (bb);
1365 8469093 : if (freq == 0)
1366 1983722 : freq = 1;
1367 :
1368 : /* Invalidate all allocno_saved_at_call entries. */
1369 14292350 : last_call_num++;
1370 :
1371 : /* Scan the code of this basic block, noting which allocnos and
1372 : hard regs are born or die.
1373 :
1374 : Note that this loop treats uninitialized values as live until
1375 : the beginning of the block. For example, if an instruction
1376 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1377 : set, FOO will remain live until the beginning of the block.
1378 : Likewise if FOO is not set at all. This is unnecessarily
1379 : pessimistic, but it probably doesn't matter much in practice. */
1380 171128432 : FOR_BB_INSNS_REVERSE (bb, insn)
1381 : {
1382 156836082 : ira_allocno_t a;
1383 156836082 : df_ref def, use;
1384 156836082 : bool call_p;
1385 :
1386 156836082 : if (!NONDEBUG_INSN_P (insn))
1387 73802209 : continue;
1388 :
1389 83033873 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1390 1479 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1391 1479 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1392 : curr_point);
1393 :
1394 83033873 : call_p = CALL_P (insn);
1395 83033873 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1396 :
1397 : /* Mark each defined value as live. We need to do this for
1398 : unused values because they still conflict with quantities
1399 : that are live at the time of the definition.
1400 :
1401 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1402 : references represent the effect of the called function
1403 : on a call-clobbered register. Marking the register as
1404 : live would stop us from allocating it to a call-crossing
1405 : allocno. */
1406 638855253 : FOR_EACH_INSN_DEF (def, insn)
1407 555821380 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1408 70388547 : mark_ref_live (def);
1409 :
1410 : /* If INSN has multiple outputs, then any value used in one
1411 : of the outputs conflicts with the other outputs. Model this
1412 : by making the used value live during the output phase.
1413 :
1414 : It is unsafe to use !single_set here since it will ignore
1415 : an unused output. Just because an output is unused does
1416 : not mean the compiler can assume the side effect will not
1417 : occur. Consider if ALLOCNO appears in the address of an
1418 : output and we reload the output. If we allocate ALLOCNO
1419 : to the same hard register as an unused output we could
1420 : set the hard register before the output reload insn. */
1421 83033873 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1422 1787509 : FOR_EACH_INSN_USE (use, insn)
1423 : {
1424 1404951 : int i;
1425 1404951 : rtx reg;
1426 :
1427 1404951 : reg = DF_REF_REG (use);
1428 4432947 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1429 : {
1430 3408383 : rtx set;
1431 :
1432 3408383 : set = XVECEXP (PATTERN (insn), 0, i);
1433 3408383 : if (GET_CODE (set) == SET
1434 3408383 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1435 : {
1436 : /* After the previous loop, this is a no-op if
1437 : REG is contained within SET_DEST (SET). */
1438 380387 : mark_ref_live (use);
1439 380387 : break;
1440 : }
1441 : }
1442 : }
1443 :
1444 83033873 : preferred_alternatives = ira_setup_alts (insn);
1445 83033873 : process_register_constraint_filters ();
1446 83033873 : process_single_reg_class_operands (false, freq);
1447 :
1448 83033873 : if (call_p)
1449 : {
1450 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1451 : there, try to find a pseudo that is live across the call but
1452 : can be cheaply reconstructed from the return value. */
1453 5963612 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1454 5963612 : if (cheap_reg != NULL_RTX)
1455 31882 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1456 :
1457 5963612 : last_call_num++;
1458 5963612 : sparseset_clear (allocnos_processed);
1459 : /* The current set of live allocnos are live across the call. */
1460 468432524 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1461 : {
1462 228252650 : ira_object_t obj = ira_object_id_map[i];
1463 228252650 : a = OBJECT_ALLOCNO (obj);
1464 228252650 : int num = ALLOCNO_NUM (a);
1465 228252650 : function_abi callee_abi = insn_callee_abi (insn);
1466 :
1467 : /* Don't allocate allocnos that cross setjmps or any
1468 : call, if this function receives a nonlocal
1469 : goto. */
1470 228252650 : if (cfun->has_nonlocal_label
1471 228252650 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1472 228250081 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1473 : != NULL_RTX)))
1474 : {
1475 10929 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1476 228252650 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1477 : }
1478 228252650 : eh_region r;
1479 228252650 : if (can_throw_internal (insn)
1480 228252650 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1481 3371463 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1482 228252650 : if (sparseset_bit_p (allocnos_processed, num))
1483 104000869 : continue;
1484 124251781 : sparseset_set_bit (allocnos_processed, num);
1485 :
1486 124251781 : if (allocno_saved_at_call[num] != last_call_num)
1487 : /* Here we are mimicking caller-save.cc behavior
1488 : which does not save hard register at a call if
1489 : it was saved on previous call in the same basic
1490 : block and the hard register was not mentioned
1491 : between the two calls. */
1492 39503892 : ALLOCNO_CALL_FREQ (a) += freq;
1493 : /* Mark it as saved at the next call. */
1494 124251781 : allocno_saved_at_call[num] = last_call_num + 1;
1495 124251781 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1496 124251781 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1497 124251781 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1498 124251781 : |= callee_abi.full_and_partial_reg_clobbers ();
1499 124251781 : if (cheap_reg != NULL_RTX
1500 124251781 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1501 31882 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1502 : }
1503 : }
1504 :
1505 : /* See which defined values die here. Note that we include
1506 : the call insn in the lifetimes of these values, so we don't
1507 : mistakenly consider, for e.g. an addressing mode with a
1508 : side-effect like a post-increment fetching the address,
1509 : that the use happens before the call, and the def to happen
1510 : after the call: we believe both to happen before the actual
1511 : call. (We don't handle return-values here.) */
1512 638855253 : FOR_EACH_INSN_DEF (def, insn)
1513 555821380 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1514 70388547 : mark_ref_dead (def);
1515 :
1516 83033873 : make_early_clobber_and_input_conflicts ();
1517 :
1518 83033873 : curr_point++;
1519 :
1520 : /* Mark each used value as live. */
1521 183271932 : FOR_EACH_INSN_USE (use, insn)
1522 100238059 : mark_ref_live (use);
1523 :
1524 83033873 : process_single_reg_class_operands (true, freq);
1525 :
1526 83033873 : set_p = mark_hard_reg_early_clobbers (insn, true);
1527 :
1528 83033873 : if (set_p)
1529 : {
1530 10585150 : mark_hard_reg_early_clobbers (insn, false);
1531 :
1532 : /* Mark each hard reg as live again. For example, a
1533 : hard register can be in clobber and in an insn
1534 : input. */
1535 26190350 : FOR_EACH_INSN_USE (use, insn)
1536 : {
1537 15605200 : rtx ureg = DF_REF_REG (use);
1538 :
1539 15605200 : if (GET_CODE (ureg) == SUBREG)
1540 305098 : ureg = SUBREG_REG (ureg);
1541 15605200 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1542 9667648 : continue;
1543 :
1544 5937552 : mark_ref_live (use);
1545 : }
1546 : }
1547 :
1548 83033873 : curr_point++;
1549 : }
1550 14292350 : ignore_reg_for_conflicts = NULL_RTX;
1551 :
1552 14292350 : if (bb_has_eh_pred (bb))
1553 207755 : for (j = 0; ; ++j)
1554 : {
1555 623265 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1556 415510 : if (regno == INVALID_REGNUM)
1557 : break;
1558 415510 : make_hard_regno_live (regno);
1559 415510 : }
1560 :
1561 : /* Allocnos can't go in stack regs at the start of a basic block
1562 : that is reached by an abnormal edge. Likewise for registers
1563 : that are at least partly call clobbered, because caller-save,
1564 : fixup_abnormal_edges and possibly the table driven EH machinery
1565 : are not quite ready to handle such allocnos live across such
1566 : edges. */
1567 14292350 : if (bb_has_abnormal_pred (bb))
1568 : {
1569 : #ifdef STACK_REGS
1570 647716 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1571 : {
1572 437520 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1573 :
1574 437520 : ALLOCNO_NO_STACK_REG_P (a) = true;
1575 437520 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1576 : }
1577 1891764 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1578 1681568 : make_hard_regno_live (px);
1579 : #endif
1580 : /* No need to record conflicts for call clobbered regs if we
1581 : have nonlocal labels around, as we don't ever try to
1582 : allocate such regs in this case. */
1583 210196 : if (!cfun->has_nonlocal_label
1584 210196 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1585 19320378 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1586 19112632 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1587 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1588 : /* We should create a conflict of PIC pseudo with
1589 : PIC hard reg as PIC hard reg can have a wrong
1590 : value after jump described by the abnormal edge.
1591 : In this case we cannot allocate PIC hard reg to
1592 : PIC pseudo as PIC pseudo will also have a wrong
1593 : value. This code is not critical as LRA can fix
1594 : it but it is better to have the right allocation
1595 : earlier. */
1596 19251939 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1597 207746 : && pic_offset_table_rtx != NULL_RTX
1598 6297 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1599 : #endif
1600 : )
1601 17289017 : make_hard_regno_live (px);
1602 : }
1603 :
1604 218094994 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1605 203802644 : make_object_dead (ira_object_id_map[i]);
1606 :
1607 14292350 : curr_point++;
1608 :
1609 : }
1610 : /* Propagate register pressure to upper loop tree nodes. */
1611 16391307 : if (loop_tree_node != ira_loop_tree_root)
1612 73356888 : for (i = 0; i < ira_pressure_classes_num; i++)
1613 : {
1614 58453951 : enum reg_class pclass;
1615 :
1616 58453951 : pclass = ira_pressure_classes[i];
1617 58453951 : if (loop_tree_node->reg_pressure[pclass]
1618 58453951 : > loop_tree_node->parent->reg_pressure[pclass])
1619 4218287 : loop_tree_node->parent->reg_pressure[pclass]
1620 4218287 : = loop_tree_node->reg_pressure[pclass];
1621 : }
1622 16391307 : }
1623 :
1624 : /* Create and set up IRA_START_POINT_RANGES and
1625 : IRA_FINISH_POINT_RANGES. */
1626 : static void
1627 3135917 : create_start_finish_chains (void)
1628 : {
1629 3135917 : ira_object_t obj;
1630 3135917 : ira_object_iterator oi;
1631 3135917 : live_range_t r;
1632 :
1633 3135917 : ira_start_point_ranges
1634 3135917 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1635 3135917 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1636 3135917 : ira_finish_point_ranges
1637 3135917 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1638 3135917 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1639 80279039 : FOR_EACH_OBJECT (obj, oi)
1640 182386146 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1641 : {
1642 105243024 : r->start_next = ira_start_point_ranges[r->start];
1643 105243024 : ira_start_point_ranges[r->start] = r;
1644 105243024 : r->finish_next = ira_finish_point_ranges[r->finish];
1645 105243024 : ira_finish_point_ranges[r->finish] = r;
1646 : }
1647 3135917 : }
1648 :
1649 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1650 : new live ranges and program points were added as a result if new
1651 : insn generation. */
1652 : void
1653 1647547 : ira_rebuild_start_finish_chains (void)
1654 : {
1655 1647547 : ira_free (ira_finish_point_ranges);
1656 1647547 : ira_free (ira_start_point_ranges);
1657 1647547 : create_start_finish_chains ();
1658 1647547 : }
1659 :
1660 : /* Compress allocno live ranges by removing program points where
1661 : nothing happens. */
1662 : static void
1663 1488370 : remove_some_program_points_and_update_live_ranges (void)
1664 : {
1665 1488370 : unsigned i;
1666 1488370 : int n;
1667 1488370 : int *map;
1668 1488370 : ira_object_t obj;
1669 1488370 : ira_object_iterator oi;
1670 1488370 : live_range_t r, prev_r, next_r;
1671 1488370 : sbitmap_iterator sbi;
1672 1488370 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1673 :
1674 1488370 : auto_sbitmap born (ira_max_point);
1675 1488370 : auto_sbitmap dead (ira_max_point);
1676 1488370 : bitmap_clear (born);
1677 1488370 : bitmap_clear (dead);
1678 35598371 : FOR_EACH_OBJECT (obj, oi)
1679 87332014 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1680 : {
1681 53222013 : ira_assert (r->start <= r->finish);
1682 53222013 : bitmap_set_bit (born, r->start);
1683 53222013 : bitmap_set_bit (dead, r->finish);
1684 : }
1685 :
1686 1488370 : auto_sbitmap born_or_dead (ira_max_point);
1687 1488370 : bitmap_ior (born_or_dead, born, dead);
1688 1488370 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1689 1488370 : n = -1;
1690 1488370 : prev_born_p = prev_dead_p = false;
1691 66368228 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1692 : {
1693 63391488 : born_p = bitmap_bit_p (born, i);
1694 63391488 : dead_p = bitmap_bit_p (dead, i);
1695 63391488 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1696 57346816 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1697 15934441 : map[i] = n;
1698 : else
1699 47457047 : map[i] = ++n;
1700 63391488 : prev_born_p = born_p;
1701 63391488 : prev_dead_p = dead_p;
1702 : }
1703 :
1704 1488370 : n++;
1705 1488370 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1706 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1707 95 : ira_max_point, n, 100 * n / ira_max_point);
1708 1488370 : ira_max_point = n;
1709 :
1710 35598371 : FOR_EACH_OBJECT (obj, oi)
1711 87332014 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1712 : {
1713 53222013 : next_r = r->next;
1714 53222013 : r->start = map[r->start];
1715 53222013 : r->finish = map[r->finish];
1716 53222013 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1717 : {
1718 40678506 : prev_r = r;
1719 40678506 : continue;
1720 : }
1721 12543507 : prev_r->start = r->start;
1722 12543507 : prev_r->next = next_r;
1723 12543507 : ira_finish_live_range (r);
1724 : }
1725 :
1726 1488370 : ira_free (map);
1727 1488370 : }
1728 :
1729 : /* Print live ranges R to file F. */
1730 : void
1731 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1732 : {
1733 3234 : for (; r != NULL; r = r->next)
1734 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1735 1466 : fprintf (f, "\n");
1736 1466 : }
1737 :
1738 : DEBUG_FUNCTION void
1739 0 : debug (live_range &ref)
1740 : {
1741 0 : ira_print_live_range_list (stderr, &ref);
1742 0 : }
1743 :
1744 : DEBUG_FUNCTION void
1745 0 : debug (live_range *ptr)
1746 : {
1747 0 : if (ptr)
1748 0 : debug (*ptr);
1749 : else
1750 0 : fprintf (stderr, "<nil>\n");
1751 0 : }
1752 :
1753 : /* Print live ranges R to stderr. */
1754 : void
1755 0 : ira_debug_live_range_list (live_range_t r)
1756 : {
1757 0 : ira_print_live_range_list (stderr, r);
1758 0 : }
1759 :
1760 : /* Print live ranges of object OBJ to file F. */
1761 : static void
1762 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1763 : {
1764 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1765 0 : }
1766 :
1767 : /* Print live ranges of allocno A to file F. */
1768 : static void
1769 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1770 : {
1771 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1772 1328 : int i;
1773 :
1774 2656 : for (i = 0; i < n; i++)
1775 : {
1776 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1777 1328 : if (n > 1)
1778 0 : fprintf (f, " [%d]", i);
1779 1328 : fprintf (f, "):");
1780 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1781 : }
1782 1328 : }
1783 :
1784 : /* Print live ranges of allocno A to stderr. */
1785 : void
1786 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1787 : {
1788 0 : print_allocno_live_ranges (stderr, a);
1789 0 : }
1790 :
1791 : /* Print live ranges of all allocnos to file F. */
1792 : static void
1793 190 : print_live_ranges (FILE *f)
1794 : {
1795 190 : ira_allocno_t a;
1796 190 : ira_allocno_iterator ai;
1797 :
1798 1518 : FOR_EACH_ALLOCNO (a, ai)
1799 1328 : print_allocno_live_ranges (f, a);
1800 190 : }
1801 :
1802 : /* Print live ranges of all allocnos to stderr. */
1803 : void
1804 0 : ira_debug_live_ranges (void)
1805 : {
1806 0 : print_live_ranges (stderr);
1807 0 : }
1808 :
1809 : /* The main entry function creates live ranges, set up
1810 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1811 : calculate register pressure info. */
1812 : void
1813 1488370 : ira_create_allocno_live_ranges (void)
1814 : {
1815 1488370 : objects_live = sparseset_alloc (ira_objects_num);
1816 1488370 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1817 1488370 : curr_point = 0;
1818 1488370 : last_call_num = 0;
1819 1488370 : allocno_saved_at_call
1820 1488370 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1821 1488370 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1822 1488370 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1823 : process_bb_node_lives);
1824 1488370 : ira_max_point = curr_point;
1825 1488370 : create_start_finish_chains ();
1826 1488370 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1827 95 : print_live_ranges (ira_dump_file);
1828 : /* Clean up. */
1829 1488370 : ira_free (allocno_saved_at_call);
1830 1488370 : sparseset_free (objects_live);
1831 1488370 : sparseset_free (allocnos_processed);
1832 1488370 : }
1833 :
1834 : /* Compress allocno live ranges. */
1835 : void
1836 1488370 : ira_compress_allocno_live_ranges (void)
1837 : {
1838 1488370 : remove_some_program_points_and_update_live_ranges ();
1839 1488370 : ira_rebuild_start_finish_chains ();
1840 1488370 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1841 : {
1842 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1843 95 : print_live_ranges (ira_dump_file);
1844 : }
1845 1488370 : }
1846 :
1847 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1848 : void
1849 1488370 : ira_finish_allocno_live_ranges (void)
1850 : {
1851 1488370 : ira_free (ira_finish_point_ranges);
1852 1488370 : ira_free (ira_start_point_ranges);
1853 1488370 : }
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