Line data Source code
1 : /* IRA processing allocno lives to build allocno live ranges.
2 : Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #include "config.h"
22 : #include "system.h"
23 : #include "coretypes.h"
24 : #include "backend.h"
25 : #include "target.h"
26 : #include "rtl.h"
27 : #include "stmt.h"
28 : #include "predict.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "insn-config.h"
33 : #include "regs.h"
34 : #include "ira.h"
35 : #include "ira-int.h"
36 : #include "sparseset.h"
37 : #include "function-abi.h"
38 : #include "except.h"
39 :
40 : /* The code in this file is similar to one in global but the code
41 : works on the allocno basis and creates live ranges instead of
42 : pseudo-register conflicts. */
43 :
44 : /* Program points are enumerated by numbers from range
45 : 0..IRA_MAX_POINT-1. There are approximately two times more program
46 : points than insns. Program points are places in the program where
47 : liveness info can be changed. In most general case (there are more
48 : complicated cases too) some program points correspond to places
49 : where input operand dies and other ones correspond to places where
50 : output operands are born. */
51 : int ira_max_point;
52 :
53 : /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
54 : live ranges with given start/finish point. */
55 : live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
56 :
57 : /* Number of the current program point. */
58 : static int curr_point;
59 :
60 : /* Point where register pressure excess started or -1 if there is no
61 : register pressure excess. Excess pressure for a register class at
62 : some point means that there are more allocnos of given register
63 : class living at the point than number of hard-registers of the
64 : class available for the allocation. It is defined only for
65 : pressure classes. */
66 : static int high_pressure_start_point[N_REG_CLASSES];
67 :
68 : /* Objects live at current point in the scan. */
69 : static sparseset objects_live;
70 :
71 : /* A temporary bitmap used in functions that wish to avoid visiting an allocno
72 : multiple times. */
73 : static sparseset allocnos_processed;
74 :
75 : /* Set of hard regs (except eliminable ones) currently live. */
76 : static HARD_REG_SET hard_regs_live;
77 :
78 : /* The loop tree node corresponding to the current basic block. */
79 : static ira_loop_tree_node_t curr_bb_node;
80 :
81 : /* The number of the last processed call. */
82 : static int last_call_num;
83 : /* The number of last call at which given allocno was saved. */
84 : static int *allocno_saved_at_call;
85 :
86 : /* The value returned by ira_setup_alts for the current instruction;
87 : i.e. the set of alternatives that we should consider to be likely
88 : candidates during reloading. */
89 : static alternative_mask preferred_alternatives;
90 :
91 : /* If non-NULL, the source operand of a register to register copy for which
92 : we should not add a conflict with the copy's destination operand. */
93 : static rtx ignore_reg_for_conflicts;
94 :
95 : /* Record hard register REGNO as now being live. */
96 : static void
97 38351151 : make_hard_regno_live (int regno)
98 : {
99 38351151 : SET_HARD_REG_BIT (hard_regs_live, regno);
100 0 : }
101 :
102 : /* Process the definition of hard register REGNO. This updates
103 : hard_regs_live and hard reg conflict information for living allocnos. */
104 : static void
105 15216316 : make_hard_regno_dead (int regno)
106 : {
107 15216316 : unsigned int i;
108 281138129 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
109 : {
110 265921813 : ira_object_t obj = ira_object_id_map[i];
111 :
112 267642226 : if (ignore_reg_for_conflicts != NULL_RTX
113 174697265 : && REGNO (ignore_reg_for_conflicts)
114 174697265 : == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj)))
115 1720413 : continue;
116 :
117 264201400 : SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
118 264201400 : SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
119 : }
120 15216316 : CLEAR_HARD_REG_BIT (hard_regs_live, regno);
121 15216316 : }
122 :
123 : /* Record object OBJ as now being live. Set a bit for it in objects_live,
124 : and start a new live range for it if necessary. */
125 : static void
126 244675260 : make_object_live (ira_object_t obj)
127 : {
128 244675260 : sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj));
129 :
130 244675260 : live_range_t lr = OBJECT_LIVE_RANGES (obj);
131 244675260 : if (lr == NULL
132 207295170 : || (lr->finish != curr_point && lr->finish + 1 != curr_point))
133 55363346 : ira_add_live_range_to_object (obj, curr_point, -1);
134 244675260 : }
135 :
136 : /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
137 : associated with object OBJ. */
138 : static void
139 252281968 : update_allocno_pressure_excess_length (ira_object_t obj)
140 : {
141 252281968 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
142 252281968 : int start, i;
143 252281968 : enum reg_class aclass, pclass, cl;
144 252281968 : live_range_t p;
145 :
146 252281968 : aclass = ALLOCNO_CLASS (a);
147 252281968 : pclass = ira_pressure_class_translate[aclass];
148 2476593615 : for (i = 0;
149 2476593615 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
150 : i++)
151 : {
152 2224311647 : if (! ira_reg_pressure_class_p[cl])
153 1977100601 : continue;
154 247211046 : if (high_pressure_start_point[cl] < 0)
155 75253972 : continue;
156 171957074 : p = OBJECT_LIVE_RANGES (obj);
157 171957074 : ira_assert (p != NULL);
158 171957074 : start = (high_pressure_start_point[cl] > p->start
159 171957074 : ? high_pressure_start_point[cl] : p->start);
160 171957074 : ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a) += curr_point - start + 1;
161 : }
162 252281968 : }
163 :
164 : /* Process the definition of object OBJ, which is associated with allocno A.
165 : This finishes the current live range for it. */
166 : static void
167 244675260 : make_object_dead (ira_object_t obj)
168 : {
169 244675260 : live_range_t lr;
170 244675260 : int regno;
171 244675260 : int ignore_regno = -1;
172 244675260 : int ignore_total_regno = -1;
173 244675260 : int end_regno = -1;
174 :
175 244675260 : sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj));
176 :
177 : /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
178 : with OBJ. */
179 244675260 : if (ignore_reg_for_conflicts != NULL_RTX
180 244675260 : && REGNO (ignore_reg_for_conflicts) < FIRST_PSEUDO_REGISTER)
181 : {
182 3478381 : end_regno = END_REGNO (ignore_reg_for_conflicts);
183 3478381 : ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts);
184 :
185 6956762 : for (regno = ignore_regno; regno < end_regno; regno++)
186 : {
187 3478381 : if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno))
188 525503 : ignore_regno = end_regno;
189 3478381 : if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno))
190 525503 : ignore_total_regno = end_regno;
191 : }
192 : }
193 :
194 978701040 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
195 247628138 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs_live;
196 :
197 : /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
198 : sure it still doesn't. */
199 247628138 : for (regno = ignore_regno; regno < end_regno; regno++)
200 2952878 : CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), regno);
201 247628138 : for (regno = ignore_total_regno; regno < end_regno; regno++)
202 2952878 : CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno);
203 :
204 244675260 : lr = OBJECT_LIVE_RANGES (obj);
205 244675260 : ira_assert (lr != NULL);
206 244675260 : lr->finish = curr_point;
207 244675260 : update_allocno_pressure_excess_length (obj);
208 244675260 : }
209 :
210 : /* The current register pressures for each pressure class for the current
211 : basic block. */
212 : static int curr_reg_pressure[N_REG_CLASSES];
213 :
214 : /* Record that register pressure for PCLASS increased by N registers.
215 : Update the current register pressure, maximal register pressure for
216 : the current BB and the start point of the register pressure
217 : excess. */
218 : static void
219 261488141 : inc_register_pressure (enum reg_class pclass, int n)
220 : {
221 261488141 : int i;
222 261488141 : enum reg_class cl;
223 :
224 2566072465 : for (i = 0;
225 2566072465 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
226 : i++)
227 : {
228 2304584324 : if (! ira_reg_pressure_class_p[cl])
229 2047895171 : continue;
230 256689153 : curr_reg_pressure[cl] += n;
231 256689153 : if (high_pressure_start_point[cl] < 0
232 107056045 : && (curr_reg_pressure[cl] > ira_class_hard_regs_num[cl]))
233 1801573 : high_pressure_start_point[cl] = curr_point;
234 256689153 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
235 221469785 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
236 : }
237 261488141 : }
238 :
239 : /* Record that register pressure for PCLASS has decreased by NREGS
240 : registers; update current register pressure, start point of the
241 : register pressure excess, and register pressure excess length for
242 : living allocnos. */
243 :
244 : static void
245 53263223 : dec_register_pressure (enum reg_class pclass, int nregs)
246 : {
247 53263223 : int i;
248 53263223 : unsigned int j;
249 53263223 : enum reg_class cl;
250 53263223 : bool set_p = false;
251 :
252 53263223 : for (i = 0;
253 516901170 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
254 : i++)
255 : {
256 463637947 : if (! ira_reg_pressure_class_p[cl])
257 410883732 : continue;
258 52754215 : curr_reg_pressure[cl] -= nregs;
259 52754215 : ira_assert (curr_reg_pressure[cl] >= 0);
260 52754215 : if (high_pressure_start_point[cl] >= 0
261 4806201 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
262 463637947 : set_p = true;
263 : }
264 53263223 : if (set_p)
265 : {
266 8099531 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)
267 7606708 : update_allocno_pressure_excess_length (ira_object_id_map[j]);
268 4684333 : for (i = 0;
269 5177156 : (cl = ira_reg_class_super_classes[pclass][i]) != LIM_REG_CLASSES;
270 : i++)
271 : {
272 4684333 : if (! ira_reg_pressure_class_p[cl])
273 4191510 : continue;
274 492823 : if (high_pressure_start_point[cl] >= 0
275 492823 : && curr_reg_pressure[cl] <= ira_class_hard_regs_num[cl])
276 492823 : high_pressure_start_point[cl] = -1;
277 : }
278 : }
279 53263223 : }
280 :
281 : /* Determine from the objects_live bitmap whether REGNO is currently live,
282 : and occupies only one object. Return false if we have no information. */
283 : static bool
284 122914 : pseudo_regno_single_word_and_live_p (int regno)
285 : {
286 122914 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
287 122914 : ira_object_t obj;
288 :
289 122914 : if (a == NULL)
290 : return false;
291 122914 : if (ALLOCNO_NUM_OBJECTS (a) > 1)
292 : return false;
293 :
294 122914 : obj = ALLOCNO_OBJECT (a, 0);
295 :
296 122914 : return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj));
297 : }
298 :
299 : /* Mark the pseudo register REGNO as live. Update all information about
300 : live ranges and register pressure. */
301 : static void
302 230103371 : mark_pseudo_regno_live (int regno)
303 : {
304 230103371 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
305 230103371 : enum reg_class pclass;
306 230103371 : int i, n, nregs;
307 :
308 230103371 : if (a == NULL)
309 : return;
310 :
311 : /* Invalidate because it is referenced. */
312 230103371 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
313 :
314 230103371 : n = ALLOCNO_NUM_OBJECTS (a);
315 230103371 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
316 230103371 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
317 230103371 : if (n > 1)
318 : {
319 : /* We track every subobject separately. */
320 69919229 : gcc_assert (nregs == n);
321 : nregs = 1;
322 : }
323 :
324 530125971 : for (i = 0; i < n; i++)
325 : {
326 300022600 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
327 :
328 300022600 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
329 55672678 : continue;
330 :
331 244349922 : inc_register_pressure (pclass, nregs);
332 244349922 : make_object_live (obj);
333 : }
334 : }
335 :
336 : /* Like mark_pseudo_regno_live, but try to only mark one subword of
337 : the pseudo as live. SUBWORD indicates which; a value of 0
338 : indicates the low part. */
339 : static void
340 860717 : mark_pseudo_regno_subword_live (int regno, int subword)
341 : {
342 860717 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
343 860717 : int n;
344 860717 : enum reg_class pclass;
345 860717 : ira_object_t obj;
346 :
347 860717 : if (a == NULL)
348 : return;
349 :
350 : /* Invalidate because it is referenced. */
351 860717 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
352 :
353 860717 : n = ALLOCNO_NUM_OBJECTS (a);
354 860717 : if (n == 1)
355 : {
356 40801 : mark_pseudo_regno_live (regno);
357 40801 : return;
358 : }
359 :
360 819916 : pclass = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
361 819916 : gcc_assert
362 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
363 819916 : obj = ALLOCNO_OBJECT (a, subword);
364 :
365 819916 : if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
366 : return;
367 :
368 325338 : inc_register_pressure (pclass, 1);
369 325338 : make_object_live (obj);
370 : }
371 :
372 : /* Mark the register REG as live. Store a 1 in hard_regs_live for
373 : this register, record how many consecutive hardware registers it
374 : actually needs. */
375 : static void
376 104304275 : mark_hard_reg_live (rtx reg)
377 : {
378 104304275 : int regno = REGNO (reg);
379 :
380 104304275 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
381 : {
382 31764963 : int last = END_REGNO (reg);
383 31764963 : enum reg_class aclass, pclass;
384 :
385 63529926 : while (regno < last)
386 : {
387 31764963 : if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
388 31764963 : && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
389 : {
390 16812881 : aclass = ira_hard_regno_allocno_class[regno];
391 16812881 : pclass = ira_pressure_class_translate[aclass];
392 16812881 : inc_register_pressure (pclass, 1);
393 16812881 : make_hard_regno_live (regno);
394 : }
395 31764963 : regno++;
396 : }
397 : }
398 104304275 : }
399 :
400 : /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
401 : register number; ORIG_REG is the access in the insn, which may be a
402 : subreg. */
403 : static void
404 88728813 : mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
405 : {
406 88728813 : if (read_modify_subreg_p (orig_reg))
407 : {
408 1283698 : mark_pseudo_regno_subword_live (regno,
409 860717 : subreg_lowpart_p (orig_reg) ? 0 : 1);
410 : }
411 : else
412 87868096 : mark_pseudo_regno_live (regno);
413 88728813 : }
414 :
415 : /* Mark the register referenced by use or def REF as live. */
416 : static void
417 191170426 : mark_ref_live (df_ref ref)
418 : {
419 191170426 : rtx reg = DF_REF_REG (ref);
420 191170426 : rtx orig_reg = reg;
421 :
422 191170426 : if (GET_CODE (reg) == SUBREG)
423 3086856 : reg = SUBREG_REG (reg);
424 :
425 191170426 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
426 86866151 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
427 : else
428 104304275 : mark_hard_reg_live (reg);
429 191170426 : }
430 :
431 : /* Mark the pseudo register REGNO as dead. Update all information about
432 : live ranges and register pressure. */
433 : static void
434 36404451 : mark_pseudo_regno_dead (int regno)
435 : {
436 36404451 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
437 36404451 : int n, i, nregs;
438 36404451 : enum reg_class cl;
439 :
440 36404451 : if (a == NULL)
441 : return;
442 :
443 : /* Invalidate because it is referenced. */
444 36404451 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
445 :
446 36404451 : n = ALLOCNO_NUM_OBJECTS (a);
447 36404451 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
448 36404451 : nregs = ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)];
449 36404451 : if (n > 1)
450 : {
451 : /* We track every subobject separately. */
452 1307480 : gcc_assert (nregs == n);
453 : nregs = 1;
454 : }
455 74116382 : for (i = 0; i < n; i++)
456 : {
457 37711931 : ira_object_t obj = ALLOCNO_OBJECT (a, i);
458 37711931 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
459 3609 : continue;
460 :
461 37708322 : dec_register_pressure (cl, nregs);
462 37708322 : make_object_dead (obj);
463 : }
464 : }
465 :
466 : /* Like mark_pseudo_regno_dead, but called when we know that only part of the
467 : register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
468 : static void
469 343293 : mark_pseudo_regno_subword_dead (int regno, int subword)
470 : {
471 343293 : ira_allocno_t a = ira_curr_regno_allocno_map[regno];
472 343293 : int n;
473 343293 : enum reg_class cl;
474 343293 : ira_object_t obj;
475 :
476 343293 : if (a == NULL)
477 : return;
478 :
479 : /* Invalidate because it is referenced. */
480 343293 : allocno_saved_at_call[ALLOCNO_NUM (a)] = 0;
481 :
482 343293 : n = ALLOCNO_NUM_OBJECTS (a);
483 343293 : if (n == 1)
484 : /* The allocno as a whole doesn't die in this case. */
485 : return;
486 :
487 338585 : cl = ira_pressure_class_translate[ALLOCNO_CLASS (a)];
488 338585 : gcc_assert
489 : (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
490 :
491 338585 : obj = ALLOCNO_OBJECT (a, subword);
492 338585 : if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)))
493 : return;
494 :
495 338585 : dec_register_pressure (cl, 1);
496 338585 : make_object_dead (obj);
497 : }
498 :
499 : /* Process the definition of hard register REG. This updates hard_regs_live
500 : and hard reg conflict information for living allocnos. */
501 : static void
502 47469327 : mark_hard_reg_dead (rtx reg)
503 : {
504 47469327 : int regno = REGNO (reg);
505 :
506 47469327 : if (! TEST_HARD_REG_BIT (ira_no_alloc_regs, regno))
507 : {
508 15218334 : int last = END_REGNO (reg);
509 15218334 : enum reg_class aclass, pclass;
510 :
511 30436668 : while (regno < last)
512 : {
513 15218334 : if (TEST_HARD_REG_BIT (hard_regs_live, regno))
514 : {
515 15216316 : aclass = ira_hard_regno_allocno_class[regno];
516 15216316 : pclass = ira_pressure_class_translate[aclass];
517 15216316 : dec_register_pressure (pclass, 1);
518 15216316 : make_hard_regno_dead (regno);
519 : }
520 15218334 : regno++;
521 : }
522 : }
523 47469327 : }
524 :
525 : /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
526 : register number; ORIG_REG is the access in the insn, which may be a
527 : subreg. */
528 : static void
529 36747744 : mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
530 : {
531 36747744 : if (read_modify_subreg_p (orig_reg))
532 : {
533 516498 : mark_pseudo_regno_subword_dead (regno,
534 343293 : subreg_lowpart_p (orig_reg) ? 0 : 1);
535 : }
536 : else
537 36404451 : mark_pseudo_regno_dead (regno);
538 36747744 : }
539 :
540 : /* Mark the register referenced by definition DEF as dead, if the
541 : definition is a total one. */
542 : static void
543 82358675 : mark_ref_dead (df_ref def)
544 : {
545 82358675 : rtx reg = DF_REF_REG (def);
546 82358675 : rtx orig_reg = reg;
547 :
548 82358675 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
549 : return;
550 :
551 82358675 : if (GET_CODE (reg) == SUBREG)
552 927646 : reg = SUBREG_REG (reg);
553 :
554 82358675 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
555 82358675 : && (GET_CODE (orig_reg) != SUBREG
556 331852 : || REGNO (reg) < FIRST_PSEUDO_REGISTER
557 331852 : || !read_modify_subreg_p (orig_reg)))
558 : return;
559 :
560 82354409 : if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
561 34885082 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
562 : else
563 47469327 : mark_hard_reg_dead (reg);
564 : }
565 :
566 : /* If REG is a pseudo or a subreg of it, and the class of its allocno
567 : intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
568 : rtx actually accessed, it may be identical to DREG or a subreg of it.
569 : Advance the current program point before making the conflict if
570 : ADVANCE_P. Return TRUE if we will need to advance the current
571 : program point. */
572 : static bool
573 2957604 : make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
574 : bool advance_p)
575 : {
576 2957604 : rtx orig_reg = reg;
577 2957604 : ira_allocno_t a;
578 :
579 2957604 : if (GET_CODE (reg) == SUBREG)
580 85345 : reg = SUBREG_REG (reg);
581 :
582 2957604 : if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
583 : return advance_p;
584 :
585 1008366 : a = ira_curr_regno_allocno_map[REGNO (reg)];
586 1008366 : if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)))
587 : return advance_p;
588 :
589 931331 : if (advance_p)
590 886513 : curr_point++;
591 :
592 931331 : mark_pseudo_reg_live (orig_reg, REGNO (reg));
593 931331 : mark_pseudo_reg_live (orig_dreg, REGNO (dreg));
594 931331 : mark_pseudo_reg_dead (orig_reg, REGNO (reg));
595 931331 : mark_pseudo_reg_dead (orig_dreg, REGNO (dreg));
596 :
597 931331 : return false;
598 : }
599 :
600 : /* Check and make if necessary conflicts for pseudo DREG of class
601 : DEF_CL of the current insn with input operand USE of class USE_CL.
602 : ORIG_DREG is the rtx actually accessed, it may be identical to
603 : DREG or a subreg of it. Advance the current program point before
604 : making the conflict if ADVANCE_P. Return TRUE if we will need to
605 : advance the current program point. */
606 : static bool
607 3006783 : check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
608 : enum reg_class def_cl, int use,
609 : enum reg_class use_cl, bool advance_p)
610 : {
611 3006783 : if (! reg_classes_intersect_p (def_cl, use_cl))
612 : return advance_p;
613 :
614 2942091 : advance_p = make_pseudo_conflict (recog_data.operand[use],
615 : use_cl, dreg, orig_dreg, advance_p);
616 :
617 : /* Reload may end up swapping commutative operands, so you
618 : have to take both orderings into account. The
619 : constraints for the two operands can be completely
620 : different. (Indeed, if the constraints for the two
621 : operands are the same for all alternatives, there's no
622 : point marking them as commutative.) */
623 2942091 : if (use < recog_data.n_operands - 1
624 1176796 : && recog_data.constraints[use][0] == '%')
625 6464 : advance_p
626 6464 : = make_pseudo_conflict (recog_data.operand[use + 1],
627 : use_cl, dreg, orig_dreg, advance_p);
628 2942091 : if (use >= 1
629 2941791 : && recog_data.constraints[use - 1][0] == '%')
630 9049 : advance_p
631 9049 : = make_pseudo_conflict (recog_data.operand[use - 1],
632 : use_cl, dreg, orig_dreg, advance_p);
633 : return advance_p;
634 : }
635 :
636 : /* Check and make if necessary conflicts for definition DEF of class
637 : DEF_CL of the current insn with input operands. Process only
638 : constraints of alternative ALT.
639 :
640 : One of three things is true when this function is called:
641 :
642 : (1) DEF is an earlyclobber for alternative ALT. Input operands then
643 : conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 : constraints.
645 :
646 : (2) DEF matches (via 0-9 constraints) an operand that is an
647 : earlyclobber for alternative ALT. Other input operands then
648 : conflict with DEF in ALT.
649 :
650 : (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
651 : Input operands with a different value from X then conflict with
652 : DEF in ALT.
653 :
654 : However, there's still a judgement call to make when deciding
655 : whether a conflict in ALT is important enough to be reflected
656 : in the pan-alternative allocno conflict set. */
657 : static void
658 14632808 : check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
659 : bool for_tie_p)
660 : {
661 14632808 : int use, use_match;
662 14632808 : ira_allocno_t a;
663 14632808 : enum reg_class use_cl, acl;
664 14632808 : bool advance_p;
665 14632808 : rtx dreg = recog_data.operand[def];
666 14632808 : rtx orig_dreg = dreg;
667 :
668 14632808 : if (def_cl == NO_REGS)
669 : return;
670 :
671 14632808 : if (GET_CODE (dreg) == SUBREG)
672 112255 : dreg = SUBREG_REG (dreg);
673 :
674 14632808 : if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
675 : return;
676 :
677 12412946 : a = ira_curr_regno_allocno_map[REGNO (dreg)];
678 12412946 : acl = ALLOCNO_CLASS (a);
679 12412946 : if (! reg_classes_intersect_p (acl, def_cl))
680 : return;
681 :
682 12213900 : advance_p = true;
683 :
684 12213900 : int n_operands = recog_data.n_operands;
685 12213900 : const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
686 50606832 : for (use = 0; use < n_operands; use++)
687 : {
688 38392932 : int alt1;
689 :
690 38392932 : if (use == def || recog_data.operand_type[use] == OP_OUT)
691 12376798 : continue;
692 :
693 : /* An earlyclobber on DEF doesn't apply to an input operand X if X
694 : explicitly matches DEF, but it applies to other input operands
695 : even if they happen to be the same value as X.
696 :
697 : In contrast, if an input operand X is tied to a non-earlyclobber
698 : DEF, there's no conflict with other input operands that have the
699 : same value as X. */
700 38150851 : if (op_alt[use].matches == def
701 26016134 : || (for_tie_p
702 13620548 : && rtx_equal_p (recog_data.operand[use],
703 13620548 : recog_data.operand[op_alt[def].matched])))
704 12134717 : continue;
705 :
706 13881417 : if (op_alt[use].anything_ok)
707 : use_cl = ALL_REGS;
708 : else
709 12124111 : use_cl = op_alt[use].cl;
710 12124111 : if (use_cl == NO_REGS)
711 4809302 : continue;
712 :
713 : /* If DEF is simply a tied operand, ignore cases in which this
714 : alternative requires USE to have a likely-spilled class.
715 : Adding a conflict would just constrain USE further if DEF
716 : happens to be allocated first. */
717 9072115 : if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
718 1009386 : continue;
719 :
720 : /* If there's any alternative that allows USE to match DEF, do not
721 : record a conflict. If that causes us to create an invalid
722 : instruction due to the earlyclobber, reload must fix it up.
723 :
724 : Likewise, if we're treating a tied DEF like a partial earlyclobber,
725 : do not record a conflict if there's another alternative in which
726 : DEF is neither tied nor earlyclobber. */
727 21431457 : for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
728 : {
729 18424675 : if (!TEST_BIT (preferred_alternatives, alt1))
730 8791326 : continue;
731 9633349 : const operand_alternative *op_alt1
732 9633349 : = &recog_op_alt[alt1 * n_operands];
733 9633349 : if (op_alt1[use].matches == def
734 7674023 : || (use < n_operands - 1
735 2957948 : && recog_data.constraints[use][0] == '%'
736 8120 : && op_alt1[use + 1].matches == def)
737 7674023 : || (use >= 1
738 7672501 : && recog_data.constraints[use - 1][0] == '%'
739 3099888 : && op_alt1[use - 1].matches == def))
740 : break;
741 4584840 : if (for_tie_p
742 4365593 : && !op_alt1[def].earlyclobber
743 4364429 : && op_alt1[def].matched < 0
744 29469 : && alternative_class (op_alt1, def) != NO_REGS
745 4614309 : && alternative_class (op_alt1, use) != NO_REGS)
746 : break;
747 : }
748 :
749 8062729 : if (alt1 < recog_data.n_alternatives)
750 5055947 : continue;
751 :
752 3006782 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
753 : use, use_cl, advance_p);
754 :
755 3006782 : if ((use_match = op_alt[use].matches) >= 0)
756 : {
757 1 : gcc_checking_assert (use_match != def);
758 :
759 1 : if (op_alt[use_match].anything_ok)
760 : use_cl = ALL_REGS;
761 : else
762 1 : use_cl = op_alt[use_match].cl;
763 1 : advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
764 : use, use_cl, advance_p);
765 : }
766 : }
767 : }
768 :
769 : /* Make conflicts of early clobber pseudo registers of the current
770 : insn with its inputs. Avoid introducing unnecessary conflicts by
771 : checking classes of the constraints and pseudos because otherwise
772 : significant code degradation is possible for some targets.
773 :
774 : For these purposes, tying an input to an output makes that output act
775 : like an earlyclobber for inputs with a different value, since the output
776 : register then has a predetermined purpose on input to the instruction. */
777 : static void
778 85181497 : make_early_clobber_and_input_conflicts (void)
779 : {
780 85181497 : int alt;
781 85181497 : int def, def_match;
782 85181497 : enum reg_class def_cl;
783 :
784 85181497 : int n_alternatives = recog_data.n_alternatives;
785 85181497 : int n_operands = recog_data.n_operands;
786 85181497 : const operand_alternative *op_alt = recog_op_alt;
787 1177402480 : for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
788 1092220983 : if (TEST_BIT (preferred_alternatives, alt))
789 392799645 : for (def = 0; def < n_operands; def++)
790 : {
791 271174751 : if (op_alt[def].anything_ok)
792 : def_cl = ALL_REGS;
793 : else
794 256766935 : def_cl = op_alt[def].cl;
795 256766935 : if (def_cl != NO_REGS)
796 : {
797 214844921 : if (op_alt[def].earlyclobber)
798 145535 : check_and_make_def_conflict (alt, def, def_cl, false);
799 214699386 : else if (op_alt[def].matched >= 0
800 214699386 : && !targetm.class_likely_spilled_p (def_cl))
801 14447586 : check_and_make_def_conflict (alt, def, def_cl, true);
802 : }
803 :
804 271174751 : if ((def_match = op_alt[def].matches) >= 0
805 271174751 : && (op_alt[def_match].earlyclobber
806 15150514 : || op_alt[def].earlyclobber))
807 : {
808 39687 : if (op_alt[def_match].anything_ok)
809 : def_cl = ALL_REGS;
810 : else
811 39687 : def_cl = op_alt[def_match].cl;
812 39687 : check_and_make_def_conflict (alt, def, def_cl, false);
813 : }
814 : }
815 85181497 : }
816 :
817 : /* Mark early clobber hard registers of the current INSN as live (if
818 : LIVE_P) or dead. Return true if there are such registers. */
819 : static bool
820 95924089 : mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
821 : {
822 95924089 : df_ref def;
823 95924089 : bool set_p = false;
824 :
825 701113802 : FOR_EACH_INSN_DEF (def, insn)
826 605189713 : if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER))
827 : {
828 21930775 : rtx dreg = DF_REF_REG (def);
829 :
830 21930775 : if (GET_CODE (dreg) == SUBREG)
831 0 : dreg = SUBREG_REG (dreg);
832 21930775 : if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
833 152711 : continue;
834 :
835 : /* Hard register clobbers are believed to be early clobber
836 : because there is no way to say that non-operand hard
837 : register clobbers are not early ones. */
838 21778064 : if (live_p)
839 10889032 : mark_ref_live (def);
840 : else
841 10889032 : mark_ref_dead (def);
842 : set_p = true;
843 : }
844 :
845 95924089 : return set_p;
846 : }
847 :
848 : /* Checks that CONSTRAINTS permits to use only one hard register. If
849 : it is so, the function returns the register. Otherwise it returns -1. */
850 : static int
851 180380950 : single_reg_class_regno (const char *constraints, rtx op, rtx equiv_const)
852 : {
853 180380950 : int c;
854 180380950 : int regno, next_regno;
855 180380950 : enum reg_class next_cl;
856 180380950 : enum constraint_num cn;
857 :
858 180380950 : regno = -1;
859 180380950 : alternative_mask preferred = preferred_alternatives;
860 943293957 : while ((c = *constraints))
861 : {
862 928997214 : if (c == '#')
863 0 : preferred &= ~ALTERNATIVE_BIT (0);
864 928997214 : else if (c == ',')
865 254372317 : preferred >>= 1;
866 674624897 : else if (preferred & 1)
867 203114560 : switch (c)
868 : {
869 : case 'g':
870 : return -1;
871 :
872 135 : case '{':
873 135 : next_regno = decode_hard_reg_constraint (constraints);
874 135 : if (regno >= 0 && regno != next_regno)
875 : return -1;
876 : regno = next_regno;
877 : break;
878 :
879 182868612 : default:
880 : /* ??? Is this the best way to handle memory constraints? */
881 182868612 : cn = lookup_constraint (constraints);
882 182868612 : if (insn_extra_memory_constraint (cn)
883 170681499 : || insn_extra_special_memory_constraint (cn)
884 : || insn_extra_relaxed_memory_constraint (cn)
885 353550109 : || insn_extra_address_constraint (cn))
886 : return -1;
887 170098501 : if (constraint_satisfied_p (op, cn)
888 170098501 : || (equiv_const != NULL_RTX
889 0 : && CONSTANT_P (equiv_const)
890 0 : && constraint_satisfied_p (equiv_const, cn)))
891 : return -1;
892 155311689 : next_cl = reg_class_for_constraint (cn);
893 123563155 : if (next_cl == NO_REGS)
894 : break;
895 120318502 : next_regno = ira_class_singleton[next_cl][GET_MODE (op)];
896 120318502 : if (regno < 0
897 120318502 : ? next_regno < 0
898 : : regno != next_regno)
899 : return -1;
900 : regno = next_regno;
901 : break;
902 :
903 13060163 : case '0': case '1': case '2': case '3': case '4':
904 13060163 : case '5': case '6': case '7': case '8': case '9':
905 13060163 : {
906 13060163 : char *end;
907 13060163 : unsigned long dup = strtoul (constraints, &end, 10);
908 13060163 : constraints = end;
909 13060163 : next_regno
910 26120326 : = single_reg_class_regno (recog_data.constraints[dup],
911 13060163 : recog_data.operand[dup], NULL_RTX);
912 13060163 : if (regno < 0
913 13060163 : ? next_regno < 0
914 : : regno != next_regno)
915 12826502 : return -1;
916 233661 : regno = next_regno;
917 233661 : continue;
918 233661 : }
919 : }
920 762679346 : constraints += CONSTRAINT_LEN (c, constraints);
921 : }
922 : return regno;
923 : }
924 :
925 : /* The function checks that operand OP_NUM of the current insn can use
926 : only one hard register. If it is so, the function returns the
927 : hard register. Otherwise it returns -1. */
928 : static int
929 182640628 : single_reg_operand_class_regno (int op_num)
930 : {
931 182640628 : if (op_num < 0 || recog_data.n_alternatives == 0)
932 : return -1;
933 167320787 : return single_reg_class_regno (recog_data.constraints[op_num],
934 167320787 : recog_data.operand[op_num], NULL_RTX);
935 : }
936 :
937 : /* The function sets up hard register set *SET to hard registers which
938 : might be used by insn reloads because the constraints are too
939 : strict. */
940 : void
941 29173 : ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
942 : alternative_mask preferred)
943 : {
944 29173 : int i, c, regno = 0;
945 29173 : enum reg_class cl;
946 29173 : rtx op;
947 29173 : machine_mode mode;
948 :
949 29173 : CLEAR_HARD_REG_SET (*set);
950 90484 : for (i = 0; i < recog_data.n_operands; i++)
951 : {
952 61311 : op = recog_data.operand[i];
953 :
954 61311 : if (GET_CODE (op) == SUBREG)
955 1057 : op = SUBREG_REG (op);
956 :
957 61311 : if (GET_CODE (op) == SCRATCH
958 61311 : || (REG_P (op) && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER))
959 : {
960 40722 : const char *p = recog_data.constraints[i];
961 :
962 81444 : mode = (GET_CODE (op) == SCRATCH
963 40722 : ? GET_MODE (op) : PSEUDO_REGNO_MODE (regno));
964 40722 : cl = NO_REGS;
965 40722 : for (alternative_mask curr_preferred = preferred;
966 1473442 : (c = *p);
967 1432720 : p += CONSTRAINT_LEN (c, p))
968 1432720 : if (c == '#')
969 0 : curr_preferred &= ~ALTERNATIVE_BIT (0);
970 1432720 : else if (c == ',')
971 488599 : curr_preferred >>= 1;
972 944121 : else if (curr_preferred & 1)
973 : {
974 593161 : cl = reg_class_for_constraint (lookup_constraint (p));
975 258052 : if (cl != NO_REGS)
976 : {
977 : /* There is no register pressure problem if all of the
978 : regs in this class are fixed. */
979 253083 : int regno = ira_class_singleton[cl][mode];
980 253083 : if (regno >= 0)
981 1647 : add_to_hard_reg_set (set, mode, regno);
982 : }
983 340078 : else if (c == '{')
984 : {
985 0 : int regno = decode_hard_reg_constraint (p);
986 0 : gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
987 0 : add_to_hard_reg_set (set, mode, regno);
988 : }
989 : }
990 : }
991 : }
992 29173 : }
993 : /* Processes input operands, if IN_P, or output operands otherwise of
994 : the current insn with FREQ to find allocno which can use only one
995 : hard register and makes other currently living allocnos conflicting
996 : with the hard register. */
997 : static void
998 170362994 : process_single_reg_constrained_operands (bool in_p, int freq)
999 : {
1000 170362994 : int i, regno, hard_regno;
1001 170362994 : unsigned int px;
1002 170362994 : enum reg_class cl;
1003 170362994 : rtx operand;
1004 170362994 : ira_allocno_t operand_a, a;
1005 :
1006 535484058 : for (i = 0; i < recog_data.n_operands; i++)
1007 : {
1008 365121064 : operand = recog_data.operand[i];
1009 365121064 : if (in_p && recog_data.operand_type[i] != OP_IN
1010 62242686 : && recog_data.operand_type[i] != OP_INOUT)
1011 364339667 : continue;
1012 182560532 : if (! in_p && recog_data.operand_type[i] != OP_OUT
1013 120397942 : && recog_data.operand_type[i] != OP_INOUT)
1014 120317846 : continue;
1015 182640628 : hard_regno = single_reg_operand_class_regno (i);
1016 182640628 : if (hard_regno < 0)
1017 181859231 : continue;
1018 :
1019 781397 : operand_a = NULL;
1020 :
1021 781397 : if (GET_CODE (operand) == SUBREG)
1022 59693 : operand = SUBREG_REG (operand);
1023 :
1024 781397 : if (REG_P (operand)
1025 781397 : && (regno = REGNO (operand)) >= FIRST_PSEUDO_REGISTER)
1026 : {
1027 776845 : enum reg_class aclass;
1028 :
1029 776845 : cl = NO_REGS;
1030 776845 : int nregs = hard_regno_nregs (hard_regno, recog_data.operand_mode[i]);
1031 1587536 : for (int j = 0; j < nregs; ++j)
1032 810691 : cl = reg_class_superunion[cl][REGNO_REG_CLASS (hard_regno + j)];
1033 :
1034 776845 : operand_a = ira_curr_regno_allocno_map[regno];
1035 776845 : aclass = ALLOCNO_CLASS (operand_a);
1036 776845 : if (ira_class_subset_p[cl][aclass])
1037 : {
1038 : /* View the desired allocation of OPERAND as:
1039 :
1040 : (REG:YMODE YREGNO),
1041 :
1042 : a simplification of:
1043 :
1044 : (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1045 768465 : machine_mode ymode, xmode;
1046 768465 : int xregno, yregno;
1047 768465 : poly_int64 offset;
1048 :
1049 768465 : xmode = recog_data.operand_mode[i];
1050 768465 : xregno = hard_regno;
1051 768465 : gcc_assert (xregno >= 0);
1052 768465 : ymode = ALLOCNO_MODE (operand_a);
1053 768465 : offset = subreg_lowpart_offset (ymode, xmode);
1054 768465 : yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1055 768465 : if (yregno >= 0
1056 768465 : && ira_class_hard_reg_index[aclass][yregno] >= 0)
1057 : {
1058 768465 : int cost;
1059 :
1060 768465 : ira_allocate_and_set_costs
1061 768465 : (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a),
1062 : aclass, 0);
1063 768465 : ira_init_register_move_cost_if_necessary (xmode);
1064 1536930 : cost = freq * (in_p
1065 768465 : ? ira_register_move_cost[xmode][aclass][cl]
1066 446128 : : ira_register_move_cost[xmode][cl][aclass]);
1067 768465 : ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)
1068 768465 : [ira_class_hard_reg_index[aclass][yregno]] -= cost;
1069 : }
1070 : }
1071 : }
1072 :
1073 781397 : HARD_REG_SET hard_regs;
1074 781397 : CLEAR_HARD_REG_SET (hard_regs);
1075 781397 : add_to_hard_reg_set (&hard_regs, recog_data.operand_mode[i], hard_regno);
1076 :
1077 31326722 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1078 : {
1079 30545325 : ira_object_t obj = ira_object_id_map[px];
1080 30545325 : a = OBJECT_ALLOCNO (obj);
1081 30545325 : if (a != operand_a)
1082 : {
1083 : /* We could increase costs of A instead of making it
1084 : conflicting with the hard register. But it works worse
1085 : because it will be spilled in reload in anyway. */
1086 89190417 : OBJECT_CONFLICT_HARD_REGS (obj) |= hard_regs;
1087 30545325 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= hard_regs;
1088 : }
1089 : }
1090 : }
1091 170362994 : }
1092 :
1093 : /* Go through the operands of the extracted insn looking for operand
1094 : alternatives that apply a register filter. Record any such filters
1095 : in the operand's allocno. */
1096 : static void
1097 85181497 : process_register_constraint_filters ()
1098 : {
1099 267742029 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1100 : {
1101 182560532 : rtx op = recog_data.operand[opno];
1102 182560532 : if (SUBREG_P (op))
1103 3046227 : op = SUBREG_REG (op);
1104 182560532 : if (REG_P (op) && !HARD_REGISTER_P (op))
1105 : {
1106 75624862 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1107 1080750371 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1108 : {
1109 1005125509 : if (!TEST_BIT (preferred_alternatives, alt))
1110 879947971 : continue;
1111 :
1112 125177538 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1113 125177538 : auto cl = alternative_class (op_alt, opno);
1114 : /* The two extremes are easy:
1115 :
1116 : - We should record the filter if CL matches the
1117 : allocno class.
1118 :
1119 : - We should ignore the filter if CL and the allocno class
1120 : are disjoint. We'll either pick a different alternative
1121 : or reload the operand.
1122 :
1123 : Things are trickier if the classes overlap. However:
1124 :
1125 : - If the allocno class includes registers that are not
1126 : in CL, some choices of hard register will need a reload
1127 : anyway. It isn't obvious that reloads due to filters
1128 : are worse than reloads due to regnos being outside CL.
1129 :
1130 : - Conversely, if the allocno class is a subset of CL,
1131 : any allocation will satisfy the class requirement.
1132 : We should try to make sure it satisfies the filter
1133 : requirement too. This is useful if, for example,
1134 : an allocno needs to be in "low" registers to satisfy
1135 : some uses, and its allocno class is therefore those
1136 : low registers, but the allocno is elsewhere allowed
1137 : to be in any even-numbered register. Picking an
1138 : even-numbered low register satisfies both types of use. */
1139 125177538 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1140 29321073 : continue;
1141 :
1142 95856465 : auto filters = alternative_register_filters (op_alt, opno);
1143 95856465 : if (!filters)
1144 95856465 : continue;
1145 :
1146 0 : filters |= ALLOCNO_REGISTER_FILTERS (a);
1147 0 : ALLOCNO_SET_REGISTER_FILTERS (a, filters);
1148 : }
1149 : }
1150 : }
1151 85181497 : }
1152 :
1153 : /* Append a dependent filter ID with mode MODE, referenced allocno
1154 : REF_ALLOCNO, hardreg REF_HARD_REGNO, and REF_MODE to allocno A. */
1155 :
1156 : void
1157 0 : ira_add_dependent_filter (ira_allocno_t a, int id,
1158 : machine_mode mode, ira_allocno_t ref_allocno,
1159 : unsigned int ref_hard_regno, machine_mode ref_mode)
1160 : {
1161 : /* Check if we already have the filter that should be added.
1162 : This is a linear search and the assumption is that we'll never
1163 : have more than a handful of dependent filters. Right now, the
1164 : maximum is 32 (see gensupport.cc). */
1165 0 : for (auto *filter = ALLOCNO_DEPENDENT_FILTERS (a);
1166 0 : filter;
1167 0 : filter = filter->next)
1168 0 : if (filter->id == id
1169 0 : && filter->ref_allocno == ref_allocno
1170 0 : && filter->ref_hard_regno == ref_hard_regno
1171 0 : && filter->mode == mode
1172 0 : && filter->ref_mode == ref_mode)
1173 : return;
1174 :
1175 0 : auto *filter = (ira_dependent_filter *)
1176 0 : ira_allocate (sizeof (ira_dependent_filter));
1177 0 : filter->id = id;
1178 0 : filter->ref_allocno = ref_allocno;
1179 0 : filter->ref_hard_regno = ref_hard_regno;
1180 0 : filter->mode = mode;
1181 0 : filter->ref_mode = ref_mode;
1182 0 : filter->next = ALLOCNO_DEPENDENT_FILTERS (a);
1183 0 : ALLOCNO_DEPENDENT_FILTERS (a) = filter;
1184 : }
1185 :
1186 : /* Walk the operand alternatives of the current insn. For each
1187 : operand with a dependent-filter constraint, add one
1188 : ira_dependent_filter in the appropriate allocno. */
1189 :
1190 : static void
1191 0 : process_dependent_filters ()
1192 : {
1193 0 : if (!NUM_DEPENDENT_FILTERS)
1194 0 : return;
1195 :
1196 : for (int opno = 0; opno < recog_data.n_operands; ++opno)
1197 : {
1198 : rtx op = recog_data.operand[opno];
1199 : if (SUBREG_P (op))
1200 : op = SUBREG_REG (op);
1201 : if (!REG_P (op) || HARD_REGISTER_P (op))
1202 : continue;
1203 :
1204 : ira_allocno_t a = ira_curr_regno_allocno_map[REGNO (op)];
1205 :
1206 : for (int alt = 0; alt < recog_data.n_alternatives; alt++)
1207 : {
1208 : if (!TEST_BIT (preferred_alternatives, alt))
1209 : continue;
1210 :
1211 : auto *op_alt = &recog_op_alt[alt * recog_data.n_operands];
1212 : auto cl = alternative_class (op_alt, opno);
1213 : if (!ira_class_subset_p[ALLOCNO_CLASS (a)][cl])
1214 : continue;
1215 :
1216 : auto dep_filter_mask = alternative_dependent_filters (op_alt, opno);
1217 : if (!dep_filter_mask)
1218 : continue;
1219 :
1220 : for (int id = 0; id < NUM_DEPENDENT_FILTERS; ++id)
1221 : {
1222 : if (!(dep_filter_mask & (1U << id)))
1223 : continue;
1224 :
1225 : int ref_opno = get_dependent_filter_ref (id);
1226 : if (ref_opno < 0 || ref_opno >= recog_data.n_operands)
1227 : continue;
1228 : rtx ref_op = recog_data.operand[ref_opno];
1229 : if (SUBREG_P (ref_op))
1230 : ref_op = SUBREG_REG (ref_op);
1231 : if (!REG_P (ref_op))
1232 : continue;
1233 :
1234 : ira_allocno_t ref_a = NULL;
1235 : unsigned int ref_hard_regno = INVALID_REGNUM;
1236 : if (HARD_REGISTER_P (ref_op))
1237 : ref_hard_regno = REGNO (ref_op);
1238 : else
1239 : ref_a = ira_curr_regno_allocno_map[REGNO (ref_op)];
1240 :
1241 : ira_add_dependent_filter (a, id, GET_MODE (op),
1242 : ref_a, ref_hard_regno,
1243 : GET_MODE (ref_op));
1244 : }
1245 : }
1246 : }
1247 : }
1248 :
1249 : /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1250 : we find a SET rtx that we can use to deduce that a register can be cheaply
1251 : caller-saved. Return such a register, or NULL_RTX if none is found. */
1252 : static rtx
1253 6133242 : find_call_crossed_cheap_reg (rtx_insn *insn)
1254 : {
1255 6133242 : rtx cheap_reg = NULL_RTX;
1256 6133242 : rtx exp = CALL_INSN_FUNCTION_USAGE (insn);
1257 :
1258 18000564 : while (exp != NULL)
1259 : {
1260 12022366 : rtx x = XEXP (exp, 0);
1261 12022366 : if (GET_CODE (x) == SET)
1262 : {
1263 : exp = x;
1264 : break;
1265 : }
1266 11867322 : exp = XEXP (exp, 1);
1267 : }
1268 6133242 : if (exp != NULL)
1269 : {
1270 155044 : basic_block bb = BLOCK_FOR_INSN (insn);
1271 155044 : rtx reg = SET_SRC (exp);
1272 155044 : rtx_insn *prev = PREV_INSN (insn);
1273 310107 : while (prev && !(INSN_P (prev)
1274 155044 : && BLOCK_FOR_INSN (prev) != bb))
1275 : {
1276 155063 : if (NONDEBUG_INSN_P (prev))
1277 : {
1278 155044 : rtx set = single_set (prev);
1279 :
1280 155044 : if (set && rtx_equal_p (SET_DEST (set), reg))
1281 : {
1282 155044 : rtx src = SET_SRC (set);
1283 123334 : if (!REG_P (src) || HARD_REGISTER_P (src)
1284 277958 : || !pseudo_regno_single_word_and_live_p (REGNO (src)))
1285 : break;
1286 33562 : if (!modified_between_p (src, prev, insn))
1287 6133242 : cheap_reg = src;
1288 : break;
1289 : }
1290 0 : if (set && rtx_equal_p (SET_SRC (set), reg))
1291 : {
1292 0 : rtx dest = SET_DEST (set);
1293 0 : if (!REG_P (dest) || HARD_REGISTER_P (dest)
1294 0 : || !pseudo_regno_single_word_and_live_p (REGNO (dest)))
1295 : break;
1296 0 : if (!modified_between_p (dest, prev, insn))
1297 6133242 : cheap_reg = dest;
1298 : break;
1299 : }
1300 :
1301 0 : if (reg_set_p (reg, prev))
1302 : break;
1303 : }
1304 19 : prev = PREV_INSN (prev);
1305 : }
1306 : }
1307 6133242 : return cheap_reg;
1308 : }
1309 :
1310 : /* Determine whether INSN is a register to register copy of the type where
1311 : we do not need to make the source and destiniation registers conflict.
1312 : If this is a copy instruction, then return the source reg. Otherwise,
1313 : return NULL_RTX. */
1314 : rtx
1315 312347845 : non_conflicting_reg_copy_p (rtx_insn *insn)
1316 : {
1317 : /* Reload has issues with overlapping pseudos being assigned to the
1318 : same hard register, so don't allow it. See PR87600 for details. */
1319 312347845 : if (!targetm.lra_p ())
1320 : return NULL_RTX;
1321 :
1322 312347845 : rtx set = single_set (insn);
1323 :
1324 : /* Disallow anything other than a simple register to register copy
1325 : that has no side effects. */
1326 312347845 : if (set == NULL_RTX
1327 297020231 : || !REG_P (SET_DEST (set))
1328 218984306 : || !REG_P (SET_SRC (set))
1329 386448852 : || side_effects_p (set))
1330 : return NULL_RTX;
1331 :
1332 74101007 : int dst_regno = REGNO (SET_DEST (set));
1333 74101007 : int src_regno = REGNO (SET_SRC (set));
1334 74101007 : machine_mode mode = GET_MODE (SET_DEST (set));
1335 :
1336 : /* By definition, a register does not conflict with itself, therefore we
1337 : do not have to handle it specially. Returning NULL_RTX now, helps
1338 : simplify the callers of this function. */
1339 74101007 : if (dst_regno == src_regno)
1340 : return NULL_RTX;
1341 :
1342 : /* Computing conflicts for register pairs is difficult to get right, so
1343 : for now, disallow it. */
1344 74101007 : if ((HARD_REGISTER_NUM_P (dst_regno)
1345 20305035 : && hard_regno_nregs (dst_regno, mode) != 1)
1346 94241676 : || (HARD_REGISTER_NUM_P (src_regno)
1347 10598724 : && hard_regno_nregs (src_regno, mode) != 1))
1348 310310 : return NULL_RTX;
1349 :
1350 : return SET_SRC (set);
1351 : }
1352 :
1353 : #ifdef EH_RETURN_DATA_REGNO
1354 :
1355 : /* Add EH return hard registers as conflict hard registers to allocnos
1356 : living at end of BB. For most allocnos it is already done in
1357 : process_bb_node_lives when we processing input edges but it does
1358 : not work when and EH edge is edge out of the current region. This
1359 : function covers such out of region edges. */
1360 : static void
1361 14672926 : process_out_of_region_eh_regs (basic_block bb)
1362 : {
1363 14672926 : edge e;
1364 14672926 : edge_iterator ei;
1365 14672926 : unsigned int i;
1366 14672926 : bitmap_iterator bi;
1367 14672926 : bool eh_p = false;
1368 :
1369 35627704 : FOR_EACH_EDGE (e, ei, bb->succs)
1370 20954778 : if ((e->flags & EDGE_EH)
1371 20954778 : && IRA_BB_NODE (e->dest)->parent != IRA_BB_NODE (bb)->parent)
1372 20954778 : eh_p = true;
1373 :
1374 14672926 : if (! eh_p)
1375 14663844 : return;
1376 :
1377 134069 : EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)
1378 : {
1379 124987 : ira_allocno_t a = ira_curr_regno_allocno_map[i];
1380 256088 : for (int n = ALLOCNO_NUM_OBJECTS (a) - 1; n >= 0; n--)
1381 : {
1382 131101 : ira_object_t obj = ALLOCNO_OBJECT (a, n);
1383 524404 : OBJECT_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1384 131101 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= eh_return_data_regs;
1385 : }
1386 : }
1387 : }
1388 :
1389 : #endif
1390 :
1391 : /* Add conflicts for object OBJ from REGION landing pads using CALLEE_ABI. */
1392 : static void
1393 3777850 : add_conflict_from_region_landing_pads (eh_region region, ira_object_t obj,
1394 : function_abi callee_abi)
1395 : {
1396 3777850 : ira_allocno_t a = OBJECT_ALLOCNO (obj);
1397 3777850 : rtx_code_label *landing_label;
1398 3777850 : basic_block landing_bb;
1399 :
1400 7966217 : for (eh_landing_pad lp = region->landing_pads; lp ; lp = lp->next_lp)
1401 : {
1402 6699869 : if ((landing_label = lp->landing_pad) != NULL
1403 6699869 : && (landing_bb = BLOCK_FOR_INSN (landing_label)) != NULL
1404 13399687 : && (region->type != ERT_CLEANUP
1405 5201159 : || bitmap_bit_p (df_get_live_in (landing_bb),
1406 : ALLOCNO_REGNO (a))))
1407 : {
1408 2511502 : HARD_REG_SET new_conflict_regs
1409 2511502 : = callee_abi.mode_clobbers (ALLOCNO_MODE (a));
1410 10046008 : OBJECT_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1411 2511502 : OBJECT_TOTAL_CONFLICT_HARD_REGS (obj) |= new_conflict_regs;
1412 2511502 : return;
1413 : }
1414 : }
1415 : }
1416 :
1417 : /* Process insns of the basic block given by its LOOP_TREE_NODE to
1418 : update allocno live ranges, allocno hard register conflicts,
1419 : intersected calls, and register pressure info for allocnos for the
1420 : basic block for and regions containing the basic block. */
1421 : static void
1422 16802453 : process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1423 : {
1424 16802453 : int i, freq;
1425 16802453 : unsigned int j, k;
1426 16802453 : basic_block bb;
1427 16802453 : rtx_insn *insn;
1428 16802453 : bitmap_iterator bi;
1429 16802453 : bitmap reg_live_out;
1430 16802453 : unsigned int px;
1431 16802453 : bool set_p;
1432 :
1433 16802453 : bb = loop_tree_node->bb;
1434 16802453 : if (bb != NULL)
1435 : {
1436 72200952 : for (i = 0; i < ira_pressure_classes_num; i++)
1437 : {
1438 57528026 : curr_reg_pressure[ira_pressure_classes[i]] = 0;
1439 57528026 : high_pressure_start_point[ira_pressure_classes[i]] = -1;
1440 : }
1441 14672926 : curr_bb_node = loop_tree_node;
1442 14672926 : reg_live_out = df_get_live_out (bb);
1443 14672926 : sparseset_clear (objects_live);
1444 29345852 : REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
1445 14672926 : hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
1446 14672926 : hard_reg_set_iterator hrsi;
1447 14672926 : k = 0;
1448 15814015 : EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)
1449 : {
1450 1141089 : enum reg_class aclass, pclass, cl;
1451 :
1452 1141089 : aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];
1453 1141089 : pclass = ira_pressure_class_translate[aclass];
1454 10824703 : for (j = 0;
1455 10824703 : (cl = ira_reg_class_super_classes[pclass][j])
1456 10824703 : != LIM_REG_CLASSES;
1457 : j++)
1458 : {
1459 9683614 : if (! ira_reg_pressure_class_p[cl])
1460 8542525 : continue;
1461 1141089 : curr_reg_pressure[cl]++;
1462 1141089 : if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1463 1141089 : curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1464 1141089 : ira_assert (curr_reg_pressure[cl]
1465 : <= ira_class_hard_regs_num[cl]);
1466 : }
1467 : }
1468 156867400 : EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
1469 142194474 : mark_pseudo_regno_live (j);
1470 :
1471 : #ifdef EH_RETURN_DATA_REGNO
1472 14672926 : process_out_of_region_eh_regs (bb);
1473 : #endif
1474 :
1475 14672926 : freq = REG_FREQ_FROM_BB (bb);
1476 8751979 : if (freq == 0)
1477 2062430 : freq = 1;
1478 :
1479 : /* Invalidate all allocno_saved_at_call entries. */
1480 14672926 : last_call_num++;
1481 :
1482 : /* Scan the code of this basic block, noting which allocnos and
1483 : hard regs are born or die.
1484 :
1485 : Note that this loop treats uninitialized values as live until
1486 : the beginning of the block. For example, if an instruction
1487 : uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1488 : set, FOO will remain live until the beginning of the block.
1489 : Likewise if FOO is not set at all. This is unnecessarily
1490 : pessimistic, but it probably doesn't matter much in practice. */
1491 180329189 : FOR_BB_INSNS_REVERSE (bb, insn)
1492 : {
1493 165656263 : ira_allocno_t a;
1494 165656263 : df_ref def, use;
1495 165656263 : bool call_p;
1496 :
1497 165656263 : if (!NONDEBUG_INSN_P (insn))
1498 80474766 : continue;
1499 :
1500 85181497 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1501 1477 : fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1502 1477 : INSN_UID (insn), loop_tree_node->parent->loop_num,
1503 : curr_point);
1504 :
1505 85181497 : call_p = CALL_P (insn);
1506 85181497 : ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1507 :
1508 : /* Mark each defined value as live. We need to do this for
1509 : unused values because they still conflict with quantities
1510 : that are live at the time of the definition.
1511 :
1512 : Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1513 : references represent the effect of the called function
1514 : on a call-clobbered register. Marking the register as
1515 : live would stop us from allocating it to a call-crossing
1516 : allocno. */
1517 668782060 : FOR_EACH_INSN_DEF (def, insn)
1518 583600563 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1519 71469643 : mark_ref_live (def);
1520 :
1521 : /* If INSN has multiple outputs, then any value used in one
1522 : of the outputs conflicts with the other outputs. Model this
1523 : by making the used value live during the output phase.
1524 :
1525 : It is unsafe to use !single_set here since it will ignore
1526 : an unused output. Just because an output is unused does
1527 : not mean the compiler can assume the side effect will not
1528 : occur. Consider if ALLOCNO appears in the address of an
1529 : output and we reload the output. If we allocate ALLOCNO
1530 : to the same hard register as an unused output we could
1531 : set the hard register before the output reload insn. */
1532 85181497 : if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
1533 1868291 : FOR_EACH_INSN_USE (use, insn)
1534 : {
1535 1470403 : int i;
1536 1470403 : rtx reg;
1537 :
1538 1470403 : reg = DF_REF_REG (use);
1539 4683141 : for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
1540 : {
1541 3610723 : rtx set;
1542 :
1543 3610723 : set = XVECEXP (PATTERN (insn), 0, i);
1544 3610723 : if (GET_CODE (set) == SET
1545 3610723 : && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1546 : {
1547 : /* After the previous loop, this is a no-op if
1548 : REG is contained within SET_DEST (SET). */
1549 397985 : mark_ref_live (use);
1550 397985 : break;
1551 : }
1552 : }
1553 : }
1554 :
1555 85181497 : preferred_alternatives = ira_setup_alts (insn);
1556 85181497 : process_register_constraint_filters ();
1557 85181497 : process_dependent_filters ();
1558 85181497 : process_single_reg_constrained_operands (false, freq);
1559 :
1560 85181497 : if (call_p)
1561 : {
1562 : /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1563 : there, try to find a pseudo that is live across the call but
1564 : can be cheaply reconstructed from the return value. */
1565 6133242 : rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1566 6133242 : if (cheap_reg != NULL_RTX)
1567 33562 : add_reg_note (insn, REG_RETURNED, cheap_reg);
1568 :
1569 6133242 : last_call_num++;
1570 6133242 : sparseset_clear (allocnos_processed);
1571 : /* The current set of live allocnos are live across the call. */
1572 471026272 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1573 : {
1574 229379894 : ira_object_t obj = ira_object_id_map[i];
1575 229379894 : a = OBJECT_ALLOCNO (obj);
1576 229379894 : int num = ALLOCNO_NUM (a);
1577 229379894 : function_abi callee_abi = insn_callee_abi (insn);
1578 :
1579 : /* Don't allocate allocnos that cross setjmps or any
1580 : call, if this function receives a nonlocal
1581 : goto. */
1582 229379894 : if (cfun->has_nonlocal_label
1583 229379894 : || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1584 229377320 : && (find_reg_note (insn, REG_SETJMP, NULL_RTX)
1585 : != NULL_RTX)))
1586 : {
1587 14652 : SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj));
1588 229379894 : SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
1589 : }
1590 229379894 : eh_region r;
1591 229379894 : if (can_throw_internal (insn)
1592 229379894 : && (r = get_eh_region_from_rtx (insn)) != NULL)
1593 3777850 : add_conflict_from_region_landing_pads (r, obj, callee_abi);
1594 229379894 : if (sparseset_bit_p (allocnos_processed, num))
1595 103997464 : continue;
1596 125382430 : sparseset_set_bit (allocnos_processed, num);
1597 :
1598 125382430 : if (allocno_saved_at_call[num] != last_call_num)
1599 : /* Here we are mimicking caller-save.cc behavior
1600 : which does not save hard register at a call if
1601 : it was saved on previous call in the same basic
1602 : block and the hard register was not mentioned
1603 : between the two calls. */
1604 40479980 : ALLOCNO_CALL_FREQ (a) += freq;
1605 : /* Mark it as saved at the next call. */
1606 125382430 : allocno_saved_at_call[num] = last_call_num + 1;
1607 125382430 : ALLOCNO_CALLS_CROSSED_NUM (a)++;
1608 125382430 : ALLOCNO_CROSSED_CALLS_ABIS (a) |= 1 << callee_abi.id ();
1609 125382430 : ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)
1610 125382430 : |= callee_abi.full_and_partial_reg_clobbers ();
1611 125382430 : if (cheap_reg != NULL_RTX
1612 125382430 : && ALLOCNO_REGNO (a) == (int) REGNO (cheap_reg))
1613 33562 : ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)++;
1614 : }
1615 : }
1616 :
1617 : /* See which defined values die here. Note that we include
1618 : the call insn in the lifetimes of these values, so we don't
1619 : mistakenly consider, for e.g. an addressing mode with a
1620 : side-effect like a post-increment fetching the address,
1621 : that the use happens before the call, and the def to happen
1622 : after the call: we believe both to happen before the actual
1623 : call. (We don't handle return-values here.) */
1624 668782060 : FOR_EACH_INSN_DEF (def, insn)
1625 583600563 : if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER))
1626 71469643 : mark_ref_dead (def);
1627 :
1628 85181497 : make_early_clobber_and_input_conflicts ();
1629 :
1630 85181497 : curr_point++;
1631 :
1632 : /* Mark each used value as live. */
1633 187961131 : FOR_EACH_INSN_USE (use, insn)
1634 102779634 : mark_ref_live (use);
1635 :
1636 85181497 : process_single_reg_constrained_operands (true, freq);
1637 :
1638 85181497 : set_p = mark_hard_reg_early_clobbers (insn, true);
1639 :
1640 85181497 : if (set_p)
1641 : {
1642 10742592 : mark_hard_reg_early_clobbers (insn, false);
1643 :
1644 : /* Mark each hard reg as live again. For example, a
1645 : hard register can be in clobber and in an insn
1646 : input. */
1647 26343948 : FOR_EACH_INSN_USE (use, insn)
1648 : {
1649 15601356 : rtx ureg = DF_REF_REG (use);
1650 :
1651 15601356 : if (GET_CODE (ureg) == SUBREG)
1652 329432 : ureg = SUBREG_REG (ureg);
1653 15601356 : if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
1654 9967224 : continue;
1655 :
1656 5634132 : mark_ref_live (use);
1657 : }
1658 : }
1659 :
1660 85181497 : curr_point++;
1661 : }
1662 14672926 : ignore_reg_for_conflicts = NULL_RTX;
1663 :
1664 14672926 : if (bb_has_eh_pred (bb))
1665 226037 : for (j = 0; ; ++j)
1666 : {
1667 678111 : unsigned int regno = EH_RETURN_DATA_REGNO (j);
1668 452074 : if (regno == INVALID_REGNUM)
1669 : break;
1670 452074 : make_hard_regno_live (regno);
1671 452074 : }
1672 :
1673 : /* Allocnos can't go in stack regs at the start of a basic block
1674 : that is reached by an abnormal edge. Likewise for registers
1675 : that are at least partly call clobbered, because caller-save,
1676 : fixup_abnormal_edges and possibly the table driven EH machinery
1677 : are not quite ready to handle such allocnos live across such
1678 : edges. */
1679 14672926 : if (bb_has_abnormal_pred (bb))
1680 : {
1681 : #ifdef STACK_REGS
1682 729815 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)
1683 : {
1684 501353 : ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px]);
1685 :
1686 501353 : ALLOCNO_NO_STACK_REG_P (a) = true;
1687 501353 : ALLOCNO_TOTAL_NO_STACK_REG_P (a) = true;
1688 : }
1689 2056158 : for (px = FIRST_STACK_REG; px <= LAST_STACK_REG; px++)
1690 1827696 : make_hard_regno_live (px);
1691 : #endif
1692 : /* No need to record conflicts for call clobbered regs if we
1693 : have nonlocal labels around, as we don't ever try to
1694 : allocate such regs in this case. */
1695 228462 : if (!cfun->has_nonlocal_label
1696 228462 : && has_abnormal_call_or_eh_pred_edge_p (bb))
1697 21472660 : for (px = 0; px < FIRST_PSEUDO_REGISTER; px++)
1698 21246632 : if (eh_edge_abi.clobbers_at_least_part_of_reg_p (px)
1699 : #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1700 : /* We should create a conflict of PIC pseudo with
1701 : PIC hard reg as PIC hard reg can have a wrong
1702 : value after jump described by the abnormal edge.
1703 : In this case we cannot allocate PIC hard reg to
1704 : PIC pseudo as PIC pseudo will also have a wrong
1705 : value. This code is not critical as LRA can fix
1706 : it but it is better to have the right allocation
1707 : earlier. */
1708 21385981 : || (px == REAL_PIC_OFFSET_TABLE_REGNUM
1709 226028 : && pic_offset_table_rtx != NULL_RTX
1710 6306 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
1711 : #endif
1712 : )
1713 19258500 : make_hard_regno_live (px);
1714 : }
1715 :
1716 221301279 : EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)
1717 206628353 : make_object_dead (ira_object_id_map[i]);
1718 :
1719 14672926 : curr_point++;
1720 :
1721 : }
1722 : /* Propagate register pressure to upper loop tree nodes. */
1723 16802453 : if (loop_tree_node != ira_loop_tree_root)
1724 75300737 : for (i = 0; i < ira_pressure_classes_num; i++)
1725 : {
1726 60009668 : enum reg_class pclass;
1727 :
1728 60009668 : pclass = ira_pressure_classes[i];
1729 60009668 : if (loop_tree_node->reg_pressure[pclass]
1730 60009668 : > loop_tree_node->parent->reg_pressure[pclass])
1731 4273482 : loop_tree_node->parent->reg_pressure[pclass]
1732 4273482 : = loop_tree_node->reg_pressure[pclass];
1733 : }
1734 16802453 : }
1735 :
1736 : /* Create and set up IRA_START_POINT_RANGES and
1737 : IRA_FINISH_POINT_RANGES. */
1738 : static void
1739 3184388 : create_start_finish_chains (void)
1740 : {
1741 3184388 : ira_object_t obj;
1742 3184388 : ira_object_iterator oi;
1743 3184388 : live_range_t r;
1744 :
1745 3184388 : ira_start_point_ranges
1746 3184388 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1747 3184388 : memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1748 3184388 : ira_finish_point_ranges
1749 3184388 : = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1750 3184388 : memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1751 82307476 : FOR_EACH_OBJECT (obj, oi)
1752 186877122 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1753 : {
1754 107754034 : r->start_next = ira_start_point_ranges[r->start];
1755 107754034 : ira_start_point_ranges[r->start] = r;
1756 107754034 : r->finish_next = ira_finish_point_ranges[r->finish];
1757 107754034 : ira_finish_point_ranges[r->finish] = r;
1758 : }
1759 3184388 : }
1760 :
1761 : /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1762 : new live ranges and program points were added as a result if new
1763 : insn generation. */
1764 : void
1765 1673004 : ira_rebuild_start_finish_chains (void)
1766 : {
1767 1673004 : ira_free (ira_finish_point_ranges);
1768 1673004 : ira_free (ira_start_point_ranges);
1769 1673004 : create_start_finish_chains ();
1770 1673004 : }
1771 :
1772 : /* Compress allocno live ranges by removing program points where
1773 : nothing happens. */
1774 : static void
1775 1511384 : remove_some_program_points_and_update_live_ranges (void)
1776 : {
1777 1511384 : unsigned i;
1778 1511384 : int n;
1779 1511384 : int *map;
1780 1511384 : ira_object_t obj;
1781 1511384 : ira_object_iterator oi;
1782 1511384 : live_range_t r, prev_r, next_r;
1783 1511384 : sbitmap_iterator sbi;
1784 1511384 : bool born_p, dead_p, prev_born_p, prev_dead_p;
1785 :
1786 1511384 : auto_sbitmap born (ira_max_point);
1787 1511384 : auto_sbitmap dead (ira_max_point);
1788 1511384 : bitmap_clear (born);
1789 1511384 : bitmap_clear (dead);
1790 36418187 : FOR_EACH_OBJECT (obj, oi)
1791 89248648 : for (r = OBJECT_LIVE_RANGES (obj); r != NULL; r = r->next)
1792 : {
1793 54341845 : ira_assert (r->start <= r->finish);
1794 54341845 : bitmap_set_bit (born, r->start);
1795 54341845 : bitmap_set_bit (dead, r->finish);
1796 : }
1797 :
1798 1511384 : auto_sbitmap born_or_dead (ira_max_point);
1799 1511384 : bitmap_ior (born_or_dead, born, dead);
1800 1511384 : map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1801 1511384 : n = -1;
1802 1511384 : prev_born_p = prev_dead_p = false;
1803 68155148 : EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)
1804 : {
1805 65132380 : born_p = bitmap_bit_p (born, i);
1806 65132380 : dead_p = bitmap_bit_p (dead, i);
1807 65132380 : if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1808 58894193 : || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1809 16503910 : map[i] = n;
1810 : else
1811 48628470 : map[i] = ++n;
1812 65132380 : prev_born_p = born_p;
1813 65132380 : prev_dead_p = dead_p;
1814 : }
1815 :
1816 1511384 : n++;
1817 1511384 : if (internal_flag_ira_verbose > 1 && ira_dump_file != NULL)
1818 95 : fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1819 95 : ira_max_point, n, 100 * n / ira_max_point);
1820 1511384 : ira_max_point = n;
1821 :
1822 36418187 : FOR_EACH_OBJECT (obj, oi)
1823 89248648 : for (r = OBJECT_LIVE_RANGES (obj), prev_r = NULL; r != NULL; r = next_r)
1824 : {
1825 54341845 : next_r = r->next;
1826 54341845 : r->start = map[r->start];
1827 54341845 : r->finish = map[r->finish];
1828 54341845 : if (prev_r == NULL || prev_r->start > r->finish + 1)
1829 : {
1830 41636665 : prev_r = r;
1831 41636665 : continue;
1832 : }
1833 12705180 : prev_r->start = r->start;
1834 12705180 : prev_r->next = next_r;
1835 12705180 : ira_finish_live_range (r);
1836 : }
1837 :
1838 1511384 : ira_free (map);
1839 1511384 : }
1840 :
1841 : /* Print live ranges R to file F. */
1842 : void
1843 1466 : ira_print_live_range_list (FILE *f, live_range_t r)
1844 : {
1845 3234 : for (; r != NULL; r = r->next)
1846 1768 : fprintf (f, " [%d..%d]", r->start, r->finish);
1847 1466 : fprintf (f, "\n");
1848 1466 : }
1849 :
1850 : DEBUG_FUNCTION void
1851 0 : debug (live_range &ref)
1852 : {
1853 0 : ira_print_live_range_list (stderr, &ref);
1854 0 : }
1855 :
1856 : DEBUG_FUNCTION void
1857 0 : debug (live_range *ptr)
1858 : {
1859 0 : if (ptr)
1860 0 : debug (*ptr);
1861 : else
1862 0 : fprintf (stderr, "<nil>\n");
1863 0 : }
1864 :
1865 : /* Print live ranges R to stderr. */
1866 : void
1867 0 : ira_debug_live_range_list (live_range_t r)
1868 : {
1869 0 : ira_print_live_range_list (stderr, r);
1870 0 : }
1871 :
1872 : /* Print live ranges of object OBJ to file F. */
1873 : static void
1874 1328 : print_object_live_ranges (FILE *f, ira_object_t obj)
1875 : {
1876 0 : ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj));
1877 0 : }
1878 :
1879 : /* Print live ranges of allocno A to file F. */
1880 : static void
1881 1328 : print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1882 : {
1883 1328 : int n = ALLOCNO_NUM_OBJECTS (a);
1884 1328 : int i;
1885 :
1886 2656 : for (i = 0; i < n; i++)
1887 : {
1888 1328 : fprintf (f, " a%d(r%d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a));
1889 1328 : if (n > 1)
1890 0 : fprintf (f, " [%d]", i);
1891 1328 : fprintf (f, "):");
1892 1328 : print_object_live_ranges (f, ALLOCNO_OBJECT (a, i));
1893 : }
1894 1328 : }
1895 :
1896 : /* Print live ranges of allocno A to stderr. */
1897 : void
1898 0 : ira_debug_allocno_live_ranges (ira_allocno_t a)
1899 : {
1900 0 : print_allocno_live_ranges (stderr, a);
1901 0 : }
1902 :
1903 : /* Print live ranges of all allocnos to file F. */
1904 : static void
1905 190 : print_live_ranges (FILE *f)
1906 : {
1907 190 : ira_allocno_t a;
1908 190 : ira_allocno_iterator ai;
1909 :
1910 1518 : FOR_EACH_ALLOCNO (a, ai)
1911 1328 : print_allocno_live_ranges (f, a);
1912 190 : }
1913 :
1914 : /* Print live ranges of all allocnos to stderr. */
1915 : void
1916 0 : ira_debug_live_ranges (void)
1917 : {
1918 0 : print_live_ranges (stderr);
1919 0 : }
1920 :
1921 : /* The main entry function creates live ranges, set up
1922 : CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1923 : calculate register pressure info. */
1924 : void
1925 1511384 : ira_create_allocno_live_ranges (void)
1926 : {
1927 1511384 : objects_live = sparseset_alloc (ira_objects_num);
1928 1511384 : allocnos_processed = sparseset_alloc (ira_allocnos_num);
1929 1511384 : curr_point = 0;
1930 1511384 : last_call_num = 0;
1931 1511384 : allocno_saved_at_call
1932 1511384 : = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1933 1511384 : memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1934 1511384 : ira_traverse_loop_tree (true, ira_loop_tree_root, NULL,
1935 : process_bb_node_lives);
1936 1511384 : ira_max_point = curr_point;
1937 1511384 : create_start_finish_chains ();
1938 1511384 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1939 95 : print_live_ranges (ira_dump_file);
1940 : /* Clean up. */
1941 1511384 : ira_free (allocno_saved_at_call);
1942 1511384 : sparseset_free (objects_live);
1943 1511384 : sparseset_free (allocnos_processed);
1944 1511384 : }
1945 :
1946 : /* Compress allocno live ranges. */
1947 : void
1948 1511384 : ira_compress_allocno_live_ranges (void)
1949 : {
1950 1511384 : remove_some_program_points_and_update_live_ranges ();
1951 1511384 : ira_rebuild_start_finish_chains ();
1952 1511384 : if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL)
1953 : {
1954 95 : fprintf (ira_dump_file, "Ranges after the compression:\n");
1955 95 : print_live_ranges (ira_dump_file);
1956 : }
1957 1511384 : }
1958 :
1959 : /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1960 : void
1961 1511384 : ira_finish_allocno_live_ranges (void)
1962 : {
1963 1511384 : ira_free (ira_finish_point_ranges);
1964 1511384 : ira_free (ira_start_point_ranges);
1965 1511384 : }
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