Line data Source code
1 : /* Rtl-level induction variable analysis.
2 : Copyright (C) 2004-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it
7 : under the terms of the GNU General Public License as published by the
8 : Free Software Foundation; either version 3, or (at your option) any
9 : later version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT
12 : ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : /* This is a simple analysis of induction variables of the loop. The major use
21 : is for determining the number of iterations of a loop for loop unrolling,
22 : doloop optimization and branch prediction. The iv information is computed
23 : on demand.
24 :
25 : Induction variables are analyzed by walking the use-def chains. When
26 : a basic induction variable (biv) is found, it is cached in the bivs
27 : hash table. When register is proved to be a biv, its description
28 : is stored to DF_REF_DATA of the def reference.
29 :
30 : The analysis works always with one loop -- you must call
31 : iv_analysis_loop_init (loop) for it. All the other functions then work with
32 : this loop. When you need to work with another loop, just call
33 : iv_analysis_loop_init for it. When you no longer need iv analysis, call
34 : iv_analysis_done () to clean up the memory.
35 :
36 : The available functions are:
37 :
38 : iv_analyze (insn, mode, reg, iv): Stores the description of the induction
39 : variable corresponding to the use of register REG in INSN to IV, given
40 : that REG has mode MODE. Returns true if REG is an induction variable
41 : in INSN. false otherwise. If a use of REG is not found in INSN,
42 : the following insns are scanned (so that we may call this function
43 : on insns returned by get_condition).
44 : iv_analyze_result (insn, def, iv): Stores to IV the description of the iv
45 : corresponding to DEF, which is a register defined in INSN.
46 : iv_analyze_expr (insn, mode, expr, iv): Stores to IV the description of iv
47 : corresponding to expression EXPR evaluated at INSN. All registers used by
48 : EXPR must also be used in INSN. MODE is the mode of EXPR.
49 : */
50 :
51 : #include "config.h"
52 : #include "system.h"
53 : #include "coretypes.h"
54 : #include "backend.h"
55 : #include "rtl.h"
56 : #include "df.h"
57 : #include "memmodel.h"
58 : #include "emit-rtl.h"
59 : #include "diagnostic-core.h"
60 : #include "cfgloop.h"
61 : #include "intl.h"
62 : #include "dumpfile.h"
63 : #include "rtl-iter.h"
64 : #include "tree-ssa-loop-niter.h"
65 : #include "regs.h"
66 : #include "function-abi.h"
67 :
68 : /* Possible return values of iv_get_reaching_def. */
69 :
70 : enum iv_grd_result
71 : {
72 : /* More than one reaching def, or reaching def that does not
73 : dominate the use. */
74 : GRD_INVALID,
75 :
76 : /* The use is trivial invariant of the loop, i.e. is not changed
77 : inside the loop. */
78 : GRD_INVARIANT,
79 :
80 : /* The use is reached by initial value and a value from the
81 : previous iteration. */
82 : GRD_MAYBE_BIV,
83 :
84 : /* The use has single dominating def. */
85 : GRD_SINGLE_DOM
86 : };
87 :
88 : /* Information about a biv. */
89 :
90 : class biv_entry
91 : {
92 : public:
93 : unsigned regno; /* The register of the biv. */
94 : class rtx_iv iv; /* Value of the biv. */
95 : };
96 :
97 : static bool clean_slate = true;
98 :
99 : static unsigned int iv_ref_table_size = 0;
100 :
101 : /* Table of rtx_ivs indexed by the df_ref uid field. */
102 : static class rtx_iv ** iv_ref_table;
103 :
104 : /* Induction variable stored at the reference. */
105 : #define DF_REF_IV(REF) iv_ref_table[DF_REF_ID (REF)]
106 : #define DF_REF_IV_SET(REF, IV) iv_ref_table[DF_REF_ID (REF)] = (IV)
107 :
108 : /* The current loop. */
109 :
110 : static class loop *current_loop;
111 :
112 : /* Hashtable helper. */
113 :
114 : struct biv_entry_hasher : free_ptr_hash <biv_entry>
115 : {
116 : typedef rtx_def *compare_type;
117 : static inline hashval_t hash (const biv_entry *);
118 : static inline bool equal (const biv_entry *, const rtx_def *);
119 : };
120 :
121 : /* Returns hash value for biv B. */
122 :
123 : inline hashval_t
124 116350 : biv_entry_hasher::hash (const biv_entry *b)
125 : {
126 116350 : return b->regno;
127 : }
128 :
129 : /* Compares biv B and register R. */
130 :
131 : inline bool
132 135676 : biv_entry_hasher::equal (const biv_entry *b, const rtx_def *r)
133 : {
134 135676 : return b->regno == REGNO (r);
135 : }
136 :
137 : /* Bivs of the current loop. */
138 :
139 : static hash_table<biv_entry_hasher> *bivs;
140 :
141 : static bool iv_analyze_op (rtx_insn *, scalar_int_mode, rtx, class rtx_iv *);
142 :
143 : /* Return the RTX code corresponding to the IV extend code EXTEND. */
144 : static inline enum rtx_code
145 5 : iv_extend_to_rtx_code (enum iv_extend_code extend)
146 : {
147 5 : switch (extend)
148 : {
149 : case IV_SIGN_EXTEND:
150 : return SIGN_EXTEND;
151 : case IV_ZERO_EXTEND:
152 : return ZERO_EXTEND;
153 : case IV_UNKNOWN_EXTEND:
154 : return UNKNOWN;
155 : }
156 0 : gcc_unreachable ();
157 : }
158 :
159 : /* Dumps information about IV to FILE. */
160 :
161 : extern void dump_iv_info (FILE *, class rtx_iv *);
162 : void
163 570 : dump_iv_info (FILE *file, class rtx_iv *iv)
164 : {
165 570 : if (!iv->base)
166 : {
167 57 : fprintf (file, "not simple");
168 57 : return;
169 : }
170 :
171 513 : if (iv->step == const0_rtx
172 221 : && !iv->first_special)
173 221 : fprintf (file, "invariant ");
174 :
175 513 : print_rtl (file, iv->base);
176 513 : if (iv->step != const0_rtx)
177 : {
178 292 : fprintf (file, " + ");
179 292 : print_rtl (file, iv->step);
180 292 : fprintf (file, " * iteration");
181 : }
182 513 : fprintf (file, " (in %s)", GET_MODE_NAME (iv->mode));
183 :
184 513 : if (iv->mode != iv->extend_mode)
185 0 : fprintf (file, " %s to %s",
186 0 : rtx_name[iv_extend_to_rtx_code (iv->extend)],
187 0 : GET_MODE_NAME (iv->extend_mode));
188 :
189 513 : if (iv->mult != const1_rtx)
190 : {
191 0 : fprintf (file, " * ");
192 0 : print_rtl (file, iv->mult);
193 : }
194 513 : if (iv->delta != const0_rtx)
195 : {
196 0 : fprintf (file, " + ");
197 0 : print_rtl (file, iv->delta);
198 : }
199 513 : if (iv->first_special)
200 0 : fprintf (file, " (first special)");
201 : }
202 :
203 : static void
204 2676490 : check_iv_ref_table_size (void)
205 : {
206 2676490 : if (iv_ref_table_size < DF_DEFS_TABLE_SIZE ())
207 : {
208 262221 : unsigned int new_size = DF_DEFS_TABLE_SIZE () + (DF_DEFS_TABLE_SIZE () / 4);
209 262221 : iv_ref_table = XRESIZEVEC (class rtx_iv *, iv_ref_table, new_size);
210 262221 : memset (&iv_ref_table[iv_ref_table_size], 0,
211 262221 : (new_size - iv_ref_table_size) * sizeof (class rtx_iv *));
212 262221 : iv_ref_table_size = new_size;
213 : }
214 2676490 : }
215 :
216 :
217 : /* Checks whether REG is a well-behaved register. */
218 :
219 : static bool
220 3861697 : simple_reg_p (rtx reg)
221 : {
222 3861697 : unsigned r;
223 :
224 3861697 : if (GET_CODE (reg) == SUBREG)
225 : {
226 12078 : if (!subreg_lowpart_p (reg))
227 : return false;
228 12052 : reg = SUBREG_REG (reg);
229 : }
230 :
231 3861671 : if (!REG_P (reg))
232 : return false;
233 :
234 3565859 : r = REGNO (reg);
235 3565859 : if (HARD_REGISTER_NUM_P (r))
236 : return false;
237 :
238 3529836 : if (GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
239 : return false;
240 :
241 : return true;
242 : }
243 :
244 : /* Clears the information about ivs stored in df. */
245 :
246 : static void
247 642337 : clear_iv_info (void)
248 : {
249 642337 : unsigned i, n_defs = DF_DEFS_TABLE_SIZE ();
250 642337 : class rtx_iv *iv;
251 :
252 642337 : check_iv_ref_table_size ();
253 75497912 : for (i = 0; i < n_defs; i++)
254 : {
255 74213238 : iv = iv_ref_table[i];
256 74213238 : if (iv)
257 : {
258 691113 : free (iv);
259 691113 : iv_ref_table[i] = NULL;
260 : }
261 : }
262 :
263 642337 : bivs->empty ();
264 642337 : }
265 :
266 :
267 : /* Prepare the data for an induction variable analysis of a LOOP. */
268 :
269 : void
270 642337 : iv_analysis_loop_init (class loop *loop)
271 : {
272 642337 : current_loop = loop;
273 :
274 : /* Clear the information from the analysis of the previous loop. */
275 642337 : if (clean_slate)
276 : {
277 185846 : df_set_flags (DF_EQ_NOTES + DF_DEFER_INSN_RESCAN);
278 185846 : bivs = new hash_table<biv_entry_hasher> (10);
279 185846 : clean_slate = false;
280 : }
281 : else
282 456491 : clear_iv_info ();
283 :
284 : /* Get rid of the ud chains before processing the rescans. Then add
285 : the problem back. */
286 642337 : df_remove_problem (df_chain);
287 642337 : df_process_deferred_rescans ();
288 642337 : df_set_flags (DF_RD_PRUNE_DEAD_DEFS);
289 642337 : df_chain_add_problem (DF_UD_CHAIN);
290 642337 : df_note_add_problem ();
291 642337 : df_analyze_loop (loop);
292 642337 : if (dump_file)
293 174 : df_dump_region (dump_file);
294 :
295 642337 : check_iv_ref_table_size ();
296 642337 : }
297 :
298 : /* Finds the definition of REG that dominates loop latch and stores
299 : it to DEF. Returns false if there is not a single definition
300 : dominating the latch. If REG has no definition in loop, DEF
301 : is set to NULL and true is returned. */
302 :
303 : static bool
304 678826 : latch_dominating_def (rtx reg, df_ref *def)
305 : {
306 678826 : df_ref single_rd = NULL, adef;
307 678826 : unsigned regno = REGNO (reg);
308 678826 : class df_rd_bb_info *bb_info = DF_RD_BB_INFO (current_loop->latch);
309 :
310 2180692 : for (adef = DF_REG_DEF_CHAIN (regno); adef; adef = DF_REF_NEXT_REG (adef))
311 : {
312 1501891 : if (!bitmap_bit_p (df->blocks_to_analyze, DF_REF_BBNO (adef))
313 1501891 : || !bitmap_bit_p (&bb_info->out, DF_REF_ID (adef)))
314 843732 : continue;
315 :
316 : /* More than one reaching definition. */
317 658159 : if (single_rd)
318 : return false;
319 :
320 658159 : if (!just_once_each_iteration_p (current_loop, DF_REF_BB (adef)))
321 : return false;
322 :
323 : single_rd = adef;
324 : }
325 :
326 678801 : *def = single_rd;
327 678801 : return true;
328 : }
329 :
330 : /* Gets definition of REG reaching its use in INSN and stores it to DEF. */
331 :
332 : static enum iv_grd_result
333 2073956 : iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
334 : {
335 2073956 : df_ref use, adef;
336 2073956 : basic_block def_bb, use_bb;
337 2073956 : rtx_insn *def_insn;
338 2073956 : bool dom_p;
339 :
340 2073956 : *def = NULL;
341 2073956 : if (!simple_reg_p (reg))
342 : return GRD_INVALID;
343 1986797 : if (GET_CODE (reg) == SUBREG)
344 0 : reg = SUBREG_REG (reg);
345 1986797 : gcc_assert (REG_P (reg));
346 :
347 1986797 : use = df_find_use (insn, reg);
348 1986797 : gcc_assert (use != NULL);
349 :
350 1986797 : if (!DF_REF_CHAIN (use))
351 : return GRD_INVARIANT;
352 :
353 : /* More than one reaching def. */
354 1699797 : if (DF_REF_CHAIN (use)->next)
355 : return GRD_INVALID;
356 :
357 1672558 : adef = DF_REF_CHAIN (use)->ref;
358 :
359 : /* We do not handle setting only part of the register. */
360 1672558 : if (DF_REF_FLAGS (adef) & DF_REF_READ_WRITE)
361 : return GRD_INVALID;
362 :
363 1672552 : def_insn = DF_REF_INSN (adef);
364 1672552 : def_bb = DF_REF_BB (adef);
365 1672552 : use_bb = BLOCK_FOR_INSN (insn);
366 :
367 1672552 : if (use_bb == def_bb)
368 1551814 : dom_p = (DF_INSN_LUID (def_insn) < DF_INSN_LUID (insn));
369 : else
370 120738 : dom_p = dominated_by_p (CDI_DOMINATORS, use_bb, def_bb);
371 :
372 1672552 : if (dom_p)
373 : {
374 665942 : *def = adef;
375 665942 : return GRD_SINGLE_DOM;
376 : }
377 :
378 : /* The definition does not dominate the use. This is still OK if
379 : this may be a use of a biv, i.e. if the def_bb dominates loop
380 : latch. */
381 1006610 : if (just_once_each_iteration_p (current_loop, def_bb))
382 : return GRD_MAYBE_BIV;
383 :
384 : return GRD_INVALID;
385 : }
386 :
387 : /* Sets IV to invariant CST in MODE. Always returns true (just for
388 : consistency with other iv manipulation functions that may fail). */
389 :
390 : static bool
391 932041 : iv_constant (class rtx_iv *iv, scalar_int_mode mode, rtx cst)
392 : {
393 932041 : iv->mode = mode;
394 932041 : iv->base = cst;
395 932041 : iv->step = const0_rtx;
396 932041 : iv->first_special = false;
397 932041 : iv->extend = IV_UNKNOWN_EXTEND;
398 932041 : iv->extend_mode = iv->mode;
399 932041 : iv->delta = const0_rtx;
400 932041 : iv->mult = const1_rtx;
401 :
402 932041 : return true;
403 : }
404 :
405 : /* Evaluates application of subreg to MODE on IV. */
406 :
407 : static bool
408 5993 : iv_subreg (class rtx_iv *iv, scalar_int_mode mode)
409 : {
410 : /* If iv is invariant, just calculate the new value. */
411 5993 : if (iv->step == const0_rtx
412 73 : && !iv->first_special)
413 : {
414 71 : rtx val = get_iv_value (iv, const0_rtx);
415 71 : val = lowpart_subreg (mode, val,
416 71 : iv->extend == IV_UNKNOWN_EXTEND
417 : ? iv->mode : iv->extend_mode);
418 :
419 71 : iv->base = val;
420 71 : iv->extend = IV_UNKNOWN_EXTEND;
421 71 : iv->mode = iv->extend_mode = mode;
422 71 : iv->delta = const0_rtx;
423 71 : iv->mult = const1_rtx;
424 71 : return true;
425 : }
426 :
427 5922 : if (iv->extend_mode == mode)
428 : return true;
429 :
430 17766 : if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (iv->mode))
431 : return false;
432 :
433 5922 : iv->extend = IV_UNKNOWN_EXTEND;
434 5922 : iv->mode = mode;
435 :
436 5922 : iv->base = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
437 : simplify_gen_binary (MULT, iv->extend_mode,
438 : iv->base, iv->mult));
439 5922 : iv->step = simplify_gen_binary (MULT, iv->extend_mode, iv->step, iv->mult);
440 5922 : iv->mult = const1_rtx;
441 5922 : iv->delta = const0_rtx;
442 5922 : iv->first_special = false;
443 :
444 5922 : return true;
445 : }
446 :
447 : /* Evaluates application of EXTEND to MODE on IV. */
448 :
449 : static bool
450 779 : iv_extend (class rtx_iv *iv, enum iv_extend_code extend, scalar_int_mode mode)
451 : {
452 : /* If iv is invariant, just calculate the new value. */
453 779 : if (iv->step == const0_rtx
454 5 : && !iv->first_special)
455 : {
456 5 : rtx val = get_iv_value (iv, const0_rtx);
457 5 : if (iv->extend_mode != iv->mode
458 0 : && iv->extend != IV_UNKNOWN_EXTEND
459 5 : && iv->extend != extend)
460 0 : val = lowpart_subreg (iv->mode, val, iv->extend_mode);
461 5 : val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode,
462 : val,
463 5 : iv->extend == extend
464 : ? iv->extend_mode : iv->mode);
465 5 : iv->base = val;
466 5 : iv->extend = IV_UNKNOWN_EXTEND;
467 5 : iv->mode = iv->extend_mode = mode;
468 5 : iv->delta = const0_rtx;
469 5 : iv->mult = const1_rtx;
470 5 : return true;
471 : }
472 :
473 774 : if (mode != iv->extend_mode)
474 : return false;
475 :
476 6 : if (iv->extend != IV_UNKNOWN_EXTEND
477 0 : && iv->extend != extend)
478 : return false;
479 :
480 6 : iv->extend = extend;
481 :
482 6 : return true;
483 : }
484 :
485 : /* Evaluates negation of IV. */
486 :
487 : static bool
488 26 : iv_neg (class rtx_iv *iv)
489 : {
490 26 : if (iv->extend == IV_UNKNOWN_EXTEND)
491 : {
492 26 : iv->base = simplify_gen_unary (NEG, iv->extend_mode,
493 : iv->base, iv->extend_mode);
494 26 : iv->step = simplify_gen_unary (NEG, iv->extend_mode,
495 : iv->step, iv->extend_mode);
496 : }
497 : else
498 : {
499 0 : iv->delta = simplify_gen_unary (NEG, iv->extend_mode,
500 : iv->delta, iv->extend_mode);
501 0 : iv->mult = simplify_gen_unary (NEG, iv->extend_mode,
502 : iv->mult, iv->extend_mode);
503 : }
504 :
505 26 : return true;
506 : }
507 :
508 : /* Evaluates addition or subtraction (according to OP) of IV1 to IV0. */
509 :
510 : static bool
511 464061 : iv_add (class rtx_iv *iv0, class rtx_iv *iv1, enum rtx_code op)
512 : {
513 464061 : scalar_int_mode mode;
514 464061 : rtx arg;
515 :
516 : /* Extend the constant to extend_mode of the other operand if necessary. */
517 464061 : if (iv0->extend == IV_UNKNOWN_EXTEND
518 464060 : && iv0->mode == iv0->extend_mode
519 463355 : && iv0->step == const0_rtx
520 467634 : && GET_MODE_SIZE (iv0->extend_mode) < GET_MODE_SIZE (iv1->extend_mode))
521 : {
522 234 : iv0->extend_mode = iv1->extend_mode;
523 234 : iv0->base = simplify_gen_unary (ZERO_EXTEND, iv0->extend_mode,
524 : iv0->base, iv0->mode);
525 : }
526 464061 : if (iv1->extend == IV_UNKNOWN_EXTEND
527 464061 : && iv1->mode == iv1->extend_mode
528 463827 : && iv1->step == const0_rtx
529 1853562 : && GET_MODE_SIZE (iv1->extend_mode) < GET_MODE_SIZE (iv0->extend_mode))
530 : {
531 705 : iv1->extend_mode = iv0->extend_mode;
532 705 : iv1->base = simplify_gen_unary (ZERO_EXTEND, iv1->extend_mode,
533 : iv1->base, iv1->mode);
534 : }
535 :
536 464061 : mode = iv0->extend_mode;
537 464061 : if (mode != iv1->extend_mode)
538 : return false;
539 :
540 464061 : if (iv0->extend == IV_UNKNOWN_EXTEND
541 464060 : && iv1->extend == IV_UNKNOWN_EXTEND)
542 : {
543 464060 : if (iv0->mode != iv1->mode)
544 : return false;
545 :
546 464060 : iv0->base = simplify_gen_binary (op, mode, iv0->base, iv1->base);
547 464060 : iv0->step = simplify_gen_binary (op, mode, iv0->step, iv1->step);
548 :
549 464060 : return true;
550 : }
551 :
552 : /* Handle addition of constant. */
553 1 : if (iv1->extend == IV_UNKNOWN_EXTEND
554 1 : && iv1->mode == mode
555 2 : && iv1->step == const0_rtx)
556 : {
557 1 : iv0->delta = simplify_gen_binary (op, mode, iv0->delta, iv1->base);
558 1 : return true;
559 : }
560 :
561 0 : if (iv0->extend == IV_UNKNOWN_EXTEND
562 0 : && iv0->mode == mode
563 0 : && iv0->step == const0_rtx)
564 : {
565 0 : arg = iv0->base;
566 0 : *iv0 = *iv1;
567 0 : if (op == MINUS
568 0 : && !iv_neg (iv0))
569 : return false;
570 :
571 0 : iv0->delta = simplify_gen_binary (PLUS, mode, iv0->delta, arg);
572 0 : return true;
573 : }
574 :
575 : return false;
576 : }
577 :
578 : /* Evaluates multiplication of IV by constant CST. */
579 :
580 : static bool
581 33 : iv_mult (class rtx_iv *iv, rtx mby)
582 : {
583 33 : scalar_int_mode mode = iv->extend_mode;
584 :
585 33 : if (GET_MODE (mby) != VOIDmode
586 33 : && GET_MODE (mby) != mode)
587 : return false;
588 :
589 33 : if (iv->extend == IV_UNKNOWN_EXTEND)
590 : {
591 33 : iv->base = simplify_gen_binary (MULT, mode, iv->base, mby);
592 33 : iv->step = simplify_gen_binary (MULT, mode, iv->step, mby);
593 : }
594 : else
595 : {
596 0 : iv->delta = simplify_gen_binary (MULT, mode, iv->delta, mby);
597 0 : iv->mult = simplify_gen_binary (MULT, mode, iv->mult, mby);
598 : }
599 :
600 : return true;
601 : }
602 :
603 : /* Evaluates shift of IV by constant CST. */
604 :
605 : static bool
606 154 : iv_shift (class rtx_iv *iv, rtx mby)
607 : {
608 154 : scalar_int_mode mode = iv->extend_mode;
609 :
610 154 : if (GET_MODE (mby) != VOIDmode
611 154 : && GET_MODE (mby) != mode)
612 : return false;
613 :
614 154 : if (iv->extend == IV_UNKNOWN_EXTEND)
615 : {
616 154 : iv->base = simplify_gen_binary (ASHIFT, mode, iv->base, mby);
617 154 : iv->step = simplify_gen_binary (ASHIFT, mode, iv->step, mby);
618 : }
619 : else
620 : {
621 0 : iv->delta = simplify_gen_binary (ASHIFT, mode, iv->delta, mby);
622 0 : iv->mult = simplify_gen_binary (ASHIFT, mode, iv->mult, mby);
623 : }
624 :
625 : return true;
626 : }
627 :
628 : /* The recursive part of get_biv_step. Gets the value of the single value
629 : defined by DEF wrto initial value of REG inside loop, in shape described
630 : at get_biv_step. */
631 :
632 : static bool
633 533549 : get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
634 : rtx *inner_step, scalar_int_mode *inner_mode,
635 : enum iv_extend_code *extend,
636 : rtx *outer_step)
637 : {
638 533549 : rtx set, rhs, op0 = NULL_RTX, op1 = NULL_RTX;
639 533549 : rtx next, nextr;
640 533549 : enum rtx_code code, prev_code = UNKNOWN;
641 533549 : rtx_insn *insn = DF_REF_INSN (def);
642 533549 : df_ref next_def;
643 533549 : enum iv_grd_result res;
644 :
645 533549 : set = single_set (insn);
646 533549 : if (!set)
647 : return false;
648 :
649 531967 : rhs = find_reg_equal_equiv_note (insn);
650 531967 : if (rhs)
651 1981 : rhs = XEXP (rhs, 0);
652 : else
653 529986 : rhs = SET_SRC (set);
654 :
655 531967 : code = GET_CODE (rhs);
656 531967 : switch (code)
657 : {
658 : case SUBREG:
659 : case REG:
660 : next = rhs;
661 : break;
662 :
663 492021 : case PLUS:
664 492021 : case MINUS:
665 492021 : op0 = XEXP (rhs, 0);
666 492021 : op1 = XEXP (rhs, 1);
667 :
668 492021 : if (code == PLUS && CONSTANT_P (op0))
669 : std::swap (op0, op1);
670 :
671 492021 : if (!simple_reg_p (op0)
672 492021 : || !CONSTANT_P (op1))
673 : return false;
674 :
675 473992 : if (GET_MODE (rhs) != outer_mode)
676 : {
677 : /* ppc64 uses expressions like
678 :
679 : (set x:SI (plus:SI (subreg:SI y:DI) 1)).
680 :
681 : this is equivalent to
682 :
683 : (set x':DI (plus:DI y:DI 1))
684 : (set x:SI (subreg:SI (x':DI)). */
685 17 : if (GET_CODE (op0) != SUBREG)
686 : return false;
687 9 : if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
688 : return false;
689 : }
690 :
691 : next = op0;
692 : break;
693 :
694 183 : case SIGN_EXTEND:
695 183 : case ZERO_EXTEND:
696 183 : if (GET_MODE (rhs) != outer_mode)
697 : return false;
698 :
699 179 : op0 = XEXP (rhs, 0);
700 :
701 : /* rv64 wraps SImode arithmetic inside an extension to DImode.
702 : This matches the actual hardware semantics. So peek inside
703 : the extension and see if we have simple arithmetic that we
704 : can analyze. */
705 179 : if (GET_CODE (op0) == PLUS)
706 : {
707 0 : rhs = op0;
708 0 : op0 = XEXP (rhs, 0);
709 0 : op1 = XEXP (rhs, 1);
710 :
711 0 : if (CONSTANT_P (op0))
712 0 : std::swap (op0, op1);
713 :
714 0 : if (!simple_reg_p (op0) || !CONSTANT_P (op1))
715 : return false;
716 :
717 0 : op1 = simplify_gen_unary (code, outer_mode, op1, GET_MODE (rhs));
718 0 : prev_code = code;
719 0 : code = PLUS;
720 : }
721 :
722 179 : if (!simple_reg_p (op0))
723 : return false;
724 :
725 : next = op0;
726 : break;
727 :
728 : default:
729 : return false;
730 : }
731 :
732 496980 : if (GET_CODE (next) == SUBREG)
733 : {
734 727 : if (!subreg_lowpart_p (next))
735 : return false;
736 :
737 682 : nextr = SUBREG_REG (next);
738 682 : if (GET_MODE (nextr) != outer_mode)
739 : return false;
740 : }
741 : else
742 : nextr = next;
743 :
744 496273 : res = iv_get_reaching_def (insn, nextr, &next_def);
745 :
746 496273 : if (res == GRD_INVALID || res == GRD_INVARIANT)
747 : return false;
748 :
749 492002 : if (res == GRD_MAYBE_BIV)
750 : {
751 473790 : if (!rtx_equal_p (nextr, reg))
752 : return false;
753 :
754 473308 : *inner_step = const0_rtx;
755 473308 : *extend = IV_UNKNOWN_EXTEND;
756 473308 : *inner_mode = outer_mode;
757 473308 : *outer_step = const0_rtx;
758 : }
759 18212 : else if (!get_biv_step_1 (next_def, outer_mode, reg,
760 : inner_step, inner_mode, extend,
761 : outer_step))
762 : return false;
763 :
764 483761 : if (GET_CODE (next) == SUBREG)
765 : {
766 15 : scalar_int_mode amode;
767 15 : if (!is_a <scalar_int_mode> (GET_MODE (next), &amode)
768 30 : || GET_MODE_SIZE (amode) > GET_MODE_SIZE (*inner_mode))
769 49788 : return false;
770 :
771 15 : *inner_mode = amode;
772 15 : *inner_step = simplify_gen_binary (PLUS, outer_mode,
773 : *inner_step, *outer_step);
774 15 : *outer_step = const0_rtx;
775 15 : *extend = IV_UNKNOWN_EXTEND;
776 : }
777 :
778 483761 : switch (code)
779 : {
780 : case REG:
781 : case SUBREG:
782 : break;
783 :
784 473304 : case PLUS:
785 473304 : case MINUS:
786 473304 : if (*inner_mode == outer_mode
787 : /* See comment in previous switch. */
788 473304 : || GET_MODE (rhs) != outer_mode)
789 473303 : *inner_step = simplify_gen_binary (code, outer_mode,
790 : *inner_step, op1);
791 : else
792 1 : *outer_step = simplify_gen_binary (code, outer_mode,
793 : *outer_step, op1);
794 :
795 473304 : if (prev_code == SIGN_EXTEND)
796 0 : *extend = IV_SIGN_EXTEND;
797 473304 : else if (prev_code == ZERO_EXTEND)
798 0 : *extend = IV_ZERO_EXTEND;
799 : break;
800 :
801 15 : case SIGN_EXTEND:
802 15 : case ZERO_EXTEND:
803 15 : gcc_assert (GET_MODE (op0) == *inner_mode
804 : && *extend == IV_UNKNOWN_EXTEND
805 : && *outer_step == const0_rtx);
806 :
807 15 : *extend = (code == SIGN_EXTEND) ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
808 15 : break;
809 :
810 : default:
811 : return false;
812 : }
813 :
814 : return true;
815 : }
816 :
817 : /* Gets the operation on register REG inside loop, in shape
818 :
819 : OUTER_STEP + EXTEND_{OUTER_MODE} (SUBREG_{INNER_MODE} (REG + INNER_STEP))
820 :
821 : If the operation cannot be described in this shape, return false.
822 : LAST_DEF is the definition of REG that dominates loop latch. */
823 :
824 : static bool
825 515337 : get_biv_step (df_ref last_def, scalar_int_mode outer_mode, rtx reg,
826 : rtx *inner_step, scalar_int_mode *inner_mode,
827 : enum iv_extend_code *extend, rtx *outer_step)
828 : {
829 515337 : if (!get_biv_step_1 (last_def, outer_mode, reg,
830 : inner_step, inner_mode, extend,
831 : outer_step))
832 : return false;
833 :
834 473308 : gcc_assert ((*inner_mode == outer_mode) != (*extend != IV_UNKNOWN_EXTEND));
835 473308 : gcc_assert (*inner_mode != outer_mode || *outer_step == const0_rtx);
836 :
837 : return true;
838 : }
839 :
840 : /* Records information that DEF is induction variable IV. */
841 :
842 : static void
843 691113 : record_iv (df_ref def, class rtx_iv *iv)
844 : {
845 691113 : class rtx_iv *recorded_iv = XNEW (class rtx_iv);
846 :
847 691113 : *recorded_iv = *iv;
848 691113 : check_iv_ref_table_size ();
849 691113 : DF_REF_IV_SET (def, recorded_iv);
850 691113 : }
851 :
852 : /* If DEF was already analyzed for bivness, store the description of the biv to
853 : IV and return true. Otherwise return false. */
854 :
855 : static bool
856 594083 : analyzed_for_bivness_p (rtx def, class rtx_iv *iv)
857 : {
858 594083 : class biv_entry *biv = bivs->find_with_hash (def, REGNO (def));
859 :
860 594083 : if (!biv)
861 : return false;
862 :
863 78746 : *iv = biv->iv;
864 78746 : return true;
865 : }
866 :
867 : static void
868 515337 : record_biv (rtx def, class rtx_iv *iv)
869 : {
870 515337 : class biv_entry *biv = XNEW (class biv_entry);
871 515337 : biv_entry **slot = bivs->find_slot_with_hash (def, REGNO (def), INSERT);
872 :
873 515337 : biv->regno = REGNO (def);
874 515337 : biv->iv = *iv;
875 515337 : gcc_assert (!*slot);
876 515337 : *slot = biv;
877 515337 : }
878 :
879 : /* Determines whether DEF is a biv and if so, stores its description
880 : to *IV. OUTER_MODE is the mode of DEF. */
881 :
882 : static bool
883 594083 : iv_analyze_biv (scalar_int_mode outer_mode, rtx def, class rtx_iv *iv)
884 : {
885 594083 : rtx inner_step, outer_step;
886 594083 : scalar_int_mode inner_mode;
887 594083 : enum iv_extend_code extend;
888 594083 : df_ref last_def;
889 :
890 594083 : if (dump_file)
891 : {
892 217 : fprintf (dump_file, "Analyzing ");
893 217 : print_rtl (dump_file, def);
894 217 : fprintf (dump_file, " for bivness.\n");
895 : }
896 :
897 594083 : if (!REG_P (def))
898 : {
899 0 : if (!CONSTANT_P (def))
900 : return false;
901 :
902 0 : return iv_constant (iv, outer_mode, def);
903 : }
904 :
905 594083 : if (!latch_dominating_def (def, &last_def))
906 : {
907 0 : if (dump_file)
908 0 : fprintf (dump_file, " not simple.\n");
909 0 : return false;
910 : }
911 :
912 594083 : if (!last_def)
913 0 : return iv_constant (iv, outer_mode, def);
914 :
915 594083 : if (analyzed_for_bivness_p (def, iv))
916 : {
917 78746 : if (dump_file)
918 71 : fprintf (dump_file, " already analysed.\n");
919 78746 : return iv->base != NULL_RTX;
920 : }
921 :
922 515337 : if (!get_biv_step (last_def, outer_mode, def, &inner_step, &inner_mode,
923 : &extend, &outer_step))
924 : {
925 42029 : iv->base = NULL_RTX;
926 42029 : goto end;
927 : }
928 :
929 : /* Loop transforms base to es (base + inner_step) + outer_step,
930 : where es means extend of subreg between inner_mode and outer_mode.
931 : The corresponding induction variable is
932 :
933 : es ((base - outer_step) + i * (inner_step + outer_step)) + outer_step */
934 :
935 473308 : iv->base = simplify_gen_binary (MINUS, outer_mode, def, outer_step);
936 473308 : iv->step = simplify_gen_binary (PLUS, outer_mode, inner_step, outer_step);
937 473308 : iv->mode = inner_mode;
938 473308 : iv->extend_mode = outer_mode;
939 473308 : iv->extend = extend;
940 473308 : iv->mult = const1_rtx;
941 473308 : iv->delta = outer_step;
942 473308 : iv->first_special = inner_mode != outer_mode;
943 :
944 515337 : end:
945 515337 : if (dump_file)
946 : {
947 146 : fprintf (dump_file, " ");
948 146 : dump_iv_info (dump_file, iv);
949 146 : fprintf (dump_file, "\n");
950 : }
951 :
952 515337 : record_biv (def, iv);
953 515337 : return iv->base != NULL_RTX;
954 : }
955 :
956 : /* Analyzes expression RHS used at INSN and stores the result to *IV.
957 : The mode of the induction variable is MODE. */
958 :
959 : bool
960 1678061 : iv_analyze_expr (rtx_insn *insn, scalar_int_mode mode, rtx rhs,
961 : class rtx_iv *iv)
962 : {
963 1678061 : rtx mby = NULL_RTX;
964 1678061 : rtx op0 = NULL_RTX, op1 = NULL_RTX;
965 1678061 : class rtx_iv iv0, iv1;
966 1678061 : enum rtx_code code = GET_CODE (rhs);
967 1678061 : scalar_int_mode omode = mode;
968 :
969 1678061 : iv->base = NULL_RTX;
970 1678061 : iv->step = NULL_RTX;
971 :
972 1678061 : gcc_assert (GET_MODE (rhs) == mode || GET_MODE (rhs) == VOIDmode);
973 :
974 1678061 : if (CONSTANT_P (rhs)
975 1214789 : || REG_P (rhs)
976 660007 : || code == SUBREG)
977 1019798 : return iv_analyze_op (insn, mode, rhs, iv);
978 :
979 658263 : switch (code)
980 : {
981 : case REG:
982 : op0 = rhs;
983 : break;
984 :
985 10510 : case SIGN_EXTEND:
986 10510 : case ZERO_EXTEND:
987 10510 : case NEG:
988 10510 : op0 = XEXP (rhs, 0);
989 : /* We don't know how many bits there are in a sign-extended constant. */
990 204488 : if (!is_a <scalar_int_mode> (GET_MODE (op0), &omode))
991 : return false;
992 : break;
993 :
994 507079 : case PLUS:
995 507079 : case MINUS:
996 507079 : op0 = XEXP (rhs, 0);
997 507079 : op1 = XEXP (rhs, 1);
998 507079 : break;
999 :
1000 957 : case MULT:
1001 957 : op0 = XEXP (rhs, 0);
1002 957 : mby = XEXP (rhs, 1);
1003 957 : if (!CONSTANT_P (mby))
1004 520 : std::swap (op0, mby);
1005 957 : if (!CONSTANT_P (mby))
1006 : return false;
1007 : break;
1008 :
1009 2122 : case ASHIFT:
1010 2122 : op0 = XEXP (rhs, 0);
1011 2122 : mby = XEXP (rhs, 1);
1012 2122 : if (!CONSTANT_P (mby))
1013 : return false;
1014 : break;
1015 :
1016 : default:
1017 : return false;
1018 : }
1019 :
1020 520101 : if (op0
1021 520101 : && !iv_analyze_expr (insn, omode, op0, &iv0))
1022 : return false;
1023 :
1024 467839 : if (op1
1025 467839 : && !iv_analyze_expr (insn, omode, op1, &iv1))
1026 : return false;
1027 :
1028 465053 : switch (code)
1029 : {
1030 31 : case SIGN_EXTEND:
1031 31 : if (!iv_extend (&iv0, IV_SIGN_EXTEND, mode))
1032 : return false;
1033 : break;
1034 :
1035 748 : case ZERO_EXTEND:
1036 748 : if (!iv_extend (&iv0, IV_ZERO_EXTEND, mode))
1037 : return false;
1038 : break;
1039 :
1040 26 : case NEG:
1041 26 : if (!iv_neg (&iv0))
1042 : return false;
1043 : break;
1044 :
1045 464061 : case PLUS:
1046 464061 : case MINUS:
1047 464061 : if (!iv_add (&iv0, &iv1, code))
1048 : return false;
1049 : break;
1050 :
1051 33 : case MULT:
1052 33 : if (!iv_mult (&iv0, mby))
1053 : return false;
1054 : break;
1055 :
1056 154 : case ASHIFT:
1057 154 : if (!iv_shift (&iv0, mby))
1058 : return false;
1059 : break;
1060 :
1061 : default:
1062 : break;
1063 : }
1064 :
1065 464285 : *iv = iv0;
1066 464285 : return iv->base != NULL_RTX;
1067 : }
1068 :
1069 : /* Analyzes iv DEF and stores the result to *IV. */
1070 :
1071 : static bool
1072 700703 : iv_analyze_def (df_ref def, class rtx_iv *iv)
1073 : {
1074 700703 : rtx_insn *insn = DF_REF_INSN (def);
1075 700703 : rtx reg = DF_REF_REG (def);
1076 700703 : rtx set, rhs;
1077 :
1078 700703 : if (dump_file)
1079 : {
1080 203 : fprintf (dump_file, "Analyzing def of ");
1081 203 : print_rtl (dump_file, reg);
1082 203 : fprintf (dump_file, " in insn ");
1083 203 : print_rtl_single (dump_file, insn);
1084 : }
1085 :
1086 700703 : check_iv_ref_table_size ();
1087 700703 : if (DF_REF_IV (def))
1088 : {
1089 9138 : if (dump_file)
1090 0 : fprintf (dump_file, " already analysed.\n");
1091 9138 : *iv = *DF_REF_IV (def);
1092 9138 : return iv->base != NULL_RTX;
1093 : }
1094 :
1095 691565 : iv->base = NULL_RTX;
1096 691565 : iv->step = NULL_RTX;
1097 :
1098 691565 : scalar_int_mode mode;
1099 691863 : if (!REG_P (reg) || !is_a <scalar_int_mode> (GET_MODE (reg), &mode))
1100 : return false;
1101 :
1102 691411 : set = single_set (insn);
1103 691411 : if (!set)
1104 : return false;
1105 :
1106 691113 : if (!REG_P (SET_DEST (set)))
1107 : return false;
1108 :
1109 691113 : gcc_assert (SET_DEST (set) == reg);
1110 691113 : rhs = find_reg_equal_equiv_note (insn);
1111 691113 : if (rhs)
1112 6923 : rhs = XEXP (rhs, 0);
1113 : else
1114 684190 : rhs = SET_SRC (set);
1115 :
1116 691113 : iv_analyze_expr (insn, mode, rhs, iv);
1117 691113 : record_iv (def, iv);
1118 :
1119 691113 : if (dump_file)
1120 : {
1121 203 : print_rtl (dump_file, reg);
1122 203 : fprintf (dump_file, " in insn ");
1123 203 : print_rtl_single (dump_file, insn);
1124 203 : fprintf (dump_file, " is ");
1125 203 : dump_iv_info (dump_file, iv);
1126 203 : fprintf (dump_file, "\n");
1127 : }
1128 :
1129 691113 : return iv->base != NULL_RTX;
1130 : }
1131 :
1132 : /* Analyzes operand OP of INSN and stores the result to *IV. MODE is the
1133 : mode of OP. */
1134 :
1135 : static bool
1136 2239925 : iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
1137 : {
1138 2239925 : df_ref def = NULL;
1139 2239925 : enum iv_grd_result res;
1140 :
1141 2239925 : if (dump_file)
1142 : {
1143 513 : fprintf (dump_file, "Analyzing operand ");
1144 513 : print_rtl (dump_file, op);
1145 513 : fprintf (dump_file, " of insn ");
1146 513 : print_rtl_single (dump_file, insn);
1147 : }
1148 :
1149 2239925 : if (function_invariant_p (op))
1150 : res = GRD_INVARIANT;
1151 1591484 : else if (GET_CODE (op) == SUBREG)
1152 : {
1153 13801 : scalar_int_mode inner_mode;
1154 13801 : if (!subreg_lowpart_p (op)
1155 21091 : || !is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op)), &inner_mode))
1156 : return false;
1157 :
1158 13283 : if (!iv_analyze_op (insn, inner_mode, SUBREG_REG (op), iv))
1159 : return false;
1160 :
1161 5993 : return iv_subreg (iv, mode);
1162 : }
1163 : else
1164 : {
1165 1577683 : res = iv_get_reaching_def (insn, op, &def);
1166 1577683 : if (res == GRD_INVALID)
1167 : {
1168 116314 : if (dump_file)
1169 6 : fprintf (dump_file, " not simple.\n");
1170 116314 : return false;
1171 : }
1172 : }
1173 :
1174 1461369 : if (res == GRD_INVARIANT)
1175 : {
1176 932041 : iv_constant (iv, mode, op);
1177 :
1178 932041 : if (dump_file)
1179 : {
1180 221 : fprintf (dump_file, " ");
1181 221 : dump_iv_info (dump_file, iv);
1182 221 : fprintf (dump_file, "\n");
1183 : }
1184 932041 : return true;
1185 : }
1186 :
1187 1177769 : if (res == GRD_MAYBE_BIV)
1188 530039 : return iv_analyze_biv (mode, op, iv);
1189 :
1190 647730 : return iv_analyze_def (def, iv);
1191 : }
1192 :
1193 : /* Analyzes value VAL at INSN and stores the result to *IV. MODE is the
1194 : mode of VAL. */
1195 :
1196 : bool
1197 1206844 : iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
1198 : {
1199 1206844 : rtx reg;
1200 :
1201 : /* We must find the insn in that val is used, so that we get to UD chains.
1202 : Since the function is sometimes called on result of get_condition,
1203 : this does not necessarily have to be directly INSN; scan also the
1204 : following insns. */
1205 1206844 : if (simple_reg_p (val))
1206 : {
1207 966238 : if (GET_CODE (val) == SUBREG)
1208 12019 : reg = SUBREG_REG (val);
1209 : else
1210 966238 : reg = val;
1211 :
1212 966238 : while (!df_find_use (insn, reg))
1213 0 : insn = NEXT_INSN (insn);
1214 : }
1215 :
1216 1206844 : return iv_analyze_op (insn, mode, val, iv);
1217 : }
1218 :
1219 : /* Analyzes definition of DEF in INSN and stores the result to IV. */
1220 :
1221 : bool
1222 52973 : iv_analyze_result (rtx_insn *insn, rtx def, class rtx_iv *iv)
1223 : {
1224 52973 : df_ref adef;
1225 :
1226 52973 : adef = df_find_def (insn, def);
1227 52973 : if (!adef)
1228 : return false;
1229 :
1230 52973 : return iv_analyze_def (adef, iv);
1231 : }
1232 :
1233 : /* Checks whether definition of register REG in INSN is a basic induction
1234 : variable. MODE is the mode of REG.
1235 :
1236 : IV analysis must have been initialized (via a call to
1237 : iv_analysis_loop_init) for this function to produce a result. */
1238 :
1239 : bool
1240 88697 : biv_p (rtx_insn *insn, scalar_int_mode mode, rtx reg)
1241 : {
1242 88697 : class rtx_iv iv;
1243 88697 : df_ref def, last_def;
1244 :
1245 88697 : if (!simple_reg_p (reg))
1246 : return false;
1247 :
1248 84743 : def = df_find_def (insn, reg);
1249 84743 : gcc_assert (def != NULL);
1250 84743 : if (!latch_dominating_def (reg, &last_def))
1251 : return false;
1252 84718 : if (last_def != def)
1253 : return false;
1254 :
1255 64044 : if (!iv_analyze_biv (mode, reg, &iv))
1256 : return false;
1257 :
1258 52975 : return iv.step != const0_rtx;
1259 : }
1260 :
1261 : /* Calculates value of IV at ITERATION-th iteration. */
1262 :
1263 : rtx
1264 76 : get_iv_value (class rtx_iv *iv, rtx iteration)
1265 : {
1266 76 : rtx val;
1267 :
1268 : /* We would need to generate some if_then_else patterns, and so far
1269 : it is not needed anywhere. */
1270 76 : gcc_assert (!iv->first_special);
1271 :
1272 76 : if (iv->step != const0_rtx && iteration != const0_rtx)
1273 0 : val = simplify_gen_binary (PLUS, iv->extend_mode, iv->base,
1274 : simplify_gen_binary (MULT, iv->extend_mode,
1275 : iv->step, iteration));
1276 : else
1277 76 : val = iv->base;
1278 :
1279 76 : if (iv->extend_mode == iv->mode)
1280 : return val;
1281 :
1282 0 : val = lowpart_subreg (iv->mode, val, iv->extend_mode);
1283 :
1284 0 : if (iv->extend == IV_UNKNOWN_EXTEND)
1285 : return val;
1286 :
1287 0 : val = simplify_gen_unary (iv_extend_to_rtx_code (iv->extend),
1288 : iv->extend_mode, val, iv->mode);
1289 0 : val = simplify_gen_binary (PLUS, iv->extend_mode, iv->delta,
1290 : simplify_gen_binary (MULT, iv->extend_mode,
1291 : iv->mult, val));
1292 :
1293 0 : return val;
1294 : }
1295 :
1296 : /* Free the data for an induction variable analysis. */
1297 :
1298 : void
1299 220038 : iv_analysis_done (void)
1300 : {
1301 220038 : if (!clean_slate)
1302 : {
1303 185846 : clear_iv_info ();
1304 185846 : clean_slate = true;
1305 185846 : df_finish_pass (true);
1306 185846 : delete bivs;
1307 185846 : bivs = NULL;
1308 185846 : free (iv_ref_table);
1309 185846 : iv_ref_table = NULL;
1310 185846 : iv_ref_table_size = 0;
1311 : }
1312 220038 : }
1313 :
1314 : /* Computes inverse to X modulo (1 << MOD). */
1315 :
1316 : static uint64_t
1317 395870 : inverse (uint64_t x, int mod)
1318 : {
1319 395870 : uint64_t mask =
1320 395870 : ((uint64_t) 1 << (mod - 1) << 1) - 1;
1321 395870 : uint64_t rslt = 1;
1322 395870 : int i;
1323 :
1324 22017713 : for (i = 0; i < mod - 1; i++)
1325 : {
1326 21621843 : rslt = (rslt * x) & mask;
1327 21621843 : x = (x * x) & mask;
1328 : }
1329 :
1330 395870 : return rslt;
1331 : }
1332 :
1333 : /* Checks whether any register in X is in set ALT. */
1334 :
1335 : static bool
1336 45130321 : altered_reg_used (const_rtx x, bitmap alt)
1337 : {
1338 45130321 : subrtx_iterator::array_type array;
1339 284127110 : FOR_EACH_SUBRTX (iter, array, x, NONCONST)
1340 : {
1341 239698928 : const_rtx x = *iter;
1342 239698928 : if (REG_P (x) && REGNO_REG_SET_P (alt, REGNO (x)))
1343 702139 : return true;
1344 : }
1345 44428182 : return false;
1346 45130321 : }
1347 :
1348 : /* Marks registers altered by EXPR in set ALT. */
1349 :
1350 : static void
1351 10782752 : mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
1352 : {
1353 10782752 : if (GET_CODE (expr) == SUBREG)
1354 0 : expr = SUBREG_REG (expr);
1355 10782752 : if (!REG_P (expr))
1356 : return;
1357 :
1358 9349255 : SET_REGNO_REG_SET ((bitmap) alt, REGNO (expr));
1359 : }
1360 :
1361 : /* Checks whether RHS is simple enough to process. */
1362 :
1363 : static bool
1364 7090487 : simple_rhs_p (rtx rhs)
1365 : {
1366 7090487 : rtx op0, op1;
1367 :
1368 7090487 : if (function_invariant_p (rhs)
1369 7090487 : || (REG_P (rhs) && !HARD_REGISTER_P (rhs)))
1370 : return true;
1371 :
1372 4672418 : switch (GET_CODE (rhs))
1373 : {
1374 1395490 : case PLUS:
1375 1395490 : case MINUS:
1376 1395490 : case AND:
1377 1395490 : op0 = XEXP (rhs, 0);
1378 1395490 : op1 = XEXP (rhs, 1);
1379 : /* Allow reg OP const and reg OP reg. */
1380 1287246 : if (!(REG_P (op0) && !HARD_REGISTER_P (op0))
1381 1471542 : && !function_invariant_p (op0))
1382 : return false;
1383 642982 : if (!(REG_P (op1) && !HARD_REGISTER_P (op1))
1384 1221217 : && !function_invariant_p (op1))
1385 : return false;
1386 :
1387 : return true;
1388 :
1389 650295 : case ASHIFT:
1390 650295 : case ASHIFTRT:
1391 650295 : case LSHIFTRT:
1392 650295 : case MULT:
1393 650295 : op0 = XEXP (rhs, 0);
1394 650295 : op1 = XEXP (rhs, 1);
1395 : /* Allow reg OP const. */
1396 650295 : if (!(REG_P (op0) && !HARD_REGISTER_P (op0)))
1397 : return false;
1398 634693 : if (!function_invariant_p (op1))
1399 : return false;
1400 :
1401 : return true;
1402 :
1403 : default:
1404 : return false;
1405 : }
1406 : }
1407 :
1408 : /* If any registers in *EXPR that have a single definition, try to replace
1409 : them with the known-equivalent values. */
1410 :
1411 : static void
1412 2463234 : replace_single_def_regs (rtx *expr)
1413 : {
1414 2463234 : subrtx_var_iterator::array_type array;
1415 2535617 : repeat:
1416 15661092 : FOR_EACH_SUBRTX_VAR (iter, array, *expr, NONCONST)
1417 : {
1418 13197858 : rtx x = *iter;
1419 13197858 : if (REG_P (x))
1420 3744861 : if (rtx new_x = df_find_single_def_src (x))
1421 : {
1422 72383 : *expr = simplify_replace_rtx (*expr, x, new_x);
1423 72383 : goto repeat;
1424 : }
1425 : }
1426 2463234 : }
1427 :
1428 : /* A subroutine of simplify_using_initial_values, this function examines INSN
1429 : to see if it contains a suitable set that we can use to make a replacement.
1430 : If it is suitable, return true and set DEST and SRC to the lhs and rhs of
1431 : the set; return false otherwise. */
1432 :
1433 : static bool
1434 16899461 : suitable_set_for_replacement (rtx_insn *insn, rtx *dest, rtx *src)
1435 : {
1436 16899461 : rtx set = single_set (insn);
1437 16899461 : rtx lhs = NULL_RTX, rhs;
1438 :
1439 16899461 : if (!set)
1440 : return false;
1441 :
1442 8523090 : lhs = SET_DEST (set);
1443 8523090 : if (!REG_P (lhs))
1444 : return false;
1445 :
1446 7090487 : rhs = find_reg_equal_equiv_note (insn);
1447 7090487 : if (rhs)
1448 458676 : rhs = XEXP (rhs, 0);
1449 : else
1450 6631811 : rhs = SET_SRC (set);
1451 :
1452 7090487 : if (!simple_rhs_p (rhs))
1453 : return false;
1454 :
1455 4178969 : *dest = lhs;
1456 4178969 : *src = rhs;
1457 4178969 : return true;
1458 : }
1459 :
1460 : /* Using the data returned by suitable_set_for_replacement, replace DEST
1461 : with SRC in *EXPR and return the new expression. Also call
1462 : replace_single_def_regs if the replacement changed something. */
1463 : static void
1464 5658944 : replace_in_expr (rtx *expr, rtx dest, rtx src)
1465 : {
1466 5658944 : rtx old = *expr;
1467 5658944 : *expr = simplify_replace_rtx (*expr, dest, src);
1468 5658944 : if (old == *expr)
1469 : return;
1470 1242638 : replace_single_def_regs (expr);
1471 : }
1472 :
1473 : /* Checks whether A implies B. */
1474 :
1475 : static bool
1476 2249263 : implies_p (rtx a, rtx b)
1477 : {
1478 2249263 : rtx op0, op1, opb0, opb1;
1479 2249263 : machine_mode mode;
1480 :
1481 2249263 : if (rtx_equal_p (a, b))
1482 : return true;
1483 :
1484 2246347 : if (GET_CODE (a) == EQ)
1485 : {
1486 437835 : op0 = XEXP (a, 0);
1487 437835 : op1 = XEXP (a, 1);
1488 :
1489 437835 : if (REG_P (op0)
1490 240115 : || (GET_CODE (op0) == SUBREG
1491 3906 : && REG_P (SUBREG_REG (op0))))
1492 : {
1493 200976 : rtx r = simplify_replace_rtx (b, op0, op1);
1494 200976 : if (r == const_true_rtx)
1495 : return true;
1496 : }
1497 :
1498 419086 : if (REG_P (op1)
1499 325399 : || (GET_CODE (op1) == SUBREG
1500 1492 : && REG_P (SUBREG_REG (op1))))
1501 : {
1502 95179 : rtx r = simplify_replace_rtx (b, op1, op0);
1503 95179 : if (r == const_true_rtx)
1504 : return true;
1505 : }
1506 : }
1507 :
1508 2227556 : if (b == const_true_rtx)
1509 : return true;
1510 :
1511 2227556 : if ((GET_RTX_CLASS (GET_CODE (a)) != RTX_COMM_COMPARE
1512 : && GET_RTX_CLASS (GET_CODE (a)) != RTX_COMPARE)
1513 2219611 : || (GET_RTX_CLASS (GET_CODE (b)) != RTX_COMM_COMPARE
1514 : && GET_RTX_CLASS (GET_CODE (b)) != RTX_COMPARE))
1515 : return false;
1516 :
1517 2200433 : op0 = XEXP (a, 0);
1518 2200433 : op1 = XEXP (a, 1);
1519 2200433 : opb0 = XEXP (b, 0);
1520 2200433 : opb1 = XEXP (b, 1);
1521 :
1522 2200433 : mode = GET_MODE (op0);
1523 2200433 : if (mode != GET_MODE (opb0))
1524 : mode = VOIDmode;
1525 1928632 : else if (mode == VOIDmode)
1526 : {
1527 0 : mode = GET_MODE (op1);
1528 0 : if (mode != GET_MODE (opb1))
1529 271801 : mode = VOIDmode;
1530 : }
1531 :
1532 : /* A < B implies A + 1 <= B. */
1533 2200433 : if ((GET_CODE (a) == GT || GET_CODE (a) == LT)
1534 460728 : && (GET_CODE (b) == GE || GET_CODE (b) == LE))
1535 : {
1536 :
1537 38109 : if (GET_CODE (a) == GT)
1538 22944 : std::swap (op0, op1);
1539 :
1540 38109 : if (GET_CODE (b) == GE)
1541 15778 : std::swap (opb0, opb1);
1542 :
1543 38109 : if (SCALAR_INT_MODE_P (mode)
1544 37499 : && rtx_equal_p (op1, opb1)
1545 40927 : && simplify_gen_binary (MINUS, mode, opb0, op0) == const1_rtx)
1546 : return true;
1547 37872 : return false;
1548 : }
1549 :
1550 : /* A < B or A > B imply A != B. TODO: Likewise
1551 : A + n < B implies A != B + n if neither wraps. */
1552 2162324 : if (GET_CODE (b) == NE
1553 : && (GET_CODE (a) == GT || GET_CODE (a) == GTU
1554 : || GET_CODE (a) == LT || GET_CODE (a) == LTU))
1555 : {
1556 165583 : if (rtx_equal_p (op0, opb0)
1557 165583 : && rtx_equal_p (op1, opb1))
1558 : return true;
1559 : }
1560 :
1561 : /* For unsigned comparisons, A != 0 implies A > 0 and A >= 1. */
1562 2136234 : if (GET_CODE (a) == NE
1563 567299 : && op1 == const0_rtx)
1564 : {
1565 308273 : if ((GET_CODE (b) == GTU
1566 24632 : && opb1 == const0_rtx)
1567 308273 : || (GET_CODE (b) == GEU
1568 6047 : && opb1 == const1_rtx))
1569 0 : return rtx_equal_p (op0, opb0);
1570 : }
1571 :
1572 : /* A != N is equivalent to A - (N + 1) <u -1. */
1573 2136234 : if (GET_CODE (a) == NE
1574 567299 : && CONST_INT_P (op1)
1575 404557 : && GET_CODE (b) == LTU
1576 67436 : && opb1 == constm1_rtx
1577 23210 : && GET_CODE (opb0) == PLUS
1578 5974 : && CONST_INT_P (XEXP (opb0, 1))
1579 : /* Avoid overflows. */
1580 423 : && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1581 : != (HOST_WIDE_INT_1U
1582 : << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1583 423 : && INTVAL (XEXP (opb0, 1)) + 1 == -INTVAL (op1))
1584 224 : return rtx_equal_p (op0, XEXP (opb0, 0));
1585 :
1586 : /* Likewise, A != N implies A - N > 0. */
1587 2136010 : if (GET_CODE (a) == NE
1588 567075 : && CONST_INT_P (op1))
1589 : {
1590 404333 : if (GET_CODE (b) == GTU
1591 38812 : && GET_CODE (opb0) == PLUS
1592 16849 : && opb1 == const0_rtx
1593 0 : && CONST_INT_P (XEXP (opb0, 1))
1594 : /* Avoid overflows. */
1595 0 : && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1596 : != (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
1597 404333 : && rtx_equal_p (XEXP (opb0, 0), op0))
1598 0 : return INTVAL (op1) == -INTVAL (XEXP (opb0, 1));
1599 404333 : if (GET_CODE (b) == GEU
1600 10879 : && GET_CODE (opb0) == PLUS
1601 2911 : && opb1 == const1_rtx
1602 0 : && CONST_INT_P (XEXP (opb0, 1))
1603 : /* Avoid overflows. */
1604 0 : && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (opb0, 1))
1605 : != (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
1606 404333 : && rtx_equal_p (XEXP (opb0, 0), op0))
1607 0 : return INTVAL (op1) == -INTVAL (XEXP (opb0, 1));
1608 : }
1609 :
1610 : /* A >s X, where X is positive, implies A <u Y, if Y is negative. */
1611 2136010 : if ((GET_CODE (a) == GT || GET_CODE (a) == GE)
1612 280642 : && CONST_INT_P (op1)
1613 194607 : && ((GET_CODE (a) == GT && op1 == constm1_rtx)
1614 165544 : || INTVAL (op1) >= 0)
1615 183643 : && GET_CODE (b) == LTU
1616 8219 : && CONST_INT_P (opb1)
1617 2143767 : && rtx_equal_p (op0, opb0))
1618 995 : return INTVAL (opb1) < 0;
1619 :
1620 : return false;
1621 : }
1622 :
1623 : /* Canonicalizes COND so that
1624 :
1625 : (1) Ensure that operands are ordered according to
1626 : swap_commutative_operands_p.
1627 : (2) (LE x const) will be replaced with (LT x <const+1>) and similarly
1628 : for GE, GEU, and LEU. */
1629 :
1630 : rtx
1631 2231883 : canon_condition (rtx cond)
1632 : {
1633 2231883 : rtx op0, op1;
1634 2231883 : enum rtx_code code;
1635 2231883 : machine_mode mode;
1636 :
1637 2231883 : code = GET_CODE (cond);
1638 2231883 : op0 = XEXP (cond, 0);
1639 2231883 : op1 = XEXP (cond, 1);
1640 :
1641 2231883 : if (swap_commutative_operands_p (op0, op1))
1642 : {
1643 210426 : code = swap_condition (code);
1644 210426 : std::swap (op0, op1);
1645 : }
1646 :
1647 2231883 : mode = GET_MODE (op0);
1648 2231883 : if (mode == VOIDmode)
1649 0 : mode = GET_MODE (op1);
1650 2231883 : gcc_assert (mode != VOIDmode);
1651 :
1652 2231883 : if (CONST_SCALAR_INT_P (op1) && GET_MODE_CLASS (mode) != MODE_CC)
1653 : {
1654 1563924 : rtx_mode_t const_val (op1, mode);
1655 :
1656 1563924 : switch (code)
1657 : {
1658 68242 : case LE:
1659 68242 : if (wi::ne_p (const_val, wi::max_value (mode, SIGNED)))
1660 : {
1661 68242 : code = LT;
1662 68242 : op1 = immed_wide_int_const (wi::add (const_val, 1), mode);
1663 : }
1664 : break;
1665 :
1666 125976 : case GE:
1667 125976 : if (wi::ne_p (const_val, wi::min_value (mode, SIGNED)))
1668 : {
1669 125976 : code = GT;
1670 125976 : op1 = immed_wide_int_const (wi::sub (const_val, 1), mode);
1671 : }
1672 : break;
1673 :
1674 48312 : case LEU:
1675 48312 : if (wi::ne_p (const_val, -1))
1676 : {
1677 48312 : code = LTU;
1678 48312 : op1 = immed_wide_int_const (wi::add (const_val, 1), mode);
1679 : }
1680 : break;
1681 :
1682 149934 : case GEU:
1683 149934 : if (wi::ne_p (const_val, 0))
1684 : {
1685 149934 : code = GTU;
1686 149934 : op1 = immed_wide_int_const (wi::sub (const_val, 1), mode);
1687 : }
1688 : break;
1689 :
1690 : default:
1691 : break;
1692 : }
1693 : }
1694 :
1695 2231883 : if (op0 != XEXP (cond, 0)
1696 2021457 : || op1 != XEXP (cond, 1)
1697 1686853 : || code != GET_CODE (cond)
1698 1686853 : || GET_MODE (cond) != SImode)
1699 1631503 : cond = gen_rtx_fmt_ee (code, SImode, op0, op1);
1700 :
1701 2231883 : return cond;
1702 : }
1703 :
1704 : /* Reverses CONDition; returns NULL if we cannot. */
1705 :
1706 : static rtx
1707 2018057 : reversed_condition (rtx cond)
1708 : {
1709 2018057 : enum rtx_code reversed;
1710 2018057 : reversed = reversed_comparison_code (cond, NULL);
1711 2018057 : if (reversed == UNKNOWN)
1712 : return NULL_RTX;
1713 : else
1714 2009988 : return gen_rtx_fmt_ee (reversed,
1715 : GET_MODE (cond), XEXP (cond, 0),
1716 : XEXP (cond, 1));
1717 : }
1718 :
1719 : /* Tries to use the fact that COND holds to simplify EXPR. ALTERED is the
1720 : set of altered regs. */
1721 :
1722 : void
1723 1381964 : simplify_using_condition (rtx cond, rtx *expr, regset altered)
1724 : {
1725 1381964 : rtx rev, reve, exp = *expr;
1726 :
1727 : /* If some register gets altered later, we do not really speak about its
1728 : value at the time of comparison. */
1729 1381964 : if (altered && altered_reg_used (cond, altered))
1730 : return;
1731 :
1732 1358498 : if (GET_CODE (cond) == EQ
1733 228129 : && REG_P (XEXP (cond, 0)) && CONSTANT_P (XEXP (cond, 1)))
1734 : {
1735 72660 : *expr = simplify_replace_rtx (*expr, XEXP (cond, 0), XEXP (cond, 1));
1736 72660 : return;
1737 : }
1738 :
1739 1285838 : if (!COMPARISON_P (exp))
1740 : return;
1741 :
1742 558295 : rev = reversed_condition (cond);
1743 558295 : reve = reversed_condition (exp);
1744 :
1745 558295 : cond = canon_condition (cond);
1746 558295 : exp = canon_condition (exp);
1747 558295 : if (rev)
1748 556998 : rev = canon_condition (rev);
1749 558295 : if (reve)
1750 558295 : reve = canon_condition (reve);
1751 :
1752 558295 : if (rtx_equal_p (exp, cond))
1753 : {
1754 8050 : *expr = const_true_rtx;
1755 8050 : return;
1756 : }
1757 :
1758 550245 : if (rev && rtx_equal_p (exp, rev))
1759 : {
1760 5295 : *expr = const0_rtx;
1761 5295 : return;
1762 : }
1763 :
1764 544950 : if (implies_p (cond, exp))
1765 : {
1766 27240 : *expr = const_true_rtx;
1767 27240 : return;
1768 : }
1769 :
1770 517710 : if (reve && implies_p (cond, reve))
1771 : {
1772 358 : *expr = const0_rtx;
1773 358 : return;
1774 : }
1775 :
1776 : /* A proof by contradiction. If *EXPR implies (not cond), *EXPR must
1777 : be false. */
1778 517352 : if (rev && implies_p (exp, rev))
1779 : {
1780 8999 : *expr = const0_rtx;
1781 8999 : return;
1782 : }
1783 :
1784 : /* Similarly, If (not *EXPR) implies (not cond), *EXPR must be true. */
1785 508353 : if (rev && reve && implies_p (reve, rev))
1786 : {
1787 1416 : *expr = const_true_rtx;
1788 1416 : return;
1789 : }
1790 :
1791 : /* We would like to have some other tests here. TODO. */
1792 :
1793 : return;
1794 : }
1795 :
1796 : /* Use relationship between A and *B to eventually eliminate *B.
1797 : OP is the operation we consider. */
1798 :
1799 : static void
1800 163492 : eliminate_implied_condition (enum rtx_code op, rtx a, rtx *b)
1801 : {
1802 163492 : switch (op)
1803 : {
1804 0 : case AND:
1805 : /* If A implies *B, we may replace *B by true. */
1806 0 : if (implies_p (a, *b))
1807 0 : *b = const_true_rtx;
1808 : break;
1809 :
1810 163492 : case IOR:
1811 : /* If *B implies A, we may replace *B by false. */
1812 163492 : if (implies_p (*b, a))
1813 11233 : *b = const0_rtx;
1814 : break;
1815 :
1816 0 : default:
1817 0 : gcc_unreachable ();
1818 : }
1819 163492 : }
1820 :
1821 : /* Eliminates the conditions in TAIL that are implied by HEAD. OP is the
1822 : operation we consider. */
1823 :
1824 : static void
1825 704234 : eliminate_implied_conditions (enum rtx_code op, rtx *head, rtx tail)
1826 : {
1827 704234 : rtx elt;
1828 :
1829 785980 : for (elt = tail; elt; elt = XEXP (elt, 1))
1830 81746 : eliminate_implied_condition (op, *head, &XEXP (elt, 0));
1831 785980 : for (elt = tail; elt; elt = XEXP (elt, 1))
1832 81746 : eliminate_implied_condition (op, XEXP (elt, 0), head);
1833 704234 : }
1834 :
1835 : /* Simplifies *EXPR using initial values at the start of the LOOP. If *EXPR
1836 : is a list, its elements are assumed to be combined using OP. */
1837 :
1838 : static void
1839 5046062 : simplify_using_initial_values (class loop *loop, enum rtx_code op, rtx *expr)
1840 : {
1841 5046062 : bool expression_valid;
1842 5046062 : rtx head, tail, last_valid_expr;
1843 5046062 : rtx_expr_list *cond_list;
1844 5046062 : rtx_insn *insn;
1845 5046062 : rtx neutral, aggr;
1846 5046062 : regset altered, this_altered;
1847 5046062 : edge e;
1848 :
1849 5046062 : if (!*expr)
1850 3825470 : return;
1851 :
1852 2483280 : if (CONSTANT_P (*expr))
1853 : return;
1854 :
1855 1924830 : if (GET_CODE (*expr) == EXPR_LIST)
1856 : {
1857 704234 : head = XEXP (*expr, 0);
1858 704234 : tail = XEXP (*expr, 1);
1859 :
1860 704234 : eliminate_implied_conditions (op, &head, tail);
1861 :
1862 704234 : switch (op)
1863 : {
1864 4954 : case AND:
1865 4954 : neutral = const_true_rtx;
1866 4954 : aggr = const0_rtx;
1867 4954 : break;
1868 :
1869 699280 : case IOR:
1870 699280 : neutral = const0_rtx;
1871 699280 : aggr = const_true_rtx;
1872 699280 : break;
1873 :
1874 0 : default:
1875 0 : gcc_unreachable ();
1876 : }
1877 :
1878 704234 : simplify_using_initial_values (loop, UNKNOWN, &head);
1879 704234 : if (head == aggr)
1880 : {
1881 106 : XEXP (*expr, 0) = aggr;
1882 106 : XEXP (*expr, 1) = NULL_RTX;
1883 106 : return;
1884 : }
1885 704128 : else if (head == neutral)
1886 : {
1887 390611 : *expr = tail;
1888 390611 : simplify_using_initial_values (loop, op, expr);
1889 390611 : return;
1890 : }
1891 313517 : simplify_using_initial_values (loop, op, &tail);
1892 :
1893 313517 : if (tail && XEXP (tail, 0) == aggr)
1894 : {
1895 0 : *expr = tail;
1896 0 : return;
1897 : }
1898 :
1899 313517 : XEXP (*expr, 0) = head;
1900 313517 : XEXP (*expr, 1) = tail;
1901 313517 : return;
1902 : }
1903 :
1904 1220596 : gcc_assert (op == UNKNOWN);
1905 :
1906 1220596 : replace_single_def_regs (expr);
1907 1220596 : if (CONSTANT_P (*expr))
1908 : return;
1909 :
1910 1220592 : e = loop_preheader_edge (loop);
1911 1220592 : if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun))
1912 : return;
1913 :
1914 1220592 : altered = ALLOC_REG_SET (®_obstack);
1915 1220592 : this_altered = ALLOC_REG_SET (®_obstack);
1916 :
1917 1220592 : expression_valid = true;
1918 1220592 : last_valid_expr = *expr;
1919 1220592 : cond_list = NULL;
1920 2291756 : while (1)
1921 : {
1922 2291756 : insn = BB_END (e->src);
1923 2291756 : if (any_condjump_p (insn) && onlyjump_p (insn))
1924 : {
1925 1034241 : rtx cond = get_condition (BB_END (e->src), NULL, false, true);
1926 :
1927 1034241 : if (cond && (e->flags & EDGE_FALLTHRU))
1928 723976 : cond = reversed_condition (cond);
1929 1024397 : if (cond)
1930 : {
1931 1021214 : rtx old = *expr;
1932 1021214 : simplify_using_condition (cond, expr, altered);
1933 1021214 : if (old != *expr)
1934 : {
1935 49257 : rtx note;
1936 49257 : if (CONSTANT_P (*expr))
1937 48614 : goto out;
1938 989 : for (note = cond_list; note; note = XEXP (note, 1))
1939 : {
1940 465 : simplify_using_condition (XEXP (note, 0), expr, altered);
1941 465 : if (CONSTANT_P (*expr))
1942 119 : goto out;
1943 : }
1944 : }
1945 972481 : cond_list = alloc_EXPR_LIST (0, cond, cond_list);
1946 : }
1947 : }
1948 :
1949 20706585 : FOR_BB_INSNS_REVERSE (e->src, insn)
1950 : {
1951 19195496 : rtx src, dest;
1952 19195496 : rtx old = *expr;
1953 :
1954 19195496 : if (!INSN_P (insn))
1955 2296035 : continue;
1956 :
1957 16899461 : CLEAR_REG_SET (this_altered);
1958 16899461 : note_stores (insn, mark_altered, this_altered);
1959 16899461 : if (CALL_P (insn))
1960 : {
1961 : /* Kill all registers that might be clobbered by the call.
1962 : We don't track modes of hard registers, so we need to be
1963 : conservative and assume that partial kills are full kills. */
1964 140863 : function_abi callee_abi = insn_callee_abi (insn);
1965 140863 : IOR_REG_SET_HRS (this_altered,
1966 : callee_abi.full_and_partial_reg_clobbers ());
1967 : }
1968 :
1969 16899461 : if (suitable_set_for_replacement (insn, &dest, &src))
1970 : {
1971 4178969 : rtx_expr_list **pnote, **pnote_next;
1972 :
1973 4178969 : replace_in_expr (expr, dest, src);
1974 4178969 : if (CONSTANT_P (*expr))
1975 731934 : goto out;
1976 :
1977 5338062 : for (pnote = &cond_list; *pnote; pnote = pnote_next)
1978 : {
1979 1479975 : rtx_expr_list *note = *pnote;
1980 1479975 : rtx old_cond = XEXP (note, 0);
1981 :
1982 1479975 : pnote_next = (rtx_expr_list **)&XEXP (note, 1);
1983 1479975 : replace_in_expr (&XEXP (note, 0), dest, src);
1984 :
1985 : /* We can no longer use a condition that has been simplified
1986 : to a constant, and simplify_using_condition will abort if
1987 : we try. */
1988 1479975 : if (CONSTANT_P (XEXP (note, 0)))
1989 : {
1990 32 : *pnote = *pnote_next;
1991 32 : pnote_next = pnote;
1992 32 : free_EXPR_LIST_node (note);
1993 : }
1994 : /* Retry simplifications with this condition if either the
1995 : expression or the condition changed. */
1996 1479943 : else if (old_cond != XEXP (note, 0) || old != *expr)
1997 360285 : simplify_using_condition (XEXP (note, 0), expr, altered);
1998 : }
1999 : }
2000 : else
2001 : {
2002 12720492 : rtx_expr_list **pnote, **pnote_next;
2003 :
2004 : /* If we did not use this insn to make a replacement, any overlap
2005 : between stores in this insn and our expression will cause the
2006 : expression to become invalid. */
2007 12720492 : if (altered_reg_used (*expr, this_altered))
2008 407197 : goto out;
2009 :
2010 : /* Likewise for the conditions. */
2011 27173633 : for (pnote = &cond_list; *pnote; pnote = pnote_next)
2012 : {
2013 14860338 : rtx_expr_list *note = *pnote;
2014 14860338 : rtx old_cond = XEXP (note, 0);
2015 :
2016 14860338 : pnote_next = (rtx_expr_list **)&XEXP (note, 1);
2017 14860338 : if (altered_reg_used (old_cond, this_altered))
2018 : {
2019 203196 : *pnote = *pnote_next;
2020 203196 : pnote_next = pnote;
2021 203196 : free_EXPR_LIST_node (note);
2022 : }
2023 : }
2024 : }
2025 :
2026 16171382 : if (CONSTANT_P (*expr))
2027 3855 : goto out;
2028 :
2029 16167527 : IOR_REG_SET (altered, this_altered);
2030 :
2031 : /* If the expression now contains regs that have been altered, we
2032 : can't return it to the caller. However, it is still valid for
2033 : further simplification, so keep searching to see if we can
2034 : eventually turn it into a constant. */
2035 16167527 : if (altered_reg_used (*expr, altered))
2036 : expression_valid = false;
2037 16099247 : if (expression_valid)
2038 16097994 : last_valid_expr = *expr;
2039 : }
2040 :
2041 1511089 : if (!single_pred_p (e->src)
2042 1511089 : || single_pred (e->src) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
2043 : break;
2044 : e = single_pred_edge (e->src);
2045 : }
2046 :
2047 1220592 : out:
2048 1220592 : free_EXPR_LIST_list (&cond_list);
2049 1220592 : if (!CONSTANT_P (*expr))
2050 847122 : *expr = last_valid_expr;
2051 1220592 : FREE_REG_SET (altered);
2052 1220592 : FREE_REG_SET (this_altered);
2053 : }
2054 :
2055 : /* Transforms invariant IV into MODE. Adds assumptions based on the fact
2056 : that IV occurs as left operands of comparison COND and its signedness
2057 : is SIGNED_P to DESC. */
2058 :
2059 : static void
2060 1 : shorten_into_mode (class rtx_iv *iv, scalar_int_mode mode,
2061 : enum rtx_code cond, bool signed_p, class niter_desc *desc)
2062 : {
2063 1 : rtx mmin, mmax, cond_over, cond_under;
2064 :
2065 1 : get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax);
2066 1 : cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode,
2067 : iv->base, mmin);
2068 1 : cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode,
2069 : iv->base, mmax);
2070 :
2071 1 : switch (cond)
2072 : {
2073 0 : case LE:
2074 0 : case LT:
2075 0 : case LEU:
2076 0 : case LTU:
2077 0 : if (cond_under != const0_rtx)
2078 0 : desc->infinite =
2079 0 : alloc_EXPR_LIST (0, cond_under, desc->infinite);
2080 0 : if (cond_over != const0_rtx)
2081 0 : desc->noloop_assumptions =
2082 0 : alloc_EXPR_LIST (0, cond_over, desc->noloop_assumptions);
2083 : break;
2084 :
2085 1 : case GE:
2086 1 : case GT:
2087 1 : case GEU:
2088 1 : case GTU:
2089 1 : if (cond_over != const0_rtx)
2090 1 : desc->infinite =
2091 1 : alloc_EXPR_LIST (0, cond_over, desc->infinite);
2092 1 : if (cond_under != const0_rtx)
2093 1 : desc->noloop_assumptions =
2094 1 : alloc_EXPR_LIST (0, cond_under, desc->noloop_assumptions);
2095 : break;
2096 :
2097 0 : case NE:
2098 0 : if (cond_over != const0_rtx)
2099 0 : desc->infinite =
2100 0 : alloc_EXPR_LIST (0, cond_over, desc->infinite);
2101 0 : if (cond_under != const0_rtx)
2102 0 : desc->infinite =
2103 0 : alloc_EXPR_LIST (0, cond_under, desc->infinite);
2104 : break;
2105 :
2106 0 : default:
2107 0 : gcc_unreachable ();
2108 : }
2109 :
2110 1 : iv->mode = mode;
2111 1 : iv->extend = signed_p ? IV_SIGN_EXTEND : IV_ZERO_EXTEND;
2112 1 : }
2113 :
2114 : /* Transforms IV0 and IV1 compared by COND so that they are both compared as
2115 : subregs of the same mode if possible (sometimes it is necessary to add
2116 : some assumptions to DESC). */
2117 :
2118 : static bool
2119 434004 : canonicalize_iv_subregs (class rtx_iv *iv0, class rtx_iv *iv1,
2120 : enum rtx_code cond, class niter_desc *desc)
2121 : {
2122 434004 : scalar_int_mode comp_mode;
2123 434004 : bool signed_p;
2124 :
2125 : /* If the ivs behave specially in the first iteration, or are
2126 : added/multiplied after extending, we ignore them. */
2127 434004 : if (iv0->first_special || iv0->mult != const1_rtx || iv0->delta != const0_rtx)
2128 : return false;
2129 434003 : if (iv1->first_special || iv1->mult != const1_rtx || iv1->delta != const0_rtx)
2130 : return false;
2131 :
2132 : /* If there is some extend, it must match signedness of the comparison. */
2133 434003 : switch (cond)
2134 : {
2135 31467 : case LE:
2136 31467 : case LT:
2137 31467 : if (iv0->extend == IV_ZERO_EXTEND
2138 31467 : || iv1->extend == IV_ZERO_EXTEND)
2139 : return false;
2140 : signed_p = true;
2141 : break;
2142 :
2143 39300 : case LEU:
2144 39300 : case LTU:
2145 39300 : if (iv0->extend == IV_SIGN_EXTEND
2146 39300 : || iv1->extend == IV_SIGN_EXTEND)
2147 : return false;
2148 : signed_p = false;
2149 : break;
2150 :
2151 363236 : case NE:
2152 363236 : if (iv0->extend != IV_UNKNOWN_EXTEND
2153 0 : && iv1->extend != IV_UNKNOWN_EXTEND
2154 0 : && iv0->extend != iv1->extend)
2155 : return false;
2156 :
2157 363236 : signed_p = false;
2158 363236 : if (iv0->extend != IV_UNKNOWN_EXTEND)
2159 0 : signed_p = iv0->extend == IV_SIGN_EXTEND;
2160 363236 : if (iv1->extend != IV_UNKNOWN_EXTEND)
2161 0 : signed_p = iv1->extend == IV_SIGN_EXTEND;
2162 : break;
2163 :
2164 0 : default:
2165 0 : gcc_unreachable ();
2166 : }
2167 :
2168 : /* Values of both variables should be computed in the same mode. These
2169 : might indeed be different, if we have comparison like
2170 :
2171 : (compare (subreg:SI (iv0)) (subreg:SI (iv1)))
2172 :
2173 : and iv0 and iv1 are both ivs iterating in SI mode, but calculated
2174 : in different modes. This does not seem impossible to handle, but
2175 : it hardly ever occurs in practice.
2176 :
2177 : The only exception is the case when one of operands is invariant.
2178 : For example pentium 3 generates comparisons like
2179 : (lt (subreg:HI (reg:SI)) 100). Here we assign HImode to 100, but we
2180 : definitely do not want this prevent the optimization. */
2181 434003 : comp_mode = iv0->extend_mode;
2182 1302009 : if (GET_MODE_BITSIZE (comp_mode) < GET_MODE_BITSIZE (iv1->extend_mode))
2183 434003 : comp_mode = iv1->extend_mode;
2184 :
2185 434003 : if (iv0->extend_mode != comp_mode)
2186 : {
2187 233 : if (iv0->mode != iv0->extend_mode
2188 233 : || iv0->step != const0_rtx)
2189 : return false;
2190 :
2191 233 : iv0->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2192 : comp_mode, iv0->base, iv0->mode);
2193 233 : iv0->extend_mode = comp_mode;
2194 : }
2195 :
2196 434003 : if (iv1->extend_mode != comp_mode)
2197 : {
2198 5680 : if (iv1->mode != iv1->extend_mode
2199 5680 : || iv1->step != const0_rtx)
2200 : return false;
2201 :
2202 5674 : iv1->base = simplify_gen_unary (signed_p ? SIGN_EXTEND : ZERO_EXTEND,
2203 : comp_mode, iv1->base, iv1->mode);
2204 5674 : iv1->extend_mode = comp_mode;
2205 : }
2206 :
2207 : /* Check that both ivs belong to a range of a single mode. If one of the
2208 : operands is an invariant, we may need to shorten it into the common
2209 : mode. */
2210 433997 : if (iv0->mode == iv0->extend_mode
2211 428089 : && iv0->step == const0_rtx
2212 563178 : && iv0->mode != iv1->mode)
2213 0 : shorten_into_mode (iv0, iv1->mode, cond, signed_p, desc);
2214 :
2215 433997 : if (iv1->mode == iv1->extend_mode
2216 428090 : && iv1->step == const0_rtx
2217 736717 : && iv0->mode != iv1->mode)
2218 1 : shorten_into_mode (iv1, iv0->mode, swap_condition (cond), signed_p, desc);
2219 :
2220 433997 : if (iv0->mode != iv1->mode)
2221 : return false;
2222 :
2223 433997 : desc->mode = iv0->mode;
2224 433997 : desc->signed_p = signed_p;
2225 :
2226 433997 : return true;
2227 : }
2228 :
2229 : /* Tries to estimate the maximum number of iterations in LOOP, and return the
2230 : result. This function is called from iv_number_of_iterations with
2231 : a number of fields in DESC already filled in. OLD_NITER is the original
2232 : expression for the number of iterations, before we tried to simplify it. */
2233 :
2234 : static uint64_t
2235 220524 : determine_max_iter (class loop *loop, class niter_desc *desc, rtx old_niter)
2236 : {
2237 220524 : rtx niter = desc->niter_expr;
2238 220524 : rtx mmin, mmax, cmp;
2239 220524 : uint64_t nmax, inc;
2240 220524 : uint64_t andmax = 0;
2241 :
2242 : /* We used to look for constant operand 0 of AND,
2243 : but canonicalization should always make this impossible. */
2244 220524 : gcc_checking_assert (GET_CODE (niter) != AND
2245 : || !CONST_INT_P (XEXP (niter, 0)));
2246 :
2247 220524 : if (GET_CODE (niter) == AND
2248 11155 : && CONST_INT_P (XEXP (niter, 1)))
2249 : {
2250 11155 : andmax = UINTVAL (XEXP (niter, 1));
2251 11155 : niter = XEXP (niter, 0);
2252 : }
2253 :
2254 220524 : get_mode_bounds (desc->mode, desc->signed_p, desc->mode, &mmin, &mmax);
2255 220524 : nmax = UINTVAL (mmax) - UINTVAL (mmin);
2256 :
2257 220524 : if (GET_CODE (niter) == UDIV)
2258 : {
2259 2754 : if (!CONST_INT_P (XEXP (niter, 1)))
2260 : return nmax;
2261 2754 : inc = INTVAL (XEXP (niter, 1));
2262 2754 : niter = XEXP (niter, 0);
2263 : }
2264 : else
2265 : inc = 1;
2266 :
2267 : /* We could use a binary search here, but for now improving the upper
2268 : bound by just one eliminates one important corner case. */
2269 220524 : cmp = simplify_gen_relational (desc->signed_p ? LT : LTU, VOIDmode,
2270 : desc->mode, old_niter, mmax);
2271 220524 : simplify_using_initial_values (loop, UNKNOWN, &cmp);
2272 220524 : if (cmp == const_true_rtx)
2273 : {
2274 127967 : nmax--;
2275 :
2276 127967 : if (dump_file)
2277 15 : fprintf (dump_file, ";; improved upper bound by one.\n");
2278 : }
2279 220524 : nmax /= inc;
2280 220524 : if (andmax)
2281 11155 : nmax = MIN (nmax, andmax);
2282 220524 : if (dump_file)
2283 24 : fprintf (dump_file, ";; Determined upper bound %" PRId64".\n",
2284 : nmax);
2285 : return nmax;
2286 : }
2287 :
2288 : /* Computes number of iterations of the CONDITION in INSN in LOOP and stores
2289 : the result into DESC. Very similar to determine_number_of_iterations
2290 : (basically its rtl version), complicated by things like subregs. */
2291 :
2292 : static void
2293 735923 : iv_number_of_iterations (class loop *loop, rtx_insn *insn, rtx condition,
2294 : class niter_desc *desc)
2295 : {
2296 735923 : rtx op0, op1, delta, step, bound, may_xform, tmp, tmp0, tmp1;
2297 735923 : class rtx_iv iv0, iv1;
2298 735923 : rtx assumption, may_not_xform;
2299 735923 : enum rtx_code cond;
2300 735923 : machine_mode nonvoid_mode;
2301 735923 : scalar_int_mode comp_mode;
2302 735923 : rtx mmin, mmax, mode_mmin, mode_mmax;
2303 735923 : uint64_t s, size, d, inv, max, up, down;
2304 735923 : int64_t inc, step_val;
2305 735923 : int was_sharp = false;
2306 735923 : rtx old_niter;
2307 735923 : bool step_is_pow2;
2308 :
2309 : /* The meaning of these assumptions is this:
2310 : if !assumptions
2311 : then the rest of information does not have to be valid
2312 : if noloop_assumptions then the loop does not roll
2313 : if infinite then this exit is never used */
2314 :
2315 735923 : desc->assumptions = NULL_RTX;
2316 735923 : desc->noloop_assumptions = NULL_RTX;
2317 735923 : desc->infinite = NULL_RTX;
2318 735923 : desc->simple_p = true;
2319 :
2320 735923 : desc->const_iter = false;
2321 735923 : desc->niter_expr = NULL_RTX;
2322 :
2323 735923 : cond = GET_CODE (condition);
2324 735923 : gcc_assert (COMPARISON_P (condition));
2325 :
2326 735923 : nonvoid_mode = GET_MODE (XEXP (condition, 0));
2327 735923 : if (nonvoid_mode == VOIDmode)
2328 0 : nonvoid_mode = GET_MODE (XEXP (condition, 1));
2329 : /* The constant comparisons should be folded. */
2330 735923 : gcc_assert (nonvoid_mode != VOIDmode);
2331 :
2332 : /* We only handle integers or pointers. */
2333 735923 : scalar_int_mode mode;
2334 735923 : if (!is_a <scalar_int_mode> (nonvoid_mode, &mode))
2335 506 : goto fail;
2336 :
2337 735417 : op0 = XEXP (condition, 0);
2338 735417 : if (!iv_analyze (insn, mode, op0, &iv0))
2339 263990 : goto fail;
2340 :
2341 471427 : op1 = XEXP (condition, 1);
2342 471427 : if (!iv_analyze (insn, mode, op1, &iv1))
2343 35234 : goto fail;
2344 :
2345 872126 : if (GET_MODE_BITSIZE (iv0.extend_mode) > HOST_BITS_PER_WIDE_INT
2346 872126 : || GET_MODE_BITSIZE (iv1.extend_mode) > HOST_BITS_PER_WIDE_INT)
2347 264 : goto fail;
2348 :
2349 : /* Check condition and normalize it. */
2350 :
2351 435929 : switch (cond)
2352 : {
2353 29316 : case GE:
2354 29316 : case GT:
2355 29316 : case GEU:
2356 29316 : case GTU:
2357 29316 : std::swap (iv0, iv1);
2358 29316 : cond = swap_condition (cond);
2359 29316 : break;
2360 : case NE:
2361 : case LE:
2362 : case LEU:
2363 : case LT:
2364 : case LTU:
2365 : break;
2366 1925 : default:
2367 1925 : goto fail;
2368 : }
2369 :
2370 : /* Handle extends. This is relatively nontrivial, so we only try in some
2371 : easy cases, when we can canonicalize the ivs (possibly by adding some
2372 : assumptions) to shape subreg (base + i * step). This function also fills
2373 : in desc->mode and desc->signed_p. */
2374 :
2375 434004 : if (!canonicalize_iv_subregs (&iv0, &iv1, cond, desc))
2376 7 : goto fail;
2377 :
2378 433997 : comp_mode = iv0.extend_mode;
2379 433997 : mode = iv0.mode;
2380 433997 : size = GET_MODE_PRECISION (mode);
2381 433997 : get_mode_bounds (mode, (cond == LE || cond == LT), comp_mode, &mmin, &mmax);
2382 433997 : mode_mmin = lowpart_subreg (mode, mmin, comp_mode);
2383 433997 : mode_mmax = lowpart_subreg (mode, mmax, comp_mode);
2384 :
2385 433997 : if (!CONST_INT_P (iv0.step) || !CONST_INT_P (iv1.step))
2386 0 : goto fail;
2387 :
2388 : /* We can take care of the case of two induction variables chasing each other
2389 : if the test is NE. I have never seen a loop using it, but still it is
2390 : cool. */
2391 433997 : if (iv0.step != const0_rtx && iv1.step != const0_rtx)
2392 : {
2393 326 : if (cond != NE)
2394 160 : goto fail;
2395 :
2396 166 : iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
2397 166 : iv1.step = const0_rtx;
2398 : }
2399 :
2400 433837 : iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);
2401 433837 : iv1.step = lowpart_subreg (mode, iv1.step, comp_mode);
2402 :
2403 : /* This is either infinite loop or the one that ends immediately, depending
2404 : on initial values. Unswitching should remove this kind of conditions. */
2405 433837 : if (iv0.step == const0_rtx && iv1.step == const0_rtx)
2406 4274 : goto fail;
2407 :
2408 429563 : if (cond != NE)
2409 : {
2410 67707 : if (iv0.step == const0_rtx)
2411 7979 : step_val = -INTVAL (iv1.step);
2412 : else
2413 59728 : step_val = INTVAL (iv0.step);
2414 :
2415 : /* Ignore loops of while (i-- < 10) type. */
2416 67707 : if (step_val < 0)
2417 2395 : goto fail;
2418 :
2419 65312 : step_is_pow2 = !(step_val & (step_val - 1));
2420 : }
2421 : else
2422 : {
2423 : /* We do not care about whether the step is power of two in this
2424 : case. */
2425 : step_is_pow2 = false;
2426 440030 : step_val = 0;
2427 : }
2428 :
2429 : /* Some more condition normalization. We must record some assumptions
2430 : due to overflows. */
2431 65312 : switch (cond)
2432 : {
2433 52450 : case LT:
2434 52450 : case LTU:
2435 : /* We want to take care only of non-sharp relationals; this is easy,
2436 : as in cases the overflow would make the transformation unsafe
2437 : the loop does not roll. Seemingly it would make more sense to want
2438 : to take care of sharp relationals instead, as NE is more similar to
2439 : them, but the problem is that here the transformation would be more
2440 : difficult due to possibly infinite loops. */
2441 52450 : if (iv0.step == const0_rtx)
2442 : {
2443 5960 : tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2444 5960 : assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
2445 : mode_mmax);
2446 5960 : if (assumption == const_true_rtx)
2447 0 : goto zero_iter_simplify;
2448 5960 : iv0.base = simplify_gen_binary (PLUS, comp_mode,
2449 : iv0.base, const1_rtx);
2450 : }
2451 : else
2452 : {
2453 46490 : tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2454 46490 : assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
2455 : mode_mmin);
2456 46490 : if (assumption == const_true_rtx)
2457 0 : goto zero_iter_simplify;
2458 46490 : iv1.base = simplify_gen_binary (PLUS, comp_mode,
2459 : iv1.base, constm1_rtx);
2460 : }
2461 :
2462 52450 : if (assumption != const0_rtx)
2463 41601 : desc->noloop_assumptions =
2464 41601 : alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2465 52450 : cond = (cond == LT) ? LE : LEU;
2466 :
2467 : /* It will be useful to be able to tell the difference once more in
2468 : LE -> NE reduction. */
2469 : was_sharp = true;
2470 : break;
2471 374718 : default: ;
2472 : }
2473 :
2474 : /* Take care of trivially infinite loops. */
2475 374718 : if (cond != NE)
2476 : {
2477 65312 : if (iv0.step == const0_rtx)
2478 : {
2479 7238 : tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2480 7238 : if (rtx_equal_p (tmp, mode_mmin))
2481 : {
2482 0 : desc->infinite =
2483 0 : alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX);
2484 : /* Fill in the remaining fields somehow. */
2485 0 : goto zero_iter_simplify;
2486 : }
2487 : }
2488 : else
2489 : {
2490 58074 : tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2491 58074 : if (rtx_equal_p (tmp, mode_mmax))
2492 : {
2493 0 : desc->infinite =
2494 0 : alloc_EXPR_LIST (0, const_true_rtx, NULL_RTX);
2495 : /* Fill in the remaining fields somehow. */
2496 0 : goto zero_iter_simplify;
2497 : }
2498 : }
2499 : }
2500 :
2501 : /* If we can we want to take care of NE conditions instead of size
2502 : comparisons, as they are much more friendly (most importantly
2503 : this takes care of special handling of loops with step 1). We can
2504 : do it if we first check that upper bound is greater or equal to
2505 : lower bound, their difference is constant c modulo step and that
2506 : there is not an overflow. */
2507 65312 : if (cond != NE)
2508 : {
2509 65312 : if (iv0.step == const0_rtx)
2510 7238 : step = simplify_gen_unary (NEG, comp_mode, iv1.step, comp_mode);
2511 : else
2512 : step = iv0.step;
2513 65312 : step = lowpart_subreg (mode, step, comp_mode);
2514 65312 : delta = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
2515 65312 : delta = lowpart_subreg (mode, delta, comp_mode);
2516 65312 : delta = simplify_gen_binary (UMOD, mode, delta, step);
2517 65312 : may_xform = const0_rtx;
2518 65312 : may_not_xform = const_true_rtx;
2519 :
2520 65312 : if (CONST_INT_P (delta))
2521 : {
2522 34014 : if (was_sharp && INTVAL (delta) == INTVAL (step) - 1)
2523 : {
2524 : /* A special case. We have transformed condition of type
2525 : for (i = 0; i < 4; i += 4)
2526 : into
2527 : for (i = 0; i <= 3; i += 4)
2528 : obviously if the test for overflow during that transformation
2529 : passed, we cannot overflow here. Most importantly any
2530 : loop with sharp end condition and step 1 falls into this
2531 : category, so handling this case specially is definitely
2532 : worth the troubles. */
2533 : may_xform = const_true_rtx;
2534 : }
2535 8125 : else if (iv0.step == const0_rtx)
2536 : {
2537 657 : bound = simplify_gen_binary (PLUS, comp_mode, mmin, step);
2538 657 : bound = simplify_gen_binary (MINUS, comp_mode, bound, delta);
2539 657 : bound = lowpart_subreg (mode, bound, comp_mode);
2540 657 : tmp = lowpart_subreg (mode, iv0.base, comp_mode);
2541 657 : may_xform = simplify_gen_relational (cond, SImode, mode,
2542 : bound, tmp);
2543 657 : may_not_xform = simplify_gen_relational (reverse_condition (cond),
2544 : SImode, mode,
2545 : bound, tmp);
2546 : }
2547 : else
2548 : {
2549 7468 : bound = simplify_gen_binary (MINUS, comp_mode, mmax, step);
2550 7468 : bound = simplify_gen_binary (PLUS, comp_mode, bound, delta);
2551 7468 : bound = lowpart_subreg (mode, bound, comp_mode);
2552 7468 : tmp = lowpart_subreg (mode, iv1.base, comp_mode);
2553 7468 : may_xform = simplify_gen_relational (cond, SImode, mode,
2554 : tmp, bound);
2555 7468 : may_not_xform = simplify_gen_relational (reverse_condition (cond),
2556 : SImode, mode,
2557 : tmp, bound);
2558 : }
2559 : }
2560 :
2561 65312 : if (may_xform != const0_rtx)
2562 : {
2563 : /* We perform the transformation always provided that it is not
2564 : completely senseless. This is OK, as we would need this assumption
2565 : to determine the number of iterations anyway. */
2566 34014 : if (may_xform != const_true_rtx)
2567 : {
2568 : /* If the step is a power of two and the final value we have
2569 : computed overflows, the cycle is infinite. Otherwise it
2570 : is nontrivial to compute the number of iterations. */
2571 7943 : if (step_is_pow2)
2572 7943 : desc->infinite = alloc_EXPR_LIST (0, may_not_xform,
2573 : desc->infinite);
2574 : else
2575 0 : desc->assumptions = alloc_EXPR_LIST (0, may_xform,
2576 : desc->assumptions);
2577 : }
2578 :
2579 : /* We are going to lose some information about upper bound on
2580 : number of iterations in this step, so record the information
2581 : here. */
2582 34014 : inc = INTVAL (iv0.step) - INTVAL (iv1.step);
2583 34014 : if (CONST_INT_P (iv1.base))
2584 492 : up = INTVAL (iv1.base);
2585 : else
2586 33522 : up = INTVAL (mode_mmax) - inc;
2587 34014 : down = INTVAL (CONST_INT_P (iv0.base)
2588 : ? iv0.base
2589 : : mode_mmin);
2590 34014 : max = (up - down) / inc + 1;
2591 34014 : if (!desc->infinite
2592 26071 : && !desc->assumptions)
2593 26071 : record_niter_bound (loop, max, false, true);
2594 :
2595 34014 : if (iv0.step == const0_rtx)
2596 : {
2597 1560 : iv0.base = simplify_gen_binary (PLUS, comp_mode, iv0.base, delta);
2598 1560 : iv0.base = simplify_gen_binary (MINUS, comp_mode, iv0.base, step);
2599 : }
2600 : else
2601 : {
2602 32454 : iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, delta);
2603 32454 : iv1.base = simplify_gen_binary (PLUS, comp_mode, iv1.base, step);
2604 : }
2605 :
2606 34014 : tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2607 34014 : tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2608 34014 : assumption = simplify_gen_relational (reverse_condition (cond),
2609 : SImode, mode, tmp0, tmp1);
2610 34014 : if (assumption == const_true_rtx)
2611 0 : goto zero_iter_simplify;
2612 34014 : else if (assumption != const0_rtx)
2613 34014 : desc->noloop_assumptions =
2614 34014 : alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2615 : cond = NE;
2616 : }
2617 : }
2618 :
2619 : /* Count the number of iterations. */
2620 31298 : if (cond == NE)
2621 : {
2622 : /* Everything we do here is just arithmetics modulo size of mode. This
2623 : makes us able to do more involved computations of number of iterations
2624 : than in other cases. First transform the condition into shape
2625 : s * i <> c, with s positive. */
2626 395870 : iv1.base = simplify_gen_binary (MINUS, comp_mode, iv1.base, iv0.base);
2627 395870 : iv0.base = const0_rtx;
2628 395870 : iv0.step = simplify_gen_binary (MINUS, comp_mode, iv0.step, iv1.step);
2629 395870 : iv1.step = const0_rtx;
2630 395870 : if (INTVAL (iv0.step) < 0)
2631 : {
2632 138198 : iv0.step = simplify_gen_unary (NEG, comp_mode, iv0.step, comp_mode);
2633 138198 : iv1.base = simplify_gen_unary (NEG, comp_mode, iv1.base, comp_mode);
2634 : }
2635 395870 : iv0.step = lowpart_subreg (mode, iv0.step, comp_mode);
2636 :
2637 : /* Let nsd (s, size of mode) = d. If d does not divide c, the loop
2638 : is infinite. Otherwise, the number of iterations is
2639 : (inverse(s/d) * (c/d)) mod (size of mode/d). */
2640 395870 : s = INTVAL (iv0.step); d = 1;
2641 912125 : while (s % 2 != 1)
2642 : {
2643 516255 : s /= 2;
2644 516255 : d *= 2;
2645 516255 : size--;
2646 : }
2647 395870 : bound = gen_int_mode (((uint64_t) 1 << (size - 1) << 1) - 1, mode);
2648 :
2649 395870 : tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2650 395870 : tmp = simplify_gen_binary (UMOD, mode, tmp1, gen_int_mode (d, mode));
2651 395870 : assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx);
2652 395870 : desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite);
2653 :
2654 395870 : tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode));
2655 395870 : inv = inverse (s, size);
2656 395870 : tmp = simplify_gen_binary (MULT, mode, tmp, gen_int_mode (inv, mode));
2657 395870 : desc->niter_expr = simplify_gen_binary (AND, mode, tmp, bound);
2658 : }
2659 : else
2660 : {
2661 31298 : if (iv1.step == const0_rtx)
2662 : /* Condition in shape a + s * i <= b
2663 : We must know that b + s does not overflow and a <= b + s and then we
2664 : can compute number of iterations as (b + s - a) / s. (It might
2665 : seem that we in fact could be more clever about testing the b + s
2666 : overflow condition using some information about b - a mod s,
2667 : but it was already taken into account during LE -> NE transform). */
2668 : {
2669 25620 : step = iv0.step;
2670 25620 : tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2671 25620 : tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2672 :
2673 25620 : bound = simplify_gen_binary (MINUS, mode, mode_mmax,
2674 : lowpart_subreg (mode, step,
2675 : comp_mode));
2676 25620 : if (step_is_pow2)
2677 : {
2678 23827 : rtx t0, t1;
2679 :
2680 : /* If s is power of 2, we know that the loop is infinite if
2681 : a % s <= b % s and b + s overflows. */
2682 23827 : assumption = simplify_gen_relational (reverse_condition (cond),
2683 : SImode, mode,
2684 : tmp1, bound);
2685 :
2686 23827 : t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
2687 23827 : t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
2688 23827 : tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
2689 23827 : assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
2690 23827 : desc->infinite =
2691 23827 : alloc_EXPR_LIST (0, assumption, desc->infinite);
2692 : }
2693 : else
2694 : {
2695 1793 : assumption = simplify_gen_relational (cond, SImode, mode,
2696 : tmp1, bound);
2697 1793 : desc->assumptions =
2698 1793 : alloc_EXPR_LIST (0, assumption, desc->assumptions);
2699 : }
2700 :
2701 25620 : tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step);
2702 25620 : tmp = lowpart_subreg (mode, tmp, comp_mode);
2703 25620 : assumption = simplify_gen_relational (reverse_condition (cond),
2704 : SImode, mode, tmp0, tmp);
2705 :
2706 25620 : delta = simplify_gen_binary (PLUS, mode, tmp1, step);
2707 25620 : delta = simplify_gen_binary (MINUS, mode, delta, tmp0);
2708 : }
2709 : else
2710 : {
2711 : /* Condition in shape a <= b - s * i
2712 : We must know that a - s does not overflow and a - s <= b and then
2713 : we can again compute number of iterations as (b - (a - s)) / s. */
2714 5678 : step = simplify_gen_unary (NEG, mode, iv1.step, mode);
2715 5678 : tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
2716 5678 : tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
2717 :
2718 5678 : bound = simplify_gen_binary (PLUS, mode, mode_mmin,
2719 : lowpart_subreg (mode, step, comp_mode));
2720 5678 : if (step_is_pow2)
2721 : {
2722 4690 : rtx t0, t1;
2723 :
2724 : /* If s is power of 2, we know that the loop is infinite if
2725 : a % s <= b % s and a - s overflows. */
2726 4690 : assumption = simplify_gen_relational (reverse_condition (cond),
2727 : SImode, mode,
2728 : bound, tmp0);
2729 :
2730 4690 : t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
2731 4690 : t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
2732 4690 : tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
2733 4690 : assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
2734 4690 : desc->infinite =
2735 4690 : alloc_EXPR_LIST (0, assumption, desc->infinite);
2736 : }
2737 : else
2738 : {
2739 988 : assumption = simplify_gen_relational (cond, SImode, mode,
2740 : bound, tmp0);
2741 988 : desc->assumptions =
2742 988 : alloc_EXPR_LIST (0, assumption, desc->assumptions);
2743 : }
2744 :
2745 5678 : tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step);
2746 5678 : tmp = lowpart_subreg (mode, tmp, comp_mode);
2747 5678 : assumption = simplify_gen_relational (reverse_condition (cond),
2748 : SImode, mode,
2749 : tmp, tmp1);
2750 5678 : delta = simplify_gen_binary (MINUS, mode, tmp0, step);
2751 5678 : delta = simplify_gen_binary (MINUS, mode, tmp1, delta);
2752 : }
2753 31298 : if (assumption == const_true_rtx)
2754 0 : goto zero_iter_simplify;
2755 31298 : else if (assumption != const0_rtx)
2756 31114 : desc->noloop_assumptions =
2757 31114 : alloc_EXPR_LIST (0, assumption, desc->noloop_assumptions);
2758 31298 : delta = simplify_gen_binary (UDIV, mode, delta, step);
2759 31298 : desc->niter_expr = delta;
2760 : }
2761 :
2762 427168 : old_niter = desc->niter_expr;
2763 :
2764 427168 : simplify_using_initial_values (loop, AND, &desc->assumptions);
2765 427168 : if (desc->assumptions
2766 2197 : && XEXP (desc->assumptions, 0) == const0_rtx)
2767 24 : goto fail;
2768 427144 : simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
2769 427144 : simplify_using_initial_values (loop, IOR, &desc->infinite);
2770 427144 : simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);
2771 :
2772 : /* Rerun the simplification. Consider code (created by copying loop headers)
2773 :
2774 : i = 0;
2775 :
2776 : if (0 < n)
2777 : {
2778 : do
2779 : {
2780 : i++;
2781 : } while (i < n);
2782 : }
2783 :
2784 : The first pass determines that i = 0, the second pass uses it to eliminate
2785 : noloop assumption. */
2786 :
2787 427144 : simplify_using_initial_values (loop, AND, &desc->assumptions);
2788 427144 : if (desc->assumptions
2789 2173 : && XEXP (desc->assumptions, 0) == const0_rtx)
2790 0 : goto fail;
2791 427144 : simplify_using_initial_values (loop, IOR, &desc->noloop_assumptions);
2792 427144 : simplify_using_initial_values (loop, IOR, &desc->infinite);
2793 427144 : simplify_using_initial_values (loop, UNKNOWN, &desc->niter_expr);
2794 :
2795 427144 : if (desc->noloop_assumptions
2796 53004 : && XEXP (desc->noloop_assumptions, 0) == const_true_rtx)
2797 0 : goto zero_iter;
2798 :
2799 427144 : if (CONST_INT_P (desc->niter_expr))
2800 : {
2801 206620 : uint64_t val = INTVAL (desc->niter_expr);
2802 :
2803 206620 : desc->const_iter = true;
2804 206620 : desc->niter = val & GET_MODE_MASK (desc->mode);
2805 206620 : if (!desc->infinite
2806 206538 : && !desc->assumptions)
2807 206535 : record_niter_bound (loop, desc->niter, false, true);
2808 : }
2809 : else
2810 : {
2811 220524 : max = determine_max_iter (loop, desc, old_niter);
2812 220524 : if (!max)
2813 0 : goto zero_iter_simplify;
2814 220524 : if (!desc->infinite
2815 145565 : && !desc->assumptions)
2816 143395 : record_niter_bound (loop, max, false, true);
2817 :
2818 : /* simplify_using_initial_values does a copy propagation on the registers
2819 : in the expression for the number of iterations. This prolongs life
2820 : ranges of registers and increases register pressure, and usually
2821 : brings no gain (and if it happens to do, the cse pass will take care
2822 : of it anyway). So prevent this behavior, unless it enabled us to
2823 : derive that the number of iterations is a constant. */
2824 220524 : desc->niter_expr = old_niter;
2825 : }
2826 :
2827 : return;
2828 :
2829 0 : zero_iter_simplify:
2830 : /* Simplify the assumptions. */
2831 0 : simplify_using_initial_values (loop, AND, &desc->assumptions);
2832 0 : if (desc->assumptions
2833 0 : && XEXP (desc->assumptions, 0) == const0_rtx)
2834 0 : goto fail;
2835 0 : simplify_using_initial_values (loop, IOR, &desc->infinite);
2836 :
2837 : /* Fallthru. */
2838 0 : zero_iter:
2839 0 : desc->const_iter = true;
2840 0 : desc->niter = 0;
2841 0 : record_niter_bound (loop, 0, true, true);
2842 0 : desc->noloop_assumptions = NULL_RTX;
2843 0 : desc->niter_expr = const0_rtx;
2844 0 : return;
2845 :
2846 308779 : fail:
2847 308779 : desc->simple_p = false;
2848 308779 : return;
2849 : }
2850 :
2851 : /* Checks whether E is a simple exit from LOOP and stores its description
2852 : into DESC. */
2853 :
2854 : static void
2855 1106849 : check_simple_exit (class loop *loop, edge e, class niter_desc *desc)
2856 : {
2857 1106849 : basic_block exit_bb;
2858 1106849 : rtx condition;
2859 1106849 : rtx_insn *at;
2860 1106849 : edge ein;
2861 :
2862 1106849 : exit_bb = e->src;
2863 1106849 : desc->simple_p = false;
2864 :
2865 : /* It must belong directly to the loop. */
2866 1106849 : if (exit_bb->loop_father != loop)
2867 370926 : return;
2868 :
2869 : /* It must be tested (at least) once during any iteration. */
2870 1023900 : if (!dominated_by_p (CDI_DOMINATORS, loop->latch, exit_bb))
2871 : return;
2872 :
2873 : /* It must end in a simple conditional jump. */
2874 830125 : if (!any_condjump_p (BB_END (exit_bb)) || !onlyjump_p (BB_END (exit_bb)))
2875 61244 : return;
2876 :
2877 768881 : ein = EDGE_SUCC (exit_bb, 0);
2878 768881 : if (ein == e)
2879 227458 : ein = EDGE_SUCC (exit_bb, 1);
2880 :
2881 768881 : desc->out_edge = e;
2882 768881 : desc->in_edge = ein;
2883 :
2884 : /* Test whether the condition is suitable. */
2885 768881 : if (!(condition = get_condition (BB_END (ein->src), &at, false, false)))
2886 : return;
2887 :
2888 739512 : if (ein->flags & EDGE_FALLTHRU)
2889 : {
2890 177491 : condition = reversed_condition (condition);
2891 177491 : if (!condition)
2892 : return;
2893 : }
2894 :
2895 : /* Check that we are able to determine number of iterations and fill
2896 : in information about it. */
2897 735923 : iv_number_of_iterations (loop, at, condition, desc);
2898 : }
2899 :
2900 : /* Finds a simple exit of LOOP and stores its description into DESC. */
2901 :
2902 : static void
2903 591598 : find_simple_exit (class loop *loop, class niter_desc *desc)
2904 : {
2905 591598 : unsigned i;
2906 591598 : basic_block *body;
2907 591598 : edge e;
2908 591598 : class niter_desc act;
2909 591598 : bool any = false;
2910 591598 : edge_iterator ei;
2911 :
2912 591598 : desc->simple_p = false;
2913 591598 : body = get_loop_body (loop);
2914 :
2915 4940632 : for (i = 0; i < loop->num_nodes; i++)
2916 : {
2917 9615046 : FOR_EACH_EDGE (e, ei, body[i]->succs)
2918 : {
2919 5857610 : if (flow_bb_inside_loop_p (loop, e->dest))
2920 4750761 : continue;
2921 :
2922 1106849 : check_simple_exit (loop, e, &act);
2923 1106849 : if (!act.simple_p)
2924 679705 : continue;
2925 :
2926 427144 : if (!any)
2927 : any = true;
2928 : else
2929 : {
2930 : /* Prefer constant iterations; the less the better. */
2931 14597 : if (!act.const_iter
2932 930 : || (desc->const_iter && act.niter >= desc->niter))
2933 13820 : continue;
2934 :
2935 : /* Also if the actual exit may be infinite, while the old one
2936 : not, prefer the old one. */
2937 777 : if (act.infinite && !desc->infinite)
2938 14 : continue;
2939 : }
2940 :
2941 413310 : *desc = act;
2942 : }
2943 : }
2944 :
2945 591598 : if (dump_file)
2946 : {
2947 103 : if (desc->simple_p)
2948 : {
2949 75 : fprintf (dump_file, "Loop %d is simple:\n", loop->num);
2950 75 : fprintf (dump_file, " simple exit %d -> %d\n",
2951 75 : desc->out_edge->src->index,
2952 75 : desc->out_edge->dest->index);
2953 75 : if (desc->assumptions)
2954 : {
2955 0 : fprintf (dump_file, " assumptions: ");
2956 0 : print_rtl (dump_file, desc->assumptions);
2957 0 : fprintf (dump_file, "\n");
2958 : }
2959 75 : if (desc->noloop_assumptions)
2960 : {
2961 8 : fprintf (dump_file, " does not roll if: ");
2962 8 : print_rtl (dump_file, desc->noloop_assumptions);
2963 8 : fprintf (dump_file, "\n");
2964 : }
2965 75 : if (desc->infinite)
2966 : {
2967 19 : fprintf (dump_file, " infinite if: ");
2968 19 : print_rtl (dump_file, desc->infinite);
2969 19 : fprintf (dump_file, "\n");
2970 : }
2971 :
2972 75 : fprintf (dump_file, " number of iterations: ");
2973 75 : print_rtl (dump_file, desc->niter_expr);
2974 75 : fprintf (dump_file, "\n");
2975 :
2976 75 : fprintf (dump_file, " upper bound: %li\n",
2977 : (long)get_max_loop_iterations_int (loop));
2978 75 : fprintf (dump_file, " likely upper bound: %li\n",
2979 : (long)get_likely_max_loop_iterations_int (loop));
2980 75 : fprintf (dump_file, " realistic bound: %li\n",
2981 : (long)get_estimated_loop_iterations_int (loop));
2982 : }
2983 : else
2984 28 : fprintf (dump_file, "Loop %d is not simple.\n", loop->num);
2985 : }
2986 :
2987 : /* Fix up the finiteness if possible. We can only do it for single exit,
2988 : since the loop is finite, but it's possible that we predicate one loop
2989 : exit to be finite which can not be determined as finite in middle-end as
2990 : well. It results in incorrect predicate information on the exit condition
2991 : expression. For example, if says [(int) _1 + -8, + , -8] != 0 finite,
2992 : it means _1 can exactly divide -8. */
2993 591598 : if (desc->infinite && single_exit (loop) && finite_loop_p (loop))
2994 : {
2995 35498 : desc->infinite = NULL_RTX;
2996 35498 : if (dump_file)
2997 19 : fprintf (dump_file, " infinite updated to finite.\n");
2998 : }
2999 :
3000 591598 : free (body);
3001 591598 : }
3002 :
3003 : /* Creates a simple loop description of LOOP if it was not computed
3004 : already. */
3005 :
3006 : class niter_desc *
3007 999610 : get_simple_loop_desc (class loop *loop)
3008 : {
3009 999610 : class niter_desc *desc = simple_loop_desc (loop);
3010 :
3011 999610 : if (desc)
3012 : return desc;
3013 :
3014 : /* At least desc->infinite is not always initialized by
3015 : find_simple_loop_exit. */
3016 591598 : desc = ggc_cleared_alloc<niter_desc> ();
3017 591598 : iv_analysis_loop_init (loop);
3018 591598 : find_simple_exit (loop, desc);
3019 591598 : loop->simple_loop_desc = desc;
3020 591598 : return desc;
3021 : }
3022 :
3023 : /* Releases simple loop description for LOOP. */
3024 :
3025 : void
3026 6062401 : free_simple_loop_desc (class loop *loop)
3027 : {
3028 6062401 : class niter_desc *desc = simple_loop_desc (loop);
3029 :
3030 6062401 : if (!desc)
3031 : return;
3032 :
3033 591598 : ggc_free (desc);
3034 591598 : loop->simple_loop_desc = NULL;
3035 : }
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