Line data Source code
1 : /* Decompose multiword subregs.
2 : Copyright (C) 2007-2026 Free Software Foundation, Inc.
3 : Contributed by Richard Henderson <rth@redhat.com>
4 : Ian Lance Taylor <iant@google.com>
5 :
6 : This file is part of GCC.
7 :
8 : GCC is free software; you can redistribute it and/or modify it under
9 : the terms of the GNU General Public License as published by the Free
10 : Software Foundation; either version 3, or (at your option) any later
11 : version.
12 :
13 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 : for more details.
17 :
18 : You should have received a copy of the GNU General Public License
19 : along with GCC; see the file COPYING3. If not see
20 : <http://www.gnu.org/licenses/>. */
21 :
22 : #include "config.h"
23 : #include "system.h"
24 : #include "coretypes.h"
25 : #include "backend.h"
26 : #include "rtl.h"
27 : #include "tree.h"
28 : #include "cfghooks.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "expmed.h"
33 : #include "insn-config.h"
34 : #include "emit-rtl.h"
35 : #include "recog.h"
36 : #include "cfgrtl.h"
37 : #include "cfgbuild.h"
38 : #include "dce.h"
39 : #include "expr.h"
40 : #include "explow.h"
41 : #include "tree-pass.h"
42 : #include "lower-subreg.h"
43 : #include "rtl-iter.h"
44 : #include "target.h"
45 :
46 :
47 : /* Decompose multi-word pseudo-registers into individual
48 : pseudo-registers when possible and profitable. This is possible
49 : when all the uses of a multi-word register are via SUBREG, or are
50 : copies of the register to another location. Breaking apart the
51 : register permits more CSE and permits better register allocation.
52 : This is profitable if the machine does not have move instructions
53 : to do this.
54 :
55 : This pass only splits moves with modes that are wider than
56 : word_mode and ASHIFTs, LSHIFTRTs, ASHIFTRTs and ZERO_EXTENDs with
57 : integer modes that are twice the width of word_mode. The latter
58 : could be generalized if there was a need to do this, but the trend in
59 : architectures is to not need this.
60 :
61 : There are two useful preprocessor defines for use by maintainers:
62 :
63 : #define LOG_COSTS 1
64 :
65 : if you wish to see the actual cost estimates that are being used
66 : for each mode wider than word mode and the cost estimates for zero
67 : extension and the shifts. This can be useful when port maintainers
68 : are tuning insn rtx costs.
69 :
70 : #define FORCE_LOWERING 1
71 :
72 : if you wish to test the pass with all the transformation forced on.
73 : This can be useful for finding bugs in the transformations. */
74 :
75 : #define LOG_COSTS 0
76 : #define FORCE_LOWERING 0
77 :
78 : /* Bit N in this bitmap is set if regno N is used in a context in
79 : which we can decompose it. */
80 : static bitmap decomposable_context;
81 :
82 : /* Bit N in this bitmap is set if regno N is used in a context in
83 : which it cannot be decomposed. */
84 : static bitmap non_decomposable_context;
85 :
86 : /* Bit N in this bitmap is set if regno N is used in a subreg
87 : which changes the mode but not the size. This typically happens
88 : when the register accessed as a floating-point value; we want to
89 : avoid generating accesses to its subwords in integer modes. */
90 : static bitmap subreg_context;
91 :
92 : /* Bit N in the bitmap in element M of this array is set if there is a
93 : copy from reg M to reg N. */
94 : static vec<bitmap> reg_copy_graph;
95 :
96 : struct target_lower_subreg default_target_lower_subreg;
97 : #if SWITCHABLE_TARGET
98 : struct target_lower_subreg *this_target_lower_subreg
99 : = &default_target_lower_subreg;
100 : #endif
101 :
102 : #define twice_word_mode \
103 : this_target_lower_subreg->x_twice_word_mode
104 : #define choices \
105 : this_target_lower_subreg->x_choices
106 :
107 : /* Return true if MODE is a mode we know how to lower. When returning true,
108 : store its byte size in *BYTES and its word size in *WORDS. */
109 :
110 : static inline bool
111 113102747 : interesting_mode_p (machine_mode mode, unsigned int *bytes,
112 : unsigned int *words)
113 : {
114 226205494 : if (!GET_MODE_SIZE (mode).is_constant (bytes))
115 : return false;
116 113102747 : *words = CEIL (*bytes, UNITS_PER_WORD);
117 113102747 : return true;
118 : }
119 :
120 : /* RTXes used while computing costs. */
121 : struct cost_rtxes {
122 : /* Source and target registers. */
123 : rtx source;
124 : rtx target;
125 :
126 : /* A twice_word_mode ZERO_EXTEND of SOURCE. */
127 : rtx zext;
128 :
129 : /* A shift of SOURCE. */
130 : rtx shift;
131 :
132 : /* A SET of TARGET. */
133 : rtx set;
134 : };
135 :
136 : /* Return the cost of a CODE shift in mode MODE by OP1 bits, using the
137 : rtxes in RTXES. SPEED_P selects between the speed and size cost. */
138 :
139 : static int
140 187008448 : shift_cost (bool speed_p, struct cost_rtxes *rtxes, enum rtx_code code,
141 : machine_mode mode, int op1)
142 : {
143 187008448 : PUT_CODE (rtxes->shift, code);
144 187008448 : PUT_MODE (rtxes->shift, mode);
145 187008448 : PUT_MODE (rtxes->source, mode);
146 187008448 : XEXP (rtxes->shift, 1) = gen_int_shift_amount (mode, op1);
147 187008448 : return set_src_cost (rtxes->shift, mode, speed_p);
148 : }
149 :
150 : /* For each X in the range [0, BITS_PER_WORD), set SPLITTING[X]
151 : to true if it is profitable to split a double-word CODE shift
152 : of X + BITS_PER_WORD bits. SPEED_P says whether we are testing
153 : for speed or size profitability.
154 :
155 : Use the rtxes in RTXES to calculate costs. WORD_MOVE_ZERO_COST is
156 : the cost of moving zero into a word-mode register. WORD_MOVE_COST
157 : is the cost of moving between word registers. */
158 :
159 : static void
160 1280640 : compute_splitting_shift (bool speed_p, struct cost_rtxes *rtxes,
161 : bool *splitting, enum rtx_code code,
162 : int word_move_zero_cost, int word_move_cost)
163 : {
164 1280640 : int wide_cost, narrow_cost, upper_cost, i;
165 :
166 83275434 : for (i = 0; i < BITS_PER_WORD; i++)
167 : {
168 80878272 : wide_cost = shift_cost (speed_p, rtxes, code, twice_word_mode,
169 : i + BITS_PER_WORD);
170 80878272 : if (i == 0)
171 : narrow_cost = word_move_cost;
172 : else
173 79597632 : narrow_cost = shift_cost (speed_p, rtxes, code, word_mode, i);
174 :
175 80878272 : if (code != ASHIFTRT)
176 : upper_cost = word_move_zero_cost;
177 27320320 : else if (i == BITS_PER_WORD - 1)
178 : upper_cost = word_move_cost;
179 : else
180 26532544 : upper_cost = shift_cost (speed_p, rtxes, code, word_mode,
181 : BITS_PER_WORD - 1);
182 :
183 80878272 : if (LOG_COSTS)
184 : fprintf (stderr, "%s %s by %d: original cost %d, split cost %d + %d\n",
185 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (code),
186 : i + BITS_PER_WORD, wide_cost, narrow_cost, upper_cost);
187 :
188 80878272 : if (FORCE_LOWERING || wide_cost >= narrow_cost + upper_cost)
189 80878272 : splitting[i] = true;
190 : }
191 1280640 : }
192 :
193 : /* Compute what we should do when optimizing for speed or size; SPEED_P
194 : selects which. Use RTXES for computing costs. */
195 :
196 : static void
197 426880 : compute_costs (bool speed_p, struct cost_rtxes *rtxes)
198 : {
199 426880 : unsigned int i;
200 426880 : int word_move_zero_cost, word_move_cost;
201 :
202 426880 : PUT_MODE (rtxes->target, word_mode);
203 426880 : SET_SRC (rtxes->set) = CONST0_RTX (word_mode);
204 426880 : word_move_zero_cost = set_rtx_cost (rtxes->set, speed_p);
205 :
206 426880 : SET_SRC (rtxes->set) = rtxes->source;
207 426880 : word_move_cost = set_rtx_cost (rtxes->set, speed_p);
208 :
209 426880 : if (LOG_COSTS)
210 : fprintf (stderr, "%s move: from zero cost %d, from reg cost %d\n",
211 : GET_MODE_NAME (word_mode), word_move_zero_cost, word_move_cost);
212 :
213 53360000 : for (i = 0; i < MAX_MACHINE_MODE; i++)
214 : {
215 52933120 : machine_mode mode = (machine_mode) i;
216 52933120 : unsigned int size, factor;
217 52933120 : if (interesting_mode_p (mode, &size, &factor) && factor > 1)
218 : {
219 26658286 : unsigned int mode_move_cost;
220 :
221 26658286 : PUT_MODE (rtxes->target, mode);
222 26658286 : PUT_MODE (rtxes->source, mode);
223 26658286 : mode_move_cost = set_rtx_cost (rtxes->set, speed_p);
224 :
225 26658286 : if (LOG_COSTS)
226 : fprintf (stderr, "%s move: original cost %d, split cost %d * %d\n",
227 : GET_MODE_NAME (mode), mode_move_cost,
228 : word_move_cost, factor);
229 :
230 26658286 : if (FORCE_LOWERING || mode_move_cost >= word_move_cost * factor)
231 : {
232 20350952 : choices[speed_p].move_modes_to_split[i] = true;
233 20350952 : choices[speed_p].something_to_do = true;
234 : }
235 : }
236 : }
237 :
238 : /* For the moves and shifts, the only case that is checked is one
239 : where the mode of the target is an integer mode twice the width
240 : of the word_mode.
241 :
242 : If it is not profitable to split a double word move then do not
243 : even consider the shifts or the zero extension. */
244 426880 : if (choices[speed_p].move_modes_to_split[(int) twice_word_mode])
245 : {
246 426880 : int zext_cost;
247 :
248 : /* The only case here to check to see if moving the upper part with a
249 : zero is cheaper than doing the zext itself. */
250 426880 : PUT_MODE (rtxes->source, word_mode);
251 426880 : zext_cost = set_src_cost (rtxes->zext, twice_word_mode, speed_p);
252 :
253 426880 : if (LOG_COSTS)
254 : fprintf (stderr, "%s %s: original cost %d, split cost %d + %d\n",
255 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (ZERO_EXTEND),
256 : zext_cost, word_move_cost, word_move_zero_cost);
257 :
258 426880 : if (FORCE_LOWERING || zext_cost >= word_move_cost + word_move_zero_cost)
259 0 : choices[speed_p].splitting_zext = true;
260 :
261 426880 : compute_splitting_shift (speed_p, rtxes,
262 426880 : choices[speed_p].splitting_ashift, ASHIFT,
263 : word_move_zero_cost, word_move_cost);
264 426880 : compute_splitting_shift (speed_p, rtxes,
265 426880 : choices[speed_p].splitting_lshiftrt, LSHIFTRT,
266 : word_move_zero_cost, word_move_cost);
267 426880 : compute_splitting_shift (speed_p, rtxes,
268 426880 : choices[speed_p].splitting_ashiftrt, ASHIFTRT,
269 : word_move_zero_cost, word_move_cost);
270 : }
271 426880 : }
272 :
273 : /* Do one-per-target initialisation. This involves determining
274 : which operations on the machine are profitable. If none are found,
275 : then the pass just returns when called. */
276 :
277 : void
278 213440 : init_lower_subreg (void)
279 : {
280 213440 : struct cost_rtxes rtxes;
281 :
282 213440 : memset (this_target_lower_subreg, 0, sizeof (*this_target_lower_subreg));
283 :
284 213440 : twice_word_mode = GET_MODE_2XWIDER_MODE (word_mode).require ();
285 :
286 213440 : rtxes.target = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
287 213440 : rtxes.source = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2);
288 213440 : rtxes.set = gen_rtx_SET (rtxes.target, rtxes.source);
289 213440 : rtxes.zext = gen_rtx_ZERO_EXTEND (twice_word_mode, rtxes.source);
290 213440 : rtxes.shift = gen_rtx_ASHIFT (twice_word_mode, rtxes.source, const0_rtx);
291 :
292 213440 : if (LOG_COSTS)
293 : fprintf (stderr, "\nSize costs\n==========\n\n");
294 213440 : compute_costs (false, &rtxes);
295 :
296 213440 : if (LOG_COSTS)
297 : fprintf (stderr, "\nSpeed costs\n===========\n\n");
298 213440 : compute_costs (true, &rtxes);
299 213440 : }
300 :
301 : static bool
302 80636696 : simple_move_operand (rtx x)
303 : {
304 80636696 : if (GET_CODE (x) == SUBREG)
305 3379420 : x = SUBREG_REG (x);
306 :
307 80636696 : if (!OBJECT_P (x))
308 : return false;
309 :
310 80049001 : if (GET_CODE (x) == LABEL_REF
311 80049001 : || GET_CODE (x) == SYMBOL_REF
312 76967883 : || GET_CODE (x) == HIGH
313 76967883 : || GET_CODE (x) == CONST)
314 : return false;
315 :
316 76856847 : if (MEM_P (x)
317 76856847 : && (MEM_VOLATILE_P (x)
318 21314573 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))))
319 3742864 : return false;
320 :
321 : return true;
322 : }
323 :
324 : /* If X is an operator that can be treated as a simple move that we
325 : can split, then return the operand that is operated on. */
326 :
327 : static rtx
328 43419500 : operand_for_swap_move_operator (rtx x)
329 : {
330 : /* A word sized rotate of a register pair is equivalent to swapping
331 : the registers in the register pair. */
332 43419500 : if (GET_CODE (x) == ROTATE
333 42 : && GET_MODE (x) == twice_word_mode
334 42 : && simple_move_operand (XEXP (x, 0))
335 42 : && CONST_INT_P (XEXP (x, 1))
336 43419574 : && INTVAL (XEXP (x, 1)) == BITS_PER_WORD)
337 42 : return XEXP (x, 0);
338 :
339 : return NULL_RTX;
340 : }
341 :
342 : /* If INSN is a single set between two objects that we want to split,
343 : return the single set. SPEED_P says whether we are optimizing
344 : INSN for speed or size.
345 :
346 : INSN should have been passed to recog and extract_insn before this
347 : is called. */
348 :
349 : static rtx
350 108566598 : simple_move (rtx_insn *insn, bool speed_p)
351 : {
352 108566598 : rtx x, op;
353 108566598 : rtx set;
354 108566598 : machine_mode mode;
355 :
356 108566598 : if (recog_data.n_operands != 2)
357 : return NULL_RTX;
358 :
359 55678077 : set = single_set (insn);
360 55678077 : if (!set)
361 : return NULL_RTX;
362 :
363 52956187 : x = SET_DEST (set);
364 52956187 : if (x != recog_data.operand[0] && x != recog_data.operand[1])
365 : return NULL_RTX;
366 42685693 : if (!simple_move_operand (x))
367 : return NULL_RTX;
368 :
369 39070421 : x = SET_SRC (set);
370 39070421 : if ((op = operand_for_swap_move_operator (x)) != NULL_RTX)
371 21 : x = op;
372 :
373 39070421 : if (x != recog_data.operand[0] && x != recog_data.operand[1])
374 : return NULL_RTX;
375 : /* For the src we can handle ASM_OPERANDS, and it is beneficial for
376 : things like x86 rdtsc which returns a DImode value. */
377 37950961 : if (GET_CODE (x) != ASM_OPERANDS
378 37950961 : && !simple_move_operand (x))
379 : return NULL_RTX;
380 :
381 : /* We try to decompose in integer modes, to avoid generating
382 : inefficient code copying between integer and floating point
383 : registers. That means that we can't decompose if this is a
384 : non-integer mode for which there is no integer mode of the same
385 : size. */
386 34043520 : mode = GET_MODE (SET_DEST (set));
387 34043520 : scalar_int_mode int_mode;
388 34043520 : if (!SCALAR_INT_MODE_P (mode)
389 37973072 : && (!int_mode_for_size (GET_MODE_BITSIZE (mode), 0).exists (&int_mode)
390 3927823 : || !targetm.modes_tieable_p (mode, int_mode)))
391 463445 : return NULL_RTX;
392 :
393 : /* Reject PARTIAL_INT modes. They are used for processor specific
394 : purposes and it's probably best not to tamper with them. */
395 33580075 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
396 : return NULL_RTX;
397 :
398 33580075 : if (!choices[speed_p].move_modes_to_split[(int) mode])
399 : return NULL_RTX;
400 :
401 : return set;
402 : }
403 :
404 : /* If SET is a copy from one multi-word pseudo-register to another,
405 : record that in reg_copy_graph. Return whether it is such a
406 : copy. */
407 :
408 : static bool
409 2782911 : find_pseudo_copy (rtx set)
410 : {
411 2782911 : rtx dest = SET_DEST (set);
412 2782911 : rtx src = SET_SRC (set);
413 2782911 : rtx op;
414 2782911 : unsigned int rd, rs;
415 2782911 : bitmap b;
416 :
417 2782911 : if ((op = operand_for_swap_move_operator (src)) != NULL_RTX)
418 12 : src = op;
419 :
420 2782911 : if (!REG_P (dest) || !REG_P (src))
421 : return false;
422 :
423 441840 : rd = REGNO (dest);
424 441840 : rs = REGNO (src);
425 441840 : if (HARD_REGISTER_NUM_P (rd) || HARD_REGISTER_NUM_P (rs))
426 : return false;
427 :
428 138404 : b = reg_copy_graph[rs];
429 138404 : if (b == NULL)
430 : {
431 135959 : b = BITMAP_ALLOC (NULL);
432 135959 : reg_copy_graph[rs] = b;
433 : }
434 :
435 138404 : bitmap_set_bit (b, rd);
436 :
437 138404 : return true;
438 : }
439 :
440 : /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case
441 : where they are copied to another register, add the register to
442 : which they are copied to DECOMPOSABLE_CONTEXT. Use
443 : NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
444 : copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */
445 :
446 : static void
447 108135 : propagate_pseudo_copies (void)
448 : {
449 108135 : auto_bitmap queue, propagate;
450 :
451 108135 : bitmap_copy (queue, decomposable_context);
452 111468 : do
453 : {
454 111468 : bitmap_iterator iter;
455 111468 : unsigned int i;
456 :
457 111468 : bitmap_clear (propagate);
458 :
459 405978 : EXECUTE_IF_SET_IN_BITMAP (queue, 0, i, iter)
460 : {
461 294510 : bitmap b = reg_copy_graph[i];
462 294510 : if (b)
463 6679 : bitmap_ior_and_compl_into (propagate, b, non_decomposable_context);
464 : }
465 :
466 111468 : bitmap_and_compl (queue, propagate, decomposable_context);
467 111468 : bitmap_ior_into (decomposable_context, propagate);
468 : }
469 111468 : while (!bitmap_empty_p (queue));
470 108135 : }
471 :
472 : /* A pointer to one of these values is passed to
473 : find_decomposable_subregs. */
474 :
475 : enum classify_move_insn
476 : {
477 : /* Not a simple move from one location to another. */
478 : NOT_SIMPLE_MOVE,
479 : /* A simple move we want to decompose. */
480 : DECOMPOSABLE_SIMPLE_MOVE,
481 : /* Any other simple move. */
482 : SIMPLE_MOVE
483 : };
484 :
485 : /* If we find a SUBREG in *LOC which we could use to decompose a
486 : pseudo-register, set a bit in DECOMPOSABLE_CONTEXT. If we find an
487 : unadorned register which is not a simple pseudo-register copy,
488 : DATA will point at the type of move, and we set a bit in
489 : DECOMPOSABLE_CONTEXT or NON_DECOMPOSABLE_CONTEXT as appropriate. */
490 :
491 : static void
492 123817599 : find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
493 : {
494 123817599 : subrtx_var_iterator::array_type array;
495 280960016 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
496 : {
497 157142417 : rtx x = *iter;
498 157142417 : if (GET_CODE (x) == SUBREG)
499 : {
500 2940273 : rtx inner = SUBREG_REG (x);
501 2940273 : unsigned int regno, outer_size, inner_size, outer_words, inner_words;
502 :
503 2940273 : if (!REG_P (inner))
504 1785723 : continue;
505 :
506 2940270 : regno = REGNO (inner);
507 2940270 : if (HARD_REGISTER_NUM_P (regno))
508 : {
509 2 : iter.skip_subrtxes ();
510 2 : continue;
511 : }
512 :
513 2940268 : if (!interesting_mode_p (GET_MODE (x), &outer_size, &outer_words)
514 2940268 : || !interesting_mode_p (GET_MODE (inner), &inner_size,
515 : &inner_words))
516 : continue;
517 :
518 : /* We only try to decompose single word subregs of multi-word
519 : registers. When we find one, we return -1 to avoid iterating
520 : over the inner register.
521 :
522 : ??? This doesn't allow, e.g., DImode subregs of TImode values
523 : on 32-bit targets. We would need to record the way the
524 : pseudo-register was used, and only decompose if all the uses
525 : were the same number and size of pieces. Hopefully this
526 : doesn't happen much. */
527 :
528 2940268 : if (outer_words == 1
529 2069616 : && inner_words > 1
530 : /* Don't allow to decompose floating point subregs of
531 : multi-word pseudos if the floating point mode does
532 : not have word size, because otherwise we'd generate
533 : a subreg with that floating mode from a different
534 : sized integral pseudo which is not allowed by
535 : validate_subreg. */
536 1783975 : && (!FLOAT_MODE_P (GET_MODE (x))
537 8680 : || outer_size == UNITS_PER_WORD))
538 : {
539 1783694 : bitmap_set_bit (decomposable_context, regno);
540 1783694 : iter.skip_subrtxes ();
541 1783694 : continue;
542 : }
543 :
544 : /* If this is a cast from one mode to another, where the modes
545 : have the same size, and they are not tieable, then mark this
546 : register as non-decomposable. If we decompose it we are
547 : likely to mess up whatever the backend is trying to do. */
548 1158598 : if (outer_words > 1
549 870652 : && outer_size == inner_size
550 1340049 : && !targetm.modes_tieable_p (GET_MODE (x), GET_MODE (inner)))
551 : {
552 2024 : bitmap_set_bit (non_decomposable_context, regno);
553 2024 : bitmap_set_bit (subreg_context, regno);
554 2024 : iter.skip_subrtxes ();
555 2024 : continue;
556 : }
557 : }
558 154202144 : else if (REG_P (x))
559 : {
560 77941248 : unsigned int regno, size, words;
561 :
562 : /* We will see an outer SUBREG before we see the inner REG, so
563 : when we see a plain REG here it means a direct reference to
564 : the register.
565 :
566 : If this is not a simple copy from one location to another,
567 : then we cannot decompose this register. If this is a simple
568 : copy we want to decompose, and the mode is right,
569 : then we mark the register as decomposable.
570 : Otherwise we don't say anything about this register --
571 : it could be decomposed, but whether that would be
572 : profitable depends upon how it is used elsewhere.
573 :
574 : We only set bits in the bitmap for multi-word
575 : pseudo-registers, since those are the only ones we care about
576 : and it keeps the size of the bitmaps down. */
577 :
578 77941248 : regno = REGNO (x);
579 77941248 : if (!HARD_REGISTER_NUM_P (regno)
580 49243489 : && interesting_mode_p (GET_MODE (x), &size, &words)
581 127184737 : && words > 1)
582 : {
583 8569955 : switch (*pcmi)
584 : {
585 5696042 : case NOT_SIMPLE_MOVE:
586 5696042 : bitmap_set_bit (non_decomposable_context, regno);
587 5696042 : break;
588 18796 : case DECOMPOSABLE_SIMPLE_MOVE:
589 18796 : if (targetm.modes_tieable_p (GET_MODE (x), word_mode))
590 0 : bitmap_set_bit (decomposable_context, regno);
591 : break;
592 : case SIMPLE_MOVE:
593 : break;
594 0 : default:
595 0 : gcc_unreachable ();
596 : }
597 : }
598 : }
599 76260896 : else if (MEM_P (x))
600 : {
601 16260092 : enum classify_move_insn cmi_mem = NOT_SIMPLE_MOVE;
602 :
603 : /* Any registers used in a MEM do not participate in a
604 : SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE. Do our own recursion
605 : here, and return -1 to block the parent's recursion. */
606 16260092 : find_decomposable_subregs (&XEXP (x, 0), &cmi_mem);
607 16260092 : iter.skip_subrtxes ();
608 : }
609 : }
610 123817599 : }
611 :
612 : /* Decompose REGNO into word-sized components. We smash the REG node
613 : in place. This ensures that (1) something goes wrong quickly if we
614 : fail to make some replacement, and (2) the debug information inside
615 : the symbol table is automatically kept up to date. */
616 :
617 : static void
618 294510 : decompose_register (unsigned int regno)
619 : {
620 294510 : rtx reg;
621 294510 : unsigned int size, words, i;
622 294510 : rtvec v;
623 :
624 294510 : reg = regno_reg_rtx[regno];
625 :
626 294510 : regno_reg_rtx[regno] = NULL_RTX;
627 :
628 294510 : if (!interesting_mode_p (GET_MODE (reg), &size, &words))
629 : gcc_unreachable ();
630 :
631 294510 : v = rtvec_alloc (words);
632 1192828 : for (i = 0; i < words; ++i)
633 766390 : RTVEC_ELT (v, i) = gen_reg_rtx_offset (reg, word_mode, i * UNITS_PER_WORD);
634 :
635 294510 : PUT_CODE (reg, CONCATN);
636 294510 : XVEC (reg, 0) = v;
637 :
638 294510 : if (dump_file)
639 : {
640 0 : fprintf (dump_file, "; Splitting reg %u ->", regno);
641 0 : for (i = 0; i < words; ++i)
642 0 : fprintf (dump_file, " %u", REGNO (XVECEXP (reg, 0, i)));
643 0 : fputc ('\n', dump_file);
644 : }
645 294510 : }
646 :
647 : /* Get a SUBREG of a CONCATN. */
648 :
649 : static rtx
650 1511813 : simplify_subreg_concatn (machine_mode outermode, rtx op, poly_uint64 orig_byte)
651 : {
652 1511813 : unsigned int outer_size, outer_words, inner_size, inner_words;
653 1511813 : machine_mode innermode, partmode;
654 1511813 : rtx part;
655 1511813 : unsigned int final_offset;
656 1511813 : unsigned int byte;
657 :
658 1511813 : innermode = GET_MODE (op);
659 1511813 : if (!interesting_mode_p (outermode, &outer_size, &outer_words)
660 1511813 : || !interesting_mode_p (innermode, &inner_size, &inner_words))
661 : gcc_unreachable ();
662 :
663 : /* Must be constant if interesting_mode_p passes. */
664 1511813 : byte = orig_byte.to_constant ();
665 1511813 : gcc_assert (GET_CODE (op) == CONCATN);
666 1511813 : gcc_assert (byte % outer_size == 0);
667 :
668 1511813 : gcc_assert (byte < inner_size);
669 1511813 : if (outer_size > inner_size)
670 : return NULL_RTX;
671 :
672 1511813 : inner_size /= XVECLEN (op, 0);
673 1511813 : part = XVECEXP (op, 0, byte / inner_size);
674 1511813 : partmode = GET_MODE (part);
675 :
676 1511813 : final_offset = byte % inner_size;
677 1511813 : if (final_offset + outer_size > inner_size)
678 : return NULL_RTX;
679 :
680 : /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
681 : regular CONST_VECTORs. They have vector or integer modes, depending
682 : on the capabilities of the target. Cope with them. */
683 1511802 : if (partmode == VOIDmode && VECTOR_MODE_P (innermode))
684 0 : partmode = GET_MODE_INNER (innermode);
685 0 : else if (partmode == VOIDmode)
686 0 : partmode = mode_for_size (inner_size * BITS_PER_UNIT,
687 0 : GET_MODE_CLASS (innermode), 0).require ();
688 :
689 1511802 : return simplify_gen_subreg (outermode, part, partmode, final_offset);
690 : }
691 :
692 : /* Wrapper around simplify_gen_subreg which handles CONCATN. */
693 :
694 : static rtx
695 1158159 : simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
696 : machine_mode innermode, unsigned int byte)
697 : {
698 1158475 : rtx ret;
699 :
700 : /* We have to handle generating a SUBREG of a SUBREG of a CONCATN.
701 : If OP is a SUBREG of a CONCATN, then it must be a simple mode
702 : change with the same size and offset 0, or it must extract a
703 : part. We shouldn't see anything else here. */
704 1158475 : if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
705 : {
706 320 : rtx op2;
707 :
708 640 : if (known_eq (GET_MODE_SIZE (GET_MODE (op)),
709 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
710 320 : && known_eq (SUBREG_BYTE (op), 0))
711 : return simplify_gen_subreg_concatn (outermode, SUBREG_REG (op),
712 : GET_MODE (SUBREG_REG (op)), byte);
713 :
714 8 : op2 = simplify_subreg_concatn (GET_MODE (op), SUBREG_REG (op),
715 4 : SUBREG_BYTE (op));
716 4 : if (op2 == NULL_RTX)
717 : {
718 : /* We don't handle paradoxical subregs here. */
719 4 : gcc_assert (!paradoxical_subreg_p (outermode, GET_MODE (op)));
720 4 : gcc_assert (!paradoxical_subreg_p (op));
721 8 : op2 = simplify_subreg_concatn (outermode, SUBREG_REG (op),
722 4 : byte + SUBREG_BYTE (op));
723 4 : gcc_assert (op2 != NULL_RTX);
724 : return op2;
725 : }
726 :
727 0 : op = op2;
728 0 : gcc_assert (op != NULL_RTX);
729 0 : gcc_assert (innermode == GET_MODE (op));
730 : }
731 :
732 1158155 : if (GET_CODE (op) == CONCATN)
733 649546 : return simplify_subreg_concatn (outermode, op, byte);
734 :
735 508609 : ret = simplify_gen_subreg (outermode, op, innermode, byte);
736 :
737 : /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
738 : resolve_simple_move will ask for the high part of the paradoxical
739 : subreg, which does not have a value. Just return a zero. */
740 508609 : if (ret == NULL_RTX
741 508610 : && paradoxical_subreg_p (op))
742 1 : return CONST0_RTX (outermode);
743 :
744 508608 : gcc_assert (ret != NULL_RTX);
745 : return ret;
746 : }
747 :
748 : /* Return whether we should resolve X into the registers into which it
749 : was decomposed. */
750 :
751 : static bool
752 40930760 : resolve_reg_p (rtx x)
753 : {
754 40930760 : return GET_CODE (x) == CONCATN;
755 : }
756 :
757 : /* Return whether X is a SUBREG of a register which we need to
758 : resolve. */
759 :
760 : static bool
761 109489300 : resolve_subreg_p (rtx x)
762 : {
763 2937870 : if (GET_CODE (x) != SUBREG)
764 : return false;
765 0 : return resolve_reg_p (SUBREG_REG (x));
766 : }
767 :
768 : /* Look for SUBREGs in *LOC which need to be decomposed. */
769 :
770 : static bool
771 51592900 : resolve_subreg_use (rtx *loc, rtx insn)
772 : {
773 51592900 : subrtx_ptr_iterator::array_type array;
774 127550960 : FOR_EACH_SUBRTX_PTR (iter, array, loc, NONCONST)
775 : {
776 75960145 : rtx *loc = *iter;
777 75960145 : rtx x = *loc;
778 75960145 : if (resolve_subreg_p (x))
779 : {
780 1569274 : x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x),
781 784637 : SUBREG_BYTE (x));
782 :
783 : /* It is possible for a note to contain a reference which we can
784 : decompose. In this case, return 1 to the caller to indicate
785 : that the note must be removed. */
786 784637 : if (!x)
787 : {
788 3 : gcc_assert (!insn);
789 2085 : return true;
790 : }
791 :
792 784634 : validate_change (insn, loc, x, 1);
793 784634 : iter.skip_subrtxes ();
794 : }
795 75175508 : else if (resolve_reg_p (x))
796 : /* Return 1 to the caller to indicate that we found a direct
797 : reference to a register which is being decomposed. This can
798 : happen inside notes, multiword shift or zero-extend
799 : instructions. */
800 : return true;
801 : }
802 :
803 51590815 : return false;
804 51592900 : }
805 :
806 : /* Resolve any decomposed registers which appear in register notes on
807 : INSN. */
808 :
809 : static void
810 35807706 : resolve_reg_notes (rtx_insn *insn)
811 : {
812 35807706 : rtx *pnote, note;
813 :
814 35807706 : note = find_reg_equal_equiv_note (insn);
815 35807706 : if (note)
816 : {
817 543324 : int old_count = num_validated_changes ();
818 543324 : if (resolve_subreg_use (&XEXP (note, 0), NULL_RTX))
819 2085 : remove_note (insn, note);
820 : else
821 541239 : if (old_count != num_validated_changes ())
822 3060 : df_notes_rescan (insn);
823 : }
824 :
825 35807706 : pnote = ®_NOTES (insn);
826 47526035 : while (*pnote != NULL_RTX)
827 : {
828 11718329 : bool del = false;
829 :
830 11718329 : note = *pnote;
831 11718329 : switch (REG_NOTE_KIND (note))
832 : {
833 4064907 : case REG_DEAD:
834 4064907 : case REG_UNUSED:
835 4064907 : if (resolve_reg_p (XEXP (note, 0)))
836 7880 : del = true;
837 : break;
838 :
839 : default:
840 : break;
841 : }
842 :
843 7880 : if (del)
844 7880 : *pnote = XEXP (note, 1);
845 : else
846 11710449 : pnote = &XEXP (note, 1);
847 : }
848 35807706 : }
849 :
850 : /* Return whether X can be decomposed into subwords. */
851 :
852 : static bool
853 486224 : can_decompose_p (rtx x)
854 : {
855 486224 : if (REG_P (x))
856 : {
857 141570 : unsigned int regno = REGNO (x);
858 :
859 141570 : if (HARD_REGISTER_NUM_P (regno))
860 : {
861 94041 : unsigned int byte, num_bytes, num_words;
862 :
863 94041 : if (!interesting_mode_p (GET_MODE (x), &num_bytes, &num_words))
864 : return false;
865 290596 : for (byte = 0; byte < num_bytes; byte += UNITS_PER_WORD)
866 188082 : if (simplify_subreg_regno (regno, GET_MODE (x), byte, word_mode) < 0)
867 : return false;
868 : return true;
869 : }
870 : else
871 47529 : return !bitmap_bit_p (subreg_context, regno);
872 : }
873 :
874 : return true;
875 : }
876 :
877 : /* OPND is a concatn operand this is used with a simple move operator.
878 : Return a new rtx with the concatn's operands swapped. */
879 :
880 : static rtx
881 1 : resolve_operand_for_swap_move_operator (rtx opnd)
882 : {
883 1 : gcc_assert (GET_CODE (opnd) == CONCATN);
884 1 : rtx concatn = copy_rtx (opnd);
885 1 : rtx op0 = XVECEXP (concatn, 0, 0);
886 1 : rtx op1 = XVECEXP (concatn, 0, 1);
887 1 : XVECEXP (concatn, 0, 0) = op1;
888 1 : XVECEXP (concatn, 0, 1) = op0;
889 1 : return concatn;
890 : }
891 :
892 : /* Decompose the registers used in a simple move SET within INSN. If
893 : we don't change anything, return INSN, otherwise return the start
894 : of the sequence of moves. */
895 :
896 : static rtx_insn *
897 1566168 : resolve_simple_move (rtx set, rtx_insn *insn)
898 : {
899 1566168 : rtx src, dest, real_dest, src_op;
900 1566168 : rtx_insn *insns;
901 1566168 : machine_mode orig_mode, dest_mode;
902 1566168 : unsigned int orig_size, words;
903 1566168 : bool pushing;
904 :
905 1566168 : src = SET_SRC (set);
906 1566168 : dest = SET_DEST (set);
907 1566168 : orig_mode = GET_MODE (dest);
908 :
909 1566168 : if (!interesting_mode_p (orig_mode, &orig_size, &words))
910 : gcc_unreachable ();
911 1566168 : gcc_assert (words > 1);
912 :
913 1566168 : start_sequence ();
914 :
915 : /* We have to handle copying from a SUBREG of a decomposed reg where
916 : the SUBREG is larger than word size. Rather than assume that we
917 : can take a word_mode SUBREG of the destination, we copy to a new
918 : register and then copy that to the destination. */
919 :
920 1566168 : real_dest = NULL_RTX;
921 :
922 1566168 : if ((src_op = operand_for_swap_move_operator (src)) != NULL_RTX)
923 : {
924 9 : if (resolve_reg_p (dest))
925 : {
926 : /* DEST is a CONCATN, so swap its operands and strip
927 : SRC's operator. */
928 1 : dest = resolve_operand_for_swap_move_operator (dest);
929 1 : src = src_op;
930 1 : if (resolve_reg_p (src))
931 : {
932 1 : gcc_assert (GET_CODE (src) == CONCATN);
933 1 : if (reg_overlap_mentioned_p (XVECEXP (dest, 0, 0),
934 1 : XVECEXP (src, 0, 1)))
935 : {
936 : /* If there is overlap between the first half of the
937 : destination and what will be stored to the second one,
938 : use a temporary pseudo. See PR114211. */
939 1 : rtx tem = gen_reg_rtx (GET_MODE (XVECEXP (src, 0, 1)));
940 1 : emit_move_insn (tem, XVECEXP (src, 0, 1));
941 1 : src = copy_rtx (src);
942 1 : XVECEXP (src, 0, 1) = tem;
943 : }
944 : }
945 : }
946 8 : else if (resolve_reg_p (src_op))
947 : {
948 : /* SRC is an operation on a CONCATN, so strip the operator and
949 : swap the CONCATN's operands. */
950 0 : src = resolve_operand_for_swap_move_operator (src_op);
951 : }
952 : }
953 :
954 1566168 : if (GET_CODE (src) == SUBREG
955 10771 : && resolve_reg_p (SUBREG_REG (src))
956 1566260 : && (maybe_ne (SUBREG_BYTE (src), 0)
957 182 : || maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
958 : {
959 2 : real_dest = dest;
960 2 : dest = gen_reg_rtx (orig_mode);
961 2 : if (REG_P (real_dest))
962 2 : REG_ATTRS (dest) = REG_ATTRS (real_dest);
963 : }
964 :
965 : /* Similarly if we are copying to a SUBREG of a decomposed reg where
966 : the SUBREG is larger than word size. */
967 :
968 1566168 : if (GET_CODE (dest) == SUBREG
969 899 : && resolve_reg_p (SUBREG_REG (dest))
970 1566235 : && (maybe_ne (SUBREG_BYTE (dest), 0)
971 67 : || maybe_ne (orig_size,
972 134 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))))
973 : {
974 0 : rtx reg, smove;
975 0 : rtx_insn *minsn;
976 :
977 0 : reg = gen_reg_rtx (orig_mode);
978 0 : minsn = emit_move_insn (reg, src);
979 0 : smove = single_set (minsn);
980 0 : gcc_assert (smove != NULL_RTX);
981 0 : resolve_simple_move (smove, minsn);
982 0 : src = reg;
983 : }
984 :
985 : /* If we didn't have any big SUBREGS of decomposed registers, and
986 : neither side of the move is a register we are decomposing, then
987 : we don't have to do anything here. */
988 :
989 1566168 : if (src == SET_SRC (set)
990 1566167 : && dest == SET_DEST (set)
991 1566165 : && !resolve_reg_p (src)
992 10769 : && !resolve_subreg_p (src)
993 1523726 : && !resolve_reg_p (dest)
994 1567062 : && !resolve_subreg_p (dest))
995 : {
996 1323056 : end_sequence ();
997 1323056 : return insn;
998 : }
999 :
1000 : /* It's possible for the code to use a subreg of a decomposed
1001 : register while forming an address. We need to handle that before
1002 : passing the address to emit_move_insn. We pass NULL_RTX as the
1003 : insn parameter to resolve_subreg_use because we cannot validate
1004 : the insn yet. */
1005 243112 : if (MEM_P (src) || MEM_P (dest))
1006 : {
1007 68424 : int acg;
1008 :
1009 68424 : if (MEM_P (src))
1010 51200 : resolve_subreg_use (&XEXP (src, 0), NULL_RTX);
1011 68424 : if (MEM_P (dest))
1012 17224 : resolve_subreg_use (&XEXP (dest, 0), NULL_RTX);
1013 68424 : acg = apply_change_group ();
1014 68424 : gcc_assert (acg);
1015 : }
1016 :
1017 : /* If SRC is a register which we can't decompose, or has side
1018 : effects, we need to move via a temporary register. */
1019 :
1020 243112 : if (!can_decompose_p (src)
1021 242949 : || side_effects_p (src)
1022 486061 : || GET_CODE (src) == ASM_OPERANDS)
1023 : {
1024 163 : rtx reg;
1025 :
1026 163 : reg = gen_reg_rtx (orig_mode);
1027 :
1028 163 : if (AUTO_INC_DEC)
1029 : {
1030 : rtx_insn *move = emit_move_insn (reg, src);
1031 : if (MEM_P (src))
1032 : {
1033 : rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
1034 : if (note)
1035 : add_reg_note (move, REG_INC, XEXP (note, 0));
1036 : }
1037 : }
1038 : else
1039 163 : emit_move_insn (reg, src);
1040 :
1041 163 : src = reg;
1042 : }
1043 :
1044 : /* If DEST is a register which we can't decompose, or has side
1045 : effects, we need to first move to a temporary register. We
1046 : handle the common case of pushing an operand directly. We also
1047 : go through a temporary register if it holds a floating point
1048 : value. This gives us better code on systems which can't move
1049 : data easily between integer and floating point registers. */
1050 :
1051 243112 : dest_mode = orig_mode;
1052 243112 : pushing = push_operand (dest, dest_mode);
1053 243112 : if (!can_decompose_p (dest)
1054 243106 : || (side_effects_p (dest) && !pushing)
1055 486218 : || (!SCALAR_INT_MODE_P (dest_mode)
1056 0 : && !resolve_reg_p (dest)
1057 0 : && !resolve_subreg_p (dest)))
1058 : {
1059 6 : if (real_dest == NULL_RTX)
1060 6 : real_dest = dest;
1061 6 : if (!SCALAR_INT_MODE_P (dest_mode))
1062 0 : dest_mode = int_mode_for_mode (dest_mode).require ();
1063 6 : dest = gen_reg_rtx (dest_mode);
1064 6 : if (REG_P (real_dest))
1065 6 : REG_ATTRS (dest) = REG_ATTRS (real_dest);
1066 : }
1067 :
1068 243112 : if (pushing)
1069 : {
1070 0 : unsigned int i, j, jinc;
1071 :
1072 0 : gcc_assert (orig_size % UNITS_PER_WORD == 0);
1073 0 : gcc_assert (GET_CODE (XEXP (dest, 0)) != PRE_MODIFY);
1074 0 : gcc_assert (GET_CODE (XEXP (dest, 0)) != POST_MODIFY);
1075 :
1076 0 : if (WORDS_BIG_ENDIAN == STACK_GROWS_DOWNWARD)
1077 : {
1078 : j = 0;
1079 : jinc = 1;
1080 : }
1081 : else
1082 : {
1083 0 : j = words - 1;
1084 0 : jinc = -1;
1085 : }
1086 :
1087 0 : for (i = 0; i < words; ++i, j += jinc)
1088 : {
1089 0 : rtx temp;
1090 :
1091 0 : temp = copy_rtx (XEXP (dest, 0));
1092 0 : temp = adjust_automodify_address_nv (dest, word_mode, temp,
1093 : j * UNITS_PER_WORD);
1094 0 : emit_move_insn (temp,
1095 : simplify_gen_subreg_concatn (word_mode, src,
1096 : orig_mode,
1097 0 : j * UNITS_PER_WORD));
1098 : }
1099 : }
1100 : else
1101 : {
1102 243112 : unsigned int i;
1103 :
1104 243112 : if (REG_P (dest) && !HARD_REGISTER_NUM_P (REGNO (dest)))
1105 1969 : emit_clobber (dest);
1106 :
1107 752218 : for (i = 0; i < words; ++i)
1108 : {
1109 509106 : rtx t = simplify_gen_subreg_concatn (word_mode, dest,
1110 : dest_mode,
1111 509106 : i * UNITS_PER_WORD);
1112 : /* simplify_gen_subreg_concatn can return (const_int 0) for
1113 : some sub-objects of paradoxical subregs. As a source operand,
1114 : that's fine. As a destination it must be avoided. Those are
1115 : supposed to be don't care bits, so we can just drop that store
1116 : on the floor. */
1117 509106 : if (t != CONST0_RTX (word_mode))
1118 509106 : emit_move_insn (t,
1119 : simplify_gen_subreg_concatn (word_mode, src,
1120 : orig_mode,
1121 509106 : i * UNITS_PER_WORD));
1122 : }
1123 : }
1124 :
1125 243112 : if (real_dest != NULL_RTX)
1126 : {
1127 8 : rtx mdest, smove;
1128 8 : rtx_insn *minsn;
1129 :
1130 8 : if (dest_mode == orig_mode)
1131 : mdest = dest;
1132 : else
1133 0 : mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0);
1134 8 : minsn = emit_move_insn (real_dest, mdest);
1135 :
1136 8 : if (AUTO_INC_DEC && MEM_P (real_dest)
1137 : && !(resolve_reg_p (real_dest) || resolve_subreg_p (real_dest)))
1138 : {
1139 : rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
1140 : if (note)
1141 : add_reg_note (minsn, REG_INC, XEXP (note, 0));
1142 : }
1143 :
1144 8 : smove = single_set (minsn);
1145 8 : gcc_assert (smove != NULL_RTX);
1146 :
1147 8 : resolve_simple_move (smove, minsn);
1148 : }
1149 :
1150 243112 : insns = end_sequence ();
1151 :
1152 243112 : copy_reg_eh_region_note_forward (insn, insns, NULL_RTX);
1153 :
1154 243112 : emit_insn_before (insns, insn);
1155 :
1156 : /* If we get here via self-recursion, then INSN is not yet in the insns
1157 : chain and delete_insn will fail. We only want to remove INSN from the
1158 : current sequence. See PR56738. */
1159 243112 : if (in_sequence_p ())
1160 0 : remove_insn (insn);
1161 : else
1162 243112 : delete_insn (insn);
1163 :
1164 : return insns;
1165 : }
1166 :
1167 : /* Change a CLOBBER of a decomposed register into a CLOBBER of the
1168 : component registers. Return whether we changed something. */
1169 :
1170 : static bool
1171 143313 : resolve_clobber (rtx pat, rtx_insn *insn)
1172 : {
1173 143313 : rtx reg;
1174 143313 : machine_mode orig_mode;
1175 143313 : unsigned int orig_size, words, i;
1176 143313 : int ret;
1177 :
1178 143313 : reg = XEXP (pat, 0);
1179 : /* For clobbers we can look through paradoxical subregs which
1180 : we do not handle in simplify_gen_subreg_concatn. */
1181 143313 : if (paradoxical_subreg_p (reg))
1182 143313 : reg = SUBREG_REG (reg);
1183 143313 : if (!resolve_reg_p (reg) && !resolve_subreg_p (reg))
1184 : return false;
1185 :
1186 52377 : orig_mode = GET_MODE (reg);
1187 52377 : if (!interesting_mode_p (orig_mode, &orig_size, &words))
1188 : gcc_unreachable ();
1189 :
1190 52377 : ret = validate_change (NULL_RTX, &XEXP (pat, 0),
1191 : simplify_gen_subreg_concatn (word_mode, reg,
1192 : orig_mode, 0),
1193 : 0);
1194 52377 : df_insn_rescan (insn);
1195 52377 : gcc_assert (ret != 0);
1196 :
1197 104754 : for (i = words - 1; i > 0; --i)
1198 : {
1199 52377 : rtx x;
1200 :
1201 52377 : x = simplify_gen_subreg_concatn (word_mode, reg, orig_mode,
1202 52377 : i * UNITS_PER_WORD);
1203 52377 : x = gen_rtx_CLOBBER (VOIDmode, x);
1204 52377 : emit_insn_after (x, insn);
1205 : }
1206 :
1207 52377 : resolve_reg_notes (insn);
1208 :
1209 52377 : return true;
1210 : }
1211 :
1212 : /* A USE of a decomposed register is no longer meaningful. Return
1213 : whether we changed something. */
1214 :
1215 : static bool
1216 63040 : resolve_use (rtx pat, rtx_insn *insn)
1217 : {
1218 63040 : if (resolve_reg_p (XEXP (pat, 0)) || resolve_subreg_p (XEXP (pat, 0)))
1219 : {
1220 0 : delete_insn (insn);
1221 0 : return true;
1222 : }
1223 :
1224 63040 : resolve_reg_notes (insn);
1225 :
1226 63040 : return false;
1227 : }
1228 :
1229 : /* A VAR_LOCATION can be simplified. */
1230 :
1231 : static void
1232 12482118 : resolve_debug (rtx_insn *insn)
1233 : {
1234 12482118 : subrtx_ptr_iterator::array_type array;
1235 43010363 : FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), NONCONST)
1236 : {
1237 30528245 : rtx *loc = *iter;
1238 30528245 : rtx x = *loc;
1239 30528245 : if (resolve_subreg_p (x))
1240 : {
1241 155244 : x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x),
1242 77622 : SUBREG_BYTE (x));
1243 :
1244 77622 : if (x)
1245 77618 : *loc = x;
1246 : else
1247 4 : x = copy_rtx (*loc);
1248 : }
1249 30528245 : if (resolve_reg_p (x))
1250 31962 : *loc = copy_rtx (x);
1251 : }
1252 :
1253 12482118 : df_insn_rescan (insn);
1254 :
1255 12482118 : resolve_reg_notes (insn);
1256 12482118 : }
1257 :
1258 : /* Check if INSN is a decomposable multiword-shift or zero-extend and
1259 : set the decomposable_context bitmap accordingly. SPEED_P is true
1260 : if we are optimizing INSN for speed rather than size. Return true
1261 : if INSN is decomposable. */
1262 :
1263 : static bool
1264 85392513 : find_decomposable_shift_zext (rtx_insn *insn, bool speed_p)
1265 : {
1266 85392513 : rtx set;
1267 85392513 : rtx op;
1268 85392513 : rtx op_operand;
1269 :
1270 85392513 : set = single_set (insn);
1271 85392513 : if (!set)
1272 : return false;
1273 :
1274 46636445 : op = SET_SRC (set);
1275 46636445 : if (GET_CODE (op) != ASHIFT
1276 : && GET_CODE (op) != LSHIFTRT
1277 : && GET_CODE (op) != ASHIFTRT
1278 : && GET_CODE (op) != ZERO_EXTEND)
1279 : return false;
1280 :
1281 935782 : op_operand = XEXP (op, 0);
1282 921106 : if (!REG_P (SET_DEST (set)) || !REG_P (op_operand)
1283 814902 : || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set)))
1284 814679 : || HARD_REGISTER_NUM_P (REGNO (op_operand))
1285 1750457 : || GET_MODE (op) != twice_word_mode)
1286 : return false;
1287 :
1288 127614 : if (GET_CODE (op) == ZERO_EXTEND)
1289 : {
1290 62104 : if (GET_MODE (op_operand) != word_mode
1291 62104 : || !choices[speed_p].splitting_zext)
1292 : return false;
1293 : }
1294 : else /* left or right shift */
1295 : {
1296 65510 : bool *splitting = (GET_CODE (op) == ASHIFT
1297 17548 : ? choices[speed_p].splitting_ashift
1298 : : GET_CODE (op) == ASHIFTRT
1299 9289 : ? choices[speed_p].splitting_ashiftrt
1300 38673 : : choices[speed_p].splitting_lshiftrt);
1301 65510 : if (!CONST_INT_P (XEXP (op, 1))
1302 122872 : || !IN_RANGE (INTVAL (XEXP (op, 1)), BITS_PER_WORD,
1303 : 2 * BITS_PER_WORD - 1)
1304 57976 : || !splitting[INTVAL (XEXP (op, 1)) - BITS_PER_WORD])
1305 : return false;
1306 :
1307 36086 : bitmap_set_bit (decomposable_context, REGNO (op_operand));
1308 : }
1309 :
1310 36086 : bitmap_set_bit (decomposable_context, REGNO (SET_DEST (set)));
1311 :
1312 36086 : return true;
1313 : }
1314 :
1315 : /* Decompose a more than word wide shift (in INSN) of a multiword
1316 : pseudo or a multiword zero-extend of a wordmode pseudo into a move
1317 : and 'set to zero' insn. SPEED_P says whether we are optimizing
1318 : for speed or size, when checking if a ZERO_EXTEND is preferable.
1319 : Return a pointer to the new insn when a replacement was done. */
1320 :
1321 : static rtx_insn *
1322 21644011 : resolve_shift_zext (rtx_insn *insn, bool speed_p)
1323 : {
1324 21644011 : rtx set;
1325 21644011 : rtx op;
1326 21644011 : rtx op_operand;
1327 21644011 : rtx_insn *insns;
1328 21644011 : rtx src_reg, dest_reg, dest_upper, upper_src = NULL_RTX;
1329 21644011 : int src_reg_num, dest_reg_num, offset1, offset2, src_offset;
1330 21644011 : scalar_int_mode inner_mode;
1331 :
1332 21644011 : set = single_set (insn);
1333 21644011 : if (!set)
1334 : return NULL;
1335 :
1336 20493945 : op = SET_SRC (set);
1337 20493945 : if (GET_CODE (op) != ASHIFT
1338 : && GET_CODE (op) != LSHIFTRT
1339 : && GET_CODE (op) != ASHIFTRT
1340 : && GET_CODE (op) != ZERO_EXTEND)
1341 : return NULL;
1342 :
1343 440333 : op_operand = XEXP (op, 0);
1344 440333 : if (!is_a <scalar_int_mode> (GET_MODE (op_operand), &inner_mode))
1345 : return NULL;
1346 :
1347 : /* We can tear this operation apart only if the regs were already
1348 : torn apart. */
1349 408485 : if (!resolve_reg_p (SET_DEST (set)) && !resolve_reg_p (op_operand))
1350 : return NULL;
1351 :
1352 : /* src_reg_num is the number of the word mode register which we
1353 : are operating on. For a left shift and a zero_extend on little
1354 : endian machines this is register 0. */
1355 204 : src_reg_num = (GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ASHIFTRT)
1356 11731 : ? 1 : 0;
1357 :
1358 11731 : if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
1359 : src_reg_num = 1 - src_reg_num;
1360 :
1361 11731 : if (GET_CODE (op) == ZERO_EXTEND)
1362 : dest_reg_num = WORDS_BIG_ENDIAN ? 1 : 0;
1363 : else
1364 11731 : dest_reg_num = 1 - src_reg_num;
1365 :
1366 11731 : offset1 = UNITS_PER_WORD * dest_reg_num;
1367 11731 : offset2 = UNITS_PER_WORD * (1 - dest_reg_num);
1368 11731 : src_offset = UNITS_PER_WORD * src_reg_num;
1369 :
1370 11731 : start_sequence ();
1371 :
1372 23462 : dest_reg = simplify_gen_subreg_concatn (word_mode, SET_DEST (set),
1373 11731 : GET_MODE (SET_DEST (set)),
1374 : offset1);
1375 23462 : dest_upper = simplify_gen_subreg_concatn (word_mode, SET_DEST (set),
1376 11731 : GET_MODE (SET_DEST (set)),
1377 : offset2);
1378 23462 : src_reg = simplify_gen_subreg_concatn (word_mode, op_operand,
1379 11731 : GET_MODE (op_operand),
1380 : src_offset);
1381 11731 : if (GET_CODE (op) == ASHIFTRT
1382 3224 : && INTVAL (XEXP (op, 1)) != 2 * BITS_PER_WORD - 1)
1383 3142 : upper_src = expand_shift (RSHIFT_EXPR, word_mode, copy_rtx (src_reg),
1384 3180 : BITS_PER_WORD - 1, NULL_RTX, 0);
1385 :
1386 11731 : if (GET_CODE (op) != ZERO_EXTEND)
1387 : {
1388 11731 : int shift_count = INTVAL (XEXP (op, 1));
1389 15674 : if (shift_count > BITS_PER_WORD)
1390 2937 : src_reg = expand_shift (GET_CODE (op) == ASHIFT ?
1391 : LSHIFT_EXPR : RSHIFT_EXPR,
1392 : word_mode, src_reg,
1393 2937 : shift_count - BITS_PER_WORD,
1394 : dest_reg, GET_CODE (op) != ASHIFTRT);
1395 : }
1396 :
1397 : /* Consider using ZERO_EXTEND instead of setting DEST_UPPER to zero
1398 : if this is considered reasonable. */
1399 11731 : if (GET_CODE (op) == LSHIFTRT
1400 8349 : && GET_MODE (op) == twice_word_mode
1401 8349 : && REG_P (SET_DEST (set))
1402 11905 : && !choices[speed_p].splitting_zext)
1403 : {
1404 174 : rtx tmp = force_reg (word_mode, copy_rtx (src_reg));
1405 174 : tmp = simplify_gen_unary (ZERO_EXTEND, twice_word_mode, tmp, word_mode);
1406 174 : emit_move_insn (SET_DEST (set), tmp);
1407 : }
1408 : else
1409 : {
1410 11557 : if (dest_reg != src_reg)
1411 8666 : emit_move_insn (dest_reg, src_reg);
1412 11557 : if (GET_CODE (op) != ASHIFTRT)
1413 8379 : emit_move_insn (dest_upper, CONST0_RTX (word_mode));
1414 3224 : else if (INTVAL (XEXP (op, 1)) == 2 * BITS_PER_WORD - 1)
1415 36 : emit_move_insn (dest_upper, copy_rtx (src_reg));
1416 : else
1417 3142 : emit_move_insn (dest_upper, upper_src);
1418 : }
1419 :
1420 11731 : insns = end_sequence ();
1421 :
1422 11731 : emit_insn_before (insns, insn);
1423 :
1424 11731 : if (dump_file)
1425 : {
1426 0 : rtx_insn *in;
1427 0 : fprintf (dump_file, "; Replacing insn: %d with insns: ", INSN_UID (insn));
1428 0 : for (in = insns; in != insn; in = NEXT_INSN (in))
1429 0 : fprintf (dump_file, "%d ", INSN_UID (in));
1430 0 : fprintf (dump_file, "\n");
1431 : }
1432 :
1433 11731 : delete_insn (insn);
1434 11731 : return insns;
1435 : }
1436 :
1437 : /* Print to dump_file a description of what we're doing with shift code CODE.
1438 : SPLITTING[X] is true if we are splitting shifts by X + BITS_PER_WORD. */
1439 :
1440 : static void
1441 360 : dump_shift_choices (enum rtx_code code, bool *splitting)
1442 : {
1443 360 : int i;
1444 360 : const char *sep;
1445 :
1446 360 : fprintf (dump_file,
1447 : " Splitting mode %s for %s lowering with shift amounts = ",
1448 360 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (code));
1449 360 : sep = "";
1450 23760 : for (i = 0; i < BITS_PER_WORD; i++)
1451 23040 : if (splitting[i])
1452 : {
1453 23040 : fprintf (dump_file, "%s%d", sep, i + BITS_PER_WORD);
1454 23040 : sep = ",";
1455 : }
1456 360 : fprintf (dump_file, "\n");
1457 360 : }
1458 :
1459 : /* Print to dump_file a description of what we're doing when optimizing
1460 : for speed or size; SPEED_P says which. DESCRIPTION is a description
1461 : of the SPEED_P choice. */
1462 :
1463 : static void
1464 120 : dump_choices (bool speed_p, const char *description)
1465 : {
1466 120 : unsigned int size, factor, i;
1467 :
1468 120 : fprintf (dump_file, "Choices when optimizing for %s:\n", description);
1469 :
1470 15120 : for (i = 0; i < MAX_MACHINE_MODE; i++)
1471 14880 : if (interesting_mode_p ((machine_mode) i, &size, &factor)
1472 14880 : && factor > 1)
1473 7440 : fprintf (dump_file, " %s mode %s for copy lowering.\n",
1474 7440 : choices[speed_p].move_modes_to_split[i]
1475 : ? "Splitting"
1476 : : "Skipping",
1477 7440 : GET_MODE_NAME ((machine_mode) i));
1478 :
1479 120 : fprintf (dump_file, " %s mode %s for zero_extend lowering.\n",
1480 120 : choices[speed_p].splitting_zext ? "Splitting" : "Skipping",
1481 120 : GET_MODE_NAME (twice_word_mode));
1482 :
1483 120 : dump_shift_choices (ASHIFT, choices[speed_p].splitting_ashift);
1484 120 : dump_shift_choices (LSHIFTRT, choices[speed_p].splitting_lshiftrt);
1485 120 : dump_shift_choices (ASHIFTRT, choices[speed_p].splitting_ashiftrt);
1486 120 : fprintf (dump_file, "\n");
1487 120 : }
1488 :
1489 : /* Look for registers which are always accessed via word-sized SUBREGs
1490 : or -if DECOMPOSE_COPIES is true- via copies. Decompose these
1491 : registers into several word-sized pseudo-registers. */
1492 :
1493 : static void
1494 2087297 : decompose_multiword_subregs (bool decompose_copies)
1495 : {
1496 2087297 : unsigned int max;
1497 2087297 : basic_block bb;
1498 2087297 : bool speed_p;
1499 :
1500 2087297 : if (dump_file)
1501 : {
1502 60 : dump_choices (false, "size");
1503 60 : dump_choices (true, "speed");
1504 : }
1505 :
1506 : /* Check if this target even has any modes to consider lowering. */
1507 2087297 : if (!choices[false].something_to_do && !choices[true].something_to_do)
1508 : {
1509 0 : if (dump_file)
1510 0 : fprintf (dump_file, "Nothing to do!\n");
1511 0 : return;
1512 : }
1513 :
1514 2087297 : max = max_reg_num ();
1515 :
1516 : /* First see if there are any multi-word pseudo-registers. If there
1517 : aren't, there is nothing we can do. This should speed up this
1518 : pass in the normal case, since it should be faster than scanning
1519 : all the insns. */
1520 2087297 : {
1521 2087297 : unsigned int i;
1522 2087297 : bool useful_modes_seen = false;
1523 :
1524 77963837 : for (i = FIRST_PSEUDO_REGISTER; i < max; ++i)
1525 76207180 : if (regno_reg_rtx[i] != NULL)
1526 : {
1527 76113587 : machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1528 76113587 : if (choices[false].move_modes_to_split[(int) mode]
1529 75782947 : || choices[true].move_modes_to_split[(int) mode])
1530 : {
1531 : useful_modes_seen = true;
1532 : break;
1533 : }
1534 : }
1535 :
1536 2087297 : if (!useful_modes_seen)
1537 : {
1538 1756657 : if (dump_file)
1539 60 : fprintf (dump_file, "Nothing to lower in this function.\n");
1540 1756657 : return;
1541 : }
1542 : }
1543 :
1544 330640 : if (df)
1545 : {
1546 146645 : df_set_flags (DF_DEFER_INSN_RESCAN);
1547 146645 : run_word_dce ();
1548 : }
1549 :
1550 : /* FIXME: It may be possible to change this code to look for each
1551 : multi-word pseudo-register and to find each insn which sets or
1552 : uses that register. That should be faster than scanning all the
1553 : insns. */
1554 :
1555 330640 : decomposable_context = BITMAP_ALLOC (NULL);
1556 330640 : non_decomposable_context = BITMAP_ALLOC (NULL);
1557 330640 : subreg_context = BITMAP_ALLOC (NULL);
1558 :
1559 330640 : reg_copy_graph.create (max);
1560 330640 : reg_copy_graph.safe_grow_cleared (max, true);
1561 330640 : memset (reg_copy_graph.address (), 0, sizeof (bitmap) * max);
1562 :
1563 330640 : speed_p = optimize_function_for_speed_p (cfun);
1564 8532672 : FOR_EACH_BB_FN (bb, cfun)
1565 : {
1566 8202032 : rtx_insn *insn;
1567 :
1568 107835448 : FOR_BB_INSNS (bb, insn)
1569 : {
1570 99633416 : rtx set;
1571 99633416 : enum classify_move_insn cmi;
1572 99633416 : int i, n;
1573 :
1574 113874319 : if (!INSN_P (insn)
1575 85717871 : || GET_CODE (PATTERN (insn)) == CLOBBER
1576 185221773 : || GET_CODE (PATTERN (insn)) == USE)
1577 14276989 : continue;
1578 :
1579 85392513 : recog_memoized (insn);
1580 :
1581 85392513 : if (find_decomposable_shift_zext (insn, speed_p))
1582 36086 : continue;
1583 :
1584 85356427 : extract_insn (insn);
1585 :
1586 85356427 : set = simple_move (insn, speed_p);
1587 :
1588 85356427 : if (!set)
1589 82573516 : cmi = NOT_SIMPLE_MOVE;
1590 : else
1591 : {
1592 : /* We mark pseudo-to-pseudo copies as decomposable during the
1593 : second pass only. The first pass is so early that there is
1594 : good chance such moves will be optimized away completely by
1595 : subsequent optimizations anyway.
1596 :
1597 : However, we call find_pseudo_copy even during the first pass
1598 : so as to properly set up the reg_copy_graph. */
1599 2782911 : if (find_pseudo_copy (set))
1600 267410 : cmi = decompose_copies? DECOMPOSABLE_SIMPLE_MOVE : SIMPLE_MOVE;
1601 : else
1602 2644507 : cmi = SIMPLE_MOVE;
1603 : }
1604 :
1605 85356427 : n = recog_data.n_operands;
1606 192913934 : for (i = 0; i < n; ++i)
1607 : {
1608 107557507 : find_decomposable_subregs (&recog_data.operand[i], &cmi);
1609 :
1610 : /* We handle ASM_OPERANDS as a special case to support
1611 : things like x86 rdtsc which returns a DImode value.
1612 : We can decompose the output, which will certainly be
1613 : operand 0, but not the inputs. */
1614 :
1615 107557507 : if (cmi == SIMPLE_MOVE
1616 5547026 : && GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1617 : {
1618 0 : gcc_assert (i == 0);
1619 0 : cmi = NOT_SIMPLE_MOVE;
1620 : }
1621 : }
1622 : }
1623 : }
1624 :
1625 330640 : bitmap_and_compl_into (decomposable_context, non_decomposable_context);
1626 330640 : if (!bitmap_empty_p (decomposable_context))
1627 : {
1628 108135 : unsigned int i;
1629 108135 : sbitmap_iterator sbi;
1630 108135 : bitmap_iterator iter;
1631 108135 : unsigned int regno;
1632 :
1633 108135 : propagate_pseudo_copies ();
1634 :
1635 108135 : auto_sbitmap sub_blocks (last_basic_block_for_fn (cfun));
1636 108135 : bitmap_clear (sub_blocks);
1637 :
1638 402645 : EXECUTE_IF_SET_IN_BITMAP (decomposable_context, 0, regno, iter)
1639 294510 : decompose_register (regno);
1640 :
1641 3946082 : FOR_EACH_BB_FN (bb, cfun)
1642 : {
1643 3837947 : rtx_insn *insn;
1644 :
1645 45942907 : FOR_BB_INSNS (bb, insn)
1646 : {
1647 42104960 : rtx pat;
1648 :
1649 42104960 : if (!INSN_P (insn))
1650 6206318 : continue;
1651 :
1652 35898642 : pat = PATTERN (insn);
1653 35898642 : if (GET_CODE (pat) == CLOBBER)
1654 143313 : resolve_clobber (pat, insn);
1655 35755329 : else if (GET_CODE (pat) == USE)
1656 63040 : resolve_use (pat, insn);
1657 35692289 : else if (DEBUG_INSN_P (insn))
1658 12482118 : resolve_debug (insn);
1659 : else
1660 : {
1661 23210171 : rtx set;
1662 23210171 : int i;
1663 :
1664 23210171 : recog_memoized (insn);
1665 23210171 : extract_insn (insn);
1666 :
1667 23210171 : set = simple_move (insn, speed_p);
1668 23210171 : if (set)
1669 : {
1670 1566160 : rtx_insn *orig_insn = insn;
1671 1566160 : bool cfi = control_flow_insn_p (insn);
1672 :
1673 : /* We can end up splitting loads to multi-word pseudos
1674 : into separate loads to machine word size pseudos.
1675 : When this happens, we first had one load that can
1676 : throw, and after resolve_simple_move we'll have a
1677 : bunch of loads (at least two). All those loads may
1678 : trap if we can have non-call exceptions, so they
1679 : all will end the current basic block. We split the
1680 : block after the outer loop over all insns, but we
1681 : make sure here that we will be able to split the
1682 : basic block and still produce the correct control
1683 : flow graph for it. */
1684 1566160 : gcc_assert (!cfi
1685 : || (cfun->can_throw_non_call_exceptions
1686 : && can_throw_internal (insn)));
1687 :
1688 1566160 : insn = resolve_simple_move (set, insn);
1689 1566160 : if (insn != orig_insn)
1690 : {
1691 243112 : recog_memoized (insn);
1692 243112 : extract_insn (insn);
1693 :
1694 243112 : if (cfi)
1695 6272 : bitmap_set_bit (sub_blocks, bb->index);
1696 : }
1697 : }
1698 : else
1699 : {
1700 21644011 : rtx_insn *decomposed_shift;
1701 :
1702 21644011 : decomposed_shift = resolve_shift_zext (insn, speed_p);
1703 21644011 : if (decomposed_shift != NULL_RTX)
1704 : {
1705 11731 : insn = decomposed_shift;
1706 11731 : recog_memoized (insn);
1707 11731 : extract_insn (insn);
1708 : }
1709 : }
1710 :
1711 74191323 : for (i = recog_data.n_operands - 1; i >= 0; --i)
1712 50981152 : resolve_subreg_use (recog_data.operand_loc[i], insn);
1713 :
1714 23210171 : resolve_reg_notes (insn);
1715 :
1716 23210171 : if (num_validated_changes () > 0)
1717 : {
1718 773915 : for (i = recog_data.n_dups - 1; i >= 0; --i)
1719 : {
1720 11618 : rtx *pl = recog_data.dup_loc[i];
1721 11618 : int dup_num = recog_data.dup_num[i];
1722 11618 : rtx *px = recog_data.operand_loc[dup_num];
1723 :
1724 11618 : validate_unshare_change (insn, pl, *px, 1);
1725 : }
1726 :
1727 762297 : i = apply_change_group ();
1728 762297 : gcc_assert (i);
1729 : }
1730 : }
1731 : }
1732 : }
1733 :
1734 : /* If we had insns to split that caused control flow insns in the middle
1735 : of a basic block, split those blocks now. Note that we only handle
1736 : the case where splitting a load has caused multiple possibly trapping
1737 : loads to appear. */
1738 222542 : EXECUTE_IF_SET_IN_BITMAP (sub_blocks, 0, i, sbi)
1739 : {
1740 6272 : rtx_insn *insn, *end;
1741 6272 : edge fallthru;
1742 :
1743 6272 : bb = BASIC_BLOCK_FOR_FN (cfun, i);
1744 6272 : insn = BB_HEAD (bb);
1745 6272 : end = BB_END (bb);
1746 :
1747 36493 : while (insn != end)
1748 : {
1749 30221 : if (control_flow_insn_p (insn))
1750 : {
1751 : /* Split the block after insn. There will be a fallthru
1752 : edge, which is OK so we keep it. We have to create the
1753 : exception edges ourselves. */
1754 6388 : fallthru = split_block (bb, insn);
1755 6388 : rtl_make_eh_edge (NULL, bb, BB_END (bb));
1756 6388 : bb = fallthru->dest;
1757 6388 : insn = BB_HEAD (bb);
1758 : }
1759 : else
1760 23833 : insn = NEXT_INSN (insn);
1761 : }
1762 : }
1763 108135 : }
1764 :
1765 62013062 : for (bitmap b : reg_copy_graph)
1766 61021142 : if (b)
1767 135959 : BITMAP_FREE (b);
1768 :
1769 330640 : reg_copy_graph.release ();
1770 :
1771 330640 : BITMAP_FREE (decomposable_context);
1772 330640 : BITMAP_FREE (non_decomposable_context);
1773 330640 : BITMAP_FREE (subreg_context);
1774 : }
1775 :
1776 : /* Implement first lower subreg pass. */
1777 :
1778 : namespace {
1779 :
1780 : const pass_data pass_data_lower_subreg =
1781 : {
1782 : RTL_PASS, /* type */
1783 : "subreg1", /* name */
1784 : OPTGROUP_NONE, /* optinfo_flags */
1785 : TV_LOWER_SUBREG, /* tv_id */
1786 : 0, /* properties_required */
1787 : 0, /* properties_provided */
1788 : 0, /* properties_destroyed */
1789 : 0, /* todo_flags_start */
1790 : 0, /* todo_flags_finish */
1791 : };
1792 :
1793 : class pass_lower_subreg : public rtl_opt_pass
1794 : {
1795 : public:
1796 285722 : pass_lower_subreg (gcc::context *ctxt)
1797 571444 : : rtl_opt_pass (pass_data_lower_subreg, ctxt)
1798 : {}
1799 :
1800 : /* opt_pass methods: */
1801 1471370 : bool gate (function *) final override { return flag_split_wide_types != 0; }
1802 1043648 : unsigned int execute (function *) final override
1803 : {
1804 1043648 : decompose_multiword_subregs (false);
1805 1043648 : return 0;
1806 : }
1807 :
1808 : }; // class pass_lower_subreg
1809 :
1810 : } // anon namespace
1811 :
1812 : rtl_opt_pass *
1813 285722 : make_pass_lower_subreg (gcc::context *ctxt)
1814 : {
1815 285722 : return new pass_lower_subreg (ctxt);
1816 : }
1817 :
1818 : /* Implement second lower subreg pass. */
1819 :
1820 : namespace {
1821 :
1822 : const pass_data pass_data_lower_subreg2 =
1823 : {
1824 : RTL_PASS, /* type */
1825 : "subreg2", /* name */
1826 : OPTGROUP_NONE, /* optinfo_flags */
1827 : TV_LOWER_SUBREG, /* tv_id */
1828 : 0, /* properties_required */
1829 : 0, /* properties_provided */
1830 : 0, /* properties_destroyed */
1831 : 0, /* todo_flags_start */
1832 : TODO_df_finish, /* todo_flags_finish */
1833 : };
1834 :
1835 : class pass_lower_subreg2 : public rtl_opt_pass
1836 : {
1837 : public:
1838 285722 : pass_lower_subreg2 (gcc::context *ctxt)
1839 571444 : : rtl_opt_pass (pass_data_lower_subreg2, ctxt)
1840 : {}
1841 :
1842 : /* opt_pass methods: */
1843 1471370 : bool gate (function *) final override
1844 : {
1845 1471370 : return flag_split_wide_types && flag_split_wide_types_early;
1846 : }
1847 0 : unsigned int execute (function *) final override
1848 : {
1849 0 : decompose_multiword_subregs (true);
1850 0 : return 0;
1851 : }
1852 :
1853 : }; // class pass_lower_subreg2
1854 :
1855 : } // anon namespace
1856 :
1857 : rtl_opt_pass *
1858 285722 : make_pass_lower_subreg2 (gcc::context *ctxt)
1859 : {
1860 285722 : return new pass_lower_subreg2 (ctxt);
1861 : }
1862 :
1863 : /* Implement third lower subreg pass. */
1864 :
1865 : namespace {
1866 :
1867 : const pass_data pass_data_lower_subreg3 =
1868 : {
1869 : RTL_PASS, /* type */
1870 : "subreg3", /* name */
1871 : OPTGROUP_NONE, /* optinfo_flags */
1872 : TV_LOWER_SUBREG, /* tv_id */
1873 : 0, /* properties_required */
1874 : 0, /* properties_provided */
1875 : 0, /* properties_destroyed */
1876 : 0, /* todo_flags_start */
1877 : TODO_df_finish, /* todo_flags_finish */
1878 : };
1879 :
1880 : class pass_lower_subreg3 : public rtl_opt_pass
1881 : {
1882 : public:
1883 285722 : pass_lower_subreg3 (gcc::context *ctxt)
1884 571444 : : rtl_opt_pass (pass_data_lower_subreg3, ctxt)
1885 : {}
1886 :
1887 : /* opt_pass methods: */
1888 1471370 : bool gate (function *) final override { return flag_split_wide_types; }
1889 1043649 : unsigned int execute (function *) final override
1890 : {
1891 1043649 : decompose_multiword_subregs (true);
1892 1043649 : return 0;
1893 : }
1894 :
1895 : }; // class pass_lower_subreg3
1896 :
1897 : } // anon namespace
1898 :
1899 : rtl_opt_pass *
1900 285722 : make_pass_lower_subreg3 (gcc::context *ctxt)
1901 : {
1902 285722 : return new pass_lower_subreg3 (ctxt);
1903 : }
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