Line data Source code
1 : /* Decompose multiword subregs.
2 : Copyright (C) 2007-2026 Free Software Foundation, Inc.
3 : Contributed by Richard Henderson <rth@redhat.com>
4 : Ian Lance Taylor <iant@google.com>
5 :
6 : This file is part of GCC.
7 :
8 : GCC is free software; you can redistribute it and/or modify it under
9 : the terms of the GNU General Public License as published by the Free
10 : Software Foundation; either version 3, or (at your option) any later
11 : version.
12 :
13 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 : for more details.
17 :
18 : You should have received a copy of the GNU General Public License
19 : along with GCC; see the file COPYING3. If not see
20 : <http://www.gnu.org/licenses/>. */
21 :
22 : #include "config.h"
23 : #include "system.h"
24 : #include "coretypes.h"
25 : #include "backend.h"
26 : #include "rtl.h"
27 : #include "tree.h"
28 : #include "cfghooks.h"
29 : #include "df.h"
30 : #include "memmodel.h"
31 : #include "tm_p.h"
32 : #include "expmed.h"
33 : #include "regs.h"
34 : #include "insn-config.h"
35 : #include "emit-rtl.h"
36 : #include "recog.h"
37 : #include "cfgrtl.h"
38 : #include "cfgbuild.h"
39 : #include "dce.h"
40 : #include "expr.h"
41 : #include "explow.h"
42 : #include "tree-pass.h"
43 : #include "lower-subreg.h"
44 : #include "rtl-iter.h"
45 : #include "target.h"
46 :
47 :
48 : /* Decompose multi-word pseudo-registers into individual
49 : pseudo-registers when possible and profitable. This is possible
50 : when all the uses of a multi-word register are via SUBREG, or are
51 : copies of the register to another location. Breaking apart the
52 : register permits more CSE and permits better register allocation.
53 : This is profitable if the machine does not have move instructions
54 : to do this.
55 :
56 : This pass only splits moves with modes that are wider than
57 : word_mode and ASHIFTs, LSHIFTRTs, ASHIFTRTs and ZERO_EXTENDs with
58 : integer modes that are twice the width of word_mode. The latter
59 : could be generalized if there was a need to do this, but the trend in
60 : architectures is to not need this.
61 :
62 : There are two useful preprocessor defines for use by maintainers:
63 :
64 : #define LOG_COSTS 1
65 :
66 : if you wish to see the actual cost estimates that are being used
67 : for each mode wider than word mode and the cost estimates for zero
68 : extension and the shifts. This can be useful when port maintainers
69 : are tuning insn rtx costs.
70 :
71 : #define FORCE_LOWERING 1
72 :
73 : if you wish to test the pass with all the transformation forced on.
74 : This can be useful for finding bugs in the transformations. */
75 :
76 : #define LOG_COSTS 0
77 : #define FORCE_LOWERING 0
78 :
79 : /* Bit N in this bitmap is set if regno N is used in a context in
80 : which we can decompose it. */
81 : static bitmap decomposable_context;
82 :
83 : /* Bit N in this bitmap is set if regno N is used in a context in
84 : which it cannot be decomposed. */
85 : static bitmap non_decomposable_context;
86 :
87 : /* Bit N in this bitmap is set if regno N is used in a subreg
88 : which changes the mode but not the size. This typically happens
89 : when the register accessed as a floating-point value; we want to
90 : avoid generating accesses to its subwords in integer modes. */
91 : static bitmap subreg_context;
92 :
93 : /* Bit N in the bitmap in element M of this array is set if there is a
94 : copy from reg M to reg N. */
95 : static vec<bitmap> reg_copy_graph;
96 :
97 : struct target_lower_subreg default_target_lower_subreg;
98 : #if SWITCHABLE_TARGET
99 : struct target_lower_subreg *this_target_lower_subreg
100 : = &default_target_lower_subreg;
101 : #endif
102 :
103 : #define twice_word_mode \
104 : this_target_lower_subreg->x_twice_word_mode
105 : #define choices \
106 : this_target_lower_subreg->x_choices
107 :
108 : /* Return true if MODE is a mode we know how to lower. When returning true,
109 : store its byte size in *BYTES and its word size in *WORDS. */
110 :
111 : static inline bool
112 120246844 : interesting_mode_p (machine_mode mode, unsigned int *bytes,
113 : unsigned int *words)
114 : {
115 240493688 : if (!GET_MODE_SIZE (mode).is_constant (bytes))
116 : return false;
117 143177633 : if (maybe_lt ((unsigned) UNITS_PER_WORD,
118 120246844 : (poly_uint64) REGMODE_NATURAL_SIZE (mode)))
119 : return false;
120 120246844 : *words = CEIL (*bytes, UNITS_PER_WORD);
121 120246844 : return true;
122 : }
123 :
124 : /* RTXes used while computing costs. */
125 : struct cost_rtxes {
126 : /* Source and target registers. */
127 : rtx source;
128 : rtx target;
129 :
130 : /* A twice_word_mode ZERO_EXTEND of SOURCE. */
131 : rtx zext;
132 :
133 : /* A shift of SOURCE. */
134 : rtx shift;
135 :
136 : /* A SET of TARGET. */
137 : rtx set;
138 : };
139 :
140 : /* Return the cost of a CODE shift in mode MODE by OP1 bits, using the
141 : rtxes in RTXES. SPEED_P selects between the speed and size cost. */
142 :
143 : static int
144 192920288 : shift_cost (bool speed_p, struct cost_rtxes *rtxes, enum rtx_code code,
145 : machine_mode mode, int op1)
146 : {
147 192920288 : PUT_CODE (rtxes->shift, code);
148 192920288 : PUT_MODE (rtxes->shift, mode);
149 192920288 : PUT_MODE (rtxes->source, mode);
150 192920288 : XEXP (rtxes->shift, 1) = gen_int_shift_amount (mode, op1);
151 192920288 : return set_src_cost (rtxes->shift, mode, speed_p);
152 : }
153 :
154 : /* For each X in the range [0, BITS_PER_WORD), set SPLITTING[X]
155 : to true if it is profitable to split a double-word CODE shift
156 : of X + BITS_PER_WORD bits. SPEED_P says whether we are testing
157 : for speed or size profitability.
158 :
159 : Use the rtxes in RTXES to calculate costs. WORD_MOVE_ZERO_COST is
160 : the cost of moving zero into a word-mode register. WORD_MOVE_COST
161 : is the cost of moving between word registers. */
162 :
163 : static void
164 1320600 : compute_splitting_shift (bool speed_p, struct cost_rtxes *rtxes,
165 : bool *splitting, enum rtx_code code,
166 : int word_move_zero_cost, int word_move_cost)
167 : {
168 1320600 : int wide_cost, narrow_cost, upper_cost, i;
169 :
170 85872864 : for (i = 0; i < BITS_PER_WORD; i++)
171 : {
172 83434752 : wide_cost = shift_cost (speed_p, rtxes, code, twice_word_mode,
173 : i + BITS_PER_WORD);
174 83434752 : if (i == 0)
175 : narrow_cost = word_move_cost;
176 : else
177 82114152 : narrow_cost = shift_cost (speed_p, rtxes, code, word_mode, i);
178 :
179 83434752 : if (code != ASHIFTRT)
180 : upper_cost = word_move_zero_cost;
181 28172800 : else if (i == BITS_PER_WORD - 1)
182 : upper_cost = word_move_cost;
183 : else
184 27371384 : upper_cost = shift_cost (speed_p, rtxes, code, word_mode,
185 : BITS_PER_WORD - 1);
186 :
187 83434752 : if (LOG_COSTS)
188 : fprintf (stderr, "%s %s by %d: original cost %d, split cost %d + %d\n",
189 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (code),
190 : i + BITS_PER_WORD, wide_cost, narrow_cost, upper_cost);
191 :
192 83434752 : if (FORCE_LOWERING || wide_cost >= narrow_cost + upper_cost)
193 83434752 : splitting[i] = true;
194 : }
195 1320600 : }
196 :
197 : /* Compute what we should do when optimizing for speed or size; SPEED_P
198 : selects which. Use RTXES for computing costs. */
199 :
200 : static void
201 440200 : compute_costs (bool speed_p, struct cost_rtxes *rtxes)
202 : {
203 440200 : unsigned int i;
204 440200 : int word_move_zero_cost, word_move_cost;
205 :
206 440200 : PUT_MODE (rtxes->target, word_mode);
207 440200 : SET_SRC (rtxes->set) = CONST0_RTX (word_mode);
208 440200 : word_move_zero_cost = set_rtx_cost (rtxes->set, speed_p);
209 :
210 440200 : SET_SRC (rtxes->set) = rtxes->source;
211 440200 : word_move_cost = set_rtx_cost (rtxes->set, speed_p);
212 :
213 440200 : if (LOG_COSTS)
214 : fprintf (stderr, "%s move: from zero cost %d, from reg cost %d\n",
215 : GET_MODE_NAME (word_mode), word_move_zero_cost, word_move_cost);
216 :
217 55465200 : for (i = 0; i < MAX_MACHINE_MODE; i++)
218 : {
219 54584800 : machine_mode mode = (machine_mode) i;
220 54584800 : unsigned int size, factor;
221 54584800 : if (interesting_mode_p (mode, &size, &factor) && factor > 1)
222 : {
223 27484296 : unsigned int mode_move_cost;
224 :
225 27484296 : PUT_MODE (rtxes->target, mode);
226 27484296 : PUT_MODE (rtxes->source, mode);
227 27484296 : mode_move_cost = set_rtx_cost (rtxes->set, speed_p);
228 :
229 27484296 : if (LOG_COSTS)
230 : fprintf (stderr, "%s move: original cost %d, split cost %d * %d\n",
231 : GET_MODE_NAME (mode), mode_move_cost,
232 : word_move_cost, factor);
233 :
234 27484296 : if (FORCE_LOWERING || mode_move_cost >= word_move_cost * factor)
235 : {
236 20984930 : choices[speed_p].move_modes_to_split[i] = true;
237 20984930 : choices[speed_p].something_to_do = true;
238 : }
239 : }
240 : }
241 :
242 : /* For the moves and shifts, the only case that is checked is one
243 : where the mode of the target is an integer mode twice the width
244 : of the word_mode.
245 :
246 : If it is not profitable to split a double word move then do not
247 : even consider the shifts or the zero extension. */
248 440200 : if (choices[speed_p].move_modes_to_split[(int) twice_word_mode])
249 : {
250 440200 : int zext_cost;
251 :
252 : /* The only case here to check to see if moving the upper part with a
253 : zero is cheaper than doing the zext itself. */
254 440200 : PUT_MODE (rtxes->source, word_mode);
255 440200 : zext_cost = set_src_cost (rtxes->zext, twice_word_mode, speed_p);
256 :
257 440200 : if (LOG_COSTS)
258 : fprintf (stderr, "%s %s: original cost %d, split cost %d + %d\n",
259 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (ZERO_EXTEND),
260 : zext_cost, word_move_cost, word_move_zero_cost);
261 :
262 440200 : if (FORCE_LOWERING || zext_cost >= word_move_cost + word_move_zero_cost)
263 0 : choices[speed_p].splitting_zext = true;
264 :
265 440200 : compute_splitting_shift (speed_p, rtxes,
266 440200 : choices[speed_p].splitting_ashift, ASHIFT,
267 : word_move_zero_cost, word_move_cost);
268 440200 : compute_splitting_shift (speed_p, rtxes,
269 440200 : choices[speed_p].splitting_lshiftrt, LSHIFTRT,
270 : word_move_zero_cost, word_move_cost);
271 440200 : compute_splitting_shift (speed_p, rtxes,
272 440200 : choices[speed_p].splitting_ashiftrt, ASHIFTRT,
273 : word_move_zero_cost, word_move_cost);
274 : }
275 440200 : }
276 :
277 : /* Do one-per-target initialisation. This involves determining
278 : which operations on the machine are profitable. If none are found,
279 : then the pass just returns when called. */
280 :
281 : void
282 220100 : init_lower_subreg (void)
283 : {
284 220100 : struct cost_rtxes rtxes;
285 :
286 220100 : memset (this_target_lower_subreg, 0, sizeof (*this_target_lower_subreg));
287 :
288 220100 : twice_word_mode = GET_MODE_2XWIDER_MODE (word_mode).require ();
289 :
290 220100 : rtxes.target = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1);
291 220100 : rtxes.source = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2);
292 220100 : rtxes.set = gen_rtx_SET (rtxes.target, rtxes.source);
293 220100 : rtxes.zext = gen_rtx_ZERO_EXTEND (twice_word_mode, rtxes.source);
294 220100 : rtxes.shift = gen_rtx_ASHIFT (twice_word_mode, rtxes.source, const0_rtx);
295 :
296 220100 : if (LOG_COSTS)
297 : fprintf (stderr, "\nSize costs\n==========\n\n");
298 220100 : compute_costs (false, &rtxes);
299 :
300 220100 : if (LOG_COSTS)
301 : fprintf (stderr, "\nSpeed costs\n===========\n\n");
302 220100 : compute_costs (true, &rtxes);
303 220100 : }
304 :
305 : static bool
306 83681726 : simple_move_operand (rtx x)
307 : {
308 83681726 : if (GET_CODE (x) == SUBREG)
309 : {
310 : /* Exclude subregs whose outer mode can be split into multiple words
311 : but whose inner mode cannot. Attempting to split such a subreg
312 : would mean trying to split the unsplittable inner register.
313 :
314 : If instead the subreg occupies a single word, we can keep it as-is,
315 : regardless of what the SUBREG_REG is. If the outer mode cannot be
316 : split then the subreg makes things no worse than they already are. */
317 3516075 : unsigned int factor, size;
318 7032150 : if (interesting_mode_p (GET_MODE (x), &size, &factor) && factor > 1
319 4257687 : && !interesting_mode_p (GET_MODE (SUBREG_REG (x)), &size, &factor))
320 0 : return false;
321 3516075 : x = SUBREG_REG (x);
322 : }
323 :
324 83681726 : if (!OBJECT_P (x))
325 : return false;
326 :
327 83062321 : if (GET_CODE (x) == LABEL_REF
328 83062321 : || GET_CODE (x) == SYMBOL_REF
329 79832671 : || GET_CODE (x) == HIGH
330 79832671 : || GET_CODE (x) == CONST)
331 : return false;
332 :
333 79710197 : if (MEM_P (x)
334 79710197 : && (MEM_VOLATILE_P (x)
335 21788461 : || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x))))
336 3760195 : return false;
337 :
338 : return true;
339 : }
340 :
341 : /* If X is an operator that can be treated as a simple move that we
342 : can split, then return the operand that is operated on. */
343 :
344 : static rtx
345 45030265 : operand_for_swap_move_operator (rtx x)
346 : {
347 : /* A word sized rotate of a register pair is equivalent to swapping
348 : the registers in the register pair. */
349 45030265 : if (GET_CODE (x) == ROTATE
350 10 : && GET_MODE (x) == twice_word_mode
351 10 : && simple_move_operand (XEXP (x, 0))
352 10 : && CONST_INT_P (XEXP (x, 1))
353 45030275 : && INTVAL (XEXP (x, 1)) == BITS_PER_WORD)
354 10 : return XEXP (x, 0);
355 :
356 : return NULL_RTX;
357 : }
358 :
359 : /* If INSN is a single set between two objects that we want to split,
360 : return the single set. SPEED_P says whether we are optimizing
361 : INSN for speed or size.
362 :
363 : INSN should have been passed to recog and extract_insn before this
364 : is called. */
365 :
366 : static rtx
367 117808308 : simple_move (rtx_insn *insn, bool speed_p)
368 : {
369 117808308 : rtx x, op;
370 117808308 : rtx set;
371 117808308 : machine_mode mode;
372 :
373 117808308 : if (recog_data.n_operands != 2)
374 : return NULL_RTX;
375 :
376 57656804 : set = single_set (insn);
377 57656804 : if (!set)
378 : return NULL_RTX;
379 :
380 54802352 : x = SET_DEST (set);
381 54802352 : if (x != recog_data.operand[0] && x != recog_data.operand[1])
382 : return NULL_RTX;
383 44248964 : if (!simple_move_operand (x))
384 : return NULL_RTX;
385 :
386 40616923 : x = SET_SRC (set);
387 40616923 : if ((op = operand_for_swap_move_operator (x)) != NULL_RTX)
388 5 : x = op;
389 :
390 40616923 : if (x != recog_data.operand[0] && x != recog_data.operand[1])
391 : return NULL_RTX;
392 : /* For the src we can handle ASM_OPERANDS, and it is beneficial for
393 : things like x86 rdtsc which returns a DImode value. */
394 39432752 : if (GET_CODE (x) != ASM_OPERANDS
395 39432752 : && !simple_move_operand (x))
396 : return NULL_RTX;
397 :
398 : /* We try to decompose in integer modes, to avoid generating
399 : inefficient code copying between integer and floating point
400 : registers. That means that we can't decompose if this is a
401 : non-integer mode for which there is no integer mode of the same
402 : size. */
403 35333069 : mode = GET_MODE (SET_DEST (set));
404 35333069 : scalar_int_mode int_mode;
405 35333069 : if (!SCALAR_INT_MODE_P (mode)
406 39891793 : && (!int_mode_for_size (GET_MODE_BITSIZE (mode), 0).exists (&int_mode)
407 4044226 : || !targetm.modes_tieable_p (mode, int_mode)))
408 : return NULL_RTX;
409 :
410 : /* Reject PARTIAL_INT modes. They are used for processor specific
411 : purposes and it's probably best not to tamper with them. */
412 34818571 : if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
413 : return NULL_RTX;
414 :
415 34818571 : if (!choices[speed_p].move_modes_to_split[(int) mode])
416 30405359 : return NULL_RTX;
417 :
418 : return set;
419 : }
420 :
421 : /* If SET is a copy from one multi-word pseudo-register to another,
422 : record that in reg_copy_graph. Return whether it is such a
423 : copy. */
424 :
425 : static bool
426 2830644 : find_pseudo_copy (rtx set)
427 : {
428 2830644 : rtx dest = SET_DEST (set);
429 2830644 : rtx src = SET_SRC (set);
430 2830644 : rtx op;
431 2830644 : unsigned int rd, rs;
432 2830644 : bitmap b;
433 :
434 2830644 : if ((op = operand_for_swap_move_operator (src)) != NULL_RTX)
435 4 : src = op;
436 :
437 2830644 : if (!REG_P (dest) || !REG_P (src))
438 : return false;
439 :
440 452606 : rd = REGNO (dest);
441 452606 : rs = REGNO (src);
442 452606 : if (HARD_REGISTER_NUM_P (rd) || HARD_REGISTER_NUM_P (rs))
443 : return false;
444 :
445 141585 : b = reg_copy_graph[rs];
446 141585 : if (b == NULL)
447 : {
448 138960 : b = BITMAP_ALLOC (NULL);
449 138960 : reg_copy_graph[rs] = b;
450 : }
451 :
452 141585 : bitmap_set_bit (b, rd);
453 :
454 141585 : return true;
455 : }
456 :
457 : /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case
458 : where they are copied to another register, add the register to
459 : which they are copied to DECOMPOSABLE_CONTEXT. Use
460 : NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
461 : copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */
462 :
463 : static void
464 109783 : propagate_pseudo_copies (void)
465 : {
466 109783 : auto_bitmap queue, propagate;
467 :
468 109783 : bitmap_copy (queue, decomposable_context);
469 113088 : do
470 : {
471 113088 : bitmap_iterator iter;
472 113088 : unsigned int i;
473 :
474 113088 : bitmap_clear (propagate);
475 :
476 423389 : EXECUTE_IF_SET_IN_BITMAP (queue, 0, i, iter)
477 : {
478 310301 : bitmap b = reg_copy_graph[i];
479 310301 : if (b)
480 8141 : bitmap_ior_and_compl_into (propagate, b, non_decomposable_context);
481 : }
482 :
483 113088 : bitmap_and_compl (queue, propagate, decomposable_context);
484 113088 : bitmap_ior_into (decomposable_context, propagate);
485 : }
486 113088 : while (!bitmap_empty_p (queue));
487 109783 : }
488 :
489 : /* A pointer to one of these values is passed to
490 : find_decomposable_subregs. */
491 :
492 : enum classify_move_insn
493 : {
494 : /* Not a simple move from one location to another. */
495 : NOT_SIMPLE_MOVE,
496 : /* A simple move we want to decompose. */
497 : DECOMPOSABLE_SIMPLE_MOVE,
498 : /* Any other simple move. */
499 : SIMPLE_MOVE
500 : };
501 :
502 : /* If we find a SUBREG in *LOC which we could use to decompose a
503 : pseudo-register, set a bit in DECOMPOSABLE_CONTEXT. If we find an
504 : unadorned register which is not a simple pseudo-register copy,
505 : DATA will point at the type of move, and we set a bit in
506 : DECOMPOSABLE_CONTEXT or NON_DECOMPOSABLE_CONTEXT as appropriate. */
507 :
508 : static void
509 128603651 : find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
510 : {
511 128603651 : subrtx_var_iterator::array_type array;
512 291395499 : FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
513 : {
514 162791848 : rtx x = *iter;
515 162791848 : if (GET_CODE (x) == SUBREG)
516 : {
517 3133998 : rtx inner = SUBREG_REG (x);
518 3133998 : unsigned int regno, outer_size, inner_size, outer_words, inner_words;
519 :
520 3133998 : if (!REG_P (inner))
521 1833683 : continue;
522 :
523 3133995 : regno = REGNO (inner);
524 3133995 : if (HARD_REGISTER_NUM_P (regno))
525 : {
526 2 : iter.skip_subrtxes ();
527 2 : continue;
528 : }
529 :
530 3133993 : if (!interesting_mode_p (GET_MODE (x), &outer_size, &outer_words)
531 3133993 : || !interesting_mode_p (GET_MODE (inner), &inner_size,
532 : &inner_words))
533 0 : continue;
534 :
535 : /* We only try to decompose single word subregs of multi-word
536 : registers. When we find one, we return -1 to avoid iterating
537 : over the inner register.
538 :
539 : ??? This doesn't allow, e.g., DImode subregs of TImode values
540 : on 32-bit targets. We would need to record the way the
541 : pseudo-register was used, and only decompose if all the uses
542 : were the same number and size of pieces. Hopefully this
543 : doesn't happen much. */
544 :
545 3133993 : if (outer_words == 1
546 2224145 : && inner_words > 1
547 : /* Don't allow to decompose floating point subregs of
548 : multi-word pseudos if the floating point mode does
549 : not have word size, because otherwise we'd generate
550 : a subreg with that floating mode from a different
551 : sized integral pseudo which is not allowed by
552 : validate_subreg. */
553 1831926 : && (!FLOAT_MODE_P (GET_MODE (x))
554 7790 : || outer_size == UNITS_PER_WORD))
555 : {
556 1831653 : bitmap_set_bit (decomposable_context, regno);
557 1831653 : iter.skip_subrtxes ();
558 1831653 : continue;
559 : }
560 :
561 : /* If this is a cast from one mode to another, where the modes
562 : have the same size, and they are not tieable, then mark this
563 : register as non-decomposable. If we decompose it we are
564 : likely to mess up whatever the backend is trying to do. */
565 1304365 : if (outer_words > 1
566 909848 : && outer_size == inner_size
567 1520258 : && !targetm.modes_tieable_p (GET_MODE (x), GET_MODE (inner)))
568 : {
569 2025 : bitmap_set_bit (non_decomposable_context, regno);
570 2025 : bitmap_set_bit (subreg_context, regno);
571 2025 : iter.skip_subrtxes ();
572 2025 : continue;
573 : }
574 : }
575 159657850 : else if (REG_P (x))
576 : {
577 81127421 : unsigned int regno, size, words;
578 :
579 : /* We will see an outer SUBREG before we see the inner REG, so
580 : when we see a plain REG here it means a direct reference to
581 : the register.
582 :
583 : If this is not a simple copy from one location to another,
584 : then we cannot decompose this register. If this is a simple
585 : copy we want to decompose, and the mode is right,
586 : then we mark the register as decomposable.
587 : Otherwise we don't say anything about this register --
588 : it could be decomposed, but whether that would be
589 : profitable depends upon how it is used elsewhere.
590 :
591 : We only set bits in the bitmap for multi-word
592 : pseudo-registers, since those are the only ones we care about
593 : and it keeps the size of the bitmaps down. */
594 :
595 81127421 : regno = REGNO (x);
596 81127421 : if (!HARD_REGISTER_NUM_P (regno)
597 51473457 : && interesting_mode_p (GET_MODE (x), &size, &words)
598 132600878 : && words > 1)
599 : {
600 8862005 : switch (*pcmi)
601 : {
602 5936387 : case NOT_SIMPLE_MOVE:
603 5936387 : bitmap_set_bit (non_decomposable_context, regno);
604 5936387 : break;
605 18936 : case DECOMPOSABLE_SIMPLE_MOVE:
606 18936 : if (targetm.modes_tieable_p (GET_MODE (x), word_mode))
607 0 : bitmap_set_bit (decomposable_context, regno);
608 : break;
609 : case SIMPLE_MOVE:
610 : break;
611 0 : default:
612 0 : gcc_unreachable ();
613 : }
614 : }
615 : }
616 78530429 : else if (MEM_P (x))
617 : {
618 16647115 : enum classify_move_insn cmi_mem = NOT_SIMPLE_MOVE;
619 :
620 : /* Any registers used in a MEM do not participate in a
621 : SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE. Do our own recursion
622 : here, and return -1 to block the parent's recursion. */
623 16647115 : find_decomposable_subregs (&XEXP (x, 0), &cmi_mem);
624 16647115 : iter.skip_subrtxes ();
625 : }
626 : }
627 128603651 : }
628 :
629 : /* Decompose REGNO into word-sized components. We smash the REG node
630 : in place. This ensures that (1) something goes wrong quickly if we
631 : fail to make some replacement, and (2) the debug information inside
632 : the symbol table is automatically kept up to date. */
633 :
634 : static void
635 310301 : decompose_register (unsigned int regno)
636 : {
637 310301 : rtx reg;
638 310301 : unsigned int size, words, i;
639 310301 : rtvec v;
640 :
641 310301 : reg = regno_reg_rtx[regno];
642 :
643 310301 : regno_reg_rtx[regno] = NULL_RTX;
644 :
645 310301 : if (!interesting_mode_p (GET_MODE (reg), &size, &words))
646 0 : gcc_unreachable ();
647 :
648 310301 : v = rtvec_alloc (words);
649 1256140 : for (i = 0; i < words; ++i)
650 816308 : RTVEC_ELT (v, i) = gen_reg_rtx_offset (reg, word_mode, i * UNITS_PER_WORD);
651 :
652 310301 : PUT_CODE (reg, CONCATN);
653 310301 : XVEC (reg, 0) = v;
654 :
655 310301 : if (dump_file)
656 : {
657 0 : fprintf (dump_file, "; Splitting reg %u ->", regno);
658 0 : for (i = 0; i < words; ++i)
659 0 : fprintf (dump_file, " %u", REGNO (XVECEXP (reg, 0, i)));
660 0 : fputc ('\n', dump_file);
661 : }
662 310301 : }
663 :
664 : /* Get a SUBREG of a CONCATN. */
665 :
666 : static rtx
667 1592698 : simplify_subreg_concatn (machine_mode outermode, rtx op, poly_uint64 orig_byte)
668 : {
669 1592698 : unsigned int outer_size, inner_size, inner_words;
670 1592698 : machine_mode innermode, partmode;
671 1592698 : rtx part;
672 1592698 : unsigned int final_offset;
673 1592698 : unsigned int byte;
674 :
675 1592698 : innermode = GET_MODE (op);
676 :
677 1592698 : if (!interesting_mode_p (innermode, &inner_size, &inner_words))
678 0 : gcc_unreachable ();
679 :
680 3185396 : if (!GET_MODE_SIZE (outermode).is_constant (&outer_size))
681 : return NULL_RTX;
682 :
683 : /* Must be constant if outer_size is. */
684 1592698 : byte = orig_byte.to_constant ();
685 1592698 : gcc_assert (GET_CODE (op) == CONCATN);
686 1592698 : gcc_assert (byte % outer_size == 0);
687 :
688 1592698 : gcc_assert (byte < inner_size);
689 1592698 : if (outer_size > inner_size)
690 : return NULL_RTX;
691 :
692 1592698 : inner_size /= XVECLEN (op, 0);
693 1592698 : part = XVECEXP (op, 0, byte / inner_size);
694 1592698 : partmode = GET_MODE (part);
695 :
696 1592698 : final_offset = byte % inner_size;
697 1592698 : if (final_offset + outer_size > inner_size)
698 : return NULL_RTX;
699 :
700 : /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
701 : regular CONST_VECTORs. They have vector or integer modes, depending
702 : on the capabilities of the target. Cope with them. */
703 1592323 : if (partmode == VOIDmode && VECTOR_MODE_P (innermode))
704 0 : partmode = GET_MODE_INNER (innermode);
705 0 : else if (partmode == VOIDmode)
706 0 : partmode = mode_for_size (inner_size * BITS_PER_UNIT,
707 0 : GET_MODE_CLASS (innermode), 0).require ();
708 :
709 1592323 : return simplify_gen_subreg (outermode, part, partmode, final_offset);
710 : }
711 :
712 : /* Wrapper around simplify_gen_subreg which handles CONCATN. */
713 :
714 : static rtx
715 1248067 : simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
716 : machine_mode innermode, unsigned int byte)
717 : {
718 1248383 : rtx ret;
719 :
720 : /* We have to handle generating a SUBREG of a SUBREG of a CONCATN.
721 : If OP is a SUBREG of a CONCATN, then it must be a simple mode
722 : change with the same size and offset 0, or it must extract a
723 : part. We shouldn't see anything else here. */
724 1248383 : if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
725 : {
726 546 : rtx op2;
727 :
728 1092 : if (known_eq (GET_MODE_SIZE (GET_MODE (op)),
729 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
730 546 : && known_eq (SUBREG_BYTE (op), 0))
731 : return simplify_gen_subreg_concatn (outermode, SUBREG_REG (op),
732 : GET_MODE (SUBREG_REG (op)), byte);
733 :
734 460 : op2 = simplify_subreg_concatn (GET_MODE (op), SUBREG_REG (op),
735 230 : SUBREG_BYTE (op));
736 230 : if (op2 == NULL_RTX)
737 : {
738 : /* We don't handle paradoxical subregs here. */
739 230 : gcc_assert (!paradoxical_subreg_p (outermode, GET_MODE (op)));
740 230 : gcc_assert (!paradoxical_subreg_p (op));
741 460 : op2 = simplify_subreg_concatn (outermode, SUBREG_REG (op),
742 230 : byte + SUBREG_BYTE (op));
743 230 : gcc_assert (op2 != NULL_RTX);
744 : return op2;
745 : }
746 :
747 0 : op = op2;
748 0 : gcc_assert (op != NULL_RTX);
749 0 : gcc_assert (innermode == GET_MODE (op));
750 : }
751 :
752 1247837 : if (GET_CODE (op) == CONCATN)
753 706815 : return simplify_subreg_concatn (outermode, op, byte);
754 :
755 541022 : ret = simplify_gen_subreg (outermode, op, innermode, byte);
756 :
757 : /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
758 : resolve_simple_move will ask for the high part of the paradoxical
759 : subreg, which does not have a value. Just return a zero. */
760 541022 : if (ret == NULL_RTX
761 541029 : && paradoxical_subreg_p (op))
762 7 : return CONST0_RTX (outermode);
763 :
764 541015 : gcc_assert (ret != NULL_RTX);
765 : return ret;
766 : }
767 :
768 : /* Return whether we should resolve X into the registers into which it
769 : was decomposed. */
770 :
771 : static bool
772 47064497 : resolve_reg_p (rtx x)
773 : {
774 47064497 : return GET_CODE (x) == CONCATN;
775 : }
776 :
777 : /* Return whether X is a SUBREG of a register which we need to
778 : resolve. */
779 :
780 : static bool
781 117512363 : resolve_subreg_p (rtx x)
782 : {
783 2964206 : if (GET_CODE (x) != SUBREG)
784 : return false;
785 0 : return resolve_reg_p (SUBREG_REG (x));
786 : }
787 :
788 : /* Look for SUBREGs in *LOC which need to be decomposed. */
789 :
790 : static bool
791 53201977 : resolve_subreg_use (rtx *loc, rtx insn)
792 : {
793 53201977 : subrtx_ptr_iterator::array_type array;
794 131135496 : FOR_EACH_SUBRTX_PTR (iter, array, loc, NONCONST)
795 : {
796 77935382 : rtx *loc = *iter;
797 77935382 : rtx x = *loc;
798 77935382 : if (resolve_subreg_p (x))
799 : {
800 1613246 : x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x),
801 806623 : SUBREG_BYTE (x));
802 :
803 : /* It is possible for a note to contain a reference which we can
804 : decompose. In this case, return 1 to the caller to indicate
805 : that the note must be removed. */
806 806623 : if (!x)
807 : {
808 3 : gcc_assert (!insn);
809 1863 : return true;
810 : }
811 :
812 806620 : validate_change (insn, loc, x, 1);
813 806620 : iter.skip_subrtxes ();
814 : }
815 77128759 : else if (resolve_reg_p (x))
816 : /* Return 1 to the caller to indicate that we found a direct
817 : reference to a register which is being decomposed. This can
818 : happen inside notes, multiword shift or zero-extend
819 : instructions. */
820 : return true;
821 : }
822 :
823 53200114 : return false;
824 53201977 : }
825 :
826 : /* Resolve any decomposed registers which appear in register notes on
827 : INSN. */
828 :
829 : static void
830 38920720 : resolve_reg_notes (rtx_insn *insn)
831 : {
832 38920720 : rtx *pnote, note;
833 :
834 38920720 : note = find_reg_equal_equiv_note (insn);
835 38920720 : if (note)
836 : {
837 548933 : int old_count = num_validated_changes ();
838 548933 : if (resolve_subreg_use (&XEXP (note, 0), NULL_RTX))
839 1863 : remove_note (insn, note);
840 : else
841 547070 : if (old_count != num_validated_changes ())
842 2640 : df_notes_rescan (insn);
843 : }
844 :
845 38920720 : pnote = ®_NOTES (insn);
846 50710963 : while (*pnote != NULL_RTX)
847 : {
848 11790243 : bool del = false;
849 :
850 11790243 : note = *pnote;
851 11790243 : switch (REG_NOTE_KIND (note))
852 : {
853 3996182 : case REG_DEAD:
854 3996182 : case REG_UNUSED:
855 3996182 : if (resolve_reg_p (XEXP (note, 0)))
856 8260 : del = true;
857 : break;
858 :
859 : default:
860 : break;
861 : }
862 :
863 8260 : if (del)
864 8260 : *pnote = XEXP (note, 1);
865 : else
866 11781983 : pnote = &XEXP (note, 1);
867 : }
868 38920720 : }
869 :
870 : /* Return whether X can be decomposed into subwords. */
871 :
872 : static bool
873 510996 : can_decompose_p (rtx x)
874 : {
875 510996 : if (REG_P (x))
876 : {
877 148296 : unsigned int regno = REGNO (x);
878 :
879 148296 : if (HARD_REGISTER_NUM_P (regno))
880 : {
881 100235 : unsigned int byte, num_bytes, num_words;
882 :
883 100235 : if (!interesting_mode_p (GET_MODE (x), &num_bytes, &num_words))
884 : return false;
885 309235 : for (byte = 0; byte < num_bytes; byte += UNITS_PER_WORD)
886 200470 : if (simplify_subreg_regno (regno, GET_MODE (x), byte, word_mode) < 0)
887 : return false;
888 : return true;
889 : }
890 : else
891 48061 : return !bitmap_bit_p (subreg_context, regno);
892 : }
893 :
894 : return true;
895 : }
896 :
897 : /* OPND is a concatn operand this is used with a simple move operator.
898 : Return a new rtx with the concatn's operands swapped. */
899 :
900 : static rtx
901 1 : resolve_operand_for_swap_move_operator (rtx opnd)
902 : {
903 1 : gcc_assert (GET_CODE (opnd) == CONCATN);
904 1 : rtx concatn = copy_rtx (opnd);
905 1 : rtx op0 = XVECEXP (concatn, 0, 0);
906 1 : rtx op1 = XVECEXP (concatn, 0, 1);
907 1 : XVECEXP (concatn, 0, 0) = op1;
908 1 : XVECEXP (concatn, 0, 1) = op0;
909 1 : return concatn;
910 : }
911 :
912 : /* Decompose the registers used in a simple move SET within INSN. If
913 : we don't change anything, return INSN, otherwise return the start
914 : of the sequence of moves. */
915 :
916 : static rtx_insn *
917 1582698 : resolve_simple_move (rtx set, rtx_insn *insn)
918 : {
919 1582698 : rtx src, dest, real_dest, src_op;
920 1582698 : rtx_insn *insns;
921 1582698 : machine_mode orig_mode, dest_mode;
922 1582698 : unsigned int orig_size, words;
923 1582698 : bool pushing;
924 :
925 1582698 : src = SET_SRC (set);
926 1582698 : dest = SET_DEST (set);
927 1582698 : orig_mode = GET_MODE (dest);
928 :
929 1582698 : if (!interesting_mode_p (orig_mode, &orig_size, &words))
930 0 : gcc_unreachable ();
931 1582698 : gcc_assert (words > 1);
932 :
933 1582698 : start_sequence ();
934 :
935 : /* We have to handle copying from a SUBREG of a decomposed reg where
936 : the SUBREG is larger than word size. Rather than assume that we
937 : can take a word_mode SUBREG of the destination, we copy to a new
938 : register and then copy that to the destination. */
939 :
940 1582698 : real_dest = NULL_RTX;
941 :
942 1582698 : if ((src_op = operand_for_swap_move_operator (src)) != NULL_RTX)
943 : {
944 1 : if (resolve_reg_p (dest))
945 : {
946 : /* DEST is a CONCATN, so swap its operands and strip
947 : SRC's operator. */
948 1 : dest = resolve_operand_for_swap_move_operator (dest);
949 1 : src = src_op;
950 1 : if (resolve_reg_p (src))
951 : {
952 1 : gcc_assert (GET_CODE (src) == CONCATN);
953 1 : if (reg_overlap_mentioned_p (XVECEXP (dest, 0, 0),
954 1 : XVECEXP (src, 0, 1)))
955 : {
956 : /* If there is overlap between the first half of the
957 : destination and what will be stored to the second one,
958 : use a temporary pseudo. See PR114211. */
959 1 : rtx tem = gen_reg_rtx (GET_MODE (XVECEXP (src, 0, 1)));
960 1 : emit_move_insn (tem, XVECEXP (src, 0, 1));
961 1 : src = copy_rtx (src);
962 1 : XVECEXP (src, 0, 1) = tem;
963 : }
964 : }
965 : }
966 0 : else if (resolve_reg_p (src_op))
967 : {
968 : /* SRC is an operation on a CONCATN, so strip the operator and
969 : swap the CONCATN's operands. */
970 0 : src = resolve_operand_for_swap_move_operator (src_op);
971 : }
972 : }
973 :
974 1582698 : if (GET_CODE (src) == SUBREG
975 10493 : && resolve_reg_p (SUBREG_REG (src))
976 1582792 : && (maybe_ne (SUBREG_BYTE (src), 0)
977 186 : || maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
978 : {
979 4 : real_dest = dest;
980 4 : dest = gen_reg_rtx (orig_mode);
981 4 : if (REG_P (real_dest))
982 4 : REG_ATTRS (dest) = REG_ATTRS (real_dest);
983 : }
984 :
985 : /* Similarly if we are copying to a SUBREG of a decomposed reg where
986 : the SUBREG is larger than word size. */
987 :
988 1582698 : if (GET_CODE (dest) == SUBREG
989 1112 : && resolve_reg_p (SUBREG_REG (dest))
990 1582876 : && (maybe_ne (SUBREG_BYTE (dest), 0)
991 178 : || maybe_ne (orig_size,
992 356 : GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))))
993 : {
994 111 : rtx reg, smove;
995 111 : rtx_insn *minsn;
996 :
997 111 : reg = gen_reg_rtx (orig_mode);
998 111 : minsn = emit_move_insn (reg, src);
999 111 : smove = single_set (minsn);
1000 111 : gcc_assert (smove != NULL_RTX);
1001 111 : resolve_simple_move (smove, minsn);
1002 111 : src = reg;
1003 : }
1004 :
1005 : /* If we didn't have any big SUBREGS of decomposed registers, and
1006 : neither side of the move is a register we are decomposing, then
1007 : we don't have to do anything here. */
1008 :
1009 1582698 : if (src == SET_SRC (set)
1010 1582586 : && dest == SET_DEST (set)
1011 1582582 : && !resolve_reg_p (src)
1012 10489 : && !resolve_subreg_p (src)
1013 1533237 : && !resolve_reg_p (dest)
1014 1583688 : && !resolve_subreg_p (dest))
1015 : {
1016 1327200 : end_sequence ();
1017 1327200 : return insn;
1018 : }
1019 :
1020 : /* It's possible for the code to use a subreg of a decomposed
1021 : register while forming an address. We need to handle that before
1022 : passing the address to emit_move_insn. We pass NULL_RTX as the
1023 : insn parameter to resolve_subreg_use because we cannot validate
1024 : the insn yet. */
1025 255498 : if (MEM_P (src) || MEM_P (dest))
1026 : {
1027 69666 : int acg;
1028 :
1029 69666 : if (MEM_P (src))
1030 51985 : resolve_subreg_use (&XEXP (src, 0), NULL_RTX);
1031 69666 : if (MEM_P (dest))
1032 17681 : resolve_subreg_use (&XEXP (dest, 0), NULL_RTX);
1033 69666 : acg = apply_change_group ();
1034 69666 : gcc_assert (acg);
1035 : }
1036 :
1037 : /* If SRC is a register which we can't decompose, or has side
1038 : effects, we need to move via a temporary register. */
1039 :
1040 255498 : if (!can_decompose_p (src)
1041 255335 : || side_effects_p (src)
1042 510833 : || GET_CODE (src) == ASM_OPERANDS)
1043 : {
1044 163 : rtx reg;
1045 :
1046 163 : reg = gen_reg_rtx (orig_mode);
1047 :
1048 163 : if (AUTO_INC_DEC)
1049 : {
1050 : rtx_insn *move = emit_move_insn (reg, src);
1051 : if (MEM_P (src))
1052 : {
1053 : rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
1054 : if (note)
1055 : add_reg_note (move, REG_INC, XEXP (note, 0));
1056 : }
1057 : }
1058 : else
1059 163 : emit_move_insn (reg, src);
1060 :
1061 163 : src = reg;
1062 : }
1063 :
1064 : /* If DEST is a register which we can't decompose, or has side
1065 : effects, we need to first move to a temporary register. We
1066 : handle the common case of pushing an operand directly. We also
1067 : go through a temporary register if it holds a floating point
1068 : value. This gives us better code on systems which can't move
1069 : data easily between integer and floating point registers. */
1070 :
1071 255498 : dest_mode = orig_mode;
1072 255498 : pushing = push_operand (dest, dest_mode);
1073 255498 : if (!can_decompose_p (dest)
1074 255483 : || (side_effects_p (dest) && !pushing)
1075 510981 : || (!SCALAR_INT_MODE_P (dest_mode)
1076 0 : && !resolve_reg_p (dest)
1077 0 : && !resolve_subreg_p (dest)))
1078 : {
1079 15 : if (real_dest == NULL_RTX)
1080 15 : real_dest = dest;
1081 15 : if (!SCALAR_INT_MODE_P (dest_mode))
1082 0 : dest_mode = int_mode_for_mode (dest_mode).require ();
1083 15 : dest = gen_reg_rtx (dest_mode);
1084 15 : if (REG_P (real_dest))
1085 15 : REG_ATTRS (dest) = REG_ATTRS (real_dest);
1086 : }
1087 :
1088 255498 : if (pushing)
1089 : {
1090 0 : unsigned int i, j, jinc;
1091 :
1092 0 : gcc_assert (orig_size % UNITS_PER_WORD == 0);
1093 0 : gcc_assert (GET_CODE (XEXP (dest, 0)) != PRE_MODIFY);
1094 0 : gcc_assert (GET_CODE (XEXP (dest, 0)) != POST_MODIFY);
1095 :
1096 0 : if (WORDS_BIG_ENDIAN == STACK_GROWS_DOWNWARD)
1097 : {
1098 : j = 0;
1099 : jinc = 1;
1100 : }
1101 : else
1102 : {
1103 0 : j = words - 1;
1104 0 : jinc = -1;
1105 : }
1106 :
1107 0 : for (i = 0; i < words; ++i, j += jinc)
1108 : {
1109 0 : rtx temp;
1110 :
1111 0 : temp = copy_rtx (XEXP (dest, 0));
1112 0 : temp = adjust_automodify_address_nv (dest, word_mode, temp,
1113 : j * UNITS_PER_WORD);
1114 0 : emit_move_insn (temp,
1115 : simplify_gen_subreg_concatn (word_mode, src,
1116 : orig_mode,
1117 0 : j * UNITS_PER_WORD));
1118 : }
1119 : }
1120 : else
1121 : {
1122 255498 : unsigned int i;
1123 :
1124 255498 : if (REG_P (dest) && !HARD_REGISTER_NUM_P (REGNO (dest)))
1125 3564 : emit_clobber (dest);
1126 :
1127 789702 : for (i = 0; i < words; ++i)
1128 : {
1129 534204 : rtx t = simplify_gen_subreg_concatn (word_mode, dest,
1130 : dest_mode,
1131 534204 : i * UNITS_PER_WORD);
1132 : /* simplify_gen_subreg_concatn can return (const_int 0) for
1133 : some sub-objects of paradoxical subregs. As a source operand,
1134 : that's fine. As a destination it must be avoided. Those are
1135 : supposed to be don't care bits, so we can just drop that store
1136 : on the floor. */
1137 534204 : if (t != CONST0_RTX (word_mode))
1138 534204 : emit_move_insn (t,
1139 : simplify_gen_subreg_concatn (word_mode, src,
1140 : orig_mode,
1141 534204 : i * UNITS_PER_WORD));
1142 : }
1143 : }
1144 :
1145 255498 : if (real_dest != NULL_RTX)
1146 : {
1147 19 : rtx mdest, smove;
1148 19 : rtx_insn *minsn;
1149 :
1150 19 : if (dest_mode == orig_mode)
1151 : mdest = dest;
1152 : else
1153 0 : mdest = simplify_gen_subreg (orig_mode, dest, GET_MODE (dest), 0);
1154 19 : minsn = emit_move_insn (real_dest, mdest);
1155 :
1156 19 : if (AUTO_INC_DEC && MEM_P (real_dest)
1157 : && !(resolve_reg_p (real_dest) || resolve_subreg_p (real_dest)))
1158 : {
1159 : rtx note = find_reg_note (insn, REG_INC, NULL_RTX);
1160 : if (note)
1161 : add_reg_note (minsn, REG_INC, XEXP (note, 0));
1162 : }
1163 :
1164 19 : smove = single_set (minsn);
1165 19 : gcc_assert (smove != NULL_RTX);
1166 :
1167 19 : resolve_simple_move (smove, minsn);
1168 : }
1169 :
1170 255498 : insns = end_sequence ();
1171 :
1172 255498 : copy_reg_eh_region_note_forward (insn, insns, NULL_RTX);
1173 :
1174 255498 : emit_insn_before (insns, insn);
1175 :
1176 : /* If we get here via self-recursion, then INSN is not yet in the insns
1177 : chain and delete_insn will fail. We only want to remove INSN from the
1178 : current sequence. See PR56738. */
1179 255498 : if (in_sequence_p ())
1180 6 : remove_insn (insn);
1181 : else
1182 255492 : delete_insn (insn);
1183 :
1184 : return insns;
1185 : }
1186 :
1187 : /* Change a CLOBBER of a decomposed register into a CLOBBER of the
1188 : component registers. Return whether we changed something. */
1189 :
1190 : static bool
1191 165719 : resolve_clobber (rtx pat, rtx_insn *insn)
1192 : {
1193 165719 : rtx reg;
1194 165719 : machine_mode orig_mode;
1195 165719 : unsigned int orig_size, words, i;
1196 165719 : int ret;
1197 :
1198 165719 : reg = XEXP (pat, 0);
1199 : /* For clobbers we can look through paradoxical subregs which
1200 : we do not handle in simplify_gen_subreg_concatn. */
1201 165719 : if (paradoxical_subreg_p (reg))
1202 165719 : reg = SUBREG_REG (reg);
1203 165719 : if (!resolve_reg_p (reg) && !resolve_subreg_p (reg))
1204 : return false;
1205 :
1206 62102 : orig_mode = GET_MODE (reg);
1207 62102 : if (!interesting_mode_p (orig_mode, &orig_size, &words))
1208 0 : gcc_unreachable ();
1209 :
1210 62102 : ret = validate_change (NULL_RTX, &XEXP (pat, 0),
1211 : simplify_gen_subreg_concatn (word_mode, reg,
1212 : orig_mode, 0),
1213 : 0);
1214 62102 : df_insn_rescan (insn);
1215 62102 : gcc_assert (ret != 0);
1216 :
1217 124204 : for (i = words - 1; i > 0; --i)
1218 : {
1219 62102 : rtx x;
1220 :
1221 62102 : x = simplify_gen_subreg_concatn (word_mode, reg, orig_mode,
1222 62102 : i * UNITS_PER_WORD);
1223 62102 : x = gen_rtx_CLOBBER (VOIDmode, x);
1224 62102 : emit_insn_after (x, insn);
1225 : }
1226 :
1227 62102 : resolve_reg_notes (insn);
1228 :
1229 62102 : return true;
1230 : }
1231 :
1232 : /* A USE of a decomposed register is no longer meaningful. Return
1233 : whether we changed something. */
1234 :
1235 : static bool
1236 62636 : resolve_use (rtx pat, rtx_insn *insn)
1237 : {
1238 62636 : if (resolve_reg_p (XEXP (pat, 0)) || resolve_subreg_p (XEXP (pat, 0)))
1239 : {
1240 0 : delete_insn (insn);
1241 0 : return true;
1242 : }
1243 :
1244 62636 : resolve_reg_notes (insn);
1245 :
1246 62636 : return false;
1247 : }
1248 :
1249 : /* A VAR_LOCATION can be simplified. */
1250 :
1251 : static void
1252 14902020 : resolve_debug (rtx_insn *insn)
1253 : {
1254 14902020 : subrtx_ptr_iterator::array_type array;
1255 51452159 : FOR_EACH_SUBRTX_PTR (iter, array, &PATTERN (insn), NONCONST)
1256 : {
1257 36550139 : rtx *loc = *iter;
1258 36550139 : rtx x = *loc;
1259 36550139 : if (resolve_subreg_p (x))
1260 : {
1261 157600 : x = simplify_subreg_concatn (GET_MODE (x), SUBREG_REG (x),
1262 78800 : SUBREG_BYTE (x));
1263 :
1264 78800 : if (x)
1265 78658 : *loc = x;
1266 : else
1267 142 : x = copy_rtx (*loc);
1268 : }
1269 36550139 : if (resolve_reg_p (x))
1270 48415 : *loc = copy_rtx (x);
1271 : }
1272 :
1273 14902020 : df_insn_rescan (insn);
1274 :
1275 14902020 : resolve_reg_notes (insn);
1276 14902020 : }
1277 :
1278 : /* Check if INSN is a decomposable multiword-shift or zero-extend and
1279 : set the decomposable_context bitmap accordingly. SPEED_P is true
1280 : if we are optimizing INSN for speed rather than size. Return true
1281 : if INSN is decomposable. */
1282 :
1283 : static bool
1284 93963236 : find_decomposable_shift_zext (rtx_insn *insn, bool speed_p)
1285 : {
1286 93963236 : rtx set;
1287 93963236 : rtx op;
1288 93963236 : rtx op_operand;
1289 :
1290 93963236 : set = single_set (insn);
1291 93963236 : if (!set)
1292 : return false;
1293 :
1294 48476327 : op = SET_SRC (set);
1295 48476327 : if (GET_CODE (op) != ASHIFT
1296 : && GET_CODE (op) != LSHIFTRT
1297 : && GET_CODE (op) != ASHIFTRT
1298 : && GET_CODE (op) != ZERO_EXTEND)
1299 : return false;
1300 :
1301 1026226 : op_operand = XEXP (op, 0);
1302 1011865 : if (!REG_P (SET_DEST (set)) || !REG_P (op_operand)
1303 830779 : || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set)))
1304 830350 : || HARD_REGISTER_NUM_P (REGNO (op_operand))
1305 1856572 : || GET_MODE (op) != twice_word_mode)
1306 : return false;
1307 :
1308 142905 : if (GET_CODE (op) == ZERO_EXTEND)
1309 : {
1310 65956 : if (GET_MODE (op_operand) != word_mode
1311 65956 : || !choices[speed_p].splitting_zext)
1312 : return false;
1313 : }
1314 : else /* left or right shift */
1315 : {
1316 76949 : bool *splitting = (GET_CODE (op) == ASHIFT
1317 21469 : ? choices[speed_p].splitting_ashift
1318 : : GET_CODE (op) == ASHIFTRT
1319 9349 : ? choices[speed_p].splitting_ashiftrt
1320 46131 : : choices[speed_p].splitting_lshiftrt);
1321 76949 : if (!CONST_INT_P (XEXP (op, 1))
1322 159781 : || !IN_RANGE (INTVAL (XEXP (op, 1)), BITS_PER_WORD,
1323 : 2 * BITS_PER_WORD - 1)
1324 83298 : || !splitting[INTVAL (XEXP (op, 1)) - BITS_PER_WORD])
1325 : return false;
1326 :
1327 48890 : bitmap_set_bit (decomposable_context, REGNO (op_operand));
1328 : }
1329 :
1330 48890 : bitmap_set_bit (decomposable_context, REGNO (SET_DEST (set)));
1331 :
1332 48890 : return true;
1333 : }
1334 :
1335 : /* Decompose a more than word wide shift (in INSN) of a multiword
1336 : pseudo or a multiword zero-extend of a wordmode pseudo into a move
1337 : and 'set to zero' insn. SPEED_P says whether we are optimizing
1338 : for speed or size, when checking if a ZERO_EXTEND is preferable.
1339 : Return a pointer to the new insn when a replacement was done. */
1340 :
1341 : static rtx_insn *
1342 22311394 : resolve_shift_zext (rtx_insn *insn, bool speed_p)
1343 : {
1344 22311394 : rtx set;
1345 22311394 : rtx op;
1346 22311394 : rtx op_operand;
1347 22311394 : rtx_insn *insns;
1348 22311394 : rtx src_reg, dest_reg, dest_upper, upper_src = NULL_RTX;
1349 22311394 : int src_reg_num, dest_reg_num, offset1, offset2, src_offset;
1350 22311394 : scalar_int_mode inner_mode;
1351 :
1352 22311394 : set = single_set (insn);
1353 22311394 : if (!set)
1354 : return NULL;
1355 :
1356 21129388 : op = SET_SRC (set);
1357 21129388 : if (GET_CODE (op) != ASHIFT
1358 : && GET_CODE (op) != LSHIFTRT
1359 : && GET_CODE (op) != ASHIFTRT
1360 : && GET_CODE (op) != ZERO_EXTEND)
1361 : return NULL;
1362 :
1363 469352 : op_operand = XEXP (op, 0);
1364 469352 : if (!is_a <scalar_int_mode> (GET_MODE (op_operand), &inner_mode))
1365 : return NULL;
1366 :
1367 : /* We can tear this operation apart only if the regs were already
1368 : torn apart. */
1369 432825 : if (!resolve_reg_p (SET_DEST (set)) && !resolve_reg_p (op_operand))
1370 : return NULL;
1371 :
1372 : /* src_reg_num is the number of the word mode register which we
1373 : are operating on. For a left shift and a zero_extend on little
1374 : endian machines this is register 0. */
1375 3883 : src_reg_num = (GET_CODE (op) == LSHIFTRT || GET_CODE (op) == ASHIFTRT)
1376 18485 : ? 1 : 0;
1377 :
1378 18485 : if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
1379 : src_reg_num = 1 - src_reg_num;
1380 :
1381 18485 : if (GET_CODE (op) == ZERO_EXTEND)
1382 : dest_reg_num = WORDS_BIG_ENDIAN ? 1 : 0;
1383 : else
1384 18485 : dest_reg_num = 1 - src_reg_num;
1385 :
1386 18485 : offset1 = UNITS_PER_WORD * dest_reg_num;
1387 18485 : offset2 = UNITS_PER_WORD * (1 - dest_reg_num);
1388 18485 : src_offset = UNITS_PER_WORD * src_reg_num;
1389 :
1390 18485 : start_sequence ();
1391 :
1392 36970 : dest_reg = simplify_gen_subreg_concatn (word_mode, SET_DEST (set),
1393 18485 : GET_MODE (SET_DEST (set)),
1394 : offset1);
1395 36970 : dest_upper = simplify_gen_subreg_concatn (word_mode, SET_DEST (set),
1396 18485 : GET_MODE (SET_DEST (set)),
1397 : offset2);
1398 36970 : src_reg = simplify_gen_subreg_concatn (word_mode, op_operand,
1399 18485 : GET_MODE (op_operand),
1400 : src_offset);
1401 18485 : if (GET_CODE (op) == ASHIFTRT
1402 3296 : && INTVAL (XEXP (op, 1)) != 2 * BITS_PER_WORD - 1)
1403 3142 : upper_src = expand_shift (RSHIFT_EXPR, word_mode, copy_rtx (src_reg),
1404 3178 : BITS_PER_WORD - 1, NULL_RTX, 0);
1405 :
1406 18485 : if (GET_CODE (op) != ZERO_EXTEND)
1407 : {
1408 18485 : int shift_count = INTVAL (XEXP (op, 1));
1409 29330 : if (shift_count > BITS_PER_WORD)
1410 2911 : src_reg = expand_shift (GET_CODE (op) == ASHIFT ?
1411 : LSHIFT_EXPR : RSHIFT_EXPR,
1412 : word_mode, src_reg,
1413 2911 : shift_count - BITS_PER_WORD,
1414 : dest_reg, GET_CODE (op) != ASHIFTRT);
1415 : }
1416 :
1417 : /* Consider using ZERO_EXTEND instead of setting DEST_UPPER to zero
1418 : if this is considered reasonable. */
1419 18485 : if (GET_CODE (op) == LSHIFTRT
1420 11387 : && GET_MODE (op) == twice_word_mode
1421 11387 : && REG_P (SET_DEST (set))
1422 18783 : && !choices[speed_p].splitting_zext)
1423 : {
1424 298 : rtx tmp = force_reg (word_mode, copy_rtx (src_reg));
1425 298 : tmp = simplify_gen_unary (ZERO_EXTEND, twice_word_mode, tmp, word_mode);
1426 298 : emit_move_insn (SET_DEST (set), tmp);
1427 : }
1428 : else
1429 : {
1430 18187 : if (dest_reg != src_reg)
1431 15332 : emit_move_insn (dest_reg, src_reg);
1432 18187 : if (GET_CODE (op) != ASHIFTRT)
1433 14972 : emit_move_insn (dest_upper, CONST0_RTX (word_mode));
1434 3296 : else if (INTVAL (XEXP (op, 1)) == 2 * BITS_PER_WORD - 1)
1435 73 : emit_move_insn (dest_upper, copy_rtx (src_reg));
1436 : else
1437 3142 : emit_move_insn (dest_upper, upper_src);
1438 : }
1439 :
1440 18485 : insns = end_sequence ();
1441 :
1442 18485 : emit_insn_before (insns, insn);
1443 :
1444 18485 : if (dump_file)
1445 : {
1446 0 : rtx_insn *in;
1447 0 : fprintf (dump_file, "; Replacing insn: %d with insns: ", INSN_UID (insn));
1448 0 : for (in = insns; in != insn; in = NEXT_INSN (in))
1449 0 : fprintf (dump_file, "%d ", INSN_UID (in));
1450 0 : fprintf (dump_file, "\n");
1451 : }
1452 :
1453 18485 : delete_insn (insn);
1454 18485 : return insns;
1455 : }
1456 :
1457 : /* Print to dump_file a description of what we're doing with shift code CODE.
1458 : SPLITTING[X] is true if we are splitting shifts by X + BITS_PER_WORD. */
1459 :
1460 : static void
1461 360 : dump_shift_choices (enum rtx_code code, bool *splitting)
1462 : {
1463 360 : int i;
1464 360 : const char *sep;
1465 :
1466 360 : fprintf (dump_file,
1467 : " Splitting mode %s for %s lowering with shift amounts = ",
1468 360 : GET_MODE_NAME (twice_word_mode), GET_RTX_NAME (code));
1469 360 : sep = "";
1470 23760 : for (i = 0; i < BITS_PER_WORD; i++)
1471 23040 : if (splitting[i])
1472 : {
1473 23040 : fprintf (dump_file, "%s%d", sep, i + BITS_PER_WORD);
1474 23040 : sep = ",";
1475 : }
1476 360 : fprintf (dump_file, "\n");
1477 360 : }
1478 :
1479 : /* Print to dump_file a description of what we're doing when optimizing
1480 : for speed or size; SPEED_P says which. DESCRIPTION is a description
1481 : of the SPEED_P choice. */
1482 :
1483 : static void
1484 120 : dump_choices (bool speed_p, const char *description)
1485 : {
1486 120 : unsigned int size, factor, i;
1487 :
1488 120 : fprintf (dump_file, "Choices when optimizing for %s:\n", description);
1489 :
1490 15120 : for (i = 0; i < MAX_MACHINE_MODE; i++)
1491 14880 : if (interesting_mode_p ((machine_mode) i, &size, &factor)
1492 14880 : && factor > 1)
1493 7440 : fprintf (dump_file, " %s mode %s for copy lowering.\n",
1494 7440 : choices[speed_p].move_modes_to_split[i]
1495 : ? "Splitting"
1496 : : "Skipping",
1497 7440 : GET_MODE_NAME ((machine_mode) i));
1498 :
1499 120 : fprintf (dump_file, " %s mode %s for zero_extend lowering.\n",
1500 120 : choices[speed_p].splitting_zext ? "Splitting" : "Skipping",
1501 120 : GET_MODE_NAME (twice_word_mode));
1502 :
1503 120 : dump_shift_choices (ASHIFT, choices[speed_p].splitting_ashift);
1504 120 : dump_shift_choices (LSHIFTRT, choices[speed_p].splitting_lshiftrt);
1505 120 : dump_shift_choices (ASHIFTRT, choices[speed_p].splitting_ashiftrt);
1506 120 : fprintf (dump_file, "\n");
1507 120 : }
1508 :
1509 : /* Look for registers which are always accessed via word-sized SUBREGs
1510 : or -if DECOMPOSE_COPIES is true- via copies. Decompose these
1511 : registers into several word-sized pseudo-registers. */
1512 :
1513 : static void
1514 2128701 : decompose_multiword_subregs (bool decompose_copies)
1515 : {
1516 2128701 : unsigned int max;
1517 2128701 : basic_block bb;
1518 2128701 : bool speed_p;
1519 :
1520 2128701 : if (dump_file)
1521 : {
1522 60 : dump_choices (false, "size");
1523 60 : dump_choices (true, "speed");
1524 : }
1525 :
1526 : /* Check if this target even has any modes to consider lowering. */
1527 2128701 : if (!choices[false].something_to_do && !choices[true].something_to_do)
1528 : {
1529 0 : if (dump_file)
1530 0 : fprintf (dump_file, "Nothing to do!\n");
1531 : return;
1532 : }
1533 :
1534 2128701 : max = max_reg_num ();
1535 :
1536 : /* First see if there are any multi-word pseudo-registers. If there
1537 : aren't, there is nothing we can do. This should speed up this
1538 : pass in the normal case, since it should be faster than scanning
1539 : all the insns. */
1540 2128701 : {
1541 2128701 : unsigned int i;
1542 2128701 : bool useful_modes_seen = false;
1543 :
1544 80316585 : for (i = FIRST_PSEUDO_REGISTER; i < max; ++i)
1545 78524488 : if (regno_reg_rtx[i] != NULL)
1546 : {
1547 78423855 : machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1548 78423855 : if (choices[false].move_modes_to_split[(int) mode]
1549 78087251 : || choices[true].move_modes_to_split[(int) mode])
1550 : {
1551 : useful_modes_seen = true;
1552 : break;
1553 : }
1554 : }
1555 :
1556 2128701 : if (!useful_modes_seen)
1557 : {
1558 1792097 : if (dump_file)
1559 60 : fprintf (dump_file, "Nothing to lower in this function.\n");
1560 : return;
1561 : }
1562 : }
1563 :
1564 336604 : if (df)
1565 : {
1566 147870 : df_set_flags (DF_DEFER_INSN_RESCAN);
1567 147870 : run_word_dce ();
1568 : }
1569 :
1570 : /* FIXME: It may be possible to change this code to look for each
1571 : multi-word pseudo-register and to find each insn which sets or
1572 : uses that register. That should be faster than scanning all the
1573 : insns. */
1574 :
1575 336604 : decomposable_context = BITMAP_ALLOC (NULL);
1576 336604 : non_decomposable_context = BITMAP_ALLOC (NULL);
1577 336604 : subreg_context = BITMAP_ALLOC (NULL);
1578 :
1579 336604 : reg_copy_graph.create (max);
1580 336604 : reg_copy_graph.safe_grow_cleared (max, true);
1581 336604 : memset (reg_copy_graph.address (), 0, sizeof (bitmap) * max);
1582 :
1583 336604 : speed_p = optimize_function_for_speed_p (cfun);
1584 8850069 : FOR_EACH_BB_FN (bb, cfun)
1585 : {
1586 8513465 : rtx_insn *insn;
1587 :
1588 117215128 : FOR_BB_INSNS (bb, insn)
1589 : {
1590 108701663 : rtx set;
1591 108701663 : enum classify_move_insn cmi;
1592 108701663 : int i, n;
1593 :
1594 123440090 : if (!INSN_P (insn)
1595 94304038 : || GET_CODE (PATTERN (insn)) == CLOBBER
1596 202862243 : || GET_CODE (PATTERN (insn)) == USE)
1597 14787317 : continue;
1598 :
1599 93963236 : recog_memoized (insn);
1600 :
1601 93963236 : if (find_decomposable_shift_zext (insn, speed_p))
1602 48890 : continue;
1603 :
1604 93914346 : extract_insn (insn);
1605 :
1606 93914346 : set = simple_move (insn, speed_p);
1607 :
1608 93914346 : if (!set)
1609 91083702 : cmi = NOT_SIMPLE_MOVE;
1610 : else
1611 : {
1612 : /* We mark pseudo-to-pseudo copies as decomposable during the
1613 : second pass only. The first pass is so early that there is
1614 : good chance such moves will be optimized away completely by
1615 : subsequent optimizations anyway.
1616 :
1617 : However, we call find_pseudo_copy even during the first pass
1618 : so as to properly set up the reg_copy_graph. */
1619 2830644 : if (find_pseudo_copy (set))
1620 273702 : cmi = decompose_copies? DECOMPOSABLE_SIMPLE_MOVE : SIMPLE_MOVE;
1621 : else
1622 2689059 : cmi = SIMPLE_MOVE;
1623 : }
1624 :
1625 93914346 : n = recog_data.n_operands;
1626 205870882 : for (i = 0; i < n; ++i)
1627 : {
1628 111956536 : find_decomposable_subregs (&recog_data.operand[i], &cmi);
1629 :
1630 : /* We handle ASM_OPERANDS as a special case to support
1631 : things like x86 rdtsc which returns a DImode value.
1632 : We can decompose the output, which will certainly be
1633 : operand 0, but not the inputs. */
1634 :
1635 111956536 : if (cmi == SIMPLE_MOVE
1636 5642352 : && GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1637 : {
1638 0 : gcc_assert (i == 0);
1639 0 : cmi = NOT_SIMPLE_MOVE;
1640 : }
1641 : }
1642 : }
1643 : }
1644 :
1645 336604 : bitmap_and_compl_into (decomposable_context, non_decomposable_context);
1646 336604 : if (!bitmap_empty_p (decomposable_context))
1647 : {
1648 109783 : unsigned int i;
1649 109783 : sbitmap_iterator sbi;
1650 109783 : bitmap_iterator iter;
1651 109783 : unsigned int regno;
1652 :
1653 109783 : propagate_pseudo_copies ();
1654 :
1655 109783 : auto_sbitmap sub_blocks (last_basic_block_for_fn (cfun));
1656 109783 : bitmap_clear (sub_blocks);
1657 :
1658 420084 : EXECUTE_IF_SET_IN_BITMAP (decomposable_context, 0, regno, iter)
1659 310301 : decompose_register (regno);
1660 :
1661 3995893 : FOR_EACH_BB_FN (bb, cfun)
1662 : {
1663 3886110 : rtx_insn *insn;
1664 :
1665 49194289 : FOR_BB_INSNS (bb, insn)
1666 : {
1667 45308179 : rtx pat;
1668 :
1669 45308179 : if (!INSN_P (insn))
1670 6283842 : continue;
1671 :
1672 39024337 : pat = PATTERN (insn);
1673 39024337 : if (GET_CODE (pat) == CLOBBER)
1674 165719 : resolve_clobber (pat, insn);
1675 38858618 : else if (GET_CODE (pat) == USE)
1676 62636 : resolve_use (pat, insn);
1677 38795982 : else if (DEBUG_INSN_P (insn))
1678 14902020 : resolve_debug (insn);
1679 : else
1680 : {
1681 23893962 : rtx set;
1682 23893962 : int i;
1683 :
1684 23893962 : recog_memoized (insn);
1685 23893962 : extract_insn (insn);
1686 :
1687 23893962 : set = simple_move (insn, speed_p);
1688 23893962 : if (set)
1689 : {
1690 1582568 : rtx_insn *orig_insn = insn;
1691 1582568 : bool cfi = control_flow_insn_p (insn);
1692 :
1693 : /* We can end up splitting loads to multi-word pseudos
1694 : into separate loads to machine word size pseudos.
1695 : When this happens, we first had one load that can
1696 : throw, and after resolve_simple_move we'll have a
1697 : bunch of loads (at least two). All those loads may
1698 : trap if we can have non-call exceptions, so they
1699 : all will end the current basic block. We split the
1700 : block after the outer loop over all insns, but we
1701 : make sure here that we will be able to split the
1702 : basic block and still produce the correct control
1703 : flow graph for it. */
1704 1582568 : gcc_assert (!cfi
1705 : || (cfun->can_throw_non_call_exceptions
1706 : && can_throw_internal (insn)));
1707 :
1708 1582568 : insn = resolve_simple_move (set, insn);
1709 1582568 : if (insn != orig_insn)
1710 : {
1711 255492 : recog_memoized (insn);
1712 255492 : extract_insn (insn);
1713 :
1714 255492 : if (cfi)
1715 6263 : bitmap_set_bit (sub_blocks, bb->index);
1716 : }
1717 : }
1718 : else
1719 : {
1720 22311394 : rtx_insn *decomposed_shift;
1721 :
1722 22311394 : decomposed_shift = resolve_shift_zext (insn, speed_p);
1723 22311394 : if (decomposed_shift != NULL_RTX)
1724 : {
1725 18485 : insn = decomposed_shift;
1726 18485 : recog_memoized (insn);
1727 18485 : extract_insn (insn);
1728 : }
1729 : }
1730 :
1731 76477340 : for (i = recog_data.n_operands - 1; i >= 0; --i)
1732 52583378 : resolve_subreg_use (recog_data.operand_loc[i], insn);
1733 :
1734 23893962 : resolve_reg_notes (insn);
1735 :
1736 23893962 : if (num_validated_changes () > 0)
1737 : {
1738 798385 : for (i = recog_data.n_dups - 1; i >= 0; --i)
1739 : {
1740 11786 : rtx *pl = recog_data.dup_loc[i];
1741 11786 : int dup_num = recog_data.dup_num[i];
1742 11786 : rtx *px = recog_data.operand_loc[dup_num];
1743 :
1744 11786 : validate_unshare_change (insn, pl, *px, 1);
1745 : }
1746 :
1747 786599 : i = apply_change_group ();
1748 786599 : gcc_assert (i);
1749 : }
1750 : }
1751 : }
1752 : }
1753 :
1754 : /* If we had insns to split that caused control flow insns in the middle
1755 : of a basic block, split those blocks now. Note that we only handle
1756 : the case where splitting a load has caused multiple possibly trapping
1757 : loads to appear. */
1758 225829 : EXECUTE_IF_SET_IN_BITMAP (sub_blocks, 0, i, sbi)
1759 : {
1760 6263 : rtx_insn *insn, *end;
1761 6263 : edge fallthru;
1762 :
1763 6263 : bb = BASIC_BLOCK_FOR_FN (cfun, i);
1764 6263 : insn = BB_HEAD (bb);
1765 6263 : end = BB_END (bb);
1766 :
1767 36428 : while (insn != end)
1768 : {
1769 30165 : if (control_flow_insn_p (insn))
1770 : {
1771 : /* Split the block after insn. There will be a fallthru
1772 : edge, which is OK so we keep it. We have to create the
1773 : exception edges ourselves. */
1774 6379 : fallthru = split_block (bb, insn);
1775 6379 : rtl_make_eh_edge (NULL, bb, BB_END (bb));
1776 6379 : bb = fallthru->dest;
1777 6379 : insn = BB_HEAD (bb);
1778 : }
1779 : else
1780 23786 : insn = NEXT_INSN (insn);
1781 : }
1782 : }
1783 109783 : }
1784 :
1785 64613857 : for (bitmap b : reg_copy_graph)
1786 63604045 : if (b)
1787 138960 : BITMAP_FREE (b);
1788 :
1789 336604 : reg_copy_graph.release ();
1790 :
1791 336604 : BITMAP_FREE (decomposable_context);
1792 336604 : BITMAP_FREE (non_decomposable_context);
1793 336604 : BITMAP_FREE (subreg_context);
1794 : }
1795 :
1796 : /* Implement first lower subreg pass. */
1797 :
1798 : namespace {
1799 :
1800 : const pass_data pass_data_lower_subreg =
1801 : {
1802 : RTL_PASS, /* type */
1803 : "subreg1", /* name */
1804 : OPTGROUP_NONE, /* optinfo_flags */
1805 : TV_LOWER_SUBREG, /* tv_id */
1806 : 0, /* properties_required */
1807 : 0, /* properties_provided */
1808 : 0, /* properties_destroyed */
1809 : 0, /* todo_flags_start */
1810 : 0, /* todo_flags_finish */
1811 : };
1812 :
1813 : class pass_lower_subreg : public rtl_opt_pass
1814 : {
1815 : public:
1816 294587 : pass_lower_subreg (gcc::context *ctxt)
1817 589174 : : rtl_opt_pass (pass_data_lower_subreg, ctxt)
1818 : {}
1819 :
1820 : /* opt_pass methods: */
1821 1511392 : bool gate (function *) final override { return flag_split_wide_types != 0; }
1822 1064350 : unsigned int execute (function *) final override
1823 : {
1824 1064350 : decompose_multiword_subregs (false);
1825 1064350 : return 0;
1826 : }
1827 :
1828 : }; // class pass_lower_subreg
1829 :
1830 : } // anon namespace
1831 :
1832 : rtl_opt_pass *
1833 294587 : make_pass_lower_subreg (gcc::context *ctxt)
1834 : {
1835 294587 : return new pass_lower_subreg (ctxt);
1836 : }
1837 :
1838 : /* Implement second lower subreg pass. */
1839 :
1840 : namespace {
1841 :
1842 : const pass_data pass_data_lower_subreg2 =
1843 : {
1844 : RTL_PASS, /* type */
1845 : "subreg2", /* name */
1846 : OPTGROUP_NONE, /* optinfo_flags */
1847 : TV_LOWER_SUBREG, /* tv_id */
1848 : 0, /* properties_required */
1849 : 0, /* properties_provided */
1850 : 0, /* properties_destroyed */
1851 : 0, /* todo_flags_start */
1852 : TODO_df_finish, /* todo_flags_finish */
1853 : };
1854 :
1855 : class pass_lower_subreg2 : public rtl_opt_pass
1856 : {
1857 : public:
1858 294587 : pass_lower_subreg2 (gcc::context *ctxt)
1859 589174 : : rtl_opt_pass (pass_data_lower_subreg2, ctxt)
1860 : {}
1861 :
1862 : /* opt_pass methods: */
1863 1511392 : bool gate (function *) final override
1864 : {
1865 1511392 : return flag_split_wide_types && flag_split_wide_types_early;
1866 : }
1867 0 : unsigned int execute (function *) final override
1868 : {
1869 0 : decompose_multiword_subregs (true);
1870 0 : return 0;
1871 : }
1872 :
1873 : }; // class pass_lower_subreg2
1874 :
1875 : } // anon namespace
1876 :
1877 : rtl_opt_pass *
1878 294587 : make_pass_lower_subreg2 (gcc::context *ctxt)
1879 : {
1880 294587 : return new pass_lower_subreg2 (ctxt);
1881 : }
1882 :
1883 : /* Implement third lower subreg pass. */
1884 :
1885 : namespace {
1886 :
1887 : const pass_data pass_data_lower_subreg3 =
1888 : {
1889 : RTL_PASS, /* type */
1890 : "subreg3", /* name */
1891 : OPTGROUP_NONE, /* optinfo_flags */
1892 : TV_LOWER_SUBREG, /* tv_id */
1893 : 0, /* properties_required */
1894 : 0, /* properties_provided */
1895 : 0, /* properties_destroyed */
1896 : 0, /* todo_flags_start */
1897 : TODO_df_finish, /* todo_flags_finish */
1898 : };
1899 :
1900 : class pass_lower_subreg3 : public rtl_opt_pass
1901 : {
1902 : public:
1903 294587 : pass_lower_subreg3 (gcc::context *ctxt)
1904 589174 : : rtl_opt_pass (pass_data_lower_subreg3, ctxt)
1905 : {}
1906 :
1907 : /* opt_pass methods: */
1908 1511392 : bool gate (function *) final override { return flag_split_wide_types; }
1909 1064351 : unsigned int execute (function *) final override
1910 : {
1911 1064351 : decompose_multiword_subregs (true);
1912 1064351 : return 0;
1913 : }
1914 :
1915 : }; // class pass_lower_subreg3
1916 :
1917 : } // anon namespace
1918 :
1919 : rtl_opt_pass *
1920 294587 : make_pass_lower_subreg3 (gcc::context *ctxt)
1921 : {
1922 294587 : return new pass_lower_subreg3 (ctxt);
1923 : }
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