Branch data Line data Source code
1 : : /* Code for RTL transformations to satisfy insn constraints.
2 : : Copyright (C) 2010-2024 Free Software Foundation, Inc.
3 : : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 : :
5 : : This file is part of GCC.
6 : :
7 : : GCC is free software; you can redistribute it and/or modify it under
8 : : the terms of the GNU General Public License as published by the Free
9 : : Software Foundation; either version 3, or (at your option) any later
10 : : version.
11 : :
12 : : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : : for more details.
16 : :
17 : : You should have received a copy of the GNU General Public License
18 : : along with GCC; see the file COPYING3. If not see
19 : : <http://www.gnu.org/licenses/>. */
20 : :
21 : :
22 : : /* This file contains code for 3 passes: constraint pass,
23 : : inheritance/split pass, and pass for undoing failed inheritance and
24 : : split.
25 : :
26 : : The major goal of constraint pass is to transform RTL to satisfy
27 : : insn and address constraints by:
28 : : o choosing insn alternatives;
29 : : o generating *reload insns* (or reloads in brief) and *reload
30 : : pseudos* which will get necessary hard registers later;
31 : : o substituting pseudos with equivalent values and removing the
32 : : instructions that initialized those pseudos.
33 : :
34 : : The constraint pass has biggest and most complicated code in LRA.
35 : : There are a lot of important details like:
36 : : o reuse of input reload pseudos to simplify reload pseudo
37 : : allocations;
38 : : o some heuristics to choose insn alternative to improve the
39 : : inheritance;
40 : : o early clobbers etc.
41 : :
42 : : The pass is mimicking former reload pass in alternative choosing
43 : : because the reload pass is oriented to current machine description
44 : : model. It might be changed if the machine description model is
45 : : changed.
46 : :
47 : : There is special code for preventing all LRA and this pass cycling
48 : : in case of bugs.
49 : :
50 : : On the first iteration of the pass we process every instruction and
51 : : choose an alternative for each one. On subsequent iterations we try
52 : : to avoid reprocessing instructions if we can be sure that the old
53 : : choice is still valid.
54 : :
55 : : The inheritance/spilt pass is to transform code to achieve
56 : : ineheritance and live range splitting. It is done on backward
57 : : traversal of EBBs.
58 : :
59 : : The inheritance optimization goal is to reuse values in hard
60 : : registers. There is analogous optimization in old reload pass. The
61 : : inheritance is achieved by following transformation:
62 : :
63 : : reload_p1 <- p reload_p1 <- p
64 : : ... new_p <- reload_p1
65 : : ... => ...
66 : : reload_p2 <- p reload_p2 <- new_p
67 : :
68 : : where p is spilled and not changed between the insns. Reload_p1 is
69 : : also called *original pseudo* and new_p is called *inheritance
70 : : pseudo*.
71 : :
72 : : The subsequent assignment pass will try to assign the same (or
73 : : another if it is not possible) hard register to new_p as to
74 : : reload_p1 or reload_p2.
75 : :
76 : : If the assignment pass fails to assign a hard register to new_p,
77 : : this file will undo the inheritance and restore the original code.
78 : : This is because implementing the above sequence with a spilled
79 : : new_p would make the code much worse. The inheritance is done in
80 : : EBB scope. The above is just a simplified example to get an idea
81 : : of the inheritance as the inheritance is also done for non-reload
82 : : insns.
83 : :
84 : : Splitting (transformation) is also done in EBB scope on the same
85 : : pass as the inheritance:
86 : :
87 : : r <- ... or ... <- r r <- ... or ... <- r
88 : : ... s <- r (new insn -- save)
89 : : ... =>
90 : : ... r <- s (new insn -- restore)
91 : : ... <- r ... <- r
92 : :
93 : : The *split pseudo* s is assigned to the hard register of the
94 : : original pseudo or hard register r.
95 : :
96 : : Splitting is done:
97 : : o In EBBs with high register pressure for global pseudos (living
98 : : in at least 2 BBs) and assigned to hard registers when there
99 : : are more one reloads needing the hard registers;
100 : : o for pseudos needing save/restore code around calls.
101 : :
102 : : If the split pseudo still has the same hard register as the
103 : : original pseudo after the subsequent assignment pass or the
104 : : original pseudo was split, the opposite transformation is done on
105 : : the same pass for undoing inheritance. */
106 : :
107 : : #undef REG_OK_STRICT
108 : :
109 : : #include "config.h"
110 : : #include "system.h"
111 : : #include "coretypes.h"
112 : : #include "backend.h"
113 : : #include "hooks.h"
114 : : #include "target.h"
115 : : #include "rtl.h"
116 : : #include "tree.h"
117 : : #include "predict.h"
118 : : #include "df.h"
119 : : #include "memmodel.h"
120 : : #include "tm_p.h"
121 : : #include "expmed.h"
122 : : #include "optabs.h"
123 : : #include "regs.h"
124 : : #include "ira.h"
125 : : #include "recog.h"
126 : : #include "output.h"
127 : : #include "addresses.h"
128 : : #include "expr.h"
129 : : #include "cfgrtl.h"
130 : : #include "rtl-error.h"
131 : : #include "lra.h"
132 : : #include "lra-int.h"
133 : : #include "print-rtl.h"
134 : : #include "function-abi.h"
135 : : #include "rtl-iter.h"
136 : :
137 : : /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
138 : : insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
139 : : reload insns. */
140 : : static int bb_reload_num;
141 : :
142 : : /* The current insn being processed and corresponding its single set
143 : : (NULL otherwise), its data (basic block, the insn data, the insn
144 : : static data, and the mode of each operand). */
145 : : static rtx_insn *curr_insn;
146 : : static rtx curr_insn_set;
147 : : static basic_block curr_bb;
148 : : static lra_insn_recog_data_t curr_id;
149 : : static struct lra_static_insn_data *curr_static_id;
150 : : static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS];
151 : : /* Mode of the register substituted by its equivalence with VOIDmode
152 : : (e.g. constant) and whose subreg is given operand of the current
153 : : insn. VOIDmode in all other cases. */
154 : : static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS];
155 : :
156 : :
157 : :
158 : : /* Start numbers for new registers and insns at the current constraints
159 : : pass start. */
160 : : static int new_regno_start;
161 : : static int new_insn_uid_start;
162 : :
163 : : /* If LOC is nonnull, strip any outer subreg from it. */
164 : : static inline rtx *
165 : 204332960 : strip_subreg (rtx *loc)
166 : : {
167 : 88862884 : return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
168 : : }
169 : :
170 : : /* Return hard regno of REGNO or if it is was not assigned to a hard
171 : : register, use a hard register from its allocno class. */
172 : : static int
173 : 81372 : get_try_hard_regno (int regno)
174 : : {
175 : 81372 : int hard_regno;
176 : 81372 : enum reg_class rclass;
177 : :
178 : 81372 : if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER)
179 : 81372 : hard_regno = lra_get_regno_hard_regno (regno);
180 : 81372 : if (hard_regno >= 0)
181 : : return hard_regno;
182 : 33163 : rclass = lra_get_allocno_class (regno);
183 : 33163 : if (rclass == NO_REGS)
184 : : return -1;
185 : 31723 : return ira_class_hard_regs[rclass][0];
186 : : }
187 : :
188 : : /* Return the hard regno of X after removing its subreg. If X is not a
189 : : register or a subreg of a register, return -1. If X is a pseudo, use its
190 : : assignment. If X is a hard regno, return the final hard regno which will be
191 : : after elimination. */
192 : : static int
193 : 245395898 : get_hard_regno (rtx x)
194 : : {
195 : 245395898 : rtx reg;
196 : 245395898 : int hard_regno;
197 : :
198 : 245395898 : reg = x;
199 : 245395898 : if (SUBREG_P (x))
200 : 4918547 : reg = SUBREG_REG (x);
201 : 245395898 : if (! REG_P (reg))
202 : : return -1;
203 : 163873165 : if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg)))
204 : 135691590 : hard_regno = lra_get_regno_hard_regno (hard_regno);
205 : 163873165 : if (hard_regno < 0)
206 : : return -1;
207 : 149235159 : if (HARD_REGISTER_NUM_P (REGNO (reg)))
208 : 28181575 : hard_regno = lra_get_elimination_hard_regno (hard_regno);
209 : 149235159 : if (SUBREG_P (x))
210 : 4233894 : hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg),
211 : 4233894 : SUBREG_BYTE (x), GET_MODE (x));
212 : : return hard_regno;
213 : : }
214 : :
215 : : /* If REGNO is a hard register or has been allocated a hard register,
216 : : return the class of that register. If REGNO is a reload pseudo
217 : : created by the current constraints pass, return its allocno class.
218 : : Return NO_REGS otherwise. */
219 : : static enum reg_class
220 : 448145515 : get_reg_class (int regno)
221 : : {
222 : 448145515 : int hard_regno;
223 : :
224 : 448145515 : if (! HARD_REGISTER_NUM_P (hard_regno = regno))
225 : 392891950 : hard_regno = lra_get_regno_hard_regno (regno);
226 : 448145515 : if (hard_regno >= 0)
227 : : {
228 : 281485245 : hard_regno = lra_get_elimination_hard_regno (hard_regno);
229 : 281485245 : return REGNO_REG_CLASS (hard_regno);
230 : : }
231 : 166660270 : if (regno >= new_regno_start)
232 : 56311283 : return lra_get_allocno_class (regno);
233 : : return NO_REGS;
234 : : }
235 : :
236 : : /* Return true if REG_CLASS has enough allocatable hard regs to keep value of
237 : : REG_MODE. */
238 : : static bool
239 : 16245526 : enough_allocatable_hard_regs_p (enum reg_class reg_class,
240 : : enum machine_mode reg_mode)
241 : : {
242 : 16245526 : int i, j, hard_regno, class_size, nregs;
243 : :
244 : 32491052 : if (hard_reg_set_subset_p (reg_class_contents[reg_class], lra_no_alloc_regs))
245 : : return false;
246 : 4965833 : class_size = ira_class_hard_regs_num[reg_class];
247 : 4965833 : for (i = 0; i < class_size; i++)
248 : : {
249 : 4965833 : hard_regno = ira_class_hard_regs[reg_class][i];
250 : 4965833 : nregs = hard_regno_nregs (hard_regno, reg_mode);
251 : 4965833 : if (nregs == 1)
252 : : return true;
253 : 206361 : for (j = 0; j < nregs; j++)
254 : 137574 : if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j)
255 : 137574 : || ! TEST_HARD_REG_BIT (reg_class_contents[reg_class],
256 : : hard_regno + j))
257 : : break;
258 : 68787 : if (j >= nregs)
259 : : return true;
260 : : }
261 : : return false;
262 : : }
263 : :
264 : : /* True if C is a non-empty register class that has too few registers
265 : : to be safely used as a reload target class. */
266 : : #define SMALL_REGISTER_CLASS_P(C) \
267 : : (ira_class_hard_regs_num [(C)] == 1 \
268 : : || (ira_class_hard_regs_num [(C)] >= 1 \
269 : : && targetm.class_likely_spilled_p (C)))
270 : :
271 : : /* Return true if REG satisfies (or will satisfy) reg class constraint
272 : : CL. Use elimination first if REG is a hard register. If REG is a
273 : : reload pseudo created by this constraints pass, assume that it will
274 : : be allocated a hard register from its allocno class, but allow that
275 : : class to be narrowed to CL if it is currently a superset of CL and
276 : : if either:
277 : :
278 : : - ALLOW_ALL_RELOAD_CLASS_CHANGES_P is true or
279 : : - the instruction we're processing is not a reload move.
280 : :
281 : : If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
282 : : REGNO (reg), or NO_REGS if no change in its class was needed. */
283 : : static bool
284 : 193883453 : in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class,
285 : : bool allow_all_reload_class_changes_p = false)
286 : : {
287 : 193883453 : enum reg_class rclass, common_class;
288 : 193883453 : machine_mode reg_mode;
289 : 193883453 : rtx src;
290 : 193883453 : int regno = REGNO (reg);
291 : :
292 : 193883453 : if (new_class != NULL)
293 : 100588832 : *new_class = NO_REGS;
294 : 193883453 : if (regno < FIRST_PSEUDO_REGISTER)
295 : : {
296 : 24339405 : rtx final_reg = reg;
297 : 24339405 : rtx *final_loc = &final_reg;
298 : :
299 : 24339405 : lra_eliminate_reg_if_possible (final_loc);
300 : 24339405 : return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc));
301 : : }
302 : 169544048 : reg_mode = GET_MODE (reg);
303 : 169544048 : rclass = get_reg_class (regno);
304 : 169544048 : src = curr_insn_set != NULL ? SET_SRC (curr_insn_set) : NULL;
305 : 169544048 : if (regno < new_regno_start
306 : : /* Do not allow the constraints for reload instructions to
307 : : influence the classes of new pseudos. These reloads are
308 : : typically moves that have many alternatives, and restricting
309 : : reload pseudos for one alternative may lead to situations
310 : : where other reload pseudos are no longer allocatable. */
311 : 169544048 : || (!allow_all_reload_class_changes_p
312 : 13684047 : && INSN_UID (curr_insn) >= new_insn_uid_start
313 : 13243966 : && src != NULL
314 : 13243966 : && ((REG_P (src) || MEM_P (src))
315 : 993009 : || (GET_CODE (src) == SUBREG
316 : 654089 : && (REG_P (SUBREG_REG (src)) || MEM_P (SUBREG_REG (src)))))))
317 : : /* When we don't know what class will be used finally for reload
318 : : pseudos, we use ALL_REGS. */
319 : 12905046 : return ((regno >= new_regno_start && rclass == ALL_REGS)
320 : 166200842 : || (rclass != NO_REGS && ira_class_subset_p[rclass][cl]
321 : 181674600 : && ! hard_reg_set_subset_p (reg_class_contents[cl],
322 : : lra_no_alloc_regs)));
323 : : else
324 : : {
325 : 16245526 : common_class = ira_reg_class_subset[rclass][cl];
326 : 16245526 : if (new_class != NULL)
327 : 4361753 : *new_class = common_class;
328 : 16245526 : return (enough_allocatable_hard_regs_p (common_class, reg_mode)
329 : : /* Do not permit reload insn operand matching (new_class == NULL
330 : : case) if the new class is too small. */
331 : 16245526 : && (new_class != NULL || common_class == rclass
332 : 530988 : || !SMALL_REGISTER_CLASS_P (common_class)));
333 : : }
334 : : }
335 : :
336 : : /* Return true if REGNO satisfies a memory constraint. */
337 : : static bool
338 : 48072452 : in_mem_p (int regno)
339 : : {
340 : 0 : return get_reg_class (regno) == NO_REGS;
341 : : }
342 : :
343 : : /* Return true if ADDR is a valid memory address for mode MODE in address
344 : : space AS, and check that each pseudo has the proper kind of hard
345 : : reg. */
346 : : static bool
347 : 32321603 : valid_address_p (machine_mode mode ATTRIBUTE_UNUSED,
348 : : rtx addr, addr_space_t as)
349 : : {
350 : : #ifdef GO_IF_LEGITIMATE_ADDRESS
351 : : lra_assert (ADDR_SPACE_GENERIC_P (as));
352 : : GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
353 : : return false;
354 : :
355 : : win:
356 : : return true;
357 : : #else
358 : 26878 : return targetm.addr_space.legitimate_address_p (mode, addr, 0, as,
359 : 26878 : ERROR_MARK);
360 : : #endif
361 : : }
362 : :
363 : : namespace {
364 : : /* Temporarily eliminates registers in an address (for the lifetime of
365 : : the object). */
366 : : class address_eliminator {
367 : : public:
368 : : address_eliminator (struct address_info *ad);
369 : : ~address_eliminator ();
370 : :
371 : : private:
372 : : struct address_info *m_ad;
373 : : rtx *m_base_loc;
374 : : rtx m_base_reg;
375 : : rtx *m_index_loc;
376 : : rtx m_index_reg;
377 : : };
378 : : }
379 : :
380 : 66829326 : address_eliminator::address_eliminator (struct address_info *ad)
381 : 66829326 : : m_ad (ad),
382 : 66829326 : m_base_loc (strip_subreg (ad->base_term)),
383 : 66829326 : m_base_reg (NULL_RTX),
384 : 66829326 : m_index_loc (strip_subreg (ad->index_term)),
385 : 66829326 : m_index_reg (NULL_RTX)
386 : : {
387 : 66829326 : if (m_base_loc != NULL)
388 : : {
389 : 54908318 : m_base_reg = *m_base_loc;
390 : : /* If we have non-legitimate address which is decomposed not in
391 : : the way we expected, don't do elimination here. In such case
392 : : the address will be reloaded and elimination will be done in
393 : : reload insn finally. */
394 : 54908318 : if (REG_P (m_base_reg))
395 : 54908318 : lra_eliminate_reg_if_possible (m_base_loc);
396 : 54908318 : if (m_ad->base_term2 != NULL)
397 : 0 : *m_ad->base_term2 = *m_ad->base_term;
398 : : }
399 : 66829326 : if (m_index_loc != NULL)
400 : : {
401 : 3008397 : m_index_reg = *m_index_loc;
402 : 3008397 : if (REG_P (m_index_reg))
403 : 3008397 : lra_eliminate_reg_if_possible (m_index_loc);
404 : : }
405 : 66829326 : }
406 : :
407 : 66829326 : address_eliminator::~address_eliminator ()
408 : : {
409 : 66829326 : if (m_base_loc && *m_base_loc != m_base_reg)
410 : : {
411 : 38564454 : *m_base_loc = m_base_reg;
412 : 38564454 : if (m_ad->base_term2 != NULL)
413 : 0 : *m_ad->base_term2 = *m_ad->base_term;
414 : : }
415 : 66829326 : if (m_index_loc && *m_index_loc != m_index_reg)
416 : 0 : *m_index_loc = m_index_reg;
417 : 66829326 : }
418 : :
419 : : /* Return true if the eliminated form of AD is a legitimate target address.
420 : : If OP is a MEM, AD is the address within OP, otherwise OP should be
421 : : ignored. CONSTRAINT is one constraint that the operand may need
422 : : to meet. */
423 : : static bool
424 : 32294673 : valid_address_p (rtx op, struct address_info *ad,
425 : : enum constraint_num constraint)
426 : : {
427 : 32294673 : address_eliminator eliminator (ad);
428 : :
429 : : /* Allow a memory OP if it matches CONSTRAINT, even if CONSTRAINT is more
430 : : forgiving than "m".
431 : : Need to extract memory from op for special memory constraint,
432 : : i.e. bcst_mem_operand in i386 backend. */
433 : 32294673 : if (MEM_P (extract_mem_from_operand (op))
434 : : && insn_extra_relaxed_memory_constraint (constraint)
435 : : && constraint_satisfied_p (op, constraint))
436 : : return true;
437 : :
438 : 32294673 : return valid_address_p (ad->mode, *ad->outer, ad->as);
439 : 32294673 : }
440 : :
441 : : /* For special_memory_operand, it could be false for MEM_P (op),
442 : : i.e. bcst_mem_operand in i386 backend.
443 : : Extract and return real memory operand or op. */
444 : : rtx
445 : 480868581 : extract_mem_from_operand (rtx op)
446 : : {
447 : 481763025 : for (rtx x = op;; x = XEXP (x, 0))
448 : : {
449 : 481763025 : if (MEM_P (x))
450 : 140676778 : return x;
451 : 341086247 : if (GET_RTX_LENGTH (GET_CODE (x)) != 1
452 : 278595154 : || GET_RTX_FORMAT (GET_CODE (x))[0] != 'e')
453 : : break;
454 : : }
455 : : return op;
456 : : }
457 : :
458 : : /* Return true if the eliminated form of memory reference OP satisfies
459 : : extra (special) memory constraint CONSTRAINT. */
460 : : static bool
461 : 33171964 : satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
462 : : {
463 : 33171964 : struct address_info ad;
464 : 33171964 : rtx mem = extract_mem_from_operand (op);
465 : 33171964 : if (!MEM_P (mem))
466 : : return false;
467 : :
468 : 32610263 : decompose_mem_address (&ad, mem);
469 : 32610263 : address_eliminator eliminator (&ad);
470 : 32610263 : return constraint_satisfied_p (op, constraint);
471 : 32610263 : }
472 : :
473 : : /* Return true if the eliminated form of address AD satisfies extra
474 : : address constraint CONSTRAINT. */
475 : : static bool
476 : 1924390 : satisfies_address_constraint_p (struct address_info *ad,
477 : : enum constraint_num constraint)
478 : : {
479 : 1924390 : address_eliminator eliminator (ad);
480 : 1924390 : return constraint_satisfied_p (*ad->outer, constraint);
481 : 1924390 : }
482 : :
483 : : /* Return true if the eliminated form of address OP satisfies extra
484 : : address constraint CONSTRAINT. */
485 : : static bool
486 : 935040 : satisfies_address_constraint_p (rtx op, enum constraint_num constraint)
487 : : {
488 : 935040 : struct address_info ad;
489 : :
490 : 935040 : decompose_lea_address (&ad, &op);
491 : 935040 : return satisfies_address_constraint_p (&ad, constraint);
492 : : }
493 : :
494 : : /* Initiate equivalences for LRA. As we keep original equivalences
495 : : before any elimination, we need to make copies otherwise any change
496 : : in insns might change the equivalences. */
497 : : void
498 : 1426764 : lra_init_equiv (void)
499 : : {
500 : 1426764 : ira_expand_reg_equiv ();
501 : 65390790 : for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
502 : : {
503 : 63964026 : rtx res;
504 : :
505 : 63964026 : if ((res = ira_reg_equiv[i].memory) != NULL_RTX)
506 : 2889441 : ira_reg_equiv[i].memory = copy_rtx (res);
507 : 63964026 : if ((res = ira_reg_equiv[i].invariant) != NULL_RTX)
508 : 738746 : ira_reg_equiv[i].invariant = copy_rtx (res);
509 : : }
510 : 1426764 : }
511 : :
512 : : static rtx loc_equivalence_callback (rtx, const_rtx, void *);
513 : :
514 : : /* Update equivalence for REGNO. We need to this as the equivalence
515 : : might contain other pseudos which are changed by their
516 : : equivalences. */
517 : : static void
518 : 184465550 : update_equiv (int regno)
519 : : {
520 : 184465550 : rtx x;
521 : :
522 : 184465550 : if ((x = ira_reg_equiv[regno].memory) != NULL_RTX)
523 : 8518663 : ira_reg_equiv[regno].memory
524 : 8518663 : = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
525 : : NULL_RTX);
526 : 184465550 : if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX)
527 : 2225463 : ira_reg_equiv[regno].invariant
528 : 2225463 : = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback,
529 : : NULL_RTX);
530 : 184465550 : }
531 : :
532 : : /* If we have decided to substitute X with another value, return that
533 : : value, otherwise return X. */
534 : : static rtx
535 : 396901737 : get_equiv (rtx x)
536 : : {
537 : 396901737 : int regno;
538 : 396901737 : rtx res;
539 : :
540 : 267396320 : if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER
541 : 177282646 : || ! ira_reg_equiv[regno].defined_p
542 : 23211296 : || ! ira_reg_equiv[regno].profitable_p
543 : 420080764 : || lra_get_regno_hard_regno (regno) >= 0)
544 : 393714061 : return x;
545 : 3187676 : if ((res = ira_reg_equiv[regno].memory) != NULL_RTX)
546 : : {
547 : 1940224 : if (targetm.cannot_substitute_mem_equiv_p (res))
548 : : return x;
549 : : return res;
550 : : }
551 : 1247452 : if ((res = ira_reg_equiv[regno].constant) != NULL_RTX)
552 : : return res;
553 : 601996 : if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX)
554 : : return res;
555 : 0 : gcc_unreachable ();
556 : : }
557 : :
558 : : /* If we have decided to substitute X with the equivalent value,
559 : : return that value after elimination for INSN, otherwise return
560 : : X. */
561 : : static rtx
562 : 221170266 : get_equiv_with_elimination (rtx x, rtx_insn *insn)
563 : : {
564 : 221170266 : rtx res = get_equiv (x);
565 : :
566 : 221170266 : if (x == res || CONSTANT_P (res))
567 : : return res;
568 : 906274 : return lra_eliminate_regs_1 (insn, res, GET_MODE (res),
569 : 906274 : false, false, 0, true);
570 : : }
571 : :
572 : : /* Set up curr_operand_mode. */
573 : : static void
574 : 98056148 : init_curr_operand_mode (void)
575 : : {
576 : 98056148 : int nop = curr_static_id->n_operands;
577 : 305620865 : for (int i = 0; i < nop; i++)
578 : : {
579 : 207564717 : machine_mode mode = GET_MODE (*curr_id->operand_loc[i]);
580 : 207564717 : if (mode == VOIDmode)
581 : : {
582 : : /* The .md mode for address operands is the mode of the
583 : : addressed value rather than the mode of the address itself. */
584 : 39831855 : if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address)
585 : 95 : mode = Pmode;
586 : : else
587 : 39831760 : mode = curr_static_id->operand[i].mode;
588 : : }
589 : 207564717 : curr_operand_mode[i] = mode;
590 : : }
591 : 98056148 : }
592 : :
593 : :
594 : :
595 : : /* The page contains code to reuse input reloads. */
596 : :
597 : : /* Structure describes input reload of the current insns. */
598 : : struct input_reload
599 : : {
600 : : /* True for input reload of matched operands. */
601 : : bool match_p;
602 : : /* Reloaded value. */
603 : : rtx input;
604 : : /* Reload pseudo used. */
605 : : rtx reg;
606 : : };
607 : :
608 : : /* The number of elements in the following array. */
609 : : static int curr_insn_input_reloads_num;
610 : : /* Array containing info about input reloads. It is used to find the
611 : : same input reload and reuse the reload pseudo in this case. */
612 : : static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS];
613 : :
614 : : /* Initiate data concerning reuse of input reloads for the current
615 : : insn. */
616 : : static void
617 : 98056148 : init_curr_insn_input_reloads (void)
618 : : {
619 : 98056148 : curr_insn_input_reloads_num = 0;
620 : 98056148 : }
621 : :
622 : : /* The canonical form of an rtx inside a MEM is not necessarily the same as the
623 : : canonical form of the rtx outside the MEM. Fix this up in the case that
624 : : we're reloading an address (and therefore pulling it outside a MEM). */
625 : : static rtx
626 : 72 : canonicalize_reload_addr (rtx addr)
627 : : {
628 : 72 : subrtx_var_iterator::array_type array;
629 : 246 : FOR_EACH_SUBRTX_VAR (iter, array, addr, NONCONST)
630 : : {
631 : 174 : rtx x = *iter;
632 : 174 : if (GET_CODE (x) == MULT && CONST_INT_P (XEXP (x, 1)))
633 : : {
634 : 14 : const HOST_WIDE_INT ci = INTVAL (XEXP (x, 1));
635 : 188 : const int pwr2 = exact_log2 (ci);
636 : 14 : if (pwr2 > 0)
637 : : {
638 : : /* Rewrite this to use a shift instead, which is canonical when
639 : : outside of a MEM. */
640 : 14 : PUT_CODE (x, ASHIFT);
641 : 14 : XEXP (x, 1) = GEN_INT (pwr2);
642 : : }
643 : : }
644 : : }
645 : :
646 : 72 : return addr;
647 : 72 : }
648 : :
649 : : /* Create a new pseudo using MODE, RCLASS, EXCLUDE_START_HARD_REGS, ORIGINAL or
650 : : reuse an existing reload pseudo. Don't reuse an existing reload pseudo if
651 : : IN_SUBREG_P is true and the reused pseudo should be wrapped up in a SUBREG.
652 : : The result pseudo is returned through RESULT_REG. Return TRUE if we created
653 : : a new pseudo, FALSE if we reused an existing reload pseudo. Use TITLE to
654 : : describe new registers for debug purposes. */
655 : : static bool
656 : 3073368 : get_reload_reg (enum op_type type, machine_mode mode, rtx original,
657 : : enum reg_class rclass, HARD_REG_SET *exclude_start_hard_regs,
658 : : bool in_subreg_p, const char *title, rtx *result_reg)
659 : : {
660 : 3073368 : int i, regno;
661 : 3073368 : enum reg_class new_class;
662 : 3073368 : bool unique_p = false;
663 : :
664 : 3073368 : if (type == OP_OUT)
665 : : {
666 : : /* Output reload registers tend to start out with a conservative
667 : : choice of register class. Usually this is ALL_REGS, although
668 : : a target might narrow it (for performance reasons) through
669 : : targetm.preferred_reload_class. It's therefore quite common
670 : : for a reload instruction to require a more restrictive class
671 : : than the class that was originally assigned to the reload register.
672 : :
673 : : In these situations, it's more efficient to refine the choice
674 : : of register class rather than create a second reload register.
675 : : This also helps to avoid cycling for registers that are only
676 : : used by reload instructions. */
677 : 870856 : if (REG_P (original)
678 : 649652 : && (int) REGNO (original) >= new_regno_start
679 : 2644 : && INSN_UID (curr_insn) >= new_insn_uid_start
680 : 873250 : && in_class_p (original, rclass, &new_class, true))
681 : : {
682 : 0 : unsigned int regno = REGNO (original);
683 : 0 : if (lra_dump_file != NULL)
684 : : {
685 : 0 : fprintf (lra_dump_file, " Reuse r%d for output ", regno);
686 : 0 : dump_value_slim (lra_dump_file, original, 1);
687 : : }
688 : 0 : if (new_class != lra_get_allocno_class (regno))
689 : 0 : lra_change_class (regno, new_class, ", change to", false);
690 : 0 : if (lra_dump_file != NULL)
691 : 0 : fprintf (lra_dump_file, "\n");
692 : 0 : *result_reg = original;
693 : 0 : return false;
694 : : }
695 : 870856 : *result_reg
696 : 870856 : = lra_create_new_reg_with_unique_value (mode, original, rclass,
697 : : exclude_start_hard_regs, title);
698 : 870856 : return true;
699 : : }
700 : : /* Prevent reuse value of expression with side effects,
701 : : e.g. volatile memory. */
702 : 2202512 : if (! side_effects_p (original))
703 : 2429331 : for (i = 0; i < curr_insn_input_reloads_num; i++)
704 : : {
705 : 234406 : if (! curr_insn_input_reloads[i].match_p
706 : 88215 : && rtx_equal_p (curr_insn_input_reloads[i].input, original)
707 : 242007 : && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class))
708 : : {
709 : 7587 : rtx reg = curr_insn_input_reloads[i].reg;
710 : 7587 : regno = REGNO (reg);
711 : : /* If input is equal to original and both are VOIDmode,
712 : : GET_MODE (reg) might be still different from mode.
713 : : Ensure we don't return *result_reg with wrong mode. */
714 : 7587 : if (GET_MODE (reg) != mode)
715 : : {
716 : 0 : if (in_subreg_p)
717 : 0 : continue;
718 : 0 : if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)),
719 : 0 : GET_MODE_SIZE (mode)))
720 : 0 : continue;
721 : 0 : reg = lowpart_subreg (mode, reg, GET_MODE (reg));
722 : 0 : if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
723 : 0 : continue;
724 : : }
725 : 7587 : *result_reg = reg;
726 : 7587 : if (lra_dump_file != NULL)
727 : : {
728 : 0 : fprintf (lra_dump_file, " Reuse r%d for reload ", regno);
729 : 0 : dump_value_slim (lra_dump_file, original, 1);
730 : : }
731 : 15174 : if (new_class != lra_get_allocno_class (regno))
732 : 3721 : lra_change_class (regno, new_class, ", change to", false);
733 : 7587 : if (lra_dump_file != NULL)
734 : 0 : fprintf (lra_dump_file, "\n");
735 : 7587 : return false;
736 : : }
737 : : /* If we have an input reload with a different mode, make sure it
738 : : will get a different hard reg. */
739 : 226819 : else if (REG_P (original)
740 : 184319 : && REG_P (curr_insn_input_reloads[i].input)
741 : 151894 : && REGNO (original) == REGNO (curr_insn_input_reloads[i].input)
742 : 226819 : && (GET_MODE (original)
743 : 3180 : != GET_MODE (curr_insn_input_reloads[i].input)))
744 : : unique_p = true;
745 : : }
746 : 4389850 : *result_reg = (unique_p
747 : 2194925 : ? lra_create_new_reg_with_unique_value
748 : 2194925 : : lra_create_new_reg) (mode, original, rclass,
749 : : exclude_start_hard_regs, title);
750 : 2194925 : lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
751 : 2194925 : curr_insn_input_reloads[curr_insn_input_reloads_num].input = original;
752 : 2194925 : curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false;
753 : 2194925 : curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg;
754 : 2194925 : return true;
755 : : }
756 : :
757 : :
758 : : /* The page contains major code to choose the current insn alternative
759 : : and generate reloads for it. */
760 : :
761 : : /* Return the offset from REGNO of the least significant register
762 : : in (reg:MODE REGNO).
763 : :
764 : : This function is used to tell whether two registers satisfy
765 : : a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
766 : :
767 : : REGNO1 + lra_constraint_offset (REGNO1, MODE1)
768 : : == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
769 : : int
770 : 30619412 : lra_constraint_offset (int regno, machine_mode mode)
771 : : {
772 : 30619412 : lra_assert (regno < FIRST_PSEUDO_REGISTER);
773 : :
774 : 30619412 : scalar_int_mode int_mode;
775 : 30619412 : if (WORDS_BIG_ENDIAN
776 : : && is_a <scalar_int_mode> (mode, &int_mode)
777 : : && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD)
778 : : return hard_regno_nregs (regno, mode) - 1;
779 : 30619412 : return 0;
780 : : }
781 : :
782 : : /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
783 : : if they are the same hard reg, and has special hacks for
784 : : auto-increment and auto-decrement. This is specifically intended for
785 : : process_alt_operands to use in determining whether two operands
786 : : match. X is the operand whose number is the lower of the two.
787 : :
788 : : It is supposed that X is the output operand and Y is the input
789 : : operand. Y_HARD_REGNO is the final hard regno of register Y or
790 : : register in subreg Y as we know it now. Otherwise, it is a
791 : : negative value. */
792 : : static bool
793 : 38911163 : operands_match_p (rtx x, rtx y, int y_hard_regno)
794 : : {
795 : 38911163 : int i;
796 : 38911163 : RTX_CODE code = GET_CODE (x);
797 : 38911163 : const char *fmt;
798 : :
799 : 38911163 : if (x == y)
800 : : return true;
801 : 34670766 : if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
802 : 16696295 : && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
803 : : {
804 : 16642890 : int j;
805 : :
806 : 16642890 : i = get_hard_regno (x);
807 : 16642890 : if (i < 0)
808 : 864894 : goto slow;
809 : :
810 : 15777996 : if ((j = y_hard_regno) < 0)
811 : 468290 : goto slow;
812 : :
813 : 15309706 : i += lra_constraint_offset (i, GET_MODE (x));
814 : 15309706 : j += lra_constraint_offset (j, GET_MODE (y));
815 : :
816 : 15309706 : return i == j;
817 : : }
818 : :
819 : : /* If two operands must match, because they are really a single
820 : : operand of an assembler insn, then two post-increments are invalid
821 : : because the assembler insn would increment only once. On the
822 : : other hand, a post-increment matches ordinary indexing if the
823 : : post-increment is the output operand. */
824 : 18027876 : if (code == POST_DEC || code == POST_INC || code == POST_MODIFY)
825 : 0 : return operands_match_p (XEXP (x, 0), y, y_hard_regno);
826 : :
827 : : /* Two pre-increments are invalid because the assembler insn would
828 : : increment only once. On the other hand, a pre-increment matches
829 : : ordinary indexing if the pre-increment is the input operand. */
830 : 18027876 : if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC
831 : 18027876 : || GET_CODE (y) == PRE_MODIFY)
832 : 0 : return operands_match_p (x, XEXP (y, 0), -1);
833 : :
834 : 18027876 : slow:
835 : :
836 : 19361060 : if (code == REG && REG_P (y))
837 : 1257881 : return REGNO (x) == REGNO (y);
838 : :
839 : 53959 : if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
840 : 5079 : && x == SUBREG_REG (y))
841 : : return true;
842 : 18103179 : if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
843 : 45114 : && SUBREG_REG (x) == y)
844 : : return true;
845 : :
846 : : /* Now we have disposed of all the cases in which different rtx
847 : : codes can match. */
848 : 18102972 : if (code != GET_CODE (y))
849 : : return false;
850 : :
851 : : /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
852 : 595228 : if (GET_MODE (x) != GET_MODE (y))
853 : : return false;
854 : :
855 : 594559 : switch (code)
856 : : {
857 : : CASE_CONST_UNIQUE:
858 : : return false;
859 : :
860 : 0 : case CONST_VECTOR:
861 : 0 : if (!same_vector_encodings_p (x, y))
862 : : return false;
863 : : break;
864 : :
865 : 0 : case LABEL_REF:
866 : 0 : return label_ref_label (x) == label_ref_label (y);
867 : 22 : case SYMBOL_REF:
868 : 22 : return XSTR (x, 0) == XSTR (y, 0);
869 : :
870 : : default:
871 : : break;
872 : : }
873 : :
874 : : /* Compare the elements. If any pair of corresponding elements fail
875 : : to match, return false for the whole things. */
876 : :
877 : 578782 : fmt = GET_RTX_FORMAT (code);
878 : 1652786 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
879 : : {
880 : 1135763 : int val, j;
881 : 1135763 : switch (fmt[i])
882 : : {
883 : 0 : case 'w':
884 : 0 : if (XWINT (x, i) != XWINT (y, i))
885 : : return false;
886 : : break;
887 : :
888 : 230 : case 'i':
889 : 230 : if (XINT (x, i) != XINT (y, i))
890 : : return false;
891 : : break;
892 : :
893 : 25017 : case 'p':
894 : 25017 : if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y)))
895 : : return false;
896 : : break;
897 : :
898 : 823176 : case 'e':
899 : 823176 : val = operands_match_p (XEXP (x, i), XEXP (y, i), -1);
900 : 823176 : if (val == 0)
901 : : return false;
902 : : break;
903 : :
904 : : case '0':
905 : : break;
906 : :
907 : 230 : case 'E':
908 : 230 : if (XVECLEN (x, i) != XVECLEN (y, i))
909 : : return false;
910 : 460 : for (j = XVECLEN (x, i) - 1; j >= 0; --j)
911 : : {
912 : 230 : val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1);
913 : 230 : if (val == 0)
914 : : return false;
915 : : }
916 : : break;
917 : :
918 : : /* It is believed that rtx's at this level will never
919 : : contain anything but integers and other rtx's, except for
920 : : within LABEL_REFs and SYMBOL_REFs. */
921 : 0 : default:
922 : 0 : gcc_unreachable ();
923 : : }
924 : : }
925 : : return true;
926 : : }
927 : :
928 : : /* True if X is a constant that can be forced into the constant pool.
929 : : MODE is the mode of the operand, or VOIDmode if not known. */
930 : : #define CONST_POOL_OK_P(MODE, X) \
931 : : ((MODE) != VOIDmode \
932 : : && CONSTANT_P (X) \
933 : : && GET_CODE (X) != HIGH \
934 : : && GET_MODE_SIZE (MODE).is_constant () \
935 : : && !targetm.cannot_force_const_mem (MODE, X))
936 : :
937 : : /* If REG is a reload pseudo, try to make its class satisfying CL. */
938 : : static void
939 : 3133314 : narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
940 : : {
941 : 3133314 : enum reg_class rclass;
942 : :
943 : : /* Do not make more accurate class from reloads generated. They are
944 : : mostly moves with a lot of constraints. Making more accurate
945 : : class may results in very narrow class and impossibility of find
946 : : registers for several reloads of one insn. */
947 : 3133314 : if (INSN_UID (curr_insn) >= new_insn_uid_start)
948 : 3133295 : return;
949 : 3133158 : if (GET_CODE (reg) == SUBREG)
950 : 135313 : reg = SUBREG_REG (reg);
951 : 3133158 : if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
952 : : return;
953 : 19 : if (in_class_p (reg, cl, &rclass) && rclass != cl)
954 : 0 : lra_change_class (REGNO (reg), rclass, " Change to", true);
955 : : }
956 : :
957 : : /* Searches X for any reference to a reg with the same value as REGNO,
958 : : returning the rtx of the reference found if any. Otherwise,
959 : : returns NULL_RTX. */
960 : : static rtx
961 : 526968 : regno_val_use_in (unsigned int regno, rtx x)
962 : : {
963 : 526968 : const char *fmt;
964 : 526968 : int i, j;
965 : 526968 : rtx tem;
966 : :
967 : 526968 : if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val)
968 : : return x;
969 : :
970 : 526644 : fmt = GET_RTX_FORMAT (GET_CODE (x));
971 : 1059053 : for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
972 : : {
973 : 532409 : if (fmt[i] == 'e')
974 : : {
975 : 7119 : if ((tem = regno_val_use_in (regno, XEXP (x, i))))
976 : 0 : return tem;
977 : : }
978 : 525290 : else if (fmt[i] == 'E')
979 : 0 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
980 : 0 : if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j))))
981 : 0 : return tem;
982 : : }
983 : :
984 : : return NULL_RTX;
985 : : }
986 : :
987 : : /* Return true if all current insn non-output operands except INS (it
988 : : has a negaitve end marker) do not use pseudos with the same value
989 : : as REGNO. */
990 : : static bool
991 : 2 : check_conflict_input_operands (int regno, signed char *ins)
992 : : {
993 : 2 : int in;
994 : 2 : int n_operands = curr_static_id->n_operands;
995 : :
996 : 8 : for (int nop = 0; nop < n_operands; nop++)
997 : 7 : if (! curr_static_id->operand[nop].is_operator
998 : 7 : && curr_static_id->operand[nop].type != OP_OUT)
999 : : {
1000 : 5 : for (int i = 0; (in = ins[i]) >= 0; i++)
1001 : 4 : if (in == nop)
1002 : : break;
1003 : 3 : if (in < 0
1004 : 3 : && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX)
1005 : : return false;
1006 : : }
1007 : : return true;
1008 : : }
1009 : :
1010 : : /* Generate reloads for matching OUT and INS (array of input operand numbers
1011 : : with end marker -1) with reg class GOAL_CLASS and EXCLUDE_START_HARD_REGS,
1012 : : considering output operands OUTS (similar array to INS) needing to be in
1013 : : different registers. Add input and output reloads correspondingly to the
1014 : : lists *BEFORE and *AFTER. OUT might be negative. In this case we generate
1015 : : input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag
1016 : : that the output operand is early clobbered for chosen alternative. */
1017 : : static void
1018 : 1566657 : match_reload (signed char out, signed char *ins, signed char *outs,
1019 : : enum reg_class goal_class, HARD_REG_SET *exclude_start_hard_regs,
1020 : : rtx_insn **before, rtx_insn **after, bool early_clobber_p)
1021 : : {
1022 : 1566657 : bool out_conflict;
1023 : 1566657 : int i, in;
1024 : 1566657 : rtx new_in_reg, new_out_reg, reg;
1025 : 1566657 : machine_mode inmode, outmode;
1026 : 1566657 : rtx in_rtx = *curr_id->operand_loc[ins[0]];
1027 : 1566657 : rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out];
1028 : :
1029 : 1566657 : inmode = curr_operand_mode[ins[0]];
1030 : 1566657 : outmode = out < 0 ? inmode : curr_operand_mode[out];
1031 : 1566657 : push_to_sequence (*before);
1032 : 1566657 : if (inmode != outmode)
1033 : : {
1034 : : /* process_alt_operands has already checked that the mode sizes
1035 : : are ordered. */
1036 : 135909 : if (partial_subreg_p (outmode, inmode))
1037 : : {
1038 : 1805 : bool asm_p = asm_noperands (PATTERN (curr_insn)) >= 0;
1039 : 1805 : int hr;
1040 : 1805 : HARD_REG_SET temp_hard_reg_set;
1041 : :
1042 : 19 : if (asm_p && (hr = get_hard_regno (out_rtx)) >= 0
1043 : 1808 : && hard_regno_nregs (hr, inmode) > 1)
1044 : : {
1045 : : /* See gcc.c-torture/execute/20030222-1.c.
1046 : : Consider the code for 32-bit (e.g. BE) target:
1047 : : int i, v; long x; x = v; asm ("" : "=r" (i) : "0" (x));
1048 : : We generate the following RTL with reload insns:
1049 : : 1. subreg:si(x:di, 0) = 0;
1050 : : 2. subreg:si(x:di, 4) = v:si;
1051 : : 3. t:di = x:di, dead x;
1052 : : 4. asm ("" : "=r" (subreg:si(t:di,4)) : "0" (t:di))
1053 : : 5. i:si = subreg:si(t:di,4);
1054 : : If we assign hard reg of x to t, dead code elimination
1055 : : will remove insn #2 and we will use unitialized hard reg.
1056 : : So exclude the hard reg of x for t. We could ignore this
1057 : : problem for non-empty asm using all x value but it is hard to
1058 : : check that the asm are expanded into insn realy using x
1059 : : and setting r. */
1060 : 0 : CLEAR_HARD_REG_SET (temp_hard_reg_set);
1061 : 0 : if (exclude_start_hard_regs != NULL)
1062 : 0 : temp_hard_reg_set = *exclude_start_hard_regs;
1063 : 0 : SET_HARD_REG_BIT (temp_hard_reg_set, hr);
1064 : 0 : exclude_start_hard_regs = &temp_hard_reg_set;
1065 : : }
1066 : 3610 : reg = new_in_reg
1067 : 1805 : = lra_create_new_reg_with_unique_value (inmode, in_rtx, goal_class,
1068 : : exclude_start_hard_regs,
1069 : : "");
1070 : 1805 : new_out_reg = gen_lowpart_SUBREG (outmode, reg);
1071 : 1805 : LRA_SUBREG_P (new_out_reg) = 1;
1072 : : /* If the input reg is dying here, we can use the same hard
1073 : : register for REG and IN_RTX. We do it only for original
1074 : : pseudos as reload pseudos can die although original
1075 : : pseudos still live where reload pseudos dies. */
1076 : 1678 : if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start
1077 : 1641 : && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1078 : 3039 : && (!early_clobber_p
1079 : 2 : || check_conflict_input_operands(REGNO (in_rtx), ins)))
1080 : 1233 : lra_assign_reg_val (REGNO (in_rtx), REGNO (reg));
1081 : : }
1082 : : else
1083 : : {
1084 : 268208 : reg = new_out_reg
1085 : 134104 : = lra_create_new_reg_with_unique_value (outmode, out_rtx,
1086 : : goal_class,
1087 : : exclude_start_hard_regs,
1088 : : "");
1089 : 134104 : new_in_reg = gen_lowpart_SUBREG (inmode, reg);
1090 : : /* NEW_IN_REG is non-paradoxical subreg. We don't want
1091 : : NEW_OUT_REG living above. We add clobber clause for
1092 : : this. This is just a temporary clobber. We can remove
1093 : : it at the end of LRA work. */
1094 : 134104 : rtx_insn *clobber = emit_clobber (new_out_reg);
1095 : 134104 : LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
1096 : 134104 : LRA_SUBREG_P (new_in_reg) = 1;
1097 : 134104 : if (GET_CODE (in_rtx) == SUBREG)
1098 : : {
1099 : 1469 : rtx subreg_reg = SUBREG_REG (in_rtx);
1100 : :
1101 : : /* If SUBREG_REG is dying here and sub-registers IN_RTX
1102 : : and NEW_IN_REG are similar, we can use the same hard
1103 : : register for REG and SUBREG_REG. */
1104 : 1469 : if (REG_P (subreg_reg)
1105 : 1469 : && (int) REGNO (subreg_reg) < lra_new_regno_start
1106 : 1469 : && GET_MODE (subreg_reg) == outmode
1107 : 718 : && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg))
1108 : 718 : && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))
1109 : 1546 : && (! early_clobber_p
1110 : 0 : || check_conflict_input_operands (REGNO (subreg_reg),
1111 : : ins)))
1112 : 77 : lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg));
1113 : : }
1114 : : }
1115 : : }
1116 : : else
1117 : : {
1118 : : /* Pseudos have values -- see comments for lra_reg_info.
1119 : : Different pseudos with the same value do not conflict even if
1120 : : they live in the same place. When we create a pseudo we
1121 : : assign value of original pseudo (if any) from which we
1122 : : created the new pseudo. If we create the pseudo from the
1123 : : input pseudo, the new pseudo will have no conflict with the
1124 : : input pseudo which is wrong when the input pseudo lives after
1125 : : the insn and as the new pseudo value is changed by the insn
1126 : : output. Therefore we create the new pseudo from the output
1127 : : except the case when we have single matched dying input
1128 : : pseudo.
1129 : :
1130 : : We cannot reuse the current output register because we might
1131 : : have a situation like "a <- a op b", where the constraints
1132 : : force the second input operand ("b") to match the output
1133 : : operand ("a"). "b" must then be copied into a new register
1134 : : so that it doesn't clobber the current value of "a".
1135 : :
1136 : : We cannot use the same value if the output pseudo is
1137 : : early clobbered or the input pseudo is mentioned in the
1138 : : output, e.g. as an address part in memory, because
1139 : : output reload will actually extend the pseudo liveness.
1140 : : We don't care about eliminable hard regs here as we are
1141 : : interesting only in pseudos. */
1142 : :
1143 : : /* Matching input's register value is the same as one of the other
1144 : : output operand. Output operands in a parallel insn must be in
1145 : : different registers. */
1146 : 1430748 : out_conflict = false;
1147 : 1430748 : if (REG_P (in_rtx))
1148 : : {
1149 : 2566856 : for (i = 0; outs[i] >= 0; i++)
1150 : : {
1151 : 1356308 : rtx other_out_rtx = *curr_id->operand_loc[outs[i]];
1152 : 145535 : if (outs[i] != out && REG_P (other_out_rtx)
1153 : 1501681 : && (regno_val_use_in (REGNO (in_rtx), other_out_rtx)
1154 : : != NULL_RTX))
1155 : : {
1156 : : out_conflict = true;
1157 : : break;
1158 : : }
1159 : : }
1160 : : }
1161 : :
1162 : 1430748 : new_in_reg = new_out_reg
1163 : 1399658 : = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx)
1164 : 1180904 : && (int) REGNO (in_rtx) < lra_new_regno_start
1165 : 1180637 : && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))
1166 : : && (! early_clobber_p
1167 : : || check_conflict_input_operands (REGNO (in_rtx), ins))
1168 : 374475 : && (out < 0
1169 : 374475 : || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX)
1170 : 374474 : && !out_conflict
1171 : 1805197 : ? lra_create_new_reg (inmode, in_rtx, goal_class,
1172 : : exclude_start_hard_regs, "")
1173 : 1056299 : : lra_create_new_reg_with_unique_value (outmode, out_rtx, goal_class,
1174 : : exclude_start_hard_regs,
1175 : : ""));
1176 : : }
1177 : : /* In operand can be got from transformations before processing insn
1178 : : constraints. One example of such transformations is subreg
1179 : : reloading (see function simplify_operand_subreg). The new
1180 : : pseudos created by the transformations might have inaccurate
1181 : : class (ALL_REGS) and we should make their classes more
1182 : : accurate. */
1183 : 1566657 : narrow_reload_pseudo_class (in_rtx, goal_class);
1184 : 1566657 : lra_emit_move (copy_rtx (new_in_reg), in_rtx);
1185 : 1566657 : *before = get_insns ();
1186 : 1566657 : end_sequence ();
1187 : : /* Add the new pseudo to consider values of subsequent input reload
1188 : : pseudos. */
1189 : 1566657 : lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS);
1190 : 1566657 : curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx;
1191 : 1566657 : curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true;
1192 : 1566657 : curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg;
1193 : 3133315 : for (i = 0; (in = ins[i]) >= 0; i++)
1194 : 1566658 : if (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode
1195 : 1546992 : || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in]))
1196 : 1566657 : *curr_id->operand_loc[in] = new_in_reg;
1197 : : else
1198 : : {
1199 : 1 : lra_assert
1200 : : (GET_MODE (new_out_reg) == GET_MODE (*curr_id->operand_loc[in]));
1201 : 1 : *curr_id->operand_loc[in] = new_out_reg;
1202 : : }
1203 : 1566657 : lra_update_dups (curr_id, ins);
1204 : 1566657 : if (out < 0)
1205 : : return;
1206 : : /* See a comment for the input operand above. */
1207 : 1566657 : narrow_reload_pseudo_class (out_rtx, goal_class);
1208 : 1566657 : if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX)
1209 : : {
1210 : 1463171 : reg = SUBREG_P (out_rtx) ? SUBREG_REG (out_rtx) : out_rtx;
1211 : 1463171 : start_sequence ();
1212 : : /* If we had strict_low_part, use it also in reload to keep other
1213 : : parts unchanged but do it only for regs as strict_low_part
1214 : : has no sense for memory and probably there is no insn pattern
1215 : : to match the reload insn in memory case. */
1216 : 1463171 : if (out >= 0 && curr_static_id->operand[out].strict_low && REG_P (reg))
1217 : 1 : out_rtx = gen_rtx_STRICT_LOW_PART (VOIDmode, out_rtx);
1218 : 1463171 : lra_emit_move (out_rtx, copy_rtx (new_out_reg));
1219 : 1463171 : emit_insn (*after);
1220 : 1463171 : *after = get_insns ();
1221 : 1463171 : end_sequence ();
1222 : : }
1223 : 1566657 : *curr_id->operand_loc[out] = new_out_reg;
1224 : 1566657 : lra_update_dup (curr_id, out);
1225 : : }
1226 : :
1227 : : /* Return register class which is union of all reg classes in insn
1228 : : constraint alternative string starting with P. */
1229 : : static enum reg_class
1230 : 0 : reg_class_from_constraints (const char *p)
1231 : : {
1232 : 0 : int c, len;
1233 : 0 : enum reg_class op_class = NO_REGS;
1234 : :
1235 : 0 : do
1236 : 0 : switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
1237 : : {
1238 : : case '#':
1239 : : case ',':
1240 : : return op_class;
1241 : :
1242 : 0 : case 'g':
1243 : 0 : op_class = reg_class_subunion[op_class][GENERAL_REGS];
1244 : 0 : break;
1245 : :
1246 : 0 : default:
1247 : 0 : enum constraint_num cn = lookup_constraint (p);
1248 : 0 : enum reg_class cl = reg_class_for_constraint (cn);
1249 : 0 : if (cl == NO_REGS)
1250 : : {
1251 : 0 : if (insn_extra_address_constraint (cn))
1252 : 0 : op_class
1253 : 0 : = (reg_class_subunion
1254 : 0 : [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1255 : 0 : ADDRESS, SCRATCH)]);
1256 : : break;
1257 : : }
1258 : :
1259 : 0 : op_class = reg_class_subunion[op_class][cl];
1260 : 0 : break;
1261 : : }
1262 : 0 : while ((p += len), c);
1263 : : return op_class;
1264 : : }
1265 : :
1266 : : /* If OP is a register, return the class of the register as per
1267 : : get_reg_class, otherwise return NO_REGS. */
1268 : : static inline enum reg_class
1269 : 151235359 : get_op_class (rtx op)
1270 : : {
1271 : 126177002 : return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS;
1272 : : }
1273 : :
1274 : : /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1275 : : otherwise. If modes of MEM_PSEUDO and VAL are different, use
1276 : : SUBREG for VAL to make them equal. */
1277 : : static rtx_insn *
1278 : 664401 : emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
1279 : : {
1280 : 664401 : if (GET_MODE (mem_pseudo) != GET_MODE (val))
1281 : : {
1282 : : /* Usually size of mem_pseudo is greater than val size but in
1283 : : rare cases it can be less as it can be defined by target
1284 : : dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
1285 : 952 : if (! MEM_P (val))
1286 : : {
1287 : 952 : val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
1288 : : GET_CODE (val) == SUBREG
1289 : : ? SUBREG_REG (val) : val);
1290 : 952 : LRA_SUBREG_P (val) = 1;
1291 : : }
1292 : : else
1293 : : {
1294 : 0 : mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo);
1295 : 0 : LRA_SUBREG_P (mem_pseudo) = 1;
1296 : : }
1297 : : }
1298 : 664401 : return to_p ? gen_move_insn (mem_pseudo, val)
1299 : 338548 : : gen_move_insn (val, mem_pseudo);
1300 : : }
1301 : :
1302 : : /* Process a special case insn (register move), return true if we
1303 : : don't need to process it anymore. INSN should be a single set
1304 : : insn. Set up that RTL was changed through CHANGE_P and that hook
1305 : : TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through
1306 : : SEC_MEM_P. */
1307 : : static bool
1308 : 68059302 : check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
1309 : : {
1310 : 68059302 : int sregno, dregno;
1311 : 68059302 : rtx dest, src, dreg, sreg, new_reg, scratch_reg;
1312 : 68059302 : rtx_insn *before;
1313 : 68059302 : enum reg_class dclass, sclass, secondary_class;
1314 : 68059302 : secondary_reload_info sri;
1315 : :
1316 : 68059302 : lra_assert (curr_insn_set != NULL_RTX);
1317 : 68059302 : dreg = dest = SET_DEST (curr_insn_set);
1318 : 68059302 : sreg = src = SET_SRC (curr_insn_set);
1319 : 68059302 : if (GET_CODE (dest) == SUBREG)
1320 : 1208043 : dreg = SUBREG_REG (dest);
1321 : 68059302 : if (GET_CODE (src) == SUBREG)
1322 : 1252931 : sreg = SUBREG_REG (src);
1323 : 68059302 : if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
1324 : : return false;
1325 : 31924152 : sclass = dclass = NO_REGS;
1326 : 31924152 : if (REG_P (dreg))
1327 : 20526286 : dclass = get_reg_class (REGNO (dreg));
1328 : 20526286 : gcc_assert (dclass < LIM_REG_CLASSES && dclass >= NO_REGS);
1329 : 31924152 : if (dclass == ALL_REGS)
1330 : : /* ALL_REGS is used for new pseudos created by transformations
1331 : : like reload of SUBREG_REG (see function
1332 : : simplify_operand_subreg). We don't know their class yet. We
1333 : : should figure out the class from processing the insn
1334 : : constraints not in this fast path function. Even if ALL_REGS
1335 : : were a right class for the pseudo, secondary_... hooks usually
1336 : : are not define for ALL_REGS. */
1337 : : return false;
1338 : 31922047 : if (REG_P (sreg))
1339 : 17346052 : sclass = get_reg_class (REGNO (sreg));
1340 : 17346052 : gcc_assert (sclass < LIM_REG_CLASSES && sclass >= NO_REGS);
1341 : 31922047 : if (sclass == ALL_REGS)
1342 : : /* See comments above. */
1343 : : return false;
1344 : 31922047 : if (sclass == NO_REGS && dclass == NO_REGS)
1345 : : return false;
1346 : 30545442 : if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass)
1347 : 30545442 : && ((sclass != NO_REGS && dclass != NO_REGS)
1348 : 0 : || (GET_MODE (src)
1349 : 0 : != targetm.secondary_memory_needed_mode (GET_MODE (src)))))
1350 : : {
1351 : 13021 : *sec_mem_p = true;
1352 : 13021 : return false;
1353 : : }
1354 : 30532421 : if (! REG_P (dreg) || ! REG_P (sreg))
1355 : : return false;
1356 : 6461426 : sri.prev_sri = NULL;
1357 : 6461426 : sri.icode = CODE_FOR_nothing;
1358 : 6461426 : sri.extra_cost = 0;
1359 : 6461426 : secondary_class = NO_REGS;
1360 : : /* Set up hard register for a reload pseudo for hook
1361 : : secondary_reload because some targets just ignore unassigned
1362 : : pseudos in the hook. */
1363 : 6461426 : if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0)
1364 : : {
1365 : 2522586 : dregno = REGNO (dreg);
1366 : 2522586 : reg_renumber[dregno] = ira_class_hard_regs[dclass][0];
1367 : : }
1368 : : else
1369 : : dregno = -1;
1370 : 6461426 : if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0)
1371 : : {
1372 : 1006607 : sregno = REGNO (sreg);
1373 : 1006607 : reg_renumber[sregno] = ira_class_hard_regs[sclass][0];
1374 : : }
1375 : : else
1376 : : sregno = -1;
1377 : 6461426 : if (sclass != NO_REGS)
1378 : 3314432 : secondary_class
1379 : 6628864 : = (enum reg_class) targetm.secondary_reload (false, dest,
1380 : : (reg_class_t) sclass,
1381 : 3314432 : GET_MODE (src), &sri);
1382 : 3314432 : if (sclass == NO_REGS
1383 : 3314432 : || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing)
1384 : 1095 : && dclass != NO_REGS))
1385 : : {
1386 : 3146994 : enum reg_class old_sclass = secondary_class;
1387 : 3146994 : secondary_reload_info old_sri = sri;
1388 : :
1389 : 3146994 : sri.prev_sri = NULL;
1390 : 3146994 : sri.icode = CODE_FOR_nothing;
1391 : 3146994 : sri.extra_cost = 0;
1392 : 3146994 : secondary_class
1393 : 6293988 : = (enum reg_class) targetm.secondary_reload (true, src,
1394 : : (reg_class_t) dclass,
1395 : 3146994 : GET_MODE (src), &sri);
1396 : : /* Check the target hook consistency. */
1397 : 3146994 : lra_assert
1398 : : ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1399 : : || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing)
1400 : : || (secondary_class == old_sclass && sri.icode == old_sri.icode));
1401 : : }
1402 : 6461426 : if (sregno >= 0)
1403 : 1006607 : reg_renumber [sregno] = -1;
1404 : 6461426 : if (dregno >= 0)
1405 : 2522586 : reg_renumber [dregno] = -1;
1406 : 6461426 : if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing)
1407 : : return false;
1408 : 1097 : *change_p = true;
1409 : 1097 : new_reg = NULL_RTX;
1410 : 0 : if (secondary_class != NO_REGS)
1411 : 1097 : new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX,
1412 : : secondary_class, NULL,
1413 : : "secondary");
1414 : 1097 : start_sequence ();
1415 : 1097 : if (sri.icode == CODE_FOR_nothing)
1416 : 1097 : lra_emit_move (new_reg, src);
1417 : : else
1418 : : {
1419 : 0 : enum reg_class scratch_class;
1420 : :
1421 : 0 : scratch_class = (reg_class_from_constraints
1422 : 0 : (insn_data[sri.icode].operand[2].constraint));
1423 : 0 : scratch_reg = (lra_create_new_reg_with_unique_value
1424 : 0 : (insn_data[sri.icode].operand[2].mode, NULL_RTX,
1425 : : scratch_class, NULL, "scratch"));
1426 : 0 : emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest,
1427 : : src, scratch_reg));
1428 : : }
1429 : 1097 : before = get_insns ();
1430 : 1097 : end_sequence ();
1431 : 1097 : lra_process_new_insns (curr_insn, before, NULL, "Inserting the move");
1432 : 1097 : if (new_reg != NULL_RTX)
1433 : 1097 : SET_SRC (curr_insn_set) = new_reg;
1434 : : else
1435 : : {
1436 : 0 : if (lra_dump_file != NULL)
1437 : : {
1438 : 0 : fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn));
1439 : 0 : dump_insn_slim (lra_dump_file, curr_insn);
1440 : : }
1441 : 0 : lra_set_insn_deleted (curr_insn);
1442 : 0 : return true;
1443 : : }
1444 : 1097 : return false;
1445 : : }
1446 : :
1447 : : /* The following data describe the result of process_alt_operands.
1448 : : The data are used in curr_insn_transform to generate reloads. */
1449 : :
1450 : : /* The chosen reg classes which should be used for the corresponding
1451 : : operands. */
1452 : : static enum reg_class goal_alt[MAX_RECOG_OPERANDS];
1453 : : /* Hard registers which cannot be a start hard register for the corresponding
1454 : : operands. */
1455 : : static HARD_REG_SET goal_alt_exclude_start_hard_regs[MAX_RECOG_OPERANDS];
1456 : : /* True if the operand should be the same as another operand and that
1457 : : other operand does not need a reload. */
1458 : : static bool goal_alt_match_win[MAX_RECOG_OPERANDS];
1459 : : /* True if the operand does not need a reload. */
1460 : : static bool goal_alt_win[MAX_RECOG_OPERANDS];
1461 : : /* True if the operand can be offsetable memory. */
1462 : : static bool goal_alt_offmemok[MAX_RECOG_OPERANDS];
1463 : : /* The number of an operand to which given operand can be matched to. */
1464 : : static int goal_alt_matches[MAX_RECOG_OPERANDS];
1465 : : /* The number of elements in the following array. */
1466 : : static int goal_alt_dont_inherit_ops_num;
1467 : : /* Numbers of operands whose reload pseudos should not be inherited. */
1468 : : static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
1469 : : /* True if we should try only this alternative for the next constraint sub-pass
1470 : : to speed up the sub-pass. */
1471 : : static bool goal_reuse_alt_p;
1472 : : /* True if the insn commutative operands should be swapped. */
1473 : : static bool goal_alt_swapped;
1474 : : /* The chosen insn alternative. */
1475 : : static int goal_alt_number;
1476 : : /* True if output reload of the stack pointer should be generated. */
1477 : : static bool goal_alt_out_sp_reload_p;
1478 : :
1479 : : /* True if the corresponding operand is the result of an equivalence
1480 : : substitution. */
1481 : : static bool equiv_substition_p[MAX_RECOG_OPERANDS];
1482 : :
1483 : : /* The following five variables are used to choose the best insn
1484 : : alternative. They reflect final characteristics of the best
1485 : : alternative. */
1486 : :
1487 : : /* Number of necessary reloads and overall cost reflecting the
1488 : : previous value and other unpleasantness of the best alternative. */
1489 : : static int best_losers, best_overall;
1490 : : /* Overall number hard registers used for reloads. For example, on
1491 : : some targets we need 2 general registers to reload DFmode and only
1492 : : one floating point register. */
1493 : : static int best_reload_nregs;
1494 : : /* Overall number reflecting distances of previous reloading the same
1495 : : value. The distances are counted from the current BB start. It is
1496 : : used to improve inheritance chances. */
1497 : : static int best_reload_sum;
1498 : :
1499 : : /* True if the current insn should have no correspondingly input or
1500 : : output reloads. */
1501 : : static bool no_input_reloads_p, no_output_reloads_p;
1502 : :
1503 : : /* True if we swapped the commutative operands in the current
1504 : : insn. */
1505 : : static int curr_swapped;
1506 : :
1507 : : /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a
1508 : : register of class CL. Add any input reloads to list BEFORE. AFTER
1509 : : is nonnull if *LOC is an automodified value; handle that case by
1510 : : adding the required output reloads to list AFTER. Return true if
1511 : : the RTL was changed.
1512 : :
1513 : : if CHECK_ONLY_P is true, check that the *LOC is a correct address
1514 : : register. Return false if the address register is correct. */
1515 : : static bool
1516 : 30952786 : process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after,
1517 : : enum reg_class cl)
1518 : : {
1519 : 30952786 : int regno;
1520 : 30952786 : enum reg_class rclass, new_class;
1521 : 30952786 : rtx reg;
1522 : 30952786 : rtx new_reg;
1523 : 30952786 : machine_mode mode;
1524 : 30952786 : bool subreg_p, before_p = false;
1525 : :
1526 : 30952786 : subreg_p = GET_CODE (*loc) == SUBREG;
1527 : 30952786 : if (subreg_p)
1528 : : {
1529 : 13285 : reg = SUBREG_REG (*loc);
1530 : 13285 : mode = GET_MODE (reg);
1531 : :
1532 : : /* For mode with size bigger than ptr_mode, there unlikely to be "mov"
1533 : : between two registers with different classes, but there normally will
1534 : : be "mov" which transfers element of vector register into the general
1535 : : register, and this normally will be a subreg which should be reloaded
1536 : : as a whole. This is particularly likely to be triggered when
1537 : : -fno-split-wide-types specified. */
1538 : 13285 : if (!REG_P (reg)
1539 : 13285 : || in_class_p (reg, cl, &new_class)
1540 : 15109 : || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode)))
1541 : 13285 : loc = &SUBREG_REG (*loc);
1542 : : }
1543 : :
1544 : 30952786 : reg = *loc;
1545 : 30952786 : mode = GET_MODE (reg);
1546 : 30952786 : if (! REG_P (reg))
1547 : : {
1548 : 0 : if (check_only_p)
1549 : : return true;
1550 : : /* Always reload memory in an address even if the target supports
1551 : : such addresses. */
1552 : 0 : new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, NULL,
1553 : : "address");
1554 : 0 : before_p = true;
1555 : : }
1556 : : else
1557 : : {
1558 : 30952786 : regno = REGNO (reg);
1559 : 30952786 : rclass = get_reg_class (regno);
1560 : 30952786 : if (! check_only_p
1561 : 30952786 : && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg)
1562 : : {
1563 : 90325 : if (lra_dump_file != NULL)
1564 : : {
1565 : 0 : fprintf (lra_dump_file,
1566 : : "Changing pseudo %d in address of insn %u on equiv ",
1567 : 0 : REGNO (reg), INSN_UID (curr_insn));
1568 : 0 : dump_value_slim (lra_dump_file, *loc, 1);
1569 : 0 : fprintf (lra_dump_file, "\n");
1570 : : }
1571 : 90325 : *loc = copy_rtx (*loc);
1572 : : }
1573 : 30952786 : if (*loc != reg || ! in_class_p (reg, cl, &new_class))
1574 : : {
1575 : 401814 : if (check_only_p)
1576 : : return true;
1577 : 401814 : reg = *loc;
1578 : 401814 : if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT,
1579 : : mode, reg, cl, NULL,
1580 : : subreg_p, "address", &new_reg))
1581 : : before_p = true;
1582 : : }
1583 : 30550972 : else if (new_class != NO_REGS && rclass != new_class)
1584 : : {
1585 : 392486 : if (check_only_p)
1586 : : return true;
1587 : 392486 : lra_change_class (regno, new_class, " Change to", true);
1588 : 392486 : return false;
1589 : : }
1590 : : else
1591 : : return false;
1592 : : }
1593 : 0 : if (before_p)
1594 : : {
1595 : 395474 : push_to_sequence (*before);
1596 : 395474 : lra_emit_move (new_reg, reg);
1597 : 395474 : *before = get_insns ();
1598 : 395474 : end_sequence ();
1599 : : }
1600 : 401814 : *loc = new_reg;
1601 : 401814 : if (after != NULL)
1602 : : {
1603 : 0 : start_sequence ();
1604 : 0 : lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg);
1605 : 0 : emit_insn (*after);
1606 : 0 : *after = get_insns ();
1607 : 0 : end_sequence ();
1608 : : }
1609 : : return true;
1610 : : }
1611 : :
1612 : : /* Insert move insn in simplify_operand_subreg. BEFORE returns
1613 : : the insn to be inserted before curr insn. AFTER returns the
1614 : : the insn to be inserted after curr insn. ORIGREG and NEWREG
1615 : : are the original reg and new reg for reload. */
1616 : : static void
1617 : 467 : insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg,
1618 : : rtx newreg)
1619 : : {
1620 : 467 : if (before)
1621 : : {
1622 : 467 : push_to_sequence (*before);
1623 : 467 : lra_emit_move (newreg, origreg);
1624 : 467 : *before = get_insns ();
1625 : 467 : end_sequence ();
1626 : : }
1627 : 467 : if (after)
1628 : : {
1629 : 0 : start_sequence ();
1630 : 0 : lra_emit_move (origreg, newreg);
1631 : 0 : emit_insn (*after);
1632 : 0 : *after = get_insns ();
1633 : 0 : end_sequence ();
1634 : : }
1635 : 467 : }
1636 : :
1637 : : static bool valid_address_p (machine_mode mode, rtx addr, addr_space_t as);
1638 : : static bool process_address (int, bool, rtx_insn **, rtx_insn **);
1639 : :
1640 : : /* Make reloads for subreg in operand NOP with internal subreg mode
1641 : : REG_MODE, add new reloads for further processing. Return true if
1642 : : any change was done. */
1643 : : static bool
1644 : 159244509 : simplify_operand_subreg (int nop, machine_mode reg_mode)
1645 : : {
1646 : 159244509 : int hard_regno, inner_hard_regno;
1647 : 159244509 : rtx_insn *before, *after;
1648 : 159244509 : machine_mode mode, innermode;
1649 : 159244509 : rtx reg, new_reg;
1650 : 159244509 : rtx operand = *curr_id->operand_loc[nop];
1651 : 159244509 : enum reg_class regclass;
1652 : 159244509 : enum op_type type;
1653 : :
1654 : 159244509 : before = after = NULL;
1655 : :
1656 : 159244509 : if (GET_CODE (operand) != SUBREG)
1657 : : return false;
1658 : :
1659 : 3587142 : mode = GET_MODE (operand);
1660 : 3587142 : reg = SUBREG_REG (operand);
1661 : 3587142 : innermode = GET_MODE (reg);
1662 : 3587142 : type = curr_static_id->operand[nop].type;
1663 : 3587142 : if (MEM_P (reg))
1664 : : {
1665 : 13439 : const bool addr_was_valid
1666 : 13439 : = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg));
1667 : 13439 : alter_subreg (curr_id->operand_loc[nop], false);
1668 : 13439 : rtx subst = *curr_id->operand_loc[nop];
1669 : 13439 : lra_assert (MEM_P (subst));
1670 : 26878 : const bool addr_is_valid = valid_address_p (GET_MODE (subst),
1671 : : XEXP (subst, 0),
1672 : 13439 : MEM_ADDR_SPACE (subst));
1673 : 13439 : if (!addr_was_valid
1674 : 13439 : || addr_is_valid
1675 : 13439 : || ((get_constraint_type (lookup_constraint
1676 : 0 : (curr_static_id->operand[nop].constraint))
1677 : : != CT_SPECIAL_MEMORY)
1678 : : /* We still can reload address and if the address is
1679 : : valid, we can remove subreg without reloading its
1680 : : inner memory. */
1681 : 0 : && valid_address_p (GET_MODE (subst),
1682 : 0 : regno_reg_rtx
1683 : : [ira_class_hard_regs
1684 : 0 : [base_reg_class (GET_MODE (subst),
1685 : : MEM_ADDR_SPACE (subst),
1686 : 0 : ADDRESS, SCRATCH)][0]],
1687 : 0 : MEM_ADDR_SPACE (subst))))
1688 : : {
1689 : : /* If we change the address for a paradoxical subreg of memory, the
1690 : : new address might violate the necessary alignment or the access
1691 : : might be slow; take this into consideration. We need not worry
1692 : : about accesses beyond allocated memory for paradoxical memory
1693 : : subregs as we don't substitute such equiv memory (see processing
1694 : : equivalences in function lra_constraints) and because for spilled
1695 : : pseudos we allocate stack memory enough for the biggest
1696 : : corresponding paradoxical subreg.
1697 : :
1698 : : However, do not blindly simplify a (subreg (mem ...)) for
1699 : : WORD_REGISTER_OPERATIONS targets as this may lead to loading junk
1700 : : data into a register when the inner is narrower than outer or
1701 : : missing important data from memory when the inner is wider than
1702 : : outer. This rule only applies to modes that are no wider than
1703 : : a word.
1704 : :
1705 : : If valid memory becomes invalid after subreg elimination
1706 : : and address might be different we still have to reload
1707 : : memory.
1708 : : */
1709 : 13439 : if ((! addr_was_valid
1710 : : || addr_is_valid
1711 : 0 : || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode)))
1712 : 26878 : && !(maybe_ne (GET_MODE_PRECISION (mode),
1713 : 26878 : GET_MODE_PRECISION (innermode))
1714 : 12990 : && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD)
1715 : 21908 : && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD)
1716 : : && WORD_REGISTER_OPERATIONS)
1717 : 31295 : && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode)
1718 : 4417 : && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst)))
1719 : 0 : || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode)
1720 : 0 : && targetm.slow_unaligned_access (innermode,
1721 : 0 : MEM_ALIGN (reg)))))
1722 : 13439 : return true;
1723 : :
1724 : 0 : *curr_id->operand_loc[nop] = operand;
1725 : :
1726 : : /* But if the address was not valid, we cannot reload the MEM without
1727 : : reloading the address first. */
1728 : 0 : if (!addr_was_valid)
1729 : 0 : process_address (nop, false, &before, &after);
1730 : :
1731 : : /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */
1732 : 0 : enum reg_class rclass
1733 : 0 : = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1734 : 0 : if (get_reload_reg (curr_static_id->operand[nop].type, innermode,
1735 : : reg, rclass, NULL,
1736 : : true, "slow/invalid mem", &new_reg))
1737 : : {
1738 : 0 : bool insert_before, insert_after;
1739 : 0 : bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1740 : :
1741 : 0 : insert_before = (type != OP_OUT
1742 : 0 : || partial_subreg_p (mode, innermode));
1743 : 0 : insert_after = type != OP_IN;
1744 : 0 : insert_move_for_subreg (insert_before ? &before : NULL,
1745 : : insert_after ? &after : NULL,
1746 : : reg, new_reg);
1747 : : }
1748 : 0 : SUBREG_REG (operand) = new_reg;
1749 : :
1750 : : /* Convert to MODE. */
1751 : 0 : reg = operand;
1752 : 0 : rclass
1753 : 0 : = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1754 : 0 : if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1755 : : rclass, NULL,
1756 : : true, "slow/invalid mem", &new_reg))
1757 : : {
1758 : 0 : bool insert_before, insert_after;
1759 : 0 : bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1760 : :
1761 : 0 : insert_before = type != OP_OUT;
1762 : 0 : insert_after = type != OP_IN;
1763 : 0 : insert_move_for_subreg (insert_before ? &before : NULL,
1764 : : insert_after ? &after : NULL,
1765 : : reg, new_reg);
1766 : : }
1767 : 0 : *curr_id->operand_loc[nop] = new_reg;
1768 : 0 : lra_process_new_insns (curr_insn, before, after,
1769 : : "Inserting slow/invalid mem reload");
1770 : 0 : return true;
1771 : : }
1772 : :
1773 : : /* If the address was valid and became invalid, prefer to reload
1774 : : the memory. Typical case is when the index scale should
1775 : : correspond the memory. */
1776 : 0 : *curr_id->operand_loc[nop] = operand;
1777 : : /* Do not return false here as the MEM_P (reg) will be processed
1778 : : later in this function. */
1779 : : }
1780 : 3573703 : else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)
1781 : : {
1782 : 69 : alter_subreg (curr_id->operand_loc[nop], false);
1783 : 69 : return true;
1784 : : }
1785 : 3573634 : else if (CONSTANT_P (reg))
1786 : : {
1787 : : /* Try to simplify subreg of constant. It is usually result of
1788 : : equivalence substitution. */
1789 : 751 : if (innermode == VOIDmode
1790 : 751 : && (innermode = original_subreg_reg_mode[nop]) == VOIDmode)
1791 : 0 : innermode = curr_static_id->operand[nop].mode;
1792 : 751 : if ((new_reg = simplify_subreg (mode, reg, innermode,
1793 : 751 : SUBREG_BYTE (operand))) != NULL_RTX)
1794 : : {
1795 : 335 : *curr_id->operand_loc[nop] = new_reg;
1796 : 335 : return true;
1797 : : }
1798 : : }
1799 : : /* Put constant into memory when we have mixed modes. It generates
1800 : : a better code in most cases as it does not need a secondary
1801 : : reload memory. It also prevents LRA looping when LRA is using
1802 : : secondary reload memory again and again. */
1803 : 832 : if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg)
1804 : 3573715 : && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode))
1805 : : {
1806 : 9 : SUBREG_REG (operand) = force_const_mem (reg_mode, reg);
1807 : 9 : alter_subreg (curr_id->operand_loc[nop], false);
1808 : 9 : return true;
1809 : : }
1810 : 3573290 : auto fp_subreg_can_be_simplified_after_reload_p = [] (machine_mode innermode,
1811 : : poly_uint64 offset,
1812 : : machine_mode mode) {
1813 : 0 : reload_completed = 1;
1814 : 0 : bool res = simplify_subreg_regno (FRAME_POINTER_REGNUM,
1815 : : innermode,
1816 : 0 : offset, mode) >= 0;
1817 : 0 : reload_completed = 0;
1818 : 0 : return res;
1819 : : };
1820 : : /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1821 : : if there may be a problem accessing OPERAND in the outer
1822 : : mode. */
1823 : 3573290 : if ((REG_P (reg)
1824 : 3572833 : && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1825 : 3572833 : && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1826 : : /* Don't reload paradoxical subregs because we could be looping
1827 : : having repeatedly final regno out of hard regs range. */
1828 : 3007944 : && (hard_regno_nregs (hard_regno, innermode)
1829 : 3007944 : >= hard_regno_nregs (hard_regno, mode))
1830 : 3002601 : && simplify_subreg_regno (hard_regno, innermode,
1831 : 3002601 : SUBREG_BYTE (operand), mode) < 0
1832 : : /* Exclude reloading of frame pointer in subreg if frame pointer can not
1833 : : be simplified here only because the reload is not finished yet. */
1834 : 703 : && (hard_regno != FRAME_POINTER_REGNUM
1835 : 0 : || !fp_subreg_can_be_simplified_after_reload_p (innermode,
1836 : : SUBREG_BYTE (operand),
1837 : : mode))
1838 : : /* Don't reload subreg for matching reload. It is actually
1839 : : valid subreg in LRA. */
1840 : 703 : && ! LRA_SUBREG_P (operand))
1841 : 7146113 : || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg))
1842 : : {
1843 : 467 : enum reg_class rclass;
1844 : :
1845 : 467 : if (REG_P (reg))
1846 : : /* There is a big probability that we will get the same class
1847 : : for the new pseudo and we will get the same insn which
1848 : : means infinite looping. So spill the new pseudo. */
1849 : : rclass = NO_REGS;
1850 : : else
1851 : : /* The class will be defined later in curr_insn_transform. */
1852 : 457 : rclass
1853 : 457 : = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1854 : :
1855 : 467 : if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg,
1856 : : rclass, NULL,
1857 : : true, "subreg reg", &new_reg))
1858 : : {
1859 : 467 : bool insert_before, insert_after;
1860 : 467 : bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1861 : :
1862 : 934 : insert_before = (type != OP_OUT
1863 : 467 : || read_modify_subreg_p (operand));
1864 : 467 : insert_after = (type != OP_IN);
1865 : 934 : insert_move_for_subreg (insert_before ? &before : NULL,
1866 : : insert_after ? &after : NULL,
1867 : : reg, new_reg);
1868 : : }
1869 : 467 : SUBREG_REG (operand) = new_reg;
1870 : 467 : lra_process_new_insns (curr_insn, before, after,
1871 : : "Inserting subreg reload");
1872 : 467 : return true;
1873 : : }
1874 : : /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1875 : : IRA allocates hardreg to the inner pseudo reg according to its mode
1876 : : instead of the outermode, so the size of the hardreg may not be enough
1877 : : to contain the outermode operand, in that case we may need to insert
1878 : : reload for the reg. For the following two types of paradoxical subreg,
1879 : : we need to insert reload:
1880 : : 1. If the op_type is OP_IN, and the hardreg could not be paired with
1881 : : other hardreg to contain the outermode operand
1882 : : (checked by in_hard_reg_set_p), we need to insert the reload.
1883 : : 2. If the op_type is OP_OUT or OP_INOUT.
1884 : :
1885 : : Here is a paradoxical subreg example showing how the reload is generated:
1886 : :
1887 : : (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1888 : : (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1889 : :
1890 : : In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1891 : : here, if reg107 is assigned to hardreg R15, because R15 is the last
1892 : : hardreg, compiler cannot find another hardreg to pair with R15 to
1893 : : contain TImode data. So we insert a TImode reload reg180 for it.
1894 : : After reload is inserted:
1895 : :
1896 : : (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1897 : : (reg:DI 107 [ __comp ])) -1
1898 : : (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1899 : : (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1900 : :
1901 : : Two reload hard registers will be allocated to reg180 to save TImode data
1902 : : in LRA_assign.
1903 : :
1904 : : For LRA pseudos this should normally be handled by the biggest_mode
1905 : : mechanism. However, it's possible for new uses of an LRA pseudo
1906 : : to be introduced after we've allocated it, such as when undoing
1907 : : inheritance, and the allocated register might not then be appropriate
1908 : : for the new uses. */
1909 : 3572823 : else if (REG_P (reg)
1910 : 3572823 : && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1911 : 3572823 : && paradoxical_subreg_p (operand)
1912 : 1098131 : && (inner_hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
1913 : 3572823 : && ((hard_regno
1914 : 4580876 : = simplify_subreg_regno (inner_hard_regno, innermode,
1915 : 1008053 : SUBREG_BYTE (operand), mode)) < 0
1916 : 1008053 : || ((hard_regno_nregs (inner_hard_regno, innermode)
1917 : 1008053 : < hard_regno_nregs (hard_regno, mode))
1918 : 5343 : && (regclass = lra_get_allocno_class (REGNO (reg)))
1919 : 5343 : && (type != OP_IN
1920 : 5343 : || !in_hard_reg_set_p (reg_class_contents[regclass],
1921 : : mode, hard_regno)
1922 : 5343 : || overlaps_hard_reg_set_p (lra_no_alloc_regs,
1923 : : mode, hard_regno)))))
1924 : : {
1925 : : /* The class will be defined later in curr_insn_transform. */
1926 : 0 : enum reg_class rclass
1927 : 0 : = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS);
1928 : :
1929 : 0 : if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg,
1930 : : rclass, NULL,
1931 : : true, "paradoxical subreg", &new_reg))
1932 : : {
1933 : 0 : rtx subreg;
1934 : 0 : bool insert_before, insert_after;
1935 : :
1936 : 0 : PUT_MODE (new_reg, mode);
1937 : 0 : subreg = gen_lowpart_SUBREG (innermode, new_reg);
1938 : 0 : bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg));
1939 : :
1940 : 0 : insert_before = (type != OP_OUT);
1941 : 0 : insert_after = (type != OP_IN);
1942 : 0 : insert_move_for_subreg (insert_before ? &before : NULL,
1943 : : insert_after ? &after : NULL,
1944 : : reg, subreg);
1945 : : }
1946 : 0 : SUBREG_REG (operand) = new_reg;
1947 : 0 : lra_process_new_insns (curr_insn, before, after,
1948 : : "Inserting paradoxical subreg reload");
1949 : 0 : return true;
1950 : : }
1951 : : return false;
1952 : : }
1953 : :
1954 : : /* Return TRUE if X refers for a hard register from SET. */
1955 : : static bool
1956 : 409492 : uses_hard_regs_p (rtx x, HARD_REG_SET set)
1957 : : {
1958 : 409492 : int i, j, x_hard_regno;
1959 : 409492 : machine_mode mode;
1960 : 409492 : const char *fmt;
1961 : 409492 : enum rtx_code code;
1962 : :
1963 : 409492 : if (x == NULL_RTX)
1964 : : return false;
1965 : 409492 : code = GET_CODE (x);
1966 : 409492 : mode = GET_MODE (x);
1967 : :
1968 : 409492 : if (code == SUBREG)
1969 : : {
1970 : : /* For all SUBREGs we want to check whether the full multi-register
1971 : : overlaps the set. For normal SUBREGs this means 'get_hard_regno' of
1972 : : the inner register, for paradoxical SUBREGs this means the
1973 : : 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is
1974 : : fine. Use the wider mode for all cases. */
1975 : 3068 : rtx subreg = SUBREG_REG (x);
1976 : 3068 : mode = wider_subreg_mode (x);
1977 : 3068 : if (mode == GET_MODE (subreg))
1978 : : {
1979 : 2071 : x = subreg;
1980 : 2071 : code = GET_CODE (x);
1981 : : }
1982 : : }
1983 : :
1984 : 409492 : if (REG_P (x) || SUBREG_P (x))
1985 : : {
1986 : 256066 : x_hard_regno = get_hard_regno (x);
1987 : 256066 : return (x_hard_regno >= 0
1988 : 256066 : && overlaps_hard_reg_set_p (set, mode, x_hard_regno));
1989 : : }
1990 : 153426 : fmt = GET_RTX_FORMAT (code);
1991 : 398896 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1992 : : {
1993 : 246735 : if (fmt[i] == 'e')
1994 : : {
1995 : 122416 : if (uses_hard_regs_p (XEXP (x, i), set))
1996 : : return true;
1997 : : }
1998 : 124319 : else if (fmt[i] == 'E')
1999 : : {
2000 : 4274 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2001 : 3918 : if (uses_hard_regs_p (XVECEXP (x, i, j), set))
2002 : : return true;
2003 : : }
2004 : : }
2005 : : return false;
2006 : : }
2007 : :
2008 : : /* Return true if OP is a spilled pseudo. */
2009 : : static inline bool
2010 : 59094955 : spilled_pseudo_p (rtx op)
2011 : : {
2012 : 59094955 : return (REG_P (op)
2013 : 59094955 : && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op)));
2014 : : }
2015 : :
2016 : : /* Return true if X is a general constant. */
2017 : : static inline bool
2018 : 7215320 : general_constant_p (rtx x)
2019 : : {
2020 : 7215320 : return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x));
2021 : : }
2022 : :
2023 : : static bool
2024 : 22321455 : reg_in_class_p (rtx reg, enum reg_class cl)
2025 : : {
2026 : 22321455 : if (cl == NO_REGS)
2027 : 1125724 : return get_reg_class (REGNO (reg)) == NO_REGS;
2028 : 21195731 : return in_class_p (reg, cl, NULL);
2029 : : }
2030 : :
2031 : : /* Return true if SET of RCLASS contains no hard regs which can be
2032 : : used in MODE. */
2033 : : static bool
2034 : 3185764 : prohibited_class_reg_set_mode_p (enum reg_class rclass,
2035 : : HARD_REG_SET &set,
2036 : : machine_mode mode)
2037 : : {
2038 : 3185764 : HARD_REG_SET temp;
2039 : :
2040 : 6371528 : lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
2041 : 3185764 : temp = set & ~lra_no_alloc_regs;
2042 : 3185764 : return (hard_reg_set_subset_p
2043 : 3185764 : (temp, ira_prohibited_class_mode_regs[rclass][mode]));
2044 : : }
2045 : :
2046 : :
2047 : : /* Used to check validity info about small class input operands. It
2048 : : should be incremented at start of processing an insn
2049 : : alternative. */
2050 : : static unsigned int curr_small_class_check = 0;
2051 : :
2052 : : /* Update number of used inputs of class OP_CLASS for operand NOP
2053 : : of alternative NALT. Return true if we have more such class operands
2054 : : than the number of available regs. */
2055 : : static bool
2056 : 329943323 : update_and_check_small_class_inputs (int nop, int nalt,
2057 : : enum reg_class op_class)
2058 : : {
2059 : 329943323 : static unsigned int small_class_check[LIM_REG_CLASSES];
2060 : 329943323 : static int small_class_input_nums[LIM_REG_CLASSES];
2061 : :
2062 : 326975445 : if (SMALL_REGISTER_CLASS_P (op_class)
2063 : : /* We are interesting in classes became small because of fixing
2064 : : some hard regs, e.g. by an user through GCC options. */
2065 : 3063997 : && hard_reg_set_intersect_p (reg_class_contents[op_class],
2066 : 3063997 : ira_no_alloc_regs)
2067 : 329943363 : && (curr_static_id->operand[nop].type != OP_OUT
2068 : 34 : || TEST_BIT (curr_static_id->operand[nop].early_clobber_alts, nalt)))
2069 : : {
2070 : 6 : if (small_class_check[op_class] == curr_small_class_check)
2071 : 0 : small_class_input_nums[op_class]++;
2072 : : else
2073 : : {
2074 : 6 : small_class_check[op_class] = curr_small_class_check;
2075 : 6 : small_class_input_nums[op_class] = 1;
2076 : : }
2077 : 6 : if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class])
2078 : : return true;
2079 : : }
2080 : : return false;
2081 : : }
2082 : :
2083 : : /* Print operand constraints for alternative ALT_NUMBER of the current
2084 : : insn. */
2085 : : static void
2086 : 4441 : print_curr_insn_alt (int alt_number)
2087 : : {
2088 : 15209 : for (int i = 0; i < curr_static_id->n_operands; i++)
2089 : : {
2090 : 10768 : const char *p = (curr_static_id->operand_alternative
2091 : 10768 : [alt_number * curr_static_id->n_operands + i].constraint);
2092 : 10768 : if (*p == '\0')
2093 : 248 : continue;
2094 : 10520 : fprintf (lra_dump_file, " (%d) ", i);
2095 : 38274 : for (; *p != '\0' && *p != ',' && *p != '#'; p++)
2096 : 17234 : fputc (*p, lra_dump_file);
2097 : : }
2098 : 4441 : }
2099 : :
2100 : : /* Major function to choose the current insn alternative and what
2101 : : operands should be reloaded and how. If ONLY_ALTERNATIVE is not
2102 : : negative we should consider only this alternative. Return false if
2103 : : we cannot choose the alternative or find how to reload the
2104 : : operands. */
2105 : : static bool
2106 : 81540493 : process_alt_operands (int only_alternative)
2107 : : {
2108 : 81540493 : bool ok_p = false;
2109 : 81540493 : int nop, overall, nalt;
2110 : 81540493 : int n_alternatives = curr_static_id->n_alternatives;
2111 : 81540493 : int n_operands = curr_static_id->n_operands;
2112 : : /* LOSERS counts the operands that don't fit this alternative and
2113 : : would require loading. */
2114 : 81540493 : int losers;
2115 : 81540493 : int addr_losers;
2116 : : /* REJECT is a count of how undesirable this alternative says it is
2117 : : if any reloading is required. If the alternative matches exactly
2118 : : then REJECT is ignored, but otherwise it gets this much counted
2119 : : against it in addition to the reloading needed. */
2120 : 81540493 : int reject;
2121 : : /* This is defined by '!' or '?' alternative constraint and added to
2122 : : reject. But in some cases it can be ignored. */
2123 : 81540493 : int static_reject;
2124 : 81540493 : int op_reject;
2125 : : /* The number of elements in the following array. */
2126 : 81540493 : int early_clobbered_regs_num;
2127 : : /* Numbers of operands which are early clobber registers. */
2128 : 81540493 : int early_clobbered_nops[MAX_RECOG_OPERANDS];
2129 : 81540493 : enum reg_class curr_alt[MAX_RECOG_OPERANDS];
2130 : 81540493 : HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
2131 : 81540493 : HARD_REG_SET curr_alt_exclude_start_hard_regs[MAX_RECOG_OPERANDS];
2132 : 81540493 : bool curr_alt_match_win[MAX_RECOG_OPERANDS];
2133 : 81540493 : bool curr_alt_win[MAX_RECOG_OPERANDS];
2134 : 81540493 : bool curr_alt_offmemok[MAX_RECOG_OPERANDS];
2135 : 81540493 : int curr_alt_matches[MAX_RECOG_OPERANDS];
2136 : : /* The number of elements in the following array. */
2137 : 81540493 : int curr_alt_dont_inherit_ops_num;
2138 : : /* Numbers of operands whose reload pseudos should not be inherited. */
2139 : 81540493 : int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS];
2140 : 81540493 : bool curr_reuse_alt_p;
2141 : : /* True if output stack pointer reload should be generated for the current
2142 : : alternative. */
2143 : 81540493 : bool curr_alt_out_sp_reload_p;
2144 : 81540493 : bool curr_alt_class_change_p;
2145 : 81540493 : rtx op;
2146 : : /* The register when the operand is a subreg of register, otherwise the
2147 : : operand itself. */
2148 : 81540493 : rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS];
2149 : : /* The register if the operand is a register or subreg of register,
2150 : : otherwise NULL. */
2151 : 81540493 : rtx operand_reg[MAX_RECOG_OPERANDS];
2152 : 81540493 : int hard_regno[MAX_RECOG_OPERANDS];
2153 : 81540493 : machine_mode biggest_mode[MAX_RECOG_OPERANDS];
2154 : 81540493 : int reload_nregs, reload_sum;
2155 : 81540493 : bool costly_p;
2156 : 81540493 : enum reg_class cl;
2157 : 81540493 : const HARD_REG_SET *cl_filter;
2158 : :
2159 : : /* Calculate some data common for all alternatives to speed up the
2160 : : function. */
2161 : 271949661 : for (nop = 0; nop < n_operands; nop++)
2162 : : {
2163 : 190409168 : rtx reg;
2164 : :
2165 : 190409168 : op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop];
2166 : : /* The real hard regno of the operand after the allocation. */
2167 : 190409168 : hard_regno[nop] = get_hard_regno (op);
2168 : :
2169 : 190409168 : operand_reg[nop] = reg = op;
2170 : 190409168 : biggest_mode[nop] = GET_MODE (op);
2171 : 190409168 : if (GET_CODE (op) == SUBREG)
2172 : : {
2173 : 4047517 : biggest_mode[nop] = wider_subreg_mode (op);
2174 : 4047517 : operand_reg[nop] = reg = SUBREG_REG (op);
2175 : : }
2176 : 190409168 : if (! REG_P (reg))
2177 : 80974778 : operand_reg[nop] = NULL_RTX;
2178 : 109434390 : else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
2179 : 129031092 : || ((int) REGNO (reg)
2180 : 19596702 : == lra_get_elimination_hard_regno (REGNO (reg))))
2181 : 106612490 : no_subreg_reg_operand[nop] = reg;
2182 : : else
2183 : 2821900 : operand_reg[nop] = no_subreg_reg_operand[nop]
2184 : : /* Just use natural mode for elimination result. It should
2185 : : be enough for extra constraints hooks. */
2186 : 2821900 : = regno_reg_rtx[hard_regno[nop]];
2187 : : }
2188 : :
2189 : : /* The constraints are made of several alternatives. Each operand's
2190 : : constraint looks like foo,bar,... with commas separating the
2191 : : alternatives. The first alternatives for all operands go
2192 : : together, the second alternatives go together, etc.
2193 : :
2194 : : First loop over alternatives. */
2195 : 81540493 : alternative_mask preferred = curr_id->preferred_alternatives;
2196 : 81540493 : if (only_alternative >= 0)
2197 : 906184 : preferred &= ALTERNATIVE_BIT (only_alternative);
2198 : :
2199 : 315144386 : for (nalt = 0; nalt < n_alternatives; nalt++)
2200 : : {
2201 : : /* Loop over operands for one constraint alternative. */
2202 : 302714729 : if (!TEST_BIT (preferred, nalt))
2203 : 83951544 : continue;
2204 : :
2205 : 218763185 : if (lra_dump_file != NULL)
2206 : : {
2207 : 3209 : fprintf (lra_dump_file, " Considering alt=%d of insn %d: ",
2208 : 3209 : nalt, INSN_UID (curr_insn));
2209 : 3209 : print_curr_insn_alt (nalt);
2210 : 3209 : fprintf (lra_dump_file, "\n");
2211 : : }
2212 : :
2213 : 218763185 : bool matching_early_clobber[MAX_RECOG_OPERANDS];
2214 : 218763185 : curr_small_class_check++;
2215 : 218763185 : overall = losers = addr_losers = 0;
2216 : 218763185 : static_reject = reject = reload_nregs = reload_sum = 0;
2217 : 717942263 : for (nop = 0; nop < n_operands; nop++)
2218 : : {
2219 : 499179078 : int inc = (curr_static_id
2220 : 499179078 : ->operand_alternative[nalt * n_operands + nop].reject);
2221 : 499179078 : if (lra_dump_file != NULL && inc != 0)
2222 : 54 : fprintf (lra_dump_file,
2223 : : " Staticly defined alt reject+=%d\n", inc);
2224 : 499179078 : static_reject += inc;
2225 : 499179078 : matching_early_clobber[nop] = 0;
2226 : : }
2227 : : reject += static_reject;
2228 : : early_clobbered_regs_num = 0;
2229 : : curr_alt_out_sp_reload_p = false;
2230 : : curr_reuse_alt_p = true;
2231 : : curr_alt_class_change_p = false;
2232 : :
2233 : 562542060 : for (nop = 0; nop < n_operands; nop++)
2234 : : {
2235 : 446204656 : const char *p;
2236 : 446204656 : char *end;
2237 : 446204656 : int len, c, m, i, opalt_num, this_alternative_matches;
2238 : 446204656 : bool win, did_match, offmemok, early_clobber_p;
2239 : : /* false => this operand can be reloaded somehow for this
2240 : : alternative. */
2241 : 446204656 : bool badop;
2242 : : /* true => this operand can be reloaded if the alternative
2243 : : allows regs. */
2244 : 446204656 : bool winreg;
2245 : : /* True if a constant forced into memory would be OK for
2246 : : this operand. */
2247 : 446204656 : bool constmemok;
2248 : 446204656 : enum reg_class this_alternative, this_costly_alternative;
2249 : 446204656 : HARD_REG_SET this_alternative_set, this_costly_alternative_set;
2250 : 446204656 : HARD_REG_SET this_alternative_exclude_start_hard_regs;
2251 : 446204656 : bool this_alternative_match_win, this_alternative_win;
2252 : 446204656 : bool this_alternative_offmemok;
2253 : 446204656 : bool scratch_p;
2254 : 446204656 : machine_mode mode;
2255 : 446204656 : enum constraint_num cn;
2256 : 446204656 : bool class_change_p = false;
2257 : :
2258 : 446204656 : opalt_num = nalt * n_operands + nop;
2259 : 446204656 : if (curr_static_id->operand_alternative[opalt_num].anything_ok)
2260 : : {
2261 : : /* Fast track for no constraints at all. */
2262 : 13835552 : curr_alt[nop] = NO_REGS;
2263 : 13835552 : CLEAR_HARD_REG_SET (curr_alt_set[nop]);
2264 : 13835552 : curr_alt_win[nop] = true;
2265 : 13835552 : curr_alt_match_win[nop] = false;
2266 : 13835552 : curr_alt_offmemok[nop] = false;
2267 : 13835552 : curr_alt_matches[nop] = -1;
2268 : 13835552 : continue;
2269 : : }
2270 : :
2271 : 432369104 : op = no_subreg_reg_operand[nop];
2272 : 432369104 : mode = curr_operand_mode[nop];
2273 : :
2274 : 432369104 : win = did_match = winreg = offmemok = constmemok = false;
2275 : 432369104 : badop = true;
2276 : :
2277 : 432369104 : early_clobber_p = false;
2278 : 432369104 : p = curr_static_id->operand_alternative[opalt_num].constraint;
2279 : :
2280 : 432369104 : this_costly_alternative = this_alternative = NO_REGS;
2281 : : /* We update set of possible hard regs besides its class
2282 : : because reg class might be inaccurate. For example,
2283 : : union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
2284 : : is translated in HI_REGS because classes are merged by
2285 : : pairs and there is no accurate intermediate class. */
2286 : 432369104 : CLEAR_HARD_REG_SET (this_alternative_set);
2287 : 432369104 : CLEAR_HARD_REG_SET (this_costly_alternative_set);
2288 : 432369104 : CLEAR_HARD_REG_SET (this_alternative_exclude_start_hard_regs);
2289 : 432369104 : this_alternative_win = false;
2290 : 432369104 : this_alternative_match_win = false;
2291 : 432369104 : this_alternative_offmemok = false;
2292 : 432369104 : this_alternative_matches = -1;
2293 : :
2294 : : /* An empty constraint should be excluded by the fast
2295 : : track. */
2296 : 432369104 : lra_assert (*p != 0 && *p != ',');
2297 : :
2298 : : op_reject = 0;
2299 : : /* Scan this alternative's specs for this operand; set WIN
2300 : : if the operand fits any letter in this alternative.
2301 : : Otherwise, clear BADOP if this operand could fit some
2302 : : letter after reloads, or set WINREG if this operand could
2303 : : fit after reloads provided the constraint allows some
2304 : : registers. */
2305 : : costly_p = false;
2306 : 1115603541 : do
2307 : : {
2308 : 1115603541 : switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c)
2309 : : {
2310 : : case '\0':
2311 : : len = 0;
2312 : : break;
2313 : 410745863 : case ',':
2314 : 410745863 : c = '\0';
2315 : 410745863 : break;
2316 : :
2317 : 164338 : case '&':
2318 : 164338 : early_clobber_p = true;
2319 : 164338 : break;
2320 : :
2321 : 13283 : case '$':
2322 : 13283 : op_reject += LRA_MAX_REJECT;
2323 : 13283 : break;
2324 : 0 : case '^':
2325 : 0 : op_reject += LRA_LOSER_COST_FACTOR;
2326 : 0 : break;
2327 : :
2328 : 0 : case '#':
2329 : : /* Ignore rest of this alternative. */
2330 : 0 : c = '\0';
2331 : 0 : break;
2332 : :
2333 : 38087756 : case '0': case '1': case '2': case '3': case '4':
2334 : 38087756 : case '5': case '6': case '7': case '8': case '9':
2335 : 38087756 : {
2336 : 38087756 : int m_hregno;
2337 : 38087756 : bool match_p;
2338 : :
2339 : 38087756 : m = strtoul (p, &end, 10);
2340 : 38087756 : p = end;
2341 : 38087756 : len = 0;
2342 : 38087756 : lra_assert (nop > m);
2343 : :
2344 : : /* Reject matches if we don't know which operand is
2345 : : bigger. This situation would arguably be a bug in
2346 : : an .md pattern, but could also occur in a user asm. */
2347 : 114263268 : if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]),
2348 : 114263268 : GET_MODE_SIZE (biggest_mode[nop])))
2349 : : break;
2350 : :
2351 : : /* Don't match wrong asm insn operands for proper
2352 : : diagnostic later. */
2353 : 38087756 : if (INSN_CODE (curr_insn) < 0
2354 : 36777 : && (curr_operand_mode[m] == BLKmode
2355 : 36776 : || curr_operand_mode[nop] == BLKmode)
2356 : 1 : && curr_operand_mode[m] != curr_operand_mode[nop])
2357 : : break;
2358 : :
2359 : 38087755 : m_hregno = get_hard_regno (*curr_id->operand_loc[m]);
2360 : : /* We are supposed to match a previous operand.
2361 : : If we do, we win if that one did. If we do
2362 : : not, count both of the operands as losers.
2363 : : (This is too conservative, since most of the
2364 : : time only a single reload insn will be needed
2365 : : to make the two operands win. As a result,
2366 : : this alternative may be rejected when it is
2367 : : actually desirable.) */
2368 : 38087755 : match_p = false;
2369 : 38087755 : if (operands_match_p (*curr_id->operand_loc[nop],
2370 : 38087755 : *curr_id->operand_loc[m], m_hregno))
2371 : : {
2372 : : /* We should reject matching of an early
2373 : : clobber operand if the matching operand is
2374 : : not dying in the insn. */
2375 : 9634226 : if (!TEST_BIT (curr_static_id->operand[m]
2376 : : .early_clobber_alts, nalt)
2377 : 19004 : || operand_reg[nop] == NULL_RTX
2378 : 9653230 : || (find_regno_note (curr_insn, REG_DEAD,
2379 : : REGNO (op))
2380 : 4482 : || REGNO (op) == REGNO (operand_reg[m])))
2381 : 9634226 : match_p = true;
2382 : : }
2383 : 9634226 : if (match_p)
2384 : : {
2385 : : /* If we are matching a non-offsettable
2386 : : address where an offsettable address was
2387 : : expected, then we must reject this
2388 : : combination, because we can't reload
2389 : : it. */
2390 : 9634226 : if (curr_alt_offmemok[m]
2391 : 1138 : && MEM_P (*curr_id->operand_loc[m])
2392 : 0 : && curr_alt[m] == NO_REGS && ! curr_alt_win[m])
2393 : 0 : continue;
2394 : : }
2395 : : else
2396 : : {
2397 : : /* If the operands do not match and one
2398 : : operand is INOUT, we can not match them.
2399 : : Try other possibilities, e.g. other
2400 : : alternatives or commutative operand
2401 : : exchange. */
2402 : 28453529 : if (curr_static_id->operand[nop].type == OP_INOUT
2403 : 28453529 : || curr_static_id->operand[m].type == OP_INOUT)
2404 : : break;
2405 : : /* Operands don't match. If the operands are
2406 : : different user defined explicit hard
2407 : : registers, then we cannot make them match
2408 : : when one is early clobber operand. */
2409 : 28453164 : if ((REG_P (*curr_id->operand_loc[nop])
2410 : 17863969 : || SUBREG_P (*curr_id->operand_loc[nop]))
2411 : 11031056 : && (REG_P (*curr_id->operand_loc[m])
2412 : 150813 : || SUBREG_P (*curr_id->operand_loc[m])))
2413 : : {
2414 : 10978968 : rtx nop_reg = *curr_id->operand_loc[nop];
2415 : 10978968 : if (SUBREG_P (nop_reg))
2416 : 437336 : nop_reg = SUBREG_REG (nop_reg);
2417 : 10978968 : rtx m_reg = *curr_id->operand_loc[m];
2418 : 10978968 : if (SUBREG_P (m_reg))
2419 : 98725 : m_reg = SUBREG_REG (m_reg);
2420 : :
2421 : 10978968 : if (REG_P (nop_reg)
2422 : 10978968 : && HARD_REGISTER_P (nop_reg)
2423 : 2847628 : && REG_USERVAR_P (nop_reg)
2424 : 9 : && REG_P (m_reg)
2425 : 9 : && HARD_REGISTER_P (m_reg)
2426 : 10978968 : && REG_USERVAR_P (m_reg))
2427 : : {
2428 : : int i;
2429 : :
2430 : 0 : for (i = 0; i < early_clobbered_regs_num; i++)
2431 : 0 : if (m == early_clobbered_nops[i])
2432 : : break;
2433 : 0 : if (i < early_clobbered_regs_num
2434 : 0 : || early_clobber_p)
2435 : : break;
2436 : : }
2437 : : }
2438 : : /* Both operands must allow a reload register,
2439 : : otherwise we cannot make them match. */
2440 : 28453164 : if (curr_alt[m] == NO_REGS)
2441 : : break;
2442 : : /* Retroactively mark the operand we had to
2443 : : match as a loser, if it wasn't already and
2444 : : it wasn't matched to a register constraint
2445 : : (e.g it might be matched by memory). */
2446 : 28435907 : if (curr_alt_win[m]
2447 : 27626769 : && (operand_reg[m] == NULL_RTX
2448 : 27382099 : || hard_regno[m] < 0))
2449 : : {
2450 : 627055 : losers++;
2451 : 627055 : reload_nregs
2452 : 627055 : += (ira_reg_class_max_nregs[curr_alt[m]]
2453 : 627055 : [GET_MODE (*curr_id->operand_loc[m])]);
2454 : : }
2455 : :
2456 : : /* Prefer matching earlyclobber alternative as
2457 : : it results in less hard regs required for
2458 : : the insn than a non-matching earlyclobber
2459 : : alternative. */
2460 : 28435907 : if (TEST_BIT (curr_static_id->operand[m]
2461 : : .early_clobber_alts, nalt))
2462 : : {
2463 : 17788 : if (lra_dump_file != NULL)
2464 : 0 : fprintf
2465 : 0 : (lra_dump_file,
2466 : : " %d Matching earlyclobber alt:"
2467 : : " reject--\n",
2468 : : nop);
2469 : 17788 : if (!matching_early_clobber[m])
2470 : : {
2471 : 17788 : reject--;
2472 : 17788 : matching_early_clobber[m] = 1;
2473 : : }
2474 : : }
2475 : : /* Otherwise we prefer no matching
2476 : : alternatives because it gives more freedom
2477 : : in RA. */
2478 : 28418119 : else if (operand_reg[nop] == NULL_RTX
2479 : 28418119 : || (find_regno_note (curr_insn, REG_DEAD,
2480 : : REGNO (operand_reg[nop]))
2481 : : == NULL_RTX))
2482 : : {
2483 : 24904320 : if (lra_dump_file != NULL)
2484 : 715 : fprintf
2485 : 715 : (lra_dump_file,
2486 : : " %d Matching alt: reject+=2\n",
2487 : : nop);
2488 : 24904320 : reject += 2;
2489 : : }
2490 : : }
2491 : : /* If we have to reload this operand and some
2492 : : previous operand also had to match the same
2493 : : thing as this operand, we don't know how to do
2494 : : that. */
2495 : 38070133 : if (!match_p || !curr_alt_win[m])
2496 : : {
2497 : 60828795 : for (i = 0; i < nop; i++)
2498 : 32263655 : if (curr_alt_matches[i] == m)
2499 : : break;
2500 : 28565141 : if (i < nop)
2501 : : break;
2502 : : }
2503 : : else
2504 : : did_match = true;
2505 : :
2506 : 38070132 : this_alternative_matches = m;
2507 : : /* This can be fixed with reloads if the operand
2508 : : we are supposed to match can be fixed with
2509 : : reloads. */
2510 : 38070132 : badop = false;
2511 : 38070132 : this_alternative = curr_alt[m];
2512 : 38070132 : this_alternative_set = curr_alt_set[m];
2513 : 38070132 : this_alternative_exclude_start_hard_regs
2514 : 38070132 : = curr_alt_exclude_start_hard_regs[m];
2515 : 38070132 : winreg = this_alternative != NO_REGS;
2516 : 38070132 : break;
2517 : : }
2518 : :
2519 : 10966932 : case 'g':
2520 : 10966932 : if (MEM_P (op)
2521 : 7215320 : || general_constant_p (op)
2522 : 15238217 : || spilled_pseudo_p (op))
2523 : : win = true;
2524 : 10966932 : cl = GENERAL_REGS;
2525 : 10966932 : cl_filter = nullptr;
2526 : 10966932 : goto reg;
2527 : :
2528 : 634002128 : default:
2529 : 634002128 : cn = lookup_constraint (p);
2530 : 634002128 : switch (get_constraint_type (cn))
2531 : : {
2532 : 426771043 : case CT_REGISTER:
2533 : 426771043 : cl = reg_class_for_constraint (cn);
2534 : 426771043 : if (cl != NO_REGS)
2535 : : {
2536 : 295777390 : cl_filter = get_register_filter (cn);
2537 : 295777390 : goto reg;
2538 : : }
2539 : : break;
2540 : :
2541 : 1853420 : case CT_CONST_INT:
2542 : 1853420 : if (CONST_INT_P (op)
2543 : 1853420 : && insn_const_int_ok_for_constraint (INTVAL (op), cn))
2544 : : win = true;
2545 : : break;
2546 : :
2547 : 86668476 : case CT_MEMORY:
2548 : 86668476 : case CT_RELAXED_MEMORY:
2549 : 86668476 : if (MEM_P (op)
2550 : 86668476 : && satisfies_memory_constraint_p (op, cn))
2551 : : win = true;
2552 : 54232961 : else if (spilled_pseudo_p (op))
2553 : 40500181 : win = true;
2554 : :
2555 : : /* If we didn't already win, we can reload constants
2556 : : via force_const_mem or put the pseudo value into
2557 : : memory, or make other memory by reloading the
2558 : : address like for 'o'. */
2559 : 91385700 : if (CONST_POOL_OK_P (mode, op)
2560 : 81996660 : || MEM_P (op) || REG_P (op)
2561 : : /* We can restore the equiv insn by a
2562 : : reload. */
2563 : 86872901 : || equiv_substition_p[nop])
2564 : 86622921 : badop = false;
2565 : : constmemok = true;
2566 : : offmemok = true;
2567 : : break;
2568 : :
2569 : 935059 : case CT_ADDRESS:
2570 : : /* An asm operand with an address constraint
2571 : : that doesn't satisfy address_operand has
2572 : : is_address cleared, so that we don't try to
2573 : : make a non-address fit. */
2574 : 935059 : if (!curr_static_id->operand[nop].is_address)
2575 : : break;
2576 : : /* If we didn't already win, we can reload the address
2577 : : into a base register. */
2578 : 935040 : if (satisfies_address_constraint_p (op, cn))
2579 : 935040 : win = true;
2580 : 935040 : cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
2581 : : ADDRESS, SCRATCH);
2582 : 935040 : cl_filter = nullptr;
2583 : 935040 : badop = false;
2584 : 935040 : goto reg;
2585 : :
2586 : 117138213 : case CT_FIXED_FORM:
2587 : 117138213 : if (constraint_satisfied_p (op, cn))
2588 : 1115603541 : win = true;
2589 : : break;
2590 : :
2591 : 635917 : case CT_SPECIAL_MEMORY:
2592 : 635917 : if (satisfies_memory_constraint_p (op, cn))
2593 : : win = true;
2594 : 590709 : else if (spilled_pseudo_p (op))
2595 : : {
2596 : 1115603541 : curr_reuse_alt_p = false;
2597 : 1115603541 : win = true;
2598 : : }
2599 : : break;
2600 : : }
2601 : : break;
2602 : :
2603 : 307679362 : reg:
2604 : 307679362 : if (mode == BLKmode)
2605 : : break;
2606 : 307679340 : this_alternative = reg_class_subunion[this_alternative][cl];
2607 : 307679340 : if (hard_reg_set_subset_p (this_alternative_set,
2608 : 307679340 : reg_class_contents[cl]))
2609 : 307679297 : this_alternative_exclude_start_hard_regs
2610 : 307679297 : = ira_exclude_class_mode_regs[cl][mode];
2611 : 43 : else if (!hard_reg_set_subset_p (reg_class_contents[cl],
2612 : : this_alternative_set))
2613 : 42 : this_alternative_exclude_start_hard_regs
2614 : 42 : |= ira_exclude_class_mode_regs[cl][mode];
2615 : 307679340 : this_alternative_set |= reg_class_contents[cl];
2616 : 307679340 : if (cl_filter)
2617 : 0 : this_alternative_exclude_start_hard_regs |= ~*cl_filter;
2618 : 307679340 : if (costly_p)
2619 : : {
2620 : 19361856 : this_costly_alternative
2621 : 19361856 : = reg_class_subunion[this_costly_alternative][cl];
2622 : 19361856 : this_costly_alternative_set |= reg_class_contents[cl];
2623 : : }
2624 : 307679340 : winreg = true;
2625 : 307679340 : if (REG_P (op))
2626 : : {
2627 : 191229231 : tree decl;
2628 : 191229231 : if (hard_regno[nop] >= 0
2629 : 159961402 : && in_hard_reg_set_p (this_alternative_set,
2630 : : mode, hard_regno[nop])
2631 : 144540920 : && (!cl_filter
2632 : 0 : || TEST_HARD_REG_BIT (*cl_filter,
2633 : : hard_regno[nop]))
2634 : 335770151 : && ((REG_ATTRS (op) && (decl = REG_EXPR (op)) != NULL
2635 : 80009784 : && VAR_P (decl) && DECL_HARD_REGISTER (decl))
2636 : 144537787 : || !(TEST_HARD_REG_BIT
2637 : 144537787 : (this_alternative_exclude_start_hard_regs,
2638 : : hard_regno[nop]))))
2639 : : win = true;
2640 : 46688312 : else if (hard_regno[nop] < 0)
2641 : : {
2642 : 31267829 : if (in_class_p (op, this_alternative, NULL))
2643 : : win = true;
2644 : 23642164 : else if (in_class_p (op, this_alternative, NULL, true))
2645 : : {
2646 : 1115603541 : class_change_p = true;
2647 : 1115603541 : win = true;
2648 : : }
2649 : : }
2650 : : }
2651 : : break;
2652 : : }
2653 : 1115603541 : if (c != ' ' && c != '\t')
2654 : 1115603541 : costly_p = c == '*';
2655 : : }
2656 : 1115603541 : while ((p += len), c);
2657 : :
2658 : 864738208 : scratch_p = (operand_reg[nop] != NULL_RTX
2659 : 432369104 : && ira_former_scratch_p (REGNO (operand_reg[nop])));
2660 : : /* Record which operands fit this alternative. */
2661 : 432369104 : if (win)
2662 : : {
2663 : 238509710 : this_alternative_win = true;
2664 : 238509710 : if (class_change_p)
2665 : : {
2666 : 185791 : curr_alt_class_change_p = true;
2667 : 185791 : if (lra_dump_file != NULL)
2668 : 8 : fprintf (lra_dump_file,
2669 : : " %d Narrowing class: reject+=3\n",
2670 : : nop);
2671 : 185791 : reject += 3;
2672 : : }
2673 : 238509710 : if (operand_reg[nop] != NULL_RTX)
2674 : : {
2675 : 161645660 : if (hard_regno[nop] >= 0)
2676 : : {
2677 : 144485601 : if (in_hard_reg_set_p (this_costly_alternative_set,
2678 : : mode, hard_regno[nop]))
2679 : : {
2680 : 902230 : if (lra_dump_file != NULL)
2681 : 15 : fprintf (lra_dump_file,
2682 : : " %d Costly set: reject++\n",
2683 : : nop);
2684 : 902230 : reject++;
2685 : : }
2686 : : }
2687 : : else
2688 : : {
2689 : : /* Prefer won reg to spilled pseudo under other
2690 : : equal conditions for possibe inheritance. */
2691 : 17160059 : if (! scratch_p)
2692 : : {
2693 : 17157704 : if (lra_dump_file != NULL)
2694 : 53 : fprintf
2695 : 53 : (lra_dump_file,
2696 : : " %d Non pseudo reload: reject++\n",
2697 : : nop);
2698 : 17157704 : reject++;
2699 : : }
2700 : 17160059 : if (in_class_p (operand_reg[nop],
2701 : : this_costly_alternative, NULL, true))
2702 : : {
2703 : 118016 : if (lra_dump_file != NULL)
2704 : 0 : fprintf
2705 : 0 : (lra_dump_file,
2706 : : " %d Non pseudo costly reload:"
2707 : : " reject++\n",
2708 : : nop);
2709 : 118016 : reject++;
2710 : : }
2711 : : }
2712 : : /* We simulate the behavior of old reload here.
2713 : : Although scratches need hard registers and it
2714 : : might result in spilling other pseudos, no reload
2715 : : insns are generated for the scratches. So it
2716 : : might cost something but probably less than old
2717 : : reload pass believes. */
2718 : 161645660 : if (scratch_p)
2719 : : {
2720 : 107594 : if (lra_dump_file != NULL)
2721 : 6 : fprintf (lra_dump_file,
2722 : : " %d Scratch win: reject+=2\n",
2723 : : nop);
2724 : 107594 : reject += 2;
2725 : : }
2726 : : }
2727 : : }
2728 : 193859394 : else if (did_match)
2729 : : this_alternative_match_win = true;
2730 : : else
2731 : : {
2732 : 184354402 : int const_to_mem = 0;
2733 : 184354402 : bool no_regs_p;
2734 : :
2735 : 184354402 : reject += op_reject;
2736 : : /* Mark output reload of the stack pointer. */
2737 : 184354402 : if (op == stack_pointer_rtx
2738 : 37590 : && curr_static_id->operand[nop].type != OP_IN)
2739 : 184354402 : curr_alt_out_sp_reload_p = true;
2740 : :
2741 : : /* If this alternative asks for a specific reg class, see if there
2742 : : is at least one allocatable register in that class. */
2743 : 184354402 : no_regs_p
2744 : 317310419 : = (this_alternative == NO_REGS
2745 : 184354402 : || (hard_reg_set_subset_p
2746 : 132956028 : (reg_class_contents[this_alternative],
2747 : : lra_no_alloc_regs)));
2748 : :
2749 : : /* For asms, verify that the class for this alternative is possible
2750 : : for the mode that is specified. */
2751 : 132956017 : if (!no_regs_p && INSN_CODE (curr_insn) < 0)
2752 : : {
2753 : : int i;
2754 : 42977 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2755 : 42975 : if (targetm.hard_regno_mode_ok (i, mode)
2756 : 42975 : && in_hard_reg_set_p (reg_class_contents[this_alternative],
2757 : : mode, i))
2758 : : break;
2759 : 11986 : if (i == FIRST_PSEUDO_REGISTER)
2760 : 184354402 : winreg = false;
2761 : : }
2762 : :
2763 : : /* If this operand accepts a register, and if the
2764 : : register class has at least one allocatable register,
2765 : : then this operand can be reloaded. */
2766 : 184354402 : if (winreg && !no_regs_p)
2767 : : badop = false;
2768 : :
2769 : 51398387 : if (badop)
2770 : : {
2771 : 42574328 : if (lra_dump_file != NULL)
2772 : 522 : fprintf (lra_dump_file,
2773 : : " Bad operand -- refuse\n");
2774 : 102425781 : goto fail;
2775 : : }
2776 : :
2777 : 141780074 : if (this_alternative != NO_REGS)
2778 : : {
2779 : 132956016 : HARD_REG_SET available_regs
2780 : 132956016 : = (reg_class_contents[this_alternative]
2781 : 132956016 : & ~((ira_prohibited_class_mode_regs
2782 : 132956016 : [this_alternative][mode])
2783 : 132956016 : | lra_no_alloc_regs));
2784 : 132956016 : if (hard_reg_set_empty_p (available_regs))
2785 : : {
2786 : : /* There are no hard regs holding a value of given
2787 : : mode. */
2788 : 13082 : if (offmemok)
2789 : : {
2790 : 288 : this_alternative = NO_REGS;
2791 : 288 : if (lra_dump_file != NULL)
2792 : 0 : fprintf (lra_dump_file,
2793 : : " %d Using memory because of"
2794 : : " a bad mode: reject+=2\n",
2795 : : nop);
2796 : 288 : reject += 2;
2797 : : }
2798 : : else
2799 : : {
2800 : 12794 : if (lra_dump_file != NULL)
2801 : 0 : fprintf (lra_dump_file,
2802 : : " Wrong mode -- refuse\n");
2803 : 12794 : goto fail;
2804 : : }
2805 : : }
2806 : : }
2807 : :
2808 : : /* If not assigned pseudo has a class which a subset of
2809 : : required reg class, it is a less costly alternative
2810 : : as the pseudo still can get a hard reg of necessary
2811 : : class. */
2812 : 132943222 : if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0
2813 : 19014039 : && (cl = get_reg_class (REGNO (op))) != NO_REGS
2814 : 145164504 : && ira_class_subset_p[this_alternative][cl])
2815 : : {
2816 : 1036 : if (lra_dump_file != NULL)
2817 : 0 : fprintf
2818 : 0 : (lra_dump_file,
2819 : : " %d Super set class reg: reject-=3\n", nop);
2820 : 1036 : reject -= 3;
2821 : : }
2822 : :
2823 : 141767280 : this_alternative_offmemok = offmemok;
2824 : 141767280 : if (this_costly_alternative != NO_REGS)
2825 : : {
2826 : 16860483 : if (lra_dump_file != NULL)
2827 : 44 : fprintf (lra_dump_file,
2828 : : " %d Costly loser: reject++\n", nop);
2829 : 16860483 : reject++;
2830 : : }
2831 : : /* If the operand is dying, has a matching constraint,
2832 : : and satisfies constraints of the matched operand
2833 : : which failed to satisfy the own constraints, most probably
2834 : : the reload for this operand will be gone. */
2835 : 141767280 : if (this_alternative_matches >= 0
2836 : 28550973 : && !curr_alt_win[this_alternative_matches]
2837 : 937968 : && REG_P (op)
2838 : 686163 : && find_regno_note (curr_insn, REG_DEAD, REGNO (op))
2839 : 142460122 : && (hard_regno[nop] >= 0
2840 : 360840 : ? in_hard_reg_set_p (this_alternative_set,
2841 : : mode, hard_regno[nop])
2842 : 28838 : : in_class_p (op, this_alternative, NULL)))
2843 : : {
2844 : 212546 : if (lra_dump_file != NULL)
2845 : 1 : fprintf
2846 : 1 : (lra_dump_file,
2847 : : " %d Dying matched operand reload: reject++\n",
2848 : : nop);
2849 : 212546 : reject++;
2850 : : }
2851 : : else
2852 : : {
2853 : : /* Strict_low_part requires to reload the register
2854 : : not the sub-register. In this case we should
2855 : : check that a final reload hard reg can hold the
2856 : : value mode. */
2857 : 141554734 : if (curr_static_id->operand[nop].strict_low
2858 : 174 : && REG_P (op)
2859 : 167 : && hard_regno[nop] < 0
2860 : 18 : && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
2861 : 18 : && ira_class_hard_regs_num[this_alternative] > 0
2862 : 141554752 : && (!targetm.hard_regno_mode_ok
2863 : 18 : (ira_class_hard_regs[this_alternative][0],
2864 : 18 : GET_MODE (*curr_id->operand_loc[nop]))))
2865 : : {
2866 : 0 : if (lra_dump_file != NULL)
2867 : 0 : fprintf
2868 : 0 : (lra_dump_file,
2869 : : " Strict low subreg reload -- refuse\n");
2870 : 0 : goto fail;
2871 : : }
2872 : 141554734 : losers++;
2873 : : }
2874 : 141767280 : if (operand_reg[nop] != NULL_RTX
2875 : : /* Output operands and matched input operands are
2876 : : not inherited. The following conditions do not
2877 : : exactly describe the previous statement but they
2878 : : are pretty close. */
2879 : 52771513 : && curr_static_id->operand[nop].type != OP_OUT
2880 : 22727227 : && (this_alternative_matches < 0
2881 : 11119867 : || curr_static_id->operand[nop].type != OP_IN))
2882 : : {
2883 : 11607360 : int last_reload = (lra_reg_info[ORIGINAL_REGNO
2884 : 11607360 : (operand_reg[nop])]
2885 : 11607360 : .last_reload);
2886 : :
2887 : : /* The value of reload_sum has sense only if we
2888 : : process insns in their order. It happens only on
2889 : : the first constraints sub-pass when we do most of
2890 : : reload work. */
2891 : 11607360 : if (lra_constraint_iter == 1 && last_reload > bb_reload_num)
2892 : 2637794 : reload_sum += last_reload - bb_reload_num;
2893 : : }
2894 : : /* If this is a constant that is reloaded into the
2895 : : desired class by copying it to memory first, count
2896 : : that as another reload. This is consistent with
2897 : : other code and is required to avoid choosing another
2898 : : alternative when the constant is moved into memory.
2899 : : Note that the test here is precisely the same as in
2900 : : the code below that calls force_const_mem. */
2901 : 211818800 : if (CONST_POOL_OK_P (mode, op)
2902 : 176793040 : && ((targetm.preferred_reload_class
2903 : 35025760 : (op, this_alternative) == NO_REGS)
2904 : 33544989 : || no_input_reloads_p))
2905 : : {
2906 : 1480771 : const_to_mem = 1;
2907 : 1480771 : if (! no_regs_p)
2908 : 720486 : losers++;
2909 : : }
2910 : :
2911 : : /* Alternative loses if it requires a type of reload not
2912 : : permitted for this insn. We can always reload
2913 : : objects with a REG_UNUSED note. */
2914 : 141767280 : if ((curr_static_id->operand[nop].type != OP_IN
2915 : 73867916 : && no_output_reloads_p
2916 : 0 : && ! find_reg_note (curr_insn, REG_UNUSED, op))
2917 : 141767280 : || (curr_static_id->operand[nop].type != OP_OUT
2918 : 67899738 : && no_input_reloads_p && ! const_to_mem)
2919 : 283534560 : || (this_alternative_matches >= 0
2920 : 28550973 : && (no_input_reloads_p
2921 : 28550973 : || (no_output_reloads_p
2922 : 0 : && (curr_static_id->operand
2923 : 0 : [this_alternative_matches].type != OP_IN)
2924 : 0 : && ! find_reg_note (curr_insn, REG_UNUSED,
2925 : : no_subreg_reg_operand
2926 : 0 : [this_alternative_matches])))))
2927 : : {
2928 : 0 : if (lra_dump_file != NULL)
2929 : 0 : fprintf
2930 : 0 : (lra_dump_file,
2931 : : " No input/output reload -- refuse\n");
2932 : 0 : goto fail;
2933 : : }
2934 : :
2935 : : /* Alternative loses if it required class pseudo cannot
2936 : : hold value of required mode. Such insns can be
2937 : : described by insn definitions with mode iterators. */
2938 : 141767280 : if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode
2939 : 108009951 : && ! hard_reg_set_empty_p (this_alternative_set)
2940 : : /* It is common practice for constraints to use a
2941 : : class which does not have actually enough regs to
2942 : : hold the value (e.g. x86 AREG for mode requiring
2943 : : more one general reg). Therefore we have 2
2944 : : conditions to check that the reload pseudo cannot
2945 : : hold the mode value. */
2946 : 99848874 : && (!targetm.hard_regno_mode_ok
2947 : 99848874 : (ira_class_hard_regs[this_alternative][0],
2948 : : GET_MODE (*curr_id->operand_loc[nop])))
2949 : : /* The above condition is not enough as the first
2950 : : reg in ira_class_hard_regs can be not aligned for
2951 : : multi-words mode values. */
2952 : 141767280 : && (prohibited_class_reg_set_mode_p
2953 : 0 : (this_alternative, this_alternative_set,
2954 : 0 : GET_MODE (*curr_id->operand_loc[nop]))))
2955 : : {
2956 : 0 : if (lra_dump_file != NULL)
2957 : 0 : fprintf (lra_dump_file,
2958 : : " reload pseudo for op %d "
2959 : : "cannot hold the mode value -- refuse\n",
2960 : : nop);
2961 : 0 : goto fail;
2962 : : }
2963 : :
2964 : : /* Check strong discouragement of reload of non-constant
2965 : : into class THIS_ALTERNATIVE. */
2966 : 106741520 : if (! CONSTANT_P (op) && ! no_regs_p
2967 : 240445027 : && (targetm.preferred_reload_class
2968 : 98677747 : (op, this_alternative) == NO_REGS
2969 : 91102417 : || (curr_static_id->operand[nop].type == OP_OUT
2970 : 63987147 : && (targetm.preferred_output_reload_class
2971 : 63987147 : (op, this_alternative) == NO_REGS))))
2972 : : {
2973 : 12030734 : if (offmemok && REG_P (op))
2974 : : {
2975 : 762175 : if (lra_dump_file != NULL)
2976 : 0 : fprintf
2977 : 0 : (lra_dump_file,
2978 : : " %d Spill pseudo into memory: reject+=3\n",
2979 : : nop);
2980 : 762175 : reject += 3;
2981 : : }
2982 : : else
2983 : : {
2984 : 11268559 : if (lra_dump_file != NULL)
2985 : 0 : fprintf
2986 : 0 : (lra_dump_file,
2987 : : " %d Non-prefered reload: reject+=%d\n",
2988 : : nop, LRA_MAX_REJECT);
2989 : 11268559 : reject += LRA_MAX_REJECT;
2990 : : }
2991 : : }
2992 : :
2993 : 141767280 : if (! (MEM_P (op) && offmemok)
2994 : 141767204 : && ! (const_to_mem && constmemok))
2995 : : {
2996 : : /* We prefer to reload pseudos over reloading other
2997 : : things, since such reloads may be able to be
2998 : : eliminated later. So bump REJECT in other cases.
2999 : : Don't do this in the case where we are forcing a
3000 : : constant into memory and it will then win since
3001 : : we don't want to have a different alternative
3002 : : match then. */
3003 : 140891421 : if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
3004 : : {
3005 : 95301625 : if (lra_dump_file != NULL)
3006 : 1489 : fprintf
3007 : 1489 : (lra_dump_file,
3008 : : " %d Non-pseudo reload: reject+=2\n",
3009 : : nop);
3010 : 95301625 : reject += 2;
3011 : : }
3012 : :
3013 : 140891421 : if (! no_regs_p)
3014 : 132827694 : reload_nregs
3015 : 132827694 : += ira_reg_class_max_nregs[this_alternative][mode];
3016 : :
3017 : 140891421 : if (SMALL_REGISTER_CLASS_P (this_alternative))
3018 : : {
3019 : 884637 : if (lra_dump_file != NULL)
3020 : 69 : fprintf
3021 : 69 : (lra_dump_file,
3022 : : " %d Small class reload: reject+=%d\n",
3023 : : nop, LRA_LOSER_COST_FACTOR / 2);
3024 : 884637 : reject += LRA_LOSER_COST_FACTOR / 2;
3025 : : }
3026 : : }
3027 : :
3028 : : /* We are trying to spill pseudo into memory. It is
3029 : : usually more costly than moving to a hard register
3030 : : although it might takes the same number of
3031 : : reloads.
3032 : :
3033 : : Non-pseudo spill may happen also. Suppose a target allows both
3034 : : register and memory in the operand constraint alternatives,
3035 : : then it's typical that an eliminable register has a substition
3036 : : of "base + offset" which can either be reloaded by a simple
3037 : : "new_reg <= base + offset" which will match the register
3038 : : constraint, or a similar reg addition followed by further spill
3039 : : to and reload from memory which will match the memory
3040 : : constraint, but this memory spill will be much more costly
3041 : : usually.
3042 : :
3043 : : Code below increases the reject for both pseudo and non-pseudo
3044 : : spill. */
3045 : 141767280 : if (no_regs_p
3046 : 8824058 : && !(MEM_P (op) && offmemok)
3047 : 8824012 : && !(REG_P (op) && hard_regno[nop] < 0))
3048 : : {
3049 : 7554541 : if (lra_dump_file != NULL)
3050 : 18 : fprintf
3051 : 26 : (lra_dump_file,
3052 : : " %d Spill %spseudo into memory: reject+=3\n",
3053 : : nop, REG_P (op) ? "" : "Non-");
3054 : 7554541 : reject += 3;
3055 : 7554541 : if (VECTOR_MODE_P (mode))
3056 : : {
3057 : : /* Spilling vectors into memory is usually more
3058 : : costly as they contain big values. */
3059 : 375073 : if (lra_dump_file != NULL)
3060 : 0 : fprintf
3061 : 0 : (lra_dump_file,
3062 : : " %d Spill vector pseudo: reject+=2\n",
3063 : : nop);
3064 : 375073 : reject += 2;
3065 : : }
3066 : : }
3067 : :
3068 : : /* When we use an operand requiring memory in given
3069 : : alternative, the insn should write *and* read the
3070 : : value to/from memory it is costly in comparison with
3071 : : an insn alternative which does not use memory
3072 : : (e.g. register or immediate operand). We exclude
3073 : : memory operand for such case as we can satisfy the
3074 : : memory constraints by reloading address. */
3075 : 141767280 : if (no_regs_p && offmemok && !MEM_P (op))
3076 : : {
3077 : 8823750 : if (lra_dump_file != NULL)
3078 : 32 : fprintf
3079 : 32 : (lra_dump_file,
3080 : : " Using memory insn operand %d: reject+=3\n",
3081 : : nop);
3082 : 8823750 : reject += 3;
3083 : : }
3084 : :
3085 : : /* If reload requires moving value through secondary
3086 : : memory, it will need one more insn at least. */
3087 : 141767280 : if (this_alternative != NO_REGS
3088 : 132942934 : && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS
3089 : 170858707 : && ((curr_static_id->operand[nop].type != OP_OUT
3090 : 15993444 : && targetm.secondary_memory_needed (GET_MODE (op), cl,
3091 : : this_alternative))
3092 : 25633800 : || (curr_static_id->operand[nop].type != OP_IN
3093 : 13098332 : && (targetm.secondary_memory_needed
3094 : 13098332 : (GET_MODE (op), this_alternative, cl)))))
3095 : 10248113 : losers++;
3096 : :
3097 : 141767280 : if (MEM_P (op) && offmemok)
3098 : 76 : addr_losers++;
3099 : : else
3100 : : {
3101 : : /* Input reloads can be inherited more often than
3102 : : output reloads can be removed, so penalize output
3103 : : reloads. */
3104 : 141767204 : if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN)
3105 : : {
3106 : 119040344 : if (lra_dump_file != NULL)
3107 : 1577 : fprintf
3108 : 1577 : (lra_dump_file,
3109 : : " %d Non input pseudo reload: reject++\n",
3110 : : nop);
3111 : 119040344 : reject++;
3112 : : }
3113 : :
3114 : 141767204 : if (curr_static_id->operand[nop].type == OP_INOUT)
3115 : : {
3116 : 374 : if (lra_dump_file != NULL)
3117 : 0 : fprintf
3118 : 0 : (lra_dump_file,
3119 : : " %d Input/Output reload: reject+=%d\n",
3120 : : nop, LRA_LOSER_COST_FACTOR);
3121 : 374 : reject += LRA_LOSER_COST_FACTOR;
3122 : : }
3123 : : }
3124 : : }
3125 : :
3126 : 389781982 : if (early_clobber_p && ! scratch_p)
3127 : : {
3128 : 152411 : if (lra_dump_file != NULL)
3129 : 4 : fprintf (lra_dump_file,
3130 : : " %d Early clobber: reject++\n", nop);
3131 : 152411 : reject++;
3132 : : }
3133 : : /* ??? We check early clobbers after processing all operands
3134 : : (see loop below) and there we update the costs more.
3135 : : Should we update the cost (may be approximately) here
3136 : : because of early clobber register reloads or it is a rare
3137 : : or non-important thing to be worth to do it. */
3138 : 779563964 : overall = (losers * LRA_LOSER_COST_FACTOR + reject
3139 : 389781982 : - (addr_losers == losers ? static_reject : 0));
3140 : 389781982 : if ((best_losers == 0 || losers != 0) && best_overall < overall)
3141 : : {
3142 : 59838659 : if (lra_dump_file != NULL)
3143 : 948 : fprintf (lra_dump_file,
3144 : : " overall=%d,losers=%d -- refuse\n",
3145 : : overall, losers);
3146 : 59838659 : goto fail;
3147 : : }
3148 : :
3149 : 329943323 : if (update_and_check_small_class_inputs (nop, nalt,
3150 : : this_alternative))
3151 : : {
3152 : 0 : if (lra_dump_file != NULL)
3153 : 0 : fprintf (lra_dump_file,
3154 : : " not enough small class regs -- refuse\n");
3155 : 0 : goto fail;
3156 : : }
3157 : 329943323 : curr_alt[nop] = this_alternative;
3158 : 329943323 : curr_alt_set[nop] = this_alternative_set;
3159 : 329943323 : curr_alt_exclude_start_hard_regs[nop]
3160 : 329943323 : = this_alternative_exclude_start_hard_regs;
3161 : 329943323 : curr_alt_win[nop] = this_alternative_win;
3162 : 329943323 : curr_alt_match_win[nop] = this_alternative_match_win;
3163 : 329943323 : curr_alt_offmemok[nop] = this_alternative_offmemok;
3164 : 329943323 : curr_alt_matches[nop] = this_alternative_matches;
3165 : :
3166 : 329943323 : if (this_alternative_matches >= 0
3167 : 329943323 : && !did_match && !this_alternative_win)
3168 : 9156801 : curr_alt_win[this_alternative_matches] = false;
3169 : :
3170 : 329943323 : if (early_clobber_p && operand_reg[nop] != NULL_RTX)
3171 : 160048 : early_clobbered_nops[early_clobbered_regs_num++] = nop;
3172 : : }
3173 : :
3174 : 112602362 : if (curr_insn_set != NULL_RTX && n_operands == 2
3175 : : /* Prevent processing non-move insns. */
3176 : 92117395 : && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
3177 : 90129183 : || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
3178 : 198557774 : && ((! curr_alt_win[0] && ! curr_alt_win[1]
3179 : 5519004 : && REG_P (no_subreg_reg_operand[0])
3180 : 2864372 : && REG_P (no_subreg_reg_operand[1])
3181 : 1144447 : && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
3182 : 975364 : || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])))
3183 : 81749815 : || (! curr_alt_win[0] && curr_alt_win[1]
3184 : 24283402 : && REG_P (no_subreg_reg_operand[1])
3185 : : /* Check that we reload memory not the memory
3186 : : address. */
3187 : 13684055 : && ! (curr_alt_offmemok[0]
3188 : 440940 : && MEM_P (no_subreg_reg_operand[0]))
3189 : 13684055 : && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))
3190 : 69425087 : || (curr_alt_win[0] && ! curr_alt_win[1]
3191 : 8846954 : && REG_P (no_subreg_reg_operand[0])
3192 : : /* Check that we reload memory not the memory
3193 : : address. */
3194 : 6517591 : && ! (curr_alt_offmemok[1]
3195 : 641970 : && MEM_P (no_subreg_reg_operand[1]))
3196 : 6517589 : && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1])
3197 : 106096135 : && (! CONST_POOL_OK_P (curr_operand_mode[1],
3198 : : no_subreg_reg_operand[1])
3199 : 2373504 : || (targetm.preferred_reload_class
3200 : 2373504 : (no_subreg_reg_operand[1],
3201 : : (enum reg_class) curr_alt[1]) != NO_REGS))
3202 : : /* If it is a result of recent elimination in move
3203 : : insn we can transform it into an add still by
3204 : : using this alternative. */
3205 : 5651058 : && GET_CODE (no_subreg_reg_operand[1]) != PLUS
3206 : : /* Likewise if the source has been replaced with an
3207 : : equivalent value. This only happens once -- the reload
3208 : : will use the equivalent value instead of the register it
3209 : : replaces -- so there should be no danger of cycling. */
3210 : 5524459 : && !equiv_substition_p[1])))
3211 : : {
3212 : : /* We have a move insn and a new reload insn will be similar
3213 : : to the current insn. We should avoid such situation as
3214 : : it results in LRA cycling. */
3215 : 18310609 : if (lra_dump_file != NULL)
3216 : 254 : fprintf (lra_dump_file,
3217 : : " Cycle danger: overall += LRA_MAX_REJECT\n");
3218 : 18310609 : overall += LRA_MAX_REJECT;
3219 : : }
3220 : 116495423 : ok_p = true;
3221 : : curr_alt_dont_inherit_ops_num = 0;
3222 : 116495423 : for (nop = 0; nop < early_clobbered_regs_num; nop++)
3223 : : {
3224 : 158020 : int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j;
3225 : 158020 : HARD_REG_SET temp_set;
3226 : :
3227 : 158020 : i = early_clobbered_nops[nop];
3228 : 158020 : if ((! curr_alt_win[i] && ! curr_alt_match_win[i])
3229 : 119173 : || hard_regno[i] < 0)
3230 : 157601 : continue;
3231 : 117735 : lra_assert (operand_reg[i] != NULL_RTX);
3232 : 117735 : clobbered_hard_regno = hard_regno[i];
3233 : 117735 : CLEAR_HARD_REG_SET (temp_set);
3234 : 117735 : add_to_hard_reg_set (&temp_set, GET_MODE (*curr_id->operand_loc[i]),
3235 : : clobbered_hard_regno);
3236 : 117735 : first_conflict_j = last_conflict_j = -1;
3237 : 596737 : for (j = 0; j < n_operands; j++)
3238 : 479003 : if (j == i
3239 : : /* We don't want process insides of match_operator and
3240 : : match_parallel because otherwise we would process
3241 : : their operands once again generating a wrong
3242 : : code. */
3243 : 361268 : || curr_static_id->operand[j].is_operator)
3244 : 120006 : continue;
3245 : 358997 : else if ((curr_alt_matches[j] == i && curr_alt_match_win[j])
3246 : 340304 : || (curr_alt_matches[i] == j && curr_alt_match_win[i]))
3247 : 18693 : continue;
3248 : : /* If we don't reload j-th operand, check conflicts. */
3249 : 114629 : else if ((curr_alt_win[j] || curr_alt_match_win[j])
3250 : 397787 : && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set))
3251 : : {
3252 : 744 : if (first_conflict_j < 0)
3253 : 419 : first_conflict_j = j;
3254 : 744 : last_conflict_j = j;
3255 : : /* Both the earlyclobber operand and conflicting operand
3256 : : cannot both be user defined hard registers. */
3257 : 744 : if (HARD_REGISTER_P (operand_reg[i])
3258 : 1 : && REG_USERVAR_P (operand_reg[i])
3259 : 1 : && operand_reg[j] != NULL_RTX
3260 : 1 : && HARD_REGISTER_P (operand_reg[j])
3261 : 745 : && REG_USERVAR_P (operand_reg[j]))
3262 : : {
3263 : : /* For asm, let curr_insn_transform diagnose it. */
3264 : 1 : if (INSN_CODE (curr_insn) < 0)
3265 : 1 : return false;
3266 : 0 : fatal_insn ("unable to generate reloads for "
3267 : : "impossible constraints:", curr_insn);
3268 : : }
3269 : : }
3270 : 117734 : if (last_conflict_j < 0)
3271 : 117316 : continue;
3272 : :
3273 : : /* If an earlyclobber operand conflicts with another non-matching
3274 : : operand (ie, they have been assigned the same hard register),
3275 : : then it is better to reload the other operand, as there may
3276 : : exist yet another operand with a matching constraint associated
3277 : : with the earlyclobber operand. However, if one of the operands
3278 : : is an explicit use of a hard register, then we must reload the
3279 : : other non-hard register operand. */
3280 : 418 : if (HARD_REGISTER_P (operand_reg[i])
3281 : 418 : || (first_conflict_j == last_conflict_j
3282 : 93 : && operand_reg[last_conflict_j] != NULL_RTX
3283 : 60 : && !curr_alt_match_win[last_conflict_j]
3284 : 60 : && !HARD_REGISTER_P (operand_reg[last_conflict_j])))
3285 : : {
3286 : 60 : curr_alt_win[last_conflict_j] = false;
3287 : 60 : curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++]
3288 : 60 : = last_conflict_j;
3289 : 60 : losers++;
3290 : 60 : if (lra_dump_file != NULL)
3291 : 0 : fprintf
3292 : 0 : (lra_dump_file,
3293 : : " %d Conflict early clobber reload: reject--\n",
3294 : : i);
3295 : : }
3296 : : else
3297 : : {
3298 : : /* We need to reload early clobbered register and the
3299 : : matched registers. */
3300 : 1778 : for (j = 0; j < n_operands; j++)
3301 : 1420 : if (curr_alt_matches[j] == i)
3302 : : {
3303 : 0 : curr_alt_match_win[j] = false;
3304 : 0 : losers++;
3305 : 0 : overall += LRA_LOSER_COST_FACTOR;
3306 : : }
3307 : 358 : if (! curr_alt_match_win[i])
3308 : 358 : curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i;
3309 : : else
3310 : : {
3311 : : /* Remember pseudos used for match reloads are never
3312 : : inherited. */
3313 : 0 : lra_assert (curr_alt_matches[i] >= 0);
3314 : 0 : curr_alt_win[curr_alt_matches[i]] = false;
3315 : : }
3316 : 358 : curr_alt_win[i] = curr_alt_match_win[i] = false;
3317 : 358 : losers++;
3318 : 358 : if (lra_dump_file != NULL)
3319 : 0 : fprintf
3320 : 0 : (lra_dump_file,
3321 : : " %d Matched conflict early clobber reloads: "
3322 : : "reject--\n",
3323 : : i);
3324 : : }
3325 : : /* Early clobber was already reflected in REJECT. */
3326 : 418 : if (!matching_early_clobber[i])
3327 : : {
3328 : 418 : lra_assert (reject > 0);
3329 : 418 : reject--;
3330 : 418 : matching_early_clobber[i] = 1;
3331 : : }
3332 : 418 : overall += LRA_LOSER_COST_FACTOR - 1;
3333 : : }
3334 : 116337403 : if (lra_dump_file != NULL)
3335 : 1739 : fprintf (lra_dump_file, " overall=%d,losers=%d,rld_nregs=%d\n",
3336 : : overall, losers, reload_nregs);
3337 : :
3338 : : /* If this alternative can be made to work by reloading, and it
3339 : : needs less reloading than the others checked so far, record
3340 : : it as the chosen goal for reloading. */
3341 : 116337403 : if ((best_losers != 0 && losers == 0)
3342 : 48100715 : || (((best_losers == 0 && losers == 0)
3343 : 47212641 : || (best_losers != 0 && losers != 0))
3344 : 48100715 : && (best_overall > overall
3345 : 13995031 : || (best_overall == overall
3346 : : /* If the cost of the reloads is the same,
3347 : : prefer alternative which requires minimal
3348 : : number of reload regs. */
3349 : 10177773 : && (reload_nregs < best_reload_nregs
3350 : 10075785 : || (reload_nregs == best_reload_nregs
3351 : 10033862 : && (best_reload_sum < reload_sum
3352 : 10018304 : || (best_reload_sum == reload_sum
3353 : 9998391 : && nalt < goal_alt_number))))))))
3354 : : {
3355 : 329290532 : for (nop = 0; nop < n_operands; nop++)
3356 : : {
3357 : 226619752 : goal_alt_win[nop] = curr_alt_win[nop];
3358 : 226619752 : goal_alt_match_win[nop] = curr_alt_match_win[nop];
3359 : 226619752 : goal_alt_matches[nop] = curr_alt_matches[nop];
3360 : 226619752 : goal_alt[nop] = curr_alt[nop];
3361 : 226619752 : goal_alt_exclude_start_hard_regs[nop]
3362 : 226619752 : = curr_alt_exclude_start_hard_regs[nop];
3363 : 226619752 : goal_alt_offmemok[nop] = curr_alt_offmemok[nop];
3364 : : }
3365 : 102670780 : goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num;
3366 : 102670780 : goal_reuse_alt_p = curr_reuse_alt_p;
3367 : 102671185 : for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++)
3368 : 405 : goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop];
3369 : 102670780 : goal_alt_swapped = curr_swapped;
3370 : 102670780 : goal_alt_out_sp_reload_p = curr_alt_out_sp_reload_p;
3371 : 102670780 : best_overall = overall;
3372 : 102670780 : best_losers = losers;
3373 : 102670780 : best_reload_nregs = reload_nregs;
3374 : 102670780 : best_reload_sum = reload_sum;
3375 : 102670780 : goal_alt_number = nalt;
3376 : : }
3377 : 116337403 : if (losers == 0 && !curr_alt_class_change_p)
3378 : : /* Everything is satisfied. Do not process alternatives
3379 : : anymore. */
3380 : : break;
3381 : 47226568 : fail:
3382 : 149652349 : ;
3383 : : }
3384 : : return ok_p;
3385 : : }
3386 : :
3387 : : /* Make reload base reg from address AD. */
3388 : : static rtx
3389 : 52 : base_to_reg (struct address_info *ad)
3390 : : {
3391 : 52 : enum reg_class cl;
3392 : 52 : int code = -1;
3393 : 52 : rtx new_inner = NULL_RTX;
3394 : 52 : rtx new_reg = NULL_RTX;
3395 : 52 : rtx_insn *insn;
3396 : 52 : rtx_insn *last_insn = get_last_insn();
3397 : :
3398 : 52 : lra_assert (ad->disp == ad->disp_term);
3399 : 52 : cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3400 : : get_index_code (ad));
3401 : 52 : new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, cl, NULL,
3402 : : "base");
3403 : 52 : new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg,
3404 : 52 : ad->disp_term == NULL
3405 : : ? const0_rtx
3406 : : : *ad->disp_term);
3407 : 52 : if (!valid_address_p (ad->mode, new_inner, ad->as))
3408 : : return NULL_RTX;
3409 : 0 : insn = emit_insn (gen_rtx_SET (new_reg, *ad->base));
3410 : 0 : code = recog_memoized (insn);
3411 : 0 : if (code < 0)
3412 : : {
3413 : 0 : delete_insns_since (last_insn);
3414 : 0 : return NULL_RTX;
3415 : : }
3416 : :
3417 : : return new_inner;
3418 : : }
3419 : :
3420 : : /* Make reload base reg + DISP from address AD. Return the new pseudo. */
3421 : : static rtx
3422 : 95 : base_plus_disp_to_reg (struct address_info *ad, rtx disp)
3423 : : {
3424 : 95 : enum reg_class cl;
3425 : 95 : rtx new_reg;
3426 : :
3427 : 95 : lra_assert (ad->base == ad->base_term);
3428 : 95 : cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code,
3429 : : get_index_code (ad));
3430 : 95 : new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, cl, NULL,
3431 : : "base + disp");
3432 : 95 : lra_emit_add (new_reg, *ad->base_term, disp);
3433 : 95 : return new_reg;
3434 : : }
3435 : :
3436 : : /* Make reload of index part of address AD. Return the new
3437 : : pseudo. */
3438 : : static rtx
3439 : 0 : index_part_to_reg (struct address_info *ad, enum reg_class index_class)
3440 : : {
3441 : 0 : rtx new_reg;
3442 : :
3443 : 0 : new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX,
3444 : : index_class, NULL, "index term");
3445 : 0 : expand_mult (GET_MODE (*ad->index), *ad->index_term,
3446 : : GEN_INT (get_index_scale (ad)), new_reg, 1);
3447 : 0 : return new_reg;
3448 : : }
3449 : :
3450 : : /* Return true if we can add a displacement to address AD, even if that
3451 : : makes the address invalid. The fix-up code requires any new address
3452 : : to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
3453 : : static bool
3454 : 8502 : can_add_disp_p (struct address_info *ad)
3455 : : {
3456 : 8502 : return (!ad->autoinc_p
3457 : 8502 : && ad->segment == NULL
3458 : 8502 : && ad->base == ad->base_term
3459 : 17004 : && ad->disp == ad->disp_term);
3460 : : }
3461 : :
3462 : : /* Make equiv substitution in address AD. Return true if a substitution
3463 : : was made. */
3464 : : static bool
3465 : 35337154 : equiv_address_substitution (struct address_info *ad)
3466 : : {
3467 : 35337154 : rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term;
3468 : 35337154 : poly_int64 disp;
3469 : 35337154 : HOST_WIDE_INT scale;
3470 : 35337154 : bool change_p;
3471 : :
3472 : 35337154 : base_term = strip_subreg (ad->base_term);
3473 : 7354 : if (base_term == NULL)
3474 : : base_reg = new_base_reg = NULL_RTX;
3475 : : else
3476 : : {
3477 : 29432302 : base_reg = *base_term;
3478 : 29432302 : new_base_reg = get_equiv_with_elimination (base_reg, curr_insn);
3479 : : }
3480 : 35337154 : index_term = strip_subreg (ad->index_term);
3481 : 5519 : if (index_term == NULL)
3482 : : index_reg = new_index_reg = NULL_RTX;
3483 : : else
3484 : : {
3485 : 1513867 : index_reg = *index_term;
3486 : 1513867 : new_index_reg = get_equiv_with_elimination (index_reg, curr_insn);
3487 : : }
3488 : 35337154 : if (base_reg == new_base_reg && index_reg == new_index_reg)
3489 : : return false;
3490 : 99121 : disp = 0;
3491 : 99121 : change_p = false;
3492 : 99121 : if (lra_dump_file != NULL)
3493 : : {
3494 : 0 : fprintf (lra_dump_file, "Changing address in insn %d ",
3495 : 0 : INSN_UID (curr_insn));
3496 : 0 : dump_value_slim (lra_dump_file, *ad->outer, 1);
3497 : : }
3498 : 99121 : if (base_reg != new_base_reg)
3499 : : {
3500 : 98202 : poly_int64 offset;
3501 : 98202 : if (REG_P (new_base_reg))
3502 : : {
3503 : 465 : *base_term = new_base_reg;
3504 : 465 : change_p = true;
3505 : : }
3506 : 97737 : else if (GET_CODE (new_base_reg) == PLUS
3507 : 8502 : && REG_P (XEXP (new_base_reg, 0))
3508 : 8502 : && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset)
3509 : 106239 : && can_add_disp_p (ad))
3510 : : {
3511 : 8502 : disp += offset;
3512 : 8502 : *base_term = XEXP (new_base_reg, 0);
3513 : 8502 : change_p = true;
3514 : : }
3515 : 98202 : if (ad->base_term2 != NULL)
3516 : 0 : *ad->base_term2 = *ad->base_term;
3517 : : }
3518 : 99121 : if (index_reg != new_index_reg)
3519 : : {
3520 : 1090 : poly_int64 offset;
3521 : 1090 : if (REG_P (new_index_reg))
3522 : : {
3523 : 0 : *index_term = new_index_reg;
3524 : 0 : change_p = true;
3525 : : }
3526 : 1090 : else if (GET_CODE (new_index_reg) == PLUS
3527 : 0 : && REG_P (XEXP (new_index_reg, 0))
3528 : 0 : && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset)
3529 : 0 : && can_add_disp_p (ad)
3530 : 1090 : && (scale = get_index_scale (ad)))
3531 : : {
3532 : 0 : disp += offset * scale;
3533 : 0 : *index_term = XEXP (new_index_reg, 0);
3534 : 0 : change_p = true;
3535 : : }
3536 : : }
3537 : 99121 : if (maybe_ne (disp, 0))
3538 : : {
3539 : 8502 : if (ad->disp != NULL)
3540 : 1483 : *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp);
3541 : : else
3542 : : {
3543 : 7019 : *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp);
3544 : 7019 : update_address (ad);
3545 : : }
3546 : : change_p = true;
3547 : : }
3548 : 99121 : if (lra_dump_file != NULL)
3549 : : {
3550 : 0 : if (! change_p)
3551 : 0 : fprintf (lra_dump_file, " -- no change\n");
3552 : : else
3553 : : {
3554 : 0 : fprintf (lra_dump_file, " on equiv ");
3555 : 0 : dump_value_slim (lra_dump_file, *ad->outer, 1);
3556 : 0 : fprintf (lra_dump_file, "\n");
3557 : : }
3558 : : }
3559 : : return change_p;
3560 : : }
3561 : :
3562 : : /* Skip all modifiers and whitespaces in constraint STR and return the
3563 : : result. */
3564 : : static const char *
3565 : 463660809 : skip_constraint_modifiers (const char *str)
3566 : : {
3567 : 655745241 : for (;;str++)
3568 : 559703025 : switch (*str)
3569 : : {
3570 : 96042216 : case '+': case '&' : case '=': case '*': case ' ': case '\t':
3571 : 96042216 : case '$': case '^' : case '%': case '?': case '!':
3572 : 96042216 : break;
3573 : 463660809 : default: return str;
3574 : : }
3575 : : }
3576 : :
3577 : : /* Takes a string of 0 or more comma-separated constraints. When more
3578 : : than one constraint is present, evaluate whether they all correspond
3579 : : to a single, repeated constraint (e.g. "r,r") or whether we have
3580 : : more than one distinct constraints (e.g. "r,m"). */
3581 : : static bool
3582 : 147541291 : constraint_unique (const char *cstr)
3583 : : {
3584 : 147541291 : enum constraint_num ca, cb;
3585 : 147541291 : ca = CONSTRAINT__UNKNOWN;
3586 : 290927134 : for (;;)
3587 : : {
3588 : 290927134 : cstr = skip_constraint_modifiers (cstr);
3589 : 290927134 : if (*cstr == '\0' || *cstr == ',')
3590 : : cb = CONSTRAINT_X;
3591 : : else
3592 : : {
3593 : 290927134 : cb = lookup_constraint (cstr);
3594 : 290927134 : if (cb == CONSTRAINT__UNKNOWN)
3595 : : return false;
3596 : 279614002 : cstr += CONSTRAINT_LEN (cstr[0], cstr);
3597 : : }
3598 : : /* Handle the first iteration of the loop. */
3599 : 279614002 : if (ca == CONSTRAINT__UNKNOWN)
3600 : : ca = cb;
3601 : : /* Handle the general case of comparing ca with subsequent
3602 : : constraints. */
3603 : 143256837 : else if (ca != cb)
3604 : : return false;
3605 : 149803579 : if (*cstr == '\0')
3606 : : return true;
3607 : 143385843 : if (*cstr == ',')
3608 : 70197253 : cstr += 1;
3609 : : }
3610 : : }
3611 : :
3612 : : /* Major function to make reloads for an address in operand NOP or
3613 : : check its correctness (If CHECK_ONLY_P is true). The supported
3614 : : cases are:
3615 : :
3616 : : 1) an address that existed before LRA started, at which point it
3617 : : must have been valid. These addresses are subject to elimination
3618 : : and may have become invalid due to the elimination offset being out
3619 : : of range.
3620 : :
3621 : : 2) an address created by forcing a constant to memory
3622 : : (force_const_to_mem). The initial form of these addresses might
3623 : : not be valid, and it is this function's job to make them valid.
3624 : :
3625 : : 3) a frame address formed from a register and a (possibly zero)
3626 : : constant offset. As above, these addresses might not be valid and
3627 : : this function must make them so.
3628 : :
3629 : : Add reloads to the lists *BEFORE and *AFTER. We might need to add
3630 : : reloads to *AFTER because of inc/dec, {pre, post} modify in the
3631 : : address. Return true for any RTL change.
3632 : :
3633 : : The function is a helper function which does not produce all
3634 : : transformations (when CHECK_ONLY_P is false) which can be
3635 : : necessary. It does just basic steps. To do all necessary
3636 : : transformations use function process_address. */
3637 : : static bool
3638 : 159832704 : process_address_1 (int nop, bool check_only_p,
3639 : : rtx_insn **before, rtx_insn **after)
3640 : : {
3641 : 159832704 : struct address_info ad;
3642 : 159832704 : rtx new_reg;
3643 : 159832704 : HOST_WIDE_INT scale;
3644 : 159832704 : rtx op = *curr_id->operand_loc[nop];
3645 : 159832704 : rtx mem = extract_mem_from_operand (op);
3646 : 159832704 : const char *constraint;
3647 : 159832704 : enum constraint_num cn;
3648 : 159832704 : bool change_p = false;
3649 : :
3650 : 159832704 : if (MEM_P (mem)
3651 : 34354328 : && GET_MODE (mem) == BLKmode
3652 : 23970 : && GET_CODE (XEXP (mem, 0)) == SCRATCH)
3653 : : return false;
3654 : :
3655 : 159832704 : constraint
3656 : 159832704 : = skip_constraint_modifiers (curr_static_id->operand[nop].constraint);
3657 : 159832704 : if (IN_RANGE (constraint[0], '0', '9'))
3658 : : {
3659 : 12900971 : char *end;
3660 : 12900971 : unsigned long dup = strtoul (constraint, &end, 10);
3661 : 12900971 : constraint
3662 : 12900971 : = skip_constraint_modifiers (curr_static_id->operand[dup].constraint);
3663 : : }
3664 : 171134749 : cn = lookup_constraint (*constraint == '\0' ? "X" : constraint);
3665 : : /* If we have several alternatives or/and several constraints in an
3666 : : alternative and we can not say at this stage what constraint will be used,
3667 : : use unknown constraint. The exception is an address constraint. If
3668 : : operand has one address constraint, probably all others constraints are
3669 : : address ones. */
3670 : 148530659 : if (constraint[0] != '\0' && get_constraint_type (cn) != CT_ADDRESS
3671 : 307373995 : && !constraint_unique (constraint))
3672 : : cn = CONSTRAINT__UNKNOWN;
3673 : 159832704 : if (insn_extra_address_constraint (cn)
3674 : : /* When we find an asm operand with an address constraint that
3675 : : doesn't satisfy address_operand to begin with, we clear
3676 : : is_address, so that we don't try to make a non-address fit.
3677 : : If the asm statement got this far, it's because other
3678 : : constraints are available, and we'll use them, disregarding
3679 : : the unsatisfiable address ones. */
3680 : 159832704 : && curr_static_id->operand[nop].is_address)
3681 : 989349 : decompose_lea_address (&ad, curr_id->operand_loc[nop]);
3682 : : /* Do not attempt to decompose arbitrary addresses generated by combine
3683 : : for asm operands with loose constraints, e.g 'X'.
3684 : : Need to extract memory from op for special memory constraint,
3685 : : i.e. bcst_mem_operand in i386 backend. */
3686 : 158843355 : else if (MEM_P (mem)
3687 : 158843580 : && !(INSN_CODE (curr_insn) < 0
3688 : 17987 : && get_constraint_type (cn) == CT_FIXED_FORM
3689 : 225 : && constraint_satisfied_p (op, cn)))
3690 : 34354103 : decompose_mem_address (&ad, mem);
3691 : 124489252 : else if (GET_CODE (op) == SUBREG
3692 : 3572924 : && MEM_P (SUBREG_REG (op)))
3693 : 0 : decompose_mem_address (&ad, SUBREG_REG (op));
3694 : : else
3695 : : return false;
3696 : : /* If INDEX_REG_CLASS is assigned to base_term already and isn't to
3697 : : index_term, swap them so to avoid assigning INDEX_REG_CLASS to both
3698 : : when INDEX_REG_CLASS is a single register class. */
3699 : 35343452 : enum reg_class index_cl = index_reg_class (curr_insn);
3700 : 35343452 : if (ad.base_term != NULL
3701 : 29438455 : && ad.index_term != NULL
3702 : 1150444 : && ira_class_hard_regs_num[index_cl] == 1
3703 : 0 : && REG_P (*ad.base_term)
3704 : 0 : && REG_P (*ad.index_term)
3705 : 0 : && in_class_p (*ad.base_term, index_cl, NULL)
3706 : 35343452 : && ! in_class_p (*ad.index_term, index_cl, NULL))
3707 : : {
3708 : 0 : std::swap (ad.base, ad.index);
3709 : 0 : std::swap (ad.base_term, ad.index_term);
3710 : : }
3711 : 35343452 : if (! check_only_p)
3712 : 35337154 : change_p = equiv_address_substitution (&ad);
3713 : 35343452 : if (ad.base_term != NULL
3714 : 64781907 : && (process_addr_reg
3715 : 58876910 : (ad.base_term, check_only_p, before,
3716 : 29438455 : (ad.autoinc_p
3717 : 4110788 : && !(REG_P (*ad.base_term)
3718 : 2055394 : && find_regno_note (curr_insn, REG_DEAD,
3719 : : REGNO (*ad.base_term)) != NULL_RTX)
3720 : : ? after : NULL),
3721 : 29438455 : base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3722 : : get_index_code (&ad), curr_insn))))
3723 : : {
3724 : 371008 : change_p = true;
3725 : 371008 : if (ad.base_term2 != NULL)
3726 : 0 : *ad.base_term2 = *ad.base_term;
3727 : : }
3728 : 35343452 : if (ad.index_term != NULL
3729 : 35343452 : && process_addr_reg (ad.index_term, check_only_p,
3730 : : before, NULL, index_cl))
3731 : : change_p = true;
3732 : :
3733 : : /* Target hooks sometimes don't treat extra-constraint addresses as
3734 : : legitimate address_operands, so handle them specially. */
3735 : 35343452 : if (insn_extra_address_constraint (cn)
3736 : 35343452 : && satisfies_address_constraint_p (&ad, cn))
3737 : : return change_p;
3738 : :
3739 : 34354111 : if (check_only_p)
3740 : : return change_p;
3741 : :
3742 : : /* There are three cases where the shape of *AD.INNER may now be invalid:
3743 : :
3744 : : 1) the original address was valid, but either elimination or
3745 : : equiv_address_substitution was applied and that made
3746 : : the address invalid.
3747 : :
3748 : : 2) the address is an invalid symbolic address created by
3749 : : force_const_to_mem.
3750 : :
3751 : : 3) the address is a frame address with an invalid offset.
3752 : :
3753 : : 4) the address is a frame address with an invalid base.
3754 : :
3755 : : All these cases involve a non-autoinc address, so there is no
3756 : : point revalidating other types. */
3757 : 34348290 : if (ad.autoinc_p || valid_address_p (op, &ad, cn))
3758 : 34347865 : return change_p;
3759 : :
3760 : : /* Any index existed before LRA started, so we can assume that the
3761 : : presence and shape of the index is valid. */
3762 : 425 : push_to_sequence (*before);
3763 : 425 : lra_assert (ad.disp == ad.disp_term);
3764 : 425 : if (ad.base == NULL)
3765 : : {
3766 : 330 : if (ad.index == NULL)
3767 : : {
3768 : 330 : rtx_insn *insn;
3769 : 330 : rtx_insn *last = get_last_insn ();
3770 : 330 : int code = -1;
3771 : 330 : enum reg_class cl = base_reg_class (ad.mode, ad.as,
3772 : : SCRATCH, SCRATCH,
3773 : : curr_insn);
3774 : 330 : rtx addr = *ad.inner;
3775 : :
3776 : 330 : new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "addr");
3777 : 330 : if (HAVE_lo_sum)
3778 : : {
3779 : : /* addr => lo_sum (new_base, addr), case (2) above. */
3780 : : insn = emit_insn (gen_rtx_SET
3781 : : (new_reg,
3782 : : gen_rtx_HIGH (Pmode, copy_rtx (addr))));
3783 : : code = recog_memoized (insn);
3784 : : if (code >= 0)
3785 : : {
3786 : : *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr);
3787 : : if (!valid_address_p (op, &ad, cn))
3788 : : {
3789 : : /* Try to put lo_sum into register. */
3790 : : insn = emit_insn (gen_rtx_SET
3791 : : (new_reg,
3792 : : gen_rtx_LO_SUM (Pmode, new_reg, addr)));
3793 : : code = recog_memoized (insn);
3794 : : if (code >= 0)
3795 : : {
3796 : : *ad.inner = new_reg;
3797 : : if (!valid_address_p (op, &ad, cn))
3798 : : {
3799 : : *ad.inner = addr;
3800 : : code = -1;
3801 : : }
3802 : : }
3803 : :
3804 : : }
3805 : : }
3806 : : if (code < 0)
3807 : : delete_insns_since (last);
3808 : : }
3809 : :
3810 : 330 : if (code < 0)
3811 : : {
3812 : : /* addr => new_base, case (2) above. */
3813 : 330 : lra_emit_move (new_reg, addr);
3814 : :
3815 : 660 : for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last);
3816 : 660 : insn != NULL_RTX;
3817 : 330 : insn = NEXT_INSN (insn))
3818 : 330 : if (recog_memoized (insn) < 0)
3819 : : break;
3820 : 330 : if (insn != NULL_RTX)
3821 : : {
3822 : : /* Do nothing if we cannot generate right insns.
3823 : : This is analogous to reload pass behavior. */
3824 : 0 : delete_insns_since (last);
3825 : 0 : end_sequence ();
3826 : 0 : return false;
3827 : : }
3828 : 330 : *ad.inner = new_reg;
3829 : : }
3830 : : }
3831 : : else
3832 : : {
3833 : : /* index * scale + disp => new base + index * scale,
3834 : : case (1) above. */
3835 : 0 : enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS,
3836 : 0 : GET_CODE (*ad.index),
3837 : : curr_insn);
3838 : :
3839 : 0 : lra_assert (index_cl != NO_REGS);
3840 : 0 : new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "disp");
3841 : 0 : lra_emit_move (new_reg, *ad.disp);
3842 : 0 : *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3843 : 0 : new_reg, *ad.index);
3844 : : }
3845 : : }
3846 : 95 : else if (ad.index == NULL)
3847 : : {
3848 : 52 : int regno;
3849 : 52 : enum reg_class cl;
3850 : 52 : rtx set;
3851 : 52 : rtx_insn *insns, *last_insn;
3852 : : /* Try to reload base into register only if the base is invalid
3853 : : for the address but with valid offset, case (4) above. */
3854 : 52 : start_sequence ();
3855 : 52 : new_reg = base_to_reg (&ad);
3856 : :
3857 : : /* base + disp => new base, cases (1) and (3) above. */
3858 : : /* Another option would be to reload the displacement into an
3859 : : index register. However, postreload has code to optimize
3860 : : address reloads that have the same base and different
3861 : : displacements, so reloading into an index register would
3862 : : not necessarily be a win. */
3863 : 52 : if (new_reg == NULL_RTX)
3864 : : {
3865 : : /* See if the target can split the displacement into a
3866 : : legitimate new displacement from a local anchor. */
3867 : 52 : gcc_assert (ad.disp == ad.disp_term);
3868 : 52 : poly_int64 orig_offset;
3869 : 52 : rtx offset1, offset2;
3870 : 52 : if (poly_int_rtx_p (*ad.disp, &orig_offset)
3871 : 52 : && targetm.legitimize_address_displacement (&offset1, &offset2,
3872 : : orig_offset,
3873 : : ad.mode))
3874 : : {
3875 : 0 : new_reg = base_plus_disp_to_reg (&ad, offset1);
3876 : 0 : new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2);
3877 : : }
3878 : : else
3879 : 52 : new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3880 : : }
3881 : 52 : insns = get_insns ();
3882 : 52 : last_insn = get_last_insn ();
3883 : : /* If we generated at least two insns, try last insn source as
3884 : : an address. If we succeed, we generate one less insn. */
3885 : 52 : if (REG_P (new_reg)
3886 : 52 : && last_insn != insns
3887 : 52 : && (set = single_set (last_insn)) != NULL_RTX
3888 : 52 : && GET_CODE (SET_SRC (set)) == PLUS
3889 : 52 : && REG_P (XEXP (SET_SRC (set), 0))
3890 : 104 : && CONSTANT_P (XEXP (SET_SRC (set), 1)))
3891 : : {
3892 : 0 : *ad.inner = SET_SRC (set);
3893 : 0 : if (valid_address_p (op, &ad, cn))
3894 : : {
3895 : 0 : *ad.base_term = XEXP (SET_SRC (set), 0);
3896 : 0 : *ad.disp_term = XEXP (SET_SRC (set), 1);
3897 : 0 : cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code,
3898 : : get_index_code (&ad), curr_insn);
3899 : 0 : regno = REGNO (*ad.base_term);
3900 : 0 : if (regno >= FIRST_PSEUDO_REGISTER
3901 : 0 : && cl != lra_get_allocno_class (regno))
3902 : 0 : lra_change_class (regno, cl, " Change to", true);
3903 : 0 : new_reg = SET_SRC (set);
3904 : 0 : delete_insns_since (PREV_INSN (last_insn));
3905 : : }
3906 : : }
3907 : 52 : end_sequence ();
3908 : 52 : emit_insn (insns);
3909 : 52 : *ad.inner = new_reg;
3910 : : }
3911 : 43 : else if (ad.disp_term != NULL)
3912 : : {
3913 : : /* base + scale * index + disp => new base + scale * index,
3914 : : case (1) above. */
3915 : 43 : gcc_assert (ad.disp == ad.disp_term);
3916 : 43 : new_reg = base_plus_disp_to_reg (&ad, *ad.disp);
3917 : 43 : *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3918 : 43 : new_reg, *ad.index);
3919 : : }
3920 : 0 : else if ((scale = get_index_scale (&ad)) == 1)
3921 : : {
3922 : : /* The last transformation to one reg will be made in
3923 : : curr_insn_transform function. */
3924 : 0 : end_sequence ();
3925 : 0 : return false;
3926 : : }
3927 : 0 : else if (scale != 0)
3928 : : {
3929 : : /* base + scale * index => base + new_reg,
3930 : : case (1) above.
3931 : : Index part of address may become invalid. For example, we
3932 : : changed pseudo on the equivalent memory and a subreg of the
3933 : : pseudo onto the memory of different mode for which the scale is
3934 : : prohibitted. */
3935 : 0 : new_reg = index_part_to_reg (&ad, index_cl);
3936 : 0 : *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg),
3937 : 0 : *ad.base_term, new_reg);
3938 : : }
3939 : : else
3940 : : {
3941 : 0 : enum reg_class cl = base_reg_class (ad.mode, ad.as,
3942 : : SCRATCH, SCRATCH,
3943 : : curr_insn);
3944 : 0 : rtx addr = *ad.inner;
3945 : :
3946 : 0 : new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, NULL, "addr");
3947 : : /* addr => new_base. */
3948 : 0 : lra_emit_move (new_reg, addr);
3949 : 0 : *ad.inner = new_reg;
3950 : : }
3951 : 425 : *before = get_insns ();
3952 : 425 : end_sequence ();
3953 : 425 : return true;
3954 : : }
3955 : :
3956 : : /* If CHECK_ONLY_P is false, do address reloads until it is necessary.
3957 : : Use process_address_1 as a helper function. Return true for any
3958 : : RTL changes.
3959 : :
3960 : : If CHECK_ONLY_P is true, just check address correctness. Return
3961 : : false if the address correct. */
3962 : : static bool
3963 : 159434350 : process_address (int nop, bool check_only_p,
3964 : : rtx_insn **before, rtx_insn **after)
3965 : : {
3966 : 159434350 : bool res = false;
3967 : :
3968 : 159832704 : while (process_address_1 (nop, check_only_p, before, after))
3969 : : {
3970 : 398354 : if (check_only_p)
3971 : : return true;
3972 : : res = true;
3973 : : }
3974 : : return res;
3975 : : }
3976 : :
3977 : : /* Override the generic address_reload_context in order to
3978 : : control the creation of reload pseudos. */
3979 : : class lra_autoinc_reload_context : public address_reload_context
3980 : : {
3981 : : machine_mode mode;
3982 : : enum reg_class rclass;
3983 : :
3984 : : public:
3985 : 0 : lra_autoinc_reload_context (machine_mode mode, enum reg_class new_rclass)
3986 : 0 : : mode (mode), rclass (new_rclass) {}
3987 : :
3988 : 0 : rtx get_reload_reg () const override final
3989 : : {
3990 : 0 : return lra_create_new_reg (mode, NULL_RTX, rclass, NULL, "INC/DEC result");
3991 : : }
3992 : : };
3993 : :
3994 : : /* Emit insns to reload VALUE into a new register. VALUE is an
3995 : : auto-increment or auto-decrement RTX whose operand is a register or
3996 : : memory location; so reloading involves incrementing that location.
3997 : :
3998 : : INC_AMOUNT is the number to increment or decrement by (always
3999 : : positive and ignored for POST_MODIFY/PRE_MODIFY).
4000 : :
4001 : : Return a pseudo containing the result. */
4002 : : static rtx
4003 : 0 : emit_inc (enum reg_class new_rclass, rtx value, poly_int64 inc_amount)
4004 : : {
4005 : 0 : lra_autoinc_reload_context context (GET_MODE (value), new_rclass);
4006 : 0 : return context.emit_autoinc (value, inc_amount);
4007 : : }
4008 : :
4009 : : /* Return true if the current move insn does not need processing as we
4010 : : already know that it satisfies its constraints. */
4011 : : static bool
4012 : 92833021 : simple_move_p (void)
4013 : : {
4014 : 92833021 : rtx dest, src;
4015 : 92833021 : enum reg_class dclass, sclass;
4016 : :
4017 : 92833021 : lra_assert (curr_insn_set != NULL_RTX);
4018 : 92833021 : dest = SET_DEST (curr_insn_set);
4019 : 92833021 : src = SET_SRC (curr_insn_set);
4020 : :
4021 : : /* If the instruction has multiple sets we need to process it even if it
4022 : : is single_set. This can happen if one or more of the SETs are dead.
4023 : : See PR73650. */
4024 : 92833021 : if (multiple_sets (curr_insn))
4025 : : return false;
4026 : :
4027 : 92645815 : return ((dclass = get_op_class (dest)) != NO_REGS
4028 : 20504156 : && (sclass = get_op_class (src)) != NO_REGS
4029 : : /* The backend guarantees that register moves of cost 2
4030 : : never need reloads. */
4031 : 84892784 : && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2);
4032 : : }
4033 : :
4034 : : /* Swap operands NOP and NOP + 1. */
4035 : : static inline void
4036 : 20092794 : swap_operands (int nop)
4037 : : {
4038 : 20092794 : std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]);
4039 : 20092794 : std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]);
4040 : 20092794 : std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]);
4041 : 20092794 : std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]);
4042 : : /* Swap the duplicates too. */
4043 : 20092794 : lra_update_dup (curr_id, nop);
4044 : 20092794 : lra_update_dup (curr_id, nop + 1);
4045 : 20092794 : }
4046 : :
4047 : : /* Main entry point of the constraint code: search the body of the
4048 : : current insn to choose the best alternative. It is mimicking insn
4049 : : alternative cost calculation model of former reload pass. That is
4050 : : because machine descriptions were written to use this model. This
4051 : : model can be changed in future. Make commutative operand exchange
4052 : : if it is chosen.
4053 : :
4054 : : if CHECK_ONLY_P is false, do RTL changes to satisfy the
4055 : : constraints. Return true if any change happened during function
4056 : : call.
4057 : :
4058 : : If CHECK_ONLY_P is true then don't do any transformation. Just
4059 : : check that the insn satisfies all constraints. If the insn does
4060 : : not satisfy any constraint, return true. */
4061 : : static bool
4062 : 98071781 : curr_insn_transform (bool check_only_p)
4063 : : {
4064 : 98071781 : int i, j, k;
4065 : 98071781 : int n_operands;
4066 : 98071781 : int n_alternatives;
4067 : 98071781 : int n_outputs;
4068 : 98071781 : int commutative;
4069 : 98071781 : signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS];
4070 : 98071781 : signed char match_inputs[MAX_RECOG_OPERANDS + 1];
4071 : 98071781 : signed char outputs[MAX_RECOG_OPERANDS + 1];
4072 : 98071781 : rtx_insn *before, *after;
4073 : 98071781 : bool alt_p = false;
4074 : : /* Flag that the insn has been changed through a transformation. */
4075 : 98071781 : bool change_p;
4076 : 98071781 : bool sec_mem_p;
4077 : 98071781 : bool use_sec_mem_p;
4078 : 98071781 : int max_regno_before;
4079 : 98071781 : int reused_alternative_num;
4080 : :
4081 : 98071781 : curr_insn_set = single_set (curr_insn);
4082 : 98071781 : if (curr_insn_set != NULL_RTX && simple_move_p ())
4083 : : {
4084 : : /* We assume that the corresponding insn alternative has no
4085 : : earlier clobbers. If it is not the case, don't define move
4086 : : cost equal to 2 for the corresponding register classes. */
4087 : 16770395 : lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT);
4088 : 16770395 : return false;
4089 : : }
4090 : :
4091 : 81301386 : no_input_reloads_p = no_output_reloads_p = false;
4092 : 81301386 : goal_alt_number = -1;
4093 : 81301386 : change_p = sec_mem_p = false;
4094 : :
4095 : : /* CALL_INSNs are not allowed to have any output reloads. */
4096 : 81301386 : if (CALL_P (curr_insn))
4097 : 5752131 : no_output_reloads_p = true;
4098 : :
4099 : 81301386 : n_operands = curr_static_id->n_operands;
4100 : 81301386 : n_alternatives = curr_static_id->n_alternatives;
4101 : :
4102 : : /* Just return "no reloads" if insn has no operands with
4103 : : constraints. */
4104 : 81301386 : if (n_operands == 0 || n_alternatives == 0)
4105 : : return false;
4106 : :
4107 : 71764613 : max_regno_before = max_reg_num ();
4108 : :
4109 : 304090052 : for (i = 0; i < n_operands; i++)
4110 : : {
4111 : 160560826 : goal_alt_matched[i][0] = -1;
4112 : 160560826 : goal_alt_matches[i] = -1;
4113 : : }
4114 : :
4115 : 71764613 : commutative = curr_static_id->commutative;
4116 : :
4117 : : /* Now see what we need for pseudos that didn't get hard regs or got
4118 : : the wrong kind of hard reg. For this, we must consider all the
4119 : : operands together against the register constraints. */
4120 : :
4121 : 71764613 : best_losers = best_overall = INT_MAX;
4122 : 71764613 : best_reload_sum = 0;
4123 : :
4124 : 71764613 : curr_swapped = false;
4125 : 71764613 : goal_alt_swapped = false;
4126 : :
4127 : 71764613 : if (! check_only_p)
4128 : : /* Make equivalence substitution and memory subreg elimination
4129 : : before address processing because an address legitimacy can
4130 : : depend on memory mode. */
4131 : 232272024 : for (i = 0; i < n_operands; i++)
4132 : : {
4133 : 160522885 : rtx op, subst, old;
4134 : 160522885 : bool op_change_p = false;
4135 : :
4136 : 160522885 : if (curr_static_id->operand[i].is_operator)
4137 : 1278376 : continue;
4138 : :
4139 : 159244509 : old = op = *curr_id->operand_loc[i];
4140 : 159244509 : if (GET_CODE (old) == SUBREG)
4141 : 3587142 : old = SUBREG_REG (old);
4142 : 159244509 : subst = get_equiv_with_elimination (old, curr_insn);
4143 : 159244509 : original_subreg_reg_mode[i] = VOIDmode;
4144 : 159244509 : equiv_substition_p[i] = false;
4145 : 159244509 : if (subst != old)
4146 : : {
4147 : 900329 : equiv_substition_p[i] = true;
4148 : 900329 : subst = copy_rtx (subst);
4149 : 900329 : lra_assert (REG_P (old));
4150 : 900329 : if (GET_CODE (op) != SUBREG)
4151 : 886634 : *curr_id->operand_loc[i] = subst;
4152 : : else
4153 : : {
4154 : 13695 : SUBREG_REG (op) = subst;
4155 : 13695 : if (GET_MODE (subst) == VOIDmode)
4156 : 49 : original_subreg_reg_mode[i] = GET_MODE (old);
4157 : : }
4158 : 900329 : if (lra_dump_file != NULL)
4159 : : {
4160 : 3 : fprintf (lra_dump_file,
4161 : : "Changing pseudo %d in operand %i of insn %u on equiv ",
4162 : 3 : REGNO (old), i, INSN_UID (curr_insn));
4163 : 3 : dump_value_slim (lra_dump_file, subst, 1);
4164 : 3 : fprintf (lra_dump_file, "\n");
4165 : : }
4166 : 900329 : op_change_p = change_p = true;
4167 : : }
4168 : 159244509 : if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p)
4169 : : {
4170 : 900953 : change_p = true;
4171 : 900953 : lra_update_dup (curr_id, i);
4172 : : }
4173 : : }
4174 : :
4175 : : /* Reload address registers and displacements. We do it before
4176 : : finding an alternative because of memory constraints. */
4177 : 71764613 : before = after = NULL;
4178 : 232325439 : for (i = 0; i < n_operands; i++)
4179 : 160560826 : if (! curr_static_id->operand[i].is_operator
4180 : 160560826 : && process_address (i, check_only_p, &before, &after))
4181 : : {
4182 : 398343 : if (check_only_p)
4183 : : return true;
4184 : 398343 : change_p = true;
4185 : 398343 : lra_update_dup (curr_id, i);
4186 : : }
4187 : :
4188 : 71764613 : if (change_p)
4189 : : /* If we've changed the instruction then any alternative that
4190 : : we chose previously may no longer be valid. */
4191 : 1259745 : lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT);
4192 : :
4193 : 71749139 : if (! check_only_p && curr_insn_set != NULL_RTX
4194 : 139823915 : && check_and_process_move (&change_p, &sec_mem_p))
4195 : 0 : return change_p;
4196 : :
4197 : 71764613 : try_swapped:
4198 : :
4199 : 81540493 : reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative;
4200 : 81540493 : if (lra_dump_file != NULL && reused_alternative_num >= 0)
4201 : 0 : fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n",
4202 : 0 : reused_alternative_num, INSN_UID (curr_insn));
4203 : :
4204 : 81540493 : if (process_alt_operands (reused_alternative_num))
4205 : 73330229 : alt_p = true;
4206 : :
4207 : 81540493 : if (check_only_p)
4208 : 26520 : return ! alt_p || best_losers != 0;
4209 : :
4210 : : /* If insn is commutative (it's safe to exchange a certain pair of
4211 : : operands) then we need to try each alternative twice, the second
4212 : : time matching those two operands as if we had exchanged them. To
4213 : : do this, really exchange them in operands.
4214 : :
4215 : : If we have just tried the alternatives the second time, return
4216 : : operands to normal and drop through. */
4217 : :
4218 : 81525019 : if (reused_alternative_num < 0 && commutative >= 0)
4219 : : {
4220 : 19551760 : curr_swapped = !curr_swapped;
4221 : 19551760 : if (curr_swapped)
4222 : : {
4223 : 9775880 : swap_operands (commutative);
4224 : 9775880 : goto try_swapped;
4225 : : }
4226 : : else
4227 : 9775880 : swap_operands (commutative);
4228 : : }
4229 : :
4230 : 71749139 : if (! alt_p && ! sec_mem_p)
4231 : : {
4232 : : /* No alternative works with reloads?? */
4233 : 6 : if (INSN_CODE (curr_insn) >= 0)
4234 : 0 : fatal_insn ("unable to generate reloads for:", curr_insn);
4235 : 6 : error_for_asm (curr_insn,
4236 : : "inconsistent operand constraints in an %<asm%>");
4237 : 6 : lra_asm_error_p = true;
4238 : 6 : if (! JUMP_P (curr_insn))
4239 : : {
4240 : : /* Avoid further trouble with this insn. Don't generate use
4241 : : pattern here as we could use the insn SP offset. */
4242 : 6 : lra_set_insn_deleted (curr_insn);
4243 : : }
4244 : : else
4245 : : {
4246 : 0 : lra_invalidate_insn_data (curr_insn);
4247 : 0 : ira_nullify_asm_goto (curr_insn);
4248 : 0 : lra_update_insn_regno_info (curr_insn);
4249 : : }
4250 : 6 : return true;
4251 : : }
4252 : :
4253 : : /* If the best alternative is with operands 1 and 2 swapped, swap
4254 : : them. Update the operand numbers of any reloads already
4255 : : pushed. */
4256 : :
4257 : 71749133 : if (goal_alt_swapped)
4258 : : {
4259 : 537311 : if (lra_dump_file != NULL)
4260 : 17 : fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n",
4261 : 17 : INSN_UID (curr_insn));
4262 : :
4263 : : /* Swap the duplicates too. */
4264 : 537311 : swap_operands (commutative);
4265 : 537311 : change_p = true;
4266 : : }
4267 : :
4268 : : /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
4269 : : too conservatively. So we use the secondary memory only if there
4270 : : is no any alternative without reloads. */
4271 : 71749133 : use_sec_mem_p = false;
4272 : 71749133 : if (! alt_p)
4273 : : use_sec_mem_p = true;
4274 : 71749133 : else if (sec_mem_p)
4275 : : {
4276 : 14845 : for (i = 0; i < n_operands; i++)
4277 : 14527 : if (! goal_alt_win[i] && ! goal_alt_match_win[i])
4278 : : break;
4279 : 13021 : use_sec_mem_p = i < n_operands;
4280 : : }
4281 : :
4282 : 13021 : if (use_sec_mem_p)
4283 : : {
4284 : 12703 : int in = -1, out = -1;
4285 : 12703 : rtx new_reg, src, dest, rld;
4286 : 12703 : machine_mode sec_mode, rld_mode;
4287 : :
4288 : 12703 : lra_assert (curr_insn_set != NULL_RTX && sec_mem_p);
4289 : 12703 : dest = SET_DEST (curr_insn_set);
4290 : 12703 : src = SET_SRC (curr_insn_set);
4291 : 38109 : for (i = 0; i < n_operands; i++)
4292 : 25406 : if (*curr_id->operand_loc[i] == dest)
4293 : : out = i;
4294 : 12703 : else if (*curr_id->operand_loc[i] == src)
4295 : 12703 : in = i;
4296 : 12703 : for (i = 0; i < curr_static_id->n_dups; i++)
4297 : 0 : if (out < 0 && *curr_id->dup_loc[i] == dest)
4298 : 0 : out = curr_static_id->dup_num[i];
4299 : 0 : else if (in < 0 && *curr_id->dup_loc[i] == src)
4300 : 0 : in = curr_static_id->dup_num[i];
4301 : 12703 : lra_assert (out >= 0 && in >= 0
4302 : : && curr_static_id->operand[out].type == OP_OUT
4303 : : && curr_static_id->operand[in].type == OP_IN);
4304 : 12703 : rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest;
4305 : 12703 : rld_mode = GET_MODE (rld);
4306 : 12703 : sec_mode = targetm.secondary_memory_needed_mode (rld_mode);
4307 : 12703 : new_reg = lra_create_new_reg (sec_mode, NULL_RTX, NO_REGS, NULL,
4308 : : "secondary");
4309 : : /* If the mode is changed, it should be wider. */
4310 : 12703 : lra_assert (!partial_subreg_p (sec_mode, rld_mode));
4311 : 12703 : if (sec_mode != rld_mode)
4312 : : {
4313 : : /* If the target says specifically to use another mode for
4314 : : secondary memory moves we cannot reuse the original
4315 : : insn. */
4316 : 8 : after = emit_spill_move (false, new_reg, dest);
4317 : 8 : lra_process_new_insns (curr_insn, NULL, after,
4318 : : "Inserting the sec. move");
4319 : : /* We may have non null BEFORE here (e.g. after address
4320 : : processing. */
4321 : 8 : push_to_sequence (before);
4322 : 8 : before = emit_spill_move (true, new_reg, src);
4323 : 8 : emit_insn (before);
4324 : 8 : before = get_insns ();
4325 : 8 : end_sequence ();
4326 : 8 : lra_process_new_insns (curr_insn, before, NULL, "Changing on");
4327 : 8 : lra_set_insn_deleted (curr_insn);
4328 : : }
4329 : 12695 : else if (dest == rld)
4330 : : {
4331 : 12695 : *curr_id->operand_loc[out] = new_reg;
4332 : 12695 : lra_update_dup (curr_id, out);
4333 : 12695 : after = emit_spill_move (false, new_reg, dest);
4334 : 12695 : lra_process_new_insns (curr_insn, NULL, after,
4335 : : "Inserting the sec. move");
4336 : : }
4337 : : else
4338 : : {
4339 : 0 : *curr_id->operand_loc[in] = new_reg;
4340 : 0 : lra_update_dup (curr_id, in);
4341 : : /* See comments above. */
4342 : 0 : push_to_sequence (before);
4343 : 0 : before = emit_spill_move (true, new_reg, src);
4344 : 0 : emit_insn (before);
4345 : 0 : before = get_insns ();
4346 : 0 : end_sequence ();
4347 : 0 : lra_process_new_insns (curr_insn, before, NULL,
4348 : : "Inserting the sec. move");
4349 : : }
4350 : 12703 : lra_update_insn_regno_info (curr_insn);
4351 : 12703 : return true;
4352 : : }
4353 : :
4354 : 71736430 : lra_assert (goal_alt_number >= 0);
4355 : 143423064 : lra_set_used_insn_alternative (curr_insn, goal_reuse_alt_p
4356 : : ? goal_alt_number : LRA_UNKNOWN_ALT);
4357 : :
4358 : 71736430 : if (lra_dump_file != NULL)
4359 : : {
4360 : 1232 : const char *p;
4361 : :
4362 : 1232 : fprintf (lra_dump_file, " Choosing alt %d in insn %u:",
4363 : 1232 : goal_alt_number, INSN_UID (curr_insn));
4364 : 1232 : print_curr_insn_alt (goal_alt_number);
4365 : 1232 : if (INSN_CODE (curr_insn) >= 0
4366 : 1232 : && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL)
4367 : 1225 : fprintf (lra_dump_file, " {%s}", p);
4368 : 1232 : if (maybe_ne (curr_id->sp_offset, 0))
4369 : : {
4370 : 0 : fprintf (lra_dump_file, " (sp_off=");
4371 : 0 : print_dec (curr_id->sp_offset, lra_dump_file);
4372 : 0 : fprintf (lra_dump_file, ")");
4373 : : }
4374 : 1232 : fprintf (lra_dump_file, "\n");
4375 : : }
4376 : :
4377 : : /* Right now, for any pair of operands I and J that are required to
4378 : : match, with J < I, goal_alt_matches[I] is J. Add I to
4379 : : goal_alt_matched[J]. */
4380 : :
4381 : 232233895 : for (i = 0; i < n_operands; i++)
4382 : 160497465 : if ((j = goal_alt_matches[i]) >= 0)
4383 : : {
4384 : 9842177 : for (k = 0; goal_alt_matched[j][k] >= 0; k++)
4385 : : ;
4386 : : /* We allow matching one output operand and several input
4387 : : operands. */
4388 : 9842176 : lra_assert (k == 0
4389 : : || (curr_static_id->operand[j].type == OP_OUT
4390 : : && curr_static_id->operand[i].type == OP_IN
4391 : : && (curr_static_id->operand
4392 : : [goal_alt_matched[j][0]].type == OP_IN)));
4393 : 9842176 : goal_alt_matched[j][k] = i;
4394 : 9842176 : goal_alt_matched[j][k + 1] = -1;
4395 : : }
4396 : :
4397 : 232233895 : for (i = 0; i < n_operands; i++)
4398 : 160497465 : goal_alt_win[i] |= goal_alt_match_win[i];
4399 : :
4400 : : /* Any constants that aren't allowed and can't be reloaded into
4401 : : registers are here changed into memory references. */
4402 : 232233895 : for (i = 0; i < n_operands; i++)
4403 : 160497465 : if (goal_alt_win[i])
4404 : : {
4405 : 155305456 : int regno;
4406 : 155305456 : enum reg_class new_class;
4407 : 155305456 : rtx reg = *curr_id->operand_loc[i];
4408 : :
4409 : 155305456 : if (GET_CODE (reg) == SUBREG)
4410 : 3343236 : reg = SUBREG_REG (reg);
4411 : :
4412 : 155305456 : if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
4413 : : {
4414 : 69703072 : bool ok_p = in_class_p (reg, goal_alt[i], &new_class, true);
4415 : :
4416 : 69703072 : if (new_class != NO_REGS && get_reg_class (regno) != new_class)
4417 : : {
4418 : 2802484 : lra_assert (ok_p);
4419 : 2802484 : lra_change_class (regno, new_class, " Change to", true);
4420 : : }
4421 : : }
4422 : : }
4423 : : else
4424 : : {
4425 : 5192009 : const char *constraint;
4426 : 5192009 : char c;
4427 : 5192009 : rtx op = *curr_id->operand_loc[i];
4428 : 5192009 : rtx subreg = NULL_RTX;
4429 : 5192009 : machine_mode mode = curr_operand_mode[i];
4430 : :
4431 : 5192009 : if (GET_CODE (op) == SUBREG)
4432 : : {
4433 : 219417 : subreg = op;
4434 : 219417 : op = SUBREG_REG (op);
4435 : 219417 : mode = GET_MODE (op);
4436 : : }
4437 : :
4438 : 5623303 : if (CONST_POOL_OK_P (mode, op)
4439 : 5407656 : && ((targetm.preferred_reload_class
4440 : 215647 : (op, (enum reg_class) goal_alt[i]) == NO_REGS)
4441 : 63322 : || no_input_reloads_p))
4442 : : {
4443 : 152325 : rtx tem = force_const_mem (mode, op);
4444 : :
4445 : 152325 : change_p = true;
4446 : 152325 : if (subreg != NULL_RTX)
4447 : 0 : tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg));
4448 : :
4449 : 152325 : *curr_id->operand_loc[i] = tem;
4450 : 152325 : lra_update_dup (curr_id, i);
4451 : 152325 : process_address (i, false, &before, &after);
4452 : :
4453 : : /* If the alternative accepts constant pool refs directly
4454 : : there will be no reload needed at all. */
4455 : 152325 : if (subreg != NULL_RTX)
4456 : 0 : continue;
4457 : : /* Skip alternatives before the one requested. */
4458 : 152325 : constraint = (curr_static_id->operand_alternative
4459 : 152325 : [goal_alt_number * n_operands + i].constraint);
4460 : 152325 : for (;
4461 : 261196 : (c = *constraint) && c != ',' && c != '#';
4462 : 108871 : constraint += CONSTRAINT_LEN (c, constraint))
4463 : : {
4464 : 209327 : enum constraint_num cn = lookup_constraint (constraint);
4465 : 209327 : if ((insn_extra_memory_constraint (cn)
4466 : 109328 : || insn_extra_special_memory_constraint (cn)
4467 : 108871 : || insn_extra_relaxed_memory_constraint (cn))
4468 : 209784 : && satisfies_memory_constraint_p (tem, cn))
4469 : : break;
4470 : : }
4471 : 152325 : if (c == '\0' || c == ',' || c == '#')
4472 : 51869 : continue;
4473 : :
4474 : 100456 : goal_alt_win[i] = true;
4475 : : }
4476 : : }
4477 : :
4478 : : n_outputs = 0;
4479 : 232233895 : for (i = 0; i < n_operands; i++)
4480 : 160497465 : if (curr_static_id->operand[i].type == OP_OUT)
4481 : 62229307 : outputs[n_outputs++] = i;
4482 : 71736430 : outputs[n_outputs] = -1;
4483 : 232233895 : for (i = 0; i < n_operands; i++)
4484 : : {
4485 : 160497465 : int regno;
4486 : 160497465 : bool optional_p = false;
4487 : 160497465 : rtx old, new_reg;
4488 : 160497465 : rtx op = *curr_id->operand_loc[i];
4489 : :
4490 : 160497465 : if (goal_alt_win[i])
4491 : : {
4492 : 155405912 : if (goal_alt[i] == NO_REGS
4493 : 38908789 : && REG_P (op)
4494 : 4669206 : && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4495 : : /* We assigned a hard register to the pseudo in the past but now
4496 : : decided to spill it for the insn. If the pseudo is used only
4497 : : in this insn, it is better to spill it here as we free hard
4498 : : registers for other pseudos referenced in the insn. The most
4499 : : common case of this is a scratch register which will be
4500 : : transformed to scratch back at the end of LRA. */
4501 : 157727277 : && bitmap_single_bit_set_p (&lra_reg_info[regno].insn_bitmap))
4502 : : {
4503 : 5665 : if (lra_get_allocno_class (regno) != NO_REGS)
4504 : 5308 : lra_change_class (regno, NO_REGS, " Change to", true);
4505 : 5665 : reg_renumber[regno] = -1;
4506 : : }
4507 : : /* We can do an optional reload. If the pseudo got a hard
4508 : : reg, we might improve the code through inheritance. If
4509 : : it does not get a hard register we coalesce memory/memory
4510 : : moves later. Ignore move insns to avoid cycling. */
4511 : 155405912 : if (! lra_simple_p
4512 : 154805243 : && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES
4513 : 143322081 : && goal_alt[i] != NO_REGS && REG_P (op)
4514 : 70490936 : && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER
4515 : 58838114 : && regno < new_regno_start
4516 : 54952917 : && ! ira_former_scratch_p (regno)
4517 : 54900093 : && reg_renumber[regno] < 0
4518 : : /* Check that the optional reload pseudo will be able to
4519 : : hold given mode value. */
4520 : 3185601 : && ! (prohibited_class_reg_set_mode_p
4521 : 3185601 : (goal_alt[i], reg_class_contents[goal_alt[i]],
4522 : 3185601 : PSEUDO_REGNO_MODE (regno)))
4523 : 158591503 : && (curr_insn_set == NULL_RTX
4524 : 3179626 : || !((REG_P (SET_SRC (curr_insn_set))
4525 : : || MEM_P (SET_SRC (curr_insn_set))
4526 : : || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
4527 : 2591046 : && (REG_P (SET_DEST (curr_insn_set))
4528 : : || MEM_P (SET_DEST (curr_insn_set))
4529 : : || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
4530 : : optional_p = true;
4531 : 154811333 : else if (goal_alt_matched[i][0] != -1
4532 : 8289485 : && curr_static_id->operand[i].type == OP_OUT
4533 : 8288361 : && (curr_static_id->operand_alternative
4534 : 8288361 : [goal_alt_number * n_operands + i].earlyclobber)
4535 : 19284 : && REG_P (op))
4536 : : {
4537 : 24495 : for (j = 0; goal_alt_matched[i][j] != -1; j++)
4538 : : {
4539 : 19231 : rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]];
4540 : :
4541 : 19231 : if (REG_P (op2) && REGNO (op) != REGNO (op2))
4542 : : break;
4543 : : }
4544 : 19231 : if (goal_alt_matched[i][j] != -1)
4545 : : {
4546 : : /* Generate reloads for different output and matched
4547 : : input registers. This is the easiest way to avoid
4548 : : creation of non-existing register conflicts in
4549 : : lra-lives.cc. */
4550 : 13967 : match_reload (i, goal_alt_matched[i], outputs, goal_alt[i],
4551 : : &goal_alt_exclude_start_hard_regs[i], &before,
4552 : : &after, true);
4553 : : }
4554 : 156273688 : continue;
4555 : 19231 : }
4556 : : else
4557 : : {
4558 : 154792102 : enum reg_class rclass, common_class;
4559 : :
4560 : 230253270 : if (REG_P (op) && goal_alt[i] != NO_REGS
4561 : 75461168 : && (regno = REGNO (op)) >= new_regno_start
4562 : 3894698 : && (rclass = get_reg_class (regno)) == ALL_REGS
4563 : 0 : && ((common_class = ira_reg_class_subset[rclass][goal_alt[i]])
4564 : : != NO_REGS)
4565 : 0 : && common_class != ALL_REGS
4566 : 154792102 : && enough_allocatable_hard_regs_p (common_class,
4567 : 0 : GET_MODE (op)))
4568 : : /* Refine reload pseudo class from chosen alternative
4569 : : constraint. */
4570 : 0 : lra_change_class (regno, common_class, " Change to", true);
4571 : 154792102 : continue;
4572 : 154792102 : }
4573 : : }
4574 : :
4575 : : /* Operands that match previous ones have already been handled. */
4576 : 5686132 : if (goal_alt_matches[i] >= 0)
4577 : 1462355 : continue;
4578 : :
4579 : : /* We should not have an operand with a non-offsettable address
4580 : : appearing where an offsettable address will do. It also may
4581 : : be a case when the address should be special in other words
4582 : : not a general one (e.g. it needs no index reg). */
4583 : 4223777 : if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op))
4584 : : {
4585 : 72 : enum reg_class rclass;
4586 : 72 : rtx *loc = &XEXP (op, 0);
4587 : 72 : enum rtx_code code = GET_CODE (*loc);
4588 : :
4589 : 72 : push_to_sequence (before);
4590 : 72 : rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op),
4591 : : MEM, SCRATCH, curr_insn);
4592 : 72 : if (GET_RTX_CLASS (code) == RTX_AUTOINC)
4593 : 0 : new_reg = emit_inc (rclass, *loc,
4594 : : /* This value does not matter for MODIFY. */
4595 : 0 : GET_MODE_SIZE (GET_MODE (op)));
4596 : 72 : else if (get_reload_reg (OP_IN, Pmode, *loc, rclass,
4597 : : NULL, false,
4598 : : "offsetable address", &new_reg))
4599 : : {
4600 : 72 : rtx addr = *loc;
4601 : 72 : enum rtx_code code = GET_CODE (addr);
4602 : 72 : bool align_p = false;
4603 : :
4604 : 72 : if (code == AND && CONST_INT_P (XEXP (addr, 1)))
4605 : : {
4606 : : /* (and ... (const_int -X)) is used to align to X bytes. */
4607 : 0 : align_p = true;
4608 : 0 : addr = XEXP (*loc, 0);
4609 : : }
4610 : : else
4611 : 72 : addr = canonicalize_reload_addr (addr);
4612 : :
4613 : 72 : lra_emit_move (new_reg, addr);
4614 : 72 : if (align_p)
4615 : 0 : emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1)));
4616 : : }
4617 : 72 : before = get_insns ();
4618 : 72 : end_sequence ();
4619 : 72 : *loc = new_reg;
4620 : 72 : lra_update_dup (curr_id, i);
4621 : 72 : }
4622 : 4223705 : else if (goal_alt_matched[i][0] == -1)
4623 : : {
4624 : 2671015 : machine_mode mode;
4625 : 2671015 : rtx reg, *loc;
4626 : 2671015 : int hard_regno;
4627 : 2671015 : enum op_type type = curr_static_id->operand[i].type;
4628 : :
4629 : 2671015 : loc = curr_id->operand_loc[i];
4630 : 2671015 : mode = curr_operand_mode[i];
4631 : 2671015 : if (GET_CODE (*loc) == SUBREG)
4632 : : {
4633 : 84104 : reg = SUBREG_REG (*loc);
4634 : 84104 : poly_int64 byte = SUBREG_BYTE (*loc);
4635 : 84104 : if (REG_P (reg)
4636 : : /* Strict_low_part requires reloading the register and not
4637 : : just the subreg. Likewise for a strict subreg no wider
4638 : : than a word for WORD_REGISTER_OPERATIONS targets. */
4639 : 84104 : && (curr_static_id->operand[i].strict_low
4640 : 83941 : || (!paradoxical_subreg_p (mode, GET_MODE (reg))
4641 : 81372 : && (hard_regno
4642 : 81372 : = get_try_hard_regno (REGNO (reg))) >= 0
4643 : 79932 : && (simplify_subreg_regno
4644 : 79932 : (hard_regno,
4645 : 79932 : GET_MODE (reg), byte, mode) < 0)
4646 : 0 : && (goal_alt[i] == NO_REGS
4647 : 0 : || (simplify_subreg_regno
4648 : 0 : (ira_class_hard_regs[goal_alt[i]][0],
4649 : 0 : GET_MODE (reg), byte, mode) >= 0)))
4650 : 83941 : || (partial_subreg_p (mode, GET_MODE (reg))
4651 : 180175 : && known_le (GET_MODE_SIZE (GET_MODE (reg)),
4652 : : UNITS_PER_WORD)
4653 : : && WORD_REGISTER_OPERATIONS))
4654 : : /* Avoid the situation when there are no available hard regs
4655 : : for the pseudo mode but there are ones for the subreg
4656 : : mode: */
4657 : 84267 : && !(goal_alt[i] != NO_REGS
4658 : 163 : && REGNO (reg) >= FIRST_PSEUDO_REGISTER
4659 : 163 : && (prohibited_class_reg_set_mode_p
4660 : 163 : (goal_alt[i], reg_class_contents[goal_alt[i]],
4661 : 163 : GET_MODE (reg)))
4662 : : && !(prohibited_class_reg_set_mode_p
4663 : 0 : (goal_alt[i], reg_class_contents[goal_alt[i]],
4664 : : mode))))
4665 : : {
4666 : : /* An OP_INOUT is required when reloading a subreg of a
4667 : : mode wider than a word to ensure that data beyond the
4668 : : word being reloaded is preserved. Also automatically
4669 : : ensure that strict_low_part reloads are made into
4670 : : OP_INOUT which should already be true from the backend
4671 : : constraints. */
4672 : 163 : if (type == OP_OUT
4673 : 163 : && (curr_static_id->operand[i].strict_low
4674 : 0 : || read_modify_subreg_p (*loc)))
4675 : : type = OP_INOUT;
4676 : 163 : loc = &SUBREG_REG (*loc);
4677 : 163 : mode = GET_MODE (*loc);
4678 : : }
4679 : : }
4680 : 2671015 : old = *loc;
4681 : 2671015 : if (get_reload_reg (type, mode, old, goal_alt[i],
4682 : : &goal_alt_exclude_start_hard_regs[i],
4683 : 2671015 : loc != curr_id->operand_loc[i], "", &new_reg)
4684 : 2671015 : && type != OP_OUT)
4685 : : {
4686 : 1798912 : push_to_sequence (before);
4687 : 1798912 : lra_emit_move (new_reg, old);
4688 : 1798912 : before = get_insns ();
4689 : 1798912 : end_sequence ();
4690 : : }
4691 : 2671015 : *loc = new_reg;
4692 : 2671015 : if (type != OP_IN
4693 : 2671015 : && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX)
4694 : : {
4695 : 857763 : start_sequence ();
4696 : 857763 : lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg);
4697 : 857763 : emit_insn (after);
4698 : 857763 : after = get_insns ();
4699 : 857763 : end_sequence ();
4700 : 857763 : *loc = new_reg;
4701 : : }
4702 : 2671015 : for (j = 0; j < goal_alt_dont_inherit_ops_num; j++)
4703 : 369 : if (goal_alt_dont_inherit_ops[j] == i)
4704 : : {
4705 : 369 : lra_set_regno_unique_value (REGNO (new_reg));
4706 : 369 : break;
4707 : : }
4708 : 2671015 : lra_update_dup (curr_id, i);
4709 : : }
4710 : 1552690 : else if (curr_static_id->operand[i].type == OP_IN
4711 : 1552690 : && (curr_static_id->operand[goal_alt_matched[i][0]].type
4712 : : == OP_OUT
4713 : 0 : || (curr_static_id->operand[goal_alt_matched[i][0]].type
4714 : : == OP_INOUT
4715 : 0 : && (operands_match_p
4716 : 0 : (*curr_id->operand_loc[i],
4717 : 0 : *curr_id->operand_loc[goal_alt_matched[i][0]],
4718 : : -1)))))
4719 : : {
4720 : : /* generate reloads for input and matched outputs. */
4721 : 16492 : match_inputs[0] = i;
4722 : 16492 : match_inputs[1] = -1;
4723 : 16492 : match_reload (goal_alt_matched[i][0], match_inputs, outputs,
4724 : : goal_alt[i], &goal_alt_exclude_start_hard_regs[i],
4725 : : &before, &after,
4726 : 16492 : curr_static_id->operand_alternative
4727 : 16492 : [goal_alt_number * n_operands + goal_alt_matched[i][0]]
4728 : 16492 : .earlyclobber);
4729 : : }
4730 : 1536198 : else if ((curr_static_id->operand[i].type == OP_OUT
4731 : 2 : || (curr_static_id->operand[i].type == OP_INOUT
4732 : 2 : && (operands_match_p
4733 : 2 : (*curr_id->operand_loc[i],
4734 : 2 : *curr_id->operand_loc[goal_alt_matched[i][0]],
4735 : : -1))))
4736 : 1536200 : && (curr_static_id->operand[goal_alt_matched[i][0]].type
4737 : : == OP_IN))
4738 : : /* Generate reloads for output and matched inputs. */
4739 : 1536198 : match_reload (i, goal_alt_matched[i], outputs, goal_alt[i],
4740 : : &goal_alt_exclude_start_hard_regs[i], &before, &after,
4741 : 1536198 : curr_static_id->operand_alternative
4742 : 1536198 : [goal_alt_number * n_operands + i].earlyclobber);
4743 : 0 : else if (curr_static_id->operand[i].type == OP_IN
4744 : 0 : && (curr_static_id->operand[goal_alt_matched[i][0]].type
4745 : : == OP_IN))
4746 : : {
4747 : : /* Generate reloads for matched inputs. */
4748 : 0 : match_inputs[0] = i;
4749 : 0 : for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++)
4750 : 0 : match_inputs[j + 1] = k;
4751 : 0 : match_inputs[j + 1] = -1;
4752 : 0 : match_reload (-1, match_inputs, outputs, goal_alt[i],
4753 : : &goal_alt_exclude_start_hard_regs[i],
4754 : : &before, &after, false);
4755 : : }
4756 : : else
4757 : : /* We must generate code in any case when function
4758 : : process_alt_operands decides that it is possible. */
4759 : 0 : gcc_unreachable ();
4760 : :
4761 : 4223777 : if (optional_p)
4762 : : {
4763 : 594579 : rtx reg = op;
4764 : :
4765 : 594579 : lra_assert (REG_P (reg));
4766 : 594579 : regno = REGNO (reg);
4767 : 594579 : op = *curr_id->operand_loc[i]; /* Substitution. */
4768 : 594579 : if (GET_CODE (op) == SUBREG)
4769 : 0 : op = SUBREG_REG (op);
4770 : 594579 : gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
4771 : 594579 : bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
4772 : 594579 : lra_reg_info[REGNO (op)].restore_rtx = reg;
4773 : 594579 : if (lra_dump_file != NULL)
4774 : 3 : fprintf (lra_dump_file,
4775 : : " Making reload reg %d for reg %d optional\n",
4776 : : REGNO (op), regno);
4777 : : }
4778 : : }
4779 : 68226087 : if (before != NULL_RTX || after != NULL_RTX
4780 : 139227614 : || max_regno_before != max_reg_num ())
4781 : 4259172 : change_p = true;
4782 : 71736430 : if (change_p)
4783 : : {
4784 : 4951880 : lra_update_operator_dups (curr_id);
4785 : : /* Something changes -- process the insn. */
4786 : 4951880 : lra_update_insn_regno_info (curr_insn);
4787 : 4951880 : if (asm_noperands (PATTERN (curr_insn)) >= 0
4788 : 4951880 : && ++curr_id->asm_reloads_num >= FIRST_PSEUDO_REGISTER)
4789 : : /* Most probably there are no enough registers to satisfy asm insn: */
4790 : 2 : lra_asm_insn_error (curr_insn);
4791 : : }
4792 : 71736430 : if (goal_alt_out_sp_reload_p)
4793 : : {
4794 : : /* We have an output stack pointer reload -- update sp offset: */
4795 : 0 : rtx set;
4796 : 0 : bool done_p = false;
4797 : 0 : poly_int64 sp_offset = curr_id->sp_offset;
4798 : 0 : for (rtx_insn *insn = after; insn != NULL_RTX; insn = NEXT_INSN (insn))
4799 : 0 : if ((set = single_set (insn)) != NULL_RTX
4800 : 0 : && SET_DEST (set) == stack_pointer_rtx)
4801 : : {
4802 : 0 : lra_assert (!done_p);
4803 : 0 : done_p = true;
4804 : 0 : curr_id->sp_offset = 0;
4805 : 0 : lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
4806 : 0 : id->sp_offset = sp_offset;
4807 : 0 : if (lra_dump_file != NULL)
4808 : 0 : fprintf (lra_dump_file,
4809 : : " Moving sp offset from insn %u to %u\n",
4810 : 0 : INSN_UID (curr_insn), INSN_UID (insn));
4811 : : }
4812 : 0 : lra_assert (done_p);
4813 : : }
4814 : 71736430 : lra_process_new_insns (curr_insn, before, after, "Inserting insn reload");
4815 : 71736430 : return change_p;
4816 : : }
4817 : :
4818 : : /* Return true if INSN satisfies all constraints. In other words, no
4819 : : reload insns are needed. */
4820 : : bool
4821 : 2413 : lra_constrain_insn (rtx_insn *insn)
4822 : : {
4823 : 2413 : int saved_new_regno_start = new_regno_start;
4824 : 2413 : int saved_new_insn_uid_start = new_insn_uid_start;
4825 : 2413 : bool change_p;
4826 : :
4827 : 2413 : curr_insn = insn;
4828 : 2413 : curr_id = lra_get_insn_recog_data (curr_insn);
4829 : 2413 : curr_static_id = curr_id->insn_static_data;
4830 : 2413 : new_insn_uid_start = get_max_uid ();
4831 : 2413 : new_regno_start = max_reg_num ();
4832 : 2413 : change_p = curr_insn_transform (true);
4833 : 2413 : new_regno_start = saved_new_regno_start;
4834 : 2413 : new_insn_uid_start = saved_new_insn_uid_start;
4835 : 2413 : return ! change_p;
4836 : : }
4837 : :
4838 : : /* Return true if X is in LIST. */
4839 : : static bool
4840 : 750685 : in_list_p (rtx x, rtx list)
4841 : : {
4842 : 1168887 : for (; list != NULL_RTX; list = XEXP (list, 1))
4843 : 691869 : if (XEXP (list, 0) == x)
4844 : : return true;
4845 : : return false;
4846 : : }
4847 : :
4848 : : /* Return true if X contains an allocatable hard register (if
4849 : : HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
4850 : : static bool
4851 : 4875553 : contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p)
4852 : : {
4853 : 4875553 : int i, j;
4854 : 4875553 : const char *fmt;
4855 : 4875553 : enum rtx_code code;
4856 : :
4857 : 4875553 : code = GET_CODE (x);
4858 : 4875553 : if (REG_P (x))
4859 : : {
4860 : 1065021 : int regno = REGNO (x);
4861 : 1065021 : HARD_REG_SET alloc_regs;
4862 : :
4863 : 1065021 : if (hard_reg_p)
4864 : : {
4865 : 334967 : if (regno >= FIRST_PSEUDO_REGISTER)
4866 : 125107 : regno = lra_get_regno_hard_regno (regno);
4867 : 334967 : if (regno < 0)
4868 : : return false;
4869 : 334967 : alloc_regs = ~lra_no_alloc_regs;
4870 : 334967 : return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno);
4871 : : }
4872 : : else
4873 : : {
4874 : 730054 : if (regno < FIRST_PSEUDO_REGISTER)
4875 : : return false;
4876 : 295966 : if (! spilled_p)
4877 : : return true;
4878 : 158037 : return lra_get_regno_hard_regno (regno) < 0;
4879 : : }
4880 : : }
4881 : 3810532 : fmt = GET_RTX_FORMAT (code);
4882 : 9889799 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4883 : : {
4884 : 6594673 : if (fmt[i] == 'e')
4885 : : {
4886 : 3097213 : if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p))
4887 : : return true;
4888 : : }
4889 : 3497460 : else if (fmt[i] == 'E')
4890 : : {
4891 : 214178 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4892 : 171529 : if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p))
4893 : : return true;
4894 : : }
4895 : : }
4896 : : return false;
4897 : : }
4898 : :
4899 : : /* Process all regs in location *LOC and change them on equivalent
4900 : : substitution. Return true if any change was done. */
4901 : : static bool
4902 : 2906 : loc_equivalence_change_p (rtx *loc)
4903 : : {
4904 : 2906 : rtx subst, reg, x = *loc;
4905 : 2906 : bool result = false;
4906 : 2906 : enum rtx_code code = GET_CODE (x);
4907 : 2906 : const char *fmt;
4908 : 2906 : int i, j;
4909 : :
4910 : 2906 : if (code == SUBREG)
4911 : : {
4912 : 10 : reg = SUBREG_REG (x);
4913 : 10 : if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg
4914 : 10 : && GET_MODE (subst) == VOIDmode)
4915 : : {
4916 : : /* We cannot reload debug location. Simplify subreg here
4917 : : while we know the inner mode. */
4918 : 0 : *loc = simplify_gen_subreg (GET_MODE (x), subst,
4919 : 0 : GET_MODE (reg), SUBREG_BYTE (x));
4920 : 0 : return true;
4921 : : }
4922 : : }
4923 : 2906 : if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x)
4924 : : {
4925 : 5 : *loc = subst;
4926 : 5 : return true;
4927 : : }
4928 : :
4929 : : /* Scan all the operand sub-expressions. */
4930 : 2901 : fmt = GET_RTX_FORMAT (code);
4931 : 7037 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4932 : : {
4933 : 4136 : if (fmt[i] == 'e')
4934 : 2274 : result = loc_equivalence_change_p (&XEXP (x, i)) || result;
4935 : 1862 : else if (fmt[i] == 'E')
4936 : 135 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4937 : 100 : result
4938 : 110 : = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result;
4939 : : }
4940 : : return result;
4941 : : }
4942 : :
4943 : : /* Similar to loc_equivalence_change_p, but for use as
4944 : : simplify_replace_fn_rtx callback. DATA is insn for which the
4945 : : elimination is done. If it null we don't do the elimination. */
4946 : : static rtx
4947 : 38046418 : loc_equivalence_callback (rtx loc, const_rtx, void *data)
4948 : : {
4949 : 38046418 : if (!REG_P (loc))
4950 : : return NULL_RTX;
4951 : :
4952 : 9795663 : rtx subst = (data == NULL
4953 : 9795663 : ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data));
4954 : 9795663 : if (subst != loc)
4955 : : return subst;
4956 : :
4957 : : return NULL_RTX;
4958 : : }
4959 : :
4960 : : /* Maximum number of generated reload insns per an insn. It is for
4961 : : preventing this pass cycling in a bug case. */
4962 : : #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
4963 : :
4964 : : /* The current iteration number of this LRA pass. */
4965 : : int lra_constraint_iter;
4966 : :
4967 : : /* True if we should during assignment sub-pass check assignment
4968 : : correctness for all pseudos and spill some of them to correct
4969 : : conflicts. It can be necessary when we substitute equiv which
4970 : : needs checking register allocation correctness because the
4971 : : equivalent value contains allocatable hard registers, or when we
4972 : : restore multi-register pseudo, or when we change the insn code and
4973 : : its operand became INOUT operand when it was IN one before. */
4974 : : bool check_and_force_assignment_correctness_p;
4975 : :
4976 : : /* Return true if REGNO is referenced in more than one block. */
4977 : : static bool
4978 : 133004 : multi_block_pseudo_p (int regno)
4979 : : {
4980 : 133004 : basic_block bb = NULL;
4981 : 133004 : unsigned int uid;
4982 : 133004 : bitmap_iterator bi;
4983 : :
4984 : 133004 : if (regno < FIRST_PSEUDO_REGISTER)
4985 : : return false;
4986 : :
4987 : 405423 : EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
4988 : 276562 : if (bb == NULL)
4989 : 133004 : bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn);
4990 : 143558 : else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb)
4991 : : return true;
4992 : : return false;
4993 : : }
4994 : :
4995 : : /* Return true if LIST contains a deleted insn. */
4996 : : static bool
4997 : 535639 : contains_deleted_insn_p (rtx_insn_list *list)
4998 : : {
4999 : 1020954 : for (; list != NULL_RTX; list = list->next ())
5000 : 485315 : if (NOTE_P (list->insn ())
5001 : 485315 : && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED)
5002 : : return true;
5003 : : return false;
5004 : : }
5005 : :
5006 : : /* Return true if X contains a pseudo dying in INSN. */
5007 : : static bool
5008 : 1562014 : dead_pseudo_p (rtx x, rtx_insn *insn)
5009 : : {
5010 : 1562014 : int i, j;
5011 : 1562014 : const char *fmt;
5012 : 1562014 : enum rtx_code code;
5013 : :
5014 : 1562014 : if (REG_P (x))
5015 : 361345 : return (insn != NULL_RTX
5016 : 361345 : && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX);
5017 : 1200669 : code = GET_CODE (x);
5018 : 1200669 : fmt = GET_RTX_FORMAT (code);
5019 : 3206384 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5020 : : {
5021 : 2012210 : if (fmt[i] == 'e')
5022 : : {
5023 : 1055765 : if (dead_pseudo_p (XEXP (x, i), insn))
5024 : : return true;
5025 : : }
5026 : 956445 : else if (fmt[i] == 'E')
5027 : : {
5028 : 31129 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5029 : 22666 : if (dead_pseudo_p (XVECEXP (x, i, j), insn))
5030 : : return true;
5031 : : }
5032 : : }
5033 : : return false;
5034 : : }
5035 : :
5036 : : /* Return true if INSN contains a dying pseudo in INSN right hand
5037 : : side. */
5038 : : static bool
5039 : 483583 : insn_rhs_dead_pseudo_p (rtx_insn *insn)
5040 : : {
5041 : 483583 : rtx set = single_set (insn);
5042 : :
5043 : 483583 : gcc_assert (set != NULL);
5044 : 483583 : return dead_pseudo_p (SET_SRC (set), insn);
5045 : : }
5046 : :
5047 : : /* Return true if any init insn of REGNO contains a dying pseudo in
5048 : : insn right hand side. */
5049 : : static bool
5050 : 533908 : init_insn_rhs_dead_pseudo_p (int regno)
5051 : : {
5052 : 533908 : rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
5053 : :
5054 : 533908 : if (insns == NULL)
5055 : : return false;
5056 : 960787 : for (; insns != NULL_RTX; insns = insns->next ())
5057 : 483583 : if (insn_rhs_dead_pseudo_p (insns->insn ()))
5058 : : return true;
5059 : : return false;
5060 : : }
5061 : :
5062 : : /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
5063 : : reverse only if we have one init insn with given REGNO as a
5064 : : source. */
5065 : : static bool
5066 : 535639 : reverse_equiv_p (int regno)
5067 : : {
5068 : 535639 : rtx_insn_list *insns = ira_reg_equiv[regno].init_insns;
5069 : 535639 : rtx set;
5070 : :
5071 : 535639 : if (insns == NULL)
5072 : : return false;
5073 : 485314 : if (! INSN_P (insns->insn ())
5074 : 970628 : || insns->next () != NULL)
5075 : : return false;
5076 : 485313 : if ((set = single_set (insns->insn ())) == NULL_RTX)
5077 : : return false;
5078 : 485313 : return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno;
5079 : : }
5080 : :
5081 : : /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
5082 : : call this function only for non-reverse equivalence. */
5083 : : static bool
5084 : 527529 : contains_reloaded_insn_p (int regno)
5085 : : {
5086 : 527529 : rtx set;
5087 : 527529 : rtx_insn_list *list = ira_reg_equiv[regno].init_insns;
5088 : :
5089 : 1004726 : for (; list != NULL; list = list->next ())
5090 : 477204 : if ((set = single_set (list->insn ())) == NULL_RTX
5091 : 477204 : || ! REG_P (SET_DEST (set))
5092 : 954408 : || (int) REGNO (SET_DEST (set)) != regno)
5093 : : return true;
5094 : : return false;
5095 : : }
5096 : :
5097 : : /* Try combine secondary memory reload insn FROM for insn TO into TO insn.
5098 : : FROM should be a load insn (usually a secondary memory reload insn). Return
5099 : : TRUE in case of success. */
5100 : : static bool
5101 : 6235932 : combine_reload_insn (rtx_insn *from, rtx_insn *to)
5102 : : {
5103 : 6235932 : bool ok_p;
5104 : 6235932 : rtx_insn *saved_insn;
5105 : 6235932 : rtx set, from_reg, to_reg, op;
5106 : 6235932 : enum reg_class to_class, from_class;
5107 : 6235932 : int n, nop;
5108 : 6235932 : signed char changed_nops[MAX_RECOG_OPERANDS + 1];
5109 : :
5110 : : /* Check conditions for second memory reload and original insn: */
5111 : 6235932 : if ((targetm.secondary_memory_needed
5112 : : == hook_bool_mode_reg_class_t_reg_class_t_false)
5113 : 6235932 : || NEXT_INSN (from) != to
5114 : 3512700 : || !NONDEBUG_INSN_P (to)
5115 : 9748632 : || CALL_P (to))
5116 : : return false;
5117 : :
5118 : 3508071 : lra_insn_recog_data_t id = lra_get_insn_recog_data (to);
5119 : 3508071 : struct lra_static_insn_data *static_id = id->insn_static_data;
5120 : :
5121 : 3508071 : if (id->used_insn_alternative == LRA_UNKNOWN_ALT
5122 : 3508071 : || (set = single_set (from)) == NULL_RTX)
5123 : 28789 : return false;
5124 : 3479282 : from_reg = SET_DEST (set);
5125 : 3479282 : to_reg = SET_SRC (set);
5126 : : /* Ignore optional reloads: */
5127 : 3403728 : if (! REG_P (from_reg) || ! REG_P (to_reg)
5128 : 6037352 : || bitmap_bit_p (&lra_optional_reload_pseudos, REGNO (from_reg)))
5129 : 1433976 : return false;
5130 : 2045306 : to_class = lra_get_allocno_class (REGNO (to_reg));
5131 : 2045306 : from_class = lra_get_allocno_class (REGNO (from_reg));
5132 : : /* Check that reload insn is a load: */
5133 : 2045306 : if (to_class != NO_REGS || from_class == NO_REGS)
5134 : : return false;
5135 : 38697 : for (n = nop = 0; nop < static_id->n_operands; nop++)
5136 : : {
5137 : 27316 : if (static_id->operand[nop].type != OP_IN)
5138 : 10230 : continue;
5139 : 17086 : op = *id->operand_loc[nop];
5140 : 17086 : if (!REG_P (op) || REGNO (op) != REGNO (from_reg))
5141 : 5938 : continue;
5142 : 11148 : *id->operand_loc[nop] = to_reg;
5143 : 11148 : changed_nops[n++] = nop;
5144 : : }
5145 : 11381 : changed_nops[n] = -1;
5146 : 11381 : lra_update_dups (id, changed_nops);
5147 : 11381 : lra_update_insn_regno_info (to);
5148 : 11381 : ok_p = recog_memoized (to) >= 0;
5149 : 11381 : if (ok_p)
5150 : : {
5151 : : /* Check that combined insn does not need any reloads: */
5152 : 11358 : saved_insn = curr_insn;
5153 : 11358 : curr_insn = to;
5154 : 11358 : curr_id = lra_get_insn_recog_data (curr_insn);
5155 : 11358 : curr_static_id = curr_id->insn_static_data;
5156 : 11358 : for (bool swapped_p = false;;)
5157 : : {
5158 : 13220 : ok_p = !curr_insn_transform (true);
5159 : 13220 : if (ok_p || curr_static_id->commutative < 0)
5160 : : break;
5161 : 3723 : swap_operands (curr_static_id->commutative);
5162 : 3723 : if (lra_dump_file != NULL)
5163 : : {
5164 : 0 : fprintf (lra_dump_file,
5165 : : " Swapping %scombined insn operands:\n",
5166 : : swapped_p ? "back " : "");
5167 : 0 : dump_insn_slim (lra_dump_file, to);
5168 : : }
5169 : 3723 : if (swapped_p)
5170 : : break;
5171 : : swapped_p = true;
5172 : : }
5173 : 11358 : curr_insn = saved_insn;
5174 : 11358 : curr_id = lra_get_insn_recog_data (curr_insn);
5175 : 11358 : curr_static_id = curr_id->insn_static_data;
5176 : : }
5177 : 11381 : if (ok_p)
5178 : : {
5179 : 2579 : id->used_insn_alternative = -1;
5180 : 2579 : lra_push_insn_and_update_insn_regno_info (to);
5181 : 2579 : if (lra_dump_file != NULL)
5182 : : {
5183 : 0 : fprintf (lra_dump_file, " Use combined insn:\n");
5184 : 0 : dump_insn_slim (lra_dump_file, to);
5185 : : }
5186 : 2579 : return true;
5187 : : }
5188 : 8802 : if (lra_dump_file != NULL)
5189 : : {
5190 : 0 : fprintf (lra_dump_file, " Failed combined insn:\n");
5191 : 0 : dump_insn_slim (lra_dump_file, to);
5192 : : }
5193 : 17875 : for (int i = 0; i < n; i++)
5194 : : {
5195 : 9073 : nop = changed_nops[i];
5196 : 9073 : *id->operand_loc[nop] = from_reg;
5197 : : }
5198 : 8802 : lra_update_dups (id, changed_nops);
5199 : 8802 : lra_update_insn_regno_info (to);
5200 : 8802 : if (lra_dump_file != NULL)
5201 : : {
5202 : 0 : fprintf (lra_dump_file, " Restoring insn after failed combining:\n");
5203 : 0 : dump_insn_slim (lra_dump_file, to);
5204 : : }
5205 : : return false;
5206 : : }
5207 : :
5208 : : /* Entry function of LRA constraint pass. Return true if the
5209 : : constraint pass did change the code. */
5210 : : bool
5211 : 3054948 : lra_constraints (bool first_p)
5212 : : {
5213 : 3054948 : bool changed_p;
5214 : 3054948 : int i, hard_regno, new_insns_num;
5215 : 3054948 : unsigned int min_len, new_min_len, uid;
5216 : 3054948 : rtx set, x, reg, nosubreg_dest;
5217 : 3054948 : rtx_insn *original_insn;
5218 : 3054948 : basic_block last_bb;
5219 : 3054948 : bitmap_iterator bi;
5220 : :
5221 : 3054948 : lra_constraint_iter++;
5222 : 3054948 : if (lra_dump_file != NULL)
5223 : 210 : fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n",
5224 : : lra_constraint_iter);
5225 : 3054948 : changed_p = false;
5226 : 3054948 : if (pic_offset_table_rtx
5227 : 3054948 : && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER)
5228 : 98853 : check_and_force_assignment_correctness_p = true;
5229 : 2956095 : else if (first_p)
5230 : : /* On the first iteration we should check IRA assignment
5231 : : correctness. In rare cases, the assignments can be wrong as
5232 : : early clobbers operands are ignored in IRA or usages of
5233 : : paradoxical sub-registers are not taken into account by
5234 : : IRA. */
5235 : 1387426 : check_and_force_assignment_correctness_p = true;
5236 : 3054948 : new_insn_uid_start = get_max_uid ();
5237 : 3054948 : new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num ();
5238 : : /* Mark used hard regs for target stack size calulations. */
5239 : 187520498 : for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
5240 : 184465550 : if (lra_reg_info[i].nrefs != 0
5241 : 184465550 : && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
5242 : : {
5243 : 89128164 : int j, nregs;
5244 : :
5245 : 89128164 : nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode);
5246 : 181240444 : for (j = 0; j < nregs; j++)
5247 : 92112280 : df_set_regs_ever_live (hard_regno + j, true);
5248 : : }
5249 : : /* Do elimination before the equivalence processing as we can spill
5250 : : some pseudos during elimination. */
5251 : 3054948 : lra_eliminate (false, first_p);
5252 : 3054948 : auto_bitmap equiv_insn_bitmap (®_obstack);
5253 : 187520498 : for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
5254 : 184465550 : if (lra_reg_info[i].nrefs != 0)
5255 : : {
5256 : 92255045 : ira_reg_equiv[i].profitable_p = true;
5257 : 92255045 : reg = regno_reg_rtx[i];
5258 : 92255045 : if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg)
5259 : : {
5260 : 544707 : bool pseudo_p = contains_reg_p (x, false, false);
5261 : :
5262 : : /* After RTL transformation, we cannot guarantee that
5263 : : pseudo in the substitution was not reloaded which might
5264 : : make equivalence invalid. For example, in reverse
5265 : : equiv of p0
5266 : :
5267 : : p0 <- ...
5268 : : ...
5269 : : equiv_mem <- p0
5270 : :
5271 : : the memory address register was reloaded before the 2nd
5272 : : insn. */
5273 : 544707 : if ((! first_p && pseudo_p)
5274 : : /* We don't use DF for compilation speed sake. So it
5275 : : is problematic to update live info when we use an
5276 : : equivalence containing pseudos in more than one
5277 : : BB. */
5278 : 539782 : || (pseudo_p && multi_block_pseudo_p (i))
5279 : : /* If an init insn was deleted for some reason, cancel
5280 : : the equiv. We could update the equiv insns after
5281 : : transformations including an equiv insn deletion
5282 : : but it is not worthy as such cases are extremely
5283 : : rare. */
5284 : 535639 : || contains_deleted_insn_p (ira_reg_equiv[i].init_insns)
5285 : : /* If it is not a reverse equivalence, we check that a
5286 : : pseudo in rhs of the init insn is not dying in the
5287 : : insn. Otherwise, the live info at the beginning of
5288 : : the corresponding BB might be wrong after we
5289 : : removed the insn. When the equiv can be a
5290 : : constant, the right hand side of the init insn can
5291 : : be a pseudo. */
5292 : 535639 : || (! reverse_equiv_p (i)
5293 : 533908 : && (init_insn_rhs_dead_pseudo_p (i)
5294 : : /* If we reloaded the pseudo in an equivalence
5295 : : init insn, we cannot remove the equiv init
5296 : : insns and the init insns might write into
5297 : : const memory in this case. */
5298 : 527529 : || contains_reloaded_insn_p (i)))
5299 : : /* Prevent access beyond equivalent memory for
5300 : : paradoxical subregs. */
5301 : 529253 : || (MEM_P (x)
5302 : 999966 : && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode),
5303 : : GET_MODE_SIZE (GET_MODE (x))))
5304 : 1073842 : || (pic_offset_table_rtx
5305 : 563482 : && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x)
5306 : 1797 : && (targetm.preferred_reload_class
5307 : 1797 : (x, lra_get_allocno_class (i)) == NO_REGS))
5308 : 33667 : || contains_symbol_ref_p (x))))
5309 : 17458 : ira_reg_equiv[i].defined_p
5310 : 17458 : = ira_reg_equiv[i].caller_save_p = false;
5311 : 544707 : if (contains_reg_p (x, false, true))
5312 : 7653 : ira_reg_equiv[i].profitable_p = false;
5313 : 544707 : if (get_equiv (reg) != reg)
5314 : 523535 : bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap);
5315 : : }
5316 : : }
5317 : 187520498 : for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
5318 : 184465550 : update_equiv (i);
5319 : : /* We should add all insns containing pseudos which should be
5320 : : substituted by their equivalences. */
5321 : 4566203 : EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi)
5322 : 1511255 : lra_push_insn_by_uid (uid);
5323 : 3054948 : min_len = lra_insn_stack_length ();
5324 : 3054948 : new_insns_num = 0;
5325 : 3054948 : last_bb = NULL;
5326 : 3054948 : changed_p = false;
5327 : 3054948 : original_insn = NULL;
5328 : 146487601 : while ((new_min_len = lra_insn_stack_length ()) != 0)
5329 : : {
5330 : 140377705 : curr_insn = lra_pop_insn ();
5331 : 140377705 : --new_min_len;
5332 : 140377705 : curr_bb = BLOCK_FOR_INSN (curr_insn);
5333 : 140377705 : if (curr_bb != last_bb)
5334 : : {
5335 : 18025479 : last_bb = curr_bb;
5336 : 18025479 : bb_reload_num = lra_curr_reload_num;
5337 : : }
5338 : 140377705 : if (min_len > new_min_len)
5339 : : {
5340 : : min_len = new_min_len;
5341 : : new_insns_num = 0;
5342 : : original_insn = curr_insn;
5343 : : }
5344 : 6235932 : else if (combine_reload_insn (curr_insn, original_insn))
5345 : : {
5346 : 2579 : continue;
5347 : : }
5348 : 140375126 : if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
5349 : 0 : internal_error
5350 : 0 : ("maximum number of generated reload insns per insn achieved (%d)",
5351 : : MAX_RELOAD_INSNS_NUMBER);
5352 : 140375126 : new_insns_num++;
5353 : 140375126 : if (DEBUG_INSN_P (curr_insn))
5354 : : {
5355 : : /* We need to check equivalence in debug insn and change
5356 : : pseudo to the equivalent value if necessary. */
5357 : 40801088 : curr_id = lra_get_insn_recog_data (curr_insn);
5358 : 40801088 : if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)))
5359 : : {
5360 : 29648 : rtx old = *curr_id->operand_loc[0];
5361 : 29648 : *curr_id->operand_loc[0]
5362 : 29648 : = simplify_replace_fn_rtx (old, NULL_RTX,
5363 : : loc_equivalence_callback, curr_insn);
5364 : 29648 : if (old != *curr_id->operand_loc[0])
5365 : : {
5366 : : /* If we substitute pseudo by shared equivalence, we can fail
5367 : : to update LRA reg info and this can result in many
5368 : : unexpected consequences. So keep rtl unshared: */
5369 : 29648 : *curr_id->operand_loc[0]
5370 : 29648 : = copy_rtx (*curr_id->operand_loc[0]);
5371 : 29648 : lra_update_insn_regno_info (curr_insn);
5372 : 29648 : changed_p = true;
5373 : : }
5374 : : }
5375 : : }
5376 : 99574038 : else if (INSN_P (curr_insn))
5377 : : {
5378 : 98573545 : if ((set = single_set (curr_insn)) != NULL_RTX)
5379 : : {
5380 : 93335060 : nosubreg_dest = SET_DEST (set);
5381 : : /* The equivalence pseudo could be set up as SUBREG in a
5382 : : case when it is a call restore insn in a mode
5383 : : different from the pseudo mode. */
5384 : 93335060 : if (GET_CODE (nosubreg_dest) == SUBREG)
5385 : 1209170 : nosubreg_dest = SUBREG_REG (nosubreg_dest);
5386 : 93852457 : if ((REG_P (nosubreg_dest)
5387 : 69450929 : && (x = get_equiv (nosubreg_dest)) != nosubreg_dest
5388 : : /* Remove insns which set up a pseudo whose value
5389 : : cannot be changed. Such insns might be not in
5390 : : init_insns because we don't update equiv data
5391 : : during insn transformations.
5392 : :
5393 : : As an example, let suppose that a pseudo got
5394 : : hard register and on the 1st pass was not
5395 : : changed to equivalent constant. We generate an
5396 : : additional insn setting up the pseudo because of
5397 : : secondary memory movement. Then the pseudo is
5398 : : spilled and we use the equiv constant. In this
5399 : : case we should remove the additional insn and
5400 : : this insn is not init_insns list. */
5401 : 527252 : && (! MEM_P (x) || MEM_READONLY_P (x)
5402 : : /* Check that this is actually an insn setting
5403 : : up the equivalence. */
5404 : 283522 : || in_list_p (curr_insn,
5405 : 283522 : ira_reg_equiv
5406 : 283522 : [REGNO (nosubreg_dest)].init_insns)))
5407 : 162270260 : || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set))
5408 : 467163 : && in_list_p (curr_insn,
5409 : 467163 : ira_reg_equiv
5410 : 467163 : [REGNO (SET_SRC (set))].init_insns)
5411 : : /* This is a reverse equivalence to memory (see ira.cc)
5412 : : in store insn. We can reload all the destination and
5413 : : have an output reload which is a store to memory. If
5414 : : we just remove the insn, we will have the output
5415 : : reload storing an undefined value to the memory.
5416 : : Check that we did not reload the memory to prevent a
5417 : : wrong code generation. We could implement using the
5418 : : equivalence still in such case but doing this is not
5419 : : worth the efforts as such case is very rare. */
5420 : 1668 : && MEM_P (nosubreg_dest)))
5421 : : {
5422 : : /* This is equiv init insn of pseudo which did not get a
5423 : : hard register -- remove the insn. */
5424 : 517397 : if (lra_dump_file != NULL)
5425 : : {
5426 : 6 : fprintf (lra_dump_file,
5427 : : " Removing equiv init insn %i (freq=%d)\n",
5428 : 3 : INSN_UID (curr_insn),
5429 : 6 : REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn)));
5430 : 3 : dump_insn_slim (lra_dump_file, curr_insn);
5431 : : }
5432 : 517397 : if (contains_reg_p (x, true, false))
5433 : 125107 : check_and_force_assignment_correctness_p = true;
5434 : 517397 : lra_set_insn_deleted (curr_insn);
5435 : 517397 : continue;
5436 : : }
5437 : : }
5438 : 98056148 : curr_id = lra_get_insn_recog_data (curr_insn);
5439 : 98056148 : curr_static_id = curr_id->insn_static_data;
5440 : 98056148 : init_curr_insn_input_reloads ();
5441 : 98056148 : init_curr_operand_mode ();
5442 : 98056148 : if (curr_insn_transform (false))
5443 : : changed_p = true;
5444 : : /* Check non-transformed insns too for equiv change as USE
5445 : : or CLOBBER don't need reloads but can contain pseudos
5446 : : being changed on their equivalences. */
5447 : 93091559 : else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))
5448 : 93091559 : && loc_equivalence_change_p (&PATTERN (curr_insn)))
5449 : : {
5450 : 5 : lra_update_insn_regno_info (curr_insn);
5451 : 5 : changed_p = true;
5452 : : }
5453 : : }
5454 : : }
5455 : :
5456 : : /* If we used a new hard regno, changed_p should be true because the
5457 : : hard reg is assigned to a new pseudo. */
5458 : 3054948 : if (flag_checking && !changed_p)
5459 : : {
5460 : 120832441 : for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++)
5461 : 118321800 : if (lra_reg_info[i].nrefs != 0
5462 : 118321800 : && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
5463 : : {
5464 : 56219550 : int j, nregs = hard_regno_nregs (hard_regno,
5465 : 56219550 : PSEUDO_REGNO_MODE (i));
5466 : :
5467 : 114417128 : for (j = 0; j < nregs; j++)
5468 : 58197578 : lra_assert (df_regs_ever_live_p (hard_regno + j));
5469 : : }
5470 : : }
5471 : 2510689 : if (changed_p)
5472 : 544262 : lra_dump_insns_if_possible ("changed func after local");
5473 : 6109896 : return changed_p;
5474 : 3054948 : }
5475 : :
5476 : : static void initiate_invariants (void);
5477 : : static void finish_invariants (void);
5478 : :
5479 : : /* Initiate the LRA constraint pass. It is done once per
5480 : : function. */
5481 : : void
5482 : 1426764 : lra_constraints_init (void)
5483 : : {
5484 : 1426764 : initiate_invariants ();
5485 : 1426764 : }
5486 : :
5487 : : /* Finalize the LRA constraint pass. It is done once per
5488 : : function. */
5489 : : void
5490 : 1426764 : lra_constraints_finish (void)
5491 : : {
5492 : 1426764 : finish_invariants ();
5493 : 1426764 : }
5494 : :
5495 : :
5496 : :
5497 : : /* Structure describes invariants for ineheritance. */
5498 : : struct lra_invariant
5499 : : {
5500 : : /* The order number of the invariant. */
5501 : : int num;
5502 : : /* The invariant RTX. */
5503 : : rtx invariant_rtx;
5504 : : /* The origin insn of the invariant. */
5505 : : rtx_insn *insn;
5506 : : };
5507 : :
5508 : : typedef lra_invariant invariant_t;
5509 : : typedef invariant_t *invariant_ptr_t;
5510 : : typedef const invariant_t *const_invariant_ptr_t;
5511 : :
5512 : : /* Pointer to the inheritance invariants. */
5513 : : static vec<invariant_ptr_t> invariants;
5514 : :
5515 : : /* Allocation pool for the invariants. */
5516 : : static object_allocator<lra_invariant> *invariants_pool;
5517 : :
5518 : : /* Hash table for the invariants. */
5519 : : static htab_t invariant_table;
5520 : :
5521 : : /* Hash function for INVARIANT. */
5522 : : static hashval_t
5523 : 141568 : invariant_hash (const void *invariant)
5524 : : {
5525 : 141568 : rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx;
5526 : 141568 : return lra_rtx_hash (inv);
5527 : : }
5528 : :
5529 : : /* Equal function for invariants INVARIANT1 and INVARIANT2. */
5530 : : static int
5531 : 35368 : invariant_eq_p (const void *invariant1, const void *invariant2)
5532 : : {
5533 : 35368 : rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx;
5534 : 35368 : rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx;
5535 : :
5536 : 35368 : return rtx_equal_p (inv1, inv2);
5537 : : }
5538 : :
5539 : : /* Insert INVARIANT_RTX into the table if it is not there yet. Return
5540 : : invariant which is in the table. */
5541 : : static invariant_ptr_t
5542 : 141376 : insert_invariant (rtx invariant_rtx)
5543 : : {
5544 : 141376 : void **entry_ptr;
5545 : 141376 : invariant_t invariant;
5546 : 141376 : invariant_ptr_t invariant_ptr;
5547 : :
5548 : 141376 : invariant.invariant_rtx = invariant_rtx;
5549 : 141376 : entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT);
5550 : 141376 : if (*entry_ptr == NULL)
5551 : : {
5552 : 125233 : invariant_ptr = invariants_pool->allocate ();
5553 : 125233 : invariant_ptr->invariant_rtx = invariant_rtx;
5554 : 125233 : invariant_ptr->insn = NULL;
5555 : 125233 : invariants.safe_push (invariant_ptr);
5556 : 125233 : *entry_ptr = (void *) invariant_ptr;
5557 : : }
5558 : 141376 : return (invariant_ptr_t) *entry_ptr;
5559 : : }
5560 : :
5561 : : /* Initiate the invariant table. */
5562 : : static void
5563 : 1426764 : initiate_invariants (void)
5564 : : {
5565 : 1426764 : invariants.create (100);
5566 : 1426764 : invariants_pool
5567 : 1426764 : = new object_allocator<lra_invariant> ("Inheritance invariants");
5568 : 1426764 : invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL);
5569 : 1426764 : }
5570 : :
5571 : : /* Finish the invariant table. */
5572 : : static void
5573 : 1426764 : finish_invariants (void)
5574 : : {
5575 : 1426764 : htab_delete (invariant_table);
5576 : 2853528 : delete invariants_pool;
5577 : 1426764 : invariants.release ();
5578 : 1426764 : }
5579 : :
5580 : : /* Make the invariant table empty. */
5581 : : static void
5582 : 11600551 : clear_invariants (void)
5583 : : {
5584 : 11600551 : htab_empty (invariant_table);
5585 : 11600551 : invariants_pool->release ();
5586 : 11600551 : invariants.truncate (0);
5587 : 11600551 : }
5588 : :
5589 : :
5590 : :
5591 : : /* This page contains code to do inheritance/split
5592 : : transformations. */
5593 : :
5594 : : /* Number of reloads passed so far in current EBB. */
5595 : : static int reloads_num;
5596 : :
5597 : : /* Number of calls passed so far in current EBB. */
5598 : : static int calls_num;
5599 : :
5600 : : /* Index ID is the CALLS_NUM associated the last call we saw with
5601 : : ABI identifier ID. */
5602 : : static int last_call_for_abi[NUM_ABI_IDS];
5603 : :
5604 : : /* Which registers have been fully or partially clobbered by a call
5605 : : since they were last used. */
5606 : : static HARD_REG_SET full_and_partial_call_clobbers;
5607 : :
5608 : : /* Current reload pseudo check for validity of elements in
5609 : : USAGE_INSNS. */
5610 : : static int curr_usage_insns_check;
5611 : :
5612 : : /* Info about last usage of registers in EBB to do inheritance/split
5613 : : transformation. Inheritance transformation is done from a spilled
5614 : : pseudo and split transformations from a hard register or a pseudo
5615 : : assigned to a hard register. */
5616 : : struct usage_insns
5617 : : {
5618 : : /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
5619 : : value INSNS is valid. The insns is chain of optional debug insns
5620 : : and a finishing non-debug insn using the corresponding reg. The
5621 : : value is also used to mark the registers which are set up in the
5622 : : current insn. The negated insn uid is used for this. */
5623 : : int check;
5624 : : /* Value of global reloads_num at the last insn in INSNS. */
5625 : : int reloads_num;
5626 : : /* Value of global reloads_nums at the last insn in INSNS. */
5627 : : int calls_num;
5628 : : /* It can be true only for splitting. And it means that the restore
5629 : : insn should be put after insn given by the following member. */
5630 : : bool after_p;
5631 : : /* Next insns in the current EBB which use the original reg and the
5632 : : original reg value is not changed between the current insn and
5633 : : the next insns. In order words, e.g. for inheritance, if we need
5634 : : to use the original reg value again in the next insns we can try
5635 : : to use the value in a hard register from a reload insn of the
5636 : : current insn. */
5637 : : rtx insns;
5638 : : };
5639 : :
5640 : : /* Map: regno -> corresponding pseudo usage insns. */
5641 : : static struct usage_insns *usage_insns;
5642 : :
5643 : : static void
5644 : 223962293 : setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p)
5645 : : {
5646 : 223962293 : usage_insns[regno].check = curr_usage_insns_check;
5647 : 223962293 : usage_insns[regno].insns = insn;
5648 : 223962293 : usage_insns[regno].reloads_num = reloads_num;
5649 : 223962293 : usage_insns[regno].calls_num = calls_num;
5650 : 223962293 : usage_insns[regno].after_p = after_p;
5651 : 223962293 : if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0)
5652 : 101094880 : remove_from_hard_reg_set (&full_and_partial_call_clobbers,
5653 : 101094880 : PSEUDO_REGNO_MODE (regno),
5654 : : reg_renumber[regno]);
5655 : 223962293 : }
5656 : :
5657 : : /* The function is used to form list REGNO usages which consists of
5658 : : optional debug insns finished by a non-debug insn using REGNO.
5659 : : RELOADS_NUM is current number of reload insns processed so far. */
5660 : : static void
5661 : 127187789 : add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num)
5662 : : {
5663 : 127187789 : rtx next_usage_insns;
5664 : :
5665 : 127187789 : if (usage_insns[regno].check == curr_usage_insns_check
5666 : 63116237 : && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX
5667 : 190304026 : && DEBUG_INSN_P (insn))
5668 : : {
5669 : : /* Check that we did not add the debug insn yet. */
5670 : 11055221 : if (next_usage_insns != insn
5671 : 11055221 : && (GET_CODE (next_usage_insns) != INSN_LIST
5672 : 4521320 : || XEXP (next_usage_insns, 0) != insn))
5673 : 11055207 : usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn,
5674 : : next_usage_insns);
5675 : : }
5676 : 116132568 : else if (NONDEBUG_INSN_P (insn))
5677 : 115616881 : setup_next_usage_insn (regno, insn, reloads_num, false);
5678 : : else
5679 : 515687 : usage_insns[regno].check = 0;
5680 : 127187789 : }
5681 : :
5682 : : /* Return first non-debug insn in list USAGE_INSNS. */
5683 : : static rtx_insn *
5684 : 1003459 : skip_usage_debug_insns (rtx usage_insns)
5685 : : {
5686 : 1003459 : rtx insn;
5687 : :
5688 : : /* Skip debug insns. */
5689 : 1003459 : for (insn = usage_insns;
5690 : 1220058 : insn != NULL_RTX && GET_CODE (insn) == INSN_LIST;
5691 : 216599 : insn = XEXP (insn, 1))
5692 : : ;
5693 : 1003459 : return safe_as_a <rtx_insn *> (insn);
5694 : : }
5695 : :
5696 : : /* Return true if we need secondary memory moves for insn in
5697 : : USAGE_INSNS after inserting inherited pseudo of class INHER_CL
5698 : : into the insn. */
5699 : : static bool
5700 : 1003463 : check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED,
5701 : : rtx usage_insns ATTRIBUTE_UNUSED)
5702 : : {
5703 : 1003463 : rtx_insn *insn;
5704 : 1003463 : rtx set, dest;
5705 : 1003463 : enum reg_class cl;
5706 : :
5707 : 1003463 : if (inher_cl == ALL_REGS
5708 : 1003463 : || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX)
5709 : : return false;
5710 : 1003459 : lra_assert (INSN_P (insn));
5711 : 1003459 : if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set)))
5712 : : return false;
5713 : 964120 : dest = SET_DEST (set);
5714 : 964120 : if (! REG_P (dest))
5715 : : return false;
5716 : 964120 : lra_assert (inher_cl != NO_REGS);
5717 : 964120 : cl = get_reg_class (REGNO (dest));
5718 : 964120 : return (cl != NO_REGS && cl != ALL_REGS
5719 : 964120 : && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl));
5720 : : }
5721 : :
5722 : : /* Registers involved in inheritance/split in the current EBB
5723 : : (inheritance/split pseudos and original registers). */
5724 : : static bitmap_head check_only_regs;
5725 : :
5726 : : /* Reload pseudos cannot be involded in invariant inheritance in the
5727 : : current EBB. */
5728 : : static bitmap_head invalid_invariant_regs;
5729 : :
5730 : : /* Do inheritance transformations for insn INSN, which defines (if
5731 : : DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
5732 : : instruction in the EBB next uses ORIGINAL_REGNO; it has the same
5733 : : form as the "insns" field of usage_insns. Return true if we
5734 : : succeed in such transformation.
5735 : :
5736 : : The transformations look like:
5737 : :
5738 : : p <- ... i <- ...
5739 : : ... p <- i (new insn)
5740 : : ... =>
5741 : : <- ... p ... <- ... i ...
5742 : : or
5743 : : ... i <- p (new insn)
5744 : : <- ... p ... <- ... i ...
5745 : : ... =>
5746 : : <- ... p ... <- ... i ...
5747 : : where p is a spilled original pseudo and i is a new inheritance pseudo.
5748 : :
5749 : :
5750 : : The inheritance pseudo has the smallest class of two classes CL and
5751 : : class of ORIGINAL REGNO. */
5752 : : static bool
5753 : 1112164 : inherit_reload_reg (bool def_p, int original_regno,
5754 : : enum reg_class cl, rtx_insn *insn, rtx next_usage_insns)
5755 : : {
5756 : 1112164 : if (optimize_function_for_size_p (cfun))
5757 : : return false;
5758 : :
5759 : 1078231 : enum reg_class rclass = lra_get_allocno_class (original_regno);
5760 : 1078231 : rtx original_reg = regno_reg_rtx[original_regno];
5761 : 1078231 : rtx new_reg, usage_insn;
5762 : 1078231 : rtx_insn *new_insns;
5763 : :
5764 : 1078231 : lra_assert (! usage_insns[original_regno].after_p);
5765 : 1078231 : if (lra_dump_file != NULL)
5766 : 2 : fprintf (lra_dump_file,
5767 : : " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
5768 : 1078231 : if (! ira_reg_classes_intersect_p[cl][rclass])
5769 : : {
5770 : 74768 : if (lra_dump_file != NULL)
5771 : : {
5772 : 0 : fprintf (lra_dump_file,
5773 : : " Rejecting inheritance for %d "
5774 : : "because of disjoint classes %s and %s\n",
5775 : : original_regno, reg_class_names[cl],
5776 : : reg_class_names[rclass]);
5777 : 0 : fprintf (lra_dump_file,
5778 : : " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5779 : : }
5780 : 74768 : return false;
5781 : : }
5782 : 1003463 : if ((ira_class_subset_p[cl][rclass] && cl != rclass)
5783 : : /* We don't use a subset of two classes because it can be
5784 : : NO_REGS. This transformation is still profitable in most
5785 : : cases even if the classes are not intersected as register
5786 : : move is probably cheaper than a memory load. */
5787 : 395915 : || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass])
5788 : : {
5789 : 607548 : if (lra_dump_file != NULL)
5790 : 2 : fprintf (lra_dump_file, " Use smallest class of %s and %s\n",
5791 : : reg_class_names[cl], reg_class_names[rclass]);
5792 : :
5793 : : rclass = cl;
5794 : : }
5795 : 1003463 : if (check_secondary_memory_needed_p (rclass, next_usage_insns))
5796 : : {
5797 : : /* Reject inheritance resulting in secondary memory moves.
5798 : : Otherwise, there is a danger in LRA cycling. Also such
5799 : : transformation will be unprofitable. */
5800 : 12220 : if (lra_dump_file != NULL)
5801 : : {
5802 : 0 : rtx_insn *insn = skip_usage_debug_insns (next_usage_insns);
5803 : 0 : rtx set = single_set (insn);
5804 : :
5805 : 0 : lra_assert (set != NULL_RTX);
5806 : :
5807 : 0 : rtx dest = SET_DEST (set);
5808 : :
5809 : 0 : lra_assert (REG_P (dest));
5810 : 0 : fprintf (lra_dump_file,
5811 : : " Rejecting inheritance for insn %d(%s)<-%d(%s) "
5812 : : "as secondary mem is needed\n",
5813 : 0 : REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))],
5814 : 0 : original_regno, reg_class_names[rclass]);
5815 : 0 : fprintf (lra_dump_file,
5816 : : " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5817 : : }
5818 : 12220 : return false;
5819 : : }
5820 : 991243 : new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg,
5821 : : rclass, NULL, "inheritance");
5822 : 991243 : start_sequence ();
5823 : 991243 : if (def_p)
5824 : 438520 : lra_emit_move (original_reg, new_reg);
5825 : : else
5826 : 552723 : lra_emit_move (new_reg, original_reg);
5827 : 991243 : new_insns = get_insns ();
5828 : 991243 : end_sequence ();
5829 : 991243 : if (NEXT_INSN (new_insns) != NULL_RTX)
5830 : : {
5831 : 0 : if (lra_dump_file != NULL)
5832 : : {
5833 : 0 : fprintf (lra_dump_file,
5834 : : " Rejecting inheritance %d->%d "
5835 : : "as it results in 2 or more insns:\n",
5836 : : original_regno, REGNO (new_reg));
5837 : 0 : dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0);
5838 : 0 : fprintf (lra_dump_file,
5839 : : " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5840 : : }
5841 : 0 : return false;
5842 : : }
5843 : 991243 : lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false);
5844 : 991243 : lra_update_insn_regno_info (insn);
5845 : 991243 : if (! def_p)
5846 : : /* We now have a new usage insn for original regno. */
5847 : 552723 : setup_next_usage_insn (original_regno, new_insns, reloads_num, false);
5848 : 991243 : if (lra_dump_file != NULL)
5849 : 2 : fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n",
5850 : 2 : original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
5851 : 991243 : lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno];
5852 : 991243 : bitmap_set_bit (&check_only_regs, REGNO (new_reg));
5853 : 991243 : bitmap_set_bit (&check_only_regs, original_regno);
5854 : 991243 : bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
5855 : 991243 : if (def_p)
5856 : 438520 : lra_process_new_insns (insn, NULL, new_insns,
5857 : : "Add original<-inheritance");
5858 : : else
5859 : 552723 : lra_process_new_insns (insn, new_insns, NULL,
5860 : : "Add inheritance<-original");
5861 : 2197706 : while (next_usage_insns != NULL_RTX)
5862 : : {
5863 : 1206463 : if (GET_CODE (next_usage_insns) != INSN_LIST)
5864 : : {
5865 : 991243 : usage_insn = next_usage_insns;
5866 : 991243 : lra_assert (NONDEBUG_INSN_P (usage_insn));
5867 : : next_usage_insns = NULL;
5868 : : }
5869 : : else
5870 : : {
5871 : 215220 : usage_insn = XEXP (next_usage_insns, 0);
5872 : 215220 : lra_assert (DEBUG_INSN_P (usage_insn));
5873 : 215220 : next_usage_insns = XEXP (next_usage_insns, 1);
5874 : : }
5875 : 1206463 : lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
5876 : 1206463 : DEBUG_INSN_P (usage_insn));
5877 : 1206463 : lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
5878 : 1206463 : if (lra_dump_file != NULL)
5879 : : {
5880 : 2 : basic_block bb = BLOCK_FOR_INSN (usage_insn);
5881 : 2 : fprintf (lra_dump_file,
5882 : : " Inheritance reuse change %d->%d (bb%d):\n",
5883 : : original_regno, REGNO (new_reg),
5884 : : bb ? bb->index : -1);
5885 : 2 : dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
5886 : : }
5887 : : }
5888 : 991243 : if (lra_dump_file != NULL)
5889 : 2 : fprintf (lra_dump_file,
5890 : : " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
5891 : : return true;
5892 : : }
5893 : :
5894 : : /* Return true if we need a caller save/restore for pseudo REGNO which
5895 : : was assigned to a hard register. */
5896 : : static inline bool
5897 : 103150821 : need_for_call_save_p (int regno)
5898 : : {
5899 : 103150821 : lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0);
5900 : 103150821 : if (usage_insns[regno].calls_num < calls_num)
5901 : : {
5902 : : unsigned int abis = 0;
5903 : 79862976 : for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
5904 : 70989312 : if (last_call_for_abi[i] > usage_insns[regno].calls_num)
5905 : 8873664 : abis |= 1 << i;
5906 : 8873664 : gcc_assert (abis);
5907 : 8873664 : if (call_clobbered_in_region_p (abis, full_and_partial_call_clobbers,
5908 : 8873664 : PSEUDO_REGNO_MODE (regno),
5909 : : reg_renumber[regno]))
5910 : : return true;
5911 : : }
5912 : : return false;
5913 : : }
5914 : :
5915 : : /* Global registers occurring in the current EBB. */
5916 : : static bitmap_head ebb_global_regs;
5917 : :
5918 : : /* Return true if we need a split for hard register REGNO or pseudo
5919 : : REGNO which was assigned to a hard register.
5920 : : POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
5921 : : used for reloads since the EBB end. It is an approximation of the
5922 : : used hard registers in the split range. The exact value would
5923 : : require expensive calculations. If we were aggressive with
5924 : : splitting because of the approximation, the split pseudo will save
5925 : : the same hard register assignment and will be removed in the undo
5926 : : pass. We still need the approximation because too aggressive
5927 : : splitting would result in too inaccurate cost calculation in the
5928 : : assignment pass because of too many generated moves which will be
5929 : : probably removed in the undo pass. */
5930 : : static inline bool
5931 : 220437443 : need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno)
5932 : : {
5933 : 220437443 : int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno];
5934 : :
5935 : 220437443 : lra_assert (hard_regno >= 0);
5936 : 220437443 : return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno)
5937 : : /* Don't split eliminable hard registers, otherwise we can
5938 : : split hard registers like hard frame pointer, which
5939 : : lives on BB start/end according to DF-infrastructure,
5940 : : when there is a pseudo assigned to the register and
5941 : : living in the same BB. */
5942 : 582585 : && (regno >= FIRST_PSEUDO_REGISTER
5943 : 36993 : || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno))
5944 : 557365 : && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno)
5945 : : /* Don't split call clobbered hard regs living through
5946 : : calls, otherwise we might have a check problem in the
5947 : : assign sub-pass as in the most cases (exception is a
5948 : : situation when check_and_force_assignment_correctness_p value is
5949 : : true) the assign pass assumes that all pseudos living
5950 : : through calls are assigned to call saved hard regs. */
5951 : 546383 : && (regno >= FIRST_PSEUDO_REGISTER
5952 : 791 : || !TEST_HARD_REG_BIT (full_and_partial_call_clobbers, regno))
5953 : : /* We need at least 2 reloads to make pseudo splitting
5954 : : profitable. We should provide hard regno splitting in
5955 : : any case to solve 1st insn scheduling problem when
5956 : : moving hard register definition up might result in
5957 : : impossibility to find hard register for reload pseudo of
5958 : : small register class. */
5959 : 1092746 : && (usage_insns[regno].reloads_num
5960 : 1091965 : + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num)
5961 : 3441 : && (regno < FIRST_PSEUDO_REGISTER
5962 : : /* For short living pseudos, spilling + inheritance can
5963 : : be considered a substitution for splitting.
5964 : : Therefore we do not splitting for local pseudos. It
5965 : : decreases also aggressiveness of splitting. The
5966 : : minimal number of references is chosen taking into
5967 : : account that for 2 references splitting has no sense
5968 : : as we can just spill the pseudo. */
5969 : : || (regno >= FIRST_PSEUDO_REGISTER
5970 : 3394 : && lra_reg_info[regno].nrefs > 3
5971 : 2464 : && bitmap_bit_p (&ebb_global_regs, regno))))
5972 : 221018525 : || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno)));
5973 : : }
5974 : :
5975 : : /* Return class for the split pseudo created from original pseudo with
5976 : : ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
5977 : : choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
5978 : : results in no secondary memory movements. */
5979 : : static enum reg_class
5980 : 1660 : choose_split_class (enum reg_class allocno_class,
5981 : : int hard_regno ATTRIBUTE_UNUSED,
5982 : : machine_mode mode ATTRIBUTE_UNUSED)
5983 : : {
5984 : 1660 : int i;
5985 : 1660 : enum reg_class cl, best_cl = NO_REGS;
5986 : 1660 : enum reg_class hard_reg_class ATTRIBUTE_UNUSED
5987 : : = REGNO_REG_CLASS (hard_regno);
5988 : :
5989 : 1660 : if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class)
5990 : 1660 : && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno))
5991 : : return allocno_class;
5992 : 0 : for (i = 0;
5993 : 0 : (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES;
5994 : : i++)
5995 : 0 : if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class)
5996 : 0 : && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl)
5997 : 0 : && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno)
5998 : 0 : && (best_cl == NO_REGS
5999 : 0 : || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl]))
6000 : : best_cl = cl;
6001 : : return best_cl;
6002 : : }
6003 : :
6004 : : /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. It only
6005 : : makes sense to call this function if NEW_REGNO is always equal to
6006 : : ORIGINAL_REGNO. Set up defined_p flag when caller_save_p flag is set up and
6007 : : CALL_SAVE_P is true. */
6008 : :
6009 : : static void
6010 : 325170 : lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno,
6011 : : bool call_save_p)
6012 : : {
6013 : 325170 : if (!ira_reg_equiv[original_regno].defined_p
6014 : 276141 : && !(call_save_p && ira_reg_equiv[original_regno].caller_save_p))
6015 : : return;
6016 : :
6017 : 49193 : ira_expand_reg_equiv ();
6018 : 49193 : ira_reg_equiv[new_regno].defined_p = true;
6019 : 49193 : if (ira_reg_equiv[original_regno].memory)
6020 : 21218 : ira_reg_equiv[new_regno].memory
6021 : 21218 : = copy_rtx (ira_reg_equiv[original_regno].memory);
6022 : 49193 : if (ira_reg_equiv[original_regno].constant)
6023 : 23237 : ira_reg_equiv[new_regno].constant
6024 : 23237 : = copy_rtx (ira_reg_equiv[original_regno].constant);
6025 : 49193 : if (ira_reg_equiv[original_regno].invariant)
6026 : 4738 : ira_reg_equiv[new_regno].invariant
6027 : 4738 : = copy_rtx (ira_reg_equiv[original_regno].invariant);
6028 : : }
6029 : :
6030 : : /* Do split transformations for insn INSN, which defines or uses
6031 : : ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
6032 : : the EBB next uses ORIGINAL_REGNO; it has the same form as the
6033 : : "insns" field of usage_insns. If TO is not NULL, we don't use
6034 : : usage_insns, we put restore insns after TO insn. It is a case when
6035 : : we call it from lra_split_hard_reg_for, outside the inheritance
6036 : : pass.
6037 : :
6038 : : The transformations look like:
6039 : :
6040 : : p <- ... p <- ...
6041 : : ... s <- p (new insn -- save)
6042 : : ... =>
6043 : : ... p <- s (new insn -- restore)
6044 : : <- ... p ... <- ... p ...
6045 : : or
6046 : : <- ... p ... <- ... p ...
6047 : : ... s <- p (new insn -- save)
6048 : : ... =>
6049 : : ... p <- s (new insn -- restore)
6050 : : <- ... p ... <- ... p ...
6051 : :
6052 : : where p is an original pseudo got a hard register or a hard
6053 : : register and s is a new split pseudo. The save is put before INSN
6054 : : if BEFORE_P is true. Return true if we succeed in such
6055 : : transformation. */
6056 : : static bool
6057 : 325845 : split_reg (bool before_p, int original_regno, rtx_insn *insn,
6058 : : rtx next_usage_insns, rtx_insn *to)
6059 : : {
6060 : 325845 : enum reg_class rclass;
6061 : 325845 : rtx original_reg;
6062 : 325845 : int hard_regno, nregs;
6063 : 325845 : rtx new_reg, usage_insn;
6064 : 325845 : rtx_insn *restore, *save;
6065 : 325845 : bool after_p;
6066 : 325845 : bool call_save_p;
6067 : 325845 : machine_mode mode;
6068 : :
6069 : 325845 : if (original_regno < FIRST_PSEUDO_REGISTER)
6070 : : {
6071 : 207 : rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)];
6072 : 207 : hard_regno = original_regno;
6073 : 207 : call_save_p = false;
6074 : 207 : nregs = 1;
6075 : 207 : mode = lra_reg_info[hard_regno].biggest_mode;
6076 : 207 : machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]);
6077 : : /* A reg can have a biggest_mode of VOIDmode if it was only ever seen as
6078 : : part of a multi-word register. In that case, just use the reg_rtx
6079 : : mode. Do the same also if the biggest mode was larger than a register
6080 : : or we can not compare the modes. Otherwise, limit the size to that of
6081 : : the biggest access in the function or to the natural mode at least. */
6082 : 207 : if (mode == VOIDmode
6083 : 207 : || !ordered_p (GET_MODE_PRECISION (mode),
6084 : 207 : GET_MODE_PRECISION (reg_rtx_mode))
6085 : 207 : || paradoxical_subreg_p (mode, reg_rtx_mode)
6086 : 413 : || maybe_gt (GET_MODE_PRECISION (reg_rtx_mode), GET_MODE_PRECISION (mode)))
6087 : : {
6088 : 325845 : original_reg = regno_reg_rtx[hard_regno];
6089 : 325845 : mode = reg_rtx_mode;
6090 : : }
6091 : : else
6092 : 190 : original_reg = gen_rtx_REG (mode, hard_regno);
6093 : : }
6094 : : else
6095 : : {
6096 : 325638 : mode = PSEUDO_REGNO_MODE (original_regno);
6097 : 325638 : hard_regno = reg_renumber[original_regno];
6098 : 325638 : nregs = hard_regno_nregs (hard_regno, mode);
6099 : 325638 : rclass = lra_get_allocno_class (original_regno);
6100 : 325638 : original_reg = regno_reg_rtx[original_regno];
6101 : 325638 : call_save_p = need_for_call_save_p (original_regno);
6102 : : }
6103 : 325845 : lra_assert (hard_regno >= 0);
6104 : 325845 : if (lra_dump_file != NULL)
6105 : 0 : fprintf (lra_dump_file,
6106 : : " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
6107 : :
6108 : 325845 : if (call_save_p)
6109 : : {
6110 : 324185 : mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno,
6111 : : hard_regno_nregs (hard_regno, mode),
6112 : : mode);
6113 : 324185 : new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, NULL, "save");
6114 : : }
6115 : : else
6116 : : {
6117 : 1660 : rclass = choose_split_class (rclass, hard_regno, mode);
6118 : 1660 : if (rclass == NO_REGS)
6119 : : {
6120 : 0 : if (lra_dump_file != NULL)
6121 : : {
6122 : 0 : fprintf (lra_dump_file,
6123 : : " Rejecting split of %d(%s): "
6124 : : "no good reg class for %d(%s)\n",
6125 : : original_regno,
6126 : 0 : reg_class_names[lra_get_allocno_class (original_regno)],
6127 : : hard_regno,
6128 : 0 : reg_class_names[REGNO_REG_CLASS (hard_regno)]);
6129 : 0 : fprintf
6130 : 0 : (lra_dump_file,
6131 : : " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6132 : : }
6133 : 0 : return false;
6134 : : }
6135 : : /* Split_if_necessary can split hard registers used as part of a
6136 : : multi-register mode but splits each register individually. The
6137 : : mode used for each independent register may not be supported
6138 : : so reject the split. Splitting the wider mode should theoretically
6139 : : be possible but is not implemented. */
6140 : 1660 : if (!targetm.hard_regno_mode_ok (hard_regno, mode))
6141 : : {
6142 : 0 : if (lra_dump_file != NULL)
6143 : : {
6144 : 0 : fprintf (lra_dump_file,
6145 : : " Rejecting split of %d(%s): unsuitable mode %s\n",
6146 : : original_regno,
6147 : 0 : reg_class_names[lra_get_allocno_class (original_regno)],
6148 : 0 : GET_MODE_NAME (mode));
6149 : 0 : fprintf
6150 : 0 : (lra_dump_file,
6151 : : " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6152 : : }
6153 : 0 : return false;
6154 : : }
6155 : 1660 : new_reg = lra_create_new_reg (mode, original_reg, rclass, NULL, "split");
6156 : 1660 : reg_renumber[REGNO (new_reg)] = hard_regno;
6157 : : }
6158 : 325845 : int new_regno = REGNO (new_reg);
6159 : 325845 : save = emit_spill_move (true, new_reg, original_reg);
6160 : 325845 : if (NEXT_INSN (save) != NULL_RTX && !call_save_p)
6161 : : {
6162 : 0 : if (lra_dump_file != NULL)
6163 : : {
6164 : 0 : fprintf
6165 : 0 : (lra_dump_file,
6166 : : " Rejecting split %d->%d resulting in > 2 save insns:\n",
6167 : : original_regno, new_regno);
6168 : 0 : dump_rtl_slim (lra_dump_file, save, NULL, -1, 0);
6169 : 0 : fprintf (lra_dump_file,
6170 : : " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6171 : : }
6172 : 0 : return false;
6173 : : }
6174 : 325845 : restore = emit_spill_move (false, new_reg, original_reg);
6175 : 325845 : if (NEXT_INSN (restore) != NULL_RTX && !call_save_p)
6176 : : {
6177 : 0 : if (lra_dump_file != NULL)
6178 : : {
6179 : 0 : fprintf (lra_dump_file,
6180 : : " Rejecting split %d->%d "
6181 : : "resulting in > 2 restore insns:\n",
6182 : : original_regno, new_regno);
6183 : 0 : dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0);
6184 : 0 : fprintf (lra_dump_file,
6185 : : " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6186 : : }
6187 : 0 : return false;
6188 : : }
6189 : : /* Transfer equivalence information to the spill register, so that
6190 : : if we fail to allocate the spill register, we have the option of
6191 : : rematerializing the original value instead of spilling to the stack. */
6192 : 325845 : if (!HARD_REGISTER_NUM_P (original_regno)
6193 : 325638 : && mode == PSEUDO_REGNO_MODE (original_regno))
6194 : 325170 : lra_copy_reg_equiv (new_regno, original_regno, call_save_p);
6195 : 325845 : lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno];
6196 : 325845 : bitmap_set_bit (&lra_split_regs, new_regno);
6197 : 325845 : if (to != NULL)
6198 : : {
6199 : 160 : lra_assert (next_usage_insns == NULL);
6200 : 160 : usage_insn = to;
6201 : 160 : after_p = true;
6202 : : }
6203 : : else
6204 : : {
6205 : : /* We need check_only_regs only inside the inheritance pass. */
6206 : 325685 : bitmap_set_bit (&check_only_regs, new_regno);
6207 : 325685 : bitmap_set_bit (&check_only_regs, original_regno);
6208 : 325685 : after_p = usage_insns[original_regno].after_p;
6209 : 360688 : for (;;)
6210 : : {
6211 : 360688 : if (GET_CODE (next_usage_insns) != INSN_LIST)
6212 : : {
6213 : 325685 : usage_insn = next_usage_insns;
6214 : 325685 : break;
6215 : : }
6216 : 35003 : usage_insn = XEXP (next_usage_insns, 0);
6217 : 35003 : lra_assert (DEBUG_INSN_P (usage_insn));
6218 : 35003 : next_usage_insns = XEXP (next_usage_insns, 1);
6219 : 35003 : lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false,
6220 : : true);
6221 : 35003 : lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn));
6222 : 35003 : if (lra_dump_file != NULL)
6223 : : {
6224 : 0 : fprintf (lra_dump_file, " Split reuse change %d->%d:\n",
6225 : : original_regno, new_regno);
6226 : 0 : dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn));
6227 : : }
6228 : : }
6229 : : }
6230 : 325845 : lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn));
6231 : 325845 : lra_assert (usage_insn != insn || (after_p && before_p));
6232 : 560200 : lra_process_new_insns (as_a <rtx_insn *> (usage_insn),
6233 : : after_p ? NULL : restore,
6234 : : after_p ? restore : NULL,
6235 : : call_save_p
6236 : : ? "Add reg<-save" : "Add reg<-split");
6237 : 653093 : lra_process_new_insns (insn, before_p ? save : NULL,
6238 : : before_p ? NULL : save,
6239 : : call_save_p
6240 : : ? "Add save<-reg" : "Add split<-reg");
6241 : 325845 : if (nregs > 1 || original_regno < FIRST_PSEUDO_REGISTER)
6242 : : /* If we are trying to split multi-register. We should check
6243 : : conflicts on the next assignment sub-pass. IRA can allocate on
6244 : : sub-register levels, LRA do this on pseudos level right now and
6245 : : this discrepancy may create allocation conflicts after
6246 : : splitting.
6247 : :
6248 : : If we are trying to split hard register we should also check conflicts
6249 : : as such splitting can create artificial conflict of the hard register
6250 : : with another pseudo because of simplified conflict calculation in
6251 : : LRA. */
6252 : 4608 : check_and_force_assignment_correctness_p = true;
6253 : 325845 : if (lra_dump_file != NULL)
6254 : 0 : fprintf (lra_dump_file,
6255 : : " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
6256 : : return true;
6257 : : }
6258 : :
6259 : : /* Split a hard reg for reload pseudo REGNO having RCLASS and living
6260 : : in the range [FROM, TO]. Return true if did a split. Otherwise,
6261 : : return false. */
6262 : : bool
6263 : 174 : spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to)
6264 : : {
6265 : 174 : int i, hard_regno;
6266 : 174 : int rclass_size;
6267 : 174 : rtx_insn *insn;
6268 : 174 : unsigned int uid;
6269 : 174 : bitmap_iterator bi;
6270 : 174 : HARD_REG_SET ignore;
6271 : :
6272 : 174 : lra_assert (from != NULL && to != NULL);
6273 : 174 : ignore = lra_no_alloc_regs;
6274 : 497 : EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
6275 : : {
6276 : 323 : lra_insn_recog_data_t id = lra_insn_recog_data[uid];
6277 : 323 : struct lra_static_insn_data *static_id = id->insn_static_data;
6278 : 323 : struct lra_insn_reg *reg;
6279 : :
6280 : 1192 : for (reg = id->regs; reg != NULL; reg = reg->next)
6281 : 869 : if (reg->regno < FIRST_PSEUDO_REGISTER)
6282 : 205 : SET_HARD_REG_BIT (ignore, reg->regno);
6283 : 407 : for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
6284 : 84 : SET_HARD_REG_BIT (ignore, reg->regno);
6285 : : }
6286 : 174 : rclass_size = ira_class_hard_regs_num[rclass];
6287 : 381 : for (i = 0; i < rclass_size; i++)
6288 : : {
6289 : 367 : hard_regno = ira_class_hard_regs[rclass][i];
6290 : 367 : if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
6291 : 367 : || TEST_HARD_REG_BIT (ignore, hard_regno))
6292 : 201 : continue;
6293 : 479 : for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
6294 : : {
6295 : 319 : struct lra_static_insn_data *static_id;
6296 : 319 : struct lra_insn_reg *reg;
6297 : :
6298 : 319 : if (!INSN_P (insn))
6299 : 0 : continue;
6300 : 319 : if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap,
6301 : 319 : INSN_UID (insn)))
6302 : : break;
6303 : 313 : static_id = lra_get_insn_recog_data (insn)->insn_static_data;
6304 : 367 : for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
6305 : 54 : if (reg->regno == hard_regno)
6306 : : break;
6307 : : if (reg != NULL)
6308 : : break;
6309 : : }
6310 : 166 : if (insn != NEXT_INSN (to))
6311 : 6 : continue;
6312 : 160 : if (split_reg (true, hard_regno, from, NULL, to))
6313 : : return true;
6314 : : }
6315 : : return false;
6316 : : }
6317 : :
6318 : : /* Recognize that we need a split transformation for insn INSN, which
6319 : : defines or uses REGNO in its insn biggest MODE (we use it only if
6320 : : REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
6321 : : hard registers which might be used for reloads since the EBB end.
6322 : : Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
6323 : : uid before starting INSN processing. Return true if we succeed in
6324 : : such transformation. */
6325 : : static bool
6326 : 186399345 : split_if_necessary (int regno, machine_mode mode,
6327 : : HARD_REG_SET potential_reload_hard_regs,
6328 : : bool before_p, rtx_insn *insn, int max_uid)
6329 : : {
6330 : 186399345 : bool res = false;
6331 : 186399345 : int i, nregs = 1;
6332 : 186399345 : rtx next_usage_insns;
6333 : :
6334 : 186399345 : if (regno < FIRST_PSEUDO_REGISTER)
6335 : 85444766 : nregs = hard_regno_nregs (regno, mode);
6336 : 373147930 : for (i = 0; i < nregs; i++)
6337 : 186748585 : if (usage_insns[regno + i].check == curr_usage_insns_check
6338 : 122879977 : && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX
6339 : : /* To avoid processing the register twice or more. */
6340 : 122879977 : && ((GET_CODE (next_usage_insns) != INSN_LIST
6341 : 119127072 : && INSN_UID (next_usage_insns) < max_uid)
6342 : 3752905 : || (GET_CODE (next_usage_insns) == INSN_LIST
6343 : 3752905 : && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid)))
6344 : 122879977 : && need_for_split_p (potential_reload_hard_regs, regno + i)
6345 : 186901600 : && split_reg (before_p, regno + i, insn, next_usage_insns, NULL))
6346 : : res = true;
6347 : 186399345 : return res;
6348 : : }
6349 : :
6350 : : /* Return TRUE if rtx X is considered as an invariant for
6351 : : inheritance. */
6352 : : static bool
6353 : 9093842 : invariant_p (const_rtx x)
6354 : : {
6355 : 9093842 : machine_mode mode;
6356 : 9093842 : const char *fmt;
6357 : 9093842 : enum rtx_code code;
6358 : 9093842 : int i, j;
6359 : :
6360 : 9093842 : if (side_effects_p (x))
6361 : : return false;
6362 : :
6363 : 9085762 : code = GET_CODE (x);
6364 : 9085762 : mode = GET_MODE (x);
6365 : 9085762 : if (code == SUBREG)
6366 : : {
6367 : 409054 : x = SUBREG_REG (x);
6368 : 409054 : code = GET_CODE (x);
6369 : 409054 : mode = wider_subreg_mode (mode, GET_MODE (x));
6370 : : }
6371 : :
6372 : 9085762 : if (MEM_P (x))
6373 : : return false;
6374 : :
6375 : 7515803 : if (REG_P (x))
6376 : : {
6377 : 2717173 : int i, nregs, regno = REGNO (x);
6378 : :
6379 : 2717173 : if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM
6380 : 433838 : || TEST_HARD_REG_BIT (eliminable_regset, regno)
6381 : 2728950 : || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC)
6382 : : return false;
6383 : 2 : nregs = hard_regno_nregs (regno, mode);
6384 : 2 : for (i = 0; i < nregs; i++)
6385 : 2 : if (! fixed_regs[regno + i]
6386 : : /* A hard register may be clobbered in the current insn
6387 : : but we can ignore this case because if the hard
6388 : : register is used it should be set somewhere after the
6389 : : clobber. */
6390 : 2 : || bitmap_bit_p (&invalid_invariant_regs, regno + i))
6391 : 2 : return false;
6392 : : }
6393 : 4798630 : fmt = GET_RTX_FORMAT (code);
6394 : 8210699 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6395 : : {
6396 : 6223409 : if (fmt[i] == 'e')
6397 : : {
6398 : 4086958 : if (! invariant_p (XEXP (x, i)))
6399 : : return false;
6400 : : }
6401 : 2136451 : else if (fmt[i] == 'E')
6402 : : {
6403 : 518291 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6404 : 431744 : if (! invariant_p (XVECEXP (x, i, j)))
6405 : : return false;
6406 : : }
6407 : : }
6408 : : return true;
6409 : : }
6410 : :
6411 : : /* We have 'dest_reg <- invariant'. Let us try to make an invariant
6412 : : inheritance transformation (using dest_reg instead invariant in a
6413 : : subsequent insn). */
6414 : : static bool
6415 : 141376 : process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx)
6416 : : {
6417 : 141376 : invariant_ptr_t invariant_ptr;
6418 : 141376 : rtx_insn *insn, *new_insns;
6419 : 141376 : rtx insn_set, insn_reg, new_reg;
6420 : 141376 : int insn_regno;
6421 : 141376 : bool succ_p = false;
6422 : 141376 : int dst_regno = REGNO (dst_reg);
6423 : 141376 : machine_mode dst_mode = GET_MODE (dst_reg);
6424 : 141376 : enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl;
6425 : :
6426 : 141376 : invariant_ptr = insert_invariant (invariant_rtx);
6427 : 141376 : if ((insn = invariant_ptr->insn) != NULL_RTX)
6428 : : {
6429 : : /* We have a subsequent insn using the invariant. */
6430 : 16143 : insn_set = single_set (insn);
6431 : 16143 : lra_assert (insn_set != NULL);
6432 : 16143 : insn_reg = SET_DEST (insn_set);
6433 : 16143 : lra_assert (REG_P (insn_reg));
6434 : 16143 : insn_regno = REGNO (insn_reg);
6435 : 16143 : insn_reg_cl = lra_get_allocno_class (insn_regno);
6436 : :
6437 : 16143 : if (dst_mode == GET_MODE (insn_reg)
6438 : : /* We should consider only result move reg insns which are
6439 : : cheap. */
6440 : 16077 : && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2
6441 : 31785 : && targetm.register_move_cost (dst_mode, cl, cl) == 2)
6442 : : {
6443 : 15642 : if (lra_dump_file != NULL)
6444 : 0 : fprintf (lra_dump_file,
6445 : : " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n");
6446 : 15642 : new_reg = lra_create_new_reg (dst_mode, dst_reg, cl, NULL,
6447 : : "invariant inheritance");
6448 : 15642 : bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg));
6449 : 15642 : bitmap_set_bit (&check_only_regs, REGNO (new_reg));
6450 : 15642 : lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn);
6451 : 15642 : start_sequence ();
6452 : 15642 : lra_emit_move (new_reg, dst_reg);
6453 : 15642 : new_insns = get_insns ();
6454 : 15642 : end_sequence ();
6455 : 15642 : lra_process_new_insns (curr_insn, NULL, new_insns,
6456 : : "Add invariant inheritance<-original");
6457 : 15642 : start_sequence ();
6458 : 15642 : lra_emit_move (SET_DEST (insn_set), new_reg);
6459 : 15642 : new_insns = get_insns ();
6460 : 15642 : end_sequence ();
6461 : 15642 : lra_process_new_insns (insn, NULL, new_insns,
6462 : : "Changing reload<-inheritance");
6463 : 15642 : lra_set_insn_deleted (insn);
6464 : 15642 : succ_p = true;
6465 : 15642 : if (lra_dump_file != NULL)
6466 : : {
6467 : 0 : fprintf (lra_dump_file,
6468 : : " Invariant inheritance reuse change %d (bb%d):\n",
6469 : 0 : REGNO (new_reg), BLOCK_FOR_INSN (insn)->index);
6470 : 0 : dump_insn_slim (lra_dump_file, insn);
6471 : 0 : fprintf (lra_dump_file,
6472 : : " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n");
6473 : : }
6474 : : }
6475 : : }
6476 : 141376 : invariant_ptr->insn = curr_insn;
6477 : 141376 : return succ_p;
6478 : : }
6479 : :
6480 : : /* Check only registers living at the current program point in the
6481 : : current EBB. */
6482 : : static bitmap_head live_regs;
6483 : :
6484 : : /* Update live info in EBB given by its HEAD and TAIL insns after
6485 : : inheritance/split transformation. The function removes dead moves
6486 : : too. */
6487 : : static void
6488 : 515918 : update_ebb_live_info (rtx_insn *head, rtx_insn *tail)
6489 : : {
6490 : 515918 : unsigned int j;
6491 : 515918 : int i, regno;
6492 : 515918 : bool live_p;
6493 : 515918 : rtx_insn *prev_insn;
6494 : 515918 : rtx set;
6495 : 515918 : bool remove_p;
6496 : 515918 : basic_block last_bb, prev_bb, curr_bb;
6497 : 515918 : bitmap_iterator bi;
6498 : 515918 : struct lra_insn_reg *reg;
6499 : 515918 : edge e;
6500 : 515918 : edge_iterator ei;
6501 : :
6502 : 515918 : last_bb = BLOCK_FOR_INSN (tail);
6503 : 515918 : prev_bb = NULL;
6504 : 515918 : for (curr_insn = tail;
6505 : 27224566 : curr_insn != PREV_INSN (head);
6506 : 26708648 : curr_insn = prev_insn)
6507 : : {
6508 : 26708648 : prev_insn = PREV_INSN (curr_insn);
6509 : : /* We need to process empty blocks too. They contain
6510 : : NOTE_INSN_BASIC_BLOCK referring for the basic block. */
6511 : 26708648 : if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK)
6512 : 1097679 : continue;
6513 : 25610969 : curr_bb = BLOCK_FOR_INSN (curr_insn);
6514 : 25610969 : if (curr_bb != prev_bb)
6515 : : {
6516 : 1080338 : if (prev_bb != NULL)
6517 : : {
6518 : : /* Update df_get_live_in (prev_bb): */
6519 : 44871474 : EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
6520 : 44307054 : if (bitmap_bit_p (&live_regs, j))
6521 : 1225725 : bitmap_set_bit (df_get_live_in (prev_bb), j);
6522 : : else
6523 : 43081329 : bitmap_clear_bit (df_get_live_in (prev_bb), j);
6524 : : }
6525 : 1080338 : if (curr_bb != last_bb)
6526 : : {
6527 : : /* Update df_get_live_out (curr_bb): */
6528 : 44871474 : EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi)
6529 : : {
6530 : 44307054 : live_p = bitmap_bit_p (&live_regs, j);
6531 : 44307054 : if (! live_p)
6532 : 129169342 : FOR_EACH_EDGE (e, ei, curr_bb->succs)
6533 : 86127871 : if (bitmap_bit_p (df_get_live_in (e->dest), j))
6534 : : {
6535 : : live_p = true;
6536 : : break;
6537 : : }
6538 : 43081329 : if (live_p)
6539 : 1265583 : bitmap_set_bit (df_get_live_out (curr_bb), j);
6540 : : else
6541 : 43041471 : bitmap_clear_bit (df_get_live_out (curr_bb), j);
6542 : : }
6543 : : }
6544 : 1080338 : prev_bb = curr_bb;
6545 : 1080338 : bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb));
6546 : : }
6547 : 25610969 : if (! NONDEBUG_INSN_P (curr_insn))
6548 : 7723299 : continue;
6549 : 17887670 : curr_id = lra_get_insn_recog_data (curr_insn);
6550 : 17887670 : curr_static_id = curr_id->insn_static_data;
6551 : 17887670 : remove_p = false;
6552 : 17887670 : if ((set = single_set (curr_insn)) != NULL_RTX
6553 : 17349203 : && REG_P (SET_DEST (set))
6554 : 13885555 : && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER
6555 : 10478494 : && SET_DEST (set) != pic_offset_table_rtx
6556 : 10472362 : && bitmap_bit_p (&check_only_regs, regno)
6557 : 20102771 : && ! bitmap_bit_p (&live_regs, regno))
6558 : : remove_p = true;
6559 : : /* See which defined values die here. */
6560 : 49516410 : for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6561 : 31628740 : if (reg->type == OP_OUT && ! reg->subreg_p)
6562 : 12426286 : bitmap_clear_bit (&live_regs, reg->regno);
6563 : 21277656 : for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6564 : 3389986 : if (reg->type == OP_OUT && ! reg->subreg_p)
6565 : 2625246 : bitmap_clear_bit (&live_regs, reg->regno);
6566 : 17887670 : if (curr_id->arg_hard_regs != NULL)
6567 : : /* Make clobbered argument hard registers die. */
6568 : 2576553 : for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6569 : 1870578 : if (regno >= FIRST_PSEUDO_REGISTER)
6570 : 166596 : bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER);
6571 : : /* Mark each used value as live. */
6572 : 49516410 : for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6573 : 31628740 : if (reg->type != OP_OUT
6574 : 31628740 : && bitmap_bit_p (&check_only_regs, reg->regno))
6575 : 3201727 : bitmap_set_bit (&live_regs, reg->regno);
6576 : 21277656 : for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
6577 : 3389986 : if (reg->type != OP_OUT
6578 : 3389986 : && bitmap_bit_p (&check_only_regs, reg->regno))
6579 : 0 : bitmap_set_bit (&live_regs, reg->regno);
6580 : 17887670 : if (curr_id->arg_hard_regs != NULL)
6581 : : /* Make used argument hard registers live. */
6582 : 2576553 : for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6583 : 1870578 : if (regno < FIRST_PSEUDO_REGISTER
6584 : 1870578 : && bitmap_bit_p (&check_only_regs, regno))
6585 : 0 : bitmap_set_bit (&live_regs, regno);
6586 : : /* It is quite important to remove dead move insns because it
6587 : : means removing dead store. We don't need to process them for
6588 : : constraints. */
6589 : 17887670 : if (remove_p)
6590 : : {
6591 : 246411 : if (lra_dump_file != NULL)
6592 : : {
6593 : 2 : fprintf (lra_dump_file, " Removing dead insn:\n ");
6594 : 2 : dump_insn_slim (lra_dump_file, curr_insn);
6595 : : }
6596 : 246411 : lra_set_insn_deleted (curr_insn);
6597 : : }
6598 : : }
6599 : 515918 : }
6600 : :
6601 : : /* The structure describes info to do an inheritance for the current
6602 : : insn. We need to collect such info first before doing the
6603 : : transformations because the transformations change the insn
6604 : : internal representation. */
6605 : : struct to_inherit
6606 : : {
6607 : : /* Original regno. */
6608 : : int regno;
6609 : : /* Subsequent insns which can inherit original reg value. */
6610 : : rtx insns;
6611 : : };
6612 : :
6613 : : /* Array containing all info for doing inheritance from the current
6614 : : insn. */
6615 : : static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS];
6616 : :
6617 : : /* Number elements in the previous array. */
6618 : : static int to_inherit_num;
6619 : :
6620 : : /* Add inheritance info REGNO and INSNS. Their meaning is described in
6621 : : structure to_inherit. */
6622 : : static void
6623 : 291949 : add_to_inherit (int regno, rtx insns)
6624 : : {
6625 : 291949 : int i;
6626 : :
6627 : 292007 : for (i = 0; i < to_inherit_num; i++)
6628 : 58 : if (to_inherit[i].regno == regno)
6629 : : return;
6630 : 291949 : lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS);
6631 : 291949 : to_inherit[to_inherit_num].regno = regno;
6632 : 291949 : to_inherit[to_inherit_num++].insns = insns;
6633 : : }
6634 : :
6635 : : /* Return the last non-debug insn in basic block BB, or the block begin
6636 : : note if none. */
6637 : : static rtx_insn *
6638 : 27126844 : get_last_insertion_point (basic_block bb)
6639 : : {
6640 : 27126844 : rtx_insn *insn;
6641 : :
6642 : 28978967 : FOR_BB_INSNS_REVERSE (bb, insn)
6643 : 28978967 : if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn))
6644 : 27126844 : return insn;
6645 : 0 : gcc_unreachable ();
6646 : : }
6647 : :
6648 : : /* Set up RES by registers living on edges FROM except the edge (FROM,
6649 : : TO) or by registers set up in a jump insn in BB FROM. */
6650 : : static void
6651 : 10350937 : get_live_on_other_edges (basic_block from, basic_block to, bitmap res)
6652 : : {
6653 : 10350937 : rtx_insn *last;
6654 : 10350937 : struct lra_insn_reg *reg;
6655 : 10350937 : edge e;
6656 : 10350937 : edge_iterator ei;
6657 : :
6658 : 10350937 : lra_assert (to != NULL);
6659 : 10350937 : bitmap_clear (res);
6660 : 30780317 : FOR_EACH_EDGE (e, ei, from->succs)
6661 : 20429380 : if (e->dest != to)
6662 : 10078443 : bitmap_ior_into (res, df_get_live_in (e->dest));
6663 : 10350937 : last = get_last_insertion_point (from);
6664 : 10350937 : if (! JUMP_P (last))
6665 : 1893879 : return;
6666 : 8457058 : curr_id = lra_get_insn_recog_data (last);
6667 : 16913944 : for (reg = curr_id->regs; reg != NULL; reg = reg->next)
6668 : 8456886 : if (reg->type != OP_IN)
6669 : 74 : bitmap_set_bit (res, reg->regno);
6670 : : }
6671 : :
6672 : : /* Used as a temporary results of some bitmap calculations. */
6673 : : static bitmap_head temp_bitmap;
6674 : :
6675 : : /* We split for reloads of small class of hard regs. The following
6676 : : defines how many hard regs the class should have to be qualified as
6677 : : small. The code is mostly oriented to x86/x86-64 architecture
6678 : : where some insns need to use only specific register or pair of
6679 : : registers and these register can live in RTL explicitly, e.g. for
6680 : : parameter passing. */
6681 : : static const int max_small_class_regs_num = 2;
6682 : :
6683 : : /* Do inheritance/split transformations in EBB starting with HEAD and
6684 : : finishing on TAIL. We process EBB insns in the reverse order.
6685 : : Return true if we did any inheritance/split transformation in the
6686 : : EBB.
6687 : :
6688 : : We should avoid excessive splitting which results in worse code
6689 : : because of inaccurate cost calculations for spilling new split
6690 : : pseudos in such case. To achieve this we do splitting only if
6691 : : register pressure is high in given basic block and there are reload
6692 : : pseudos requiring hard registers. We could do more register
6693 : : pressure calculations at any given program point to avoid necessary
6694 : : splitting even more but it is to expensive and the current approach
6695 : : works well enough. */
6696 : : static bool
6697 : 11600551 : inherit_in_ebb (rtx_insn *head, rtx_insn *tail)
6698 : : {
6699 : 11600551 : int i, src_regno, dst_regno, nregs;
6700 : 11600551 : bool change_p, succ_p, update_reloads_num_p;
6701 : 11600551 : rtx_insn *prev_insn, *last_insn;
6702 : 11600551 : rtx next_usage_insns, curr_set;
6703 : 11600551 : enum reg_class cl;
6704 : 11600551 : struct lra_insn_reg *reg;
6705 : 11600551 : basic_block last_processed_bb, curr_bb = NULL;
6706 : 11600551 : HARD_REG_SET potential_reload_hard_regs, live_hard_regs;
6707 : 11600551 : bitmap to_process;
6708 : 11600551 : unsigned int j;
6709 : 11600551 : bitmap_iterator bi;
6710 : 11600551 : bool head_p, after_p;
6711 : :
6712 : 11600551 : change_p = false;
6713 : 11600551 : curr_usage_insns_check++;
6714 : 11600551 : clear_invariants ();
6715 : 11600551 : reloads_num = calls_num = 0;
6716 : 104404959 : for (unsigned int i = 0; i < NUM_ABI_IDS; ++i)
6717 : 92804408 : last_call_for_abi[i] = 0;
6718 : 11600551 : CLEAR_HARD_REG_SET (full_and_partial_call_clobbers);
6719 : 11600551 : bitmap_clear (&check_only_regs);
6720 : 11600551 : bitmap_clear (&invalid_invariant_regs);
6721 : 11600551 : last_processed_bb = NULL;
6722 : 11600551 : CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6723 : 11600551 : live_hard_regs = eliminable_regset | lra_no_alloc_regs;
6724 : : /* We don't process new insns generated in the loop. */
6725 : 208595934 : for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn)
6726 : : {
6727 : 196995383 : prev_insn = PREV_INSN (curr_insn);
6728 : 196995383 : if (BLOCK_FOR_INSN (curr_insn) != NULL)
6729 : 196995158 : curr_bb = BLOCK_FOR_INSN (curr_insn);
6730 : 196995383 : if (last_processed_bb != curr_bb)
6731 : : {
6732 : : /* We are at the end of BB. Add qualified living
6733 : : pseudos for potential splitting. */
6734 : 16775907 : to_process = df_get_live_out (curr_bb);
6735 : 16775907 : if (last_processed_bb != NULL)
6736 : : {
6737 : : /* We are somewhere in the middle of EBB. */
6738 : 5175356 : get_live_on_other_edges (curr_bb, last_processed_bb,
6739 : : &temp_bitmap);
6740 : 5175356 : to_process = &temp_bitmap;
6741 : : }
6742 : 16775907 : last_processed_bb = curr_bb;
6743 : 16775907 : last_insn = get_last_insertion_point (curr_bb);
6744 : 33551814 : after_p = (! JUMP_P (last_insn)
6745 : 16775907 : && (! CALL_P (last_insn)
6746 : 2182409 : || (find_reg_note (last_insn,
6747 : : REG_NORETURN, NULL_RTX) == NULL_RTX
6748 : 1306660 : && ! SIBLING_CALL_P (last_insn))));
6749 : 16775907 : CLEAR_HARD_REG_SET (potential_reload_hard_regs);
6750 : 179618020 : EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
6751 : : {
6752 : 162842300 : if ((int) j >= lra_constraint_new_regno_start)
6753 : : break;
6754 : 162842113 : if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
6755 : : {
6756 : 105803815 : if (j < FIRST_PSEUDO_REGISTER)
6757 : 63169011 : SET_HARD_REG_BIT (live_hard_regs, j);
6758 : : else
6759 : 42634804 : add_to_hard_reg_set (&live_hard_regs,
6760 : 42634804 : PSEUDO_REGNO_MODE (j),
6761 : 42634804 : reg_renumber[j]);
6762 : 105803815 : setup_next_usage_insn (j, last_insn, reloads_num, after_p);
6763 : : }
6764 : : }
6765 : : }
6766 : 196995383 : src_regno = dst_regno = -1;
6767 : 196995383 : curr_set = single_set (curr_insn);
6768 : 196995383 : if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set)))
6769 : 78664356 : dst_regno = REGNO (SET_DEST (curr_set));
6770 : 105961102 : if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set)))
6771 : 37908338 : src_regno = REGNO (SET_SRC (curr_set));
6772 : 196995383 : update_reloads_num_p = true;
6773 : 196995383 : if (src_regno < lra_constraint_new_regno_start
6774 : 191736260 : && src_regno >= FIRST_PSEUDO_REGISTER
6775 : 27713282 : && reg_renumber[src_regno] < 0
6776 : 3346237 : && dst_regno >= lra_constraint_new_regno_start
6777 : 199353460 : && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS)
6778 : : {
6779 : : /* 'reload_pseudo <- original_pseudo'. */
6780 : 2358077 : if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6781 : 21658 : reloads_num++;
6782 : 2358077 : update_reloads_num_p = false;
6783 : 2358077 : succ_p = false;
6784 : 2358077 : if (usage_insns[src_regno].check == curr_usage_insns_check
6785 : 2358077 : && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX)
6786 : 417609 : succ_p = inherit_reload_reg (false, src_regno, cl,
6787 : : curr_insn, next_usage_insns);
6788 : 417609 : if (succ_p)
6789 : : change_p = true;
6790 : : else
6791 : 1963181 : setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
6792 : 4716154 : if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6793 : 196995383 : potential_reload_hard_regs |= reg_class_contents[cl];
6794 : : }
6795 : 194637306 : else if (src_regno < 0
6796 : 159087045 : && dst_regno >= lra_constraint_new_regno_start
6797 : 4575140 : && invariant_p (SET_SRC (curr_set))
6798 : 279928 : && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS
6799 : 279399 : && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno)
6800 : 194884690 : && ! bitmap_bit_p (&invalid_invariant_regs,
6801 : 247384 : ORIGINAL_REGNO(regno_reg_rtx[dst_regno])))
6802 : : {
6803 : : /* 'reload_pseudo <- invariant'. */
6804 : 141376 : if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6805 : 12623 : reloads_num++;
6806 : 141376 : update_reloads_num_p = false;
6807 : 141376 : if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set)))
6808 : 15642 : change_p = true;
6809 : 282752 : if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6810 : 196995383 : potential_reload_hard_regs |= reg_class_contents[cl];
6811 : : }
6812 : 194495930 : else if (src_regno >= lra_constraint_new_regno_start
6813 : 5259123 : && dst_regno < lra_constraint_new_regno_start
6814 : 4593220 : && dst_regno >= FIRST_PSEUDO_REGISTER
6815 : 3369111 : && reg_renumber[dst_regno] < 0
6816 : 1321440 : && (cl = lra_get_allocno_class (src_regno)) != NO_REGS
6817 : 1321440 : && usage_insns[dst_regno].check == curr_usage_insns_check
6818 : 194495930 : && (next_usage_insns
6819 : 402606 : = usage_insns[dst_regno].insns) != NULL_RTX)
6820 : : {
6821 : 402606 : if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
6822 : 6516 : reloads_num++;
6823 : 402606 : update_reloads_num_p = false;
6824 : : /* 'original_pseudo <- reload_pseudo'. */
6825 : 402606 : if (! JUMP_P (curr_insn)
6826 : 402606 : && inherit_reload_reg (true, dst_regno, cl,
6827 : : curr_insn, next_usage_insns))
6828 : : change_p = true;
6829 : : /* Invalidate. */
6830 : 402606 : usage_insns[dst_regno].check = 0;
6831 : 805212 : if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
6832 : 196995383 : potential_reload_hard_regs |= reg_class_contents[cl];
6833 : : }
6834 : 194093324 : else if (INSN_P (curr_insn))
6835 : : {
6836 : 162030235 : int iter;
6837 : 162030235 : int max_uid = get_max_uid ();
6838 : :
6839 : 162030235 : curr_id = lra_get_insn_recog_data (curr_insn);
6840 : 162030235 : curr_static_id = curr_id->insn_static_data;
6841 : 162030235 : to_inherit_num = 0;
6842 : : /* Process insn definitions. */
6843 : 486090705 : for (iter = 0; iter < 2; iter++)
6844 : 324060470 : for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6845 : 532923688 : reg != NULL;
6846 : 208863218 : reg = reg->next)
6847 : 208863218 : if (reg->type != OP_IN
6848 : 208863218 : && (dst_regno = reg->regno) < lra_constraint_new_regno_start)
6849 : : {
6850 : 44551696 : if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT
6851 : 42638003 : && reg_renumber[dst_regno] < 0 && ! reg->subreg_p
6852 : 1655594 : && usage_insns[dst_regno].check == curr_usage_insns_check
6853 : 86627637 : && (next_usage_insns
6854 : 108429 : = usage_insns[dst_regno].insns) != NULL_RTX)
6855 : : {
6856 : 108429 : struct lra_insn_reg *r;
6857 : :
6858 : 324106 : for (r = curr_id->regs; r != NULL; r = r->next)
6859 : 215677 : if (r->type != OP_OUT && r->regno == dst_regno)
6860 : : break;
6861 : : /* Don't do inheritance if the pseudo is also
6862 : : used in the insn. */
6863 : 108429 : if (r == NULL)
6864 : : /* We cannot do inheritance right now
6865 : : because the current insn reg info (chain
6866 : : regs) can change after that. */
6867 : 108429 : add_to_inherit (dst_regno, next_usage_insns);
6868 : : }
6869 : : /* We cannot process one reg twice here because of
6870 : : usage_insns invalidation. */
6871 : 86627637 : if ((dst_regno < FIRST_PSEUDO_REGISTER
6872 : 44551696 : || reg_renumber[dst_regno] >= 0)
6873 : 84832503 : && ! reg->subreg_p && reg->type != OP_IN)
6874 : : {
6875 : 84570530 : HARD_REG_SET s;
6876 : :
6877 : 84570530 : if (split_if_necessary (dst_regno, reg->biggest_mode,
6878 : : potential_reload_hard_regs,
6879 : : false, curr_insn, max_uid))
6880 : 42102 : change_p = true;
6881 : 84570530 : CLEAR_HARD_REG_SET (s);
6882 : 84570530 : if (dst_regno < FIRST_PSEUDO_REGISTER)
6883 : 42075941 : add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno);
6884 : : else
6885 : 42494589 : add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
6886 : 42494589 : reg_renumber[dst_regno]);
6887 : 84570530 : live_hard_regs &= ~s;
6888 : 169141060 : potential_reload_hard_regs &= ~s;
6889 : : }
6890 : : /* We should invalidate potential inheritance or
6891 : : splitting for the current insn usages to the next
6892 : : usage insns (see code below) as the output pseudo
6893 : : prevents this. */
6894 : 86627637 : if ((dst_regno >= FIRST_PSEUDO_REGISTER
6895 : 44551696 : && reg_renumber[dst_regno] < 0)
6896 : 84832503 : || (reg->type == OP_OUT && ! reg->subreg_p
6897 : 77262960 : && (dst_regno < FIRST_PSEUDO_REGISTER
6898 : 40589755 : || reg_renumber[dst_regno] >= 0)))
6899 : : {
6900 : : /* Invalidate and mark definitions. */
6901 : 42384889 : if (dst_regno >= FIRST_PSEUDO_REGISTER)
6902 : 42384889 : usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn);
6903 : : else
6904 : : {
6905 : 36673205 : nregs = hard_regno_nregs (dst_regno,
6906 : 36673205 : reg->biggest_mode);
6907 : 73595144 : for (i = 0; i < nregs; i++)
6908 : 73843878 : usage_insns[dst_regno + i].check
6909 : 36921939 : = -(int) INSN_UID (curr_insn);
6910 : : }
6911 : : }
6912 : : }
6913 : : /* Process clobbered call regs. */
6914 : 162030235 : if (curr_id->arg_hard_regs != NULL)
6915 : 18799498 : for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
6916 : 13413725 : if (dst_regno >= FIRST_PSEUDO_REGISTER)
6917 : 1618146 : usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check
6918 : 809073 : = -(int) INSN_UID (curr_insn);
6919 : 162030235 : if (! JUMP_P (curr_insn))
6920 : 151821812 : for (i = 0; i < to_inherit_num; i++)
6921 : 108429 : if (inherit_reload_reg (true, to_inherit[i].regno,
6922 : : ALL_REGS, curr_insn,
6923 : : to_inherit[i].insns))
6924 : 82599 : change_p = true;
6925 : 162030235 : if (CALL_P (curr_insn))
6926 : : {
6927 : 6946180 : rtx cheap, pat, dest;
6928 : 6946180 : rtx_insn *restore;
6929 : 6946180 : int regno, hard_regno;
6930 : :
6931 : 6946180 : calls_num++;
6932 : 6946180 : function_abi callee_abi = insn_callee_abi (curr_insn);
6933 : 6946180 : last_call_for_abi[callee_abi.id ()] = calls_num;
6934 : 6946180 : full_and_partial_call_clobbers
6935 : 6946180 : |= callee_abi.full_and_partial_reg_clobbers ();
6936 : 13892360 : if ((cheap = find_reg_note (curr_insn,
6937 : : REG_RETURNED, NULL_RTX)) != NULL_RTX
6938 : 25761 : && ((cheap = XEXP (cheap, 0)), true)
6939 : 25761 : && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER
6940 : 25761 : && (hard_regno = reg_renumber[regno]) >= 0
6941 : 23229 : && usage_insns[regno].check == curr_usage_insns_check
6942 : : /* If there are pending saves/restores, the
6943 : : optimization is not worth. */
6944 : 19628 : && usage_insns[regno].calls_num == calls_num - 1
6945 : 6964596 : && callee_abi.clobbers_reg_p (GET_MODE (cheap), hard_regno))
6946 : : {
6947 : : /* Restore the pseudo from the call result as
6948 : : REG_RETURNED note says that the pseudo value is
6949 : : in the call result and the pseudo is an argument
6950 : : of the call. */
6951 : 6789 : pat = PATTERN (curr_insn);
6952 : 6789 : if (GET_CODE (pat) == PARALLEL)
6953 : 0 : pat = XVECEXP (pat, 0, 0);
6954 : 6789 : dest = SET_DEST (pat);
6955 : : /* For multiple return values dest is PARALLEL.
6956 : : Currently we handle only single return value case. */
6957 : 6789 : if (REG_P (dest))
6958 : : {
6959 : 6789 : start_sequence ();
6960 : 6789 : emit_move_insn (cheap, copy_rtx (dest));
6961 : 6789 : restore = get_insns ();
6962 : 6789 : end_sequence ();
6963 : 6789 : lra_process_new_insns (curr_insn, NULL, restore,
6964 : : "Inserting call parameter restore");
6965 : : /* We don't need to save/restore of the pseudo from
6966 : : this call. */
6967 : 6789 : usage_insns[regno].calls_num = calls_num;
6968 : 6789 : remove_from_hard_reg_set
6969 : 6789 : (&full_and_partial_call_clobbers,
6970 : 6789 : GET_MODE (cheap), hard_regno);
6971 : 6789 : bitmap_set_bit (&check_only_regs, regno);
6972 : : }
6973 : : }
6974 : : }
6975 : 162030235 : to_inherit_num = 0;
6976 : : /* Process insn usages. */
6977 : 486090705 : for (iter = 0; iter < 2; iter++)
6978 : 324060470 : for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs;
6979 : 532923688 : reg != NULL;
6980 : 208863218 : reg = reg->next)
6981 : 208863218 : if ((reg->type != OP_OUT
6982 : 84750327 : || (reg->type == OP_OUT && reg->subreg_p))
6983 : 209415327 : && (src_regno = reg->regno) < lra_constraint_new_regno_start)
6984 : : {
6985 : 114804985 : if (src_regno >= FIRST_PSEUDO_REGISTER
6986 : 67696356 : && reg_renumber[src_regno] < 0 && reg->type == OP_IN)
6987 : : {
6988 : 2259415 : if (usage_insns[src_regno].check == curr_usage_insns_check
6989 : 664112 : && (next_usage_insns
6990 : 664112 : = usage_insns[src_regno].insns) != NULL_RTX
6991 : 2923527 : && NONDEBUG_INSN_P (curr_insn))
6992 : 183520 : add_to_inherit (src_regno, next_usage_insns);
6993 : 4151790 : else if (usage_insns[src_regno].check
6994 : 2075895 : != -(int) INSN_UID (curr_insn))
6995 : : /* Add usages but only if the reg is not set up
6996 : : in the same insn. */
6997 : 2075895 : add_next_usage_insn (src_regno, curr_insn, reloads_num);
6998 : : }
6999 : 65436941 : else if (src_regno < FIRST_PSEUDO_REGISTER
7000 : 65436941 : || reg_renumber[src_regno] >= 0)
7001 : : {
7002 : 112406030 : bool before_p;
7003 : 112406030 : rtx_insn *use_insn = curr_insn;
7004 : :
7005 : 224812060 : before_p = (JUMP_P (curr_insn)
7006 : 112406030 : || (CALL_P (curr_insn) && reg->type == OP_IN));
7007 : 112406030 : if (NONDEBUG_INSN_P (curr_insn)
7008 : 101828923 : && (! JUMP_P (curr_insn) || reg->type == OP_IN)
7009 : 214234845 : && split_if_necessary (src_regno, reg->biggest_mode,
7010 : : potential_reload_hard_regs,
7011 : : before_p, curr_insn, max_uid))
7012 : : {
7013 : 110913 : if (reg->subreg_p)
7014 : 1638 : check_and_force_assignment_correctness_p = true;
7015 : 110913 : change_p = true;
7016 : : /* Invalidate. */
7017 : 110913 : usage_insns[src_regno].check = 0;
7018 : 110913 : if (before_p)
7019 : 97 : use_insn = PREV_INSN (curr_insn);
7020 : : }
7021 : 112406030 : if (NONDEBUG_INSN_P (curr_insn))
7022 : : {
7023 : 101828923 : if (src_regno < FIRST_PSEUDO_REGISTER)
7024 : 43368847 : add_to_hard_reg_set (&live_hard_regs,
7025 : 43368847 : reg->biggest_mode, src_regno);
7026 : : else
7027 : 58460076 : add_to_hard_reg_set (&live_hard_regs,
7028 : 58460076 : PSEUDO_REGNO_MODE (src_regno),
7029 : 58460076 : reg_renumber[src_regno]);
7030 : : }
7031 : 112406030 : if (src_regno >= FIRST_PSEUDO_REGISTER)
7032 : 65297401 : add_next_usage_insn (src_regno, use_insn, reloads_num);
7033 : : else
7034 : : {
7035 : 94318470 : for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++)
7036 : 47209841 : add_next_usage_insn (src_regno + i, use_insn, reloads_num);
7037 : : }
7038 : : }
7039 : : }
7040 : : /* Process used call regs. */
7041 : 162030235 : if (curr_id->arg_hard_regs != NULL)
7042 : 18799498 : for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++)
7043 : 13413725 : if (src_regno < FIRST_PSEUDO_REGISTER)
7044 : : {
7045 : 12604652 : SET_HARD_REG_BIT (live_hard_regs, src_regno);
7046 : 12604652 : add_next_usage_insn (src_regno, curr_insn, reloads_num);
7047 : : }
7048 : 162213755 : for (i = 0; i < to_inherit_num; i++)
7049 : : {
7050 : 183520 : src_regno = to_inherit[i].regno;
7051 : 183520 : if (inherit_reload_reg (false, src_regno, ALL_REGS,
7052 : : curr_insn, to_inherit[i].insns))
7053 : : change_p = true;
7054 : : else
7055 : 25693 : setup_next_usage_insn (src_regno, curr_insn, reloads_num, false);
7056 : : }
7057 : : }
7058 : 196995383 : if (update_reloads_num_p
7059 : 194093324 : && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX)
7060 : : {
7061 : 103059043 : int regno = -1;
7062 : 103059043 : if ((REG_P (SET_DEST (curr_set))
7063 : 75762297 : && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start
7064 : 6871587 : && reg_renumber[regno] < 0
7065 : 4338336 : && (cl = lra_get_allocno_class (regno)) != NO_REGS)
7066 : 174689484 : || (REG_P (SET_SRC (curr_set))
7067 : 33988299 : && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start
7068 : 4929050 : && reg_renumber[regno] < 0
7069 : 2818704 : && (cl = lra_get_allocno_class (regno)) != NO_REGS))
7070 : : {
7071 : 6754087 : if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num)
7072 : 235299 : reloads_num++;
7073 : 13508174 : if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs))
7074 : 196995383 : potential_reload_hard_regs |= reg_class_contents[cl];
7075 : : }
7076 : : }
7077 : 196995383 : if (NONDEBUG_INSN_P (curr_insn))
7078 : : {
7079 : 112101014 : int regno;
7080 : :
7081 : : /* Invalidate invariants with changed regs. */
7082 : 112101014 : curr_id = lra_get_insn_recog_data (curr_insn);
7083 : 286420857 : for (reg = curr_id->regs; reg != NULL; reg = reg->next)
7084 : 174319843 : if (reg->type != OP_IN)
7085 : : {
7086 : 76315013 : bitmap_set_bit (&invalid_invariant_regs, reg->regno);
7087 : 152630026 : bitmap_set_bit (&invalid_invariant_regs,
7088 : 76315013 : ORIGINAL_REGNO (regno_reg_rtx[reg->regno]));
7089 : : }
7090 : 112101014 : curr_static_id = curr_id->insn_static_data;
7091 : 140642399 : for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next)
7092 : 28541385 : if (reg->type != OP_IN)
7093 : 20682374 : bitmap_set_bit (&invalid_invariant_regs, reg->regno);
7094 : 112101014 : if (curr_id->arg_hard_regs != NULL)
7095 : 18799498 : for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++)
7096 : 13413725 : if (regno >= FIRST_PSEUDO_REGISTER)
7097 : 809073 : bitmap_set_bit (&invalid_invariant_regs,
7098 : : regno - FIRST_PSEUDO_REGISTER);
7099 : : }
7100 : : /* We reached the start of the current basic block. */
7101 : 196995382 : if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head)
7102 : 382390215 : || BLOCK_FOR_INSN (prev_insn) != curr_bb)
7103 : : {
7104 : : /* We reached the beginning of the current block -- do
7105 : : rest of spliting in the current BB. */
7106 : 16776132 : to_process = df_get_live_in (curr_bb);
7107 : 16776132 : if (BLOCK_FOR_INSN (head) != curr_bb)
7108 : : {
7109 : : /* We are somewhere in the middle of EBB. */
7110 : 5175581 : get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src,
7111 : : curr_bb, &temp_bitmap);
7112 : 5175581 : to_process = &temp_bitmap;
7113 : : }
7114 : 16776132 : head_p = true;
7115 : 173965799 : EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi)
7116 : : {
7117 : 157189871 : if ((int) j >= lra_constraint_new_regno_start)
7118 : : break;
7119 : 98667004 : if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0)
7120 : 99279882 : && usage_insns[j].check == curr_usage_insns_check
7121 : 254747133 : && (next_usage_insns = usage_insns[j].insns) != NULL_RTX)
7122 : : {
7123 : 97557466 : if (need_for_split_p (potential_reload_hard_regs, j))
7124 : : {
7125 : 172670 : if (lra_dump_file != NULL && head_p)
7126 : : {
7127 : 0 : fprintf (lra_dump_file,
7128 : : " ----------------------------------\n");
7129 : 0 : head_p = false;
7130 : : }
7131 : 172670 : if (split_reg (false, j, bb_note (curr_bb),
7132 : : next_usage_insns, NULL))
7133 : 172670 : change_p = true;
7134 : : }
7135 : 97557466 : usage_insns[j].check = 0;
7136 : : }
7137 : : }
7138 : : }
7139 : : }
7140 : 11600551 : return change_p;
7141 : : }
7142 : :
7143 : : /* This value affects EBB forming. If probability of edge from EBB to
7144 : : a BB is not greater than the following value, we don't add the BB
7145 : : to EBB. */
7146 : : #define EBB_PROBABILITY_CUTOFF \
7147 : : ((REG_BR_PROB_BASE * param_lra_inheritance_ebb_probability_cutoff) / 100)
7148 : :
7149 : : /* Current number of inheritance/split iteration. */
7150 : : int lra_inheritance_iter;
7151 : :
7152 : : /* Entry function for inheritance/split pass. */
7153 : : void
7154 : 1485280 : lra_inheritance (void)
7155 : : {
7156 : 1485280 : int i;
7157 : 1485280 : basic_block bb, start_bb;
7158 : 1485280 : edge e;
7159 : :
7160 : 1485280 : lra_inheritance_iter++;
7161 : 1485280 : if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7162 : : return;
7163 : 1481622 : timevar_push (TV_LRA_INHERITANCE);
7164 : 1481622 : if (lra_dump_file != NULL)
7165 : 105 : fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n",
7166 : : lra_inheritance_iter);
7167 : 1481622 : curr_usage_insns_check = 0;
7168 : 1481622 : usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start);
7169 : 217301277 : for (i = 0; i < lra_constraint_new_regno_start; i++)
7170 : 215819655 : usage_insns[i].check = 0;
7171 : 1481622 : bitmap_initialize (&check_only_regs, ®_obstack);
7172 : 1481622 : bitmap_initialize (&invalid_invariant_regs, ®_obstack);
7173 : 1481622 : bitmap_initialize (&live_regs, ®_obstack);
7174 : 1481622 : bitmap_initialize (&temp_bitmap, ®_obstack);
7175 : 1481622 : bitmap_initialize (&ebb_global_regs, ®_obstack);
7176 : 13082173 : FOR_EACH_BB_FN (bb, cfun)
7177 : : {
7178 : 11600551 : start_bb = bb;
7179 : 11600551 : if (lra_dump_file != NULL)
7180 : 357 : fprintf (lra_dump_file, "EBB");
7181 : : /* Form a EBB starting with BB. */
7182 : 11600551 : bitmap_clear (&ebb_global_regs);
7183 : 11600551 : bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb));
7184 : 16775907 : for (;;)
7185 : : {
7186 : 16775907 : if (lra_dump_file != NULL)
7187 : 477 : fprintf (lra_dump_file, " %d", bb->index);
7188 : 16775907 : if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
7189 : 15294285 : || LABEL_P (BB_HEAD (bb->next_bb)))
7190 : : break;
7191 : 7324355 : e = find_fallthru_edge (bb->succs);
7192 : 7324355 : if (! e)
7193 : : break;
7194 : 7324355 : if (e->probability.initialized_p ()
7195 : 7324355 : && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF)
7196 : : break;
7197 : : bb = bb->next_bb;
7198 : : }
7199 : 11600551 : bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb));
7200 : 11600551 : if (lra_dump_file != NULL)
7201 : 357 : fprintf (lra_dump_file, "\n");
7202 : 11600551 : if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb)))
7203 : : /* Remember that the EBB head and tail can change in
7204 : : inherit_in_ebb. */
7205 : 515918 : update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb));
7206 : : }
7207 : 1481622 : bitmap_release (&ebb_global_regs);
7208 : 1481622 : bitmap_release (&temp_bitmap);
7209 : 1481622 : bitmap_release (&live_regs);
7210 : 1481622 : bitmap_release (&invalid_invariant_regs);
7211 : 1481622 : bitmap_release (&check_only_regs);
7212 : 1481622 : free (usage_insns);
7213 : 1481622 : lra_dump_insns_if_possible ("func after inheritance");
7214 : 1481622 : timevar_pop (TV_LRA_INHERITANCE);
7215 : : }
7216 : :
7217 : :
7218 : :
7219 : : /* This page contains code to undo failed inheritance/split
7220 : : transformations. */
7221 : :
7222 : : /* Current number of iteration undoing inheritance/split. */
7223 : : int lra_undo_inheritance_iter;
7224 : :
7225 : : /* Fix BB live info LIVE after removing pseudos created on pass doing
7226 : : inheritance/split which are REMOVED_PSEUDOS. */
7227 : : static void
7228 : 33551838 : fix_bb_live_info (bitmap live, bitmap removed_pseudos)
7229 : : {
7230 : 33551838 : unsigned int regno;
7231 : 33551838 : bitmap_iterator bi;
7232 : :
7233 : 259539388 : EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi)
7234 : 225987550 : if (bitmap_clear_bit (live, regno)
7235 : 225987550 : && REG_P (lra_reg_info[regno].restore_rtx))
7236 : 1086398 : bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx));
7237 : 33551838 : }
7238 : :
7239 : : /* Return regno of the (subreg of) REG. Otherwise, return a negative
7240 : : number. */
7241 : : static int
7242 : 63678339 : get_regno (rtx reg)
7243 : : {
7244 : 1067415 : if (GET_CODE (reg) == SUBREG)
7245 : 1099853 : reg = SUBREG_REG (reg);
7246 : 63678339 : if (REG_P (reg))
7247 : 41602089 : return REGNO (reg);
7248 : : return -1;
7249 : : }
7250 : :
7251 : : /* Delete a move INSN with destination reg DREGNO and a previous
7252 : : clobber insn with the same regno. The inheritance/split code can
7253 : : generate moves with preceding clobber and when we delete such moves
7254 : : we should delete the clobber insn too to keep the correct life
7255 : : info. */
7256 : : static void
7257 : 738123 : delete_move_and_clobber (rtx_insn *insn, int dregno)
7258 : : {
7259 : 738123 : rtx_insn *prev_insn = PREV_INSN (insn);
7260 : :
7261 : 738123 : lra_set_insn_deleted (insn);
7262 : 738123 : lra_assert (dregno >= 0);
7263 : 738123 : if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn)
7264 : 307539 : && GET_CODE (PATTERN (prev_insn)) == CLOBBER
7265 : 738809 : && dregno == get_regno (XEXP (PATTERN (prev_insn), 0)))
7266 : 0 : lra_set_insn_deleted (prev_insn);
7267 : 738123 : }
7268 : :
7269 : : /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
7270 : : return true if we did any change. The undo transformations for
7271 : : inheritance looks like
7272 : : i <- i2
7273 : : p <- i => p <- i2
7274 : : or removing
7275 : : p <- i, i <- p, and i <- i3
7276 : : where p is original pseudo from which inheritance pseudo i was
7277 : : created, i and i3 are removed inheritance pseudos, i2 is another
7278 : : not removed inheritance pseudo. All split pseudos or other
7279 : : occurrences of removed inheritance pseudos are changed on the
7280 : : corresponding original pseudos.
7281 : :
7282 : : The function also schedules insns changed and created during
7283 : : inheritance/split pass for processing by the subsequent constraint
7284 : : pass. */
7285 : : static bool
7286 : 1481624 : remove_inheritance_pseudos (bitmap remove_pseudos)
7287 : : {
7288 : 1481624 : basic_block bb;
7289 : 1481624 : int regno, sregno, prev_sregno, dregno;
7290 : 1481624 : rtx restore_rtx;
7291 : 1481624 : rtx set, prev_set;
7292 : 1481624 : rtx_insn *prev_insn;
7293 : 1481624 : bool change_p, done_p;
7294 : :
7295 : 1481624 : change_p = ! bitmap_empty_p (remove_pseudos);
7296 : : /* We cannot finish the function right away if CHANGE_P is true
7297 : : because we need to marks insns affected by previous
7298 : : inheritance/split pass for processing by the subsequent
7299 : : constraint pass. */
7300 : 18257543 : FOR_EACH_BB_FN (bb, cfun)
7301 : : {
7302 : 16775919 : fix_bb_live_info (df_get_live_in (bb), remove_pseudos);
7303 : 16775919 : fix_bb_live_info (df_get_live_out (bb), remove_pseudos);
7304 : 215451892 : FOR_BB_INSNS_REVERSE (bb, curr_insn)
7305 : : {
7306 : 198675973 : if (! INSN_P (curr_insn))
7307 : 32353225 : continue;
7308 : 166322748 : done_p = false;
7309 : 166322748 : sregno = dregno = -1;
7310 : 45306917 : if (change_p && NONDEBUG_INSN_P (curr_insn)
7311 : 196438102 : && (set = single_set (curr_insn)) != NULL_RTX)
7312 : : {
7313 : 29069962 : dregno = get_regno (SET_DEST (set));
7314 : 29069962 : sregno = get_regno (SET_SRC (set));
7315 : : }
7316 : :
7317 : 166322748 : if (sregno >= 0 && dregno >= 0)
7318 : : {
7319 : 10534212 : if (bitmap_bit_p (remove_pseudos, dregno)
7320 : 10534212 : && ! REG_P (lra_reg_info[dregno].restore_rtx))
7321 : : {
7322 : : /* invariant inheritance pseudo <- original pseudo */
7323 : 7332 : if (lra_dump_file != NULL)
7324 : : {
7325 : 0 : fprintf (lra_dump_file, " Removing invariant inheritance:\n");
7326 : 0 : dump_insn_slim (lra_dump_file, curr_insn);
7327 : 0 : fprintf (lra_dump_file, "\n");
7328 : : }
7329 : 7332 : delete_move_and_clobber (curr_insn, dregno);
7330 : 7332 : done_p = true;
7331 : : }
7332 : 10526880 : else if (bitmap_bit_p (remove_pseudos, sregno)
7333 : 10526880 : && ! REG_P (lra_reg_info[sregno].restore_rtx))
7334 : : {
7335 : : /* reload pseudo <- invariant inheritance pseudo */
7336 : 7332 : start_sequence ();
7337 : : /* We cannot just change the source. It might be
7338 : : an insn different from the move. */
7339 : 7332 : emit_insn (lra_reg_info[sregno].restore_rtx);
7340 : 7332 : rtx_insn *new_insns = get_insns ();
7341 : 7332 : end_sequence ();
7342 : 7332 : lra_assert (single_set (new_insns) != NULL
7343 : : && SET_DEST (set) == SET_DEST (single_set (new_insns)));
7344 : 7332 : lra_process_new_insns (curr_insn, NULL, new_insns,
7345 : : "Changing reload<-invariant inheritance");
7346 : 7332 : delete_move_and_clobber (curr_insn, dregno);
7347 : 7332 : done_p = true;
7348 : : }
7349 : 10519548 : else if ((bitmap_bit_p (remove_pseudos, sregno)
7350 : 1169896 : && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno
7351 : 556921 : || (bitmap_bit_p (remove_pseudos, dregno)
7352 : 198190 : && get_regno (lra_reg_info[sregno].restore_rtx) >= 0
7353 : 198190 : && (get_regno (lra_reg_info[sregno].restore_rtx)
7354 : 198190 : == get_regno (lra_reg_info[dregno].restore_rtx)))))
7355 : 10977374 : || (bitmap_bit_p (remove_pseudos, dregno)
7356 : 604510 : && get_regno (lra_reg_info[dregno].restore_rtx) == sregno))
7357 : : /* One of the following cases:
7358 : : original <- removed inheritance pseudo
7359 : : removed inherit pseudo <- another removed inherit pseudo
7360 : : removed inherit pseudo <- original pseudo
7361 : : Or
7362 : : removed_split_pseudo <- original_reg
7363 : : original_reg <- removed_split_pseudo */
7364 : : {
7365 : 178522 : if (lra_dump_file != NULL)
7366 : : {
7367 : 0 : fprintf (lra_dump_file, " Removing %s:\n",
7368 : 0 : bitmap_bit_p (&lra_split_regs, sregno)
7369 : 0 : || bitmap_bit_p (&lra_split_regs, dregno)
7370 : : ? "split" : "inheritance");
7371 : 0 : dump_insn_slim (lra_dump_file, curr_insn);
7372 : : }
7373 : 178522 : delete_move_and_clobber (curr_insn, dregno);
7374 : 178522 : done_p = true;
7375 : : }
7376 : 10341026 : else if (bitmap_bit_p (remove_pseudos, sregno)
7377 : 10341026 : && bitmap_bit_p (&lra_inheritance_pseudos, sregno))
7378 : : {
7379 : : /* Search the following pattern:
7380 : : inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
7381 : : original_pseudo <- inherit_or_split_pseudo1
7382 : : where the 2nd insn is the current insn and
7383 : : inherit_or_split_pseudo2 is not removed. If it is found,
7384 : : change the current insn onto:
7385 : : original_pseudo <- inherit_or_split_pseudo2. */
7386 : 676939 : for (prev_insn = PREV_INSN (curr_insn);
7387 : 676939 : prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn);
7388 : 219113 : prev_insn = PREV_INSN (prev_insn))
7389 : : ;
7390 : 457826 : if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb
7391 : 445273 : && (prev_set = single_set (prev_insn)) != NULL_RTX
7392 : : /* There should be no subregs in insn we are
7393 : : searching because only the original reg might
7394 : : be in subreg when we changed the mode of
7395 : : load/store for splitting. */
7396 : 438805 : && REG_P (SET_DEST (prev_set))
7397 : 345173 : && REG_P (SET_SRC (prev_set))
7398 : 268314 : && (int) REGNO (SET_DEST (prev_set)) == sregno
7399 : 188494 : && ((prev_sregno = REGNO (SET_SRC (prev_set)))
7400 : : >= FIRST_PSEUDO_REGISTER)
7401 : 188494 : && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX
7402 : 144852 : ||
7403 : : /* As we consider chain of inheritance or
7404 : : splitting described in above comment we should
7405 : : check that sregno and prev_sregno were
7406 : : inheritance/split pseudos created from the
7407 : : same original regno. */
7408 : 747530 : (get_regno (lra_reg_info[sregno].restore_rtx) >= 0
7409 : 289704 : && (get_regno (lra_reg_info[sregno].restore_rtx)
7410 : 289704 : == get_regno (lra_reg_info[prev_sregno].restore_rtx))))
7411 : 646320 : && ! bitmap_bit_p (remove_pseudos, prev_sregno))
7412 : : {
7413 : 101827 : int restore_regno = get_regno (lra_reg_info[sregno].restore_rtx);
7414 : 101827 : if (restore_regno < 0)
7415 : 0 : restore_regno = prev_sregno;
7416 : 101827 : lra_assert (GET_MODE (SET_SRC (prev_set))
7417 : : == GET_MODE (regno_reg_rtx[restore_regno]));
7418 : : /* Although we have a single set, the insn can
7419 : : contain more one sregno register occurrence
7420 : : as a source. Change all occurrences. */
7421 : 101827 : lra_substitute_pseudo_within_insn (curr_insn, sregno,
7422 : : regno_reg_rtx[restore_regno],
7423 : : false);
7424 : : /* As we are finishing with processing the insn
7425 : : here, check the destination too as it might
7426 : : inheritance pseudo for another pseudo. */
7427 : 101827 : if (bitmap_bit_p (remove_pseudos, dregno)
7428 : 0 : && bitmap_bit_p (&lra_inheritance_pseudos, dregno)
7429 : 101827 : && (restore_rtx
7430 : 0 : = lra_reg_info[dregno].restore_rtx) != NULL_RTX)
7431 : : {
7432 : 0 : if (GET_CODE (SET_DEST (set)) == SUBREG)
7433 : 0 : SUBREG_REG (SET_DEST (set)) = restore_rtx;
7434 : : else
7435 : 0 : SET_DEST (set) = restore_rtx;
7436 : : }
7437 : 101827 : lra_push_insn_and_update_insn_regno_info (curr_insn);
7438 : 101827 : lra_set_used_insn_alternative_by_uid
7439 : 101827 : (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
7440 : 101827 : done_p = true;
7441 : 101827 : if (lra_dump_file != NULL)
7442 : : {
7443 : 0 : fprintf (lra_dump_file, " Change reload insn:\n");
7444 : 0 : dump_insn_slim (lra_dump_file, curr_insn);
7445 : : }
7446 : : }
7447 : : }
7448 : : }
7449 : 166322748 : if (! done_p)
7450 : : {
7451 : 166027735 : struct lra_insn_reg *reg;
7452 : 166027735 : bool restored_regs_p = false;
7453 : 166027735 : bool kept_regs_p = false;
7454 : :
7455 : 166027735 : curr_id = lra_get_insn_recog_data (curr_insn);
7456 : 354240348 : for (reg = curr_id->regs; reg != NULL; reg = reg->next)
7457 : : {
7458 : 188212613 : regno = reg->regno;
7459 : 188212613 : restore_rtx = lra_reg_info[regno].restore_rtx;
7460 : 188212613 : if (restore_rtx != NULL_RTX)
7461 : : {
7462 : 4528707 : if (change_p && bitmap_bit_p (remove_pseudos, regno))
7463 : : {
7464 : 777672 : lra_substitute_pseudo_within_insn
7465 : 777672 : (curr_insn, regno, restore_rtx, false);
7466 : 777672 : restored_regs_p = true;
7467 : : }
7468 : : else
7469 : : kept_regs_p = true;
7470 : : }
7471 : : }
7472 : 166027735 : if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p)
7473 : : {
7474 : : /* The instruction has changed since the previous
7475 : : constraints pass. */
7476 : 3323699 : lra_push_insn_and_update_insn_regno_info (curr_insn);
7477 : 3323699 : lra_set_used_insn_alternative_by_uid
7478 : 3323699 : (INSN_UID (curr_insn), LRA_UNKNOWN_ALT);
7479 : : }
7480 : 162704036 : else if (restored_regs_p)
7481 : : /* The instruction has been restored to the form that
7482 : : it had during the previous constraints pass. */
7483 : 619877 : lra_update_insn_regno_info (curr_insn);
7484 : 3943576 : if (restored_regs_p && lra_dump_file != NULL)
7485 : : {
7486 : 0 : fprintf (lra_dump_file, " Insn after restoring regs:\n");
7487 : 0 : dump_insn_slim (lra_dump_file, curr_insn);
7488 : : }
7489 : : }
7490 : : }
7491 : : }
7492 : 1481624 : return change_p;
7493 : : }
7494 : :
7495 : : /* If optional reload pseudos failed to get a hard register or was not
7496 : : inherited, it is better to remove optional reloads. We do this
7497 : : transformation after undoing inheritance to figure out necessity to
7498 : : remove optional reloads easier. Return true if we do any
7499 : : change. */
7500 : : static bool
7501 : 1481624 : undo_optional_reloads (void)
7502 : : {
7503 : 1481624 : bool change_p, keep_p;
7504 : 1481624 : unsigned int regno, uid;
7505 : 1481624 : bitmap_iterator bi, bi2;
7506 : 1481624 : rtx_insn *insn;
7507 : 1481624 : rtx set, src, dest;
7508 : 1481624 : auto_bitmap removed_optional_reload_pseudos (®_obstack);
7509 : :
7510 : 1481624 : bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos);
7511 : 2408107 : EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7512 : : {
7513 : 926483 : keep_p = false;
7514 : : /* Keep optional reloads from previous subpasses. */
7515 : 926483 : if (lra_reg_info[regno].restore_rtx == NULL_RTX
7516 : : /* If the original pseudo changed its allocation, just
7517 : : removing the optional pseudo is dangerous as the original
7518 : : pseudo will have longer live range. */
7519 : 926483 : || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0)
7520 : : keep_p = true;
7521 : 591210 : else if (reg_renumber[regno] >= 0)
7522 : 1705343 : EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2)
7523 : : {
7524 : 1234135 : insn = lra_insn_recog_data[uid]->insn;
7525 : 1234135 : if ((set = single_set (insn)) == NULL_RTX)
7526 : 5809 : continue;
7527 : 1228326 : src = SET_SRC (set);
7528 : 1228326 : dest = SET_DEST (set);
7529 : 1228326 : if ((! REG_P (src) && ! SUBREG_P (src))
7530 : 658536 : || (! REG_P (dest) && ! SUBREG_P (dest)))
7531 : 569822 : continue;
7532 : 658504 : if (get_regno (dest) == (int) regno
7533 : : /* Ignore insn for optional reloads itself. */
7534 : 1118176 : && (get_regno (lra_reg_info[regno].restore_rtx)
7535 : 559088 : != get_regno (src))
7536 : : /* Check only inheritance on last inheritance pass. */
7537 : 104423 : && get_regno (src) >= new_regno_start
7538 : : /* Check that the optional reload was inherited. */
7539 : 762927 : && bitmap_bit_p (&lra_inheritance_pseudos, get_regno (src)))
7540 : : {
7541 : : keep_p = true;
7542 : : break;
7543 : : }
7544 : : }
7545 : 910904 : if (keep_p)
7546 : : {
7547 : 439696 : bitmap_clear_bit (removed_optional_reload_pseudos, regno);
7548 : 439696 : if (lra_dump_file != NULL)
7549 : 3 : fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno);
7550 : : }
7551 : : }
7552 : 1481624 : change_p = ! bitmap_empty_p (removed_optional_reload_pseudos);
7553 : 1481624 : auto_bitmap insn_bitmap (®_obstack);
7554 : 1968411 : EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi)
7555 : : {
7556 : 486787 : if (lra_dump_file != NULL)
7557 : 2 : fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno);
7558 : 486787 : bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap);
7559 : 1544705 : EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2)
7560 : : {
7561 : : /* We may have already removed a clobber. */
7562 : 1057918 : if (!lra_insn_recog_data[uid])
7563 : 0 : continue;
7564 : 1057918 : insn = lra_insn_recog_data[uid]->insn;
7565 : 1057918 : if ((set = single_set (insn)) != NULL_RTX)
7566 : : {
7567 : 1052216 : src = SET_SRC (set);
7568 : 1052216 : dest = SET_DEST (set);
7569 : 481063 : if ((REG_P (src) || SUBREG_P (src))
7570 : 571165 : && (REG_P (dest) || SUBREG_P (dest))
7571 : 1623347 : && ((get_regno (src) == (int) regno
7572 : 201970 : && (get_regno (lra_reg_info[regno].restore_rtx)
7573 : 100985 : == get_regno (dest)))
7574 : 496284 : || (get_regno (dest) == (int) regno
7575 : 470146 : && (get_regno (lra_reg_info[regno].restore_rtx)
7576 : 470146 : == get_regno (src)))))
7577 : : {
7578 : 544937 : if (lra_dump_file != NULL)
7579 : : {
7580 : 0 : fprintf (lra_dump_file, " Deleting move %u\n",
7581 : 0 : INSN_UID (insn));
7582 : 0 : dump_insn_slim (lra_dump_file, insn);
7583 : : }
7584 : 1089874 : delete_move_and_clobber (insn, get_regno (dest));
7585 : 544937 : continue;
7586 : : }
7587 : : /* We should not worry about generation memory-memory
7588 : : moves here as if the corresponding inheritance did
7589 : : not work (inheritance pseudo did not get a hard reg),
7590 : : we remove the inheritance pseudo and the optional
7591 : : reload. */
7592 : : }
7593 : 512981 : if (GET_CODE (PATTERN (insn)) == CLOBBER
7594 : 0 : && REG_P (SET_DEST (insn))
7595 : 512981 : && get_regno (SET_DEST (insn)) == (int) regno)
7596 : : /* Refuse to remap clobbers to preexisting pseudos. */
7597 : 0 : gcc_unreachable ();
7598 : 512981 : lra_substitute_pseudo_within_insn
7599 : 512981 : (insn, regno, lra_reg_info[regno].restore_rtx, false);
7600 : 512981 : lra_update_insn_regno_info (insn);
7601 : 512981 : if (lra_dump_file != NULL)
7602 : : {
7603 : 4 : fprintf (lra_dump_file,
7604 : : " Restoring original insn:\n");
7605 : 4 : dump_insn_slim (lra_dump_file, insn);
7606 : : }
7607 : : }
7608 : : }
7609 : : /* Clear restore_regnos. */
7610 : 2408107 : EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi)
7611 : 926483 : lra_reg_info[regno].restore_rtx = NULL_RTX;
7612 : 1481624 : return change_p;
7613 : 1481624 : }
7614 : :
7615 : : /* Entry function for undoing inheritance/split transformation. Return true
7616 : : if we did any RTL change in this pass. */
7617 : : bool
7618 : 1485377 : lra_undo_inheritance (void)
7619 : : {
7620 : 1485377 : unsigned int regno;
7621 : 1485377 : int hard_regno;
7622 : 1485377 : int n_all_inherit, n_inherit, n_all_split, n_split;
7623 : 1485377 : rtx restore_rtx;
7624 : 1485377 : bitmap_iterator bi;
7625 : 1485377 : bool change_p;
7626 : :
7627 : 1485377 : lra_undo_inheritance_iter++;
7628 : 1485377 : if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES)
7629 : : return false;
7630 : 1481624 : if (lra_dump_file != NULL)
7631 : 105 : fprintf (lra_dump_file,
7632 : : "\n********** Undoing inheritance #%d: **********\n\n",
7633 : : lra_undo_inheritance_iter);
7634 : 1481624 : auto_bitmap remove_pseudos (®_obstack);
7635 : 1481624 : n_inherit = n_all_inherit = 0;
7636 : 3086249 : EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7637 : 1604625 : if (lra_reg_info[regno].restore_rtx != NULL_RTX)
7638 : : {
7639 : 1006838 : n_all_inherit++;
7640 : 1006838 : if (reg_renumber[regno] < 0
7641 : : /* If the original pseudo changed its allocation, just
7642 : : removing inheritance is dangerous as for changing
7643 : : allocation we used shorter live-ranges. */
7644 : 1006838 : && (! REG_P (lra_reg_info[regno].restore_rtx)
7645 : 402177 : || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0))
7646 : 409509 : bitmap_set_bit (remove_pseudos, regno);
7647 : : else
7648 : 597329 : n_inherit++;
7649 : : }
7650 : 1481624 : if (lra_dump_file != NULL && n_all_inherit != 0)
7651 : 2 : fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n",
7652 : : n_inherit, n_all_inherit,
7653 : 2 : (double) n_inherit / n_all_inherit * 100);
7654 : 1481624 : n_split = n_all_split = 0;
7655 : 2020417 : EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7656 : 538793 : if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX)
7657 : : {
7658 : 325700 : int restore_regno = REGNO (restore_rtx);
7659 : :
7660 : 325700 : n_all_split++;
7661 : 651400 : hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER
7662 : 325700 : ? reg_renumber[restore_regno] : restore_regno);
7663 : 325700 : if (hard_regno < 0 || reg_renumber[regno] == hard_regno)
7664 : 2130 : bitmap_set_bit (remove_pseudos, regno);
7665 : : else
7666 : : {
7667 : 323570 : n_split++;
7668 : 323570 : if (lra_dump_file != NULL)
7669 : 0 : fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n",
7670 : : regno, restore_regno);
7671 : : }
7672 : : }
7673 : 1481624 : if (lra_dump_file != NULL && n_all_split != 0)
7674 : 0 : fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n",
7675 : : n_split, n_all_split,
7676 : 0 : (double) n_split / n_all_split * 100);
7677 : 1481624 : change_p = remove_inheritance_pseudos (remove_pseudos);
7678 : : /* Clear restore_regnos. */
7679 : 3086249 : EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi)
7680 : 1604625 : lra_reg_info[regno].restore_rtx = NULL_RTX;
7681 : 2020417 : EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi)
7682 : 538793 : lra_reg_info[regno].restore_rtx = NULL_RTX;
7683 : 1481624 : change_p = undo_optional_reloads () || change_p;
7684 : : if (change_p)
7685 : 105077 : lra_dump_insns_if_possible ("changed func after undoing inheritance");
7686 : 1481624 : return change_p;
7687 : 1481624 : }
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