Line data Source code
1 : /* Local Register Allocator (LRA) intercommunication header file.
2 : Copyright (C) 2010-2026 Free Software Foundation, Inc.
3 : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 :
5 : This file is part of GCC.
6 :
7 : GCC is free software; you can redistribute it and/or modify it under
8 : the terms of the GNU General Public License as published by the Free
9 : Software Foundation; either version 3, or (at your option) any later
10 : version.
11 :
12 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : for more details.
16 :
17 : You should have received a copy of the GNU General Public License
18 : along with GCC; see the file COPYING3. If not see
19 : <http://www.gnu.org/licenses/>. */
20 :
21 : #ifndef GCC_LRA_INT_H
22 : #define GCC_LRA_INT_H
23 :
24 : #define lra_assert(c) gcc_checking_assert (c)
25 :
26 : /* The parameter used to prevent infinite reloading for an insn. Each
27 : insn operands might require a reload and, if it is a memory, its
28 : base and index registers might require a reload too. */
29 : #define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3)
30 :
31 : typedef struct lra_live_range *lra_live_range_t;
32 :
33 : struct dependent_filter
34 : {
35 : int id;
36 : machine_mode mode;
37 : unsigned int partner_regno;
38 : machine_mode partner_mode;
39 : bool is_ref;
40 : };
41 :
42 : /* Cache entry of a dependent filter. The same fields as above, just with
43 : a hard-reg set of allowed hardregs. */
44 :
45 : struct dependent_filter_entry : dependent_filter
46 : {
47 : HARD_REG_SET allowed;
48 : };
49 :
50 : extern void lra_init_dependent_filter_cache (void);
51 : extern void lra_finish_dependent_filter_cache (void);
52 :
53 : /* The structure describes program points where a given pseudo lives.
54 : The live ranges can be used to find conflicts with other pseudos.
55 : If the live ranges of two pseudos are intersected, the pseudos are
56 : in conflict. */
57 : struct lra_live_range
58 : {
59 : /* Pseudo regno whose live range is described by given
60 : structure. */
61 : int regno;
62 : /* Program point range. */
63 : int start, finish;
64 : /* Next structure describing program points where the pseudo
65 : lives. */
66 : lra_live_range_t next;
67 : /* Pointer to structures with the same start. */
68 : lra_live_range_t start_next;
69 : };
70 :
71 : typedef struct lra_copy *lra_copy_t;
72 :
73 : /* Copy between pseudos which affects assigning hard registers. */
74 : struct lra_copy
75 : {
76 : /* True if regno1 is the destination of the copy. */
77 : bool regno1_dest_p;
78 : /* Execution frequency of the copy. */
79 : int freq;
80 : /* Pseudos connected by the copy. REGNO1 < REGNO2. */
81 : int regno1, regno2;
82 : /* Next copy with correspondingly REGNO1 and REGNO2. */
83 : lra_copy_t regno1_next, regno2_next;
84 : };
85 :
86 : /* Common info about a register (pseudo or hard register). */
87 : class lra_reg
88 : {
89 : public:
90 : /* Bitmap of UIDs of insns (including debug insns) referring the
91 : reg. */
92 : bitmap_head insn_bitmap;
93 : /* The following fields are defined only for pseudos. */
94 : /* Hard registers with which the pseudo conflicts. */
95 : HARD_REG_SET conflict_hard_regs;
96 : /* Pseudo allocno class hard registers which cannot be a start hard register
97 : of the pseudo. */
98 : HARD_REG_SET exclude_start_hard_regs;
99 : /* We assign hard registers to reload pseudos which can occur in few
100 : places. So two hard register preferences are enough for them.
101 : The following fields define the preferred hard registers. If
102 : there are no such hard registers the first field value is
103 : negative. If there is only one preferred hard register, the 2nd
104 : field is negative. */
105 : int preferred_hard_regno1, preferred_hard_regno2;
106 : /* Profits to use the corresponding preferred hard registers. If
107 : the both hard registers defined, the first hard register has not
108 : less profit than the second one. */
109 : int preferred_hard_regno_profit1, preferred_hard_regno_profit2;
110 : #ifdef STACK_REGS
111 : /* True if the pseudo should not be assigned to a stack register. */
112 : bool no_stack_p;
113 : #endif
114 : /* Number of references and execution frequencies of the register in
115 : *non-debug* insns. */
116 : int nrefs, freq;
117 : int last_reload;
118 : /* rtx used to undo the inheritance. It can be non-null only
119 : between subsequent inheritance and undo inheritance passes. */
120 : rtx restore_rtx;
121 : /* Value holding by register. If the pseudos have the same value
122 : they do not conflict. */
123 : int val;
124 : /* Offset from relative eliminate register to pesudo reg. */
125 : poly_int64 offset;
126 : /* These members are set up in lra-lives.cc and updated in
127 : lra-coalesce.cc. */
128 : /* The biggest size mode in which each pseudo reg is referred in
129 : whole function (possibly via subreg). */
130 : machine_mode biggest_mode;
131 : /* Live ranges of the pseudo. */
132 : lra_live_range_t live_ranges;
133 : /* This member is set up in lra-lives.cc for subsequent
134 : assignments. */
135 : lra_copy_t copies;
136 : /* Dependent filters for this reg. */
137 : vec<dependent_filter> dependent_filters;
138 : };
139 :
140 : /* References to the common info about each register. */
141 : extern class lra_reg *lra_reg_info;
142 :
143 : extern HARD_REG_SET hard_regs_spilled_into;
144 :
145 : /* Static info about each insn operand (common for all insns with the
146 : same ICODE). Warning: if the structure definition is changed, the
147 : initializer for debug_operand_data in lra.cc should be changed
148 : too. */
149 : struct lra_operand_data
150 : {
151 : /* The machine description constraint string of the operand. */
152 : const char *constraint;
153 : /* Alternatives for which early_clobber can be true. */
154 : alternative_mask early_clobber_alts;
155 : /* It is taken only from machine description (which is different
156 : from recog_data.operand_mode) and can be of VOIDmode. */
157 : ENUM_BITFIELD(machine_mode) mode : 16;
158 : /* The type of the operand (in/out/inout). */
159 : ENUM_BITFIELD (op_type) type : 8;
160 : /* Through if accessed through STRICT_LOW. */
161 : unsigned int strict_low : 1;
162 : /* True if the operand is an operator. */
163 : unsigned int is_operator : 1;
164 : /* True if the operand is an address. */
165 : unsigned int is_address : 1;
166 : };
167 :
168 : /* Info about register occurrence in an insn. */
169 : struct lra_insn_reg
170 : {
171 : /* Alternatives for which early_clobber can be true. */
172 : alternative_mask early_clobber_alts;
173 : /* The biggest mode through which the insn refers to the register
174 : occurrence (remember the register can be accessed through a
175 : subreg in the insn). */
176 : ENUM_BITFIELD(machine_mode) biggest_mode : 16;
177 : /* The type of the corresponding operand which is the register. */
178 : ENUM_BITFIELD (op_type) type : 8;
179 : /* True if the reg is accessed through a subreg and the subreg is
180 : just a part of the register. */
181 : unsigned int subreg_p : 1;
182 : /* The corresponding regno of the register. */
183 : int regno;
184 : /* Next reg info of the same insn. */
185 : struct lra_insn_reg *next;
186 : };
187 :
188 : /* Static part (common info for insns with the same ICODE) of LRA
189 : internal insn info. It exists in at most one exemplar for each
190 : non-negative ICODE. There is only one exception. Each asm insn has
191 : own structure. Warning: if the structure definition is changed,
192 : the initializer for debug_insn_static_data in lra.cc should be
193 : changed too. */
194 : struct lra_static_insn_data
195 : {
196 : /* Static info about each insn operand. */
197 : struct lra_operand_data *operand;
198 : /* Each duplication refers to the number of the corresponding
199 : operand which is duplicated. */
200 : int *dup_num;
201 : /* The number of an operand marked as commutative, -1 otherwise. */
202 : int commutative;
203 : /* Number of operands, duplications, and alternatives of the
204 : insn. */
205 : char n_operands;
206 : char n_dups;
207 : char n_alternatives;
208 : /* Insns in machine description (or clobbers in asm) may contain
209 : explicit hard regs which are not operands. The following list
210 : describes such hard registers. */
211 : struct lra_insn_reg *hard_regs;
212 : /* Array [n_alternatives][n_operand] of static constraint info for
213 : given operand in given alternative. This info can be changed if
214 : the target reg info is changed. */
215 : const struct operand_alternative *operand_alternative;
216 : };
217 :
218 : /* Negative insn alternative numbers used for special cases. */
219 : #define LRA_UNKNOWN_ALT -1
220 : #define LRA_NON_CLOBBERED_ALT -2
221 :
222 : /* LRA internal info about an insn (LRA internal insn
223 : representation). */
224 : class lra_insn_recog_data
225 : {
226 : public:
227 : /* The insn code. */
228 : int icode;
229 : /* The alternative should be used for the insn, LRA_UNKNOWN_ALT if
230 : unknown, or we should assume any alternative, or the insn is a
231 : debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier
232 : clobbers for the insn. */
233 : int used_insn_alternative;
234 : /* Defined for asm insn and it is how many times we already generated reloads
235 : for the asm insn. */
236 : int asm_reloads_num;
237 : /* SP offset before the insn relative to one at the func start. */
238 : poly_int64 sp_offset;
239 : /* The insn itself. */
240 : rtx_insn *insn;
241 : /* Common data for insns with the same ICODE. Asm insns (their
242 : ICODE is negative) do not share such structures. */
243 : struct lra_static_insn_data *insn_static_data;
244 : /* Two arrays of size correspondingly equal to the operand and the
245 : duplication numbers: */
246 : rtx **operand_loc; /* The operand locations, NULL if no operands. */
247 : rtx **dup_loc; /* The dup locations, NULL if no dups. */
248 : /* Number of hard registers implicitly used/clobbered in given call
249 : insn. The value can be NULL or points to array of the hard
250 : register numbers ending with a negative value. To differ
251 : clobbered and used hard regs, clobbered hard regs are incremented
252 : by FIRST_PSEUDO_REGISTER. */
253 : int *arg_hard_regs;
254 : /* Cached value of get_preferred_alternatives. */
255 : alternative_mask preferred_alternatives;
256 : /* The following member value is always NULL for a debug insn. */
257 : struct lra_insn_reg *regs;
258 : };
259 :
260 : typedef class lra_insn_recog_data *lra_insn_recog_data_t;
261 :
262 : /* Whether the clobber is used temporary in LRA. */
263 : #define LRA_TEMP_CLOBBER_P(x) \
264 : (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging)
265 :
266 : /* Cost factor for each additional reload and maximal cost reject for
267 : insn reloads. One might ask about such strange numbers. Their
268 : values occurred historically from former reload pass. */
269 : #define LRA_LOSER_COST_FACTOR 6
270 : #define LRA_MAX_REJECT 600
271 :
272 : /* Maximum allowed number of assignment pass iterations after the
273 : latest spill pass when any former reload pseudo was spilled. It is
274 : for preventing LRA cycling in a bug case. */
275 : #define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30
276 :
277 : /* Maximum allowed number of tries to split hard reg live ranges after failure
278 : in assignment of reload pseudos. Theoretical bound for the value is the
279 : number of the insn reload pseudos plus the number of inheritance pseudos
280 : generated from the reload pseudos. This bound can be achieved when all the
281 : reload pseudos and the inheritance pseudos require hard reg splitting for
282 : their assignment. This is extremely unlikely event. */
283 : #define LRA_MAX_FAILED_SPLITS 10
284 :
285 : #if LRA_MAX_FAILED_SPLITS >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER
286 : #error wrong LRA_MAX_FAILED_SPLITS value
287 : #endif
288 :
289 : /* The maximal number of inheritance/split passes in LRA. It should
290 : be more 1 in order to perform caller saves transformations and much
291 : less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many
292 : as permitted constraint passes in some complicated cases. The
293 : first inheritance/split pass has a biggest impact on generated code
294 : quality. Each subsequent affects generated code in less degree.
295 : For example, the 3rd pass does not change generated SPEC2000 code
296 : at all on x86-64. */
297 : #define LRA_MAX_INHERITANCE_PASSES 2
298 :
299 : #if LRA_MAX_INHERITANCE_PASSES <= 0 \
300 : || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
301 : #error wrong LRA_MAX_INHERITANCE_PASSES value
302 : #endif
303 :
304 : /* Analogous macro to the above one but for rematerialization. */
305 : #define LRA_MAX_REMATERIALIZATION_PASSES 2
306 :
307 : #if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \
308 : || LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
309 : #error wrong LRA_MAX_REMATERIALIZATION_PASSES value
310 : #endif
311 :
312 : /* lra.cc: */
313 :
314 : extern FILE *lra_dump_file;
315 : extern int lra_verbose;
316 :
317 : extern bool lra_hard_reg_split_p;
318 : extern bool lra_asm_error_p;
319 : extern bool lra_reg_spill_p;
320 :
321 : extern HARD_REG_SET lra_no_alloc_regs;
322 :
323 : extern int lra_insn_recog_data_len;
324 : extern lra_insn_recog_data_t *lra_insn_recog_data;
325 :
326 : extern int lra_curr_reload_num;
327 :
328 : extern void lra_dump_bitmap_with_title (const char *, bitmap, int);
329 : extern hashval_t lra_rtx_hash (rtx x);
330 : extern void lra_push_insn (rtx_insn *);
331 : extern void lra_push_insn_by_uid (unsigned int);
332 : extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *);
333 : extern rtx_insn *lra_pop_insn (void);
334 : extern unsigned int lra_insn_stack_length (void);
335 :
336 : extern rtx lra_create_new_reg (machine_mode, rtx, enum reg_class, HARD_REG_SET *,
337 : const char *);
338 : extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx,
339 : enum reg_class, HARD_REG_SET *,
340 : const char *);
341 : extern void lra_set_regno_unique_value (int);
342 : extern void lra_invalidate_insn_data (rtx_insn *);
343 : extern void lra_set_insn_deleted (rtx_insn *);
344 : extern void lra_delete_dead_insn (rtx_insn *);
345 : extern void lra_emit_add (rtx, rtx, rtx);
346 : extern void lra_emit_move (rtx, rtx);
347 : extern void lra_update_dups (lra_insn_recog_data_t, signed char *);
348 : extern void lra_asm_insn_error (rtx_insn *insn);
349 :
350 : extern void lra_dump_insns (FILE *f);
351 : extern void lra_dump_insns_if_possible (const char *title);
352 :
353 : extern void lra_process_new_insns (rtx_insn *insn, rtx_insn *before,
354 : rtx_insn *after, const char *title,
355 : bool fixup_reg_args_size = false);
356 :
357 : extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool);
358 : extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool);
359 :
360 : extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *);
361 : extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *);
362 : extern void lra_set_used_insn_alternative (rtx_insn *, int);
363 : extern void lra_set_used_insn_alternative_by_uid (int, int);
364 :
365 : extern void lra_invalidate_insn_regno_info (rtx_insn *);
366 : extern void lra_update_insn_regno_info (rtx_insn *);
367 : extern struct lra_insn_reg *lra_get_insn_regs (int);
368 :
369 : extern void lra_free_copies (void);
370 : extern void lra_create_copy (int, int, int);
371 : extern lra_copy_t lra_get_copy (int);
372 :
373 : extern int lra_new_regno_start;
374 : extern int lra_constraint_new_regno_start;
375 : extern int lra_bad_spill_regno_start;
376 : extern rtx lra_pmode_pseudo;
377 : extern bitmap_head lra_inheritance_pseudos;
378 : extern bitmap_head lra_split_regs;
379 : extern bitmap_head lra_subreg_reload_pseudos;
380 : extern bitmap_head lra_optional_reload_pseudos;
381 : extern bitmap_head lra_postponed_insns;
382 :
383 : /* lra-constraints.cc: */
384 :
385 : extern void lra_init_equiv (void);
386 : extern void lra_pointer_equiv_set_add (rtx);
387 : extern bool lra_pointer_equiv_set_in (rtx);
388 : extern void lra_finish_equiv (void);
389 : extern int lra_constraint_offset (int, machine_mode);
390 :
391 : extern int lra_constraint_iter;
392 : extern bool check_and_force_assignment_correctness_p;
393 : extern int lra_inheritance_iter;
394 : extern int lra_undo_inheritance_iter;
395 : extern bool lra_constrain_insn (rtx_insn *);
396 : extern bool lra_constraints (bool);
397 : extern void lra_constraints_init (void);
398 : extern void lra_constraints_finish (void);
399 : extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *);
400 : extern void lra_inheritance (void);
401 : extern bool lra_undo_inheritance (void);
402 :
403 : /* lra-lives.cc: */
404 :
405 : extern int lra_live_max_point;
406 : extern int *lra_point_freq;
407 :
408 : extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER];
409 :
410 : extern int lra_live_range_iter;
411 : extern void lra_reset_live_range_list (lra_live_range_t &);
412 : extern void lra_create_live_ranges (bool, bool);
413 : extern bool lra_complete_live_ranges (void);
414 : extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t);
415 : extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t,
416 : lra_live_range_t);
417 : extern bool lra_intersected_live_ranges_p (lra_live_range_t,
418 : lra_live_range_t);
419 : extern void lra_print_live_range_list (FILE *, lra_live_range_t);
420 : extern void debug (lra_live_range &ref);
421 : extern void debug (lra_live_range *ptr);
422 : extern void lra_debug_live_range_list (lra_live_range_t);
423 : extern void lra_debug_pseudo_live_ranges (int);
424 : extern void lra_debug_live_ranges (void);
425 : extern void lra_clear_live_ranges (void);
426 : extern void lra_live_ranges_init (void);
427 : extern void lra_live_ranges_finish (void);
428 : extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int);
429 :
430 : /* lra-assigns.cc: */
431 :
432 : extern int lra_assignment_iter;
433 : extern int lra_assignment_iter_after_spill;
434 : extern void lra_setup_reg_renumber (int, int, bool);
435 : extern bool lra_assign (bool &);
436 : extern bool lra_split_hard_reg_for (bool fail_p);
437 :
438 : /* lra-coalesce.cc: */
439 :
440 : extern int lra_coalesce_iter;
441 : extern bool lra_coalesce (void);
442 :
443 : /* lra-spills.cc: */
444 :
445 : extern bool lra_need_for_scratch_reg_p (void);
446 : extern bool lra_need_for_spills_p (void);
447 : extern void lra_spill (void);
448 : extern void lra_final_code_change (void);
449 : extern void lra_recompute_slots_live_ranges (void);
450 :
451 : /* lra-remat.cc: */
452 :
453 : extern int lra_rematerialization_iter;
454 : extern bool lra_remat (void);
455 :
456 : /* lra-elimination.c: */
457 :
458 : extern void lra_debug_elim_table (void);
459 : extern int lra_get_elimination_hard_regno (int);
460 : extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode,
461 : bool, bool, poly_int64, bool);
462 : extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64);
463 : extern int lra_update_fp2sp_elimination (int *spilled_pseudos);
464 : extern bool lra_fp_pseudo_p (void);
465 : extern void lra_eliminate (bool, bool);
466 :
467 : extern poly_int64 lra_update_sp_offset (rtx, poly_int64);
468 : extern void lra_eliminate_reg_if_possible (rtx *);
469 :
470 :
471 :
472 : /* Return the hard register which given pseudo REGNO assigned to.
473 : Negative value means that the register got memory or we don't know
474 : allocation yet. */
475 : inline int
476 1055680372 : lra_get_regno_hard_regno (int regno)
477 : {
478 1055680372 : resize_reg_info ();
479 1055680372 : return reg_renumber[regno];
480 : }
481 :
482 : /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
483 : using TITLE. Output a new line if NL_P. */
484 : inline void
485 4061024 : lra_change_class (int regno, enum reg_class new_class,
486 : const char *title, bool nl_p)
487 : {
488 4061024 : lra_assert (regno >= FIRST_PSEUDO_REGISTER);
489 4061024 : if (lra_dump_file != NULL)
490 8 : fprintf (lra_dump_file, "%s class %s for r%d",
491 8 : title, reg_class_names[new_class], regno);
492 4061024 : setup_reg_classes (regno, new_class, NO_REGS, new_class);
493 4061024 : if (lra_dump_file != NULL && nl_p)
494 8 : fprintf (lra_dump_file, "\n");
495 4061024 : }
496 :
497 : /* Update insn operands which are duplication of NOP operand. The
498 : insn is represented by its LRA internal representation ID. */
499 : inline void
500 53821360 : lra_update_dup (lra_insn_recog_data_t id, int nop)
501 : {
502 53821360 : int i;
503 53821360 : struct lra_static_insn_data *static_id = id->insn_static_data;
504 :
505 56267836 : for (i = 0; i < static_id->n_dups; i++)
506 2446476 : if (static_id->dup_num[i] == nop)
507 915238 : *id->dup_loc[i] = *id->operand_loc[nop];
508 53821360 : }
509 :
510 : /* Process operator duplications in insn with ID. We do it after the
511 : operands processing. Generally speaking, we could do this probably
512 : simultaneously with operands processing because a common practice
513 : is to enumerate the operators after their operands. */
514 : inline void
515 8969212 : lra_update_operator_dups (lra_insn_recog_data_t id)
516 : {
517 8969212 : int i;
518 8969212 : struct lra_static_insn_data *static_id = id->insn_static_data;
519 :
520 9451834 : for (i = 0; i < static_id->n_dups; i++)
521 : {
522 482622 : int ndup = static_id->dup_num[i];
523 :
524 482622 : if (static_id->operand[ndup].is_operator)
525 5222 : *id->dup_loc[i] = *id->operand_loc[ndup];
526 : }
527 8969212 : }
528 :
529 : /* Return info about INSN. Set up the info if it is not done yet. */
530 : inline lra_insn_recog_data_t
531 1973002140 : lra_get_insn_recog_data (rtx_insn *insn)
532 : {
533 1973002140 : lra_insn_recog_data_t data;
534 1973002140 : unsigned int uid = INSN_UID (insn);
535 :
536 1973002140 : if (lra_insn_recog_data_len > (int) uid
537 1973002140 : && (data = lra_insn_recog_data[uid]) != NULL)
538 : {
539 : /* Check that we did not change insn without updating the insn
540 : info. */
541 1824180184 : lra_assert (data->insn == insn
542 : && (INSN_CODE (insn) < 0
543 : || data->icode == INSN_CODE (insn)));
544 : return data;
545 : }
546 148821956 : return lra_set_insn_recog_data (insn);
547 : }
548 :
549 : /* Update offset from pseudos with VAL by INCR. */
550 : inline void
551 3375748 : lra_update_reg_val_offset (int val, poly_int64 incr)
552 : {
553 3375748 : int i;
554 :
555 204223129 : for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
556 : {
557 200847381 : if (lra_reg_info[i].val == val)
558 200847381 : lra_reg_info[i].offset += incr;
559 : }
560 3375748 : }
561 :
562 : /* Return true if register content is equal to VAL with OFFSET. */
563 : inline bool
564 295259209 : lra_reg_val_equal_p (int regno, int val, poly_int64 offset)
565 : {
566 295259209 : if (lra_reg_info[regno].val == val
567 295259209 : && known_eq (lra_reg_info[regno].offset, offset))
568 944995 : return true;
569 :
570 : return false;
571 : }
572 :
573 : /* Assign value of register FROM to TO. */
574 : inline void
575 3386122 : lra_assign_reg_val (int from, int to)
576 : {
577 3386122 : lra_reg_info[to].val = lra_reg_info[from].val;
578 3386122 : lra_reg_info[to].offset = lra_reg_info[from].offset;
579 3386122 : }
580 :
581 : /* Update REGNO's biggest recorded mode so that it includes a reference
582 : in mode MODE. */
583 : inline void
584 632536101 : lra_update_biggest_mode (int regno, machine_mode mode)
585 : {
586 632536101 : if (!ordered_p (GET_MODE_SIZE (lra_reg_info[regno].biggest_mode),
587 632536101 : GET_MODE_SIZE (mode)))
588 : {
589 : gcc_checking_assert (HARD_REGISTER_NUM_P (regno));
590 : lra_reg_info[regno].biggest_mode = reg_raw_mode[regno];
591 : }
592 632536101 : else if (partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
593 56709891 : lra_reg_info[regno].biggest_mode = mode;
594 632536101 : }
595 :
596 : #endif /* GCC_LRA_INT_H */
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