Branch data Line data Source code
1 : : /* Change pseudos by memory.
2 : : Copyright (C) 2010-2025 Free Software Foundation, Inc.
3 : : Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4 : :
5 : : This file is part of GCC.
6 : :
7 : : GCC is free software; you can redistribute it and/or modify it under
8 : : the terms of the GNU General Public License as published by the Free
9 : : Software Foundation; either version 3, or (at your option) any later
10 : : version.
11 : :
12 : : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 : : WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 : : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 : : for more details.
16 : :
17 : : You should have received a copy of the GNU General Public License
18 : : along with GCC; see the file COPYING3. If not see
19 : : <http://www.gnu.org/licenses/>. */
20 : :
21 : :
22 : : /* This file contains code for a pass to change spilled pseudos into
23 : : memory.
24 : :
25 : : The pass creates necessary stack slots and assigns spilled pseudos
26 : : to the stack slots in following way:
27 : :
28 : : for all spilled pseudos P most frequently used first do
29 : : for all stack slots S do
30 : : if P doesn't conflict with pseudos assigned to S then
31 : : assign S to P and goto to the next pseudo process
32 : : end
33 : : end
34 : : create new stack slot S and assign P to S
35 : : end
36 : :
37 : : The actual algorithm is bit more complicated because of different
38 : : pseudo sizes.
39 : :
40 : : After that the code changes spilled pseudos (except ones created
41 : : from scratches) by corresponding stack slot memory in RTL.
42 : :
43 : : If at least one stack slot was created, we need to run more passes
44 : : because we have new addresses which should be checked and because
45 : : the old address displacements might change and address constraints
46 : : (or insn memory constraints) might not be satisfied any more.
47 : :
48 : : For some targets, the pass can spill some pseudos into hard
49 : : registers of different class (usually into vector registers)
50 : : instead of spilling them into memory if it is possible and
51 : : profitable. Spilling GENERAL_REGS pseudo into SSE registers for
52 : : Intel Corei7 is an example of such optimization. And this is
53 : : actually recommended by Intel optimization guide.
54 : :
55 : : The file also contains code for final change of pseudos on hard
56 : : regs correspondingly assigned to them. */
57 : :
58 : : #include "config.h"
59 : : #include "system.h"
60 : : #include "coretypes.h"
61 : : #include "backend.h"
62 : : #include "target.h"
63 : : #include "rtl.h"
64 : : #include "df.h"
65 : : #include "insn-config.h"
66 : : #include "regs.h"
67 : : #include "memmodel.h"
68 : : #include "ira.h"
69 : : #include "recog.h"
70 : : #include "output.h"
71 : : #include "cfgrtl.h"
72 : : #include "lra.h"
73 : : #include "lra-int.h"
74 : :
75 : :
76 : : /* Max regno at the start of the pass. */
77 : : static int regs_num;
78 : :
79 : : /* Map spilled regno -> hard regno used instead of memory for
80 : : spilling. */
81 : : static rtx *spill_hard_reg;
82 : :
83 : : /* The structure describes stack slot of a spilled pseudo. */
84 : : struct pseudo_slot
85 : : {
86 : : /* Number (0, 1, ...) of the stack slot to which given pseudo
87 : : belongs. */
88 : : int slot_num;
89 : : /* First or next slot with the same slot number. */
90 : : struct pseudo_slot *next, *first;
91 : : /* Memory representing the spilled pseudo. */
92 : : rtx mem;
93 : : };
94 : :
95 : : /* The stack slots for each spilled pseudo. Indexed by regnos. */
96 : : static struct pseudo_slot *pseudo_slots;
97 : :
98 : : /* The structure describes a register or a stack slot which can be
99 : : used for several spilled pseudos. */
100 : : class slot
101 : : {
102 : : public:
103 : : /* First pseudo with given stack slot. */
104 : : int regno;
105 : : /* Hard reg into which the slot pseudos are spilled. The value is
106 : : negative for pseudos spilled into memory. */
107 : : int hard_regno;
108 : : /* Maximum alignment required by all users of the slot. */
109 : : unsigned int align;
110 : : /* Maximum size required by all users of the slot. */
111 : : poly_int64 size;
112 : : /* Memory representing the all stack slot. It can be different from
113 : : memory representing a pseudo belonging to give stack slot because
114 : : pseudo can be placed in a part of the corresponding stack slot.
115 : : The value is NULL for pseudos spilled into a hard reg. */
116 : : rtx mem;
117 : : /* Combined live ranges of all pseudos belonging to given slot. It
118 : : is used to figure out that a new spilled pseudo can use given
119 : : stack slot. */
120 : : lra_live_range_t live_ranges;
121 : : };
122 : :
123 : : /* Array containing info about the stack slots. The array element is
124 : : indexed by the stack slot number in the range [0..slots_num). */
125 : : static class slot *slots;
126 : : /* The number of the stack slots currently existing. */
127 : : static int slots_num;
128 : :
129 : : /* Set up memory of the spilled pseudo I. The function can allocate
130 : : the corresponding stack slot if it is not done yet. */
131 : : static void
132 : 1426361 : assign_mem_slot (int i)
133 : : {
134 : 1426361 : rtx x = NULL_RTX;
135 : 1426361 : machine_mode mode = GET_MODE (regno_reg_rtx[i]);
136 : 2852722 : poly_int64 inherent_size = PSEUDO_REGNO_BYTES (i);
137 : 1426361 : machine_mode wider_mode
138 : 1426361 : = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode);
139 : 2852722 : poly_int64 total_size = GET_MODE_SIZE (wider_mode);
140 : 1426361 : poly_int64 adjust = 0;
141 : :
142 : 1426361 : lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i])
143 : : && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0);
144 : :
145 : 1426361 : unsigned int slot_num = pseudo_slots[i].slot_num;
146 : 1426361 : x = slots[slot_num].mem;
147 : 1426361 : if (!x)
148 : : {
149 : 1539754 : x = assign_stack_local (BLKmode, slots[slot_num].size,
150 : 769877 : slots[slot_num].align);
151 : 769877 : slots[slot_num].mem = x;
152 : : }
153 : :
154 : : /* On a big endian machine, the "address" of the slot is the address
155 : : of the low part that fits its inherent mode. */
156 : 1426361 : adjust += subreg_size_lowpart_offset (inherent_size, total_size);
157 : 1426361 : x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
158 : :
159 : : /* Set all of the memory attributes as appropriate for a spill. */
160 : 1426361 : set_mem_attrs_for_spill (x);
161 : 1426361 : pseudo_slots[i].mem = x;
162 : 1426361 : }
163 : :
164 : : /* Sort pseudos according their usage frequencies. */
165 : : static int
166 : 29781527 : regno_freq_compare (const void *v1p, const void *v2p)
167 : : {
168 : 29781527 : const int regno1 = *(const int *) v1p;
169 : 29781527 : const int regno2 = *(const int *) v2p;
170 : 29781527 : int diff;
171 : :
172 : 29781527 : if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0)
173 : : return diff;
174 : 11644518 : return regno1 - regno2;
175 : : }
176 : :
177 : : /* Sort pseudos according to their slots, putting the slots in the order
178 : : that they should be allocated.
179 : :
180 : : First prefer to group slots with variable sizes together and slots
181 : : with constant sizes together, since that usually makes them easier
182 : : to address from a common anchor point. E.g. loads of polynomial-sized
183 : : registers tend to take polynomial offsets while loads of constant-sized
184 : : registers tend to take constant (non-polynomial) offsets.
185 : :
186 : : Next, slots with lower numbers have the highest priority and should
187 : : get the smallest displacement from the stack or frame pointer
188 : : (whichever is being used).
189 : :
190 : : The first allocated slot is always closest to the frame pointer,
191 : : so prefer lower slot numbers when frame_pointer_needed. If the stack
192 : : and frame grow in the same direction, then the first allocated slot is
193 : : always closest to the initial stack pointer and furthest away from the
194 : : final stack pointer, so allocate higher numbers first when using the
195 : : stack pointer in that case. The reverse is true if the stack and
196 : : frame grow in opposite directions. */
197 : : static int
198 : 30200736 : pseudo_reg_slot_compare (const void *v1p, const void *v2p)
199 : : {
200 : 30200736 : const int regno1 = *(const int *) v1p;
201 : 30200736 : const int regno2 = *(const int *) v2p;
202 : 30200736 : int diff, slot_num1, slot_num2;
203 : :
204 : 30200736 : slot_num1 = pseudo_slots[regno1].slot_num;
205 : 30200736 : slot_num2 = pseudo_slots[regno2].slot_num;
206 : 30200736 : diff = (int (slots[slot_num1].size.is_constant ())
207 : 30200736 : - int (slots[slot_num2].size.is_constant ()));
208 : 30200736 : if (diff != 0)
209 : : return diff;
210 : 30200736 : if ((diff = slot_num1 - slot_num2) != 0)
211 : 22374311 : return (frame_pointer_needed
212 : 22374311 : || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff);
213 : 15652850 : poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode);
214 : 15652850 : poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode);
215 : 7826425 : if ((diff = compare_sizes_for_sort (total_size2, total_size1)) != 0)
216 : 1568056 : return diff;
217 : 6258369 : return regno1 - regno2;
218 : : }
219 : :
220 : : /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is
221 : : sorted in order of highest frequency first. Put the pseudos which
222 : : did not get a spill hard register at the beginning of array
223 : : PSEUDO_REGNOS. Return the number of such pseudos. */
224 : : static int
225 : 215785 : assign_spill_hard_regs (int *pseudo_regnos, int n)
226 : : {
227 : 215785 : int i, k, p, regno, res, spill_class_size, hard_regno, nr;
228 : 215785 : enum reg_class rclass, spill_class;
229 : 215785 : machine_mode mode;
230 : 215785 : lra_live_range_t r;
231 : 215785 : rtx_insn *insn;
232 : 215785 : rtx set;
233 : 215785 : basic_block bb;
234 : 215785 : HARD_REG_SET conflict_hard_regs;
235 : 215785 : bitmap setjump_crosses = regstat_get_setjmp_crosses ();
236 : : /* Hard registers which cannot be used for any purpose at given
237 : : program point because they are unallocatable or already allocated
238 : : for other pseudos. */
239 : 215785 : HARD_REG_SET *reserved_hard_regs;
240 : :
241 : 215785 : if (! lra_reg_spill_p)
242 : : return n;
243 : : /* Set up reserved hard regs for every program point. */
244 : 0 : reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point);
245 : 0 : for (p = 0; p < lra_live_max_point; p++)
246 : 0 : reserved_hard_regs[p] = lra_no_alloc_regs;
247 : 0 : for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
248 : 0 : if (lra_reg_info[i].nrefs != 0
249 : 0 : && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
250 : 0 : for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next)
251 : 0 : for (p = r->start; p <= r->finish; p++)
252 : 0 : add_to_hard_reg_set (&reserved_hard_regs[p],
253 : : lra_reg_info[i].biggest_mode, hard_regno);
254 : 0 : auto_bitmap ok_insn_bitmap (®_obstack);
255 : 0 : FOR_EACH_BB_FN (bb, cfun)
256 : 0 : FOR_BB_INSNS (bb, insn)
257 : 0 : if (DEBUG_INSN_P (insn)
258 : 0 : || ((set = single_set (insn)) != NULL_RTX
259 : 0 : && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))))
260 : 0 : bitmap_set_bit (ok_insn_bitmap, INSN_UID (insn));
261 : 0 : for (res = i = 0; i < n; i++)
262 : : {
263 : 0 : regno = pseudo_regnos[i];
264 : 0 : rclass = lra_get_allocno_class (regno);
265 : 0 : if (bitmap_bit_p (setjump_crosses, regno)
266 : 0 : || (spill_class
267 : 0 : = ((enum reg_class)
268 : 0 : targetm.spill_class ((reg_class_t) rclass,
269 : 0 : PSEUDO_REGNO_MODE (regno)))) == NO_REGS
270 : 0 : || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap,
271 : : ok_insn_bitmap))
272 : : {
273 : 0 : pseudo_regnos[res++] = regno;
274 : 0 : continue;
275 : : }
276 : 0 : lra_assert (spill_class != NO_REGS);
277 : 0 : conflict_hard_regs = lra_reg_info[regno].conflict_hard_regs;
278 : 0 : for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
279 : 0 : for (p = r->start; p <= r->finish; p++)
280 : 0 : conflict_hard_regs |= reserved_hard_regs[p];
281 : 0 : spill_class_size = ira_class_hard_regs_num[spill_class];
282 : 0 : mode = lra_reg_info[regno].biggest_mode;
283 : 0 : for (k = 0; k < spill_class_size; k++)
284 : : {
285 : 0 : hard_regno = ira_class_hard_regs[spill_class][k];
286 : 0 : if (TEST_HARD_REG_BIT (eliminable_regset, hard_regno)
287 : 0 : || !targetm.hard_regno_mode_ok (hard_regno, mode))
288 : 0 : continue;
289 : 0 : if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno))
290 : : break;
291 : : }
292 : 0 : if (k >= spill_class_size)
293 : : {
294 : : /* There is no available regs -- assign memory later. */
295 : 0 : pseudo_regnos[res++] = regno;
296 : 0 : continue;
297 : : }
298 : 0 : if (lra_dump_file != NULL)
299 : 0 : fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno);
300 : 0 : add_to_hard_reg_set (&hard_regs_spilled_into,
301 : 0 : lra_reg_info[regno].biggest_mode, hard_regno);
302 : : /* Update reserved_hard_regs. */
303 : 0 : for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
304 : 0 : for (p = r->start; p <= r->finish; p++)
305 : 0 : add_to_hard_reg_set (&reserved_hard_regs[p],
306 : : lra_reg_info[regno].biggest_mode, hard_regno);
307 : 0 : spill_hard_reg[regno]
308 : 0 : = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno);
309 : 0 : for (nr = 0;
310 : 0 : nr < hard_regno_nregs (hard_regno,
311 : 0 : lra_reg_info[regno].biggest_mode);
312 : : nr++)
313 : : /* Just loop. */
314 : 0 : df_set_regs_ever_live (hard_regno + nr, true);
315 : : }
316 : 0 : free (reserved_hard_regs);
317 : 0 : return res;
318 : 0 : }
319 : :
320 : : /* Add pseudo REGNO to slot SLOT_NUM. */
321 : : static void
322 : 1426361 : add_pseudo_to_slot (int regno, int slot_num)
323 : : {
324 : 1426361 : struct pseudo_slot *first;
325 : :
326 : : /* Each pseudo has an inherent size which comes from its own mode,
327 : : and a total size which provides room for paradoxical subregs.
328 : : We need to make sure the size and alignment of the slot are
329 : : sufficient for both. */
330 : 2852722 : machine_mode mode = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),
331 : 1426361 : lra_reg_info[regno].biggest_mode);
332 : 1426361 : unsigned int align = spill_slot_alignment (mode);
333 : 1426361 : slots[slot_num].align = MAX (slots[slot_num].align, align);
334 : 1426361 : slots[slot_num].size = upper_bound (slots[slot_num].size,
335 : 1426361 : GET_MODE_SIZE (mode));
336 : :
337 : 1426361 : if (slots[slot_num].regno < 0)
338 : : {
339 : : /* It is the first pseudo in the slot. */
340 : 769877 : slots[slot_num].regno = regno;
341 : 769877 : pseudo_slots[regno].first = &pseudo_slots[regno];
342 : 769877 : pseudo_slots[regno].next = NULL;
343 : : }
344 : : else
345 : : {
346 : 656484 : first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno];
347 : 656484 : pseudo_slots[regno].next = first->next;
348 : 656484 : first->next = &pseudo_slots[regno];
349 : : }
350 : 1426361 : pseudo_slots[regno].mem = NULL_RTX;
351 : 1426361 : pseudo_slots[regno].slot_num = slot_num;
352 : 1426361 : slots[slot_num].live_ranges
353 : 1426361 : = lra_merge_live_ranges (slots[slot_num].live_ranges,
354 : : lra_copy_live_range_list
355 : 1426361 : (lra_reg_info[regno].live_ranges));
356 : 1426361 : }
357 : :
358 : : /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of
359 : : length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning
360 : : memory stack slots. */
361 : : static void
362 : 215785 : assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n)
363 : : {
364 : 215785 : int i, j, regno;
365 : :
366 : : /* Assign stack slot numbers to spilled pseudos, use smaller numbers
367 : : for most frequently used pseudos. */
368 : 1642146 : for (i = 0; i < n; i++)
369 : : {
370 : 1426361 : regno = pseudo_regnos[i];
371 : 1426361 : if (! flag_ira_share_spill_slots)
372 : 27578 : j = slots_num;
373 : : else
374 : : {
375 : 1398783 : machine_mode mode
376 : 2797566 : = wider_subreg_mode (PSEUDO_REGNO_MODE (regno),
377 : 1398783 : lra_reg_info[regno].biggest_mode);
378 : 26189123 : for (j = 0; j < slots_num; j++)
379 : 25446824 : if (slots[j].hard_regno < 0
380 : : /* Although it's possible to share slots between modes
381 : : with constant and non-constant widths, we usually
382 : : get better spill code by keeping the constant and
383 : : non-constant areas separate. */
384 : 25446824 : && (GET_MODE_SIZE (mode).is_constant ()
385 : : == slots[j].size.is_constant ())
386 : 50893648 : && ! (lra_intersected_live_ranges_p
387 : 25446824 : (slots[j].live_ranges,
388 : 25446824 : lra_reg_info[regno].live_ranges)))
389 : : {
390 : : /* A slot without allocated memory can be shared. */
391 : 656484 : if (slots[j].mem == NULL_RTX)
392 : : break;
393 : :
394 : : /* A slot with allocated memory can be shared only with equal
395 : : or smaller register with equal or smaller alignment. */
396 : 0 : if (slots[j].align >= spill_slot_alignment (mode)
397 : 0 : && known_ge (slots[j].size, GET_MODE_SIZE (mode)))
398 : : break;
399 : : }
400 : : }
401 : 1426361 : if (j >= slots_num)
402 : : {
403 : : /* New slot. */
404 : 769877 : slots[j].live_ranges = NULL;
405 : 769877 : slots[j].size = 0;
406 : 769877 : slots[j].align = BITS_PER_UNIT;
407 : 769877 : slots[j].regno = slots[j].hard_regno = -1;
408 : 769877 : slots[j].mem = NULL_RTX;
409 : 769877 : slots_num++;
410 : : }
411 : 1426361 : add_pseudo_to_slot (regno, j);
412 : : }
413 : : /* Sort regnos according to their slot numbers. */
414 : 215785 : qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare);
415 : 215785 : }
416 : :
417 : : /* Recursively process LOC in INSN and change spilled pseudos to the
418 : : corresponding memory or spilled hard reg. Ignore spilled pseudos
419 : : created from the scratches. Return true if the pseudo nrefs equal
420 : : to 0 (don't change the pseudo in this case). Otherwise return false. */
421 : : static bool
422 : 33783397 : remove_pseudos (rtx *loc, rtx_insn *insn)
423 : : {
424 : 33783397 : int i;
425 : 33783397 : rtx hard_reg;
426 : 33783397 : const char *fmt;
427 : 33783397 : enum rtx_code code;
428 : 33783397 : bool res = false;
429 : :
430 : 33783397 : if (*loc == NULL_RTX)
431 : : return res;
432 : 31029162 : code = GET_CODE (*loc);
433 : 31029162 : if (code == SUBREG && REG_P (SUBREG_REG (*loc)))
434 : : {
435 : : /* Try to remove memory subregs to simplify LRA job
436 : : and avoid LRA cycling in case of subreg memory reload. */
437 : 273231 : res = remove_pseudos (&SUBREG_REG (*loc), insn);
438 : 273231 : if (GET_CODE (SUBREG_REG (*loc)) == MEM)
439 : : {
440 : 208730 : alter_subreg (loc, false);
441 : 208730 : if (GET_CODE (*loc) == MEM)
442 : : {
443 : 208730 : lra_update_insn_recog_data (insn);
444 : 208730 : if (lra_dump_file != NULL)
445 : 0 : fprintf (lra_dump_file,
446 : : "Memory subreg was simplified in insn #%u\n",
447 : 0 : INSN_UID (insn));
448 : : }
449 : : }
450 : 273231 : return res;
451 : : }
452 : 14301319 : else if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER
453 : 8646961 : && lra_get_regno_hard_regno (i) < 0
454 : : /* We do not want to assign memory for former scratches because
455 : : it might result in an address reload for some targets. In
456 : : any case we transform such pseudos not getting hard registers
457 : : into scratches back. */
458 : 35687949 : && ! ira_former_scratch_p (i))
459 : : {
460 : 4932018 : if (lra_reg_info[i].nrefs == 0
461 : 22923 : && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL)
462 : : return true;
463 : 4932018 : if ((hard_reg = spill_hard_reg[i]) != NULL_RTX)
464 : 0 : *loc = copy_rtx (hard_reg);
465 : 4932018 : else if (pseudo_slots[i].mem != NULL_RTX)
466 : : /* There might be no memory slot or hard reg for a pseudo when we spill
467 : : the frame pointer after elimination of frame pointer to stack
468 : : pointer became impossible. */
469 : : {
470 : 9864036 : rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem,
471 : 4932018 : GET_MODE (pseudo_slots[i].mem),
472 : 4932018 : false, false, 0, true);
473 : 4932018 : *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x);
474 : : }
475 : 4932018 : return res;
476 : : }
477 : :
478 : 25823913 : fmt = GET_RTX_FORMAT (code);
479 : 62285898 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
480 : : {
481 : 36461985 : if (fmt[i] == 'e')
482 : 25677711 : res = remove_pseudos (&XEXP (*loc, i), insn) || res;
483 : 10784274 : else if (fmt[i] == 'E')
484 : : {
485 : 101341 : int j;
486 : :
487 : 315604 : for (j = XVECLEN (*loc, i) - 1; j >= 0; j--)
488 : 214263 : res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res;
489 : : }
490 : : }
491 : : return res;
492 : : }
493 : :
494 : : /* Convert spilled pseudos into their stack slots or spill hard regs,
495 : : put insns to process on the constraint stack (that is all insns in
496 : : which pseudos were changed to memory or spill hard regs). */
497 : : static void
498 : 215785 : spill_pseudos (void)
499 : : {
500 : 215785 : basic_block bb;
501 : 215785 : rtx_insn *insn, *curr;
502 : 215785 : int i;
503 : :
504 : 215785 : auto_bitmap spilled_pseudos (®_obstack);
505 : 215785 : auto_bitmap changed_insns (®_obstack);
506 : 34924277 : for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
507 : : {
508 : 17857542 : if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
509 : 36138181 : && ! ira_former_scratch_p (i))
510 : : {
511 : 1426361 : bitmap_set_bit (spilled_pseudos, i);
512 : 1426361 : bitmap_ior_into (changed_insns, &lra_reg_info[i].insn_bitmap);
513 : : }
514 : : }
515 : 6824123 : FOR_EACH_BB_FN (bb, cfun)
516 : : {
517 : 194595312 : FOR_BB_INSNS_SAFE (bb, insn, curr)
518 : : {
519 : 90689318 : bool removed_pseudo_p = false;
520 : :
521 : 90689318 : if (bitmap_bit_p (changed_insns, INSN_UID (insn)))
522 : : {
523 : 4863957 : rtx *link_loc, link;
524 : :
525 : 4863957 : removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn);
526 : 4863957 : if (CALL_P (insn)
527 : 4863957 : && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
528 : : removed_pseudo_p = true;
529 : 4863957 : for (link_loc = ®_NOTES (insn);
530 : 8195064 : (link = *link_loc) != NULL_RTX;
531 : 3331107 : link_loc = &XEXP (link, 1))
532 : : {
533 : 3331107 : switch (REG_NOTE_KIND (link))
534 : : {
535 : 0 : case REG_FRAME_RELATED_EXPR:
536 : 0 : case REG_CFA_DEF_CFA:
537 : 0 : case REG_CFA_ADJUST_CFA:
538 : 0 : case REG_CFA_OFFSET:
539 : 0 : case REG_CFA_REGISTER:
540 : 0 : case REG_CFA_EXPRESSION:
541 : 0 : case REG_CFA_RESTORE:
542 : 0 : case REG_CFA_SET_VDRAP:
543 : 0 : if (remove_pseudos (&XEXP (link, 0), insn))
544 : 3331107 : removed_pseudo_p = true;
545 : : break;
546 : : default:
547 : : break;
548 : : }
549 : : }
550 : 4863957 : if (GET_CODE (PATTERN (insn)) == CLOBBER)
551 : : /* This is a CLOBBER insn with pseudo spilled to memory.
552 : : Mark it for removing it later together with LRA temporary
553 : : CLOBBER insns. */
554 : 8068 : LRA_TEMP_CLOBBER_P (PATTERN (insn)) = 1;
555 : 4863957 : if (lra_dump_file != NULL)
556 : 6 : fprintf (lra_dump_file,
557 : : "Changing spilled pseudos to memory in insn #%u\n",
558 : 6 : INSN_UID (insn));
559 : 4863957 : lra_push_insn (insn);
560 : 4863957 : if (lra_reg_spill_p || targetm.different_addr_displacement_p ())
561 : 0 : lra_set_used_insn_alternative (insn, LRA_UNKNOWN_ALT);
562 : : }
563 : 85825361 : else if (CALL_P (insn)
564 : : /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE
565 : : does not affect value of insn_bitmap of the
566 : : corresponding lra_reg_info. That is because we
567 : : don't need to reload pseudos in
568 : : CALL_INSN_FUNCTION_USAGEs. So if we process only
569 : : insns in the insn_bitmap of given pseudo here, we
570 : : can miss the pseudo in some
571 : : CALL_INSN_FUNCTION_USAGEs. */
572 : 85825361 : && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
573 : : removed_pseudo_p = true;
574 : 4863957 : if (removed_pseudo_p)
575 : : {
576 : 0 : lra_assert (DEBUG_INSN_P (insn));
577 : 0 : lra_invalidate_insn_data (insn);
578 : 0 : INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
579 : 0 : if (lra_dump_file != NULL)
580 : 0 : fprintf (lra_dump_file,
581 : : "Debug insn #%u is reset because it referenced "
582 : 0 : "removed pseudo\n", INSN_UID (insn));
583 : : }
584 : 90689318 : bitmap_and_compl_into (df_get_live_in (bb), spilled_pseudos);
585 : 90689318 : bitmap_and_compl_into (df_get_live_out (bb), spilled_pseudos);
586 : : }
587 : : }
588 : 215785 : }
589 : :
590 : : /* Return true if we need scratch reg assignments. */
591 : : bool
592 : 328 : lra_need_for_scratch_reg_p (void)
593 : : {
594 : 328 : int i; max_regno = max_reg_num ();
595 : :
596 : 17793 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
597 : 6504 : if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
598 : 17465 : && ira_former_scratch_p (i))
599 : : return true;
600 : : return false;
601 : : }
602 : :
603 : : /* Return true if we need to change some pseudos into memory. */
604 : : bool
605 : 1644963 : lra_need_for_spills_p (void)
606 : : {
607 : 1644963 : int i;
608 : :
609 : 1644963 : max_regno = max_reg_num ();
610 : 86716651 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
611 : 38871268 : if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
612 : 85512757 : && ! ira_former_scratch_p (i))
613 : : return true;
614 : : return false;
615 : : }
616 : :
617 : : /* Change spilled pseudos into memory or spill hard regs. Put changed
618 : : insns on the constraint stack (these insns will be considered on
619 : : the next constraint pass). The changed insns are all insns in
620 : : which pseudos were changed. */
621 : : void
622 : 215785 : lra_spill (void)
623 : : {
624 : 215785 : int i, n, n2, curr_regno;
625 : 215785 : int *pseudo_regnos;
626 : :
627 : 215785 : regs_num = max_reg_num ();
628 : 215785 : spill_hard_reg = XNEWVEC (rtx, regs_num);
629 : 215785 : pseudo_regnos = XNEWVEC (int, regs_num);
630 : 35140062 : for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
631 : 17857542 : if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
632 : : /* We do not want to assign memory for former scratches. */
633 : 36138181 : && ! ira_former_scratch_p (i))
634 : 1426361 : pseudo_regnos[n++] = i;
635 : 215785 : lra_assert (n > 0);
636 : 215785 : pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num);
637 : 34924277 : for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
638 : : {
639 : 34708492 : spill_hard_reg[i] = NULL_RTX;
640 : 34708492 : pseudo_slots[i].mem = NULL_RTX;
641 : : }
642 : 215785 : slots = XNEWVEC (class slot, regs_num);
643 : : /* Sort regnos according their usage frequencies. */
644 : 215785 : qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare);
645 : 215785 : n = assign_spill_hard_regs (pseudo_regnos, n);
646 : 215785 : slots_num = 0;
647 : 215785 : assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n);
648 : 1857931 : for (i = 0; i < n; i++)
649 : 1426361 : if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
650 : 1426361 : assign_mem_slot (pseudo_regnos[i]);
651 : 215785 : if ((n2 = lra_update_fp2sp_elimination (pseudo_regnos)) > 0)
652 : : {
653 : : /* Assign stack slots to spilled pseudos assigned to fp. */
654 : 0 : assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n2);
655 : 0 : for (i = 0; i < n2; i++)
656 : 0 : if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
657 : 0 : assign_mem_slot (pseudo_regnos[i]);
658 : : }
659 : 215785 : if (n + n2 > 0 && crtl->stack_alignment_needed)
660 : : /* If we have a stack frame, we must align it now. The stack size
661 : : may be a part of the offset computation for register
662 : : elimination. */
663 : 215785 : assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
664 : 215785 : if (lra_dump_file != NULL)
665 : : {
666 : 3 : for (i = 0; i < slots_num; i++)
667 : : {
668 : 2 : fprintf (lra_dump_file, " Slot %d regnos (width = ", i);
669 : 2 : print_dec (slots[i].size, lra_dump_file, SIGNED);
670 : 2 : fprintf (lra_dump_file, "):");
671 : 2 : for (curr_regno = slots[i].regno;;
672 : 0 : curr_regno = pseudo_slots[curr_regno].next - pseudo_slots)
673 : : {
674 : 2 : fprintf (lra_dump_file, " %d", curr_regno);
675 : 2 : if (pseudo_slots[curr_regno].next == NULL)
676 : : break;
677 : : }
678 : 2 : fprintf (lra_dump_file, "\n");
679 : : }
680 : : }
681 : 215785 : spill_pseudos ();
682 : 215785 : free (slots);
683 : 215785 : free (pseudo_slots);
684 : 215785 : free (pseudo_regnos);
685 : 215785 : free (spill_hard_reg);
686 : 215785 : }
687 : :
688 : : /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for
689 : : alter_subreg calls. Return true if any subreg of reg is
690 : : processed. */
691 : : static bool
692 : 326308400 : alter_subregs (rtx *loc, bool final_p)
693 : : {
694 : 326308400 : int i;
695 : 326308400 : rtx x = *loc;
696 : 326308400 : bool res;
697 : 326308400 : const char *fmt;
698 : 326308400 : enum rtx_code code;
699 : :
700 : 326308400 : if (x == NULL_RTX)
701 : : return false;
702 : 326308400 : code = GET_CODE (x);
703 : 326308400 : if (code == SUBREG && REG_P (SUBREG_REG (x)))
704 : : {
705 : 2939100 : lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER);
706 : 2939100 : alter_subreg (loc, final_p);
707 : 2939100 : return true;
708 : : }
709 : 323369300 : fmt = GET_RTX_FORMAT (code);
710 : 323369300 : res = false;
711 : 775750169 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
712 : : {
713 : 452380869 : if (fmt[i] == 'e')
714 : : {
715 : 110895130 : if (alter_subregs (&XEXP (x, i), final_p))
716 : 452380869 : res = true;
717 : : }
718 : 341485739 : else if (fmt[i] == 'E')
719 : : {
720 : 471295 : int j;
721 : :
722 : 2142379 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
723 : 1671084 : if (alter_subregs (&XVECEXP (x, i, j), final_p))
724 : 417 : res = true;
725 : : }
726 : : }
727 : : return res;
728 : : }
729 : :
730 : : /* Final change of pseudos got hard registers into the corresponding
731 : : hard registers and removing temporary clobbers. */
732 : : void
733 : 1427236 : lra_final_code_change (void)
734 : : {
735 : 1427236 : int i, hard_regno;
736 : 1427236 : basic_block bb;
737 : 1427236 : rtx_insn *insn, *curr;
738 : 1427236 : rtx set;
739 : 1427236 : int max_regno = max_reg_num ();
740 : :
741 : 75277045 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
742 : 72422573 : if (lra_reg_info[i].nrefs != 0
743 : 106194632 : && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
744 : 33766739 : SET_REGNO (regno_reg_rtx[i], hard_regno);
745 : 15090845 : FOR_EACH_BB_FN (bb, cfun)
746 : 340815604 : FOR_BB_INSNS_SAFE (bb, insn, curr)
747 : 156744193 : if (INSN_P (insn))
748 : : {
749 : 129827201 : rtx pat = PATTERN (insn);
750 : :
751 : 129827201 : if (GET_CODE (pat) == USE && XEXP (pat, 0) == const1_rtx)
752 : : {
753 : : /* Remove markers to eliminate critical edges for jump insn
754 : : output reloads (see code in ira.cc::ira). */
755 : 11 : lra_invalidate_insn_data (insn);
756 : 11 : delete_insn (insn);
757 : 11 : continue;
758 : : }
759 : 129827190 : if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
760 : : {
761 : : /* Remove clobbers temporarily created in LRA. We don't
762 : : need them anymore and don't want to waste compiler
763 : : time processing them in a few subsequent passes. */
764 : 135441 : lra_invalidate_insn_data (insn);
765 : 135441 : delete_insn (insn);
766 : 135441 : continue;
767 : : }
768 : :
769 : : /* IRA can generate move insns involving pseudos. It is
770 : : better remove them earlier to speed up compiler a bit.
771 : : It is also better to do it here as they might not pass
772 : : final RTL check in LRA, (e.g. insn moving a control
773 : : register into itself). So remove an useless move insn
774 : : unless next insn is USE marking the return reg (we should
775 : : save this as some subsequent optimizations assume that
776 : : such original insns are saved). */
777 : 75306210 : if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET
778 : 63783513 : && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat))
779 : 16530717 : && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat))
780 : 139943029 : && REGNO (SET_SRC (pat)) >= FIRST_PSEUDO_REGISTER)
781 : : {
782 : 0 : lra_invalidate_insn_data (insn);
783 : 0 : delete_insn (insn);
784 : 0 : continue;
785 : : }
786 : :
787 : 129691749 : lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
788 : 129691749 : struct lra_insn_reg *reg;
789 : :
790 : 275482888 : for (reg = id->regs; reg != NULL; reg = reg->next)
791 : 145791392 : if (reg->regno >= FIRST_PSEUDO_REGISTER
792 : 95516786 : && lra_reg_info [reg->regno].nrefs == 0)
793 : : break;
794 : :
795 : 129691749 : if (reg != NULL)
796 : : {
797 : : /* Pseudos still can be in debug insns in some very rare
798 : : and complicated cases, e.g. the pseudo was removed by
799 : : inheritance and the debug insn is not EBBs where the
800 : : inheritance happened. It is difficult and time
801 : : consuming to find what hard register corresponds the
802 : : pseudo -- so just remove the debug insn. Another
803 : : solution could be assigning hard reg/memory but it
804 : : would be a misleading info. It is better not to have
805 : : info than have it wrong. */
806 : 253 : lra_assert (DEBUG_INSN_P (insn));
807 : 253 : lra_invalidate_insn_data (insn);
808 : 253 : delete_insn (insn);
809 : 253 : continue;
810 : : }
811 : :
812 : 129691496 : struct lra_static_insn_data *static_id = id->insn_static_data;
813 : 129691496 : bool insn_change_p = false;
814 : :
815 : 349696098 : for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
816 : 189595754 : if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
817 : 402561532 : && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
818 : : {
819 : 2937391 : lra_update_dup (id, i);
820 : 2937391 : insn_change_p = true;
821 : : }
822 : 129691496 : if ((GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
823 : 129691496 : && alter_subregs (&XEXP (pat, 0), false))
824 : : insn_change_p = true;
825 : 129691496 : if (insn_change_p)
826 : 2601741 : lra_update_operator_dups (id);
827 : :
828 : 129691496 : if ((set = single_set (insn)) != NULL
829 : 84254262 : && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
830 : 147228409 : && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set)))
831 : : {
832 : : /* Remove an useless move insn. IRA can generate move
833 : : insns involving pseudos. It is better remove them
834 : : earlier to speed up compiler a bit. It is also
835 : : better to do it here as they might not pass final RTL
836 : : check in LRA, (e.g. insn moving a control register
837 : : into itself). */
838 : 10581093 : lra_invalidate_insn_data (insn);
839 : 10581093 : delete_insn (insn);
840 : : }
841 : : }
842 : 1427236 : }
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