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1 : : // Implementation of instruction-related RTL SSA functions -*- C++ -*-
2 : : // Copyright (C) 2020-2024 Free Software Foundation, Inc.
3 : : //
4 : : // This file is part of GCC.
5 : : //
6 : : // GCC is free software; you can redistribute it and/or modify it under
7 : : // the terms of the GNU General Public License as published by the Free
8 : : // Software Foundation; either version 3, or (at your option) any later
9 : : // version.
10 : : //
11 : : // GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : : // WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : : // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : : // for more details.
15 : : //
16 : : // You should have received a copy of the GNU General Public License
17 : : // along with GCC; see the file COPYING3. If not see
18 : : // <http://www.gnu.org/licenses/>.
19 : :
20 : : #define INCLUDE_ALGORITHM
21 : : #define INCLUDE_FUNCTIONAL
22 : : #include "config.h"
23 : : #include "system.h"
24 : : #include "coretypes.h"
25 : : #include "backend.h"
26 : : #include "rtl.h"
27 : : #include "df.h"
28 : : #include "rtl-ssa.h"
29 : : #include "rtl-ssa/internals.h"
30 : : #include "rtl-ssa/internals.inl"
31 : : #include "predict.h"
32 : : #include "print-rtl.h"
33 : : #include "rtl-iter.h"
34 : :
35 : : using namespace rtl_ssa;
36 : :
37 : : // The gap to leave between program points when building up the list
38 : : // of instructions for the first time. Using 2 allows an instruction
39 : : // to be inserted between two others without resorting to splay tree
40 : : // ordering. Using 0 is useful as a debugging aid to stress the
41 : : // splay tree code.
42 : : static const unsigned int POINT_INCREASE = 2;
43 : :
44 : : // Calculate and record the cost of the instruction, based on the
45 : : // form it had before any in-progress changes were made.
46 : : void
47 : 0 : insn_info::calculate_cost () const
48 : : {
49 : 0 : basic_block cfg_bb = BLOCK_FOR_INSN (m_rtl);
50 : 0 : temporarily_undo_changes (0);
51 : 0 : m_cost_or_uid = insn_cost (m_rtl, optimize_bb_for_speed_p (cfg_bb));
52 : 0 : redo_changes (0);
53 : 0 : }
54 : :
55 : : // Add NOTE to the instruction's notes.
56 : : void
57 : 8324577 : insn_info::add_note (insn_note *note)
58 : : {
59 : 8324577 : insn_note **ptr = &m_first_note;
60 : : // Always put the order node first, since it's the one that's likely
61 : : // to be used most often.
62 : 8324577 : if (*ptr && (*ptr)->kind () == insn_note_kind::ORDER_NODE)
63 : 0 : ptr = &(*ptr)->m_next_note;
64 : 8324577 : note->m_next_note = *ptr;
65 : 8324577 : *ptr = note;
66 : 8324577 : }
67 : :
68 : : // Implement compare_with for the case in which this insn and OTHER
69 : : // have the same program point.
70 : : int
71 : 0 : insn_info::slow_compare_with (const insn_info &other) const
72 : : {
73 : 0 : return order_splay_tree::compare_nodes (get_known_order_node (),
74 : 0 : other.get_known_order_node ());
75 : : }
76 : :
77 : : // Print insn uid UID to PP, where UID has the same form as insn_info::uid.
78 : : void
79 : 0 : insn_info::print_uid (pretty_printer *pp, int uid)
80 : : {
81 : 0 : char tmp[3 * sizeof (uid) + 2];
82 : 0 : if (uid < 0)
83 : : // An artificial instruction.
84 : 0 : snprintf (tmp, sizeof (tmp), "a%d", -uid);
85 : : else
86 : : // A real RTL instruction.
87 : 0 : snprintf (tmp, sizeof (tmp), "i%d", uid);
88 : 0 : pp_string (pp, tmp);
89 : 0 : }
90 : :
91 : : // See comment above declaration.
92 : : void
93 : 0 : insn_info::print_identifier (pretty_printer *pp) const
94 : : {
95 : 0 : print_uid (pp, uid ());
96 : 0 : }
97 : :
98 : : // See comment above declaration.
99 : : void
100 : 0 : insn_info::print_location (pretty_printer *pp) const
101 : : {
102 : 0 : if (bb_info *bb = this->bb ())
103 : : {
104 : 0 : ebb_info *ebb = bb->ebb ();
105 : 0 : if (ebb && is_phi ())
106 : 0 : ebb->print_identifier (pp);
107 : : else
108 : 0 : bb->print_identifier (pp);
109 : 0 : pp_string (pp, " at point ");
110 : 0 : pp_decimal_int (pp, m_point);
111 : : }
112 : : else
113 : 0 : pp_string (pp, "<unknown location>");
114 : 0 : }
115 : :
116 : : // See comment above declaration.
117 : : void
118 : 0 : insn_info::print_identifier_and_location (pretty_printer *pp) const
119 : : {
120 : 0 : if (m_is_asm)
121 : 0 : pp_string (pp, "asm ");
122 : 0 : if (m_is_debug_insn)
123 : 0 : pp_string (pp, "debug ");
124 : 0 : pp_string (pp, "insn ");
125 : 0 : print_identifier (pp);
126 : 0 : pp_string (pp, " in ");
127 : 0 : print_location (pp);
128 : 0 : }
129 : :
130 : : // See comment above declaration.
131 : : void
132 : 0 : insn_info::print_full (pretty_printer *pp) const
133 : : {
134 : 0 : print_identifier_and_location (pp);
135 : 0 : pp_colon (pp);
136 : 0 : if (is_real ())
137 : : {
138 : 0 : pp_newline_and_indent (pp, 2);
139 : 0 : if (has_been_deleted ())
140 : 0 : pp_string (pp, "deleted");
141 : : else
142 : : {
143 : : // Print the insn pattern to a temporary printer.
144 : 0 : pretty_printer sub_pp;
145 : 0 : print_insn_with_notes (&sub_pp, rtl ());
146 : 0 : const char *text = pp_formatted_text (&sub_pp);
147 : :
148 : : // Calculate the length of the maximum line in the pattern.
149 : 0 : unsigned int max_len = 0;
150 : 0 : const char *start = text;
151 : 0 : while (const char *end = strchr (start, '\n'))
152 : : {
153 : 0 : max_len = MAX (max_len, (unsigned int) (end - start));
154 : 0 : start = end + 1;
155 : 0 : }
156 : :
157 : : // Print a separator before or after the pattern.
158 : 0 : auto print_top_bottom = [&]()
159 : : {
160 : 0 : pp_character (pp, '+');
161 : 0 : for (unsigned int i = 0; i < max_len + 2; ++i)
162 : 0 : pp_character (pp, '-');
163 : 0 : };
164 : :
165 : 0 : print_top_bottom ();
166 : 0 : start = text;
167 : 0 : while (const char *end = strchr (start, '\n'))
168 : : {
169 : 0 : pp_newline_and_indent (pp, 0);
170 : 0 : pp_character (pp, '|');
171 : : // Each line of the pattern already starts with a space.
172 : : // so we don't need to add another one here.
173 : 0 : pp_append_text (pp, start, end);
174 : 0 : start = end + 1;
175 : 0 : }
176 : 0 : pp_newline_and_indent (pp, 0);
177 : 0 : print_top_bottom ();
178 : :
179 : 0 : if (m_cost_or_uid != UNKNOWN_COST)
180 : : {
181 : 0 : pp_newline_and_indent (pp, 0);
182 : 0 : pp_string (pp, "cost: ");
183 : 0 : pp_decimal_int (pp, m_cost_or_uid);
184 : : }
185 : 0 : if (m_has_pre_post_modify)
186 : : {
187 : 0 : pp_newline_and_indent (pp, 0);
188 : 0 : pp_string (pp, "has pre/post-modify operations");
189 : : }
190 : 0 : if (m_has_volatile_refs)
191 : : {
192 : 0 : pp_newline_and_indent (pp, 0);
193 : 0 : pp_string (pp, "has volatile refs");
194 : : }
195 : 0 : if (m_is_temp)
196 : : {
197 : 0 : pp_newline_and_indent (pp, 0);
198 : 0 : pp_string (pp, "temporary");
199 : : }
200 : 0 : }
201 : 0 : pp_indentation (pp) -= 2;
202 : : }
203 : :
204 : 0 : auto print_accesses = [&](const char *heading, access_array accesses,
205 : : unsigned int flags)
206 : : {
207 : 0 : if (!accesses.empty ())
208 : : {
209 : 0 : pp_newline_and_indent (pp, 2);
210 : 0 : pp_string (pp, heading);
211 : 0 : pp_newline_and_indent (pp, 2);
212 : 0 : pp_accesses (pp, accesses, flags);
213 : 0 : pp_indentation (pp) -= 4;
214 : : }
215 : 0 : };
216 : :
217 : 0 : print_accesses ("uses:", uses (), PP_ACCESS_USER);
218 : 0 : auto *call_clobbers_note = find_note<insn_call_clobbers_note> ();
219 : 0 : if (call_clobbers_note)
220 : : {
221 : 0 : pp_newline_and_indent (pp, 2);
222 : 0 : pp_string (pp, "has call clobbers for ABI ");
223 : 0 : pp_decimal_int (pp, call_clobbers_note->abi_id ());
224 : 0 : pp_indentation (pp) -= 2;
225 : : }
226 : 0 : print_accesses ("defines:", defs (), PP_ACCESS_SETTER);
227 : 0 : if (num_uses () == 0 && !call_clobbers_note && num_defs () == 0)
228 : : {
229 : 0 : pp_newline_and_indent (pp, 2);
230 : 0 : pp_string (pp, "has no uses or defs");
231 : 0 : pp_indentation (pp) -= 2;
232 : : }
233 : :
234 : 0 : if (order_node *node = get_order_node ())
235 : : {
236 : 0 : while (node->m_parent)
237 : : node = node->m_parent;
238 : :
239 : 0 : pp_newline_and_indent (pp, 2);
240 : 0 : pp_string (pp, "insn order: ");
241 : 0 : pp_newline_and_indent (pp, 2);
242 : 0 : auto print_order = [](pretty_printer *pp, order_node *node)
243 : : {
244 : 0 : print_uid (pp, node->uid ());
245 : : };
246 : 0 : order_splay_tree::print (pp, node, print_order);
247 : 0 : pp_indentation (pp) -= 4;
248 : : }
249 : 0 : }
250 : :
251 : : // Return an insn_info::order_node for INSN, creating one if necessary.
252 : : insn_info::order_node *
253 : 0 : function_info::need_order_node (insn_info *insn)
254 : : {
255 : 0 : insn_info::order_node *order = insn->get_order_node ();
256 : 0 : if (!order)
257 : : {
258 : 0 : order = allocate<insn_info::order_node> (insn->uid ());
259 : 0 : insn->add_note (order);
260 : : }
261 : 0 : return order;
262 : : }
263 : :
264 : : // Add instruction INSN immediately after AFTER in the reverse postorder list.
265 : : // INSN is not currently in the list.
266 : : void
267 : 249260047 : function_info::add_insn_after (insn_info *insn, insn_info *after)
268 : : {
269 : 249260047 : gcc_checking_assert (!insn->has_insn_links ());
270 : :
271 : 249260047 : insn->copy_next_from (after);
272 : 249260047 : after->set_next_any_insn (insn);
273 : :
274 : : // The prev link is easy if AFTER and INSN are the same type.
275 : : // Handle the other cases below.
276 : 249260047 : if (after->is_debug_insn () == insn->is_debug_insn ())
277 : 223749739 : insn->set_prev_sametype_insn (after);
278 : :
279 : 249260047 : if (insn_info *next = insn->next_any_insn ())
280 : : {
281 : 0 : if (insn->is_debug_insn () == next->is_debug_insn ())
282 : : {
283 : : // INSN might now be the start of the subsequence of debug insns,
284 : : // and so its prev pointer might point to the end of the subsequence
285 : : // instead of AFTER.
286 : 0 : insn->copy_prev_from (next);
287 : 0 : next->set_prev_sametype_insn (insn);
288 : : }
289 : 0 : else if (insn->is_debug_insn ()) // && !next->is_debug_insn ()
290 : : {
291 : : // INSN ends a subsequence of debug instructions. Find the
292 : : // first debug instruction in the subsequence, which might
293 : : // be INSN itself. (If it isn't, then AFTER is also a debug
294 : : // instruction and we updated INSN's prev link above.)
295 : 0 : insn_info *first = next->prev_nondebug_insn ()->next_any_insn ();
296 : 0 : first->set_last_debug_insn (insn);
297 : : }
298 : : else // !insn->is_debug_insn () && next->is_debug_insn ()
299 : : {
300 : : // At present we don't (need to) support inserting a nondebug
301 : : // instruction between two existing debug instructions.
302 : 0 : gcc_assert (!after->is_debug_insn ());
303 : :
304 : : // Find the next nondebug insn and update its previous pointer
305 : : // to point to INSN.
306 : 0 : auto next_nondebug = next->last_debug_insn ()->next_any_insn ();
307 : 0 : gcc_checking_assert (!next_nondebug->is_debug_insn ());
308 : 0 : next_nondebug->set_prev_sametype_insn (insn);
309 : : }
310 : :
311 : : // If AFTER and NEXT are separated by at least two points, we can
312 : : // use a unique point number for INSN. Otherwise INSN will have
313 : : // the same point number as AFTER.
314 : 0 : insn->set_point ((next->point () + after->point ()) / 2);
315 : : }
316 : : else
317 : : {
318 : 249260047 : if (!insn->is_debug_insn ())
319 : : {
320 : 172853942 : insn->set_prev_sametype_insn (m_last_nondebug_insn);
321 : 172853942 : m_last_nondebug_insn = insn;
322 : : }
323 : : else
324 : : // There is now at least one debug instruction after
325 : : // m_last_nondebug_insn: either INSN itself, or the start of
326 : : // a longer subsequence of debug insns that now ends with AFTER
327 : : // followed by INSN.
328 : 152812210 : m_last_nondebug_insn->next_any_insn ()->set_last_debug_insn (insn);
329 : 249260047 : m_last_insn = insn;
330 : :
331 : 249260047 : insn->set_point (after->point () + POINT_INCREASE);
332 : : }
333 : :
334 : : // If INSN's program point is the same as AFTER's, we need to use the
335 : : // splay tree to record their relative order.
336 : 249260047 : if (insn->point () == after->point ())
337 : : {
338 : 0 : insn_info::order_node *after_node = need_order_node (after);
339 : 0 : insn_info::order_node *insn_node = need_order_node (insn);
340 : 0 : insn_info::order_splay_tree::insert_child (after_node, 1, insn_node);
341 : : }
342 : 249260047 : }
343 : :
344 : : // Remove INSN from the function's list of instructions.
345 : : void
346 : 0 : function_info::remove_insn (insn_info *insn)
347 : : {
348 : 0 : if (insn_info::order_node *order = insn->get_order_node ())
349 : 0 : insn_info::order_splay_tree::remove_node (order);
350 : :
351 : 0 : if (auto *note = insn->find_note<insn_call_clobbers_note> ())
352 : : {
353 : 0 : ebb_call_clobbers_info *ecc = insn->ebb ()->first_call_clobbers ();
354 : 0 : while (ecc->abi ()->id () != note->abi_id ())
355 : 0 : ecc = ecc->next ();
356 : 0 : int comparison = lookup_call_clobbers (*ecc, insn);
357 : 0 : gcc_assert (comparison == 0);
358 : 0 : ecc->remove_root ();
359 : : }
360 : :
361 : 0 : insn_info *prev = insn->prev_any_insn ();
362 : 0 : insn_info *next = insn->next_any_insn ();
363 : 0 : insn_info *prev_nondebug = insn->prev_nondebug_insn ();
364 : 0 : insn_info *next_nondebug = insn->next_nondebug_insn ();
365 : :
366 : : // We should never remove the entry or exit block's instructions.
367 : : // At present we also don't remove entire blocks, so should never
368 : : // remove debug instructions.
369 : 0 : gcc_checking_assert (prev_nondebug
370 : : && next_nondebug
371 : : && !insn->is_debug_insn ());
372 : :
373 : 0 : if (prev->is_debug_insn () && next->is_debug_insn ())
374 : : {
375 : : // We need to stitch together two subsequences of debug insns.
376 : 0 : insn_info *last = next->last_debug_insn ();
377 : 0 : next->set_prev_sametype_insn (prev);
378 : 0 : prev_nondebug->next_any_insn ()->set_last_debug_insn (last);
379 : : }
380 : 0 : prev->set_next_any_insn (next);
381 : 0 : next_nondebug->set_prev_sametype_insn (prev_nondebug);
382 : :
383 : 0 : insn->clear_insn_links ();
384 : 0 : }
385 : :
386 : : // Create an artificial instruction for BB, associating it with RTL (which can
387 : : // be null). Add the new instruction to the end of the function's list and
388 : : // return the new instruction.
389 : : insn_info *
390 : 60973283 : function_info::append_artificial_insn (bb_info *bb, rtx_insn *rtl)
391 : : {
392 : 60973283 : insn_info *insn = allocate<insn_info> (bb, rtl, m_next_artificial_uid);
393 : 60973283 : m_next_artificial_uid -= 1;
394 : 60973283 : append_insn (insn);
395 : 60973283 : return insn;
396 : : }
397 : :
398 : : // Finish building a new list of uses and definitions for instruction INSN.
399 : : void
400 : 234538710 : function_info::finish_insn_accesses (insn_info *insn)
401 : : {
402 : 234538710 : unsigned int num_defs = m_temp_defs.length ();
403 : 234538710 : unsigned int num_uses = m_temp_uses.length ();
404 : 234538710 : obstack_make_room (&m_obstack, num_defs + num_uses);
405 : 234538710 : if (num_defs)
406 : : {
407 : 105802705 : sort_accesses (m_temp_defs);
408 : 105802705 : obstack_grow (&m_obstack, m_temp_defs.address (),
409 : : num_defs * sizeof (access_info *));
410 : 105802705 : m_temp_defs.truncate (0);
411 : : }
412 : 234538710 : if (num_uses)
413 : : {
414 : 136754509 : sort_accesses (m_temp_uses);
415 : 136754509 : obstack_grow (&m_obstack, m_temp_uses.address (),
416 : : num_uses * sizeof (access_info *));
417 : 136754509 : m_temp_uses.truncate (0);
418 : : }
419 : 234538710 : void *addr = obstack_finish (&m_obstack);
420 : 234538710 : insn->set_accesses (static_cast<access_info **> (addr), num_defs, num_uses);
421 : 234538710 : }
422 : :
423 : : // Called while building SSA form using BI. Create and return a use of
424 : : // register RESOURCE in INSN. Create a degenerate phi where necessary.
425 : : use_info *
426 : 255105864 : function_info::create_reg_use (build_info &bi, insn_info *insn,
427 : : resource_info resource)
428 : : {
429 : 255105864 : set_info *value = bi.current_reg_value (resource.regno);
430 : 255105864 : if (value && value->ebb () != bi.current_ebb)
431 : : {
432 : 122637272 : if (insn->is_debug_insn ())
433 : 7759000 : value = look_through_degenerate_phi (value);
434 : 114878272 : else if (bitmap_bit_p (bi.potential_phi_regs, resource.regno))
435 : : {
436 : : // VALUE is defined by a previous EBB and RESOURCE has multiple
437 : : // definitions. Create a degenerate phi in the current EBB
438 : : // so that all definitions and uses follow a linear RPO view;
439 : : // see rtl.texi for details.
440 : 9176271 : access_info *inputs[] = { look_through_degenerate_phi (value) };
441 : 9176271 : value = create_phi (bi.current_ebb, value->resource (), inputs, 1);
442 : 9176271 : bi.record_reg_def (value);
443 : : }
444 : : }
445 : 255105864 : auto *use = allocate<use_info> (insn, resource, value);
446 : 255105864 : add_use (use);
447 : 255105864 : return use;
448 : : }
449 : :
450 : : // Called while building SSA form using BI. Record that INSN contains
451 : : // read reference REF. If this requires new entries to be added to
452 : : // INSN->uses (), add those entries to the list we're building in
453 : : // m_temp_uses.
454 : : void
455 : 186956472 : function_info::record_use (build_info &bi, insn_info *insn,
456 : : rtx_obj_reference ref)
457 : : {
458 : 186956472 : unsigned int regno = ref.regno;
459 : 186956472 : machine_mode mode = ref.is_reg () ? ref.mode : BLKmode;
460 : 186956472 : access_info *access = bi.last_access[ref.regno + 1];
461 : 186956472 : use_info *use = safe_dyn_cast<use_info *> (access);
462 : 186956472 : if (!use)
463 : : {
464 : 171276490 : set_info *value = safe_dyn_cast<set_info *> (access);
465 : : // In order to ensure that -g doesn't affect codegen, uses in debug
466 : : // instructions do not affect liveness, either in DF or here.
467 : : // This means that there might be no correct definition of the resource
468 : : // available (e.g. if it would require a phi node that the nondebug
469 : : // code doesn't need). Perhaps we could have "debug phi nodes" as
470 : : // well as "debug instructions", but that would require a method
471 : : // of building phi nodes that didn't depend on DF liveness information,
472 : : // and so might be significantly more expensive.
473 : : //
474 : : // Therefore, the only value we try to attach to a use by a debug
475 : : // instruction is VALUE itself (as we would for nondebug instructions).
476 : : // We then need to make a conservative check for whether VALUE is
477 : : // actually correct.
478 : 189538335 : auto value_is_valid = [&]()
479 : : {
480 : : // Memmory always has a valid definition.
481 : 18261845 : if (ref.is_mem ())
482 : : return true;
483 : :
484 : : // If VALUE would lead to an uninitialized use anyway, there's
485 : : // nothing to check.
486 : 16748976 : if (!value)
487 : : return false;
488 : :
489 : : // If the previous definition occurs in the same EBB then it
490 : : // is certainly correct.
491 : 16747020 : if (value->ebb () == bi.current_ebb)
492 : : return true;
493 : :
494 : : // Check if VALUE is the function's only definition of REGNO.
495 : : // (We already know that it dominates the use.)
496 : 7759000 : if (!bitmap_bit_p (bi.potential_phi_regs, regno))
497 : : return true;
498 : :
499 : : // If the register is live on entry to the EBB but not used
500 : : // within it, VALUE is the correct live-in value.
501 : 731724 : if (!bi.ebb_live_in_for_debug)
502 : 405609 : calculate_ebb_live_in_for_debug (bi);
503 : 731724 : if (bitmap_bit_p (bi.ebb_live_in_for_debug, regno))
504 : : return true;
505 : :
506 : : // Punt for other cases.
507 : : return false;
508 : 171276490 : };
509 : 171276490 : if (insn->is_debug_insn () && !value_is_valid ())
510 : 2071 : value = nullptr;
511 : :
512 : 171276490 : use = create_reg_use (bi, insn, { mode, regno });
513 : 171276490 : m_temp_uses.safe_push (use);
514 : 171276490 : bi.last_access[ref.regno + 1] = use;
515 : 171276490 : use->record_reference (ref, true);
516 : : }
517 : : else
518 : : {
519 : : // Record the mode of the largest use. The choice is arbitrary if
520 : : // the instruction (unusually) references the same register in two
521 : : // different but equal-sized modes.
522 : 15679982 : gcc_checking_assert (use->insn () == insn);
523 : 15679982 : if (HARD_REGISTER_NUM_P (regno))
524 : : {
525 : 4300201 : if (!ordered_p (GET_MODE_PRECISION (use->mode ()),
526 : 4300201 : GET_MODE_PRECISION (mode)))
527 : : use->set_mode (reg_raw_mode[regno]);
528 : 4300201 : else if (partial_subreg_p (use->mode (), mode))
529 : 828 : use->set_mode (mode);
530 : : }
531 : 15679982 : use->record_reference (ref, false);
532 : : }
533 : 186956472 : }
534 : :
535 : : // Called while building SSA form for INSN using BI. Record the effect
536 : : // of call clobbers in RTL. We have already added the explicit sets and
537 : : // clobbers for RTL, which have priority over any call clobbers.
538 : : void
539 : 8823791 : function_info::record_call_clobbers (build_info &bi, insn_info *insn,
540 : : rtx_call_insn *rtl)
541 : : {
542 : : // See whether we should record this call in the EBB's list of
543 : : // call clobbers. Three things affect this choice:
544 : : //
545 : : // (1) The list is the only way we have of recording partial clobbers.
546 : : // All calls that only partially clobber registers must therefore
547 : : // be in the list.
548 : : //
549 : : // (2) Adding calls to the list is much more memory-efficient than
550 : : // creating a long list of clobber_infos.
551 : : //
552 : : // (3) Adding calls to the list limits the ability to move definitions
553 : : // of registers that are normally fully or partially clobbered
554 : : // by the associated predefined ABI. So adding calls to the list
555 : : // can hamper optimization if (thanks to -fipa-ra) the number of
556 : : // clobbers is much smaller than the usual set.
557 : : //
558 : : // The trade-off that we currently take is to use the list if there
559 : : // are some registers that the call only partially clobbers or if
560 : : // the set of clobbers is the standard set.
561 : 8823791 : function_abi abi = insn_callee_abi (rtl);
562 : 8823791 : if (abi.base_abi ().full_reg_clobbers () == abi.full_reg_clobbers ()
563 : 9323005 : || abi.full_and_partial_reg_clobbers () != abi.full_reg_clobbers ())
564 : : {
565 : : // Find an entry for this predefined ABI, creating one if necessary.
566 : 8324577 : ebb_call_clobbers_info *ecc = bi.current_ebb->first_call_clobbers ();
567 : 8324579 : while (ecc && ecc->abi () != &abi.base_abi ())
568 : 2 : ecc = ecc->next ();
569 : 8324577 : if (!ecc)
570 : : {
571 : 4741776 : ecc = allocate<ebb_call_clobbers_info> (&abi.base_abi ());
572 : 4741776 : ecc->m_next = bi.current_ebb->first_call_clobbers ();
573 : 4741776 : bi.current_ebb->set_first_call_clobbers (ecc);
574 : : }
575 : :
576 : 8324577 : auto abi_id = abi.base_abi ().id ();
577 : 8324577 : auto *insn_clobbers = allocate<insn_call_clobbers_note> (abi_id, insn);
578 : 8324577 : insn->add_note (insn_clobbers);
579 : :
580 : 8324577 : ecc->insert_max_node (insn_clobbers);
581 : :
582 : 16649154 : m_clobbered_by_calls |= abi.full_and_partial_reg_clobbers ();
583 : : }
584 : : else
585 : 46426902 : for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
586 : 45927688 : if (TEST_HARD_REG_BIT (abi.full_reg_clobbers (), regno))
587 : : {
588 : 26371473 : def_info *def = m_defs[regno + 1];
589 : 26371473 : if (!def || def->last_def ()->insn () != insn)
590 : : {
591 : 26221993 : def = allocate<clobber_info> (insn, regno);
592 : 26221993 : def->m_is_call_clobber = true;
593 : 26221993 : append_def (def);
594 : 26221993 : m_temp_defs.safe_push (def);
595 : 26221993 : bi.record_reg_def (def);
596 : : }
597 : : }
598 : 8823791 : }
599 : :
600 : : // Called while building SSA form using BI. Record that INSN contains
601 : : // write reference REF. Add associated def_infos to the list of accesses
602 : : // that we're building in m_temp_defs. Record the register's new live
603 : : // value in BI.
604 : : void
605 : 127876476 : function_info::record_def (build_info &bi, insn_info *insn,
606 : : rtx_obj_reference ref)
607 : : {
608 : : // Punt if we see multiple definitions of the same resource.
609 : : // This can happen for several reasons:
610 : : //
611 : : // - An instruction might store two values to memory at once, giving two
612 : : // distinct memory references.
613 : : //
614 : : // - An instruction might assign to multiple pieces of a wide pseudo
615 : : // register. For example, on 32-bit targets, an instruction might
616 : : // assign to both the upper and lower halves of a 64-bit pseudo register.
617 : : //
618 : : // - It's possible for the same register to be clobbered by the
619 : : // CALL_INSN_FUNCTION_USAGE and to be set by the main instruction
620 : : // pattern as well. In that case, the clobber conceptually happens
621 : : // before the set and can essentially be ignored.
622 : : //
623 : : // - Similarly, global registers are implicitly set by a call but can
624 : : // be explicitly set or clobbered as well. In that situation, the sets
625 : : // are listed first and should win over a clobber.
626 : 127876476 : unsigned int regno = ref.regno;
627 : 127876476 : machine_mode mode = ref.is_reg () ? ref.mode : BLKmode;
628 : 127876476 : def_info *def = safe_dyn_cast<def_info *> (bi.last_access[ref.regno + 1]);
629 : 76178617 : if (def && def->insn () == insn)
630 : : {
631 : 3766 : if (!ref.is_clobber ())
632 : : {
633 : 2174 : gcc_checking_assert (!is_a<clobber_info *> (def));
634 : 2174 : def->record_reference (ref, false);
635 : : }
636 : 3766 : return;
637 : : }
638 : :
639 : : // Memory is always well-defined, so only use clobber_infos for registers.
640 : 127872710 : if (ref.is_reg () && ref.is_clobber ())
641 : 17196029 : def = allocate<clobber_info> (insn, regno);
642 : : else
643 : 110676681 : def = allocate<set_info> (insn, resource_info { mode, regno });
644 : 127872710 : def->record_reference (ref, true);
645 : 127872710 : append_def (def);
646 : 127872710 : m_temp_defs.safe_push (def);
647 : 127872710 : bi.record_reg_def (def);
648 : : }
649 : :
650 : : // Called while building SSA form using BI. Add an insn_info for RTL
651 : : // to the block that we're current building.
652 : : void
653 : 190262028 : function_info::add_insn_to_block (build_info &bi, rtx_insn *rtl)
654 : : {
655 : 190262028 : insn_info *insn = allocate<insn_info> (bi.current_bb, rtl, UNKNOWN_COST);
656 : 190262028 : append_insn (insn);
657 : :
658 : 190262028 : vec_rtx_properties properties;
659 : 190262028 : properties.add_insn (rtl, true);
660 : 190262028 : insn->set_properties (properties);
661 : :
662 : 190262028 : start_insn_accesses ();
663 : :
664 : : // Record the uses.
665 : 489941613 : for (rtx_obj_reference ref : properties.refs ())
666 : 299679585 : if (ref.is_read ())
667 : 186956472 : record_use (bi, insn, ref);
668 : :
669 : : // Restore the contents of bi.last_access, which we used as a cache
670 : : // when assembling the uses.
671 : 738700020 : for (access_info *access : m_temp_uses)
672 : : {
673 : 171276490 : unsigned int regno = access->regno ();
674 : 171276490 : gcc_checking_assert (bi.last_access[regno + 1] == access);
675 : 171276490 : bi.last_access[regno + 1] = as_a<use_info *> (access)->def ();
676 : : }
677 : :
678 : : // Record the definitions.
679 : 489941613 : for (rtx_obj_reference ref : properties.refs ())
680 : 299679585 : if (ref.is_write ())
681 : 127876476 : record_def (bi, insn, ref);
682 : :
683 : : // Logically these happen before the explicit definitions, but if the
684 : : // explicit definitions and call clobbers reference the same register,
685 : : // the explicit definition should win.
686 : 190262028 : if (auto *call_rtl = dyn_cast<rtx_call_insn *> (rtl))
687 : 8823791 : record_call_clobbers (bi, insn, call_rtl);
688 : :
689 : 190262028 : finish_insn_accesses (insn);
690 : 190262028 : }
691 : :
692 : : // Check whether INSN sets any registers that are never subsequently used.
693 : : // If so, add REG_UNUSED notes for them. The caller has already removed
694 : : // any previous REG_UNUSED notes.
695 : : void
696 : 2980495 : function_info::add_reg_unused_notes (insn_info *insn)
697 : : {
698 : 2980495 : rtx_insn *rtl = insn->rtl ();
699 : :
700 : 6336108 : auto handle_potential_set = [&](rtx pattern)
701 : : {
702 : 3355613 : if (GET_CODE (pattern) != SET)
703 : 3221505 : return;
704 : :
705 : 2619404 : rtx dest = SET_DEST (pattern);
706 : 2619404 : if (!REG_P (dest))
707 : : return;
708 : :
709 : 2036287 : def_array defs = insn->defs ();
710 : 2036287 : unsigned int index = find_access_index (defs, REGNO (dest));
711 : 2170399 : for (unsigned int i = 0; i < REG_NREGS (dest); ++i)
712 : : {
713 : 2036291 : def_info *def = defs[index + i];
714 : 2036291 : gcc_checking_assert (def->regno () == REGNO (dest) + i);
715 : 2170403 : set_info *set = dyn_cast<set_info *> (def);
716 : 3355617 : if (set && set->has_nondebug_uses ())
717 : : return;
718 : : }
719 : 134108 : add_reg_note (rtl, REG_UNUSED, dest);
720 : 2980495 : };
721 : :
722 : 2980495 : rtx pattern = PATTERN (rtl);
723 : 2980495 : if (GET_CODE (pattern) == PARALLEL)
724 : 978982 : for (int i = 0; i < XVECLEN (pattern, 0); ++i)
725 : 677050 : handle_potential_set (XVECEXP (pattern, 0, i));
726 : : else
727 : 2678563 : handle_potential_set (pattern);
728 : 2980495 : }
729 : :
730 : : // Search TREE for call clobbers at INSN. Return:
731 : : //
732 : : // - less than zero if INSN occurs before the root of TREE
733 : : // - 0 if INSN is the root of TREE
734 : : // - greater than zero if INSN occurs after the root of TREE
735 : : int
736 : 28441939 : rtl_ssa::lookup_call_clobbers (insn_call_clobbers_tree &tree, insn_info *insn)
737 : : {
738 : 71467778 : auto compare = [&](insn_call_clobbers_note *clobbers)
739 : : {
740 : 43025839 : return insn->compare_with (clobbers->insn ());
741 : 28441939 : };
742 : 28441939 : return tree.lookup (compare);
743 : : }
744 : :
745 : : // Print a description of INSN to PP.
746 : : void
747 : 0 : rtl_ssa::pp_insn (pretty_printer *pp, const insn_info *insn)
748 : : {
749 : 0 : if (!insn)
750 : 0 : pp_string (pp, "<null>");
751 : : else
752 : 0 : insn->print_full (pp);
753 : 0 : }
754 : :
755 : : // Print a description of INSN to FILE.
756 : : void
757 : 0 : dump (FILE *file, const insn_info *insn)
758 : : {
759 : 0 : dump_using (file, pp_insn, insn);
760 : 0 : }
761 : :
762 : : // Debug interface to the dump routine above.
763 : 0 : void debug (const insn_info *x) { dump (stderr, x); }
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