LCOV - code coverage report
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Test Date: 2024-11-30 13:30:02 Functions: 88.1 % 42 37
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             Branch data     Line data    Source code
       1                 :             : ;; Constraint definitions for IA-32 and x86-64.
       2                 :             : ;; Copyright (C) 2006-2024 Free Software Foundation, Inc.
       3                 :             : ;;
       4                 :             : ;; This file is part of GCC.
       5                 :             : ;;
       6                 :             : ;; GCC is free software; you can redistribute it and/or modify
       7                 :             : ;; it under the terms of the GNU General Public License as published by
       8                 :             : ;; the Free Software Foundation; either version 3, or (at your option)
       9                 :             : ;; any later version.
      10                 :             : ;;
      11                 :             : ;; GCC is distributed in the hope that it will be useful,
      12                 :             : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
      13                 :             : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      14                 :             : ;; GNU General Public License for more details.
      15                 :             : ;;
      16                 :             : ;; You should have received a copy of the GNU General Public License
      17                 :             : ;; along with GCC; see the file COPYING3.  If not see
      18                 :             : ;; <http://www.gnu.org/licenses/>.
      19                 :             : 
      20                 :             : ;;; Unused letters:
      21                 :             : ;;;           H
      22                 :             : ;;;                             z
      23                 :             : 
      24                 :             : ;; Integer register constraints.
      25                 :             : ;; It is not necessary to define 'r' here.
      26                 :             : (define_register_constraint "R" "LEGACY_GENERAL_REGS"
      27                 :             :  "Legacy register---the eight integer registers available on all
      28                 :             :   i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
      29                 :             :   @code{si}, @code{di}, @code{bp}, @code{sp}).")
      30                 :             : 
      31                 :             : (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
      32                 :             :  "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
      33                 :             :   @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
      34                 :             : 
      35                 :             : (define_register_constraint "Q" "Q_REGS"
      36                 :             :  "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
      37                 :             :   @code{c}, and @code{d}.")
      38                 :             : 
      39                 :             : (define_register_constraint "l" "INDEX_REGS"
      40                 :             :  "@internal Any register that can be used as the index in a base+index
      41                 :             :   memory access: that is, any general register except the stack pointer.")
      42                 :             : 
      43                 :             : (define_register_constraint "a" "AREG"
      44                 :             :  "The @code{a} register.")
      45                 :             : 
      46                 :             : (define_register_constraint "b" "BREG"
      47                 :             :  "The @code{b} register.")
      48                 :             : 
      49                 :             : (define_register_constraint "c" "CREG"
      50                 :             :  "The @code{c} register.")
      51                 :             : 
      52                 :             : (define_register_constraint "d" "DREG"
      53                 :             :  "The @code{d} register.")
      54                 :             : 
      55                 :             : (define_register_constraint "S" "SIREG"
      56                 :             :  "The @code{si} register.")
      57                 :             : 
      58                 :             : (define_register_constraint "D" "DIREG"
      59                 :             :  "The @code{di} register.")
      60                 :             : 
      61                 :             : (define_register_constraint "A" "AD_REGS"
      62                 :             :  "The @code{a} and @code{d} registers, as a pair (for instructions
      63                 :             :   that return half the result in one and half in the other).")
      64                 :             : 
      65                 :             : (define_register_constraint "U" "CLOBBERED_REGS"
      66                 :             :  "The call-clobbered integer registers.")
      67                 :             : 
      68                 :             : ;; Floating-point register constraints.
      69                 :             : (define_register_constraint "f"
      70                 :             :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
      71                 :             :  "Any 80387 floating-point (stack) register.")
      72                 :             : 
      73                 :             : (define_register_constraint "t"
      74                 :             :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
      75                 :             :  "Top of 80387 floating-point stack (@code{%st(0)}).")
      76                 :             : 
      77                 :             : (define_register_constraint "u"
      78                 :             :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
      79                 :             :  "Second from top of 80387 floating-point stack (@code{%st(1)}).")
      80                 :             : 
      81                 :             : (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
      82                 :             : "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
      83                 :             : 
      84                 :             : (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
      85                 :             : "@internal Any mask register.")
      86                 :             : 
      87                 :             : ;; Vector registers (also used for plain floating point nowadays).
      88                 :             : (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
      89                 :             :  "Any MMX register.")
      90                 :             : 
      91                 :             : (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
      92                 :             :  "Any SSE register.")
      93                 :             : 
      94                 :             : (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
      95                 :             :  "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
      96                 :             : 
      97                 :             : ;; We use the Y prefix to denote any number of conditional register sets:
      98                 :             : ;;  z   First SSE register.
      99                 :             : ;;  d   any EVEX encodable SSE register for AVX512DQ target or
     100                 :             : ;;      any SSE register for SSE4_1 target.
     101                 :             : ;;  p   Integer register when TARGET_PARTIAL_REG_STALL is disabled
     102                 :             : ;;  a   Integer register when zero extensions with AND are disabled
     103                 :             : ;;  b   Any register that can be used as the GOT base when calling
     104                 :             : ;;      ___tls_get_addr: that is, any general register except EAX
     105                 :             : ;;      and ESP, for -fno-plt if linker supports it.  Otherwise,
     106                 :             : ;;      EBX.
     107                 :             : ;;  f   x87 register when 80387 floating point arithmetic is enabled
     108                 :             : ;;  r   SSE regs not requiring REX prefix when prefixes avoidance is enabled
     109                 :             : ;;      and all SSE regs otherwise
     110                 :             : ;;  v   any EVEX encodable SSE register for AVX512VL target,
     111                 :             : ;;      otherwise any SSE register
     112                 :             : ;;  w   any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
     113                 :             : ;;      target, otherwise any SSE register.
     114                 :             : ;;  W   any EVEX encodable SSE register for AVX512BW target,
     115                 :             : ;;      otherwise any SSE register.
     116                 :             : 
     117                 :             : (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
     118                 :             :  "First SSE register (@code{%xmm0}).")
     119                 :             : 
     120                 :             : (define_register_constraint "Yd"
     121                 :             :  "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
     122                 :             :  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
     123                 :             : 
     124                 :             : (define_register_constraint "Yp"
     125                 :             :  "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
     126                 :             :  "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
     127                 :             : 
     128                 :             : (define_register_constraint "Ya"
     129                 :             :  "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
     130                 :             :   ? NO_REGS : GENERAL_REGS"
     131                 :             :  "@internal Any integer register when zero extensions with AND are disabled.")
     132                 :             : 
     133                 :             : (define_register_constraint "Yb"
     134                 :             :  "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
     135                 :             :  "@internal Any register that can be used as the GOT base when calling
     136                 :             :   ___tls_get_addr: that is, any general register except @code{a} and
     137                 :             :   @code{sp} registers, for -fno-plt if linker supports it.  Otherwise,
     138                 :             :   @code{b} register.")
     139                 :             : 
     140                 :             : (define_register_constraint "Yf"
     141                 :             :  "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
     142                 :             :  "@internal Any x87 register when 80387 FP arithmetic is enabled.")
     143                 :             : 
     144                 :             : (define_register_constraint "Yr"
     145                 :             :  "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
     146                 :             :  "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
     147                 :             : 
     148                 :             : (define_register_constraint "Yv"
     149                 :             :  "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
     150                 :             :  "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
     151                 :             : 
     152                 :             : (define_register_constraint "Yw"
     153                 :             :  "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
     154                 :             :  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
     155                 :             : 
     156                 :             : (define_register_constraint "YW"
     157                 :             :  "TARGET_AVX512BW ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
     158                 :             :  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target, otherwise any SSE register.")
     159                 :             : 
     160                 :             : ;; We use the B prefix to denote any number of internal operands:
     161                 :             : ;;  f  FLAGS_REG
     162                 :             : ;;  g  GOT memory operand.
     163                 :             : ;;  m  Vector memory operand
     164                 :             : ;;  c  Constant memory operand
     165                 :             : ;;  k  TLS address that allows insn using non-integer registers
     166                 :             : ;;  n  Memory operand without REX prefix
     167                 :             : ;;  r  Broadcast memory operand
     168                 :             : ;;  s  Sibcall memory operand, not valid for TARGET_X32
     169                 :             : ;;  w  Call memory operand, not valid for TARGET_X32
     170                 :             : ;;  z  Constant call address operand.
     171                 :             : ;;  C  Integer SSE constant with all bits set operand.
     172                 :             : ;;  F  Floating-point SSE constant with all bits set operand.
     173                 :             : ;;  H  Integer SSE constant that is 128/256bit all ones
     174                 :             : ;;     and zero-extand to 256/512bit, or 128bit all ones
     175                 :             : ;;     and zero-extend to 512bit.
     176                 :             : ;;  M  x86-64 memory operand.
     177                 :             : 
     178                 :             : (define_constraint "Bf"
     179                 :             :   "@internal Flags register operand."
     180                 :             :   (match_operand 0 "flags_reg_operand"))
     181                 :             : 
     182                 :             : (define_constraint "Bg"
     183                 :             :   "@internal GOT memory operand."
     184                 :             :   (match_operand 0 "GOT_memory_operand"))
     185                 :             : 
     186                 :             : (define_special_memory_constraint "Bm"
     187                 :             :   "@internal Vector memory operand."
     188                 :             :   (match_operand 0 "vector_memory_operand"))
     189                 :             : 
     190                 :             : (define_special_memory_constraint "Bk"
     191                 :             :   "@internal TLS address that allows insn using non-integer registers."
     192                 :             :   (and (match_operand 0 "memory_operand")
     193                 :    15590575 :        (not (match_test "ix86_gpr_tls_address_pattern_p (op)"))))
     194                 :             : 
     195                 :             : (define_special_memory_constraint "Bn"
     196                 :      109883 :   "@internal Memory operand without REX prefix."
     197                 :             :   (and (match_operand 0 "memory_operand")
     198                 :       22958 :        (not (match_test "x86_extended_reg_mentioned_p (op)"))))
     199                 :      132841 : 
     200                 :             : (define_special_memory_constraint "Br"
     201                 :     1076303 :   "@internal bcst memory operand."
     202                 :             :   (match_operand 0 "bcst_mem_operand"))
     203                 :     1076303 : 
     204                 :     1076303 : (define_constraint "Bs"
     205                 :             :   "@internal Sibcall memory operand."
     206                 :     3310529 :   (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
     207                 :     1103257 :             (not (match_test "TARGET_X32"))
     208                 :             :             (match_operand 0 "sibcall_memory_operand"))
     209                 :     1092995 :        (and (match_test "TARGET_X32")
     210                 :     1103717 :             (match_test "Pmode == DImode")
     211                 :             :             (match_operand 0 "GOT_memory_operand"))))
     212                 :             : 
     213                 :    47901945 : (define_constraint "Bw"
     214                 :             :   "@internal Call memory operand."
     215                 :   143705599 :   (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
     216                 :    47901945 :             (not (match_test "TARGET_X32"))
     217                 :             :             (match_operand 0 "memory_operand"))
     218                 :    47026878 :        (and (match_test "TARGET_X32")
     219                 :         631 :             (match_test "Pmode == DImode")
     220                 :             :             (match_operand 0 "GOT_memory_operand"))))
     221                 :             : 
     222                 :    48786655 : (define_constraint "Bz"
     223                 :             :   "@internal Constant call address operand."
     224                 :    48786655 :   (match_operand 0 "constant_call_address_operand"))
     225                 :    48786655 : 
     226                 :             : (define_constraint "BC"
     227                 :             :   "@internal integer SSE constant with all bits set operand."
     228                 :   174345788 :   (and (match_test "TARGET_SSE")
     229                 :    87172866 :        (ior (match_test "op == constm1_rtx")
     230                 :    87172922 :             (match_operand 0 "vector_all_ones_operand"))))
     231                 :    87172922 : 
     232                 :    38291126 : (define_constraint "BF"
     233                 :             :   "@internal floating-point SSE constant with all bits set operand."
     234                 :    38291126 :   (and (match_test "TARGET_SSE")
     235                 :    38291126 :        (match_operand 0 "float_vector_all_ones_operand")))
     236                 :             : 
     237                 :   109235443 : (define_constraint "BH"
     238                 :             :   "@internal integer constant with last half/quarter bits set operand."
     239                 :   109235443 :   (ior (match_operand 0 "vector_all_ones_zero_extend_half_operand")
     240                 :   109235443 :        (match_operand 0 "vector_all_ones_zero_extend_quarter_operand")))
     241                 :             : 
     242                 :             : ;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64
     243                 :    70014512 : ;; to prevent LRA from converting the operand to the form '(mem (reg X))'
     244                 :             : ;; where X is a base register.
     245                 :    77501129 : (define_constraint "BM"
     246                 :             :   "@internal x86-64 memory operand."
     247                 :             :   (and (match_code "mem")
     248                 :     7486617 :        (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
     249                 :     7486617 :                                                  MEM_ADDR_SPACE (op))")))
     250                 :             : 
     251                 :             : ;; Integer constant constraints.
     252                 :         401 : (define_constraint "Wb"
     253                 :             :   "Integer constant in the range 0 @dots{} 7, for 8-bit shifts."
     254                 :         401 :   (and (match_code "const_int")
     255                 :         401 :        (match_test "IN_RANGE (ival, 0, 7)")))
     256                 :         401 : 
     257                 :         401 : (define_constraint "Wc"
     258                 :       61108 :   "Integer constant -1 or 1."
     259                 :             :   (and (match_code "const_int")
     260                 :       61108 :        (ior (match_test "op == constm1_rtx")
     261                 :        3914 :             (match_test "op == const1_rtx"))))
     262                 :             : 
     263                 :             : (define_constraint "Ww"
     264                 :        2348 :   "Integer constant in the range 0 @dots{} 15, for 16-bit shifts."
     265                 :             :   (and (match_code "const_int")
     266                 :        6915 :        (match_test "IN_RANGE (ival, 0, 15)")))
     267                 :        2348 : 
     268                 :        2219 : (define_constraint "I"
     269                 :        2348 :   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
     270                 :             :   (and (match_code "const_int")
     271                 :     1329024 :        (match_test "IN_RANGE (ival, 0, 31)")))
     272                 :     3224868 : 
     273                 :     2828617 : (define_constraint "J"
     274                 :     3224868 :   "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
     275                 :             :   (and (match_code "const_int")
     276                 :     2126495 :        (match_test "IN_RANGE (ival, 0, 63)")))
     277                 :     5468957 : 
     278                 :     5190105 : (define_constraint "K"
     279                 :   191226215 :   "Signed 8-bit integer constant."
     280                 :             :   (and (match_code "const_int")
     281                 :   369933923 :        (match_test "IN_RANGE (ival, -128, 127)")))
     282                 :   187921963 : 
     283                 :   184567639 : (define_constraint "L"
     284                 :   186419305 :   "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
     285                 :             :    for AND as a zero-extending move."
     286                 :      563428 :   (and (match_code "const_int")
     287                 :     1440592 :        (ior (match_test "ival == 0xff")
     288                 :      538429 :             (match_test "ival == 0xffff")
     289                 :     1440473 :             (match_test "ival == HOST_WIDE_INT_C (0xffffffff)"))))
     290                 :             : 
     291                 :     1560334 : (define_constraint "M"
     292                 :     2070648 :   "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
     293                 :             :   (and (match_code "const_int")
     294                 :     1560334 :        (match_test "IN_RANGE (ival, 0, 3)")))
     295                 :      510314 : 
     296                 :      482880 : (define_constraint "N"
     297                 :      510314 :   "Unsigned 8-bit integer constant (for @code{in} and @code{out}
     298                 :             :    instructions)."
     299                 :     1050734 :   (and (match_code "const_int")
     300                 :     1376718 :        (match_test "IN_RANGE (ival, 0, 255)")))
     301                 :     1040067 : 
     302                 :     1050734 : (define_constraint "O"
     303                 :      128742 :   "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
     304                 :             :   (and (match_code "const_int")
     305                 :       64606 :        (match_test "IN_RANGE (ival, 0, 127)")))
     306                 :       64136 : 
     307                 :       61349 : ;; Floating-point constant constraints.
     308                 :       64136 : ;; We allow constants even if TARGET_80387 isn't set, because the
     309                 :             : ;; stack register converter may need to load 0.0 into the function
     310                 :    47925934 : ;; value register (top of stack).
     311                 :             : (define_constraint "G"
     312                 :             :   "Standard 80387 floating point constant."
     313                 :             :   (and (match_code "const_double")
     314                 :     2507542 :        (match_test "standard_80387_constant_p (op) > 0")))
     315                 :             : 
     316                 :      845513 : ;; This can theoretically be any mode's CONST0_RTX.
     317                 :   614073615 : (define_constraint "C"
     318                 :             :   "Constant zero operand."
     319                 :   605585585 :   (ior (match_test "op == const0_rtx")
     320                 :   614073615 :        (match_operand 0 "const0_operand")))
     321                 :             : 
     322                 :   674684203 : ;; Constant-or-symbol-reference constraints.
     323                 :             : 
     324                 :   674684203 : (define_constraint "e"
     325                 :   674684203 :   "32-bit signed integer constant, or a symbolic reference known
     326                 :             :    to fit that range (for immediate operands in sign-extending x86-64
     327                 :             :    instructions)."
     328                 :      290164 :   (match_operand 0 "x86_64_immediate_operand"))
     329                 :             : 
     330                 :      290164 : ;; We use W prefix to denote any number of
     331                 :      290164 : ;; constant-or-symbol-reference constraints
     332                 :             : 
     333                 :             : (define_constraint "We"
     334                 :             :   "32-bit signed integer constant, or a symbolic reference known
     335                 :             :    to fit that range (for sign-extending conversion operations that
     336                 :             :    require non-VOIDmode immediate operands)."
     337                 :             :   (and (match_operand 0 "x86_64_immediate_operand")
     338                 :      290164 :        (match_test "mode != VOIDmode")))
     339                 :             : 
     340                 :             : (define_constraint "Wz"
     341                 :     1821526 :   "32-bit unsigned integer constant, or a symbolic reference known
     342                 :             :    to fit that range (for zero-extending conversion operations that
     343                 :     1821526 :    require non-VOIDmode immediate operands)."
     344                 :     1821526 :   (and (match_operand 0 "x86_64_zext_immediate_operand")
     345                 :     1821526 :        (match_test "mode != VOIDmode")))
     346                 :             : 
     347                 :             : (define_constraint "Wd"
     348                 :      204981 :   "128-bit integer constant where both the high and low 64-bit word
     349                 :             :    of it satisfies the e constraint."
     350                 :      204981 :   (match_operand 0 "x86_64_hilo_int_operand"))
     351                 :      204981 : 
     352                 :             : (define_constraint "Wf"
     353                 :             :   "32-bit signed integer constant zero extended from word size
     354                 :        1098 :    to double word size."
     355                 :             :   (match_operand 0 "x86_64_dwzext_immediate_operand"))
     356                 :        1098 : 
     357                 :        1098 : (define_constraint "Ws"
     358                 :             :   "A symbolic reference or label reference."
     359                 :             :   (match_code "const,symbol_ref,label_ref"))
     360                 :          14 : 
     361                 :             : (define_constraint "Z"
     362                 :          14 :   "32-bit unsigned integer constant, or a symbolic reference known
     363                 :             :    to fit that range (for immediate operands in zero-extending x86-64
     364                 :             :    instructions)."
     365                 :             :   (match_operand 0 "x86_64_zext_immediate_operand"))
     366                 :             : 
     367                 :             : ;; T prefix is used for different address constraints
     368                 :           0 : ;;   v - VSIB address
     369                 :           0 : ;;   s - address with no segment register
     370                 :             : ;;   i - address with no index and no rip
     371                 :           0 : ;;   b - address with no base and no rip
     372                 :             : 
     373                 :             : (define_address_constraint "Tv"
     374                 :   333916799 :   "VSIB address operand"
     375                 :             :   (match_operand 0 "vsib_address_operand"))
     376                 :   333916799 : 
     377                 :   333916799 : (define_address_constraint "Ts"
     378                 :             :   "Address operand without segment register"
     379                 :             :   (match_operand 0 "address_no_seg_operand"))
     380                 :       13354 : 
     381                 :             : ;; j prefix is used for APX operand constraints.
     382                 :       13354 : ;;  <  Auto-dec memory operand without GPR32.
     383                 :       13354 : ;;  >  Auto-inc memory operand without GPR32.
     384                 :             : ;;  a  Vector memory operand without GPR32.
     385                 :             : ;;  b  VSIB address operand without EGPR.
     386                 :    32386954 : ;;  c  Integer register.  GENERAL_GPR16 for TARGET_APX_EGPR and
     387                 :             : ;;     !TARGET_AVX, otherwise GENERAL_REGS.
     388                 :    32386954 : ;;  e  Memory operand for APX NDD ADD.
     389                 :    32386954 : ;;  j  Integer register.  GENERAL_GPR16 for TARGET_APX_EGPR, otherwise
     390                 :             : ;;     GENERAL_REGS.
     391                 :             : ;;  o  Offsetable memory operand without GPR32.
     392                 :      421231 : ;;  p  General address operand without GPR32.
     393                 :             : ;;  m  Memory operand without GPR32.
     394                 :      421231 : ;;  M  Memory operand, with APX NDD check.
     395                 :      421799 : ;;  R  Integer register.  GENERAL_REGS.
     396                 :             : ;;  O  Offsettable memory operand, with APX NDD check.
     397                 :             : ;;  V  Non-offsetable memory operand without GPR32.
     398                 :             : 
     399                 :             : ;; Constraint that force to use EGPR, can only adopt to register class.
     400                 :             : (define_register_constraint  "jR" "GENERAL_REGS")
     401                 :             : 
     402                 :             : (define_register_constraint  "jr"
     403                 :             :  "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
     404                 :             : 
     405                 :             : (define_memory_constraint "jm"
     406                 :             :   "@internal memory operand without GPR32."
     407                 :             :   (and (match_operand 0 "memory_operand")
     408                 :      108880 :        (not (and (match_test "TARGET_APX_EGPR")
     409                 :         568 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     410                 :             : 
     411                 :             : (define_constraint "j<"
     412                 :           0 :   "@internal auto-dec memory operand without GPR32."
     413                 :             :   (and (and (match_code "mem")
     414                 :           0 :             (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
     415                 :           0 :                  (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC")))
     416                 :           0 :        (not (and (match_test "TARGET_APX_EGPR")
     417                 :           0 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     418                 :             : 
     419                 :             : (define_constraint "j>"
     420                 :           0 :   "@internal auto-inc memory operand without GPR32."
     421                 :             :   (and (and (match_code "mem")
     422                 :           0 :             (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC")
     423                 :           0 :                  (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")))
     424                 :           0 :        (not (and (match_test "TARGET_APX_EGPR")
     425                 :           0 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     426                 :             : 
     427                 :             : (define_memory_constraint "jo"
     428                 :           0 :   "@internal offsetable memory operand without GPR32."
     429                 :             :   (and (and (match_code "mem")
     430                 :           0 :             (match_test "offsettable_nonstrict_memref_p (op)"))
     431                 :           0 :        (not (and (match_test "TARGET_APX_EGPR")
     432                 :           0 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     433                 :             : 
     434                 :             : (define_constraint "jV"
     435                 :           0 :   "@internal non-offsetable memory operand without GPR32."
     436                 :             :   (and (and (match_code "mem")
     437                 :           0 :             (match_test "memory_address_addr_space_p (GET_MODE (op),
     438                 :             :                                                       XEXP (op, 0),
     439                 :           0 :                                                       MEM_ADDR_SPACE (op))")
     440                 :           0 :             (not (match_test "offsettable_nonstrict_memref_p (op)")))
     441                 :           0 :        (not (and (match_test "TARGET_APX_EGPR")
     442                 :           0 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     443                 :             : 
     444                 :             : (define_address_constraint "jp"
     445                 :           0 :   "@internal general address operand without GPR32"
     446                 :           0 :   (and (match_test "address_operand (op, VOIDmode)")
     447                 :           0 :        (not (and (match_test "TARGET_APX_EGPR")
     448                 :           0 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     449                 :             : 
     450                 :             : (define_special_memory_constraint "ja"
     451                 :       88456 :   "@internal vector memory operand without GPR32."
     452                 :             :   (and (match_operand 0 "vector_memory_operand")
     453                 :      123718 :        (not (and (match_test "TARGET_APX_EGPR")
     454                 :       88456 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     455                 :             : 
     456                 :             : (define_address_constraint "jb"
     457                 :        4936 :   "VSIB address operand without EGPR"
     458                 :             :   (and (match_operand 0 "vsib_address_operand")
     459                 :        9872 :        (not (and (match_test "TARGET_APX_EGPR")
     460                 :        4936 :                  (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
     461                 :             : 
     462                 :             : (define_register_constraint  "jc"
     463                 :         857 :  "TARGET_APX_EGPR && !TARGET_AVX ? GENERAL_GPR16 : GENERAL_REGS")
     464                 :             : 
     465                 :         857 : (define_memory_constraint "je"
     466                 :         857 :   "@internal Memory operand for APX EVEX-encoded ADD (i.e. APX NDD/NF)."
     467                 :             :   (match_operand 0 "apx_evex_add_memory_operand"))
     468                 :             : 
     469                 :        1675 : (define_memory_constraint "jM"
     470                 :             :   "@internal Memory operand, with APX EVEX-encoded (i.e. APX NDD/NF) check."
     471                 :        1675 :   (match_operand 0 "apx_evex_memory_operand"))
     472                 :        1675 : 
     473                 :             : (define_memory_constraint "jO"
     474                 :             :   "@internal Offsettable memory operand, with APX EVEX-encoded
     475                 :         105 :    (i.e. APX NDD/NF) check."
     476                 :             :   (and (match_operand 0 "apx_evex_memory_operand")
     477                 :          78 :            (match_test "offsettable_nonstrict_memref_p (op)")))
     478                 :         183 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/constraints.md not long enough */
        

Generated by: LCOV version 2.1-beta

LCOV profile is generated on x86_64 machine using following configure options: configure --disable-bootstrap --enable-coverage=opt --enable-languages=c,c++,fortran,go,jit,lto,rust,m2 --enable-host-shared. GCC test suite is run with the built compiler.