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1 : : ;; Constraint definitions for IA-32 and x86-64.
2 : : ;; Copyright (C) 2006-2025 Free Software Foundation, Inc.
3 : : ;;
4 : : ;; This file is part of GCC.
5 : : ;;
6 : : ;; GCC is free software; you can redistribute it and/or modify
7 : : ;; it under the terms of the GNU General Public License as published by
8 : : ;; the Free Software Foundation; either version 3, or (at your option)
9 : : ;; any later version.
10 : : ;;
11 : : ;; GCC is distributed in the hope that it will be useful,
12 : : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : : ;; GNU General Public License for more details.
15 : : ;;
16 : : ;; You should have received a copy of the GNU General Public License
17 : : ;; along with GCC; see the file COPYING3. If not see
18 : : ;; <http://www.gnu.org/licenses/>.
19 : :
20 : : ;;; Unused letters:
21 : : ;;; H
22 : : ;;; z
23 : :
24 : : ;; Integer register constraints.
25 : : ;; It is not necessary to define 'r' here.
26 : : (define_register_constraint "R" "LEGACY_GENERAL_REGS"
27 : : "Legacy register---the eight integer registers available on all
28 : : i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
29 : : @code{si}, @code{di}, @code{bp}, @code{sp}).")
30 : :
31 : : (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
32 : : "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
33 : : @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
34 : :
35 : : (define_register_constraint "Q" "Q_REGS"
36 : : "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
37 : : @code{c}, and @code{d}.")
38 : :
39 : : (define_register_constraint "l" "INDEX_REGS"
40 : : "@internal Any register that can be used as the index in a base+index
41 : : memory access: that is, any general register except the stack pointer.")
42 : :
43 : : (define_register_constraint "a" "AREG"
44 : : "The @code{a} register.")
45 : :
46 : : (define_register_constraint "b" "BREG"
47 : : "The @code{b} register.")
48 : :
49 : : (define_register_constraint "c" "CREG"
50 : : "The @code{c} register.")
51 : :
52 : : (define_register_constraint "d" "DREG"
53 : : "The @code{d} register.")
54 : :
55 : : (define_register_constraint "S" "SIREG"
56 : : "The @code{si} register.")
57 : :
58 : : (define_register_constraint "D" "DIREG"
59 : : "The @code{di} register.")
60 : :
61 : : (define_register_constraint "A" "AD_REGS"
62 : : "The @code{a} and @code{d} registers, as a pair (for instructions
63 : : that return half the result in one and half in the other).")
64 : :
65 : : (define_register_constraint "U" "CLOBBERED_REGS"
66 : : "The call-clobbered integer registers.")
67 : :
68 : : ;; Floating-point register constraints.
69 : : (define_register_constraint "f"
70 : : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
71 : : "Any 80387 floating-point (stack) register.")
72 : :
73 : : (define_register_constraint "t"
74 : : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
75 : : "Top of 80387 floating-point stack (@code{%st(0)}).")
76 : :
77 : : (define_register_constraint "u"
78 : : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
79 : : "Second from top of 80387 floating-point stack (@code{%st(1)}).")
80 : :
81 : : (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
82 : : "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
83 : :
84 : : (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
85 : : "@internal Any mask register.")
86 : :
87 : : ;; Vector registers (also used for plain floating point nowadays).
88 : : (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
89 : : "Any MMX register.")
90 : :
91 : : (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
92 : : "Any SSE register.")
93 : :
94 : : (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
95 : : "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
96 : :
97 : : ;; We use the Y prefix to denote any number of conditional register sets:
98 : : ;; z First SSE register.
99 : : ;; d any EVEX encodable SSE register for AVX512DQ target or
100 : : ;; any SSE register for SSE4_1 target.
101 : : ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
102 : : ;; a Integer register when zero extensions with AND are disabled
103 : : ;; b Any register that can be used as the GOT base when calling
104 : : ;; ___tls_get_addr: that is, any general register except EAX
105 : : ;; and ESP, for -fno-plt if linker supports it. Otherwise,
106 : : ;; EBX.
107 : : ;; f x87 register when 80387 floating point arithmetic is enabled
108 : : ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled
109 : : ;; and all SSE regs otherwise
110 : : ;; v any EVEX encodable SSE register for AVX512VL target,
111 : : ;; otherwise any SSE register
112 : : ;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
113 : : ;; target, otherwise any SSE register.
114 : : ;; W any EVEX encodable SSE register for AVX512BW target,
115 : : ;; otherwise any SSE register.
116 : :
117 : : (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
118 : : "First SSE register (@code{%xmm0}).")
119 : :
120 : : (define_register_constraint "Yd"
121 : : "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
122 : : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
123 : :
124 : : (define_register_constraint "Yp"
125 : : "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
126 : : "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
127 : :
128 : : (define_register_constraint "Ya"
129 : : "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
130 : : ? NO_REGS : GENERAL_REGS"
131 : : "@internal Any integer register when zero extensions with AND are disabled.")
132 : :
133 : : (define_register_constraint "Yb"
134 : : "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
135 : : "@internal Any register that can be used as the GOT base when calling
136 : : ___tls_get_addr: that is, any general register except @code{a} and
137 : : @code{sp} registers, for -fno-plt if linker supports it. Otherwise,
138 : : @code{b} register.")
139 : :
140 : : (define_register_constraint "Yf"
141 : : "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
142 : : "@internal Any x87 register when 80387 FP arithmetic is enabled.")
143 : :
144 : : (define_register_constraint "Yr"
145 : : "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
146 : : "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
147 : :
148 : : (define_register_constraint "Yv"
149 : : "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
150 : : "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
151 : :
152 : : (define_register_constraint "Yw"
153 : : "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
154 : : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
155 : :
156 : : (define_register_constraint "YW"
157 : : "TARGET_AVX512BW ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
158 : : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target, otherwise any SSE register.")
159 : :
160 : : ;; We use the B prefix to denote any number of internal operands:
161 : : ;; f FLAGS_REG
162 : : ;; g GOT memory operand.
163 : : ;; m Vector memory operand
164 : : ;; c Constant memory operand
165 : : ;; k TLS address that allows insn using non-integer registers
166 : : ;; n Memory operand without REX prefix
167 : : ;; r Broadcast memory operand
168 : : ;; s Sibcall memory operand, not valid for TARGET_X32
169 : : ;; w Call memory operand, not valid for TARGET_X32
170 : : ;; z Constant call address operand.
171 : : ;; C Integer SSE constant with all bits set operand.
172 : : ;; F Floating-point SSE constant with all bits set operand.
173 : : ;; H Integer SSE constant that is 128/256bit all ones
174 : : ;; and zero-extand to 256/512bit, or 128bit all ones
175 : : ;; and zero-extend to 512bit.
176 : : ;; M x86-64 memory operand.
177 : :
178 : : (define_constraint "Bf"
179 : : "@internal Flags register operand."
180 : : (match_operand 0 "flags_reg_operand"))
181 : :
182 : : (define_constraint "Bg"
183 : : "@internal GOT memory operand."
184 : : (match_operand 0 "GOT_memory_operand"))
185 : :
186 : : (define_special_memory_constraint "Bm"
187 : : "@internal Vector memory operand."
188 : : (match_operand 0 "vector_memory_operand"))
189 : :
190 : : (define_special_memory_constraint "Bk"
191 : : "@internal TLS address that allows insn using non-integer registers."
192 : : (and (match_operand 0 "memory_operand")
193 : 15513232 : (not (match_test "ix86_gpr_tls_address_pattern_p (op)"))))
194 : :
195 : : (define_special_memory_constraint "Bn"
196 : 117651 : "@internal Memory operand without REX prefix."
197 : : (and (match_operand 0 "memory_operand")
198 : 24272 : (not (match_test "x86_extended_reg_mentioned_p (op)"))))
199 : 141923 :
200 : : (define_special_memory_constraint "Br"
201 : 1086365 : "@internal bcst memory operand."
202 : : (match_operand 0 "bcst_mem_operand"))
203 : 1086365 :
204 : 1086365 : (define_constraint "Bs"
205 : : "@internal Sibcall memory operand."
206 : 4097041 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
207 : 2730133 : (if_then_else (match_test "TARGET_X32")
208 : 1365150 : (and (match_test "Pmode == DImode")
209 : 1366114 : (match_operand 0 "GOT_memory_operand"))
210 : 1366114 : (match_operand 0 "sibcall_memory_operand"))))
211 : 49854586 :
212 : : (define_constraint "Bw"
213 : 49854586 : "@internal Call memory operand."
214 : 49854586 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
215 : 99706565 : (if_then_else (match_test "TARGET_X32")
216 : 49854014 : (and (match_test "Pmode == DImode")
217 : : (match_operand 0 "GOT_memory_operand"))
218 : : (match_operand 0 "memory_operand"))))
219 : 49848174 :
220 : : (define_constraint "Bz"
221 : 49848174 : "@internal Constant call address operand."
222 : 49848174 : (match_operand 0 "constant_call_address_operand"))
223 : :
224 : : (define_constraint "BC"
225 : 88488625 : "@internal integer SSE constant with all bits set operand."
226 : 176977250 : (and (match_test "TARGET_SSE")
227 : 88488625 : (ior (match_test "op == constm1_rtx")
228 : 88488625 : (match_operand 0 "vector_all_ones_operand"))))
229 : :
230 : 38365686 : (define_constraint "BF"
231 : : "@internal floating-point SSE constant with all bits set operand."
232 : 38365686 : (and (match_test "TARGET_SSE")
233 : 38365686 : (match_operand 0 "float_vector_all_ones_operand")))
234 : :
235 : 110911892 : (define_constraint "BH"
236 : : "@internal integer constant with last half/quarter bits set operand."
237 : 110911892 : (ior (match_operand 0 "vector_all_ones_zero_extend_half_operand")
238 : 110911892 : (match_operand 0 "vector_all_ones_zero_extend_quarter_operand")))
239 : :
240 : : ;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64
241 : 72536850 : ;; to prevent LRA from converting the operand to the form '(mem (reg X))'
242 : : ;; where X is a base register.
243 : 80292750 : (define_constraint "BM"
244 : : "@internal x86-64 memory operand."
245 : : (and (match_code "mem")
246 : 7755900 : (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
247 : 7755900 : MEM_ADDR_SPACE (op))")))
248 : :
249 : : ;; Integer constant constraints.
250 : 400 : (define_constraint "Wb"
251 : : "Integer constant in the range 0 @dots{} 7, for 8-bit shifts."
252 : 400 : (and (match_code "const_int")
253 : 400 : (match_test "IN_RANGE (ival, 0, 7)")))
254 : 400 :
255 : 400 : (define_constraint "Wc"
256 : 67295 : "Integer constant -1 or 1."
257 : : (and (match_code "const_int")
258 : 67295 : (ior (match_test "op == constm1_rtx")
259 : 3954 : (match_test "op == const1_rtx"))))
260 : :
261 : : (define_constraint "Ww"
262 : 2336 : "Integer constant in the range 0 @dots{} 15, for 16-bit shifts."
263 : : (and (match_code "const_int")
264 : 6879 : (match_test "IN_RANGE (ival, 0, 15)")))
265 : 2336 :
266 : 2207 : (define_constraint "I"
267 : 2336 : "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
268 : : (and (match_code "const_int")
269 : 1374063 : (match_test "IN_RANGE (ival, 0, 31)")))
270 : 3468973 :
271 : 3053503 : (define_constraint "J"
272 : 3468973 : "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
273 : : (and (match_code "const_int")
274 : 2424750 : (match_test "IN_RANGE (ival, 0, 63)")))
275 : 6390271 :
276 : 6083567 : (define_constraint "K"
277 : 213279395 : "Signed 8-bit integer constant."
278 : : (and (match_code "const_int")
279 : 412901710 : (match_test "IN_RANGE (ival, -128, 127)")))
280 : 209360876 :
281 : 206440881 : (define_constraint "L"
282 : 208494911 : "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
283 : : for AND as a zero-extending move."
284 : 660152 : (and (match_code "const_int")
285 : 1620600 : (ior (match_test "ival == 0xff")
286 : 634240 : (match_test "ival == 0xffff")
287 : 1620459 : (match_test "ival == HOST_WIDE_INT_C (0xffffffff)"))))
288 : :
289 : 1617327 : (define_constraint "M"
290 : 2161076 : "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
291 : : (and (match_code "const_int")
292 : 1617327 : (match_test "IN_RANGE (ival, 0, 3)")))
293 : 543749 :
294 : 513686 : (define_constraint "N"
295 : 543749 : "Unsigned 8-bit integer constant (for @code{in} and @code{out}
296 : : instructions)."
297 : 1014195 : (and (match_code "const_int")
298 : 1320495 : (match_test "IN_RANGE (ival, 0, 255)")))
299 : 1003606 :
300 : 1014195 : (define_constraint "O"
301 : 130829 : "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
302 : : (and (match_code "const_int")
303 : 64396 : (match_test "IN_RANGE (ival, 0, 127)")))
304 : 66433 :
305 : 63438 : ;; Floating-point constant constraints.
306 : 66433 : ;; We allow constants even if TARGET_80387 isn't set, because the
307 : : ;; stack register converter may need to load 0.0 into the function
308 : 48940725 : ;; value register (top of stack).
309 : : (define_constraint "G"
310 : : "Standard 80387 floating point constant."
311 : : (and (match_code "const_double")
312 : 2593187 : (match_test "standard_80387_constant_p (op) > 0")))
313 : :
314 : 791155 : ;; This can theoretically be any mode's CONST0_RTX.
315 : 621223657 : (define_constraint "C"
316 : : "Constant zero operand."
317 : 611952572 : (ior (match_test "op == const0_rtx")
318 : 621223657 : (match_operand 0 "const0_operand")))
319 : :
320 : 718120424 : ;; Constant-or-symbol-reference constraints.
321 : :
322 : 718120424 : (define_constraint "e"
323 : 718120424 : "32-bit signed integer constant, or a symbolic reference known
324 : : to fit that range (for immediate operands in sign-extending x86-64
325 : : instructions)."
326 : 308638 : (match_operand 0 "x86_64_immediate_operand"))
327 : :
328 : 308638 : ;; We use W prefix to denote any number of
329 : 308638 : ;; constant-or-symbol-reference constraints
330 : :
331 : : (define_constraint "We"
332 : : "32-bit signed integer constant, or a symbolic reference known
333 : : to fit that range (for sign-extending conversion operations that
334 : : require non-VOIDmode immediate operands)."
335 : : (and (match_operand 0 "x86_64_immediate_operand")
336 : 308638 : (match_test "mode != VOIDmode")))
337 : :
338 : : (define_constraint "Wz"
339 : 2257076 : "32-bit unsigned integer constant, or a symbolic reference known
340 : : to fit that range (for zero-extending conversion operations that
341 : 2257076 : require non-VOIDmode immediate operands)."
342 : 2257076 : (and (match_operand 0 "x86_64_zext_immediate_operand")
343 : 2257076 : (match_test "mode != VOIDmode")))
344 : :
345 : : (define_constraint "Wd"
346 : 212610 : "128-bit integer constant where both the high and low 64-bit word
347 : : of it satisfies the e constraint."
348 : 212610 : (match_operand 0 "x86_64_hilo_int_operand"))
349 : 212610 :
350 : : (define_constraint "Wf"
351 : : "32-bit signed integer constant zero extended from word size
352 : 1098 : to double word size."
353 : : (match_operand 0 "x86_64_dwzext_immediate_operand"))
354 : 1098 :
355 : 1098 : (define_constraint "Ws"
356 : : "A symbolic reference or label reference."
357 : : (match_code "const,symbol_ref,label_ref"))
358 : 14 :
359 : : (define_constraint "Z"
360 : 14 : "32-bit unsigned integer constant, or a symbolic reference known
361 : : to fit that range (for immediate operands in zero-extending x86-64
362 : : instructions)."
363 : : (match_operand 0 "x86_64_zext_immediate_operand"))
364 : :
365 : : ;; T prefix is used for different address constraints
366 : 0 : ;; v - VSIB address
367 : 0 : ;; s - address with no segment register
368 : : ;; i - address with no index and no rip
369 : 0 : ;; b - address with no base and no rip
370 : :
371 : : (define_address_constraint "Tv"
372 : 363822332 : "VSIB address operand"
373 : : (match_operand 0 "vsib_address_operand"))
374 : 363822332 :
375 : 363822332 : (define_address_constraint "Ts"
376 : : "Address operand without segment register"
377 : : (match_operand 0 "address_no_seg_operand"))
378 : 12813 :
379 : : ;; j prefix is used for APX operand constraints.
380 : 12813 : ;; < Auto-dec memory operand without GPR32.
381 : 12813 : ;; > Auto-inc memory operand without GPR32.
382 : : ;; a Vector memory operand without GPR32.
383 : : ;; b VSIB address operand without EGPR.
384 : 35118528 : ;; c Integer register. GENERAL_GPR16 for TARGET_APX_EGPR and
385 : : ;; !TARGET_AVX, otherwise GENERAL_REGS.
386 : 35118528 : ;; e Memory operand for APX NDD ADD.
387 : 35118528 : ;; j Integer register. GENERAL_GPR16 for TARGET_APX_EGPR, otherwise
388 : : ;; GENERAL_REGS.
389 : : ;; o Offsetable memory operand without GPR32.
390 : 450835 : ;; p General address operand without GPR32.
391 : : ;; m Memory operand without GPR32.
392 : 450835 : ;; M Memory operand, with APX NDD check.
393 : 451451 : ;; R Integer register. GENERAL_REGS.
394 : : ;; O Offsettable memory operand, with APX NDD check.
395 : : ;; V Non-offsetable memory operand without GPR32.
396 : :
397 : : ;; Constraint that force to use EGPR, can only adopt to register class.
398 : : (define_register_constraint "jR" "GENERAL_REGS")
399 : :
400 : : (define_register_constraint "jr"
401 : : "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
402 : :
403 : : (define_memory_constraint "jm"
404 : : "@internal memory operand without GPR32."
405 : : (and (match_operand 0 "memory_operand")
406 : 115419 : (not (and (match_test "TARGET_APX_EGPR")
407 : 616 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
408 : :
409 : : (define_constraint "j<"
410 : 0 : "@internal auto-dec memory operand without GPR32."
411 : : (and (and (match_code "mem")
412 : 0 : (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
413 : 0 : (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC")))
414 : 0 : (not (and (match_test "TARGET_APX_EGPR")
415 : 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
416 : :
417 : : (define_constraint "j>"
418 : 0 : "@internal auto-inc memory operand without GPR32."
419 : : (and (and (match_code "mem")
420 : 0 : (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC")
421 : 0 : (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")))
422 : 0 : (not (and (match_test "TARGET_APX_EGPR")
423 : 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
424 : :
425 : : (define_memory_constraint "jo"
426 : 0 : "@internal offsetable memory operand without GPR32."
427 : : (and (and (match_code "mem")
428 : 0 : (match_test "offsettable_nonstrict_memref_p (op)"))
429 : 0 : (not (and (match_test "TARGET_APX_EGPR")
430 : 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
431 : :
432 : : (define_constraint "jV"
433 : 0 : "@internal non-offsetable memory operand without GPR32."
434 : : (and (and (match_code "mem")
435 : 0 : (match_test "memory_address_addr_space_p (GET_MODE (op),
436 : : XEXP (op, 0),
437 : 0 : MEM_ADDR_SPACE (op))")
438 : 0 : (not (match_test "offsettable_nonstrict_memref_p (op)")))
439 : 0 : (not (and (match_test "TARGET_APX_EGPR")
440 : 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
441 : :
442 : : (define_address_constraint "jp"
443 : 0 : "@internal general address operand without GPR32"
444 : 0 : (and (match_test "address_operand (op, VOIDmode)")
445 : 0 : (not (and (match_test "TARGET_APX_EGPR")
446 : 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
447 : :
448 : : (define_special_memory_constraint "ja"
449 : 88818 : "@internal vector memory operand without GPR32."
450 : : (and (match_operand 0 "vector_memory_operand")
451 : 123827 : (not (and (match_test "TARGET_APX_EGPR")
452 : 88818 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
453 : :
454 : : (define_address_constraint "jb"
455 : 4968 : "VSIB address operand without EGPR"
456 : : (and (match_operand 0 "vsib_address_operand")
457 : 9936 : (not (and (match_test "TARGET_APX_EGPR")
458 : 4968 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
459 : :
460 : : (define_register_constraint "jc"
461 : 1027 : "TARGET_APX_EGPR && !TARGET_AVX ? GENERAL_GPR16 : GENERAL_REGS")
462 : :
463 : 1027 : (define_memory_constraint "je"
464 : 1027 : "@internal Memory operand for APX EVEX-encoded ADD (i.e. APX NDD/NF)."
465 : : (match_operand 0 "apx_evex_add_memory_operand"))
466 : :
467 : 1795 : (define_memory_constraint "jM"
468 : : "@internal Memory operand, with APX EVEX-encoded (i.e. APX NDD/NF) check."
469 : 1795 : (match_operand 0 "apx_evex_memory_operand"))
470 : 1795 :
471 : : (define_memory_constraint "jO"
472 : : "@internal Offsettable memory operand, with APX EVEX-encoded
473 : 105 : (i.e. APX NDD/NF) check."
474 : : (and (match_operand 0 "apx_evex_memory_operand")
475 : 78 : (match_test "offsettable_nonstrict_memref_p (op)")))
476 : 183 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/constraints.md not long enough */
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