Line data Source code
1 : ;; Constraint definitions for IA-32 and x86-64.
2 : ;; Copyright (C) 2006-2026 Free Software Foundation, Inc.
3 : ;;
4 : ;; This file is part of GCC.
5 : ;;
6 : ;; GCC is free software; you can redistribute it and/or modify
7 : ;; it under the terms of the GNU General Public License as published by
8 : ;; the Free Software Foundation; either version 3, or (at your option)
9 : ;; any later version.
10 : ;;
11 : ;; GCC is distributed in the hope that it will be useful,
12 : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 : ;; GNU General Public License for more details.
15 : ;;
16 : ;; You should have received a copy of the GNU General Public License
17 : ;; along with GCC; see the file COPYING3. If not see
18 : ;; <http://www.gnu.org/licenses/>.
19 :
20 : ;;; Unused letters:
21 : ;;; H
22 : ;;; z
23 :
24 : ;; Integer register constraints.
25 : ;; It is not necessary to define 'r' here.
26 : (define_register_constraint "R" "LEGACY_GENERAL_REGS"
27 : "Legacy register---the eight integer registers available on all
28 : i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
29 : @code{si}, @code{di}, @code{bp}, @code{sp}).")
30 :
31 : (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
32 : "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
33 : @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
34 :
35 : (define_register_constraint "Q" "Q_REGS"
36 : "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
37 : @code{c}, and @code{d}.")
38 :
39 : (define_register_constraint "l" "INDEX_REGS"
40 : "@internal Any register that can be used as the index in a base+index
41 : memory access: that is, any general register except the stack pointer.")
42 :
43 : (define_register_constraint "a" "AREG"
44 : "The @code{a} register.")
45 :
46 : (define_register_constraint "b" "BREG"
47 : "The @code{b} register.")
48 :
49 : (define_register_constraint "c" "CREG"
50 : "The @code{c} register.")
51 :
52 : (define_register_constraint "d" "DREG"
53 : "The @code{d} register.")
54 :
55 : (define_register_constraint "S" "SIREG"
56 : "The @code{si} register.")
57 :
58 : (define_register_constraint "D" "DIREG"
59 : "The @code{di} register.")
60 :
61 : (define_register_constraint "A" "AD_REGS"
62 : "The @code{a} and @code{d} registers, as a pair (for instructions
63 : that return half the result in one and half in the other).")
64 :
65 : (define_register_constraint "U" "CLOBBERED_REGS"
66 : "The call-clobbered integer registers.")
67 :
68 : ;; Floating-point register constraints.
69 : (define_register_constraint "f"
70 : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
71 : "Any 80387 floating-point (stack) register.")
72 :
73 : (define_register_constraint "t"
74 : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
75 : "Top of 80387 floating-point stack (@code{%st(0)}).")
76 :
77 : (define_register_constraint "u"
78 : "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
79 : "Second from top of 80387 floating-point stack (@code{%st(1)}).")
80 :
81 : (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
82 : "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
83 :
84 : (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
85 : "@internal Any mask register.")
86 :
87 : ;; Vector registers (also used for plain floating point nowadays).
88 : (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
89 : "Any MMX register.")
90 :
91 : (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
92 : "Any SSE register.")
93 :
94 : (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
95 : "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
96 :
97 : ;; We use the Y prefix to denote any number of conditional register sets:
98 : ;; z First SSE register.
99 : ;; d any EVEX encodable SSE register for AVX512DQ target or
100 : ;; any SSE register for SSE4_1 target.
101 : ;; D any EVEX encodable SSE register for AVX512DQ target or
102 : ;; any SSE register for SSE2 target.
103 : ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
104 : ;; a Integer register when zero extensions with AND are disabled
105 : ;; b Any register that can be used as the GOT base when calling
106 : ;; ___tls_get_addr: that is, any general register except EAX
107 : ;; and ESP, for -fno-plt if linker supports it. Otherwise,
108 : ;; EBX.
109 : ;; f x87 register when 80387 floating point arithmetic is enabled
110 : ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled
111 : ;; and all SSE regs otherwise
112 : ;; v any EVEX encodable SSE register for AVX512VL target,
113 : ;; otherwise any SSE register
114 : ;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
115 : ;; target, otherwise any SSE register.
116 : ;; W any EVEX encodable SSE register for AVX512BW target,
117 : ;; otherwise any SSE register.
118 :
119 : (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
120 : "First SSE register (@code{%xmm0}).")
121 :
122 : (define_register_constraint "Yd"
123 : "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
124 : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
125 :
126 : (define_register_constraint "YD"
127 : "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE2 ? SSE_REGS : NO_REGS"
128 : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE2 target.")
129 :
130 : (define_register_constraint "Yp"
131 : "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
132 : "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
133 :
134 : (define_register_constraint "Ya"
135 : "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
136 : ? NO_REGS : GENERAL_REGS"
137 : "@internal Any integer register when zero extensions with AND are disabled.")
138 :
139 : (define_register_constraint "Yb"
140 : "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
141 : "@internal Any register that can be used as the GOT base when calling
142 : ___tls_get_addr: that is, any general register except @code{a} and
143 : @code{sp} registers, for -fno-plt if linker supports it. Otherwise,
144 : @code{b} register.")
145 :
146 : (define_register_constraint "Yf"
147 : "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
148 : "@internal Any x87 register when 80387 FP arithmetic is enabled.")
149 :
150 : (define_register_constraint "Yr"
151 : "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
152 : "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
153 :
154 : (define_register_constraint "Yv"
155 : "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
156 : "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
157 :
158 : (define_register_constraint "Yw"
159 : "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
160 : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
161 :
162 : (define_register_constraint "YW"
163 : "TARGET_AVX512BW ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
164 : "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target, otherwise any SSE register.")
165 :
166 : ;; We use the B prefix to denote any number of internal operands:
167 : ;; f FLAGS_REG
168 : ;; g GOT memory operand.
169 : ;; m Vector memory operand
170 : ;; c Constant memory operand
171 : ;; k TLS address that allows insn using non-integer registers
172 : ;; n Memory operand without REX prefix
173 : ;; r Broadcast memory operand
174 : ;; s Sibcall memory operand, not valid for TARGET_X32
175 : ;; w Call memory operand, not valid for TARGET_X32
176 : ;; z Constant call address operand.
177 : ;; C Integer SSE constant with all bits set operand.
178 : ;; F Floating-point SSE constant with all bits set operand.
179 : ;; H Integer SSE constant that is 128/256bit all ones
180 : ;; and zero-extand to 256/512bit, or 128bit all ones
181 : ;; and zero-extend to 512bit.
182 : ;; M x86-64 memory operand.
183 :
184 : (define_constraint "Bf"
185 : "@internal Flags register operand."
186 : (match_operand 0 "flags_reg_operand"))
187 :
188 : (define_constraint "Bg"
189 : "@internal GOT memory operand."
190 : (match_operand 0 "GOT_memory_operand"))
191 :
192 : (define_special_memory_constraint "Bm"
193 : "@internal Vector memory operand."
194 : (match_operand 0 "vector_memory_operand"))
195 :
196 : (define_special_memory_constraint "Bk"
197 : "@internal TLS address that allows insn using non-integer registers."
198 : (and (match_operand 0 "memory_operand")
199 14900873 : (not (match_test "ix86_gpr_tls_address_pattern_p (op)"))))
200 :
201 : (define_special_memory_constraint "Bn"
202 120370 : "@internal Memory operand without REX prefix."
203 : (and (match_operand 0 "memory_operand")
204 26370 : (not (match_test "x86_extended_reg_mentioned_p (op)"))))
205 146740 :
206 : (define_special_memory_constraint "Br"
207 1118876 : "@internal bcst memory operand."
208 : (match_operand 0 "bcst_mem_operand"))
209 1118876 :
210 1118876 : (define_constraint "Bs"
211 : "@internal Sibcall memory operand."
212 4162404 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
213 2773570 : (if_then_else (match_test "TARGET_X32")
214 1386993 : (and (match_test "Pmode == DImode")
215 1387874 : (match_operand 0 "GOT_memory_operand"))
216 1387874 : (match_operand 0 "sibcall_memory_operand"))))
217 52018576 :
218 : (define_constraint "Bw"
219 52018576 : "@internal Call memory operand."
220 52018576 : (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
221 104034487 : (if_then_else (match_test "TARGET_X32")
222 52018062 : (and (match_test "Pmode == DImode")
223 : (match_operand 0 "GOT_memory_operand"))
224 : (match_operand 0 "memory_operand"))))
225 52193834 :
226 : (define_constraint "Bz"
227 52193834 : "@internal Constant call address operand."
228 52193834 : (match_operand 0 "constant_call_address_operand"))
229 :
230 : (define_constraint "BC"
231 96920230 : "@internal integer SSE constant with all bits set operand."
232 193840460 : (and (match_test "TARGET_SSE")
233 96920230 : (ior (match_test "op == constm1_rtx")
234 96920230 : (match_operand 0 "vector_all_ones_operand"))))
235 :
236 39313178 : (define_constraint "BF"
237 : "@internal floating-point SSE constant with all bits set operand."
238 39313178 : (and (match_test "TARGET_SSE")
239 39313178 : (match_operand 0 "float_vector_all_ones_operand")))
240 :
241 120613641 : (define_constraint "BH"
242 : "@internal integer constant with last half/quarter bits set operand."
243 120613641 : (ior (match_operand 0 "vector_all_ones_zero_extend_half_operand")
244 120613641 : (match_operand 0 "vector_all_ones_zero_extend_quarter_operand")))
245 :
246 : ;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64
247 75267835 : ;; to prevent LRA from converting the operand to the form '(mem (reg X))'
248 : ;; where X is a base register.
249 83716425 : (define_constraint "BM"
250 : "@internal x86-64 memory operand."
251 : (and (match_code "mem")
252 8448590 : (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
253 8448590 : MEM_ADDR_SPACE (op))")))
254 :
255 : ;; Integer constant constraints.
256 430 : (define_constraint "Wb"
257 : "Integer constant in the range 0 @dots{} 7, for 8-bit shifts."
258 430 : (and (match_code "const_int")
259 430 : (match_test "IN_RANGE (ival, 0, 7)")))
260 430 :
261 430 : (define_constraint "Wc"
262 66651 : "Integer constant -1 or 1."
263 : (and (match_code "const_int")
264 66651 : (ior (match_test "op == constm1_rtx")
265 3911 : (match_test "op == const1_rtx"))))
266 :
267 : (define_constraint "Ww"
268 3017 : "Integer constant in the range 0 @dots{} 15, for 16-bit shifts."
269 : (and (match_code "const_int")
270 8922 : (match_test "IN_RANGE (ival, 0, 15)")))
271 3017 :
272 2888 : (define_constraint "I"
273 3017 : "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
274 : (and (match_code "const_int")
275 1351653 : (match_test "IN_RANGE (ival, 0, 31)")))
276 3497867 :
277 2995819 : (define_constraint "J"
278 3497867 : "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
279 : (and (match_code "const_int")
280 2611783 : (match_test "IN_RANGE (ival, 0, 63)")))
281 6692733 :
282 6403745 : (define_constraint "K"
283 227918084 : "Signed 8-bit integer constant."
284 : (and (match_code "const_int")
285 441444221 : (match_test "IN_RANGE (ival, -128, 127)")))
286 223705673 :
287 220579113 : (define_constraint "L"
288 222812955 : "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
289 : for AND as a zero-extending move."
290 595018 : (and (match_code "const_int")
291 1407557 : (ior (match_test "ival == 0xff")
292 565506 : (match_test "ival == 0xffff")
293 1407424 : (match_test "ival == HOST_WIDE_INT_C (0xffffffff)"))))
294 :
295 1791048 : (define_constraint "M"
296 2415339 : "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
297 : (and (match_code "const_int")
298 1791048 : (match_test "IN_RANGE (ival, 0, 3)")))
299 624291 :
300 590508 : (define_constraint "N"
301 624291 : "Unsigned 8-bit integer constant (for @code{in} and @code{out}
302 : instructions)."
303 1119227 : (and (match_code "const_int")
304 1452069 : (match_test "IN_RANGE (ival, 0, 255)")))
305 1104091 :
306 1119227 : (define_constraint "O"
307 121357 : "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
308 : (and (match_code "const_int")
309 61131 : (match_test "IN_RANGE (ival, 0, 127)")))
310 60226 :
311 57173 : ;; Floating-point constant constraints.
312 60226 : ;; We allow constants even if TARGET_80387 isn't set, because the
313 : ;; stack register converter may need to load 0.0 into the function
314 49284485 : ;; value register (top of stack).
315 : (define_constraint "G"
316 : "Standard 80387 floating point constant."
317 : (and (match_code "const_double")
318 2518413 : (match_test "standard_80387_constant_p (op) > 0")))
319 :
320 801399 : ;; This can theoretically be any mode's CONST0_RTX.
321 647653628 : (define_constraint "C"
322 : "Constant zero operand."
323 638378696 : (ior (match_test "op == const0_rtx")
324 647653628 : (match_operand 0 "const0_operand")))
325 :
326 746436147 : ;; Constant-or-symbol-reference constraints.
327 :
328 746436147 : (define_constraint "e"
329 746436147 : "32-bit signed integer constant, or a symbolic reference known
330 : to fit that range (for immediate operands in sign-extending x86-64
331 : instructions)."
332 303064 : (match_operand 0 "x86_64_immediate_operand"))
333 :
334 303064 : ;; We use W prefix to denote any number of
335 303064 : ;; constant-or-symbol-reference constraints
336 :
337 : (define_constraint "We"
338 : "32-bit signed integer constant, or a symbolic reference known
339 : to fit that range (for sign-extending conversion operations that
340 : require non-VOIDmode immediate operands)."
341 : (and (match_operand 0 "x86_64_immediate_operand")
342 303064 : (match_test "mode != VOIDmode")))
343 :
344 : (define_constraint "Wz"
345 2588651 : "32-bit unsigned integer constant, or a symbolic reference known
346 : to fit that range (for zero-extending conversion operations that
347 2588651 : require non-VOIDmode immediate operands)."
348 2588651 : (and (match_operand 0 "x86_64_zext_immediate_operand")
349 2588651 : (match_test "mode != VOIDmode")))
350 :
351 : (define_constraint "Wd"
352 207261 : "128-bit integer constant where both the high and low 64-bit word
353 : of it satisfies the e constraint."
354 207261 : (match_operand 0 "x86_64_hilo_int_operand"))
355 207261 :
356 : (define_constraint "Wf"
357 : "32-bit signed integer constant zero extended from word size
358 1098 : to double word size."
359 : (match_operand 0 "x86_64_dwzext_immediate_operand"))
360 1098 :
361 1098 : (define_constraint "Ws"
362 : "A symbolic reference or label reference."
363 : (match_code "const,symbol_ref,label_ref"))
364 14 :
365 : (define_constraint "Z"
366 14 : "32-bit unsigned integer constant, or a symbolic reference known
367 : to fit that range (for immediate operands in zero-extending x86-64
368 : instructions)."
369 : (match_operand 0 "x86_64_zext_immediate_operand"))
370 :
371 : ;; T prefix is used for different address constraints
372 0 : ;; v - VSIB address
373 0 : ;; s - address with no segment register
374 : ;; i - address with no index and no rip
375 0 : ;; b - address with no base and no rip
376 :
377 : (define_address_constraint "Tv"
378 377144277 : "VSIB address operand"
379 : (match_operand 0 "vsib_address_operand"))
380 377144277 :
381 377144277 : (define_address_constraint "Ts"
382 : "Address operand without segment register"
383 : (match_operand 0 "address_no_seg_operand"))
384 12587 :
385 : ;; j prefix is used for APX operand constraints.
386 12587 : ;; < Auto-dec memory operand without GPR32.
387 12587 : ;; > Auto-inc memory operand without GPR32.
388 : ;; a Vector memory operand without GPR32.
389 : ;; b VSIB address operand without EGPR.
390 37442257 : ;; c Integer register. GENERAL_GPR16 for TARGET_APX_EGPR and
391 : ;; !TARGET_AVX, otherwise GENERAL_REGS.
392 37442257 : ;; e Memory operand for APX NDD ADD.
393 37442257 : ;; j Integer register. GENERAL_GPR16 for TARGET_APX_EGPR, otherwise
394 : ;; GENERAL_REGS.
395 : ;; o Offsetable memory operand without GPR32.
396 642330 : ;; p General address operand without GPR32.
397 : ;; m Memory operand without GPR32.
398 642330 : ;; M Memory operand, with APX NDD check.
399 643002 : ;; R Integer register. GENERAL_REGS.
400 : ;; O Offsettable memory operand, with APX NDD check.
401 : ;; V Non-offsetable memory operand without GPR32.
402 :
403 : ;; Constraint that force to use EGPR, can only adopt to register class.
404 : (define_register_constraint "jR" "GENERAL_REGS")
405 :
406 : (define_register_constraint "jr"
407 : "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
408 :
409 : (define_memory_constraint "jm"
410 : "@internal memory operand without GPR32."
411 : (and (match_operand 0 "memory_operand")
412 201605 : (not (and (match_test "TARGET_APX_EGPR")
413 672 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
414 :
415 : (define_constraint "j<"
416 0 : "@internal auto-dec memory operand without GPR32."
417 : (and (and (match_code "mem")
418 0 : (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
419 0 : (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC")))
420 0 : (not (and (match_test "TARGET_APX_EGPR")
421 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
422 :
423 : (define_constraint "j>"
424 0 : "@internal auto-inc memory operand without GPR32."
425 : (and (and (match_code "mem")
426 0 : (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC")
427 0 : (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")))
428 0 : (not (and (match_test "TARGET_APX_EGPR")
429 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
430 :
431 : (define_memory_constraint "jo"
432 0 : "@internal offsetable memory operand without GPR32."
433 : (and (and (match_code "mem")
434 0 : (match_test "offsettable_nonstrict_memref_p (op)"))
435 0 : (not (and (match_test "TARGET_APX_EGPR")
436 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
437 :
438 : (define_constraint "jV"
439 0 : "@internal non-offsetable memory operand without GPR32."
440 : (and (and (match_code "mem")
441 0 : (match_test "memory_address_addr_space_p (GET_MODE (op),
442 : XEXP (op, 0),
443 0 : MEM_ADDR_SPACE (op))")
444 0 : (not (match_test "offsettable_nonstrict_memref_p (op)")))
445 0 : (not (and (match_test "TARGET_APX_EGPR")
446 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
447 :
448 : (define_address_constraint "jp"
449 0 : "@internal general address operand without GPR32"
450 0 : (and (match_test "address_operand (op, VOIDmode)")
451 0 : (not (and (match_test "TARGET_APX_EGPR")
452 0 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
453 :
454 : (define_special_memory_constraint "ja"
455 133639 : "@internal vector memory operand without GPR32."
456 : (and (match_operand 0 "vector_memory_operand")
457 168975 : (not (and (match_test "TARGET_APX_EGPR")
458 133639 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
459 :
460 : (define_address_constraint "jb"
461 4540 : "VSIB address operand without EGPR"
462 : (and (match_operand 0 "vsib_address_operand")
463 9080 : (not (and (match_test "TARGET_APX_EGPR")
464 4540 : (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
465 :
466 : (define_register_constraint "jc"
467 848 : "TARGET_APX_EGPR && !TARGET_AVX ? GENERAL_GPR16 : GENERAL_REGS")
468 :
469 848 : (define_memory_constraint "je"
470 848 : "@internal Memory operand for APX EVEX-encoded ADD (i.e. APX NDD/NF)."
471 : (match_operand 0 "apx_evex_add_memory_operand"))
472 :
473 1696 : (define_memory_constraint "jM"
474 : "@internal Memory operand, with APX EVEX-encoded (i.e. APX NDD/NF) check."
475 1696 : (match_operand 0 "apx_evex_memory_operand"))
476 1696 :
477 : (define_memory_constraint "jO"
478 : "@internal Offsettable memory operand, with APX EVEX-encoded
479 108 : (i.e. APX NDD/NF) check."
480 : (and (match_operand 0 "apx_evex_memory_operand")
481 78 : (match_test "offsettable_nonstrict_memref_p (op)")))
482 186 : /* /home/worker/buildworker/tiber-lcov/build/gcc/config/i386/constraints.md not long enough */
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