Line data Source code
1 : /* Reload pseudo regs into hard regs for insns that require hard regs.
2 : Copyright (C) 1987-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it under
7 : the terms of the GNU General Public License as published by the Free
8 : Software Foundation; either version 3, or (at your option) any later
9 : version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "backend.h"
24 : #include "target.h"
25 : #include "rtl.h"
26 : #include "tree.h"
27 : #include "predict.h"
28 : #include "df.h"
29 : #include "memmodel.h"
30 : #include "tm_p.h"
31 : #include "optabs.h"
32 : #include "regs.h"
33 : #include "ira.h"
34 : #include "recog.h"
35 :
36 : #include "rtl-error.h"
37 : #include "expr.h"
38 : #include "addresses.h"
39 : #include "cfgrtl.h"
40 : #include "cfgbuild.h"
41 : #include "reload.h"
42 : #include "except.h"
43 : #include "dumpfile.h"
44 : #include "rtl-iter.h"
45 : #include "function-abi.h"
46 :
47 : /* This file contains the reload pass of the compiler, which is
48 : run after register allocation has been done. It checks that
49 : each insn is valid (operands required to be in registers really
50 : are in registers of the proper class) and fixes up invalid ones
51 : by copying values temporarily into registers for the insns
52 : that need them.
53 :
54 : The results of register allocation are described by the vector
55 : reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 : can be used to find which hard reg, if any, a pseudo reg is in.
57 :
58 : The technique we always use is to free up a few hard regs that are
59 : called ``reload regs'', and for each place where a pseudo reg
60 : must be in a hard reg, copy it temporarily into one of the reload regs.
61 :
62 : Reload regs are allocated locally for every instruction that needs
63 : reloads. When there are pseudos which are allocated to a register that
64 : has been chosen as a reload reg, such pseudos must be ``spilled''.
65 : This means that they go to other hard regs, or to stack slots if no other
66 : available hard regs can be found. Spilling can invalidate more
67 : insns, requiring additional need for reloads, so we must keep checking
68 : until the process stabilizes.
69 :
70 : For machines with different classes of registers, we must keep track
71 : of the register class needed for each reload, and make sure that
72 : we allocate enough reload registers of each class.
73 :
74 : The file reload.cc contains the code that checks one insn for
75 : validity and reports the reloads that it needs. This file
76 : is in charge of scanning the entire rtl code, accumulating the
77 : reload needs, spilling, assigning reload registers to use for
78 : fixing up each insn, and generating the new insns to copy values
79 : into the reload registers. */
80 :
81 : struct target_reload default_target_reload;
82 : #if SWITCHABLE_TARGET
83 : struct target_reload *this_target_reload = &default_target_reload;
84 : #endif
85 :
86 : #define spill_indirect_levels \
87 : (this_target_reload->x_spill_indirect_levels)
88 :
89 : /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 : into which reg N has been reloaded (perhaps for a previous insn). */
91 : static rtx *reg_last_reload_reg;
92 :
93 : /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 : for an output reload that stores into reg N. */
95 : static regset_head reg_has_output_reload;
96 :
97 : /* Indicates which hard regs are reload-registers for an output reload
98 : in the current insn. */
99 : static HARD_REG_SET reg_is_output_reload;
100 :
101 : /* Widest mode in which each pseudo reg is referred to (via subreg). */
102 : static machine_mode *reg_max_ref_mode;
103 :
104 : /* Vector to remember old contents of reg_renumber before spilling. */
105 : static short *reg_old_renumber;
106 :
107 : /* During reload_as_needed, element N contains the last pseudo regno reloaded
108 : into hard register N. If that pseudo reg occupied more than one register,
109 : reg_reloaded_contents points to that pseudo for each spill register in
110 : use; all of these must remain set for an inheritance to occur. */
111 : static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
112 :
113 : /* During reload_as_needed, element N contains the insn for which
114 : hard register N was last used. Its contents are significant only
115 : when reg_reloaded_valid is set for this register. */
116 : static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
117 :
118 : /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
119 : static HARD_REG_SET reg_reloaded_valid;
120 : /* Indicate if the register was dead at the end of the reload.
121 : This is only valid if reg_reloaded_contents is set and valid. */
122 : static HARD_REG_SET reg_reloaded_dead;
123 :
124 : /* Number of spill-regs so far; number of valid elements of spill_regs. */
125 : static int n_spills;
126 :
127 : /* In parallel with spill_regs, contains REG rtx's for those regs.
128 : Holds the last rtx used for any given reg, or 0 if it has never
129 : been used for spilling yet. This rtx is reused, provided it has
130 : the proper mode. */
131 : static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132 :
133 : /* In parallel with spill_regs, contains nonzero for a spill reg
134 : that was stored after the last time it was used.
135 : The precise value is the insn generated to do the store. */
136 : static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
137 :
138 : /* This is the register that was stored with spill_reg_store. This is a
139 : copy of reload_out / reload_out_reg when the value was stored; if
140 : reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
141 : static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
142 :
143 : /* This table is the inverse mapping of spill_regs:
144 : indexed by hard reg number,
145 : it contains the position of that reg in spill_regs,
146 : or -1 for something that is not in spill_regs.
147 :
148 : ?!? This is no longer accurate. */
149 : static short spill_reg_order[FIRST_PSEUDO_REGISTER];
150 :
151 : /* This reg set indicates registers that can't be used as spill registers for
152 : the currently processed insn. These are the hard registers which are live
153 : during the insn, but not allocated to pseudos, as well as fixed
154 : registers. */
155 : static HARD_REG_SET bad_spill_regs;
156 :
157 : /* These are the hard registers that can't be used as spill register for any
158 : insn. This includes registers used for user variables and registers that
159 : we can't eliminate. A register that appears in this set also can't be used
160 : to retry register allocation. */
161 : static HARD_REG_SET bad_spill_regs_global;
162 :
163 : /* Describes order of use of registers for reloading
164 : of spilled pseudo-registers. `n_spills' is the number of
165 : elements that are actually valid; new ones are added at the end.
166 :
167 : Both spill_regs and spill_reg_order are used on two occasions:
168 : once during find_reload_regs, where they keep track of the spill registers
169 : for a single insn, but also during reload_as_needed where they show all
170 : the registers ever used by reload. For the latter case, the information
171 : is calculated during finish_spills. */
172 : static short spill_regs[FIRST_PSEUDO_REGISTER];
173 :
174 : /* This vector of reg sets indicates, for each pseudo, which hard registers
175 : may not be used for retrying global allocation because the register was
176 : formerly spilled from one of them. If we allowed reallocating a pseudo to
177 : a register that it was already allocated to, reload might not
178 : terminate. */
179 : static HARD_REG_SET *pseudo_previous_regs;
180 :
181 : /* This vector of reg sets indicates, for each pseudo, which hard
182 : registers may not be used for retrying global allocation because they
183 : are used as spill registers during one of the insns in which the
184 : pseudo is live. */
185 : static HARD_REG_SET *pseudo_forbidden_regs;
186 :
187 : /* All hard regs that have been used as spill registers for any insn are
188 : marked in this set. */
189 : static HARD_REG_SET used_spill_regs;
190 :
191 : /* Index of last register assigned as a spill register. We allocate in
192 : a round-robin fashion. */
193 : static int last_spill_reg;
194 :
195 : /* Record the stack slot for each spilled hard register. */
196 : static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
197 :
198 : /* Width allocated so far for that stack slot. */
199 : static poly_uint64 spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
200 :
201 : /* Record which pseudos needed to be spilled. */
202 : static regset_head spilled_pseudos;
203 :
204 : /* Record which pseudos changed their allocation in finish_spills. */
205 : static regset_head changed_allocation_pseudos;
206 :
207 : /* Used for communication between order_regs_for_reload and count_pseudo.
208 : Used to avoid counting one pseudo twice. */
209 : static regset_head pseudos_counted;
210 :
211 : /* First uid used by insns created by reload in this function.
212 : Used in find_equiv_reg. */
213 : int reload_first_uid;
214 :
215 : /* Flag set by local-alloc or global-alloc if anything is live in
216 : a call-clobbered reg across calls. */
217 : int caller_save_needed;
218 :
219 : /* Set to 1 while reload_as_needed is operating.
220 : Required by some machines to handle any generated moves differently. */
221 : int reload_in_progress = 0;
222 :
223 : /* This obstack is used for allocation of rtl during register elimination.
224 : The allocated storage can be freed once find_reloads has processed the
225 : insn. */
226 : static struct obstack reload_obstack;
227 :
228 : /* Points to the beginning of the reload_obstack. All insn_chain structures
229 : are allocated first. */
230 : static char *reload_startobj;
231 :
232 : /* The point after all insn_chain structures. Used to quickly deallocate
233 : memory allocated in copy_reloads during calculate_needs_all_insns. */
234 : static char *reload_firstobj;
235 :
236 : /* This points before all local rtl generated by register elimination.
237 : Used to quickly free all memory after processing one insn. */
238 : static char *reload_insn_firstobj;
239 :
240 : /* List of insn_chain instructions, one for every insn that reload needs to
241 : examine. */
242 : class insn_chain *reload_insn_chain;
243 :
244 : /* TRUE if we potentially left dead insns in the insn stream and want to
245 : run DCE immediately after reload, FALSE otherwise. */
246 : static bool need_dce;
247 :
248 : /* List of all insns needing reloads. */
249 : static class insn_chain *insns_need_reload;
250 :
251 : /* This structure is used to record information about register eliminations.
252 : Each array entry describes one possible way of eliminating a register
253 : in favor of another. If there is more than one way of eliminating a
254 : particular register, the most preferred should be specified first. */
255 :
256 : struct elim_table
257 : {
258 : int from; /* Register number to be eliminated. */
259 : int to; /* Register number used as replacement. */
260 : poly_int64 initial_offset; /* Initial difference between values. */
261 : int can_eliminate; /* Nonzero if this elimination can be done. */
262 : int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
263 : target hook in previous scan over insns
264 : made by reload. */
265 : poly_int64 offset; /* Current offset between the two regs. */
266 : poly_int64 previous_offset; /* Offset at end of previous insn. */
267 : int ref_outside_mem; /* "to" has been referenced outside a MEM. */
268 : rtx from_rtx; /* REG rtx for the register to be eliminated.
269 : We cannot simply compare the number since
270 : we might then spuriously replace a hard
271 : register corresponding to a pseudo
272 : assigned to the reg to be eliminated. */
273 : rtx to_rtx; /* REG rtx for the replacement. */
274 : };
275 :
276 : static struct elim_table *reg_eliminate = 0;
277 :
278 : /* This is an intermediate structure to initialize the table. It has
279 : exactly the members provided by ELIMINABLE_REGS. */
280 : static const struct elim_table_1
281 : {
282 : const int from;
283 : const int to;
284 : } reg_eliminate_1[] =
285 :
286 : /* Reload and LRA don't agree on how a multi-register frame pointer
287 : is represented for elimination. See avr.h for a use case. */
288 : #ifdef RELOAD_ELIMINABLE_REGS
289 : RELOAD_ELIMINABLE_REGS;
290 : #else
291 : ELIMINABLE_REGS;
292 : #endif
293 :
294 : #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
295 :
296 : /* Record the number of pending eliminations that have an offset not equal
297 : to their initial offset. If nonzero, we use a new copy of each
298 : replacement result in any insns encountered. */
299 : int num_not_at_initial_offset;
300 :
301 : /* Count the number of registers that we may be able to eliminate. */
302 : static int num_eliminable;
303 : /* And the number of registers that are equivalent to a constant that
304 : can be eliminated to frame_pointer / arg_pointer + constant. */
305 : static int num_eliminable_invariants;
306 :
307 : /* For each label, we record the offset of each elimination. If we reach
308 : a label by more than one path and an offset differs, we cannot do the
309 : elimination. This information is indexed by the difference of the
310 : number of the label and the first label number. We can't offset the
311 : pointer itself as this can cause problems on machines with segmented
312 : memory. The first table is an array of flags that records whether we
313 : have yet encountered a label and the second table is an array of arrays,
314 : one entry in the latter array for each elimination. */
315 :
316 : static int first_label_num;
317 : static char *offsets_known_at;
318 : static poly_int64 (*offsets_at)[NUM_ELIMINABLE_REGS];
319 :
320 : vec<reg_equivs_t, va_gc> *reg_equivs;
321 :
322 : /* Stack of addresses where an rtx has been changed. We can undo the
323 : changes by popping items off the stack and restoring the original
324 : value at each location.
325 :
326 : We use this simplistic undo capability rather than copy_rtx as copy_rtx
327 : will not make a deep copy of a normally sharable rtx, such as
328 : (const (plus (symbol_ref) (const_int))). If such an expression appears
329 : as R1 in gen_reload_chain_without_interm_reg_p, then a shared
330 : rtx expression would be changed. See PR 42431. */
331 :
332 : typedef rtx *rtx_p;
333 : static vec<rtx_p> substitute_stack;
334 :
335 : /* Number of labels in the current function. */
336 :
337 : static int num_labels;
338 :
339 : static void replace_pseudos_in (rtx *, machine_mode, rtx);
340 : static void maybe_fix_stack_asms (void);
341 : static void copy_reloads (class insn_chain *);
342 : static void calculate_needs_all_insns (int);
343 : static int find_reg (class insn_chain *, int);
344 : static void find_reload_regs (class insn_chain *);
345 : static void select_reload_regs (void);
346 : static void delete_caller_save_insns (void);
347 :
348 : static void spill_failure (rtx_insn *, enum reg_class);
349 : static void count_spilled_pseudo (int, int, int);
350 : static void delete_dead_insn (rtx_insn *);
351 : static void alter_reg (int, int, bool);
352 : static void set_label_offsets (rtx, rtx_insn *, int);
353 : static void check_eliminable_occurrences (rtx);
354 : static void elimination_effects (rtx, machine_mode);
355 : static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
356 : static int eliminate_regs_in_insn (rtx_insn *, int);
357 : static void update_eliminable_offsets (void);
358 : static void mark_not_eliminable (rtx, const_rtx, void *);
359 : static void set_initial_elim_offsets (void);
360 : static bool verify_initial_elim_offsets (void);
361 : static void set_initial_label_offsets (void);
362 : static void set_offsets_for_label (rtx_insn *);
363 : static void init_eliminable_invariants (rtx_insn *, bool);
364 : static void init_elim_table (void);
365 : static void free_reg_equiv (void);
366 : static void update_eliminables (HARD_REG_SET *);
367 : static bool update_eliminables_and_spill (void);
368 : static void elimination_costs_in_insn (rtx_insn *);
369 : static void spill_hard_reg (unsigned int, int);
370 : static int finish_spills (int);
371 : static void scan_paradoxical_subregs (rtx);
372 : static void count_pseudo (int);
373 : static void order_regs_for_reload (class insn_chain *);
374 : static void reload_as_needed (int);
375 : static void forget_old_reloads_1 (rtx, const_rtx, void *);
376 : static void forget_marked_reloads (regset);
377 : static int reload_reg_class_lower (const void *, const void *);
378 : static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
379 : machine_mode);
380 : static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
381 : machine_mode);
382 : static int reload_reg_free_p (unsigned int, int, enum reload_type);
383 : static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
384 : rtx, rtx, int, int);
385 : static int free_for_value_p (int, machine_mode, int, enum reload_type,
386 : rtx, rtx, int, int);
387 : static int allocate_reload_reg (class insn_chain *, int, int);
388 : static int conflicts_with_override (rtx);
389 : static void failed_reload (rtx_insn *, int);
390 : static int set_reload_reg (int, int);
391 : static void choose_reload_regs_init (class insn_chain *, rtx *);
392 : static void choose_reload_regs (class insn_chain *);
393 : static void emit_input_reload_insns (class insn_chain *, struct reload *,
394 : rtx, int);
395 : static void emit_output_reload_insns (class insn_chain *, struct reload *,
396 : int);
397 : static void do_input_reload (class insn_chain *, struct reload *, int);
398 : static void do_output_reload (class insn_chain *, struct reload *, int);
399 : static void emit_reload_insns (class insn_chain *);
400 : static void delete_output_reload (rtx_insn *, int, int, rtx);
401 : static void delete_address_reloads (rtx_insn *, rtx_insn *);
402 : static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
403 : static void inc_for_reload (rtx, rtx, rtx, poly_int64);
404 : static void substitute (rtx *, const_rtx, rtx);
405 : static bool gen_reload_chain_without_interm_reg_p (int, int);
406 : static int reloads_conflict (int, int);
407 : static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
408 : static rtx_insn *emit_insn_if_valid_for_reload (rtx);
409 :
410 : /* Initialize the reload pass. This is called at the beginning of compilation
411 : and may be called again if the target is reinitialized. */
412 :
413 : void
414 0 : init_reload (void)
415 : {
416 0 : int i;
417 :
418 : /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
419 : Set spill_indirect_levels to the number of levels such addressing is
420 : permitted, zero if it is not permitted at all. */
421 :
422 0 : rtx tem
423 0 : = gen_rtx_MEM (Pmode,
424 0 : gen_rtx_PLUS (Pmode,
425 : gen_rtx_REG (Pmode,
426 : LAST_VIRTUAL_REGISTER + 1),
427 : gen_int_mode (4, Pmode)));
428 0 : spill_indirect_levels = 0;
429 :
430 0 : while (memory_address_p (QImode, tem))
431 : {
432 0 : spill_indirect_levels++;
433 0 : tem = gen_rtx_MEM (Pmode, tem);
434 : }
435 :
436 : /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 :
438 0 : tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
439 0 : indirect_symref_ok = memory_address_p (QImode, tem);
440 :
441 : /* See if reg+reg is a valid (and offsettable) address. */
442 :
443 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
444 : {
445 0 : tem = gen_rtx_PLUS (Pmode,
446 : gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
447 : gen_rtx_REG (Pmode, i));
448 :
449 : /* This way, we make sure that reg+reg is an offsettable address. */
450 0 : tem = plus_constant (Pmode, tem, 4);
451 :
452 0 : for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
453 0 : if (!double_reg_address_ok[mode]
454 0 : && memory_address_p ((enum machine_mode)mode, tem))
455 0 : double_reg_address_ok[mode] = 1;
456 : }
457 :
458 : /* Initialize obstack for our rtl allocation. */
459 0 : if (reload_startobj == NULL)
460 : {
461 0 : gcc_obstack_init (&reload_obstack);
462 0 : reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
463 : }
464 :
465 0 : INIT_REG_SET (&spilled_pseudos);
466 0 : INIT_REG_SET (&changed_allocation_pseudos);
467 0 : INIT_REG_SET (&pseudos_counted);
468 0 : }
469 :
470 : /* List of insn chains that are currently unused. */
471 : static class insn_chain *unused_insn_chains = 0;
472 :
473 : /* Allocate an empty insn_chain structure. */
474 : class insn_chain *
475 0 : new_insn_chain (void)
476 : {
477 0 : class insn_chain *c;
478 :
479 0 : if (unused_insn_chains == 0)
480 : {
481 0 : c = XOBNEW (&reload_obstack, class insn_chain);
482 0 : INIT_REG_SET (&c->live_throughout);
483 0 : INIT_REG_SET (&c->dead_or_set);
484 : }
485 : else
486 : {
487 0 : c = unused_insn_chains;
488 0 : unused_insn_chains = c->next;
489 : }
490 0 : c->is_caller_save_insn = 0;
491 0 : c->need_operand_change = 0;
492 0 : c->need_reload = 0;
493 0 : c->need_elim = 0;
494 0 : return c;
495 : }
496 :
497 : /* Small utility function to set all regs in hard reg set TO which are
498 : allocated to pseudos in regset FROM. */
499 :
500 : void
501 5360586 : compute_use_by_pseudos (HARD_REG_SET *to, regset from)
502 : {
503 5360586 : unsigned int regno;
504 5360586 : reg_set_iterator rsi;
505 :
506 5360586 : EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
507 : {
508 0 : int r = reg_renumber[regno];
509 :
510 0 : if (r < 0)
511 : {
512 : /* reload_combine uses the information from DF_LIVE_IN,
513 : which might still contain registers that have not
514 : actually been allocated since they have an
515 : equivalence. */
516 0 : gcc_assert (ira_conflicts_p || reload_completed);
517 : }
518 : else
519 0 : add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
520 : }
521 5360586 : }
522 :
523 : /* Replace all pseudos found in LOC with their corresponding
524 : equivalences. */
525 :
526 : static void
527 0 : replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
528 : {
529 0 : rtx x = *loc;
530 0 : enum rtx_code code;
531 0 : const char *fmt;
532 0 : int i, j;
533 :
534 0 : if (! x)
535 : return;
536 :
537 0 : code = GET_CODE (x);
538 0 : if (code == REG)
539 : {
540 0 : unsigned int regno = REGNO (x);
541 :
542 0 : if (regno < FIRST_PSEUDO_REGISTER)
543 : return;
544 :
545 0 : x = eliminate_regs_1 (x, mem_mode, usage, true, false);
546 0 : if (x != *loc)
547 : {
548 0 : *loc = x;
549 0 : replace_pseudos_in (loc, mem_mode, usage);
550 0 : return;
551 : }
552 :
553 0 : if (reg_equiv_constant (regno))
554 0 : *loc = reg_equiv_constant (regno);
555 0 : else if (reg_equiv_invariant (regno))
556 0 : *loc = reg_equiv_invariant (regno);
557 0 : else if (reg_equiv_mem (regno))
558 0 : *loc = reg_equiv_mem (regno);
559 0 : else if (reg_equiv_address (regno))
560 0 : *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
561 : else
562 : {
563 0 : gcc_assert (!REG_P (regno_reg_rtx[regno])
564 : || REGNO (regno_reg_rtx[regno]) != regno);
565 0 : *loc = regno_reg_rtx[regno];
566 : }
567 :
568 0 : return;
569 : }
570 0 : else if (code == MEM)
571 : {
572 0 : replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
573 0 : return;
574 : }
575 :
576 : /* Process each of our operands recursively. */
577 0 : fmt = GET_RTX_FORMAT (code);
578 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
579 0 : if (*fmt == 'e')
580 0 : replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
581 0 : else if (*fmt == 'E')
582 0 : for (j = 0; j < XVECLEN (x, i); j++)
583 0 : replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
584 : }
585 :
586 : /* Determine if the current function has an exception receiver block
587 : that reaches the exit block via non-exceptional edges */
588 :
589 : static bool
590 0 : has_nonexceptional_receiver (void)
591 : {
592 0 : edge e;
593 0 : edge_iterator ei;
594 0 : basic_block *tos, *worklist, bb;
595 :
596 : /* If we're not optimizing, then just err on the safe side. */
597 0 : if (!optimize)
598 : return true;
599 :
600 : /* First determine which blocks can reach exit via normal paths. */
601 0 : tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
602 :
603 0 : FOR_EACH_BB_FN (bb, cfun)
604 0 : bb->flags &= ~BB_REACHABLE;
605 :
606 : /* Place the exit block on our worklist. */
607 0 : EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
608 0 : *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
609 :
610 : /* Iterate: find everything reachable from what we've already seen. */
611 0 : while (tos != worklist)
612 : {
613 0 : bb = *--tos;
614 :
615 0 : FOR_EACH_EDGE (e, ei, bb->preds)
616 0 : if (!(e->flags & EDGE_ABNORMAL))
617 : {
618 0 : basic_block src = e->src;
619 :
620 0 : if (!(src->flags & BB_REACHABLE))
621 : {
622 0 : src->flags |= BB_REACHABLE;
623 0 : *tos++ = src;
624 : }
625 : }
626 : }
627 0 : free (worklist);
628 :
629 : /* Now see if there's a reachable block with an exceptional incoming
630 : edge. */
631 0 : FOR_EACH_BB_FN (bb, cfun)
632 0 : if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
633 : return true;
634 :
635 : /* No exceptional block reached exit unexceptionally. */
636 : return false;
637 : }
638 :
639 : /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
640 : zero elements) to MAX_REG_NUM elements.
641 :
642 : Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 : void
644 2823876 : grow_reg_equivs (void)
645 : {
646 2823876 : int old_size = vec_safe_length (reg_equivs);
647 2823876 : int max_regno = max_reg_num ();
648 2823876 : int i;
649 2823876 : reg_equivs_t ze;
650 :
651 2823876 : memset (&ze, 0, sizeof (reg_equivs_t));
652 2823876 : vec_safe_reserve (reg_equivs, max_regno);
653 209271617 : for (i = old_size; i < max_regno; i++)
654 203623865 : reg_equivs->quick_insert (i, ze);
655 2823876 : }
656 :
657 :
658 : /* Global variables used by reload and its subroutines. */
659 :
660 : /* The current basic block while in calculate_elim_costs_all_insns. */
661 : static basic_block elim_bb;
662 :
663 : /* Set during calculate_needs if an insn needs register elimination. */
664 : static int something_needs_elimination;
665 : /* Set during calculate_needs if an insn needs an operand changed. */
666 : static int something_needs_operands_changed;
667 : /* Set by alter_regs if we spilled a register to the stack. */
668 : static bool something_was_spilled;
669 :
670 : /* Nonzero means we couldn't get enough spill regs. */
671 : static int failure;
672 :
673 : /* Temporary array of pseudo-register number. */
674 : static int *temp_pseudo_reg_arr;
675 :
676 : /* If a pseudo has no hard reg, delete the insns that made the equivalence.
677 : If that insn didn't set the register (i.e., it copied the register to
678 : memory), just delete that insn instead of the equivalencing insn plus
679 : anything now dead. If we call delete_dead_insn on that insn, we may
680 : delete the insn that actually sets the register if the register dies
681 : there and that is incorrect. */
682 : static void
683 0 : remove_init_insns ()
684 : {
685 0 : for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 : {
687 0 : if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
688 : {
689 : rtx list;
690 0 : for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
691 : {
692 0 : rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
693 :
694 : /* If we already deleted the insn or if it may trap, we can't
695 : delete it. The latter case shouldn't happen, but can
696 : if an insn has a variable address, gets a REG_EH_REGION
697 : note added to it, and then gets converted into a load
698 : from a constant address. */
699 0 : if (NOTE_P (equiv_insn)
700 0 : || can_throw_internal (equiv_insn))
701 : ;
702 0 : else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
703 0 : delete_dead_insn (equiv_insn);
704 : else
705 0 : SET_INSN_DELETED (equiv_insn);
706 : }
707 : }
708 : }
709 0 : }
710 :
711 : /* Return true if remove_init_insns will delete INSN. */
712 : static bool
713 0 : will_delete_init_insn_p (rtx_insn *insn)
714 : {
715 0 : rtx set = single_set (insn);
716 0 : if (!set || !REG_P (SET_DEST (set)))
717 : return false;
718 0 : unsigned regno = REGNO (SET_DEST (set));
719 :
720 0 : if (can_throw_internal (insn))
721 : return false;
722 :
723 0 : if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
724 : return false;
725 :
726 0 : for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
727 : {
728 0 : rtx equiv_insn = XEXP (list, 0);
729 0 : if (equiv_insn == insn)
730 : return true;
731 : }
732 : return false;
733 : }
734 :
735 : /* Main entry point for the reload pass.
736 :
737 : FIRST is the first insn of the function being compiled.
738 :
739 : GLOBAL nonzero means we were called from global_alloc
740 : and should attempt to reallocate any pseudoregs that we
741 : displace from hard regs we will use for reloads.
742 : If GLOBAL is zero, we do not have enough information to do that,
743 : so any pseudo reg that is spilled must go to the stack.
744 :
745 : Return value is TRUE if reload likely left dead insns in the
746 : stream and a DCE pass should be run to eliminate them. Else the
747 : return value is FALSE. */
748 :
749 : bool
750 0 : reload (rtx_insn *first, int global)
751 : {
752 0 : int i, n;
753 0 : rtx_insn *insn;
754 0 : struct elim_table *ep;
755 0 : basic_block bb;
756 0 : bool inserted;
757 :
758 : /* Make sure even insns with volatile mem refs are recognizable. */
759 0 : init_recog ();
760 :
761 0 : failure = 0;
762 :
763 0 : reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
764 :
765 : /* Make sure that the last insn in the chain
766 : is not something that needs reloading. */
767 0 : emit_note (NOTE_INSN_DELETED);
768 :
769 : /* Enable find_equiv_reg to distinguish insns made by reload. */
770 0 : reload_first_uid = get_max_uid ();
771 :
772 : /* Initialize the secondary memory table. */
773 0 : clear_secondary_mem ();
774 :
775 : /* We don't have a stack slot for any spill reg yet. */
776 0 : memset (spill_stack_slot, 0, sizeof spill_stack_slot);
777 0 : memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
778 :
779 : /* Initialize the save area information for caller-save, in case some
780 : are needed. */
781 0 : init_save_areas ();
782 :
783 : /* Compute which hard registers are now in use
784 : as homes for pseudo registers.
785 : This is done here rather than (eg) in global_alloc
786 : because this point is reached even if not optimizing. */
787 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
788 0 : mark_home_live (i);
789 :
790 : /* A function that has a nonlocal label that can reach the exit
791 : block via non-exceptional paths must save all call-saved
792 : registers. */
793 0 : if (cfun->has_nonlocal_label
794 0 : && has_nonexceptional_receiver ())
795 0 : crtl->saves_all_registers = 1;
796 :
797 0 : if (crtl->saves_all_registers)
798 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
799 0 : if (! crtl->abi->clobbers_full_reg_p (i)
800 0 : && ! fixed_regs[i]
801 0 : && ! LOCAL_REGNO (i))
802 0 : df_set_regs_ever_live (i, true);
803 :
804 : /* Find all the pseudo registers that didn't get hard regs
805 : but do have known equivalent constants or memory slots.
806 : These include parameters (known equivalent to parameter slots)
807 : and cse'd or loop-moved constant memory addresses.
808 :
809 : Record constant equivalents in reg_equiv_constant
810 : so they will be substituted by find_reloads.
811 : Record memory equivalents in reg_mem_equiv so they can
812 : be substituted eventually by altering the REG-rtx's. */
813 :
814 0 : grow_reg_equivs ();
815 0 : reg_old_renumber = XCNEWVEC (short, max_regno);
816 0 : memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
817 0 : pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
818 0 : pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
819 :
820 0 : CLEAR_HARD_REG_SET (bad_spill_regs_global);
821 :
822 0 : init_eliminable_invariants (first, true);
823 0 : init_elim_table ();
824 :
825 : /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
826 : stack slots to the pseudos that lack hard regs or equivalents.
827 : Do not touch virtual registers. */
828 :
829 0 : temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
830 0 : for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 0 : temp_pseudo_reg_arr[n++] = i;
832 :
833 0 : if (ira_conflicts_p)
834 : /* Ask IRA to order pseudo-registers for better stack slot
835 : sharing. */
836 0 : ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
837 :
838 0 : for (i = 0; i < n; i++)
839 0 : alter_reg (temp_pseudo_reg_arr[i], -1, false);
840 :
841 : /* If we have some registers we think can be eliminated, scan all insns to
842 : see if there is an insn that sets one of these registers to something
843 : other than itself plus a constant. If so, the register cannot be
844 : eliminated. Doing this scan here eliminates an extra pass through the
845 : main reload loop in the most common case where register elimination
846 : cannot be done. */
847 0 : for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
848 0 : if (INSN_P (insn))
849 0 : note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULL);
850 :
851 0 : maybe_fix_stack_asms ();
852 :
853 0 : insns_need_reload = 0;
854 0 : something_needs_elimination = 0;
855 :
856 : /* Initialize to -1, which means take the first spill register. */
857 0 : last_spill_reg = -1;
858 :
859 : /* Spill any hard regs that we know we can't eliminate. */
860 0 : CLEAR_HARD_REG_SET (used_spill_regs);
861 : /* There can be multiple ways to eliminate a register;
862 : they should be listed adjacently.
863 : Elimination for any register fails only if all possible ways fail. */
864 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
865 : {
866 0 : int from = ep->from;
867 0 : int can_eliminate = 0;
868 0 : do
869 : {
870 0 : can_eliminate |= ep->can_eliminate;
871 0 : ep++;
872 : }
873 0 : while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
874 0 : if (! can_eliminate)
875 0 : spill_hard_reg (from, 1);
876 : }
877 :
878 0 : if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
879 0 : spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
880 :
881 0 : finish_spills (global);
882 :
883 : /* From now on, we may need to generate moves differently. We may also
884 : allow modifications of insns which cause them to not be recognized.
885 : Any such modifications will be cleaned up during reload itself. */
886 0 : reload_in_progress = 1;
887 :
888 : /* This loop scans the entire function each go-round
889 : and repeats until one repetition spills no additional hard regs. */
890 0 : for (;;)
891 : {
892 0 : int something_changed;
893 0 : poly_int64 starting_frame_size;
894 :
895 0 : starting_frame_size = get_frame_size ();
896 0 : something_was_spilled = false;
897 :
898 0 : set_initial_elim_offsets ();
899 0 : set_initial_label_offsets ();
900 :
901 : /* For each pseudo register that has an equivalent location defined,
902 : try to eliminate any eliminable registers (such as the frame pointer)
903 : assuming initial offsets for the replacement register, which
904 : is the normal case.
905 :
906 : If the resulting location is directly addressable, substitute
907 : the MEM we just got directly for the old REG.
908 :
909 : If it is not addressable but is a constant or the sum of a hard reg
910 : and constant, it is probably not addressable because the constant is
911 : out of range, in that case record the address; we will generate
912 : hairy code to compute the address in a register each time it is
913 : needed. Similarly if it is a hard register, but one that is not
914 : valid as an address register.
915 :
916 : If the location is not addressable, but does not have one of the
917 : above forms, assign a stack slot. We have to do this to avoid the
918 : potential of producing lots of reloads if, e.g., a location involves
919 : a pseudo that didn't get a hard register and has an equivalent memory
920 : location that also involves a pseudo that didn't get a hard register.
921 :
922 : Perhaps at some point we will improve reload_when_needed handling
923 : so this problem goes away. But that's very hairy. */
924 :
925 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
926 0 : if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
927 : {
928 0 : rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
929 : NULL_RTX);
930 :
931 0 : if (strict_memory_address_addr_space_p
932 0 : (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
933 0 : MEM_ADDR_SPACE (x)))
934 0 : reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
935 0 : else if (CONSTANT_P (XEXP (x, 0))
936 0 : || (REG_P (XEXP (x, 0))
937 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
938 0 : || (GET_CODE (XEXP (x, 0)) == PLUS
939 0 : && REG_P (XEXP (XEXP (x, 0), 0))
940 0 : && (REGNO (XEXP (XEXP (x, 0), 0))
941 : < FIRST_PSEUDO_REGISTER)
942 0 : && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
943 0 : reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
944 : else
945 : {
946 : /* Make a new stack slot. Then indicate that something
947 : changed so we go back and recompute offsets for
948 : eliminable registers because the allocation of memory
949 : below might change some offset. reg_equiv_{mem,address}
950 : will be set up for this pseudo on the next pass around
951 : the loop. */
952 0 : reg_equiv_memory_loc (i) = 0;
953 0 : reg_equiv_init (i) = 0;
954 0 : alter_reg (i, -1, true);
955 : }
956 : }
957 :
958 0 : if (caller_save_needed)
959 0 : setup_save_areas ();
960 :
961 0 : if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
962 : {
963 : /* If we have a stack frame, we must align it now. The
964 : stack size may be a part of the offset computation for
965 : register elimination. So if this changes the stack size,
966 : then repeat the elimination bookkeeping. We don't
967 : realign when there is no stack, as that will cause a
968 : stack frame when none is needed should
969 : TARGET_STARTING_FRAME_OFFSET not be already aligned to
970 : STACK_BOUNDARY. */
971 0 : assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
972 : }
973 : /* If we allocated another stack slot, redo elimination bookkeeping. */
974 0 : if (something_was_spilled
975 0 : || maybe_ne (starting_frame_size, get_frame_size ()))
976 : {
977 0 : if (update_eliminables_and_spill ())
978 0 : finish_spills (0);
979 0 : continue;
980 : }
981 :
982 0 : if (caller_save_needed)
983 : {
984 0 : save_call_clobbered_regs ();
985 : /* That might have allocated new insn_chain structures. */
986 0 : reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
987 : }
988 :
989 0 : calculate_needs_all_insns (global);
990 :
991 0 : if (! ira_conflicts_p)
992 : /* Don't do it for IRA. We need this info because we don't
993 : change live_throughout and dead_or_set for chains when IRA
994 : is used. */
995 0 : CLEAR_REG_SET (&spilled_pseudos);
996 :
997 0 : something_changed = 0;
998 :
999 : /* If we allocated any new memory locations, make another pass
1000 : since it might have changed elimination offsets. */
1001 0 : if (something_was_spilled
1002 0 : || maybe_ne (starting_frame_size, get_frame_size ()))
1003 : something_changed = 1;
1004 :
1005 : /* Even if the frame size remained the same, we might still have
1006 : changed elimination offsets, e.g. if find_reloads called
1007 : force_const_mem requiring the back end to allocate a constant
1008 : pool base register that needs to be saved on the stack. */
1009 0 : else if (!verify_initial_elim_offsets ())
1010 0 : something_changed = 1;
1011 :
1012 0 : if (update_eliminables_and_spill ())
1013 : {
1014 0 : finish_spills (0);
1015 0 : something_changed = 1;
1016 : }
1017 : else
1018 : {
1019 0 : select_reload_regs ();
1020 0 : if (failure)
1021 0 : goto failed;
1022 0 : if (insns_need_reload)
1023 0 : something_changed |= finish_spills (global);
1024 : }
1025 :
1026 0 : if (! something_changed)
1027 : break;
1028 :
1029 0 : if (caller_save_needed)
1030 0 : delete_caller_save_insns ();
1031 :
1032 0 : obstack_free (&reload_obstack, reload_firstobj);
1033 : }
1034 :
1035 : /* If global-alloc was run, notify it of any register eliminations we have
1036 : done. */
1037 0 : if (global)
1038 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 0 : if (ep->can_eliminate)
1040 0 : mark_elimination (ep->from, ep->to);
1041 :
1042 0 : remove_init_insns ();
1043 :
1044 : /* Use the reload registers where necessary
1045 : by generating move instructions to move the must-be-register
1046 : values into or out of the reload registers. */
1047 :
1048 0 : if (insns_need_reload != 0 || something_needs_elimination
1049 0 : || something_needs_operands_changed)
1050 : {
1051 0 : poly_int64 old_frame_size = get_frame_size ();
1052 :
1053 0 : reload_as_needed (global);
1054 :
1055 0 : gcc_assert (known_eq (old_frame_size, get_frame_size ()));
1056 :
1057 0 : gcc_assert (verify_initial_elim_offsets ());
1058 : }
1059 :
1060 : /* If we were able to eliminate the frame pointer, show that it is no
1061 : longer live at the start of any basic block. If it ls live by
1062 : virtue of being in a pseudo, that pseudo will be marked live
1063 : and hence the frame pointer will be known to be live via that
1064 : pseudo. */
1065 :
1066 0 : if (! frame_pointer_needed)
1067 0 : FOR_EACH_BB_FN (bb, cfun)
1068 0 : bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1069 :
1070 : /* Come here (with failure set nonzero) if we can't get enough spill
1071 : regs. */
1072 0 : failed:
1073 :
1074 0 : CLEAR_REG_SET (&changed_allocation_pseudos);
1075 0 : CLEAR_REG_SET (&spilled_pseudos);
1076 0 : reload_in_progress = 0;
1077 :
1078 : /* Now eliminate all pseudo regs by modifying them into
1079 : their equivalent memory references.
1080 : The REG-rtx's for the pseudos are modified in place,
1081 : so all insns that used to refer to them now refer to memory.
1082 :
1083 : For a reg that has a reg_equiv_address, all those insns
1084 : were changed by reloading so that no insns refer to it any longer;
1085 : but the DECL_RTL of a variable decl may refer to it,
1086 : and if so this causes the debugging info to mention the variable. */
1087 :
1088 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1089 : {
1090 0 : rtx addr = 0;
1091 :
1092 0 : if (reg_equiv_mem (i))
1093 0 : addr = XEXP (reg_equiv_mem (i), 0);
1094 :
1095 0 : if (reg_equiv_address (i))
1096 0 : addr = reg_equiv_address (i);
1097 :
1098 0 : if (addr)
1099 : {
1100 0 : if (reg_renumber[i] < 0)
1101 : {
1102 0 : rtx reg = regno_reg_rtx[i];
1103 :
1104 0 : REG_USERVAR_P (reg) = 0;
1105 0 : PUT_CODE (reg, MEM);
1106 0 : XEXP (reg, 0) = addr;
1107 0 : if (reg_equiv_memory_loc (i))
1108 0 : MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1109 : else
1110 0 : MEM_ATTRS (reg) = 0;
1111 0 : MEM_NOTRAP_P (reg) = 1;
1112 : }
1113 0 : else if (reg_equiv_mem (i))
1114 0 : XEXP (reg_equiv_mem (i), 0) = addr;
1115 : }
1116 :
1117 : /* We don't want complex addressing modes in debug insns
1118 : if simpler ones will do, so delegitimize equivalences
1119 : in debug insns. */
1120 0 : if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1121 : {
1122 0 : rtx reg = regno_reg_rtx[i];
1123 0 : rtx equiv = 0;
1124 0 : df_ref use, next;
1125 :
1126 0 : if (reg_equiv_constant (i))
1127 : equiv = reg_equiv_constant (i);
1128 0 : else if (reg_equiv_invariant (i))
1129 : equiv = reg_equiv_invariant (i);
1130 0 : else if (reg && MEM_P (reg))
1131 0 : equiv = targetm.delegitimize_address (reg);
1132 0 : else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1133 : equiv = reg;
1134 :
1135 0 : if (equiv == reg)
1136 0 : continue;
1137 :
1138 0 : for (use = DF_REG_USE_CHAIN (i); use; use = next)
1139 : {
1140 0 : insn = DF_REF_INSN (use);
1141 :
1142 : /* Make sure the next ref is for a different instruction,
1143 : so that we're not affected by the rescan. */
1144 0 : next = DF_REF_NEXT_REG (use);
1145 0 : while (next && DF_REF_INSN (next) == insn)
1146 0 : next = DF_REF_NEXT_REG (next);
1147 :
1148 0 : if (DEBUG_BIND_INSN_P (insn))
1149 : {
1150 0 : if (!equiv)
1151 : {
1152 0 : INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1153 0 : df_insn_rescan_debug_internal (insn);
1154 : }
1155 : else
1156 0 : INSN_VAR_LOCATION_LOC (insn)
1157 0 : = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1158 : reg, equiv);
1159 : }
1160 : }
1161 : }
1162 : }
1163 :
1164 : /* We must set reload_completed now since the cleanup_subreg_operands call
1165 : below will re-recognize each insn and reload may have generated insns
1166 : which are only valid during and after reload. */
1167 0 : reload_completed = 1;
1168 :
1169 : /* Make a pass over all the insns and delete all USEs which we inserted
1170 : only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1171 : notes. Delete all CLOBBER insns, except those that refer to the return
1172 : value and the special mem:BLK CLOBBERs added to prevent the scheduler
1173 : from misarranging variable-array code, and simplify (subreg (reg))
1174 : operands. Strip and regenerate REG_INC notes that may have been moved
1175 : around. */
1176 :
1177 0 : for (insn = first; insn; insn = NEXT_INSN (insn))
1178 0 : if (INSN_P (insn))
1179 : {
1180 0 : rtx *pnote;
1181 :
1182 0 : if (CALL_P (insn))
1183 0 : replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1184 : VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1185 :
1186 0 : if ((GET_CODE (PATTERN (insn)) == USE
1187 : /* We mark with QImode USEs introduced by reload itself. */
1188 0 : && (GET_MODE (insn) == QImode
1189 0 : || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1190 0 : || (GET_CODE (PATTERN (insn)) == CLOBBER
1191 0 : && (!MEM_P (XEXP (PATTERN (insn), 0))
1192 0 : || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1193 0 : || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1194 0 : && XEXP (XEXP (PATTERN (insn), 0), 0)
1195 0 : != stack_pointer_rtx))
1196 0 : && (!REG_P (XEXP (PATTERN (insn), 0))
1197 0 : || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1198 : {
1199 0 : delete_insn (insn);
1200 0 : continue;
1201 : }
1202 :
1203 : /* Some CLOBBERs may survive until here and still reference unassigned
1204 : pseudos with const equivalent, which may in turn cause ICE in later
1205 : passes if the reference remains in place. */
1206 0 : if (GET_CODE (PATTERN (insn)) == CLOBBER)
1207 0 : replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1208 0 : VOIDmode, PATTERN (insn));
1209 :
1210 : /* Discard obvious no-ops, even without -O. This optimization
1211 : is fast and doesn't interfere with debugging. */
1212 0 : if (NONJUMP_INSN_P (insn)
1213 0 : && GET_CODE (PATTERN (insn)) == SET
1214 0 : && REG_P (SET_SRC (PATTERN (insn)))
1215 0 : && REG_P (SET_DEST (PATTERN (insn)))
1216 0 : && (REGNO (SET_SRC (PATTERN (insn)))
1217 0 : == REGNO (SET_DEST (PATTERN (insn)))))
1218 : {
1219 0 : delete_insn (insn);
1220 0 : continue;
1221 : }
1222 :
1223 0 : pnote = ®_NOTES (insn);
1224 0 : while (*pnote != 0)
1225 : {
1226 0 : if (REG_NOTE_KIND (*pnote) == REG_DEAD
1227 0 : || REG_NOTE_KIND (*pnote) == REG_UNUSED
1228 0 : || REG_NOTE_KIND (*pnote) == REG_INC)
1229 0 : *pnote = XEXP (*pnote, 1);
1230 : else
1231 0 : pnote = &XEXP (*pnote, 1);
1232 : }
1233 :
1234 0 : if (AUTO_INC_DEC)
1235 : add_auto_inc_notes (insn, PATTERN (insn));
1236 :
1237 : /* Simplify (subreg (reg)) if it appears as an operand. */
1238 0 : cleanup_subreg_operands (insn);
1239 :
1240 : /* Clean up invalid ASMs so that they don't confuse later passes.
1241 : See PR 21299. */
1242 0 : if (asm_noperands (PATTERN (insn)) >= 0)
1243 : {
1244 0 : extract_insn (insn);
1245 0 : if (!constrain_operands (1, get_enabled_alternatives (insn)))
1246 : {
1247 0 : error_for_asm (insn,
1248 : "%<asm%> operand has impossible constraints");
1249 0 : delete_insn (insn);
1250 0 : continue;
1251 : }
1252 : }
1253 : }
1254 :
1255 0 : free (temp_pseudo_reg_arr);
1256 :
1257 : /* Indicate that we no longer have known memory locations or constants. */
1258 0 : free_reg_equiv ();
1259 :
1260 0 : free (reg_max_ref_mode);
1261 0 : free (reg_old_renumber);
1262 0 : free (pseudo_previous_regs);
1263 0 : free (pseudo_forbidden_regs);
1264 :
1265 0 : CLEAR_HARD_REG_SET (used_spill_regs);
1266 0 : for (i = 0; i < n_spills; i++)
1267 0 : SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1268 :
1269 : /* Free all the insn_chain structures at once. */
1270 0 : obstack_free (&reload_obstack, reload_startobj);
1271 0 : unused_insn_chains = 0;
1272 :
1273 0 : inserted = fixup_abnormal_edges ();
1274 :
1275 : /* Split basic blocks if we've possibly turned single trapping insn
1276 : into multiple ones or otherwise the backend requested to do so. */
1277 0 : if (cfun->can_throw_non_call_exceptions
1278 0 : || cfun->split_basic_blocks_after_reload)
1279 : {
1280 0 : auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1281 0 : bitmap_ones (blocks);
1282 0 : find_many_sub_basic_blocks (blocks);
1283 0 : }
1284 :
1285 0 : if (inserted)
1286 0 : commit_edge_insertions ();
1287 :
1288 : /* Replacing pseudos with their memory equivalents might have
1289 : created shared rtx. Subsequent passes would get confused
1290 : by this, so unshare everything here. */
1291 0 : unshare_all_rtl_again (first);
1292 :
1293 : #ifdef STACK_BOUNDARY
1294 : /* init_emit has set the alignment of the hard frame pointer
1295 : to STACK_BOUNDARY. It is very likely no longer valid if
1296 : the hard frame pointer was used for register allocation. */
1297 0 : if (!frame_pointer_needed)
1298 0 : REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1299 : #endif
1300 :
1301 0 : substitute_stack.release ();
1302 :
1303 0 : gcc_assert (bitmap_empty_p (&spilled_pseudos));
1304 :
1305 0 : reload_completed = !failure;
1306 :
1307 0 : return need_dce;
1308 : }
1309 :
1310 : /* Yet another special case. Unfortunately, reg-stack forces people to
1311 : write incorrect clobbers in asm statements. These clobbers must not
1312 : cause the register to appear in bad_spill_regs, otherwise we'll call
1313 : fatal_insn later. We clear the corresponding regnos in the live
1314 : register sets to avoid this.
1315 : The whole thing is rather sick, I'm afraid. */
1316 :
1317 : static void
1318 0 : maybe_fix_stack_asms (void)
1319 : {
1320 : #ifdef STACK_REGS
1321 0 : const char *constraints[MAX_RECOG_OPERANDS];
1322 0 : machine_mode operand_mode[MAX_RECOG_OPERANDS];
1323 0 : class insn_chain *chain;
1324 :
1325 0 : for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1326 : {
1327 0 : int i, noperands;
1328 0 : HARD_REG_SET clobbered, allowed;
1329 0 : rtx pat;
1330 :
1331 0 : if (! INSN_P (chain->insn)
1332 0 : || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1333 0 : continue;
1334 0 : pat = PATTERN (chain->insn);
1335 0 : if (GET_CODE (pat) != PARALLEL)
1336 0 : continue;
1337 :
1338 0 : CLEAR_HARD_REG_SET (clobbered);
1339 0 : CLEAR_HARD_REG_SET (allowed);
1340 :
1341 : /* First, make a mask of all stack regs that are clobbered. */
1342 0 : for (i = 0; i < XVECLEN (pat, 0); i++)
1343 : {
1344 0 : rtx t = XVECEXP (pat, 0, i);
1345 0 : if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1346 0 : SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1347 : }
1348 :
1349 : /* Get the operand values and constraints out of the insn. */
1350 0 : decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1351 : constraints, operand_mode, NULL);
1352 :
1353 : /* For every operand, see what registers are allowed. */
1354 0 : for (i = 0; i < noperands; i++)
1355 : {
1356 0 : const char *p = constraints[i];
1357 : /* For every alternative, we compute the class of registers allowed
1358 : for reloading in CLS, and merge its contents into the reg set
1359 : ALLOWED. */
1360 0 : int cls = (int) NO_REGS;
1361 :
1362 0 : for (;;)
1363 : {
1364 0 : char c = *p;
1365 :
1366 0 : if (c == '\0' || c == ',' || c == '#')
1367 : {
1368 : /* End of one alternative - mark the regs in the current
1369 : class, and reset the class. */
1370 0 : allowed |= reg_class_contents[cls];
1371 0 : cls = NO_REGS;
1372 0 : p++;
1373 0 : if (c == '#')
1374 0 : do {
1375 0 : c = *p++;
1376 0 : } while (c != '\0' && c != ',');
1377 0 : if (c == '\0')
1378 : break;
1379 0 : continue;
1380 : }
1381 :
1382 0 : switch (c)
1383 : {
1384 0 : case 'g':
1385 0 : cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 0 : break;
1387 :
1388 0 : default:
1389 0 : enum constraint_num cn = lookup_constraint (p);
1390 0 : if (insn_extra_address_constraint (cn))
1391 0 : cls = (int) reg_class_subunion[cls]
1392 0 : [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1393 0 : ADDRESS, SCRATCH, chain->insn)];
1394 : else
1395 0 : cls = (int) reg_class_subunion[cls]
1396 0 : [reg_class_for_constraint (cn)];
1397 : break;
1398 : }
1399 0 : p += CONSTRAINT_LEN (c, p);
1400 : }
1401 : }
1402 : /* Those of the registers which are clobbered, but allowed by the
1403 : constraints, must be usable as reload registers. So clear them
1404 : out of the life information. */
1405 0 : allowed &= clobbered;
1406 0 : hard_reg_set_iterator hrsi;
1407 0 : unsigned int j = 0;
1408 0 : EXECUTE_IF_SET_IN_HARD_REG_SET (allowed, 0, j, hrsi)
1409 : {
1410 0 : CLEAR_REGNO_REG_SET (&chain->live_throughout, j);
1411 0 : CLEAR_REGNO_REG_SET (&chain->dead_or_set, j);
1412 : }
1413 : }
1414 :
1415 : #endif
1416 0 : }
1417 :
1418 : /* Copy the global variables n_reloads and rld into the corresponding elts
1419 : of CHAIN. */
1420 : static void
1421 0 : copy_reloads (class insn_chain *chain)
1422 : {
1423 0 : chain->n_reloads = n_reloads;
1424 0 : chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1425 0 : memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1426 0 : reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1427 0 : }
1428 :
1429 : /* Walk the chain of insns, and determine for each whether it needs reloads
1430 : and/or eliminations. Build the corresponding insns_need_reload list, and
1431 : set something_needs_elimination as appropriate. */
1432 : static void
1433 0 : calculate_needs_all_insns (int global)
1434 : {
1435 0 : class insn_chain **pprev_reload = &insns_need_reload;
1436 0 : class insn_chain *chain, *next = 0;
1437 :
1438 0 : something_needs_elimination = 0;
1439 :
1440 0 : reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1441 0 : for (chain = reload_insn_chain; chain != 0; chain = next)
1442 : {
1443 0 : rtx_insn *insn = chain->insn;
1444 :
1445 0 : next = chain->next;
1446 :
1447 : /* Clear out the shortcuts. */
1448 0 : chain->n_reloads = 0;
1449 0 : chain->need_elim = 0;
1450 0 : chain->need_reload = 0;
1451 0 : chain->need_operand_change = 0;
1452 :
1453 : /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1454 : include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1455 : what effects this has on the known offsets at labels. */
1456 :
1457 0 : if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1458 0 : || (INSN_P (insn) && REG_NOTES (insn) != 0))
1459 0 : set_label_offsets (insn, insn, 0);
1460 :
1461 0 : if (INSN_P (insn))
1462 : {
1463 0 : rtx old_body = PATTERN (insn);
1464 0 : int old_code = INSN_CODE (insn);
1465 0 : rtx old_notes = REG_NOTES (insn);
1466 0 : int did_elimination = 0;
1467 0 : int operands_changed = 0;
1468 :
1469 : /* Skip insns that only set an equivalence. */
1470 0 : if (will_delete_init_insn_p (insn))
1471 0 : continue;
1472 :
1473 : /* If needed, eliminate any eliminable registers. */
1474 0 : if (num_eliminable || num_eliminable_invariants)
1475 0 : did_elimination = eliminate_regs_in_insn (insn, 0);
1476 :
1477 : /* Analyze the instruction. */
1478 0 : operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1479 : global, spill_reg_order);
1480 :
1481 : /* If a no-op set needs more than one reload, this is likely
1482 : to be something that needs input address reloads. We
1483 : can't get rid of this cleanly later, and it is of no use
1484 : anyway, so discard it now.
1485 : We only do this when expensive_optimizations is enabled,
1486 : since this complements reload inheritance / output
1487 : reload deletion, and it can make debugging harder. */
1488 0 : if (flag_expensive_optimizations && n_reloads > 1)
1489 : {
1490 0 : rtx set = single_set (insn);
1491 0 : if (set
1492 0 : &&
1493 0 : ((SET_SRC (set) == SET_DEST (set)
1494 0 : && REG_P (SET_SRC (set))
1495 0 : && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1496 0 : || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1497 0 : && reg_renumber[REGNO (SET_SRC (set))] < 0
1498 0 : && reg_renumber[REGNO (SET_DEST (set))] < 0
1499 0 : && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1500 0 : && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1501 0 : && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1502 0 : reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1503 : {
1504 0 : if (ira_conflicts_p)
1505 : /* Inform IRA about the insn deletion. */
1506 0 : ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1507 0 : REGNO (SET_SRC (set)));
1508 0 : delete_insn (insn);
1509 : /* Delete it from the reload chain. */
1510 0 : if (chain->prev)
1511 0 : chain->prev->next = next;
1512 : else
1513 0 : reload_insn_chain = next;
1514 0 : if (next)
1515 0 : next->prev = chain->prev;
1516 0 : chain->next = unused_insn_chains;
1517 0 : unused_insn_chains = chain;
1518 0 : continue;
1519 : }
1520 : }
1521 0 : if (num_eliminable)
1522 0 : update_eliminable_offsets ();
1523 :
1524 : /* Remember for later shortcuts which insns had any reloads or
1525 : register eliminations. */
1526 0 : chain->need_elim = did_elimination;
1527 0 : chain->need_reload = n_reloads > 0;
1528 0 : chain->need_operand_change = operands_changed;
1529 :
1530 : /* Discard any register replacements done. */
1531 0 : if (did_elimination)
1532 : {
1533 0 : obstack_free (&reload_obstack, reload_insn_firstobj);
1534 0 : PATTERN (insn) = old_body;
1535 0 : INSN_CODE (insn) = old_code;
1536 0 : REG_NOTES (insn) = old_notes;
1537 0 : something_needs_elimination = 1;
1538 : }
1539 :
1540 0 : something_needs_operands_changed |= operands_changed;
1541 :
1542 0 : if (n_reloads != 0)
1543 : {
1544 0 : copy_reloads (chain);
1545 0 : *pprev_reload = chain;
1546 0 : pprev_reload = &chain->next_need_reload;
1547 : }
1548 : }
1549 : }
1550 0 : *pprev_reload = 0;
1551 0 : }
1552 :
1553 : /* This function is called from the register allocator to set up estimates
1554 : for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1555 : an invariant. The structure is similar to calculate_needs_all_insns. */
1556 :
1557 : void
1558 0 : calculate_elim_costs_all_insns (void)
1559 : {
1560 0 : int *reg_equiv_init_cost;
1561 0 : basic_block bb;
1562 0 : int i;
1563 :
1564 0 : reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1565 0 : init_elim_table ();
1566 0 : init_eliminable_invariants (get_insns (), false);
1567 :
1568 0 : set_initial_elim_offsets ();
1569 0 : set_initial_label_offsets ();
1570 :
1571 0 : FOR_EACH_BB_FN (bb, cfun)
1572 : {
1573 0 : rtx_insn *insn;
1574 0 : elim_bb = bb;
1575 :
1576 0 : FOR_BB_INSNS (bb, insn)
1577 : {
1578 : /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1579 : include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1580 : what effects this has on the known offsets at labels. */
1581 :
1582 0 : if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1583 0 : || (INSN_P (insn) && REG_NOTES (insn) != 0))
1584 0 : set_label_offsets (insn, insn, 0);
1585 :
1586 0 : if (INSN_P (insn))
1587 : {
1588 0 : rtx set = single_set (insn);
1589 :
1590 : /* Skip insns that only set an equivalence. */
1591 0 : if (set && REG_P (SET_DEST (set))
1592 0 : && reg_renumber[REGNO (SET_DEST (set))] < 0
1593 0 : && (reg_equiv_constant (REGNO (SET_DEST (set)))
1594 0 : || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1595 : {
1596 0 : unsigned regno = REGNO (SET_DEST (set));
1597 0 : rtx_insn_list *init = reg_equiv_init (regno);
1598 0 : if (init)
1599 : {
1600 0 : rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1601 : false, true);
1602 0 : machine_mode mode = GET_MODE (SET_DEST (set));
1603 0 : int cost = set_src_cost (t, mode,
1604 0 : optimize_bb_for_speed_p (bb));
1605 0 : int freq = REG_FREQ_FROM_BB (bb);
1606 :
1607 0 : reg_equiv_init_cost[regno] = cost * freq;
1608 0 : continue;
1609 0 : }
1610 : }
1611 : /* If needed, eliminate any eliminable registers. */
1612 0 : if (num_eliminable || num_eliminable_invariants)
1613 0 : elimination_costs_in_insn (insn);
1614 :
1615 0 : if (num_eliminable)
1616 0 : update_eliminable_offsets ();
1617 : }
1618 : }
1619 : }
1620 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1621 : {
1622 0 : if (reg_equiv_invariant (i))
1623 : {
1624 0 : if (reg_equiv_init (i))
1625 : {
1626 0 : int cost = reg_equiv_init_cost[i];
1627 0 : if (dump_file)
1628 0 : fprintf (dump_file,
1629 : "Reg %d has equivalence, initial gains %d\n", i, cost);
1630 0 : if (cost != 0)
1631 0 : ira_adjust_equiv_reg_cost (i, cost);
1632 : }
1633 : else
1634 : {
1635 0 : if (dump_file)
1636 0 : fprintf (dump_file,
1637 : "Reg %d had equivalence, but can't be eliminated\n",
1638 : i);
1639 0 : ira_adjust_equiv_reg_cost (i, 0);
1640 : }
1641 : }
1642 : }
1643 :
1644 0 : free (reg_equiv_init_cost);
1645 0 : free (offsets_known_at);
1646 0 : free (offsets_at);
1647 0 : offsets_at = NULL;
1648 0 : offsets_known_at = NULL;
1649 0 : }
1650 :
1651 : /* Comparison function for qsort to decide which of two reloads
1652 : should be handled first. *P1 and *P2 are the reload numbers. */
1653 :
1654 : static int
1655 0 : reload_reg_class_lower (const void *r1p, const void *r2p)
1656 : {
1657 0 : int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1658 0 : int t;
1659 :
1660 : /* Consider required reloads before optional ones. */
1661 0 : t = rld[r1].optional - rld[r2].optional;
1662 0 : if (t != 0)
1663 : return t;
1664 :
1665 : /* Count all solitary classes before non-solitary ones. */
1666 0 : t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1667 0 : - (reg_class_size[(int) rld[r1].rclass] == 1));
1668 0 : if (t != 0)
1669 : return t;
1670 :
1671 : /* Aside from solitaires, consider all multi-reg groups first. */
1672 0 : t = rld[r2].nregs - rld[r1].nregs;
1673 0 : if (t != 0)
1674 : return t;
1675 :
1676 : /* Consider reloads in order of increasing reg-class number. */
1677 0 : t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1678 0 : if (t != 0)
1679 : return t;
1680 :
1681 : /* If reloads are equally urgent, sort by reload number,
1682 : so that the results of qsort leave nothing to chance. */
1683 0 : return r1 - r2;
1684 : }
1685 :
1686 : /* The cost of spilling each hard reg. */
1687 : static int spill_cost[FIRST_PSEUDO_REGISTER];
1688 :
1689 : /* When spilling multiple hard registers, we use SPILL_COST for the first
1690 : spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1691 : only the first hard reg for a multi-reg pseudo. */
1692 : static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1693 :
1694 : /* Map of hard regno to pseudo regno currently occupying the hard
1695 : reg. */
1696 : static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1697 :
1698 : /* Update the spill cost arrays, considering that pseudo REG is live. */
1699 :
1700 : static void
1701 0 : count_pseudo (int reg)
1702 : {
1703 0 : int freq = REG_FREQ (reg);
1704 0 : int r = reg_renumber[reg];
1705 0 : int nregs;
1706 :
1707 : /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1708 0 : if (ira_conflicts_p && r < 0)
1709 : return;
1710 :
1711 0 : if (REGNO_REG_SET_P (&pseudos_counted, reg)
1712 0 : || REGNO_REG_SET_P (&spilled_pseudos, reg))
1713 0 : return;
1714 :
1715 0 : SET_REGNO_REG_SET (&pseudos_counted, reg);
1716 :
1717 0 : gcc_assert (r >= 0);
1718 :
1719 0 : spill_add_cost[r] += freq;
1720 0 : nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1721 0 : while (nregs-- > 0)
1722 : {
1723 0 : hard_regno_to_pseudo_regno[r + nregs] = reg;
1724 0 : spill_cost[r + nregs] += freq;
1725 : }
1726 : }
1727 :
1728 : /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1729 : contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1730 :
1731 : static void
1732 0 : order_regs_for_reload (class insn_chain *chain)
1733 : {
1734 0 : unsigned i;
1735 0 : HARD_REG_SET used_by_pseudos;
1736 0 : HARD_REG_SET used_by_pseudos2;
1737 0 : reg_set_iterator rsi;
1738 :
1739 0 : bad_spill_regs = fixed_reg_set;
1740 :
1741 0 : memset (spill_cost, 0, sizeof spill_cost);
1742 0 : memset (spill_add_cost, 0, sizeof spill_add_cost);
1743 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1744 0 : hard_regno_to_pseudo_regno[i] = -1;
1745 :
1746 : /* Count number of uses of each hard reg by pseudo regs allocated to it
1747 : and then order them by decreasing use. First exclude hard registers
1748 : that are live in or across this insn. */
1749 :
1750 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1751 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1752 0 : bad_spill_regs |= used_by_pseudos;
1753 0 : bad_spill_regs |= used_by_pseudos2;
1754 :
1755 : /* Now find out which pseudos are allocated to it, and update
1756 : hard_reg_n_uses. */
1757 0 : CLEAR_REG_SET (&pseudos_counted);
1758 :
1759 0 : EXECUTE_IF_SET_IN_REG_SET
1760 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1761 : {
1762 0 : count_pseudo (i);
1763 : }
1764 0 : EXECUTE_IF_SET_IN_REG_SET
1765 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1766 : {
1767 0 : count_pseudo (i);
1768 : }
1769 0 : CLEAR_REG_SET (&pseudos_counted);
1770 0 : }
1771 :
1772 : /* Vector of reload-numbers showing the order in which the reloads should
1773 : be processed. */
1774 : static short reload_order[MAX_RELOADS];
1775 :
1776 : /* This is used to keep track of the spill regs used in one insn. */
1777 : static HARD_REG_SET used_spill_regs_local;
1778 :
1779 : /* We decided to spill hard register SPILLED, which has a size of
1780 : SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1781 : is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1782 : update SPILL_COST/SPILL_ADD_COST. */
1783 :
1784 : static void
1785 0 : count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1786 : {
1787 0 : int freq = REG_FREQ (reg);
1788 0 : int r = reg_renumber[reg];
1789 0 : int nregs;
1790 :
1791 : /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1792 0 : if (ira_conflicts_p && r < 0)
1793 : return;
1794 :
1795 0 : gcc_assert (r >= 0);
1796 :
1797 0 : nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1798 :
1799 0 : if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1800 0 : || spilled + spilled_nregs <= r || r + nregs <= spilled)
1801 : return;
1802 :
1803 0 : SET_REGNO_REG_SET (&spilled_pseudos, reg);
1804 :
1805 0 : spill_add_cost[r] -= freq;
1806 0 : while (nregs-- > 0)
1807 : {
1808 0 : hard_regno_to_pseudo_regno[r + nregs] = -1;
1809 0 : spill_cost[r + nregs] -= freq;
1810 : }
1811 : }
1812 :
1813 : /* Find reload register to use for reload number ORDER. */
1814 :
1815 : static int
1816 0 : find_reg (class insn_chain *chain, int order)
1817 : {
1818 0 : int rnum = reload_order[order];
1819 0 : struct reload *rl = rld + rnum;
1820 0 : int best_cost = INT_MAX;
1821 0 : int best_reg = -1;
1822 0 : unsigned int i, j, n;
1823 0 : int k;
1824 0 : HARD_REG_SET not_usable;
1825 0 : HARD_REG_SET used_by_other_reload;
1826 0 : reg_set_iterator rsi;
1827 0 : static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1828 0 : static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1829 :
1830 0 : not_usable = (bad_spill_regs
1831 0 : | bad_spill_regs_global
1832 0 : | ~reg_class_contents[rl->rclass]);
1833 :
1834 0 : CLEAR_HARD_REG_SET (used_by_other_reload);
1835 0 : for (k = 0; k < order; k++)
1836 : {
1837 0 : int other = reload_order[k];
1838 :
1839 0 : if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1840 0 : for (j = 0; j < rld[other].nregs; j++)
1841 0 : SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1842 : }
1843 :
1844 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1845 : {
1846 : #ifdef REG_ALLOC_ORDER
1847 0 : unsigned int regno = reg_alloc_order[i];
1848 : #else
1849 : unsigned int regno = i;
1850 : #endif
1851 :
1852 0 : if (! TEST_HARD_REG_BIT (not_usable, regno)
1853 0 : && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1854 0 : && targetm.hard_regno_mode_ok (regno, rl->mode))
1855 : {
1856 0 : int this_cost = spill_cost[regno];
1857 0 : int ok = 1;
1858 0 : unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1859 :
1860 0 : for (j = 1; j < this_nregs; j++)
1861 : {
1862 0 : this_cost += spill_add_cost[regno + j];
1863 0 : if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1864 0 : || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1865 : ok = 0;
1866 : }
1867 0 : if (! ok)
1868 0 : continue;
1869 :
1870 0 : if (ira_conflicts_p)
1871 : {
1872 : /* Ask IRA to find a better pseudo-register for
1873 : spilling. */
1874 0 : for (n = j = 0; j < this_nregs; j++)
1875 : {
1876 0 : int r = hard_regno_to_pseudo_regno[regno + j];
1877 :
1878 0 : if (r < 0)
1879 0 : continue;
1880 0 : if (n == 0 || regno_pseudo_regs[n - 1] != r)
1881 0 : regno_pseudo_regs[n++] = r;
1882 : }
1883 0 : regno_pseudo_regs[n++] = -1;
1884 0 : if (best_reg < 0
1885 0 : || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1886 : best_regno_pseudo_regs,
1887 : rl->in, rl->out,
1888 : chain->insn))
1889 : {
1890 0 : best_reg = regno;
1891 0 : for (j = 0;; j++)
1892 : {
1893 0 : best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1894 0 : if (regno_pseudo_regs[j] < 0)
1895 : break;
1896 : }
1897 : }
1898 0 : continue;
1899 0 : }
1900 :
1901 0 : if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1902 0 : this_cost--;
1903 0 : if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1904 0 : this_cost--;
1905 0 : if (this_cost < best_cost
1906 : /* Among registers with equal cost, prefer caller-saved ones, or
1907 : use REG_ALLOC_ORDER if it is defined. */
1908 0 : || (this_cost == best_cost
1909 : #ifdef REG_ALLOC_ORDER
1910 0 : && (inv_reg_alloc_order[regno]
1911 0 : < inv_reg_alloc_order[best_reg])
1912 : #else
1913 : && crtl->abi->clobbers_full_reg_p (regno)
1914 : && !crtl->abi->clobbers_full_reg_p (best_reg)
1915 : #endif
1916 : ))
1917 : {
1918 0 : best_reg = regno;
1919 0 : best_cost = this_cost;
1920 : }
1921 : }
1922 : }
1923 0 : if (best_reg == -1)
1924 : return 0;
1925 :
1926 0 : if (dump_file)
1927 0 : fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1928 :
1929 0 : rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1930 0 : rl->regno = best_reg;
1931 :
1932 0 : EXECUTE_IF_SET_IN_REG_SET
1933 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1934 : {
1935 0 : count_spilled_pseudo (best_reg, rl->nregs, j);
1936 : }
1937 :
1938 0 : EXECUTE_IF_SET_IN_REG_SET
1939 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1940 : {
1941 0 : count_spilled_pseudo (best_reg, rl->nregs, j);
1942 : }
1943 :
1944 0 : for (i = 0; i < rl->nregs; i++)
1945 : {
1946 0 : gcc_assert (spill_cost[best_reg + i] == 0);
1947 0 : gcc_assert (spill_add_cost[best_reg + i] == 0);
1948 0 : gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1949 0 : SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1950 : }
1951 : return 1;
1952 : }
1953 :
1954 : /* Find more reload regs to satisfy the remaining need of an insn, which
1955 : is given by CHAIN.
1956 : Do it by ascending class number, since otherwise a reg
1957 : might be spilled for a big class and might fail to count
1958 : for a smaller class even though it belongs to that class. */
1959 :
1960 : static void
1961 0 : find_reload_regs (class insn_chain *chain)
1962 : {
1963 0 : int i;
1964 :
1965 : /* In order to be certain of getting the registers we need,
1966 : we must sort the reloads into order of increasing register class.
1967 : Then our grabbing of reload registers will parallel the process
1968 : that provided the reload registers. */
1969 0 : for (i = 0; i < chain->n_reloads; i++)
1970 : {
1971 : /* Show whether this reload already has a hard reg. */
1972 0 : if (chain->rld[i].reg_rtx)
1973 : {
1974 0 : chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1975 0 : chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1976 : }
1977 : else
1978 0 : chain->rld[i].regno = -1;
1979 0 : reload_order[i] = i;
1980 : }
1981 :
1982 0 : n_reloads = chain->n_reloads;
1983 0 : memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1984 :
1985 0 : CLEAR_HARD_REG_SET (used_spill_regs_local);
1986 :
1987 0 : if (dump_file)
1988 0 : fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1989 :
1990 0 : qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1991 :
1992 : /* Compute the order of preference for hard registers to spill. */
1993 :
1994 0 : order_regs_for_reload (chain);
1995 :
1996 0 : for (i = 0; i < n_reloads; i++)
1997 : {
1998 0 : int r = reload_order[i];
1999 :
2000 : /* Ignore reloads that got marked inoperative. */
2001 0 : if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2002 0 : && ! rld[r].optional
2003 0 : && rld[r].regno == -1)
2004 0 : if (! find_reg (chain, i))
2005 : {
2006 0 : if (dump_file)
2007 0 : fprintf (dump_file, "reload failure for reload %d\n", r);
2008 0 : spill_failure (chain->insn, rld[r].rclass);
2009 0 : failure = 1;
2010 0 : return;
2011 : }
2012 : }
2013 :
2014 0 : chain->used_spill_regs = used_spill_regs_local;
2015 0 : used_spill_regs |= used_spill_regs_local;
2016 :
2017 0 : memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2018 : }
2019 :
2020 : static void
2021 0 : select_reload_regs (void)
2022 : {
2023 0 : class insn_chain *chain;
2024 :
2025 : /* Try to satisfy the needs for each insn. */
2026 0 : for (chain = insns_need_reload; chain != 0;
2027 0 : chain = chain->next_need_reload)
2028 0 : find_reload_regs (chain);
2029 0 : }
2030 :
2031 : /* Delete all insns that were inserted by emit_caller_save_insns during
2032 : this iteration. */
2033 : static void
2034 0 : delete_caller_save_insns (void)
2035 : {
2036 0 : class insn_chain *c = reload_insn_chain;
2037 :
2038 0 : while (c != 0)
2039 : {
2040 0 : while (c != 0 && c->is_caller_save_insn)
2041 : {
2042 0 : class insn_chain *next = c->next;
2043 0 : rtx_insn *insn = c->insn;
2044 :
2045 0 : if (c == reload_insn_chain)
2046 0 : reload_insn_chain = next;
2047 0 : delete_insn (insn);
2048 :
2049 0 : if (next)
2050 0 : next->prev = c->prev;
2051 0 : if (c->prev)
2052 0 : c->prev->next = next;
2053 0 : c->next = unused_insn_chains;
2054 0 : unused_insn_chains = c;
2055 0 : c = next;
2056 : }
2057 0 : if (c != 0)
2058 0 : c = c->next;
2059 : }
2060 0 : }
2061 :
2062 : /* Handle the failure to find a register to spill.
2063 : INSN should be one of the insns which needed this particular spill reg. */
2064 :
2065 : static void
2066 0 : spill_failure (rtx_insn *insn, enum reg_class rclass)
2067 : {
2068 0 : if (asm_noperands (PATTERN (insn)) >= 0)
2069 0 : error_for_asm (insn, "cannot find a register in class %qs while "
2070 : "reloading %<asm%>",
2071 0 : reg_class_names[rclass]);
2072 : else
2073 : {
2074 0 : error ("unable to find a register to spill in class %qs",
2075 0 : reg_class_names[rclass]);
2076 :
2077 0 : if (dump_file)
2078 : {
2079 0 : fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2080 0 : debug_reload_to_stream (dump_file);
2081 : }
2082 0 : fatal_insn ("this is the insn:", insn);
2083 : }
2084 0 : }
2085 :
2086 : /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2087 : data that is dead in INSN. */
2088 :
2089 : static void
2090 0 : delete_dead_insn (rtx_insn *insn)
2091 : {
2092 0 : rtx_insn *prev = prev_active_insn (insn);
2093 0 : rtx prev_dest;
2094 :
2095 : /* If the previous insn sets a register that dies in our insn make
2096 : a note that we want to run DCE immediately after reload.
2097 :
2098 : We used to delete the previous insn & recurse, but that's wrong for
2099 : block local equivalences. Instead of trying to figure out the exact
2100 : circumstances where we can delete the potentially dead insns, just
2101 : let DCE do the job. */
2102 0 : if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2103 0 : && GET_CODE (PATTERN (prev)) == SET
2104 0 : && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2105 0 : && reg_mentioned_p (prev_dest, PATTERN (insn))
2106 0 : && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2107 0 : && ! side_effects_p (SET_SRC (PATTERN (prev))))
2108 0 : need_dce = 1;
2109 :
2110 0 : SET_INSN_DELETED (insn);
2111 0 : }
2112 :
2113 : /* Modify the home of pseudo-reg I.
2114 : The new home is present in reg_renumber[I].
2115 :
2116 : FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2117 : or it may be -1, meaning there is none or it is not relevant.
2118 : This is used so that all pseudos spilled from a given hard reg
2119 : can share one stack slot. */
2120 :
2121 : static void
2122 0 : alter_reg (int i, int from_reg, bool dont_share_p)
2123 : {
2124 : /* When outputting an inline function, this can happen
2125 : for a reg that isn't actually used. */
2126 0 : if (regno_reg_rtx[i] == 0)
2127 : return;
2128 :
2129 : /* If the reg got changed to a MEM at rtl-generation time,
2130 : ignore it. */
2131 0 : if (!REG_P (regno_reg_rtx[i]))
2132 : return;
2133 :
2134 : /* Modify the reg-rtx to contain the new hard reg
2135 : number or else to contain its pseudo reg number. */
2136 0 : SET_REGNO (regno_reg_rtx[i],
2137 : reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2138 :
2139 : /* If we have a pseudo that is needed but has no hard reg or equivalent,
2140 : allocate a stack slot for it. */
2141 :
2142 0 : if (reg_renumber[i] < 0
2143 0 : && REG_N_REFS (i) > 0
2144 0 : && reg_equiv_constant (i) == 0
2145 0 : && (reg_equiv_invariant (i) == 0
2146 0 : || reg_equiv_init (i) == 0)
2147 0 : && reg_equiv_memory_loc (i) == 0)
2148 : {
2149 0 : rtx x = NULL_RTX;
2150 0 : machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2151 0 : poly_uint64 inherent_size = GET_MODE_SIZE (mode);
2152 0 : unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2153 0 : machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2154 0 : poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
2155 : /* ??? Seems strange to derive the minimum alignment from the size,
2156 : but that's the traditional behavior. For polynomial-size modes,
2157 : the natural extension is to use the minimum possible size. */
2158 0 : unsigned int min_align
2159 0 : = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
2160 0 : poly_int64 adjust = 0;
2161 :
2162 0 : something_was_spilled = true;
2163 :
2164 0 : if (ira_conflicts_p)
2165 : {
2166 : /* Mark the spill for IRA. */
2167 0 : SET_REGNO_REG_SET (&spilled_pseudos, i);
2168 0 : if (!dont_share_p)
2169 0 : x = ira_reuse_stack_slot (i, inherent_size, total_size);
2170 : }
2171 :
2172 0 : if (x)
2173 : ;
2174 :
2175 : /* Each pseudo reg has an inherent size which comes from its own mode,
2176 : and a total size which provides room for paradoxical subregs
2177 : which refer to the pseudo reg in wider modes.
2178 :
2179 : We can use a slot already allocated if it provides both
2180 : enough inherent space and enough total space.
2181 : Otherwise, we allocate a new slot, making sure that it has no less
2182 : inherent space, and no less total space, then the previous slot. */
2183 0 : else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2184 : {
2185 0 : rtx stack_slot;
2186 :
2187 : /* The sizes are taken from a subreg operation, which guarantees
2188 : that they're ordered. */
2189 0 : gcc_checking_assert (ordered_p (total_size, inherent_size));
2190 :
2191 : /* No known place to spill from => no slot to reuse. */
2192 0 : x = assign_stack_local (mode, total_size,
2193 : min_align > inherent_align
2194 0 : || maybe_gt (total_size, inherent_size)
2195 : ? -1 : 0);
2196 :
2197 0 : stack_slot = x;
2198 :
2199 : /* Cancel the big-endian correction done in assign_stack_local.
2200 : Get the address of the beginning of the slot. This is so we
2201 : can do a big-endian correction unconditionally below. */
2202 0 : if (BYTES_BIG_ENDIAN)
2203 : {
2204 : adjust = inherent_size - total_size;
2205 : if (maybe_ne (adjust, 0))
2206 : {
2207 : poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2208 : machine_mode mem_mode
2209 : = int_mode_for_size (total_bits, 1).else_blk ();
2210 : stack_slot = adjust_address_nv (x, mem_mode, adjust);
2211 : }
2212 : }
2213 :
2214 0 : if (! dont_share_p && ira_conflicts_p)
2215 : /* Inform IRA about allocation a new stack slot. */
2216 0 : ira_mark_new_stack_slot (stack_slot, i, total_size);
2217 : }
2218 :
2219 : /* Reuse a stack slot if possible. */
2220 0 : else if (spill_stack_slot[from_reg] != 0
2221 0 : && known_ge (spill_stack_slot_width[from_reg], total_size)
2222 0 : && known_ge (GET_MODE_SIZE
2223 : (GET_MODE (spill_stack_slot[from_reg])),
2224 : inherent_size)
2225 0 : && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2226 : x = spill_stack_slot[from_reg];
2227 :
2228 : /* Allocate a bigger slot. */
2229 : else
2230 : {
2231 : /* Compute maximum size needed, both for inherent size
2232 : and for total size. */
2233 0 : rtx stack_slot;
2234 :
2235 0 : if (spill_stack_slot[from_reg])
2236 : {
2237 0 : if (partial_subreg_p (mode,
2238 0 : GET_MODE (spill_stack_slot[from_reg])))
2239 0 : mode = GET_MODE (spill_stack_slot[from_reg]);
2240 0 : total_size = ordered_max (total_size,
2241 0 : spill_stack_slot_width[from_reg]);
2242 0 : if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2243 : min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2244 : }
2245 :
2246 : /* The sizes are taken from a subreg operation, which guarantees
2247 : that they're ordered. */
2248 0 : gcc_checking_assert (ordered_p (total_size, inherent_size));
2249 :
2250 : /* Make a slot with that size. */
2251 0 : x = assign_stack_local (mode, total_size,
2252 : min_align > inherent_align
2253 0 : || maybe_gt (total_size, inherent_size)
2254 : ? -1 : 0);
2255 0 : stack_slot = x;
2256 :
2257 : /* Cancel the big-endian correction done in assign_stack_local.
2258 : Get the address of the beginning of the slot. This is so we
2259 : can do a big-endian correction unconditionally below. */
2260 0 : if (BYTES_BIG_ENDIAN)
2261 : {
2262 : adjust = GET_MODE_SIZE (mode) - total_size;
2263 : if (maybe_ne (adjust, 0))
2264 : {
2265 : poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2266 : machine_mode mem_mode
2267 : = int_mode_for_size (total_bits, 1).else_blk ();
2268 : stack_slot = adjust_address_nv (x, mem_mode, adjust);
2269 : }
2270 : }
2271 :
2272 0 : spill_stack_slot[from_reg] = stack_slot;
2273 0 : spill_stack_slot_width[from_reg] = total_size;
2274 : }
2275 :
2276 : /* On a big endian machine, the "address" of the slot
2277 : is the address of the low part that fits its inherent mode. */
2278 0 : adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2279 :
2280 : /* If we have any adjustment to make, or if the stack slot is the
2281 : wrong mode, make a new stack slot. */
2282 0 : x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2283 :
2284 : /* Set all of the memory attributes as appropriate for a spill. */
2285 0 : set_mem_attrs_for_spill (x);
2286 :
2287 : /* Save the stack slot for later. */
2288 0 : reg_equiv_memory_loc (i) = x;
2289 : }
2290 : }
2291 :
2292 : /* Mark the slots in regs_ever_live for the hard regs used by
2293 : pseudo-reg number REGNO, accessed in MODE. */
2294 :
2295 : static void
2296 0 : mark_home_live_1 (int regno, machine_mode mode)
2297 : {
2298 0 : int i, lim;
2299 :
2300 0 : i = reg_renumber[regno];
2301 0 : if (i < 0)
2302 : return;
2303 0 : lim = end_hard_regno (mode, i);
2304 0 : while (i < lim)
2305 0 : df_set_regs_ever_live (i++, true);
2306 : }
2307 :
2308 : /* Mark the slots in regs_ever_live for the hard regs
2309 : used by pseudo-reg number REGNO. */
2310 :
2311 : void
2312 0 : mark_home_live (int regno)
2313 : {
2314 0 : if (reg_renumber[regno] >= 0)
2315 0 : mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2316 0 : }
2317 :
2318 : /* This function handles the tracking of elimination offsets around branches.
2319 :
2320 : X is a piece of RTL being scanned.
2321 :
2322 : INSN is the insn that it came from, if any.
2323 :
2324 : INITIAL_P is nonzero if we are to set the offset to be the initial
2325 : offset and zero if we are setting the offset of the label to be the
2326 : current offset. */
2327 :
2328 : static void
2329 0 : set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2330 : {
2331 0 : enum rtx_code code = GET_CODE (x);
2332 0 : rtx tem;
2333 0 : unsigned int i;
2334 0 : struct elim_table *p;
2335 :
2336 0 : switch (code)
2337 : {
2338 0 : case LABEL_REF:
2339 0 : if (LABEL_REF_NONLOCAL_P (x))
2340 : return;
2341 :
2342 0 : x = label_ref_label (x);
2343 :
2344 : /* fall through */
2345 :
2346 0 : case CODE_LABEL:
2347 : /* If we know nothing about this label, set the desired offsets. Note
2348 : that this sets the offset at a label to be the offset before a label
2349 : if we don't know anything about the label. This is not correct for
2350 : the label after a BARRIER, but is the best guess we can make. If
2351 : we guessed wrong, we will suppress an elimination that might have
2352 : been possible had we been able to guess correctly. */
2353 :
2354 0 : if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2355 : {
2356 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2357 0 : offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2358 0 : = (initial_p ? reg_eliminate[i].initial_offset
2359 0 : : reg_eliminate[i].offset);
2360 0 : offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2361 : }
2362 :
2363 : /* Otherwise, if this is the definition of a label and it is
2364 : preceded by a BARRIER, set our offsets to the known offset of
2365 : that label. */
2366 :
2367 0 : else if (x == insn
2368 0 : && (tem = prev_nonnote_insn (insn)) != 0
2369 0 : && BARRIER_P (tem))
2370 0 : set_offsets_for_label (insn);
2371 : else
2372 : /* If neither of the above cases is true, compare each offset
2373 : with those previously recorded and suppress any eliminations
2374 : where the offsets disagree. */
2375 :
2376 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2377 0 : if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
2378 0 : (initial_p ? reg_eliminate[i].initial_offset
2379 0 : : reg_eliminate[i].offset)))
2380 0 : reg_eliminate[i].can_eliminate = 0;
2381 :
2382 : return;
2383 :
2384 0 : case JUMP_TABLE_DATA:
2385 0 : set_label_offsets (PATTERN (insn), insn, initial_p);
2386 0 : return;
2387 :
2388 0 : case JUMP_INSN:
2389 0 : set_label_offsets (PATTERN (insn), insn, initial_p);
2390 :
2391 : /* fall through */
2392 :
2393 0 : case INSN:
2394 0 : case CALL_INSN:
2395 : /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2396 : to indirectly and hence must have all eliminations at their
2397 : initial offsets. */
2398 0 : for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2399 0 : if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2400 0 : set_label_offsets (XEXP (tem, 0), insn, 1);
2401 : return;
2402 :
2403 : case PARALLEL:
2404 : case ADDR_VEC:
2405 : case ADDR_DIFF_VEC:
2406 : /* Each of the labels in the parallel or address vector must be
2407 : at their initial offsets. We want the first field for PARALLEL
2408 : and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2409 :
2410 0 : for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2411 0 : set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2412 : insn, initial_p);
2413 : return;
2414 :
2415 0 : case SET:
2416 : /* We only care about setting PC. If the source is not RETURN,
2417 : IF_THEN_ELSE, or a label, disable any eliminations not at
2418 : their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2419 : isn't one of those possibilities. For branches to a label,
2420 : call ourselves recursively.
2421 :
2422 : Note that this can disable elimination unnecessarily when we have
2423 : a non-local goto since it will look like a non-constant jump to
2424 : someplace in the current function. This isn't a significant
2425 : problem since such jumps will normally be when all elimination
2426 : pairs are back to their initial offsets. */
2427 :
2428 0 : if (SET_DEST (x) != pc_rtx)
2429 : return;
2430 :
2431 0 : switch (GET_CODE (SET_SRC (x)))
2432 : {
2433 : case PC:
2434 : case RETURN:
2435 : return;
2436 :
2437 : case LABEL_REF:
2438 : set_label_offsets (SET_SRC (x), insn, initial_p);
2439 : return;
2440 :
2441 0 : case IF_THEN_ELSE:
2442 0 : tem = XEXP (SET_SRC (x), 1);
2443 0 : if (GET_CODE (tem) == LABEL_REF)
2444 0 : set_label_offsets (label_ref_label (tem), insn, initial_p);
2445 0 : else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2446 : break;
2447 :
2448 0 : tem = XEXP (SET_SRC (x), 2);
2449 0 : if (GET_CODE (tem) == LABEL_REF)
2450 0 : set_label_offsets (label_ref_label (tem), insn, initial_p);
2451 0 : else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2452 : break;
2453 : return;
2454 :
2455 : default:
2456 : break;
2457 : }
2458 :
2459 : /* If we reach here, all eliminations must be at their initial
2460 : offset because we are doing a jump to a variable address. */
2461 0 : for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2462 0 : if (maybe_ne (p->offset, p->initial_offset))
2463 0 : p->can_eliminate = 0;
2464 : break;
2465 :
2466 : default:
2467 : break;
2468 : }
2469 : }
2470 :
2471 : /* This function examines every reg that occurs in X and adjusts the
2472 : costs for its elimination which are gathered by IRA. INSN is the
2473 : insn in which X occurs. We do not recurse into MEM expressions. */
2474 :
2475 : static void
2476 0 : note_reg_elim_costly (const_rtx x, rtx insn)
2477 : {
2478 0 : subrtx_iterator::array_type array;
2479 0 : FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2480 : {
2481 0 : const_rtx x = *iter;
2482 0 : if (MEM_P (x))
2483 0 : iter.skip_subrtxes ();
2484 0 : else if (REG_P (x)
2485 0 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
2486 0 : && reg_equiv_init (REGNO (x))
2487 0 : && reg_equiv_invariant (REGNO (x)))
2488 : {
2489 0 : rtx t = reg_equiv_invariant (REGNO (x));
2490 0 : rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2491 0 : int cost = set_src_cost (new_rtx, Pmode,
2492 0 : optimize_bb_for_speed_p (elim_bb));
2493 0 : int freq = REG_FREQ_FROM_BB (elim_bb);
2494 :
2495 0 : if (cost != 0)
2496 0 : ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2497 : }
2498 : }
2499 0 : }
2500 :
2501 : /* Scan X and replace any eliminable registers (such as fp) with a
2502 : replacement (such as sp), plus an offset.
2503 :
2504 : MEM_MODE is the mode of an enclosing MEM. We need this to know how
2505 : much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2506 : MEM, we are allowed to replace a sum of a register and the constant zero
2507 : with the register, which we cannot do outside a MEM. In addition, we need
2508 : to record the fact that a register is referenced outside a MEM.
2509 :
2510 : If INSN is an insn, it is the insn containing X. If we replace a REG
2511 : in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2512 : CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2513 : the REG is being modified.
2514 :
2515 : Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2516 : That's used when we eliminate in expressions stored in notes.
2517 : This means, do not set ref_outside_mem even if the reference
2518 : is outside of MEMs.
2519 :
2520 : If FOR_COSTS is true, we are being called before reload in order to
2521 : estimate the costs of keeping registers with an equivalence unallocated.
2522 :
2523 : REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2524 : replacements done assuming all offsets are at their initial values. If
2525 : they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2526 : encounter, return the actual location so that find_reloads will do
2527 : the proper thing. */
2528 :
2529 : static rtx
2530 0 : eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2531 : bool may_use_invariant, bool for_costs)
2532 : {
2533 0 : enum rtx_code code = GET_CODE (x);
2534 0 : struct elim_table *ep;
2535 0 : int regno;
2536 0 : rtx new_rtx;
2537 0 : int i, j;
2538 0 : const char *fmt;
2539 0 : int copied = 0;
2540 :
2541 0 : if (! current_function_decl)
2542 : return x;
2543 :
2544 0 : switch (code)
2545 : {
2546 : CASE_CONST_ANY:
2547 : case CONST:
2548 : case SYMBOL_REF:
2549 : case CODE_LABEL:
2550 : case PC:
2551 : case ASM_INPUT:
2552 : case ADDR_VEC:
2553 : case ADDR_DIFF_VEC:
2554 : case RETURN:
2555 : return x;
2556 :
2557 0 : case REG:
2558 0 : regno = REGNO (x);
2559 :
2560 : /* First handle the case where we encounter a bare register that
2561 : is eliminable. Replace it with a PLUS. */
2562 0 : if (regno < FIRST_PSEUDO_REGISTER)
2563 : {
2564 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2565 : ep++)
2566 0 : if (ep->from_rtx == x && ep->can_eliminate)
2567 0 : return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2568 :
2569 : }
2570 0 : else if (reg_renumber && reg_renumber[regno] < 0
2571 0 : && reg_equivs
2572 0 : && reg_equiv_invariant (regno))
2573 : {
2574 0 : if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2575 0 : return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2576 0 : mem_mode, insn, true, for_costs);
2577 : /* There exists at least one use of REGNO that cannot be
2578 : eliminated. Prevent the defining insn from being deleted. */
2579 0 : reg_equiv_init (regno) = NULL;
2580 0 : if (!for_costs)
2581 0 : alter_reg (regno, -1, true);
2582 : }
2583 : return x;
2584 :
2585 : /* You might think handling MINUS in a manner similar to PLUS is a
2586 : good idea. It is not. It has been tried multiple times and every
2587 : time the change has had to have been reverted.
2588 :
2589 : Other parts of reload know a PLUS is special (gen_reload for example)
2590 : and require special code to handle code a reloaded PLUS operand.
2591 :
2592 : Also consider backends where the flags register is clobbered by a
2593 : MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2594 : lea instruction comes to mind). If we try to reload a MINUS, we
2595 : may kill the flags register that was holding a useful value.
2596 :
2597 : So, please before trying to handle MINUS, consider reload as a
2598 : whole instead of this little section as well as the backend issues. */
2599 0 : case PLUS:
2600 : /* If this is the sum of an eliminable register and a constant, rework
2601 : the sum. */
2602 0 : if (REG_P (XEXP (x, 0))
2603 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2604 0 : && CONSTANT_P (XEXP (x, 1)))
2605 : {
2606 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2607 : ep++)
2608 0 : if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2609 : {
2610 : /* The only time we want to replace a PLUS with a REG (this
2611 : occurs when the constant operand of the PLUS is the negative
2612 : of the offset) is when we are inside a MEM. We won't want
2613 : to do so at other times because that would change the
2614 : structure of the insn in a way that reload can't handle.
2615 : We special-case the commonest situation in
2616 : eliminate_regs_in_insn, so just replace a PLUS with a
2617 : PLUS here, unless inside a MEM. In DEBUG_INSNs, it is
2618 : always ok to replace a PLUS with just a REG. */
2619 0 : if ((mem_mode != 0 || (insn && DEBUG_INSN_P (insn)))
2620 0 : && CONST_INT_P (XEXP (x, 1))
2621 0 : && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
2622 0 : return ep->to_rtx;
2623 : else
2624 0 : return gen_rtx_PLUS (Pmode, ep->to_rtx,
2625 : plus_constant (Pmode, XEXP (x, 1),
2626 : ep->previous_offset));
2627 : }
2628 :
2629 : /* If the register is not eliminable, we are done since the other
2630 : operand is a constant. */
2631 : return x;
2632 : }
2633 :
2634 : /* If this is part of an address, we want to bring any constant to the
2635 : outermost PLUS. We will do this by doing register replacement in
2636 : our operands and seeing if a constant shows up in one of them.
2637 :
2638 : Note that there is no risk of modifying the structure of the insn,
2639 : since we only get called for its operands, thus we are either
2640 : modifying the address inside a MEM, or something like an address
2641 : operand of a load-address insn. */
2642 :
2643 0 : {
2644 0 : rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2645 : for_costs);
2646 0 : rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2647 : for_costs);
2648 :
2649 0 : if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2650 : {
2651 : /* If one side is a PLUS and the other side is a pseudo that
2652 : didn't get a hard register but has a reg_equiv_constant,
2653 : we must replace the constant here since it may no longer
2654 : be in the position of any operand. */
2655 0 : if (GET_CODE (new0) == PLUS && REG_P (new1)
2656 0 : && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2657 0 : && reg_renumber[REGNO (new1)] < 0
2658 0 : && reg_equivs
2659 0 : && reg_equiv_constant (REGNO (new1)) != 0)
2660 : new1 = reg_equiv_constant (REGNO (new1));
2661 0 : else if (GET_CODE (new1) == PLUS && REG_P (new0)
2662 0 : && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2663 0 : && reg_renumber[REGNO (new0)] < 0
2664 0 : && reg_equiv_constant (REGNO (new0)) != 0)
2665 : new0 = reg_equiv_constant (REGNO (new0));
2666 :
2667 0 : new_rtx = form_sum (GET_MODE (x), new0, new1);
2668 :
2669 : /* As above, if we are not inside a MEM we do not want to
2670 : turn a PLUS into something else. We might try to do so here
2671 : for an addition of 0 if we aren't optimizing. */
2672 0 : if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2673 0 : return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2674 : else
2675 : return new_rtx;
2676 : }
2677 : }
2678 : return x;
2679 :
2680 0 : case MULT:
2681 : /* If this is the product of an eliminable register and a
2682 : constant, apply the distribute law and move the constant out
2683 : so that we have (plus (mult ..) ..). This is needed in order
2684 : to keep load-address insns valid. This case is pathological.
2685 : We ignore the possibility of overflow here. */
2686 0 : if (REG_P (XEXP (x, 0))
2687 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2688 0 : && CONST_INT_P (XEXP (x, 1)))
2689 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2690 : ep++)
2691 0 : if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2692 : {
2693 0 : if (! mem_mode
2694 : /* Refs inside notes or in DEBUG_INSNs don't count for
2695 : this purpose. */
2696 0 : && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2697 0 : || GET_CODE (insn) == INSN_LIST
2698 0 : || DEBUG_INSN_P (insn))))
2699 0 : ep->ref_outside_mem = 1;
2700 :
2701 0 : return
2702 0 : plus_constant (Pmode,
2703 0 : gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2704 0 : ep->previous_offset * INTVAL (XEXP (x, 1)));
2705 : }
2706 :
2707 : /* fall through */
2708 :
2709 0 : case CALL:
2710 0 : case COMPARE:
2711 : /* See comments before PLUS about handling MINUS. */
2712 0 : case MINUS:
2713 0 : case DIV: case UDIV:
2714 0 : case MOD: case UMOD:
2715 0 : case AND: case IOR: case XOR:
2716 0 : case ROTATERT: case ROTATE:
2717 0 : case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2718 0 : case NE: case EQ:
2719 0 : case GE: case GT: case GEU: case GTU:
2720 0 : case LE: case LT: case LEU: case LTU:
2721 0 : {
2722 0 : rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2723 : for_costs);
2724 0 : rtx new1 = XEXP (x, 1)
2725 0 : ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2726 : for_costs) : 0;
2727 :
2728 0 : if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2729 0 : return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2730 : }
2731 : return x;
2732 :
2733 0 : case EXPR_LIST:
2734 : /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2735 0 : if (XEXP (x, 0))
2736 : {
2737 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2738 : for_costs);
2739 0 : if (new_rtx != XEXP (x, 0))
2740 : {
2741 : /* If this is a REG_DEAD note, it is not valid anymore.
2742 : Using the eliminated version could result in creating a
2743 : REG_DEAD note for the stack or frame pointer. */
2744 0 : if (REG_NOTE_KIND (x) == REG_DEAD)
2745 0 : return (XEXP (x, 1)
2746 0 : ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2747 : for_costs)
2748 : : NULL_RTX);
2749 :
2750 0 : x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2751 : }
2752 : }
2753 :
2754 : /* fall through */
2755 :
2756 0 : case INSN_LIST:
2757 0 : case INT_LIST:
2758 : /* Now do eliminations in the rest of the chain. If this was
2759 : an EXPR_LIST, this might result in allocating more memory than is
2760 : strictly needed, but it simplifies the code. */
2761 0 : if (XEXP (x, 1))
2762 : {
2763 0 : new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2764 : for_costs);
2765 0 : if (new_rtx != XEXP (x, 1))
2766 0 : return
2767 0 : gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2768 : }
2769 : return x;
2770 :
2771 : case PRE_INC:
2772 : case POST_INC:
2773 : case PRE_DEC:
2774 : case POST_DEC:
2775 : /* We do not support elimination of a register that is modified.
2776 : elimination_effects has already make sure that this does not
2777 : happen. */
2778 : return x;
2779 :
2780 0 : case PRE_MODIFY:
2781 0 : case POST_MODIFY:
2782 : /* We do not support elimination of a register that is modified.
2783 : elimination_effects has already make sure that this does not
2784 : happen. The only remaining case we need to consider here is
2785 : that the increment value may be an eliminable register. */
2786 0 : if (GET_CODE (XEXP (x, 1)) == PLUS
2787 0 : && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2788 : {
2789 0 : rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2790 : insn, true, for_costs);
2791 :
2792 0 : if (new_rtx != XEXP (XEXP (x, 1), 1))
2793 0 : return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2794 : gen_rtx_PLUS (GET_MODE (x),
2795 : XEXP (x, 0), new_rtx));
2796 : }
2797 : return x;
2798 :
2799 0 : case STRICT_LOW_PART:
2800 0 : case NEG: case NOT:
2801 0 : case SIGN_EXTEND: case ZERO_EXTEND:
2802 0 : case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2803 0 : case FLOAT: case FIX:
2804 0 : case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2805 0 : case ABS:
2806 0 : case SQRT:
2807 0 : case FFS:
2808 0 : case CLZ:
2809 0 : case CTZ:
2810 0 : case POPCOUNT:
2811 0 : case PARITY:
2812 0 : case BSWAP:
2813 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2814 : for_costs);
2815 0 : if (new_rtx != XEXP (x, 0))
2816 0 : return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2817 : return x;
2818 :
2819 0 : case SUBREG:
2820 : /* Similar to above processing, but preserve SUBREG_BYTE.
2821 : Convert (subreg (mem)) to (mem) if not paradoxical.
2822 : Also, if we have a non-paradoxical (subreg (pseudo)) and the
2823 : pseudo didn't get a hard reg, we must replace this with the
2824 : eliminated version of the memory location because push_reload
2825 : may do the replacement in certain circumstances. */
2826 0 : if (REG_P (SUBREG_REG (x))
2827 0 : && !paradoxical_subreg_p (x)
2828 0 : && reg_equivs
2829 0 : && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2830 : {
2831 : new_rtx = SUBREG_REG (x);
2832 : }
2833 : else
2834 0 : new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2835 :
2836 0 : if (new_rtx != SUBREG_REG (x))
2837 : {
2838 0 : poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x));
2839 0 : poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2840 :
2841 0 : if (MEM_P (new_rtx)
2842 0 : && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2843 : /* On RISC machines, combine can create rtl of the form
2844 : (set (subreg:m1 (reg:m2 R) 0) ...)
2845 : where m1 < m2, and expects something interesting to
2846 : happen to the entire word. Moreover, it will use the
2847 : (reg:m2 R) later, expecting all bits to be preserved.
2848 : So if the number of words is the same, preserve the
2849 : subreg so that push_reload can see it. */
2850 : && !(WORD_REGISTER_OPERATIONS
2851 : && known_equal_after_align_down (x_size - 1,
2852 : new_size - 1,
2853 : UNITS_PER_WORD)))
2854 0 : || known_eq (x_size, new_size))
2855 : )
2856 0 : return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2857 0 : else if (insn && GET_CODE (insn) == DEBUG_INSN)
2858 0 : return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2859 : else
2860 0 : return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2861 : }
2862 :
2863 : return x;
2864 :
2865 0 : case MEM:
2866 : /* Our only special processing is to pass the mode of the MEM to our
2867 : recursive call and copy the flags. While we are here, handle this
2868 : case more efficiently. */
2869 :
2870 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2871 : for_costs);
2872 0 : if (for_costs
2873 0 : && memory_address_p (GET_MODE (x), XEXP (x, 0))
2874 0 : && !memory_address_p (GET_MODE (x), new_rtx))
2875 0 : note_reg_elim_costly (XEXP (x, 0), insn);
2876 :
2877 0 : return replace_equiv_address_nv (x, new_rtx);
2878 :
2879 0 : case USE:
2880 : /* Handle insn_list USE that a call to a pure function may generate. */
2881 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2882 : for_costs);
2883 0 : if (new_rtx != XEXP (x, 0))
2884 0 : return gen_rtx_USE (GET_MODE (x), new_rtx);
2885 : return x;
2886 :
2887 0 : case CLOBBER:
2888 0 : case ASM_OPERANDS:
2889 0 : gcc_assert (insn && DEBUG_INSN_P (insn));
2890 : break;
2891 :
2892 0 : case SET:
2893 0 : gcc_unreachable ();
2894 :
2895 : default:
2896 : break;
2897 : }
2898 :
2899 : /* Process each of our operands recursively. If any have changed, make a
2900 : copy of the rtx. */
2901 0 : fmt = GET_RTX_FORMAT (code);
2902 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2903 : {
2904 0 : if (*fmt == 'e')
2905 : {
2906 0 : new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2907 : for_costs);
2908 0 : if (new_rtx != XEXP (x, i) && ! copied)
2909 : {
2910 0 : x = shallow_copy_rtx (x);
2911 0 : copied = 1;
2912 : }
2913 0 : XEXP (x, i) = new_rtx;
2914 : }
2915 0 : else if (*fmt == 'E')
2916 : {
2917 : int copied_vec = 0;
2918 0 : for (j = 0; j < XVECLEN (x, i); j++)
2919 : {
2920 0 : new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2921 : for_costs);
2922 0 : if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2923 : {
2924 0 : rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2925 0 : XVEC (x, i)->elem);
2926 0 : if (! copied)
2927 : {
2928 0 : x = shallow_copy_rtx (x);
2929 0 : copied = 1;
2930 : }
2931 0 : XVEC (x, i) = new_v;
2932 0 : copied_vec = 1;
2933 : }
2934 0 : XVECEXP (x, i, j) = new_rtx;
2935 : }
2936 : }
2937 : }
2938 :
2939 : return x;
2940 : }
2941 :
2942 : rtx
2943 0 : eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2944 : {
2945 0 : if (reg_eliminate == NULL)
2946 : {
2947 0 : gcc_assert (targetm.no_register_allocation);
2948 : return x;
2949 : }
2950 0 : return eliminate_regs_1 (x, mem_mode, insn, false, false);
2951 : }
2952 :
2953 : /* Scan rtx X for modifications of elimination target registers. Update
2954 : the table of eliminables to reflect the changed state. MEM_MODE is
2955 : the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2956 :
2957 : static void
2958 0 : elimination_effects (rtx x, machine_mode mem_mode)
2959 : {
2960 0 : enum rtx_code code = GET_CODE (x);
2961 0 : struct elim_table *ep;
2962 0 : int regno;
2963 0 : int i, j;
2964 0 : const char *fmt;
2965 :
2966 0 : switch (code)
2967 : {
2968 : CASE_CONST_ANY:
2969 : case CONST:
2970 : case SYMBOL_REF:
2971 : case CODE_LABEL:
2972 : case PC:
2973 : case ASM_INPUT:
2974 : case ADDR_VEC:
2975 : case ADDR_DIFF_VEC:
2976 : case RETURN:
2977 : return;
2978 :
2979 0 : case REG:
2980 0 : regno = REGNO (x);
2981 :
2982 : /* First handle the case where we encounter a bare register that
2983 : is eliminable. Replace it with a PLUS. */
2984 0 : if (regno < FIRST_PSEUDO_REGISTER)
2985 : {
2986 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2987 : ep++)
2988 0 : if (ep->from_rtx == x && ep->can_eliminate)
2989 : {
2990 0 : if (! mem_mode)
2991 0 : ep->ref_outside_mem = 1;
2992 0 : return;
2993 : }
2994 :
2995 : }
2996 0 : else if (reg_renumber[regno] < 0
2997 0 : && reg_equivs
2998 0 : && reg_equiv_constant (regno)
2999 0 : && ! function_invariant_p (reg_equiv_constant (regno)))
3000 0 : elimination_effects (reg_equiv_constant (regno), mem_mode);
3001 : return;
3002 :
3003 0 : case PRE_INC:
3004 0 : case POST_INC:
3005 0 : case PRE_DEC:
3006 0 : case POST_DEC:
3007 0 : case POST_MODIFY:
3008 0 : case PRE_MODIFY:
3009 : /* If we modify the source of an elimination rule, disable it. */
3010 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 0 : if (ep->from_rtx == XEXP (x, 0))
3012 0 : ep->can_eliminate = 0;
3013 :
3014 : /* If we modify the target of an elimination rule by adding a constant,
3015 : update its offset. If we modify the target in any other way, we'll
3016 : have to disable the rule as well. */
3017 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3018 0 : if (ep->to_rtx == XEXP (x, 0))
3019 : {
3020 0 : poly_int64 size = GET_MODE_SIZE (mem_mode);
3021 :
3022 : /* If more bytes than MEM_MODE are pushed, account for them. */
3023 : #ifdef PUSH_ROUNDING
3024 0 : if (ep->to_rtx == stack_pointer_rtx)
3025 0 : size = PUSH_ROUNDING (size);
3026 : #endif
3027 0 : if (code == PRE_DEC || code == POST_DEC)
3028 0 : ep->offset += size;
3029 0 : else if (code == PRE_INC || code == POST_INC)
3030 0 : ep->offset -= size;
3031 0 : else if (code == PRE_MODIFY || code == POST_MODIFY)
3032 : {
3033 0 : if (GET_CODE (XEXP (x, 1)) == PLUS
3034 0 : && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3035 0 : && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3036 0 : ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3037 : else
3038 0 : ep->can_eliminate = 0;
3039 : }
3040 : }
3041 :
3042 : /* These two aren't unary operators. */
3043 0 : if (code == POST_MODIFY || code == PRE_MODIFY)
3044 : break;
3045 :
3046 : /* Fall through to generic unary operation case. */
3047 0 : gcc_fallthrough ();
3048 0 : case STRICT_LOW_PART:
3049 0 : case NEG: case NOT:
3050 0 : case SIGN_EXTEND: case ZERO_EXTEND:
3051 0 : case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3052 0 : case FLOAT: case FIX:
3053 0 : case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3054 0 : case ABS:
3055 0 : case SQRT:
3056 0 : case FFS:
3057 0 : case CLZ:
3058 0 : case CTZ:
3059 0 : case POPCOUNT:
3060 0 : case PARITY:
3061 0 : case BSWAP:
3062 0 : elimination_effects (XEXP (x, 0), mem_mode);
3063 0 : return;
3064 :
3065 0 : case SUBREG:
3066 0 : if (REG_P (SUBREG_REG (x))
3067 0 : && !paradoxical_subreg_p (x)
3068 0 : && reg_equivs
3069 0 : && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3070 : return;
3071 :
3072 : elimination_effects (SUBREG_REG (x), mem_mode);
3073 : return;
3074 :
3075 0 : case USE:
3076 : /* If using a register that is the source of an eliminate we still
3077 : think can be performed, note it cannot be performed since we don't
3078 : know how this register is used. */
3079 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3080 0 : if (ep->from_rtx == XEXP (x, 0))
3081 0 : ep->can_eliminate = 0;
3082 :
3083 0 : elimination_effects (XEXP (x, 0), mem_mode);
3084 0 : return;
3085 :
3086 0 : case CLOBBER:
3087 : /* If clobbering a register that is the replacement register for an
3088 : elimination we still think can be performed, note that it cannot
3089 : be performed. Otherwise, we need not be concerned about it. */
3090 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3091 0 : if (ep->to_rtx == XEXP (x, 0))
3092 0 : ep->can_eliminate = 0;
3093 :
3094 0 : elimination_effects (XEXP (x, 0), mem_mode);
3095 0 : return;
3096 :
3097 0 : case SET:
3098 : /* Check for setting a register that we know about. */
3099 0 : if (REG_P (SET_DEST (x)))
3100 : {
3101 : /* See if this is setting the replacement register for an
3102 : elimination.
3103 :
3104 : If DEST is the hard frame pointer, we do nothing because we
3105 : assume that all assignments to the frame pointer are for
3106 : non-local gotos and are being done at a time when they are valid
3107 : and do not disturb anything else. Some machines want to
3108 : eliminate a fake argument pointer (or even a fake frame pointer)
3109 : with either the real frame or the stack pointer. Assignments to
3110 : the hard frame pointer must not prevent this elimination. */
3111 :
3112 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3113 : ep++)
3114 0 : if (ep->to_rtx == SET_DEST (x)
3115 0 : && SET_DEST (x) != hard_frame_pointer_rtx)
3116 : {
3117 : /* If it is being incremented, adjust the offset. Otherwise,
3118 : this elimination can't be done. */
3119 0 : rtx src = SET_SRC (x);
3120 :
3121 0 : if (GET_CODE (src) == PLUS
3122 0 : && XEXP (src, 0) == SET_DEST (x)
3123 0 : && CONST_INT_P (XEXP (src, 1)))
3124 0 : ep->offset -= INTVAL (XEXP (src, 1));
3125 : else
3126 0 : ep->can_eliminate = 0;
3127 : }
3128 : }
3129 :
3130 0 : elimination_effects (SET_DEST (x), VOIDmode);
3131 0 : elimination_effects (SET_SRC (x), VOIDmode);
3132 0 : return;
3133 :
3134 0 : case MEM:
3135 : /* Our only special processing is to pass the mode of the MEM to our
3136 : recursive call. */
3137 0 : elimination_effects (XEXP (x, 0), GET_MODE (x));
3138 0 : return;
3139 :
3140 : default:
3141 : break;
3142 : }
3143 :
3144 0 : fmt = GET_RTX_FORMAT (code);
3145 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3146 : {
3147 0 : if (*fmt == 'e')
3148 0 : elimination_effects (XEXP (x, i), mem_mode);
3149 0 : else if (*fmt == 'E')
3150 0 : for (j = 0; j < XVECLEN (x, i); j++)
3151 0 : elimination_effects (XVECEXP (x, i, j), mem_mode);
3152 : }
3153 : }
3154 :
3155 : /* Descend through rtx X and verify that no references to eliminable registers
3156 : remain. If any do remain, mark the involved register as not
3157 : eliminable. */
3158 :
3159 : static void
3160 0 : check_eliminable_occurrences (rtx x)
3161 : {
3162 0 : const char *fmt;
3163 0 : int i;
3164 0 : enum rtx_code code;
3165 :
3166 0 : if (x == 0)
3167 : return;
3168 :
3169 0 : code = GET_CODE (x);
3170 :
3171 0 : if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3172 : {
3173 0 : struct elim_table *ep;
3174 :
3175 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3176 0 : if (ep->from_rtx == x)
3177 0 : ep->can_eliminate = 0;
3178 : return;
3179 : }
3180 :
3181 0 : fmt = GET_RTX_FORMAT (code);
3182 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3183 : {
3184 0 : if (*fmt == 'e')
3185 0 : check_eliminable_occurrences (XEXP (x, i));
3186 0 : else if (*fmt == 'E')
3187 : {
3188 : int j;
3189 0 : for (j = 0; j < XVECLEN (x, i); j++)
3190 0 : check_eliminable_occurrences (XVECEXP (x, i, j));
3191 : }
3192 : }
3193 : }
3194 :
3195 : /* Scan INSN and eliminate all eliminable registers in it.
3196 :
3197 : If REPLACE is nonzero, do the replacement destructively. Also
3198 : delete the insn as dead it if it is setting an eliminable register.
3199 :
3200 : If REPLACE is zero, do all our allocations in reload_obstack.
3201 :
3202 : If no eliminations were done and this insn doesn't require any elimination
3203 : processing (these are not identical conditions: it might be updating sp,
3204 : but not referencing fp; this needs to be seen during reload_as_needed so
3205 : that the offset between fp and sp can be taken into consideration), zero
3206 : is returned. Otherwise, 1 is returned. */
3207 :
3208 : static int
3209 0 : eliminate_regs_in_insn (rtx_insn *insn, int replace)
3210 : {
3211 0 : int icode = recog_memoized (insn);
3212 0 : rtx old_body = PATTERN (insn);
3213 0 : int insn_is_asm = asm_noperands (old_body) >= 0;
3214 0 : rtx old_set = single_set (insn);
3215 0 : rtx new_body;
3216 0 : int val = 0;
3217 0 : int i;
3218 0 : rtx substed_operand[MAX_RECOG_OPERANDS];
3219 0 : rtx orig_operand[MAX_RECOG_OPERANDS];
3220 0 : struct elim_table *ep;
3221 0 : rtx plus_src, plus_cst_src;
3222 :
3223 0 : if (! insn_is_asm && icode < 0)
3224 : {
3225 0 : gcc_assert (DEBUG_INSN_P (insn)
3226 : || GET_CODE (PATTERN (insn)) == USE
3227 : || GET_CODE (PATTERN (insn)) == CLOBBER
3228 : || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3229 0 : if (DEBUG_BIND_INSN_P (insn))
3230 0 : INSN_VAR_LOCATION_LOC (insn)
3231 0 : = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3232 0 : return 0;
3233 : }
3234 :
3235 : /* We allow one special case which happens to work on all machines we
3236 : currently support: a single set with the source or a REG_EQUAL
3237 : note being a PLUS of an eliminable register and a constant. */
3238 0 : plus_src = plus_cst_src = 0;
3239 0 : if (old_set && REG_P (SET_DEST (old_set)))
3240 : {
3241 0 : if (GET_CODE (SET_SRC (old_set)) == PLUS)
3242 0 : plus_src = SET_SRC (old_set);
3243 : /* First see if the source is of the form (plus (...) CST). */
3244 0 : if (plus_src
3245 0 : && CONST_INT_P (XEXP (plus_src, 1)))
3246 : plus_cst_src = plus_src;
3247 0 : else if (REG_P (SET_SRC (old_set))
3248 0 : || plus_src)
3249 : {
3250 : /* Otherwise, see if we have a REG_EQUAL note of the form
3251 : (plus (...) CST). */
3252 0 : rtx links;
3253 0 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3254 : {
3255 0 : if ((REG_NOTE_KIND (links) == REG_EQUAL
3256 0 : || REG_NOTE_KIND (links) == REG_EQUIV)
3257 0 : && GET_CODE (XEXP (links, 0)) == PLUS
3258 0 : && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3259 : {
3260 : plus_cst_src = XEXP (links, 0);
3261 : break;
3262 : }
3263 : }
3264 : }
3265 :
3266 : /* Check that the first operand of the PLUS is a hard reg or
3267 : the lowpart subreg of one. */
3268 0 : if (plus_cst_src)
3269 : {
3270 0 : rtx reg = XEXP (plus_cst_src, 0);
3271 0 : if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3272 0 : reg = SUBREG_REG (reg);
3273 :
3274 0 : if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3275 : plus_cst_src = 0;
3276 : }
3277 : }
3278 0 : if (plus_cst_src)
3279 : {
3280 0 : rtx reg = XEXP (plus_cst_src, 0);
3281 0 : poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
3282 :
3283 0 : if (GET_CODE (reg) == SUBREG)
3284 0 : reg = SUBREG_REG (reg);
3285 :
3286 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3287 0 : if (ep->from_rtx == reg && ep->can_eliminate)
3288 : {
3289 0 : rtx to_rtx = ep->to_rtx;
3290 0 : offset += ep->offset;
3291 0 : offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3292 :
3293 0 : if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3294 0 : to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3295 : to_rtx);
3296 : /* If we have a nonzero offset, and the source is already
3297 : a simple REG, the following transformation would
3298 : increase the cost of the insn by replacing a simple REG
3299 : with (plus (reg sp) CST). So try only when we already
3300 : had a PLUS before. */
3301 0 : if (known_eq (offset, 0) || plus_src)
3302 : {
3303 0 : rtx new_src = plus_constant (GET_MODE (to_rtx),
3304 : to_rtx, offset);
3305 :
3306 0 : new_body = old_body;
3307 0 : if (! replace)
3308 : {
3309 0 : new_body = copy_insn (old_body);
3310 0 : if (REG_NOTES (insn))
3311 0 : REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3312 : }
3313 0 : PATTERN (insn) = new_body;
3314 0 : old_set = single_set (insn);
3315 :
3316 : /* First see if this insn remains valid when we make the
3317 : change. If not, try to replace the whole pattern with
3318 : a simple set (this may help if the original insn was a
3319 : PARALLEL that was only recognized as single_set due to
3320 : REG_UNUSED notes). If this isn't valid either, keep
3321 : the INSN_CODE the same and let reload fix it up. */
3322 0 : if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3323 : {
3324 0 : rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3325 :
3326 0 : if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3327 0 : SET_SRC (old_set) = new_src;
3328 : }
3329 : }
3330 : else
3331 : break;
3332 :
3333 0 : val = 1;
3334 : /* This can't have an effect on elimination offsets, so skip right
3335 : to the end. */
3336 0 : goto done;
3337 : }
3338 : }
3339 :
3340 : /* Determine the effects of this insn on elimination offsets. */
3341 0 : elimination_effects (old_body, VOIDmode);
3342 :
3343 : /* Eliminate all eliminable registers occurring in operands that
3344 : can be handled by reload. */
3345 0 : extract_insn (insn);
3346 0 : for (i = 0; i < recog_data.n_operands; i++)
3347 : {
3348 0 : orig_operand[i] = recog_data.operand[i];
3349 0 : substed_operand[i] = recog_data.operand[i];
3350 :
3351 : /* For an asm statement, every operand is eliminable. */
3352 0 : if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3353 : {
3354 0 : bool is_set_src, in_plus;
3355 :
3356 : /* Check for setting a register that we know about. */
3357 0 : if (recog_data.operand_type[i] != OP_IN
3358 0 : && REG_P (orig_operand[i]))
3359 : {
3360 : /* If we are assigning to a register that can be eliminated, it
3361 : must be as part of a PARALLEL, since the code above handles
3362 : single SETs. We must indicate that we can no longer
3363 : eliminate this reg. */
3364 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3365 : ep++)
3366 0 : if (ep->from_rtx == orig_operand[i])
3367 0 : ep->can_eliminate = 0;
3368 : }
3369 :
3370 : /* Companion to the above plus substitution, we can allow
3371 : invariants as the source of a plain move. */
3372 0 : is_set_src = false;
3373 0 : if (old_set
3374 0 : && recog_data.operand_loc[i] == &SET_SRC (old_set))
3375 0 : is_set_src = true;
3376 0 : in_plus = false;
3377 0 : if (plus_src
3378 0 : && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3379 0 : || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3380 0 : in_plus = true;
3381 :
3382 0 : substed_operand[i]
3383 0 : = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3384 : replace ? insn : NULL_RTX,
3385 0 : is_set_src || in_plus, false);
3386 0 : if (substed_operand[i] != orig_operand[i])
3387 0 : val = 1;
3388 : /* Terminate the search in check_eliminable_occurrences at
3389 : this point. */
3390 0 : *recog_data.operand_loc[i] = 0;
3391 :
3392 : /* If an output operand changed from a REG to a MEM and INSN is an
3393 : insn, write a CLOBBER insn. */
3394 0 : if (recog_data.operand_type[i] != OP_IN
3395 0 : && REG_P (orig_operand[i])
3396 0 : && MEM_P (substed_operand[i])
3397 0 : && replace)
3398 0 : emit_insn_after (gen_clobber (orig_operand[i]), insn);
3399 : }
3400 : }
3401 :
3402 0 : for (i = 0; i < recog_data.n_dups; i++)
3403 0 : *recog_data.dup_loc[i]
3404 0 : = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3405 :
3406 : /* If any eliminable remain, they aren't eliminable anymore. */
3407 0 : check_eliminable_occurrences (old_body);
3408 :
3409 : /* Substitute the operands; the new values are in the substed_operand
3410 : array. */
3411 0 : for (i = 0; i < recog_data.n_operands; i++)
3412 0 : *recog_data.operand_loc[i] = substed_operand[i];
3413 0 : for (i = 0; i < recog_data.n_dups; i++)
3414 0 : *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3415 :
3416 : /* If we are replacing a body that was a (set X (plus Y Z)), try to
3417 : re-recognize the insn. We do this in case we had a simple addition
3418 : but now can do this as a load-address. This saves an insn in this
3419 : common case.
3420 : If re-recognition fails, the old insn code number will still be used,
3421 : and some register operands may have changed into PLUS expressions.
3422 : These will be handled by find_reloads by loading them into a register
3423 : again. */
3424 :
3425 0 : if (val)
3426 : {
3427 : /* If we aren't replacing things permanently and we changed something,
3428 : make another copy to ensure that all the RTL is new. Otherwise
3429 : things can go wrong if find_reload swaps commutative operands
3430 : and one is inside RTL that has been copied while the other is not. */
3431 0 : new_body = old_body;
3432 0 : if (! replace)
3433 : {
3434 0 : new_body = copy_insn (old_body);
3435 0 : if (REG_NOTES (insn))
3436 0 : REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3437 : }
3438 0 : PATTERN (insn) = new_body;
3439 :
3440 : /* If we had a move insn but now we don't, rerecognize it. This will
3441 : cause spurious re-recognition if the old move had a PARALLEL since
3442 : the new one still will, but we can't call single_set without
3443 : having put NEW_BODY into the insn and the re-recognition won't
3444 : hurt in this rare case. */
3445 : /* ??? Why this huge if statement - why don't we just rerecognize the
3446 : thing always? */
3447 0 : if (! insn_is_asm
3448 0 : && old_set != 0
3449 0 : && ((REG_P (SET_SRC (old_set))
3450 0 : && (GET_CODE (new_body) != SET
3451 0 : || !REG_P (SET_SRC (new_body))))
3452 : /* If this was a load from or store to memory, compare
3453 : the MEM in recog_data.operand to the one in the insn.
3454 : If they are not equal, then rerecognize the insn. */
3455 : || (old_set != 0
3456 0 : && ((MEM_P (SET_SRC (old_set))
3457 0 : && SET_SRC (old_set) != recog_data.operand[1])
3458 0 : || (MEM_P (SET_DEST (old_set))
3459 0 : && SET_DEST (old_set) != recog_data.operand[0])))
3460 : /* If this was an add insn before, rerecognize. */
3461 0 : || GET_CODE (SET_SRC (old_set)) == PLUS))
3462 : {
3463 0 : int new_icode = recog (PATTERN (insn), insn, 0);
3464 0 : if (new_icode >= 0)
3465 0 : INSN_CODE (insn) = new_icode;
3466 : }
3467 : }
3468 :
3469 : /* Restore the old body. If there were any changes to it, we made a copy
3470 : of it while the changes were still in place, so we'll correctly return
3471 : a modified insn below. */
3472 0 : if (! replace)
3473 : {
3474 : /* Restore the old body. */
3475 0 : for (i = 0; i < recog_data.n_operands; i++)
3476 : /* Restoring a top-level match_parallel would clobber the new_body
3477 : we installed in the insn. */
3478 0 : if (recog_data.operand_loc[i] != &PATTERN (insn))
3479 0 : *recog_data.operand_loc[i] = orig_operand[i];
3480 0 : for (i = 0; i < recog_data.n_dups; i++)
3481 0 : *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3482 : }
3483 :
3484 : /* Update all elimination pairs to reflect the status after the current
3485 : insn. The changes we make were determined by the earlier call to
3486 : elimination_effects.
3487 :
3488 : We also detect cases where register elimination cannot be done,
3489 : namely, if a register would be both changed and referenced outside a MEM
3490 : in the resulting insn since such an insn is often undefined and, even if
3491 : not, we cannot know what meaning will be given to it. Note that it is
3492 : valid to have a register used in an address in an insn that changes it
3493 : (presumably with a pre- or post-increment or decrement).
3494 :
3495 : If anything changes, return nonzero. */
3496 :
3497 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3498 : {
3499 0 : if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3500 0 : ep->can_eliminate = 0;
3501 :
3502 0 : ep->ref_outside_mem = 0;
3503 :
3504 0 : if (maybe_ne (ep->previous_offset, ep->offset))
3505 0 : val = 1;
3506 : }
3507 :
3508 0 : done:
3509 : /* If we changed something, perform elimination in REG_NOTES. This is
3510 : needed even when REPLACE is zero because a REG_DEAD note might refer
3511 : to a register that we eliminate and could cause a different number
3512 : of spill registers to be needed in the final reload pass than in
3513 : the pre-passes. */
3514 0 : if (val && REG_NOTES (insn) != 0)
3515 0 : REG_NOTES (insn)
3516 0 : = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3517 : false);
3518 :
3519 : return val;
3520 : }
3521 :
3522 : /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3523 : register allocator. INSN is the instruction we need to examine, we perform
3524 : eliminations in its operands and record cases where eliminating a reg with
3525 : an invariant equivalence would add extra cost. */
3526 :
3527 : #pragma GCC diagnostic push
3528 : #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3529 : static void
3530 0 : elimination_costs_in_insn (rtx_insn *insn)
3531 : {
3532 0 : int icode = recog_memoized (insn);
3533 0 : rtx old_body = PATTERN (insn);
3534 0 : int insn_is_asm = asm_noperands (old_body) >= 0;
3535 0 : rtx old_set = single_set (insn);
3536 0 : int i;
3537 0 : rtx orig_operand[MAX_RECOG_OPERANDS];
3538 0 : rtx orig_dup[MAX_RECOG_OPERANDS];
3539 0 : struct elim_table *ep;
3540 0 : rtx plus_src, plus_cst_src;
3541 0 : bool sets_reg_p;
3542 :
3543 0 : if (! insn_is_asm && icode < 0)
3544 : {
3545 0 : gcc_assert (DEBUG_INSN_P (insn)
3546 : || GET_CODE (PATTERN (insn)) == USE
3547 : || GET_CODE (PATTERN (insn)) == CLOBBER
3548 : || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3549 : return;
3550 : }
3551 :
3552 0 : if (old_set != 0 && REG_P (SET_DEST (old_set))
3553 0 : && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3554 : {
3555 : /* Check for setting an eliminable register. */
3556 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3557 0 : if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3558 : return;
3559 : }
3560 :
3561 : /* We allow one special case which happens to work on all machines we
3562 : currently support: a single set with the source or a REG_EQUAL
3563 : note being a PLUS of an eliminable register and a constant. */
3564 0 : plus_src = plus_cst_src = 0;
3565 0 : sets_reg_p = false;
3566 0 : if (old_set && REG_P (SET_DEST (old_set)))
3567 : {
3568 0 : sets_reg_p = true;
3569 0 : if (GET_CODE (SET_SRC (old_set)) == PLUS)
3570 0 : plus_src = SET_SRC (old_set);
3571 : /* First see if the source is of the form (plus (...) CST). */
3572 0 : if (plus_src
3573 0 : && CONST_INT_P (XEXP (plus_src, 1)))
3574 0 : plus_cst_src = plus_src;
3575 0 : else if (REG_P (SET_SRC (old_set))
3576 : || plus_src)
3577 : {
3578 : /* Otherwise, see if we have a REG_EQUAL note of the form
3579 : (plus (...) CST). */
3580 0 : rtx links;
3581 0 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3582 : {
3583 : if ((REG_NOTE_KIND (links) == REG_EQUAL
3584 : || REG_NOTE_KIND (links) == REG_EQUIV)
3585 : && GET_CODE (XEXP (links, 0)) == PLUS
3586 : && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3587 : {
3588 : plus_cst_src = XEXP (links, 0);
3589 : break;
3590 : }
3591 : }
3592 : }
3593 : }
3594 :
3595 : /* Determine the effects of this insn on elimination offsets. */
3596 0 : elimination_effects (old_body, VOIDmode);
3597 :
3598 : /* Eliminate all eliminable registers occurring in operands that
3599 : can be handled by reload. */
3600 0 : extract_insn (insn);
3601 0 : int n_dups = recog_data.n_dups;
3602 0 : for (i = 0; i < n_dups; i++)
3603 0 : orig_dup[i] = *recog_data.dup_loc[i];
3604 :
3605 0 : int n_operands = recog_data.n_operands;
3606 0 : for (i = 0; i < n_operands; i++)
3607 : {
3608 0 : orig_operand[i] = recog_data.operand[i];
3609 :
3610 : /* For an asm statement, every operand is eliminable. */
3611 0 : if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3612 : {
3613 0 : bool is_set_src, in_plus;
3614 :
3615 : /* Check for setting a register that we know about. */
3616 0 : if (recog_data.operand_type[i] != OP_IN
3617 0 : && REG_P (orig_operand[i]))
3618 : {
3619 : /* If we are assigning to a register that can be eliminated, it
3620 : must be as part of a PARALLEL, since the code above handles
3621 : single SETs. We must indicate that we can no longer
3622 : eliminate this reg. */
3623 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3624 : ep++)
3625 0 : if (ep->from_rtx == orig_operand[i])
3626 0 : ep->can_eliminate = 0;
3627 : }
3628 :
3629 : /* Companion to the above plus substitution, we can allow
3630 : invariants as the source of a plain move. */
3631 0 : is_set_src = false;
3632 0 : if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3633 0 : is_set_src = true;
3634 0 : if (is_set_src && !sets_reg_p)
3635 0 : note_reg_elim_costly (SET_SRC (old_set), insn);
3636 0 : in_plus = false;
3637 0 : if (plus_src && sets_reg_p
3638 0 : && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3639 0 : || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3640 0 : in_plus = true;
3641 :
3642 0 : eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3643 : NULL_RTX,
3644 0 : is_set_src || in_plus, true);
3645 : /* Terminate the search in check_eliminable_occurrences at
3646 : this point. */
3647 0 : *recog_data.operand_loc[i] = 0;
3648 : }
3649 : }
3650 :
3651 0 : for (i = 0; i < n_dups; i++)
3652 0 : *recog_data.dup_loc[i]
3653 0 : = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3654 :
3655 : /* If any eliminable remain, they aren't eliminable anymore. */
3656 0 : check_eliminable_occurrences (old_body);
3657 :
3658 : /* Restore the old body. */
3659 0 : for (i = 0; i < n_operands; i++)
3660 0 : *recog_data.operand_loc[i] = orig_operand[i];
3661 0 : for (i = 0; i < n_dups; i++)
3662 0 : *recog_data.dup_loc[i] = orig_dup[i];
3663 :
3664 : /* Update all elimination pairs to reflect the status after the current
3665 : insn. The changes we make were determined by the earlier call to
3666 : elimination_effects. */
3667 :
3668 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3669 : {
3670 0 : if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3671 0 : ep->can_eliminate = 0;
3672 :
3673 0 : ep->ref_outside_mem = 0;
3674 : }
3675 :
3676 : return;
3677 : }
3678 : #pragma GCC diagnostic pop
3679 :
3680 : /* Loop through all elimination pairs.
3681 : Recalculate the number not at initial offset.
3682 :
3683 : Compute the maximum offset (minimum offset if the stack does not
3684 : grow downward) for each elimination pair. */
3685 :
3686 : static void
3687 0 : update_eliminable_offsets (void)
3688 : {
3689 0 : struct elim_table *ep;
3690 :
3691 0 : num_not_at_initial_offset = 0;
3692 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3693 : {
3694 0 : ep->previous_offset = ep->offset;
3695 0 : if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3696 0 : num_not_at_initial_offset++;
3697 : }
3698 0 : }
3699 :
3700 : /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3701 : replacement we currently believe is valid, mark it as not eliminable if X
3702 : modifies DEST in any way other than by adding a constant integer to it.
3703 :
3704 : If DEST is the frame pointer, we do nothing because we assume that
3705 : all assignments to the hard frame pointer are nonlocal gotos and are being
3706 : done at a time when they are valid and do not disturb anything else.
3707 : Some machines want to eliminate a fake argument pointer with either the
3708 : frame or stack pointer. Assignments to the hard frame pointer must not
3709 : prevent this elimination.
3710 :
3711 : Called via note_stores from reload before starting its passes to scan
3712 : the insns of the function. */
3713 :
3714 : static void
3715 0 : mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3716 : {
3717 0 : unsigned int i;
3718 :
3719 : /* A SUBREG of a hard register here is just changing its mode. We should
3720 : not see a SUBREG of an eliminable hard register, but check just in
3721 : case. */
3722 0 : if (GET_CODE (dest) == SUBREG)
3723 0 : dest = SUBREG_REG (dest);
3724 :
3725 0 : if (dest == hard_frame_pointer_rtx)
3726 : return;
3727 :
3728 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3729 0 : if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3730 0 : && (GET_CODE (x) != SET
3731 0 : || GET_CODE (SET_SRC (x)) != PLUS
3732 0 : || XEXP (SET_SRC (x), 0) != dest
3733 0 : || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3734 : {
3735 0 : reg_eliminate[i].can_eliminate_previous
3736 0 : = reg_eliminate[i].can_eliminate = 0;
3737 0 : num_eliminable--;
3738 : }
3739 : }
3740 :
3741 : /* Verify that the initial elimination offsets did not change since the
3742 : last call to set_initial_elim_offsets. This is used to catch cases
3743 : where something illegal happened during reload_as_needed that could
3744 : cause incorrect code to be generated if we did not check for it. */
3745 :
3746 : static bool
3747 0 : verify_initial_elim_offsets (void)
3748 : {
3749 0 : poly_int64 t;
3750 0 : struct elim_table *ep;
3751 :
3752 0 : if (!num_eliminable)
3753 : return true;
3754 :
3755 0 : targetm.compute_frame_layout ();
3756 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3757 : {
3758 0 : INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3759 0 : if (maybe_ne (t, ep->initial_offset))
3760 : return false;
3761 : }
3762 :
3763 : return true;
3764 : }
3765 :
3766 : /* Reset all offsets on eliminable registers to their initial values. */
3767 :
3768 : static void
3769 0 : set_initial_elim_offsets (void)
3770 : {
3771 0 : struct elim_table *ep = reg_eliminate;
3772 :
3773 0 : targetm.compute_frame_layout ();
3774 0 : for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3775 : {
3776 0 : INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3777 0 : ep->previous_offset = ep->offset = ep->initial_offset;
3778 : }
3779 :
3780 0 : num_not_at_initial_offset = 0;
3781 0 : }
3782 :
3783 : /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3784 :
3785 : static void
3786 0 : set_initial_eh_label_offset (rtx label)
3787 : {
3788 0 : set_label_offsets (label, NULL, 1);
3789 0 : }
3790 :
3791 : /* Initialize the known label offsets.
3792 : Set a known offset for each forced label to be at the initial offset
3793 : of each elimination. We do this because we assume that all
3794 : computed jumps occur from a location where each elimination is
3795 : at its initial offset.
3796 : For all other labels, show that we don't know the offsets. */
3797 :
3798 : static void
3799 0 : set_initial_label_offsets (void)
3800 : {
3801 0 : memset (offsets_known_at, 0, num_labels);
3802 :
3803 0 : unsigned int i;
3804 0 : rtx_insn *insn;
3805 0 : FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3806 0 : set_label_offsets (insn, NULL, 1);
3807 :
3808 0 : for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3809 0 : if (x->insn ())
3810 0 : set_label_offsets (x->insn (), NULL, 1);
3811 :
3812 0 : for_each_eh_label (set_initial_eh_label_offset);
3813 0 : }
3814 :
3815 : /* Set all elimination offsets to the known values for the code label given
3816 : by INSN. */
3817 :
3818 : static void
3819 0 : set_offsets_for_label (rtx_insn *insn)
3820 : {
3821 0 : unsigned int i;
3822 0 : int label_nr = CODE_LABEL_NUMBER (insn);
3823 0 : struct elim_table *ep;
3824 :
3825 0 : num_not_at_initial_offset = 0;
3826 0 : for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3827 : {
3828 0 : ep->offset = ep->previous_offset
3829 0 : = offsets_at[label_nr - first_label_num][i];
3830 0 : if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3831 0 : num_not_at_initial_offset++;
3832 : }
3833 0 : }
3834 :
3835 : /* See if anything that happened changes which eliminations are valid.
3836 : For example, on the SPARC, whether or not the frame pointer can
3837 : be eliminated can depend on what registers have been used. We need
3838 : not check some conditions again (such as flag_omit_frame_pointer)
3839 : since they can't have changed. */
3840 :
3841 : static void
3842 0 : update_eliminables (HARD_REG_SET *pset)
3843 : {
3844 0 : int previous_frame_pointer_needed = frame_pointer_needed;
3845 0 : struct elim_table *ep;
3846 :
3847 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3848 0 : if ((ep->from == HARD_FRAME_POINTER_REGNUM
3849 0 : && targetm.frame_pointer_required ())
3850 0 : || ! targetm.can_eliminate (ep->from, ep->to)
3851 : )
3852 0 : ep->can_eliminate = 0;
3853 :
3854 : /* Look for the case where we have discovered that we can't replace
3855 : register A with register B and that means that we will now be
3856 : trying to replace register A with register C. This means we can
3857 : no longer replace register C with register B and we need to disable
3858 : such an elimination, if it exists. This occurs often with A == ap,
3859 : B == sp, and C == fp. */
3860 :
3861 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3862 : {
3863 0 : struct elim_table *op;
3864 0 : int new_to = -1;
3865 :
3866 0 : if (! ep->can_eliminate && ep->can_eliminate_previous)
3867 : {
3868 : /* Find the current elimination for ep->from, if there is a
3869 : new one. */
3870 0 : for (op = reg_eliminate;
3871 0 : op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3872 0 : if (op->from == ep->from && op->can_eliminate)
3873 : {
3874 0 : new_to = op->to;
3875 0 : break;
3876 : }
3877 :
3878 : /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3879 : disable it. */
3880 0 : for (op = reg_eliminate;
3881 0 : op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3882 0 : if (op->from == new_to && op->to == ep->to)
3883 0 : op->can_eliminate = 0;
3884 : }
3885 : }
3886 :
3887 : /* See if any registers that we thought we could eliminate the previous
3888 : time are no longer eliminable. If so, something has changed and we
3889 : must spill the register. Also, recompute the number of eliminable
3890 : registers and see if the frame pointer is needed; it is if there is
3891 : no elimination of the frame pointer that we can perform. */
3892 :
3893 0 : frame_pointer_needed = 1;
3894 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3895 : {
3896 0 : if (ep->can_eliminate
3897 0 : && ep->from == FRAME_POINTER_REGNUM
3898 0 : && ep->to != HARD_FRAME_POINTER_REGNUM
3899 0 : && (! SUPPORTS_STACK_ALIGNMENT
3900 0 : || ! crtl->stack_realign_needed))
3901 0 : frame_pointer_needed = 0;
3902 :
3903 0 : if (! ep->can_eliminate && ep->can_eliminate_previous)
3904 : {
3905 0 : ep->can_eliminate_previous = 0;
3906 0 : SET_HARD_REG_BIT (*pset, ep->from);
3907 0 : num_eliminable--;
3908 : }
3909 : }
3910 :
3911 : /* If we didn't need a frame pointer last time, but we do now, spill
3912 : the hard frame pointer. */
3913 0 : if (frame_pointer_needed && ! previous_frame_pointer_needed)
3914 0 : SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3915 0 : }
3916 :
3917 : /* Call update_eliminables an spill any registers we can't eliminate anymore.
3918 : Return true iff a register was spilled. */
3919 :
3920 : static bool
3921 0 : update_eliminables_and_spill (void)
3922 : {
3923 0 : unsigned int i;
3924 0 : bool did_spill = false;
3925 0 : HARD_REG_SET to_spill;
3926 0 : CLEAR_HARD_REG_SET (to_spill);
3927 0 : update_eliminables (&to_spill);
3928 0 : used_spill_regs &= ~to_spill;
3929 :
3930 0 : hard_reg_set_iterator hrsi;
3931 0 : EXECUTE_IF_SET_IN_HARD_REG_SET (to_spill, 0, i, hrsi)
3932 : {
3933 0 : spill_hard_reg (i, 1);
3934 0 : did_spill = true;
3935 :
3936 : /* Regardless of the state of spills, if we previously had
3937 : a register that we thought we could eliminate, but now
3938 : cannot eliminate, we must run another pass.
3939 :
3940 : Consider pseudos which have an entry in reg_equiv_* which
3941 : reference an eliminable register. We must make another pass
3942 : to update reg_equiv_* so that we do not substitute in the
3943 : old value from when we thought the elimination could be
3944 : performed. */
3945 : }
3946 0 : return did_spill;
3947 : }
3948 :
3949 : /* Return true if X is used as the target register of an elimination. */
3950 :
3951 : bool
3952 0 : elimination_target_reg_p (rtx x)
3953 : {
3954 0 : struct elim_table *ep;
3955 :
3956 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3957 0 : if (ep->to_rtx == x && ep->can_eliminate)
3958 : return true;
3959 :
3960 : return false;
3961 : }
3962 :
3963 : /* Initialize the table of registers to eliminate.
3964 : Pre-condition: global flag frame_pointer_needed has been set before
3965 : calling this function. */
3966 :
3967 : static void
3968 0 : init_elim_table (void)
3969 : {
3970 0 : struct elim_table *ep;
3971 0 : const struct elim_table_1 *ep1;
3972 :
3973 0 : if (!reg_eliminate)
3974 0 : reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3975 :
3976 0 : num_eliminable = 0;
3977 :
3978 0 : for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3979 0 : ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3980 : {
3981 0 : ep->from = ep1->from;
3982 0 : ep->to = ep1->to;
3983 0 : ep->can_eliminate = ep->can_eliminate_previous
3984 0 : = (targetm.can_eliminate (ep->from, ep->to)
3985 0 : && ! (ep->to == STACK_POINTER_REGNUM
3986 0 : && frame_pointer_needed
3987 0 : && (! SUPPORTS_STACK_ALIGNMENT
3988 0 : || ! stack_realign_fp)));
3989 : }
3990 :
3991 : /* Count the number of eliminable registers and build the FROM and TO
3992 : REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3993 : gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3994 : We depend on this. */
3995 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3996 : {
3997 0 : num_eliminable += ep->can_eliminate;
3998 0 : ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3999 0 : ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4000 : }
4001 0 : }
4002 :
4003 : /* Find all the pseudo registers that didn't get hard regs
4004 : but do have known equivalent constants or memory slots.
4005 : These include parameters (known equivalent to parameter slots)
4006 : and cse'd or loop-moved constant memory addresses.
4007 :
4008 : Record constant equivalents in reg_equiv_constant
4009 : so they will be substituted by find_reloads.
4010 : Record memory equivalents in reg_mem_equiv so they can
4011 : be substituted eventually by altering the REG-rtx's. */
4012 :
4013 : static void
4014 0 : init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4015 : {
4016 0 : int i;
4017 0 : rtx_insn *insn;
4018 :
4019 0 : grow_reg_equivs ();
4020 0 : if (do_subregs)
4021 0 : reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4022 : else
4023 0 : reg_max_ref_mode = NULL;
4024 :
4025 0 : num_eliminable_invariants = 0;
4026 :
4027 0 : first_label_num = get_first_label_num ();
4028 0 : num_labels = max_label_num () - first_label_num;
4029 :
4030 : /* Allocate the tables used to store offset information at labels. */
4031 0 : offsets_known_at = XNEWVEC (char, num_labels);
4032 0 : offsets_at = (poly_int64 (*)[NUM_ELIMINABLE_REGS])
4033 0 : xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
4034 :
4035 : /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4036 : to. If DO_SUBREGS is true, also find all paradoxical subregs and
4037 : find largest such for each pseudo. FIRST is the head of the insn
4038 : list. */
4039 :
4040 0 : for (insn = first; insn; insn = NEXT_INSN (insn))
4041 : {
4042 0 : rtx set = single_set (insn);
4043 :
4044 : /* We may introduce USEs that we want to remove at the end, so
4045 : we'll mark them with QImode. Make sure there are no
4046 : previously-marked insns left by say regmove. */
4047 0 : if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4048 0 : && GET_MODE (insn) != VOIDmode)
4049 0 : PUT_MODE (insn, VOIDmode);
4050 :
4051 0 : if (do_subregs && NONDEBUG_INSN_P (insn))
4052 0 : scan_paradoxical_subregs (PATTERN (insn));
4053 :
4054 0 : if (set != 0 && REG_P (SET_DEST (set)))
4055 : {
4056 0 : rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4057 0 : rtx x;
4058 :
4059 0 : if (! note)
4060 0 : continue;
4061 :
4062 0 : i = REGNO (SET_DEST (set));
4063 0 : x = XEXP (note, 0);
4064 :
4065 0 : if (i <= LAST_VIRTUAL_REGISTER)
4066 0 : continue;
4067 :
4068 : /* If flag_pic and we have constant, verify it's legitimate. */
4069 0 : if (!CONSTANT_P (x)
4070 0 : || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4071 : {
4072 : /* It can happen that a REG_EQUIV note contains a MEM
4073 : that is not a legitimate memory operand. As later
4074 : stages of reload assume that all addresses found
4075 : in the reg_equiv_* arrays were originally legitimate,
4076 : we ignore such REG_EQUIV notes. */
4077 0 : if (memory_operand (x, VOIDmode))
4078 : {
4079 : /* Always unshare the equivalence, so we can
4080 : substitute into this insn without touching the
4081 : equivalence. */
4082 0 : reg_equiv_memory_loc (i) = copy_rtx (x);
4083 : }
4084 0 : else if (function_invariant_p (x))
4085 : {
4086 0 : machine_mode mode;
4087 :
4088 0 : mode = GET_MODE (SET_DEST (set));
4089 0 : if (GET_CODE (x) == PLUS)
4090 : {
4091 : /* This is PLUS of frame pointer and a constant,
4092 : and might be shared. Unshare it. */
4093 0 : reg_equiv_invariant (i) = copy_rtx (x);
4094 0 : num_eliminable_invariants++;
4095 : }
4096 0 : else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4097 : {
4098 0 : reg_equiv_invariant (i) = x;
4099 0 : num_eliminable_invariants++;
4100 : }
4101 0 : else if (targetm.legitimate_constant_p (mode, x))
4102 0 : reg_equiv_constant (i) = x;
4103 : else
4104 : {
4105 0 : reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4106 0 : if (! reg_equiv_memory_loc (i))
4107 0 : reg_equiv_init (i) = NULL;
4108 : }
4109 : }
4110 : else
4111 : {
4112 0 : reg_equiv_init (i) = NULL;
4113 0 : continue;
4114 : }
4115 : }
4116 : else
4117 0 : reg_equiv_init (i) = NULL;
4118 : }
4119 : }
4120 :
4121 0 : if (dump_file)
4122 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4123 0 : if (reg_equiv_init (i))
4124 : {
4125 0 : fprintf (dump_file, "init_insns for %u: ", i);
4126 0 : print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4127 0 : fprintf (dump_file, "\n");
4128 : }
4129 0 : }
4130 :
4131 : /* Indicate that we no longer have known memory locations or constants.
4132 : Free all data involved in tracking these. */
4133 :
4134 : static void
4135 0 : free_reg_equiv (void)
4136 : {
4137 0 : int i;
4138 :
4139 0 : free (offsets_known_at);
4140 0 : free (offsets_at);
4141 0 : offsets_at = 0;
4142 0 : offsets_known_at = 0;
4143 :
4144 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4145 0 : if (reg_equiv_alt_mem_list (i))
4146 0 : free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4147 0 : vec_free (reg_equivs);
4148 0 : }
4149 :
4150 : /* Kick all pseudos out of hard register REGNO.
4151 :
4152 : If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4153 : because we found we can't eliminate some register. In the case, no pseudos
4154 : are allowed to be in the register, even if they are only in a block that
4155 : doesn't require spill registers, unlike the case when we are spilling this
4156 : hard reg to produce another spill register.
4157 :
4158 : Return nonzero if any pseudos needed to be kicked out. */
4159 :
4160 : static void
4161 0 : spill_hard_reg (unsigned int regno, int cant_eliminate)
4162 : {
4163 0 : int i;
4164 :
4165 0 : if (cant_eliminate)
4166 : {
4167 0 : SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4168 0 : df_set_regs_ever_live (regno, true);
4169 : }
4170 :
4171 : /* Spill every pseudo reg that was allocated to this reg
4172 : or to something that overlaps this reg. */
4173 :
4174 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4175 0 : if (reg_renumber[i] >= 0
4176 0 : && (unsigned int) reg_renumber[i] <= regno
4177 0 : && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4178 0 : SET_REGNO_REG_SET (&spilled_pseudos, i);
4179 0 : }
4180 :
4181 : /* After spill_hard_reg was called and/or find_reload_regs was run for all
4182 : insns that need reloads, this function is used to actually spill pseudo
4183 : registers and try to reallocate them. It also sets up the spill_regs
4184 : array for use by choose_reload_regs.
4185 :
4186 : GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4187 : that we displace from hard registers. */
4188 :
4189 : static int
4190 0 : finish_spills (int global)
4191 : {
4192 0 : class insn_chain *chain;
4193 0 : int something_changed = 0;
4194 0 : unsigned i;
4195 0 : reg_set_iterator rsi;
4196 :
4197 : /* Build the spill_regs array for the function. */
4198 : /* If there are some registers still to eliminate and one of the spill regs
4199 : wasn't ever used before, additional stack space may have to be
4200 : allocated to store this register. Thus, we may have changed the offset
4201 : between the stack and frame pointers, so mark that something has changed.
4202 :
4203 : One might think that we need only set VAL to 1 if this is a call-used
4204 : register. However, the set of registers that must be saved by the
4205 : prologue is not identical to the call-used set. For example, the
4206 : register used by the call insn for the return PC is a call-used register,
4207 : but must be saved by the prologue. */
4208 :
4209 0 : n_spills = 0;
4210 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4211 0 : if (TEST_HARD_REG_BIT (used_spill_regs, i))
4212 : {
4213 0 : spill_reg_order[i] = n_spills;
4214 0 : spill_regs[n_spills++] = i;
4215 0 : if (num_eliminable && ! df_regs_ever_live_p (i))
4216 : something_changed = 1;
4217 0 : df_set_regs_ever_live (i, true);
4218 : }
4219 : else
4220 0 : spill_reg_order[i] = -1;
4221 :
4222 0 : EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4223 0 : if (reg_renumber[i] >= 0)
4224 : {
4225 0 : SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4226 : /* Mark it as no longer having a hard register home. */
4227 0 : reg_renumber[i] = -1;
4228 0 : if (ira_conflicts_p)
4229 : /* Inform IRA about the change. */
4230 0 : ira_mark_allocation_change (i);
4231 : /* We will need to scan everything again. */
4232 : something_changed = 1;
4233 : }
4234 :
4235 : /* Retry global register allocation if possible. */
4236 0 : if (global && ira_conflicts_p)
4237 : {
4238 0 : unsigned int n;
4239 :
4240 0 : memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4241 : /* For every insn that needs reloads, set the registers used as spill
4242 : regs in pseudo_forbidden_regs for every pseudo live across the
4243 : insn. */
4244 0 : for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4245 : {
4246 0 : EXECUTE_IF_SET_IN_REG_SET
4247 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4248 : {
4249 0 : pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4250 : }
4251 0 : EXECUTE_IF_SET_IN_REG_SET
4252 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4253 : {
4254 0 : pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4255 : }
4256 : }
4257 :
4258 : /* Retry allocating the pseudos spilled in IRA and the
4259 : reload. For each reg, merge the various reg sets that
4260 : indicate which hard regs can't be used, and call
4261 : ira_reassign_pseudos. */
4262 0 : for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4263 0 : if (reg_old_renumber[i] != reg_renumber[i])
4264 : {
4265 0 : if (reg_renumber[i] < 0)
4266 0 : temp_pseudo_reg_arr[n++] = i;
4267 : else
4268 0 : CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4269 : }
4270 0 : if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4271 : bad_spill_regs_global,
4272 : pseudo_forbidden_regs, pseudo_previous_regs,
4273 : &spilled_pseudos))
4274 0 : something_changed = 1;
4275 : }
4276 : /* Fix up the register information in the insn chain.
4277 : This involves deleting those of the spilled pseudos which did not get
4278 : a new hard register home from the live_{before,after} sets. */
4279 0 : for (chain = reload_insn_chain; chain; chain = chain->next)
4280 : {
4281 0 : HARD_REG_SET used_by_pseudos;
4282 0 : HARD_REG_SET used_by_pseudos2;
4283 :
4284 0 : if (! ira_conflicts_p)
4285 : {
4286 : /* Don't do it for IRA because IRA and the reload still can
4287 : assign hard registers to the spilled pseudos on next
4288 : reload iterations. */
4289 0 : AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4290 0 : AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4291 : }
4292 : /* Mark any unallocated hard regs as available for spills. That
4293 : makes inheritance work somewhat better. */
4294 0 : if (chain->need_reload)
4295 : {
4296 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4297 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4298 0 : used_by_pseudos |= used_by_pseudos2;
4299 :
4300 0 : compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4301 0 : compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4302 : /* Value of chain->used_spill_regs from previous iteration
4303 : may be not included in the value calculated here because
4304 : of possible removing caller-saves insns (see function
4305 : delete_caller_save_insns. */
4306 0 : chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
4307 : }
4308 : }
4309 :
4310 0 : CLEAR_REG_SET (&changed_allocation_pseudos);
4311 : /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4312 0 : for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4313 : {
4314 0 : int regno = reg_renumber[i];
4315 0 : if (reg_old_renumber[i] == regno)
4316 0 : continue;
4317 :
4318 0 : SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4319 :
4320 0 : alter_reg (i, reg_old_renumber[i], false);
4321 0 : reg_old_renumber[i] = regno;
4322 0 : if (dump_file)
4323 : {
4324 0 : if (regno == -1)
4325 0 : fprintf (dump_file, " Register %d now on stack.\n\n", i);
4326 : else
4327 0 : fprintf (dump_file, " Register %d now in %d.\n\n",
4328 0 : i, reg_renumber[i]);
4329 : }
4330 : }
4331 :
4332 0 : return something_changed;
4333 : }
4334 :
4335 : /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4336 :
4337 : static void
4338 0 : scan_paradoxical_subregs (rtx x)
4339 : {
4340 0 : int i;
4341 0 : const char *fmt;
4342 0 : enum rtx_code code = GET_CODE (x);
4343 :
4344 0 : switch (code)
4345 : {
4346 : case REG:
4347 : case CONST:
4348 : case SYMBOL_REF:
4349 : case LABEL_REF:
4350 : CASE_CONST_ANY:
4351 : case PC:
4352 : case USE:
4353 : case CLOBBER:
4354 : return;
4355 :
4356 0 : case SUBREG:
4357 0 : if (REG_P (SUBREG_REG (x)))
4358 : {
4359 0 : unsigned int regno = REGNO (SUBREG_REG (x));
4360 0 : if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4361 : {
4362 0 : reg_max_ref_mode[regno] = GET_MODE (x);
4363 0 : mark_home_live_1 (regno, GET_MODE (x));
4364 : }
4365 : }
4366 : return;
4367 :
4368 0 : default:
4369 0 : break;
4370 : }
4371 :
4372 0 : fmt = GET_RTX_FORMAT (code);
4373 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4374 : {
4375 0 : if (fmt[i] == 'e')
4376 0 : scan_paradoxical_subregs (XEXP (x, i));
4377 0 : else if (fmt[i] == 'E')
4378 : {
4379 0 : int j;
4380 0 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4381 0 : scan_paradoxical_subregs (XVECEXP (x, i, j));
4382 : }
4383 : }
4384 : }
4385 :
4386 : /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4387 : If *OP_PTR is a paradoxical subreg, try to remove that subreg
4388 : and apply the corresponding narrowing subreg to *OTHER_PTR.
4389 : Return true if the operands were changed, false otherwise. */
4390 :
4391 : static bool
4392 0 : strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4393 : {
4394 0 : rtx op, inner, other, tem;
4395 :
4396 0 : op = *op_ptr;
4397 0 : if (!paradoxical_subreg_p (op))
4398 : return false;
4399 0 : inner = SUBREG_REG (op);
4400 :
4401 0 : other = *other_ptr;
4402 0 : tem = gen_lowpart_common (GET_MODE (inner), other);
4403 0 : if (!tem)
4404 : return false;
4405 :
4406 : /* If the lowpart operation turned a hard register into a subreg,
4407 : rather than simplifying it to another hard register, then the
4408 : mode change cannot be properly represented. For example, OTHER
4409 : might be valid in its current mode, but not in the new one. */
4410 0 : if (GET_CODE (tem) == SUBREG
4411 0 : && REG_P (other)
4412 0 : && HARD_REGISTER_P (other))
4413 : return false;
4414 :
4415 0 : *op_ptr = inner;
4416 0 : *other_ptr = tem;
4417 0 : return true;
4418 : }
4419 :
4420 : /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4421 : examine all of the reload insns between PREV and NEXT exclusive, and
4422 : annotate all that may trap. */
4423 :
4424 : static void
4425 0 : fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4426 : {
4427 0 : rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4428 0 : if (note == NULL)
4429 : return;
4430 0 : if (!insn_could_throw_p (insn))
4431 0 : remove_note (insn, note);
4432 0 : copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4433 : }
4434 :
4435 : /* Reload pseudo-registers into hard regs around each insn as needed.
4436 : Additional register load insns are output before the insn that needs it
4437 : and perhaps store insns after insns that modify the reloaded pseudo reg.
4438 :
4439 : reg_last_reload_reg and reg_reloaded_contents keep track of
4440 : which registers are already available in reload registers.
4441 : We update these for the reloads that we perform,
4442 : as the insns are scanned. */
4443 :
4444 : static void
4445 0 : reload_as_needed (int live_known)
4446 : {
4447 0 : class insn_chain *chain;
4448 : #if AUTO_INC_DEC
4449 : int i;
4450 : #endif
4451 0 : rtx_note *marker;
4452 :
4453 0 : memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4454 0 : memset (spill_reg_store, 0, sizeof spill_reg_store);
4455 0 : reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4456 0 : INIT_REG_SET (®_has_output_reload);
4457 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4458 :
4459 0 : set_initial_elim_offsets ();
4460 :
4461 : /* Generate a marker insn that we will move around. */
4462 0 : marker = emit_note (NOTE_INSN_DELETED);
4463 0 : unlink_insn_chain (marker, marker);
4464 :
4465 0 : for (chain = reload_insn_chain; chain; chain = chain->next)
4466 : {
4467 0 : rtx_insn *prev = 0;
4468 0 : rtx_insn *insn = chain->insn;
4469 0 : rtx_insn *old_next = NEXT_INSN (insn);
4470 : #if AUTO_INC_DEC
4471 : rtx_insn *old_prev = PREV_INSN (insn);
4472 : #endif
4473 :
4474 0 : if (will_delete_init_insn_p (insn))
4475 0 : continue;
4476 :
4477 : /* If we pass a label, copy the offsets from the label information
4478 : into the current offsets of each elimination. */
4479 0 : if (LABEL_P (insn))
4480 0 : set_offsets_for_label (insn);
4481 :
4482 0 : else if (INSN_P (insn))
4483 : {
4484 0 : regset_head regs_to_forget;
4485 0 : INIT_REG_SET (®s_to_forget);
4486 0 : note_stores (insn, forget_old_reloads_1, ®s_to_forget);
4487 :
4488 : /* If this is a USE and CLOBBER of a MEM, ensure that any
4489 : references to eliminable registers have been removed. */
4490 :
4491 0 : if ((GET_CODE (PATTERN (insn)) == USE
4492 0 : || GET_CODE (PATTERN (insn)) == CLOBBER)
4493 0 : && MEM_P (XEXP (PATTERN (insn), 0)))
4494 0 : XEXP (XEXP (PATTERN (insn), 0), 0)
4495 0 : = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4496 0 : GET_MODE (XEXP (PATTERN (insn), 0)),
4497 : NULL_RTX);
4498 :
4499 : /* If we need to do register elimination processing, do so.
4500 : This might delete the insn, in which case we are done. */
4501 0 : if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4502 : {
4503 0 : eliminate_regs_in_insn (insn, 1);
4504 0 : if (NOTE_P (insn))
4505 : {
4506 0 : update_eliminable_offsets ();
4507 0 : CLEAR_REG_SET (®s_to_forget);
4508 0 : continue;
4509 : }
4510 : }
4511 :
4512 : /* If need_elim is nonzero but need_reload is zero, one might think
4513 : that we could simply set n_reloads to 0. However, find_reloads
4514 : could have done some manipulation of the insn (such as swapping
4515 : commutative operands), and these manipulations are lost during
4516 : the first pass for every insn that needs register elimination.
4517 : So the actions of find_reloads must be redone here. */
4518 :
4519 0 : if (! chain->need_elim && ! chain->need_reload
4520 0 : && ! chain->need_operand_change)
4521 0 : n_reloads = 0;
4522 : /* First find the pseudo regs that must be reloaded for this insn.
4523 : This info is returned in the tables reload_... (see reload.h).
4524 : Also modify the body of INSN by substituting RELOAD
4525 : rtx's for those pseudo regs. */
4526 : else
4527 : {
4528 0 : CLEAR_REG_SET (®_has_output_reload);
4529 0 : CLEAR_HARD_REG_SET (reg_is_output_reload);
4530 :
4531 0 : find_reloads (insn, 1, spill_indirect_levels, live_known,
4532 : spill_reg_order);
4533 : }
4534 :
4535 0 : if (n_reloads > 0)
4536 : {
4537 0 : rtx_insn *next = NEXT_INSN (insn);
4538 :
4539 : /* ??? PREV can get deleted by reload inheritance.
4540 : Work around this by emitting a marker note. */
4541 0 : prev = PREV_INSN (insn);
4542 0 : reorder_insns_nobb (marker, marker, prev);
4543 :
4544 : /* Now compute which reload regs to reload them into. Perhaps
4545 : reusing reload regs from previous insns, or else output
4546 : load insns to reload them. Maybe output store insns too.
4547 : Record the choices of reload reg in reload_reg_rtx. */
4548 0 : choose_reload_regs (chain);
4549 :
4550 : /* Generate the insns to reload operands into or out of
4551 : their reload regs. */
4552 0 : emit_reload_insns (chain);
4553 :
4554 : /* Substitute the chosen reload regs from reload_reg_rtx
4555 : into the insn's body (or perhaps into the bodies of other
4556 : load and store insn that we just made for reloading
4557 : and that we moved the structure into). */
4558 0 : subst_reloads (insn);
4559 :
4560 0 : prev = PREV_INSN (marker);
4561 0 : unlink_insn_chain (marker, marker);
4562 :
4563 : /* Adjust the exception region notes for loads and stores. */
4564 0 : if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4565 0 : fixup_eh_region_note (insn, prev, next);
4566 :
4567 : /* Adjust the location of REG_ARGS_SIZE. */
4568 0 : rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4569 0 : if (p)
4570 : {
4571 0 : remove_note (insn, p);
4572 0 : fixup_args_size_notes (prev, PREV_INSN (next),
4573 : get_args_size (p));
4574 : }
4575 :
4576 : /* If this was an ASM, make sure that all the reload insns
4577 : we have generated are valid. If not, give an error
4578 : and delete them. */
4579 0 : if (asm_noperands (PATTERN (insn)) >= 0)
4580 0 : for (rtx_insn *p = NEXT_INSN (prev);
4581 0 : p != next;
4582 0 : p = NEXT_INSN (p))
4583 0 : if (p != insn && INSN_P (p)
4584 0 : && GET_CODE (PATTERN (p)) != USE
4585 0 : && (recog_memoized (p) < 0
4586 0 : || (extract_insn (p),
4587 0 : !(constrain_operands (1,
4588 : get_enabled_alternatives (p))))))
4589 : {
4590 0 : error_for_asm (insn,
4591 : "%<asm%> operand requires "
4592 : "impossible reload");
4593 0 : delete_insn (p);
4594 : }
4595 : }
4596 :
4597 0 : if (num_eliminable && chain->need_elim)
4598 0 : update_eliminable_offsets ();
4599 :
4600 : /* Any previously reloaded spilled pseudo reg, stored in this insn,
4601 : is no longer validly lying around to save a future reload.
4602 : Note that this does not detect pseudos that were reloaded
4603 : for this insn in order to be stored in
4604 : (obeying register constraints). That is correct; such reload
4605 : registers ARE still valid. */
4606 0 : forget_marked_reloads (®s_to_forget);
4607 0 : CLEAR_REG_SET (®s_to_forget);
4608 :
4609 : /* There may have been CLOBBER insns placed after INSN. So scan
4610 : between INSN and NEXT and use them to forget old reloads. */
4611 0 : for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4612 0 : if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4613 0 : note_stores (x, forget_old_reloads_1, NULL);
4614 :
4615 : #if AUTO_INC_DEC
4616 : /* Likewise for regs altered by auto-increment in this insn.
4617 : REG_INC notes have been changed by reloading:
4618 : find_reloads_address_1 records substitutions for them,
4619 : which have been performed by subst_reloads above. */
4620 : for (i = n_reloads - 1; i >= 0; i--)
4621 : {
4622 : rtx in_reg = rld[i].in_reg;
4623 : if (in_reg)
4624 : {
4625 : enum rtx_code code = GET_CODE (in_reg);
4626 : /* PRE_INC / PRE_DEC will have the reload register ending up
4627 : with the same value as the stack slot, but that doesn't
4628 : hold true for POST_INC / POST_DEC. Either we have to
4629 : convert the memory access to a true POST_INC / POST_DEC,
4630 : or we can't use the reload register for inheritance. */
4631 : if ((code == POST_INC || code == POST_DEC)
4632 : && TEST_HARD_REG_BIT (reg_reloaded_valid,
4633 : REGNO (rld[i].reg_rtx))
4634 : /* Make sure it is the inc/dec pseudo, and not
4635 : some other (e.g. output operand) pseudo. */
4636 : && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4637 : == REGNO (XEXP (in_reg, 0))))
4638 :
4639 : {
4640 : rtx reload_reg = rld[i].reg_rtx;
4641 : machine_mode mode = GET_MODE (reload_reg);
4642 : int n = 0;
4643 : rtx_insn *p;
4644 :
4645 : for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4646 : {
4647 : /* We really want to ignore REG_INC notes here, so
4648 : use PATTERN (p) as argument to reg_set_p . */
4649 : if (reg_set_p (reload_reg, PATTERN (p)))
4650 : break;
4651 : n = count_occurrences (PATTERN (p), reload_reg, 0);
4652 : if (! n)
4653 : continue;
4654 : if (n == 1)
4655 : {
4656 : rtx replace_reg
4657 : = gen_rtx_fmt_e (code, mode, reload_reg);
4658 :
4659 : validate_replace_rtx_group (reload_reg,
4660 : replace_reg, p);
4661 : n = verify_changes (0);
4662 :
4663 : /* We must also verify that the constraints
4664 : are met after the replacement. Make sure
4665 : extract_insn is only called for an insn
4666 : where the replacements were found to be
4667 : valid so far. */
4668 : if (n)
4669 : {
4670 : extract_insn (p);
4671 : n = constrain_operands (1,
4672 : get_enabled_alternatives (p));
4673 : }
4674 :
4675 : /* If the constraints were not met, then
4676 : undo the replacement, else confirm it. */
4677 : if (!n)
4678 : cancel_changes (0);
4679 : else
4680 : confirm_change_group ();
4681 : }
4682 : break;
4683 : }
4684 : if (n == 1)
4685 : {
4686 : add_reg_note (p, REG_INC, reload_reg);
4687 : /* Mark this as having an output reload so that the
4688 : REG_INC processing code below won't invalidate
4689 : the reload for inheritance. */
4690 : SET_HARD_REG_BIT (reg_is_output_reload,
4691 : REGNO (reload_reg));
4692 : SET_REGNO_REG_SET (®_has_output_reload,
4693 : REGNO (XEXP (in_reg, 0)));
4694 : }
4695 : else
4696 : forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4697 : NULL);
4698 : }
4699 : else if ((code == PRE_INC || code == PRE_DEC)
4700 : && TEST_HARD_REG_BIT (reg_reloaded_valid,
4701 : REGNO (rld[i].reg_rtx))
4702 : /* Make sure it is the inc/dec pseudo, and not
4703 : some other (e.g. output operand) pseudo. */
4704 : && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4705 : == REGNO (XEXP (in_reg, 0))))
4706 : {
4707 : SET_HARD_REG_BIT (reg_is_output_reload,
4708 : REGNO (rld[i].reg_rtx));
4709 : SET_REGNO_REG_SET (®_has_output_reload,
4710 : REGNO (XEXP (in_reg, 0)));
4711 : }
4712 : else if (code == PRE_INC || code == PRE_DEC
4713 : || code == POST_INC || code == POST_DEC)
4714 : {
4715 : int in_regno = REGNO (XEXP (in_reg, 0));
4716 :
4717 : if (reg_last_reload_reg[in_regno] != NULL_RTX)
4718 : {
4719 : int in_hard_regno;
4720 : bool forget_p = true;
4721 :
4722 : in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4723 : if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4724 : in_hard_regno))
4725 : {
4726 : for (rtx_insn *x = (old_prev ?
4727 : NEXT_INSN (old_prev) : insn);
4728 : x != old_next;
4729 : x = NEXT_INSN (x))
4730 : if (x == reg_reloaded_insn[in_hard_regno])
4731 : {
4732 : forget_p = false;
4733 : break;
4734 : }
4735 : }
4736 : /* If for some reasons, we didn't set up
4737 : reg_last_reload_reg in this insn,
4738 : invalidate inheritance from previous
4739 : insns for the incremented/decremented
4740 : register. Such registers will be not in
4741 : reg_has_output_reload. Invalidate it
4742 : also if the corresponding element in
4743 : reg_reloaded_insn is also
4744 : invalidated. */
4745 : if (forget_p)
4746 : forget_old_reloads_1 (XEXP (in_reg, 0),
4747 : NULL_RTX, NULL);
4748 : }
4749 : }
4750 : }
4751 : }
4752 : /* If a pseudo that got a hard register is auto-incremented,
4753 : we must purge records of copying it into pseudos without
4754 : hard registers. */
4755 : for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4756 : if (REG_NOTE_KIND (x) == REG_INC)
4757 : {
4758 : /* See if this pseudo reg was reloaded in this insn.
4759 : If so, its last-reload info is still valid
4760 : because it is based on this insn's reload. */
4761 : for (i = 0; i < n_reloads; i++)
4762 : if (rld[i].out == XEXP (x, 0))
4763 : break;
4764 :
4765 : if (i == n_reloads)
4766 : forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4767 : }
4768 : #endif
4769 : }
4770 : /* A reload reg's contents are unknown after a label. */
4771 0 : if (LABEL_P (insn))
4772 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4773 :
4774 : /* Don't assume a reload reg is still good after a call insn
4775 : if it is a call-used reg, or if it contains a value that will
4776 : be partially clobbered by the call. */
4777 0 : else if (CALL_P (insn))
4778 : {
4779 0 : reg_reloaded_valid
4780 0 : &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers ();
4781 :
4782 : /* If this is a call to a setjmp-type function, we must not
4783 : reuse any reload reg contents across the call; that will
4784 : just be clobbered by other uses of the register in later
4785 : code, before the longjmp. */
4786 0 : if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4787 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4788 : }
4789 : }
4790 :
4791 : /* Clean up. */
4792 0 : free (reg_last_reload_reg);
4793 0 : CLEAR_REG_SET (®_has_output_reload);
4794 0 : }
4795 :
4796 : /* Discard all record of any value reloaded from X,
4797 : or reloaded in X from someplace else;
4798 : unless X is an output reload reg of the current insn.
4799 :
4800 : X may be a hard reg (the reload reg)
4801 : or it may be a pseudo reg that was reloaded from.
4802 :
4803 : When DATA is non-NULL just mark the registers in regset
4804 : to be forgotten later. */
4805 :
4806 : static void
4807 0 : forget_old_reloads_1 (rtx x, const_rtx, void *data)
4808 : {
4809 0 : unsigned int regno;
4810 0 : unsigned int nr;
4811 0 : regset regs = (regset) data;
4812 :
4813 : /* note_stores does give us subregs of hard regs,
4814 : subreg_regno_offset requires a hard reg. */
4815 0 : while (GET_CODE (x) == SUBREG)
4816 : {
4817 : /* We ignore the subreg offset when calculating the regno,
4818 : because we are using the entire underlying hard register
4819 : below. */
4820 0 : x = SUBREG_REG (x);
4821 : }
4822 :
4823 0 : if (!REG_P (x))
4824 : return;
4825 :
4826 0 : regno = REGNO (x);
4827 :
4828 0 : if (regno >= FIRST_PSEUDO_REGISTER)
4829 : nr = 1;
4830 : else
4831 : {
4832 0 : unsigned int i;
4833 :
4834 0 : nr = REG_NREGS (x);
4835 : /* Storing into a spilled-reg invalidates its contents.
4836 : This can happen if a block-local pseudo is allocated to that reg
4837 : and it wasn't spilled because this block's total need is 0.
4838 : Then some insn might have an optional reload and use this reg. */
4839 0 : if (!regs)
4840 0 : for (i = 0; i < nr; i++)
4841 : /* But don't do this if the reg actually serves as an output
4842 : reload reg in the current instruction. */
4843 0 : if (n_reloads == 0
4844 0 : || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4845 : {
4846 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4847 0 : spill_reg_store[regno + i] = 0;
4848 : }
4849 : }
4850 :
4851 0 : if (regs)
4852 0 : while (nr-- > 0)
4853 0 : SET_REGNO_REG_SET (regs, regno + nr);
4854 : else
4855 : {
4856 : /* Since value of X has changed,
4857 : forget any value previously copied from it. */
4858 :
4859 0 : while (nr-- > 0)
4860 : /* But don't forget a copy if this is the output reload
4861 : that establishes the copy's validity. */
4862 0 : if (n_reloads == 0
4863 0 : || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4864 0 : reg_last_reload_reg[regno + nr] = 0;
4865 : }
4866 : }
4867 :
4868 : /* Forget the reloads marked in regset by previous function. */
4869 : static void
4870 0 : forget_marked_reloads (regset regs)
4871 : {
4872 0 : unsigned int reg;
4873 0 : reg_set_iterator rsi;
4874 0 : EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4875 : {
4876 0 : if (reg < FIRST_PSEUDO_REGISTER
4877 : /* But don't do this if the reg actually serves as an output
4878 : reload reg in the current instruction. */
4879 0 : && (n_reloads == 0
4880 0 : || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4881 : {
4882 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4883 0 : spill_reg_store[reg] = 0;
4884 : }
4885 0 : if (n_reloads == 0
4886 0 : || !REGNO_REG_SET_P (®_has_output_reload, reg))
4887 0 : reg_last_reload_reg[reg] = 0;
4888 : }
4889 0 : }
4890 :
4891 : /* The following HARD_REG_SETs indicate when each hard register is
4892 : used for a reload of various parts of the current insn. */
4893 :
4894 : /* If reg is unavailable for all reloads. */
4895 : static HARD_REG_SET reload_reg_unavailable;
4896 : /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4897 : static HARD_REG_SET reload_reg_used;
4898 : /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4899 : static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4900 : /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4901 : static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4902 : /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4903 : static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4904 : /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4905 : static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4906 : /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4907 : static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4908 : /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4909 : static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4910 : /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4911 : static HARD_REG_SET reload_reg_used_in_op_addr;
4912 : /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4913 : static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4914 : /* If reg is in use for a RELOAD_FOR_INSN reload. */
4915 : static HARD_REG_SET reload_reg_used_in_insn;
4916 : /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4917 : static HARD_REG_SET reload_reg_used_in_other_addr;
4918 :
4919 : /* If reg is in use as a reload reg for any sort of reload. */
4920 : static HARD_REG_SET reload_reg_used_at_all;
4921 :
4922 : /* If reg is use as an inherited reload. We just mark the first register
4923 : in the group. */
4924 : static HARD_REG_SET reload_reg_used_for_inherit;
4925 :
4926 : /* Records which hard regs are used in any way, either as explicit use or
4927 : by being allocated to a pseudo during any point of the current insn. */
4928 : static HARD_REG_SET reg_used_in_insn;
4929 :
4930 : /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4931 : TYPE. MODE is used to indicate how many consecutive regs are
4932 : actually used. */
4933 :
4934 : static void
4935 0 : mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4936 : machine_mode mode)
4937 : {
4938 0 : switch (type)
4939 : {
4940 0 : case RELOAD_OTHER:
4941 0 : add_to_hard_reg_set (&reload_reg_used, mode, regno);
4942 0 : break;
4943 :
4944 0 : case RELOAD_FOR_INPUT_ADDRESS:
4945 0 : add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
4946 0 : break;
4947 :
4948 0 : case RELOAD_FOR_INPADDR_ADDRESS:
4949 0 : add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
4950 0 : break;
4951 :
4952 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
4953 0 : add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
4954 0 : break;
4955 :
4956 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
4957 0 : add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
4958 0 : break;
4959 :
4960 0 : case RELOAD_FOR_OPERAND_ADDRESS:
4961 0 : add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
4962 0 : break;
4963 :
4964 0 : case RELOAD_FOR_OPADDR_ADDR:
4965 0 : add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
4966 0 : break;
4967 :
4968 0 : case RELOAD_FOR_OTHER_ADDRESS:
4969 0 : add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
4970 0 : break;
4971 :
4972 0 : case RELOAD_FOR_INPUT:
4973 0 : add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
4974 0 : break;
4975 :
4976 0 : case RELOAD_FOR_OUTPUT:
4977 0 : add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
4978 0 : break;
4979 :
4980 0 : case RELOAD_FOR_INSN:
4981 0 : add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
4982 0 : break;
4983 : }
4984 :
4985 0 : add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
4986 0 : }
4987 :
4988 : /* Similarly, but show REGNO is no longer in use for a reload. */
4989 :
4990 : static void
4991 0 : clear_reload_reg_in_use (unsigned int regno, int opnum,
4992 : enum reload_type type, machine_mode mode)
4993 : {
4994 0 : unsigned int nregs = hard_regno_nregs (regno, mode);
4995 0 : unsigned int start_regno, end_regno, r;
4996 0 : int i;
4997 : /* A complication is that for some reload types, inheritance might
4998 : allow multiple reloads of the same types to share a reload register.
4999 : We set check_opnum if we have to check only reloads with the same
5000 : operand number, and check_any if we have to check all reloads. */
5001 0 : int check_opnum = 0;
5002 0 : int check_any = 0;
5003 0 : HARD_REG_SET *used_in_set;
5004 :
5005 0 : switch (type)
5006 : {
5007 : case RELOAD_OTHER:
5008 : used_in_set = &reload_reg_used;
5009 : break;
5010 :
5011 0 : case RELOAD_FOR_INPUT_ADDRESS:
5012 0 : used_in_set = &reload_reg_used_in_input_addr[opnum];
5013 0 : break;
5014 :
5015 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5016 0 : check_opnum = 1;
5017 0 : used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5018 0 : break;
5019 :
5020 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5021 0 : used_in_set = &reload_reg_used_in_output_addr[opnum];
5022 0 : break;
5023 :
5024 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5025 0 : check_opnum = 1;
5026 0 : used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5027 0 : break;
5028 :
5029 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5030 0 : used_in_set = &reload_reg_used_in_op_addr;
5031 0 : break;
5032 :
5033 0 : case RELOAD_FOR_OPADDR_ADDR:
5034 0 : check_any = 1;
5035 0 : used_in_set = &reload_reg_used_in_op_addr_reload;
5036 0 : break;
5037 :
5038 0 : case RELOAD_FOR_OTHER_ADDRESS:
5039 0 : used_in_set = &reload_reg_used_in_other_addr;
5040 0 : check_any = 1;
5041 0 : break;
5042 :
5043 0 : case RELOAD_FOR_INPUT:
5044 0 : used_in_set = &reload_reg_used_in_input[opnum];
5045 0 : break;
5046 :
5047 0 : case RELOAD_FOR_OUTPUT:
5048 0 : used_in_set = &reload_reg_used_in_output[opnum];
5049 0 : break;
5050 :
5051 0 : case RELOAD_FOR_INSN:
5052 0 : used_in_set = &reload_reg_used_in_insn;
5053 0 : break;
5054 0 : default:
5055 0 : gcc_unreachable ();
5056 : }
5057 : /* We resolve conflicts with remaining reloads of the same type by
5058 : excluding the intervals of reload registers by them from the
5059 : interval of freed reload registers. Since we only keep track of
5060 : one set of interval bounds, we might have to exclude somewhat
5061 : more than what would be necessary if we used a HARD_REG_SET here.
5062 : But this should only happen very infrequently, so there should
5063 : be no reason to worry about it. */
5064 :
5065 0 : start_regno = regno;
5066 0 : end_regno = regno + nregs;
5067 0 : if (check_opnum || check_any)
5068 : {
5069 0 : for (i = n_reloads - 1; i >= 0; i--)
5070 : {
5071 0 : if (rld[i].when_needed == type
5072 0 : && (check_any || rld[i].opnum == opnum)
5073 0 : && rld[i].reg_rtx)
5074 : {
5075 0 : unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5076 0 : unsigned int conflict_end
5077 0 : = end_hard_regno (rld[i].mode, conflict_start);
5078 :
5079 : /* If there is an overlap with the first to-be-freed register,
5080 : adjust the interval start. */
5081 0 : if (conflict_start <= start_regno && conflict_end > start_regno)
5082 0 : start_regno = conflict_end;
5083 : /* Otherwise, if there is a conflict with one of the other
5084 : to-be-freed registers, adjust the interval end. */
5085 0 : if (conflict_start > start_regno && conflict_start < end_regno)
5086 0 : end_regno = conflict_start;
5087 : }
5088 : }
5089 : }
5090 :
5091 0 : for (r = start_regno; r < end_regno; r++)
5092 0 : CLEAR_HARD_REG_BIT (*used_in_set, r);
5093 0 : }
5094 :
5095 : /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5096 : specified by OPNUM and TYPE. */
5097 :
5098 : static int
5099 0 : reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5100 : {
5101 0 : int i;
5102 :
5103 : /* In use for a RELOAD_OTHER means it's not available for anything. */
5104 0 : if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5105 0 : || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5106 : return 0;
5107 :
5108 0 : switch (type)
5109 : {
5110 0 : case RELOAD_OTHER:
5111 : /* In use for anything means we can't use it for RELOAD_OTHER. */
5112 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5113 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5114 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5115 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5116 : return 0;
5117 :
5118 0 : for (i = 0; i < reload_n_operands; i++)
5119 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5120 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5121 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5122 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5123 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5124 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5125 : return 0;
5126 :
5127 : return 1;
5128 :
5129 0 : case RELOAD_FOR_INPUT:
5130 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5131 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5132 : return 0;
5133 :
5134 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5135 : return 0;
5136 :
5137 : /* If it is used for some other input, can't use it. */
5138 0 : for (i = 0; i < reload_n_operands; i++)
5139 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5140 : return 0;
5141 :
5142 : /* If it is used in a later operand's address, can't use it. */
5143 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5144 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5145 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5146 : return 0;
5147 :
5148 : return 1;
5149 :
5150 0 : case RELOAD_FOR_INPUT_ADDRESS:
5151 : /* Can't use a register if it is used for an input address for this
5152 : operand or used as an input in an earlier one. */
5153 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5154 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5155 : return 0;
5156 :
5157 0 : for (i = 0; i < opnum; i++)
5158 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5159 : return 0;
5160 :
5161 : return 1;
5162 :
5163 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5164 : /* Can't use a register if it is used for an input address
5165 : for this operand or used as an input in an earlier
5166 : one. */
5167 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5168 : return 0;
5169 :
5170 0 : for (i = 0; i < opnum; i++)
5171 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5172 : return 0;
5173 :
5174 : return 1;
5175 :
5176 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5177 : /* Can't use a register if it is used for an output address for this
5178 : operand or used as an output in this or a later operand. Note
5179 : that multiple output operands are emitted in reverse order, so
5180 : the conflicting ones are those with lower indices. */
5181 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5182 : return 0;
5183 :
5184 0 : for (i = 0; i <= opnum; i++)
5185 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5186 : return 0;
5187 :
5188 : return 1;
5189 :
5190 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5191 : /* Can't use a register if it is used for an output address
5192 : for this operand or used as an output in this or a
5193 : later operand. Note that multiple output operands are
5194 : emitted in reverse order, so the conflicting ones are
5195 : those with lower indices. */
5196 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5197 : return 0;
5198 :
5199 0 : for (i = 0; i <= opnum; i++)
5200 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5201 : return 0;
5202 :
5203 : return 1;
5204 :
5205 : case RELOAD_FOR_OPERAND_ADDRESS:
5206 0 : for (i = 0; i < reload_n_operands; i++)
5207 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5208 : return 0;
5209 :
5210 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5211 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5212 :
5213 : case RELOAD_FOR_OPADDR_ADDR:
5214 0 : for (i = 0; i < reload_n_operands; i++)
5215 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5216 : return 0;
5217 :
5218 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5219 :
5220 0 : case RELOAD_FOR_OUTPUT:
5221 : /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5222 : outputs, or an operand address for this or an earlier output.
5223 : Note that multiple output operands are emitted in reverse order,
5224 : so the conflicting ones are those with higher indices. */
5225 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5226 : return 0;
5227 :
5228 0 : for (i = 0; i < reload_n_operands; i++)
5229 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5230 : return 0;
5231 :
5232 0 : for (i = opnum; i < reload_n_operands; i++)
5233 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5234 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5235 : return 0;
5236 :
5237 : return 1;
5238 :
5239 : case RELOAD_FOR_INSN:
5240 0 : for (i = 0; i < reload_n_operands; i++)
5241 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5242 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5243 : return 0;
5244 :
5245 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5246 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5247 :
5248 0 : case RELOAD_FOR_OTHER_ADDRESS:
5249 0 : return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5250 :
5251 0 : default:
5252 0 : gcc_unreachable ();
5253 : }
5254 : }
5255 :
5256 : /* Return 1 if the value in reload reg REGNO, as used by the reload with
5257 : the number RELOADNUM, is still available in REGNO at the end of the insn.
5258 :
5259 : We can assume that the reload reg was already tested for availability
5260 : at the time it is needed, and we should not check this again,
5261 : in case the reg has already been marked in use. */
5262 :
5263 : static int
5264 0 : reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5265 : {
5266 0 : int opnum = rld[reloadnum].opnum;
5267 0 : enum reload_type type = rld[reloadnum].when_needed;
5268 0 : int i;
5269 :
5270 : /* See if there is a reload with the same type for this operand, using
5271 : the same register. This case is not handled by the code below. */
5272 0 : for (i = reloadnum + 1; i < n_reloads; i++)
5273 : {
5274 0 : rtx reg;
5275 :
5276 0 : if (rld[i].opnum != opnum || rld[i].when_needed != type)
5277 0 : continue;
5278 0 : reg = rld[i].reg_rtx;
5279 0 : if (reg == NULL_RTX)
5280 0 : continue;
5281 0 : if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5282 : return 0;
5283 : }
5284 :
5285 0 : switch (type)
5286 : {
5287 : case RELOAD_OTHER:
5288 : /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5289 : its value must reach the end. */
5290 : return 1;
5291 :
5292 : /* If this use is for part of the insn,
5293 : its value reaches if no subsequent part uses the same register.
5294 : Just like the above function, don't try to do this with lots
5295 : of fallthroughs. */
5296 :
5297 : case RELOAD_FOR_OTHER_ADDRESS:
5298 : /* Here we check for everything else, since these don't conflict
5299 : with anything else and everything comes later. */
5300 :
5301 0 : for (i = 0; i < reload_n_operands; i++)
5302 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5303 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5304 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5305 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5306 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5307 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5308 : return 0;
5309 :
5310 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5311 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5312 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5313 0 : && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5314 :
5315 : case RELOAD_FOR_INPUT_ADDRESS:
5316 : case RELOAD_FOR_INPADDR_ADDRESS:
5317 : /* Similar, except that we check only for this and subsequent inputs
5318 : and the address of only subsequent inputs and we do not need
5319 : to check for RELOAD_OTHER objects since they are known not to
5320 : conflict. */
5321 :
5322 0 : for (i = opnum; i < reload_n_operands; i++)
5323 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5324 : return 0;
5325 :
5326 : /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5327 : could be killed if the register is also used by reload with type
5328 : RELOAD_FOR_INPUT_ADDRESS, so check it. */
5329 0 : if (type == RELOAD_FOR_INPADDR_ADDRESS
5330 0 : && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5331 : return 0;
5332 :
5333 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5334 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5335 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5336 : return 0;
5337 :
5338 0 : for (i = 0; i < reload_n_operands; i++)
5339 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5340 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5341 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5342 : return 0;
5343 :
5344 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5345 : return 0;
5346 :
5347 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5348 0 : && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5349 0 : && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5350 :
5351 0 : case RELOAD_FOR_INPUT:
5352 : /* Similar to input address, except we start at the next operand for
5353 : both input and input address and we do not check for
5354 : RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5355 : would conflict. */
5356 :
5357 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5358 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5359 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5360 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5361 : return 0;
5362 :
5363 : /* ... fall through ... */
5364 :
5365 : case RELOAD_FOR_OPERAND_ADDRESS:
5366 : /* Check outputs and their addresses. */
5367 :
5368 0 : for (i = 0; i < reload_n_operands; i++)
5369 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5370 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5371 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5372 : return 0;
5373 :
5374 0 : return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5375 :
5376 : case RELOAD_FOR_OPADDR_ADDR:
5377 0 : for (i = 0; i < reload_n_operands; i++)
5378 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5379 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5380 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5381 : return 0;
5382 :
5383 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5384 0 : && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5385 0 : && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5386 :
5387 0 : case RELOAD_FOR_INSN:
5388 : /* These conflict with other outputs with RELOAD_OTHER. So
5389 : we need only check for output addresses. */
5390 :
5391 0 : opnum = reload_n_operands;
5392 :
5393 : /* fall through */
5394 :
5395 0 : case RELOAD_FOR_OUTPUT:
5396 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5397 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5398 : /* We already know these can't conflict with a later output. So the
5399 : only thing to check are later output addresses.
5400 : Note that multiple output operands are emitted in reverse order,
5401 : so the conflicting ones are those with lower indices. */
5402 0 : for (i = 0; i < opnum; i++)
5403 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5404 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5405 : return 0;
5406 :
5407 : /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5408 : could be killed if the register is also used by reload with type
5409 : RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5410 0 : if (type == RELOAD_FOR_OUTADDR_ADDRESS
5411 0 : && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5412 : return 0;
5413 :
5414 : return 1;
5415 :
5416 0 : default:
5417 0 : gcc_unreachable ();
5418 : }
5419 : }
5420 :
5421 : /* Like reload_reg_reaches_end_p, but check that the condition holds for
5422 : every register in REG. */
5423 :
5424 : static bool
5425 0 : reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5426 : {
5427 0 : unsigned int i;
5428 :
5429 0 : for (i = REGNO (reg); i < END_REGNO (reg); i++)
5430 0 : if (!reload_reg_reaches_end_p (i, reloadnum))
5431 : return false;
5432 : return true;
5433 : }
5434 :
5435 :
5436 : /* Returns whether R1 and R2 are uniquely chained: the value of one
5437 : is used by the other, and that value is not used by any other
5438 : reload for this insn. This is used to partially undo the decision
5439 : made in find_reloads when in the case of multiple
5440 : RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5441 : RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5442 : reloads. This code tries to avoid the conflict created by that
5443 : change. It might be cleaner to explicitly keep track of which
5444 : RELOAD_FOR_OPADDR_ADDR reload is associated with which
5445 : RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5446 : this after the fact. */
5447 : static bool
5448 0 : reloads_unique_chain_p (int r1, int r2)
5449 : {
5450 0 : int i;
5451 :
5452 : /* We only check input reloads. */
5453 0 : if (! rld[r1].in || ! rld[r2].in)
5454 : return false;
5455 :
5456 : /* Avoid anything with output reloads. */
5457 0 : if (rld[r1].out || rld[r2].out)
5458 : return false;
5459 :
5460 : /* "chained" means one reload is a component of the other reload,
5461 : not the same as the other reload. */
5462 0 : if (rld[r1].opnum != rld[r2].opnum
5463 0 : || rtx_equal_p (rld[r1].in, rld[r2].in)
5464 0 : || rld[r1].optional || rld[r2].optional
5465 0 : || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5466 0 : || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5467 0 : return false;
5468 :
5469 : /* The following loop assumes that r1 is the reload that feeds r2. */
5470 0 : if (r1 > r2)
5471 0 : std::swap (r1, r2);
5472 :
5473 0 : for (i = 0; i < n_reloads; i ++)
5474 : /* Look for input reloads that aren't our two */
5475 0 : if (i != r1 && i != r2 && rld[i].in)
5476 : {
5477 : /* If our reload is mentioned at all, it isn't a simple chain. */
5478 0 : if (reg_mentioned_p (rld[r1].in, rld[i].in))
5479 : return false;
5480 : }
5481 : return true;
5482 : }
5483 :
5484 : /* The recursive function change all occurrences of WHAT in *WHERE
5485 : to REPL. */
5486 : static void
5487 0 : substitute (rtx *where, const_rtx what, rtx repl)
5488 : {
5489 0 : const char *fmt;
5490 0 : int i;
5491 0 : enum rtx_code code;
5492 :
5493 0 : if (*where == 0)
5494 : return;
5495 :
5496 0 : if (*where == what || rtx_equal_p (*where, what))
5497 : {
5498 : /* Record the location of the changed rtx. */
5499 0 : substitute_stack.safe_push (where);
5500 0 : *where = repl;
5501 0 : return;
5502 : }
5503 :
5504 0 : code = GET_CODE (*where);
5505 0 : fmt = GET_RTX_FORMAT (code);
5506 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5507 : {
5508 0 : if (fmt[i] == 'E')
5509 : {
5510 0 : int j;
5511 :
5512 0 : for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5513 0 : substitute (&XVECEXP (*where, i, j), what, repl);
5514 : }
5515 0 : else if (fmt[i] == 'e')
5516 0 : substitute (&XEXP (*where, i), what, repl);
5517 : }
5518 : }
5519 :
5520 : /* The function returns TRUE if chain of reload R1 and R2 (in any
5521 : order) can be evaluated without usage of intermediate register for
5522 : the reload containing another reload. It is important to see
5523 : gen_reload to understand what the function is trying to do. As an
5524 : example, let us have reload chain
5525 :
5526 : r2: const
5527 : r1: <something> + const
5528 :
5529 : and reload R2 got reload reg HR. The function returns true if
5530 : there is a correct insn HR = HR + <something>. Otherwise,
5531 : gen_reload will use intermediate register (and this is the reload
5532 : reg for R1) to reload <something>.
5533 :
5534 : We need this function to find a conflict for chain reloads. In our
5535 : example, if HR = HR + <something> is incorrect insn, then we cannot
5536 : use HR as a reload register for R2. If we do use it then we get a
5537 : wrong code:
5538 :
5539 : HR = const
5540 : HR = <something>
5541 : HR = HR + HR
5542 :
5543 : */
5544 : static bool
5545 0 : gen_reload_chain_without_interm_reg_p (int r1, int r2)
5546 : {
5547 : /* Assume other cases in gen_reload are not possible for
5548 : chain reloads or do need an intermediate hard registers. */
5549 0 : bool result = true;
5550 0 : int regno, code;
5551 0 : rtx out, in;
5552 0 : rtx_insn *insn;
5553 0 : rtx_insn *last = get_last_insn ();
5554 :
5555 : /* Make r2 a component of r1. */
5556 0 : if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5557 0 : std::swap (r1, r2);
5558 :
5559 0 : gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5560 0 : regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5561 0 : gcc_assert (regno >= 0);
5562 0 : out = gen_rtx_REG (rld[r1].mode, regno);
5563 0 : in = rld[r1].in;
5564 0 : substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5565 :
5566 : /* If IN is a paradoxical SUBREG, remove it and try to put the
5567 : opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5568 0 : strip_paradoxical_subreg (&in, &out);
5569 :
5570 0 : if (GET_CODE (in) == PLUS
5571 0 : && (REG_P (XEXP (in, 0))
5572 : || GET_CODE (XEXP (in, 0)) == SUBREG
5573 : || MEM_P (XEXP (in, 0)))
5574 0 : && (REG_P (XEXP (in, 1))
5575 0 : || GET_CODE (XEXP (in, 1)) == SUBREG
5576 0 : || CONSTANT_P (XEXP (in, 1))
5577 0 : || MEM_P (XEXP (in, 1))))
5578 : {
5579 0 : insn = emit_insn (gen_rtx_SET (out, in));
5580 0 : code = recog_memoized (insn);
5581 0 : result = false;
5582 :
5583 0 : if (code >= 0)
5584 : {
5585 0 : extract_insn (insn);
5586 : /* We want constrain operands to treat this insn strictly in
5587 : its validity determination, i.e., the way it would after
5588 : reload has completed. */
5589 0 : result = constrain_operands (1, get_enabled_alternatives (insn));
5590 : }
5591 :
5592 0 : delete_insns_since (last);
5593 : }
5594 :
5595 : /* Restore the original value at each changed address within R1. */
5596 0 : while (!substitute_stack.is_empty ())
5597 : {
5598 0 : rtx *where = substitute_stack.pop ();
5599 0 : *where = rld[r2].in;
5600 : }
5601 :
5602 0 : return result;
5603 : }
5604 :
5605 : /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5606 : Return 0 otherwise.
5607 :
5608 : This function uses the same algorithm as reload_reg_free_p above. */
5609 :
5610 : static int
5611 0 : reloads_conflict (int r1, int r2)
5612 : {
5613 0 : enum reload_type r1_type = rld[r1].when_needed;
5614 0 : enum reload_type r2_type = rld[r2].when_needed;
5615 0 : int r1_opnum = rld[r1].opnum;
5616 0 : int r2_opnum = rld[r2].opnum;
5617 :
5618 : /* RELOAD_OTHER conflicts with everything. */
5619 0 : if (r2_type == RELOAD_OTHER)
5620 : return 1;
5621 :
5622 : /* Otherwise, check conflicts differently for each type. */
5623 :
5624 0 : switch (r1_type)
5625 : {
5626 0 : case RELOAD_FOR_INPUT:
5627 0 : return (r2_type == RELOAD_FOR_INSN
5628 0 : || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5629 0 : || r2_type == RELOAD_FOR_OPADDR_ADDR
5630 0 : || r2_type == RELOAD_FOR_INPUT
5631 0 : || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5632 0 : || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5633 0 : && r2_opnum > r1_opnum));
5634 :
5635 0 : case RELOAD_FOR_INPUT_ADDRESS:
5636 0 : return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5637 0 : || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5638 :
5639 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5640 0 : return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5641 0 : || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5642 :
5643 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5644 0 : return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5645 0 : || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5646 :
5647 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5648 0 : return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5649 0 : || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5650 :
5651 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5652 0 : return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5653 0 : || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5654 0 : && (!reloads_unique_chain_p (r1, r2)
5655 0 : || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5656 :
5657 0 : case RELOAD_FOR_OPADDR_ADDR:
5658 0 : return (r2_type == RELOAD_FOR_INPUT
5659 0 : || r2_type == RELOAD_FOR_OPADDR_ADDR);
5660 :
5661 0 : case RELOAD_FOR_OUTPUT:
5662 0 : return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5663 0 : || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5664 0 : || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5665 0 : && r2_opnum >= r1_opnum));
5666 :
5667 0 : case RELOAD_FOR_INSN:
5668 0 : return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5669 0 : || r2_type == RELOAD_FOR_INSN
5670 0 : || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5671 :
5672 0 : case RELOAD_FOR_OTHER_ADDRESS:
5673 0 : return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5674 :
5675 : case RELOAD_OTHER:
5676 : return 1;
5677 :
5678 0 : default:
5679 0 : gcc_unreachable ();
5680 : }
5681 : }
5682 :
5683 : /* Indexed by reload number, 1 if incoming value
5684 : inherited from previous insns. */
5685 : static char reload_inherited[MAX_RELOADS];
5686 :
5687 : /* For an inherited reload, this is the insn the reload was inherited from,
5688 : if we know it. Otherwise, this is 0. */
5689 : static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5690 :
5691 : /* If nonzero, this is a place to get the value of the reload,
5692 : rather than using reload_in. */
5693 : static rtx reload_override_in[MAX_RELOADS];
5694 :
5695 : /* For each reload, the hard register number of the register used,
5696 : or -1 if we did not need a register for this reload. */
5697 : static int reload_spill_index[MAX_RELOADS];
5698 :
5699 : /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5700 : static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5701 :
5702 : /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5703 : static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5704 :
5705 : /* Subroutine of free_for_value_p, used to check a single register.
5706 : START_REGNO is the starting regno of the full reload register
5707 : (possibly comprising multiple hard registers) that we are considering. */
5708 :
5709 : static int
5710 0 : reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5711 : enum reload_type type, rtx value, rtx out,
5712 : int reloadnum, int ignore_address_reloads)
5713 : {
5714 0 : int time1;
5715 : /* Set if we see an input reload that must not share its reload register
5716 : with any new earlyclobber, but might otherwise share the reload
5717 : register with an output or input-output reload. */
5718 0 : int check_earlyclobber = 0;
5719 0 : int i;
5720 0 : int copy = 0;
5721 :
5722 0 : if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5723 : return 0;
5724 :
5725 0 : if (out == const0_rtx)
5726 : {
5727 0 : copy = 1;
5728 0 : out = NULL_RTX;
5729 : }
5730 :
5731 : /* We use some pseudo 'time' value to check if the lifetimes of the
5732 : new register use would overlap with the one of a previous reload
5733 : that is not read-only or uses a different value.
5734 : The 'time' used doesn't have to be linear in any shape or form, just
5735 : monotonic.
5736 : Some reload types use different 'buckets' for each operand.
5737 : So there are MAX_RECOG_OPERANDS different time values for each
5738 : such reload type.
5739 : We compute TIME1 as the time when the register for the prospective
5740 : new reload ceases to be live, and TIME2 for each existing
5741 : reload as the time when that the reload register of that reload
5742 : becomes live.
5743 : Where there is little to be gained by exact lifetime calculations,
5744 : we just make conservative assumptions, i.e. a longer lifetime;
5745 : this is done in the 'default:' cases. */
5746 0 : switch (type)
5747 : {
5748 0 : case RELOAD_FOR_OTHER_ADDRESS:
5749 : /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5750 0 : time1 = copy ? 0 : 1;
5751 0 : break;
5752 0 : case RELOAD_OTHER:
5753 0 : time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5754 : break;
5755 : /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5756 : RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5757 : respectively, to the time values for these, we get distinct time
5758 : values. To get distinct time values for each operand, we have to
5759 : multiply opnum by at least three. We round that up to four because
5760 : multiply by four is often cheaper. */
5761 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5762 0 : time1 = opnum * 4 + 2;
5763 0 : break;
5764 0 : case RELOAD_FOR_INPUT_ADDRESS:
5765 0 : time1 = opnum * 4 + 3;
5766 0 : break;
5767 0 : case RELOAD_FOR_INPUT:
5768 : /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5769 : executes (inclusive). */
5770 0 : time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5771 : break;
5772 : case RELOAD_FOR_OPADDR_ADDR:
5773 : /* opnum * 4 + 4
5774 : <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5775 : time1 = MAX_RECOG_OPERANDS * 4 + 1;
5776 : break;
5777 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5778 : /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5779 : is executed. */
5780 0 : time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5781 : break;
5782 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5783 0 : time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5784 0 : break;
5785 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5786 0 : time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5787 0 : break;
5788 : default:
5789 0 : time1 = MAX_RECOG_OPERANDS * 5 + 5;
5790 : }
5791 :
5792 0 : for (i = 0; i < n_reloads; i++)
5793 : {
5794 0 : rtx reg = rld[i].reg_rtx;
5795 0 : if (reg && REG_P (reg)
5796 0 : && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5797 0 : && i != reloadnum)
5798 : {
5799 0 : rtx other_input = rld[i].in;
5800 :
5801 : /* If the other reload loads the same input value, that
5802 : will not cause a conflict only if it's loading it into
5803 : the same register. */
5804 0 : if (true_regnum (reg) != start_regno)
5805 : other_input = NULL_RTX;
5806 0 : if (! other_input || ! rtx_equal_p (other_input, value)
5807 0 : || rld[i].out || out)
5808 : {
5809 0 : int time2;
5810 0 : switch (rld[i].when_needed)
5811 : {
5812 : case RELOAD_FOR_OTHER_ADDRESS:
5813 : time2 = 0;
5814 : break;
5815 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5816 : /* find_reloads makes sure that a
5817 : RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5818 : by at most one - the first -
5819 : RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5820 : address reload is inherited, the address address reload
5821 : goes away, so we can ignore this conflict. */
5822 0 : if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5823 0 : && ignore_address_reloads
5824 : /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5825 : Then the address address is still needed to store
5826 : back the new address. */
5827 0 : && ! rld[reloadnum].out)
5828 0 : continue;
5829 : /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5830 : RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5831 : reloads go away. */
5832 0 : if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5833 0 : && ignore_address_reloads
5834 : /* Unless we are reloading an auto_inc expression. */
5835 0 : && ! rld[reloadnum].out)
5836 0 : continue;
5837 0 : time2 = rld[i].opnum * 4 + 2;
5838 0 : break;
5839 0 : case RELOAD_FOR_INPUT_ADDRESS:
5840 0 : if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5841 0 : && ignore_address_reloads
5842 0 : && ! rld[reloadnum].out)
5843 0 : continue;
5844 0 : time2 = rld[i].opnum * 4 + 3;
5845 0 : break;
5846 0 : case RELOAD_FOR_INPUT:
5847 0 : time2 = rld[i].opnum * 4 + 4;
5848 0 : check_earlyclobber = 1;
5849 0 : break;
5850 : /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5851 : == MAX_RECOG_OPERAND * 4 */
5852 0 : case RELOAD_FOR_OPADDR_ADDR:
5853 0 : if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5854 0 : && ignore_address_reloads
5855 0 : && ! rld[reloadnum].out)
5856 0 : continue;
5857 : time2 = MAX_RECOG_OPERANDS * 4 + 1;
5858 : break;
5859 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5860 0 : time2 = MAX_RECOG_OPERANDS * 4 + 2;
5861 0 : check_earlyclobber = 1;
5862 0 : break;
5863 0 : case RELOAD_FOR_INSN:
5864 0 : time2 = MAX_RECOG_OPERANDS * 4 + 3;
5865 0 : break;
5866 0 : case RELOAD_FOR_OUTPUT:
5867 : /* All RELOAD_FOR_OUTPUT reloads become live just after the
5868 : instruction is executed. */
5869 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4;
5870 0 : break;
5871 : /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5872 : the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5873 : value. */
5874 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5875 0 : if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5876 0 : && ignore_address_reloads
5877 0 : && ! rld[reloadnum].out)
5878 0 : continue;
5879 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5880 0 : break;
5881 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5882 0 : time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5883 0 : break;
5884 0 : case RELOAD_OTHER:
5885 : /* If there is no conflict in the input part, handle this
5886 : like an output reload. */
5887 0 : if (! rld[i].in || rtx_equal_p (other_input, value))
5888 : {
5889 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4;
5890 : /* Earlyclobbered outputs must conflict with inputs. */
5891 0 : if (earlyclobber_operand_p (rld[i].out))
5892 0 : time2 = MAX_RECOG_OPERANDS * 4 + 3;
5893 :
5894 : break;
5895 : }
5896 0 : time2 = 1;
5897 : /* RELOAD_OTHER might be live beyond instruction execution,
5898 : but this is not obvious when we set time2 = 1. So check
5899 : here if there might be a problem with the new reload
5900 : clobbering the register used by the RELOAD_OTHER. */
5901 0 : if (out)
5902 : return 0;
5903 : break;
5904 : default:
5905 : return 0;
5906 : }
5907 0 : if ((time1 >= time2
5908 0 : && (! rld[i].in || rld[i].out
5909 0 : || ! rtx_equal_p (other_input, value)))
5910 0 : || (out && rld[reloadnum].out_reg
5911 0 : && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5912 0 : return 0;
5913 : }
5914 : }
5915 : }
5916 :
5917 : /* Earlyclobbered outputs must conflict with inputs. */
5918 0 : if (check_earlyclobber && out && earlyclobber_operand_p (out))
5919 : return 0;
5920 :
5921 : return 1;
5922 : }
5923 :
5924 : /* Return 1 if the value in reload reg REGNO, as used by a reload
5925 : needed for the part of the insn specified by OPNUM and TYPE,
5926 : may be used to load VALUE into it.
5927 :
5928 : MODE is the mode in which the register is used, this is needed to
5929 : determine how many hard regs to test.
5930 :
5931 : Other read-only reloads with the same value do not conflict
5932 : unless OUT is nonzero and these other reloads have to live while
5933 : output reloads live.
5934 : If OUT is CONST0_RTX, this is a special case: it means that the
5935 : test should not be for using register REGNO as reload register, but
5936 : for copying from register REGNO into the reload register.
5937 :
5938 : RELOADNUM is the number of the reload we want to load this value for;
5939 : a reload does not conflict with itself.
5940 :
5941 : When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5942 : reloads that load an address for the very reload we are considering.
5943 :
5944 : The caller has to make sure that there is no conflict with the return
5945 : register. */
5946 :
5947 : static int
5948 0 : free_for_value_p (int regno, machine_mode mode, int opnum,
5949 : enum reload_type type, rtx value, rtx out, int reloadnum,
5950 : int ignore_address_reloads)
5951 : {
5952 0 : int nregs = hard_regno_nregs (regno, mode);
5953 0 : while (nregs-- > 0)
5954 0 : if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5955 : value, out, reloadnum,
5956 : ignore_address_reloads))
5957 : return 0;
5958 : return 1;
5959 : }
5960 :
5961 : /* Return true if the rtx X is invariant over the current function. */
5962 : /* ??? Actually, the places where we use this expect exactly what is
5963 : tested here, and not everything that is function invariant. In
5964 : particular, the frame pointer and arg pointer are special cased;
5965 : pic_offset_table_rtx is not, and we must not spill these things to
5966 : memory. */
5967 :
5968 : bool
5969 18373735 : function_invariant_p (const_rtx x)
5970 : {
5971 18373735 : if (CONSTANT_P (x))
5972 : return 1;
5973 14064614 : if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5974 : return 1;
5975 14057670 : if (GET_CODE (x) == PLUS
5976 3575595 : && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5977 1647319 : && GET_CODE (XEXP (x, 1)) == CONST_INT)
5978 1647199 : return 1;
5979 : return 0;
5980 : }
5981 :
5982 : /* Determine whether the reload reg X overlaps any rtx'es used for
5983 : overriding inheritance. Return nonzero if so. */
5984 :
5985 : static int
5986 0 : conflicts_with_override (rtx x)
5987 : {
5988 0 : int i;
5989 0 : for (i = 0; i < n_reloads; i++)
5990 0 : if (reload_override_in[i]
5991 0 : && reg_overlap_mentioned_p (x, reload_override_in[i]))
5992 : return 1;
5993 : return 0;
5994 : }
5995 :
5996 : /* Give an error message saying we failed to find a reload for INSN,
5997 : and clear out reload R. */
5998 : static void
5999 0 : failed_reload (rtx_insn *insn, int r)
6000 : {
6001 0 : if (asm_noperands (PATTERN (insn)) < 0)
6002 : /* It's the compiler's fault. */
6003 0 : fatal_insn ("could not find a spill register", insn);
6004 :
6005 : /* It's the user's fault; the operand's mode and constraint
6006 : don't match. Disable this reload so we don't crash in final. */
6007 0 : error_for_asm (insn,
6008 : "%<asm%> operand constraint incompatible with operand size");
6009 0 : rld[r].in = 0;
6010 0 : rld[r].out = 0;
6011 0 : rld[r].reg_rtx = 0;
6012 0 : rld[r].optional = 1;
6013 0 : rld[r].secondary_p = 1;
6014 0 : }
6015 :
6016 : /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6017 : for reload R. If it's valid, get an rtx for it. Return nonzero if
6018 : successful. */
6019 : static int
6020 0 : set_reload_reg (int i, int r)
6021 : {
6022 0 : int regno;
6023 0 : rtx reg = spill_reg_rtx[i];
6024 :
6025 0 : if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6026 0 : spill_reg_rtx[i] = reg
6027 0 : = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6028 :
6029 0 : regno = true_regnum (reg);
6030 :
6031 : /* Detect when the reload reg can't hold the reload mode.
6032 : This used to be one `if', but Sequent compiler can't handle that. */
6033 0 : if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6034 : {
6035 0 : machine_mode test_mode = VOIDmode;
6036 0 : if (rld[r].in)
6037 0 : test_mode = GET_MODE (rld[r].in);
6038 : /* If rld[r].in has VOIDmode, it means we will load it
6039 : in whatever mode the reload reg has: to wit, rld[r].mode.
6040 : We have already tested that for validity. */
6041 : /* Aside from that, we need to test that the expressions
6042 : to reload from or into have modes which are valid for this
6043 : reload register. Otherwise the reload insns would be invalid. */
6044 0 : if (! (rld[r].in != 0 && test_mode != VOIDmode
6045 0 : && !targetm.hard_regno_mode_ok (regno, test_mode)))
6046 0 : if (! (rld[r].out != 0
6047 0 : && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6048 : {
6049 : /* The reg is OK. */
6050 0 : last_spill_reg = i;
6051 :
6052 : /* Mark as in use for this insn the reload regs we use
6053 : for this. */
6054 0 : mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6055 : rld[r].when_needed, rld[r].mode);
6056 :
6057 0 : rld[r].reg_rtx = reg;
6058 0 : reload_spill_index[r] = spill_regs[i];
6059 0 : return 1;
6060 : }
6061 : }
6062 : return 0;
6063 : }
6064 :
6065 : /* Find a spill register to use as a reload register for reload R.
6066 : LAST_RELOAD is nonzero if this is the last reload for the insn being
6067 : processed.
6068 :
6069 : Set rld[R].reg_rtx to the register allocated.
6070 :
6071 : We return 1 if successful, or 0 if we couldn't find a spill reg and
6072 : we didn't change anything. */
6073 :
6074 : static int
6075 0 : allocate_reload_reg (class insn_chain *chain ATTRIBUTE_UNUSED, int r,
6076 : int last_reload)
6077 : {
6078 0 : int i, pass, count;
6079 :
6080 : /* If we put this reload ahead, thinking it is a group,
6081 : then insist on finding a group. Otherwise we can grab a
6082 : reg that some other reload needs.
6083 : (That can happen when we have a 68000 DATA_OR_FP_REG
6084 : which is a group of data regs or one fp reg.)
6085 : We need not be so restrictive if there are no more reloads
6086 : for this insn.
6087 :
6088 : ??? Really it would be nicer to have smarter handling
6089 : for that kind of reg class, where a problem like this is normal.
6090 : Perhaps those classes should be avoided for reloading
6091 : by use of more alternatives. */
6092 :
6093 0 : int force_group = rld[r].nregs > 1 && ! last_reload;
6094 :
6095 : /* If we want a single register and haven't yet found one,
6096 : take any reg in the right class and not in use.
6097 : If we want a consecutive group, here is where we look for it.
6098 :
6099 : We use three passes so we can first look for reload regs to
6100 : reuse, which are already in use for other reloads in this insn,
6101 : and only then use additional registers which are not "bad", then
6102 : finally any register.
6103 :
6104 : I think that maximizing reuse is needed to make sure we don't
6105 : run out of reload regs. Suppose we have three reloads, and
6106 : reloads A and B can share regs. These need two regs.
6107 : Suppose A and B are given different regs.
6108 : That leaves none for C. */
6109 0 : for (pass = 0; pass < 3; pass++)
6110 : {
6111 : /* I is the index in spill_regs.
6112 : We advance it round-robin between insns to use all spill regs
6113 : equally, so that inherited reloads have a chance
6114 : of leapfrogging each other. */
6115 :
6116 0 : i = last_spill_reg;
6117 :
6118 0 : for (count = 0; count < n_spills; count++)
6119 : {
6120 0 : int rclass = (int) rld[r].rclass;
6121 0 : int regnum;
6122 :
6123 0 : i++;
6124 0 : if (i >= n_spills)
6125 0 : i -= n_spills;
6126 0 : regnum = spill_regs[i];
6127 :
6128 0 : if ((reload_reg_free_p (regnum, rld[r].opnum,
6129 : rld[r].when_needed)
6130 0 : || (rld[r].in
6131 : /* We check reload_reg_used to make sure we
6132 : don't clobber the return register. */
6133 0 : && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6134 0 : && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6135 : rld[r].when_needed, rld[r].in,
6136 : rld[r].out, r, 1)))
6137 0 : && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6138 0 : && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6139 : /* Look first for regs to share, then for unshared. But
6140 : don't share regs used for inherited reloads; they are
6141 : the ones we want to preserve. */
6142 0 : && (pass
6143 0 : || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6144 : regnum)
6145 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6146 : regnum))))
6147 : {
6148 0 : int nr = hard_regno_nregs (regnum, rld[r].mode);
6149 :
6150 : /* During the second pass we want to avoid reload registers
6151 : which are "bad" for this reload. */
6152 0 : if (pass == 1
6153 0 : && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6154 0 : continue;
6155 :
6156 : /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6157 : (on 68000) got us two FP regs. If NR is 1,
6158 : we would reject both of them. */
6159 0 : if (force_group)
6160 0 : nr = rld[r].nregs;
6161 : /* If we need only one reg, we have already won. */
6162 0 : if (nr == 1)
6163 : {
6164 : /* But reject a single reg if we demand a group. */
6165 0 : if (force_group)
6166 0 : continue;
6167 : break;
6168 : }
6169 : /* Otherwise check that as many consecutive regs as we need
6170 : are available here. */
6171 0 : while (nr > 1)
6172 : {
6173 0 : int regno = regnum + nr - 1;
6174 0 : if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6175 0 : && spill_reg_order[regno] >= 0
6176 0 : && reload_reg_free_p (regno, rld[r].opnum,
6177 : rld[r].when_needed)))
6178 : break;
6179 0 : nr--;
6180 : }
6181 0 : if (nr == 1)
6182 : break;
6183 : }
6184 : }
6185 :
6186 : /* If we found something on the current pass, omit later passes. */
6187 0 : if (count < n_spills)
6188 : break;
6189 : }
6190 :
6191 : /* We should have found a spill register by now. */
6192 0 : if (count >= n_spills)
6193 : return 0;
6194 :
6195 : /* I is the index in SPILL_REG_RTX of the reload register we are to
6196 : allocate. Get an rtx for it and find its register number. */
6197 :
6198 0 : return set_reload_reg (i, r);
6199 : }
6200 :
6201 : /* Initialize all the tables needed to allocate reload registers.
6202 : CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6203 : is the array we use to restore the reg_rtx field for every reload. */
6204 :
6205 : static void
6206 0 : choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
6207 : {
6208 0 : int i;
6209 :
6210 0 : for (i = 0; i < n_reloads; i++)
6211 0 : rld[i].reg_rtx = save_reload_reg_rtx[i];
6212 :
6213 0 : memset (reload_inherited, 0, MAX_RELOADS);
6214 0 : memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6215 0 : memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6216 :
6217 0 : CLEAR_HARD_REG_SET (reload_reg_used);
6218 0 : CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6219 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6220 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6221 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6222 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6223 :
6224 0 : CLEAR_HARD_REG_SET (reg_used_in_insn);
6225 : {
6226 : HARD_REG_SET tmp;
6227 0 : REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6228 0 : reg_used_in_insn |= tmp;
6229 0 : REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6230 0 : reg_used_in_insn |= tmp;
6231 0 : compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6232 0 : compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6233 : }
6234 :
6235 0 : for (i = 0; i < reload_n_operands; i++)
6236 : {
6237 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6238 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6239 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6240 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6241 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6242 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6243 : }
6244 :
6245 0 : reload_reg_unavailable = ~chain->used_spill_regs;
6246 :
6247 0 : CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6248 :
6249 0 : for (i = 0; i < n_reloads; i++)
6250 : /* If we have already decided to use a certain register,
6251 : don't use it in another way. */
6252 0 : if (rld[i].reg_rtx)
6253 0 : mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6254 : rld[i].when_needed, rld[i].mode);
6255 0 : }
6256 :
6257 : /* If X is not a subreg, return it unmodified. If it is a subreg,
6258 : look up whether we made a replacement for the SUBREG_REG. Return
6259 : either the replacement or the SUBREG_REG. */
6260 :
6261 : static rtx
6262 0 : replaced_subreg (rtx x)
6263 : {
6264 0 : if (GET_CODE (x) == SUBREG)
6265 0 : return find_replacement (&SUBREG_REG (x));
6266 : return x;
6267 : }
6268 :
6269 : /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6270 : mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6271 : SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6272 : otherwise it is NULL. */
6273 :
6274 : static poly_int64
6275 0 : compute_reload_subreg_offset (machine_mode outermode,
6276 : rtx subreg,
6277 : machine_mode innermode)
6278 : {
6279 0 : poly_int64 outer_offset;
6280 0 : machine_mode middlemode;
6281 :
6282 0 : if (!subreg)
6283 0 : return subreg_lowpart_offset (outermode, innermode);
6284 :
6285 0 : outer_offset = SUBREG_BYTE (subreg);
6286 0 : middlemode = GET_MODE (SUBREG_REG (subreg));
6287 :
6288 : /* If SUBREG is paradoxical then return the normal lowpart offset
6289 : for OUTERMODE and INNERMODE. Our caller has already checked
6290 : that OUTERMODE fits in INNERMODE. */
6291 0 : if (paradoxical_subreg_p (outermode, middlemode))
6292 0 : return subreg_lowpart_offset (outermode, innermode);
6293 :
6294 : /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6295 : plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6296 0 : return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6297 : }
6298 :
6299 : /* Assign hard reg targets for the pseudo-registers we must reload
6300 : into hard regs for this insn.
6301 : Also output the instructions to copy them in and out of the hard regs.
6302 :
6303 : For machines with register classes, we are responsible for
6304 : finding a reload reg in the proper class. */
6305 :
6306 : static void
6307 0 : choose_reload_regs (class insn_chain *chain)
6308 : {
6309 0 : rtx_insn *insn = chain->insn;
6310 0 : int i, j;
6311 0 : unsigned int max_group_size = 1;
6312 0 : enum reg_class group_class = NO_REGS;
6313 0 : int pass, win, inheritance;
6314 :
6315 0 : rtx save_reload_reg_rtx[MAX_RELOADS];
6316 :
6317 : /* In order to be certain of getting the registers we need,
6318 : we must sort the reloads into order of increasing register class.
6319 : Then our grabbing of reload registers will parallel the process
6320 : that provided the reload registers.
6321 :
6322 : Also note whether any of the reloads wants a consecutive group of regs.
6323 : If so, record the maximum size of the group desired and what
6324 : register class contains all the groups needed by this insn. */
6325 :
6326 0 : for (j = 0; j < n_reloads; j++)
6327 : {
6328 0 : reload_order[j] = j;
6329 0 : if (rld[j].reg_rtx != NULL_RTX)
6330 : {
6331 0 : gcc_assert (REG_P (rld[j].reg_rtx)
6332 : && HARD_REGISTER_P (rld[j].reg_rtx));
6333 0 : reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6334 : }
6335 : else
6336 0 : reload_spill_index[j] = -1;
6337 :
6338 0 : if (rld[j].nregs > 1)
6339 : {
6340 0 : max_group_size = MAX (rld[j].nregs, max_group_size);
6341 0 : group_class
6342 0 : = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6343 : }
6344 :
6345 0 : save_reload_reg_rtx[j] = rld[j].reg_rtx;
6346 : }
6347 :
6348 0 : if (n_reloads > 1)
6349 0 : qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6350 :
6351 : /* If -O, try first with inheritance, then turning it off.
6352 : If not -O, don't do inheritance.
6353 : Using inheritance when not optimizing leads to paradoxes
6354 : with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6355 : because one side of the comparison might be inherited. */
6356 0 : win = 0;
6357 0 : for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6358 : {
6359 0 : choose_reload_regs_init (chain, save_reload_reg_rtx);
6360 :
6361 : /* Process the reloads in order of preference just found.
6362 : Beyond this point, subregs can be found in reload_reg_rtx.
6363 :
6364 : This used to look for an existing reloaded home for all of the
6365 : reloads, and only then perform any new reloads. But that could lose
6366 : if the reloads were done out of reg-class order because a later
6367 : reload with a looser constraint might have an old home in a register
6368 : needed by an earlier reload with a tighter constraint.
6369 :
6370 : To solve this, we make two passes over the reloads, in the order
6371 : described above. In the first pass we try to inherit a reload
6372 : from a previous insn. If there is a later reload that needs a
6373 : class that is a proper subset of the class being processed, we must
6374 : also allocate a spill register during the first pass.
6375 :
6376 : Then make a second pass over the reloads to allocate any reloads
6377 : that haven't been given registers yet. */
6378 :
6379 0 : for (j = 0; j < n_reloads; j++)
6380 : {
6381 0 : int r = reload_order[j];
6382 0 : rtx search_equiv = NULL_RTX;
6383 :
6384 : /* Ignore reloads that got marked inoperative. */
6385 0 : if (rld[r].out == 0 && rld[r].in == 0
6386 0 : && ! rld[r].secondary_p)
6387 0 : continue;
6388 :
6389 : /* If find_reloads chose to use reload_in or reload_out as a reload
6390 : register, we don't need to chose one. Otherwise, try even if it
6391 : found one since we might save an insn if we find the value lying
6392 : around.
6393 : Try also when reload_in is a pseudo without a hard reg. */
6394 0 : if (rld[r].in != 0 && rld[r].reg_rtx != 0
6395 0 : && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6396 0 : || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6397 0 : && !MEM_P (rld[r].in)
6398 0 : && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6399 0 : continue;
6400 :
6401 : #if 0 /* No longer needed for correct operation.
6402 : It might give better code, or might not; worth an experiment? */
6403 : /* If this is an optional reload, we can't inherit from earlier insns
6404 : until we are sure that any non-optional reloads have been allocated.
6405 : The following code takes advantage of the fact that optional reloads
6406 : are at the end of reload_order. */
6407 : if (rld[r].optional != 0)
6408 : for (i = 0; i < j; i++)
6409 : if ((rld[reload_order[i]].out != 0
6410 : || rld[reload_order[i]].in != 0
6411 : || rld[reload_order[i]].secondary_p)
6412 : && ! rld[reload_order[i]].optional
6413 : && rld[reload_order[i]].reg_rtx == 0)
6414 : allocate_reload_reg (chain, reload_order[i], 0);
6415 : #endif
6416 :
6417 : /* First see if this pseudo is already available as reloaded
6418 : for a previous insn. We cannot try to inherit for reloads
6419 : that are smaller than the maximum number of registers needed
6420 : for groups unless the register we would allocate cannot be used
6421 : for the groups.
6422 :
6423 : We could check here to see if this is a secondary reload for
6424 : an object that is already in a register of the desired class.
6425 : This would avoid the need for the secondary reload register.
6426 : But this is complex because we can't easily determine what
6427 : objects might want to be loaded via this reload. So let a
6428 : register be allocated here. In `emit_reload_insns' we suppress
6429 : one of the loads in the case described above. */
6430 :
6431 0 : if (inheritance)
6432 : {
6433 0 : poly_int64 byte = 0;
6434 0 : int regno = -1;
6435 0 : machine_mode mode = VOIDmode;
6436 0 : rtx subreg = NULL_RTX;
6437 :
6438 0 : if (rld[r].in == 0)
6439 : ;
6440 0 : else if (REG_P (rld[r].in))
6441 : {
6442 0 : regno = REGNO (rld[r].in);
6443 0 : mode = GET_MODE (rld[r].in);
6444 : }
6445 0 : else if (REG_P (rld[r].in_reg))
6446 : {
6447 0 : regno = REGNO (rld[r].in_reg);
6448 0 : mode = GET_MODE (rld[r].in_reg);
6449 : }
6450 0 : else if (GET_CODE (rld[r].in_reg) == SUBREG
6451 0 : && REG_P (SUBREG_REG (rld[r].in_reg)))
6452 : {
6453 0 : regno = REGNO (SUBREG_REG (rld[r].in_reg));
6454 0 : if (regno < FIRST_PSEUDO_REGISTER)
6455 0 : regno = subreg_regno (rld[r].in_reg);
6456 : else
6457 : {
6458 0 : subreg = rld[r].in_reg;
6459 0 : byte = SUBREG_BYTE (subreg);
6460 : }
6461 0 : mode = GET_MODE (rld[r].in_reg);
6462 : }
6463 : #if AUTO_INC_DEC
6464 : else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6465 : && REG_P (XEXP (rld[r].in_reg, 0)))
6466 : {
6467 : regno = REGNO (XEXP (rld[r].in_reg, 0));
6468 : mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6469 : rld[r].out = rld[r].in;
6470 : }
6471 : #endif
6472 : #if 0
6473 : /* This won't work, since REGNO can be a pseudo reg number.
6474 : Also, it takes much more hair to keep track of all the things
6475 : that can invalidate an inherited reload of part of a pseudoreg. */
6476 : else if (GET_CODE (rld[r].in) == SUBREG
6477 : && REG_P (SUBREG_REG (rld[r].in)))
6478 : regno = subreg_regno (rld[r].in);
6479 : #endif
6480 :
6481 0 : if (regno >= 0
6482 0 : && reg_last_reload_reg[regno] != 0
6483 0 : && (known_ge
6484 : (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6485 : GET_MODE_SIZE (mode) + byte))
6486 : /* Verify that the register it's in can be used in
6487 : mode MODE. */
6488 0 : && (REG_CAN_CHANGE_MODE_P
6489 : (REGNO (reg_last_reload_reg[regno]),
6490 : GET_MODE (reg_last_reload_reg[regno]),
6491 : mode)))
6492 : {
6493 0 : enum reg_class rclass = rld[r].rclass, last_class;
6494 0 : rtx last_reg = reg_last_reload_reg[regno];
6495 :
6496 0 : i = REGNO (last_reg);
6497 0 : byte = compute_reload_subreg_offset (mode,
6498 : subreg,
6499 0 : GET_MODE (last_reg));
6500 0 : i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6501 0 : last_class = REGNO_REG_CLASS (i);
6502 :
6503 0 : if (reg_reloaded_contents[i] == regno
6504 0 : && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6505 0 : && targetm.hard_regno_mode_ok (i, rld[r].mode)
6506 0 : && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6507 : /* Even if we can't use this register as a reload
6508 : register, we might use it for reload_override_in,
6509 : if copying it to the desired class is cheap
6510 : enough. */
6511 0 : || ((register_move_cost (mode, last_class, rclass)
6512 0 : < memory_move_cost (mode, rclass, true))
6513 0 : && (secondary_reload_class (1, rclass, mode,
6514 : last_reg)
6515 : == NO_REGS)
6516 0 : && !(targetm.secondary_memory_needed
6517 0 : (mode, last_class, rclass))))
6518 0 : && (rld[r].nregs == max_group_size
6519 0 : || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6520 : i))
6521 0 : && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6522 : rld[r].when_needed, rld[r].in,
6523 : const0_rtx, r, 1))
6524 : {
6525 : /* If a group is needed, verify that all the subsequent
6526 : registers still have their values intact. */
6527 0 : int nr = hard_regno_nregs (i, rld[r].mode);
6528 0 : int k;
6529 :
6530 0 : for (k = 1; k < nr; k++)
6531 0 : if (reg_reloaded_contents[i + k] != regno
6532 0 : || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6533 : break;
6534 :
6535 0 : if (k == nr)
6536 : {
6537 0 : int i1;
6538 0 : int bad_for_class;
6539 :
6540 0 : last_reg = (GET_MODE (last_reg) == mode
6541 0 : ? last_reg : gen_rtx_REG (mode, i));
6542 :
6543 0 : bad_for_class = 0;
6544 0 : for (k = 0; k < nr; k++)
6545 0 : bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6546 0 : i+k);
6547 :
6548 : /* We found a register that contains the
6549 : value we need. If this register is the
6550 : same as an `earlyclobber' operand of the
6551 : current insn, just mark it as a place to
6552 : reload from since we can't use it as the
6553 : reload register itself. */
6554 :
6555 0 : for (i1 = 0; i1 < n_earlyclobbers; i1++)
6556 0 : if (reg_overlap_mentioned_for_reload_p
6557 0 : (reg_last_reload_reg[regno],
6558 : reload_earlyclobbers[i1]))
6559 : break;
6560 :
6561 0 : if (i1 != n_earlyclobbers
6562 0 : || ! (free_for_value_p (i, rld[r].mode,
6563 : rld[r].opnum,
6564 : rld[r].when_needed, rld[r].in,
6565 : rld[r].out, r, 1))
6566 : /* Don't use it if we'd clobber a pseudo reg. */
6567 0 : || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6568 0 : && rld[r].out
6569 0 : && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6570 : /* Don't clobber the frame pointer. */
6571 0 : || (i == HARD_FRAME_POINTER_REGNUM
6572 0 : && frame_pointer_needed
6573 0 : && rld[r].out)
6574 : /* Don't really use the inherited spill reg
6575 : if we need it wider than we've got it. */
6576 0 : || paradoxical_subreg_p (rld[r].mode, mode)
6577 0 : || bad_for_class
6578 :
6579 : /* If find_reloads chose reload_out as reload
6580 : register, stay with it - that leaves the
6581 : inherited register for subsequent reloads. */
6582 0 : || (rld[r].out && rld[r].reg_rtx
6583 0 : && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6584 : {
6585 0 : if (! rld[r].optional)
6586 : {
6587 0 : reload_override_in[r] = last_reg;
6588 0 : reload_inheritance_insn[r]
6589 0 : = reg_reloaded_insn[i];
6590 : }
6591 : }
6592 : else
6593 : {
6594 0 : int k;
6595 : /* We can use this as a reload reg. */
6596 : /* Mark the register as in use for this part of
6597 : the insn. */
6598 0 : mark_reload_reg_in_use (i,
6599 : rld[r].opnum,
6600 : rld[r].when_needed,
6601 : rld[r].mode);
6602 0 : rld[r].reg_rtx = last_reg;
6603 0 : reload_inherited[r] = 1;
6604 0 : reload_inheritance_insn[r]
6605 0 : = reg_reloaded_insn[i];
6606 0 : reload_spill_index[r] = i;
6607 0 : for (k = 0; k < nr; k++)
6608 0 : SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6609 0 : i + k);
6610 : }
6611 : }
6612 : }
6613 : }
6614 : }
6615 :
6616 : /* Here's another way to see if the value is already lying around. */
6617 0 : if (inheritance
6618 0 : && rld[r].in != 0
6619 0 : && ! reload_inherited[r]
6620 0 : && rld[r].out == 0
6621 0 : && (CONSTANT_P (rld[r].in)
6622 : || GET_CODE (rld[r].in) == PLUS
6623 : || REG_P (rld[r].in)
6624 : || MEM_P (rld[r].in))
6625 0 : && (rld[r].nregs == max_group_size
6626 0 : || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6627 0 : search_equiv = rld[r].in;
6628 :
6629 0 : if (search_equiv)
6630 : {
6631 0 : rtx equiv
6632 0 : = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6633 : -1, NULL, 0, rld[r].mode);
6634 0 : int regno = 0;
6635 :
6636 0 : if (equiv != 0)
6637 : {
6638 0 : if (REG_P (equiv))
6639 0 : regno = REGNO (equiv);
6640 : else
6641 : {
6642 : /* This must be a SUBREG of a hard register.
6643 : Make a new REG since this might be used in an
6644 : address and not all machines support SUBREGs
6645 : there. */
6646 0 : gcc_assert (GET_CODE (equiv) == SUBREG);
6647 0 : regno = subreg_regno (equiv);
6648 0 : equiv = gen_rtx_REG (rld[r].mode, regno);
6649 : /* If we choose EQUIV as the reload register, but the
6650 : loop below decides to cancel the inheritance, we'll
6651 : end up reloading EQUIV in rld[r].mode, not the mode
6652 : it had originally. That isn't safe when EQUIV isn't
6653 : available as a spill register since its value might
6654 : still be live at this point. */
6655 0 : for (i = regno; i < regno + (int) rld[r].nregs; i++)
6656 0 : if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6657 0 : equiv = 0;
6658 : }
6659 : }
6660 :
6661 : /* If we found a spill reg, reject it unless it is free
6662 : and of the desired class. */
6663 0 : if (equiv != 0)
6664 : {
6665 0 : int regs_used = 0;
6666 0 : int bad_for_class = 0;
6667 0 : int max_regno = regno + rld[r].nregs;
6668 :
6669 0 : for (i = regno; i < max_regno; i++)
6670 : {
6671 0 : regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6672 : i);
6673 0 : bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6674 : i);
6675 : }
6676 :
6677 0 : if ((regs_used
6678 0 : && ! free_for_value_p (regno, rld[r].mode,
6679 : rld[r].opnum, rld[r].when_needed,
6680 : rld[r].in, rld[r].out, r, 1))
6681 0 : || bad_for_class)
6682 : equiv = 0;
6683 : }
6684 :
6685 0 : if (equiv != 0
6686 0 : && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6687 : equiv = 0;
6688 :
6689 : /* We found a register that contains the value we need.
6690 : If this register is the same as an `earlyclobber' operand
6691 : of the current insn, just mark it as a place to reload from
6692 : since we can't use it as the reload register itself. */
6693 :
6694 0 : if (equiv != 0)
6695 0 : for (i = 0; i < n_earlyclobbers; i++)
6696 0 : if (reg_overlap_mentioned_for_reload_p (equiv,
6697 : reload_earlyclobbers[i]))
6698 : {
6699 0 : if (! rld[r].optional)
6700 0 : reload_override_in[r] = equiv;
6701 : equiv = 0;
6702 : break;
6703 : }
6704 :
6705 : /* If the equiv register we have found is explicitly clobbered
6706 : in the current insn, it depends on the reload type if we
6707 : can use it, use it for reload_override_in, or not at all.
6708 : In particular, we then can't use EQUIV for a
6709 : RELOAD_FOR_OUTPUT_ADDRESS reload. */
6710 :
6711 0 : if (equiv != 0)
6712 : {
6713 0 : if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6714 0 : switch (rld[r].when_needed)
6715 : {
6716 : case RELOAD_FOR_OTHER_ADDRESS:
6717 : case RELOAD_FOR_INPADDR_ADDRESS:
6718 : case RELOAD_FOR_INPUT_ADDRESS:
6719 : case RELOAD_FOR_OPADDR_ADDR:
6720 : break;
6721 0 : case RELOAD_OTHER:
6722 0 : case RELOAD_FOR_INPUT:
6723 0 : case RELOAD_FOR_OPERAND_ADDRESS:
6724 0 : if (! rld[r].optional)
6725 0 : reload_override_in[r] = equiv;
6726 : /* Fall through. */
6727 : default:
6728 : equiv = 0;
6729 : break;
6730 : }
6731 0 : else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6732 0 : switch (rld[r].when_needed)
6733 : {
6734 : case RELOAD_FOR_OTHER_ADDRESS:
6735 : case RELOAD_FOR_INPADDR_ADDRESS:
6736 : case RELOAD_FOR_INPUT_ADDRESS:
6737 : case RELOAD_FOR_OPADDR_ADDR:
6738 : case RELOAD_FOR_OPERAND_ADDRESS:
6739 : case RELOAD_FOR_INPUT:
6740 : break;
6741 0 : case RELOAD_OTHER:
6742 0 : if (! rld[r].optional)
6743 0 : reload_override_in[r] = equiv;
6744 : /* Fall through. */
6745 : default:
6746 : equiv = 0;
6747 : break;
6748 : }
6749 : }
6750 :
6751 : /* If we found an equivalent reg, say no code need be generated
6752 : to load it, and use it as our reload reg. */
6753 0 : if (equiv != 0
6754 0 : && (regno != HARD_FRAME_POINTER_REGNUM
6755 0 : || !frame_pointer_needed))
6756 : {
6757 0 : int nr = hard_regno_nregs (regno, rld[r].mode);
6758 0 : int k;
6759 0 : rld[r].reg_rtx = equiv;
6760 0 : reload_spill_index[r] = regno;
6761 0 : reload_inherited[r] = 1;
6762 :
6763 : /* If reg_reloaded_valid is not set for this register,
6764 : there might be a stale spill_reg_store lying around.
6765 : We must clear it, since otherwise emit_reload_insns
6766 : might delete the store. */
6767 0 : if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6768 0 : spill_reg_store[regno] = NULL;
6769 : /* If any of the hard registers in EQUIV are spill
6770 : registers, mark them as in use for this insn. */
6771 0 : for (k = 0; k < nr; k++)
6772 : {
6773 0 : i = spill_reg_order[regno + k];
6774 0 : if (i >= 0)
6775 : {
6776 0 : mark_reload_reg_in_use (regno, rld[r].opnum,
6777 : rld[r].when_needed,
6778 : rld[r].mode);
6779 0 : SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6780 : regno + k);
6781 : }
6782 : }
6783 : }
6784 : }
6785 :
6786 : /* If we found a register to use already, or if this is an optional
6787 : reload, we are done. */
6788 0 : if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6789 0 : continue;
6790 :
6791 : #if 0
6792 : /* No longer needed for correct operation. Might or might
6793 : not give better code on the average. Want to experiment? */
6794 :
6795 : /* See if there is a later reload that has a class different from our
6796 : class that intersects our class or that requires less register
6797 : than our reload. If so, we must allocate a register to this
6798 : reload now, since that reload might inherit a previous reload
6799 : and take the only available register in our class. Don't do this
6800 : for optional reloads since they will force all previous reloads
6801 : to be allocated. Also don't do this for reloads that have been
6802 : turned off. */
6803 :
6804 : for (i = j + 1; i < n_reloads; i++)
6805 : {
6806 : int s = reload_order[i];
6807 :
6808 : if ((rld[s].in == 0 && rld[s].out == 0
6809 : && ! rld[s].secondary_p)
6810 : || rld[s].optional)
6811 : continue;
6812 :
6813 : if ((rld[s].rclass != rld[r].rclass
6814 : && reg_classes_intersect_p (rld[r].rclass,
6815 : rld[s].rclass))
6816 : || rld[s].nregs < rld[r].nregs)
6817 : break;
6818 : }
6819 :
6820 : if (i == n_reloads)
6821 : continue;
6822 :
6823 : allocate_reload_reg (chain, r, j == n_reloads - 1);
6824 : #endif
6825 : }
6826 :
6827 : /* Now allocate reload registers for anything non-optional that
6828 : didn't get one yet. */
6829 0 : for (j = 0; j < n_reloads; j++)
6830 : {
6831 0 : int r = reload_order[j];
6832 :
6833 : /* Ignore reloads that got marked inoperative. */
6834 0 : if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6835 0 : continue;
6836 :
6837 : /* Skip reloads that already have a register allocated or are
6838 : optional. */
6839 0 : if (rld[r].reg_rtx != 0 || rld[r].optional)
6840 0 : continue;
6841 :
6842 0 : if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6843 : break;
6844 : }
6845 :
6846 : /* If that loop got all the way, we have won. */
6847 0 : if (j == n_reloads)
6848 : {
6849 : win = 1;
6850 : break;
6851 : }
6852 :
6853 : /* Loop around and try without any inheritance. */
6854 : }
6855 :
6856 0 : if (! win)
6857 : {
6858 : /* First undo everything done by the failed attempt
6859 : to allocate with inheritance. */
6860 0 : choose_reload_regs_init (chain, save_reload_reg_rtx);
6861 :
6862 : /* Some sanity tests to verify that the reloads found in the first
6863 : pass are identical to the ones we have now. */
6864 0 : gcc_assert (chain->n_reloads == n_reloads);
6865 :
6866 0 : for (i = 0; i < n_reloads; i++)
6867 : {
6868 0 : if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6869 0 : continue;
6870 0 : gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6871 0 : for (j = 0; j < n_spills; j++)
6872 0 : if (spill_regs[j] == chain->rld[i].regno)
6873 0 : if (! set_reload_reg (j, i))
6874 0 : failed_reload (chain->insn, i);
6875 : }
6876 : }
6877 :
6878 : /* If we thought we could inherit a reload, because it seemed that
6879 : nothing else wanted the same reload register earlier in the insn,
6880 : verify that assumption, now that all reloads have been assigned.
6881 : Likewise for reloads where reload_override_in has been set. */
6882 :
6883 : /* If doing expensive optimizations, do one preliminary pass that doesn't
6884 : cancel any inheritance, but removes reloads that have been needed only
6885 : for reloads that we know can be inherited. */
6886 0 : for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6887 : {
6888 0 : for (j = 0; j < n_reloads; j++)
6889 : {
6890 0 : int r = reload_order[j];
6891 0 : rtx check_reg;
6892 0 : rtx tem;
6893 0 : if (reload_inherited[r] && rld[r].reg_rtx)
6894 : check_reg = rld[r].reg_rtx;
6895 0 : else if (reload_override_in[r]
6896 0 : && (REG_P (reload_override_in[r])
6897 0 : || GET_CODE (reload_override_in[r]) == SUBREG))
6898 : check_reg = reload_override_in[r];
6899 : else
6900 0 : continue;
6901 0 : if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6902 : rld[r].opnum, rld[r].when_needed, rld[r].in,
6903 : (reload_inherited[r]
6904 : ? rld[r].out : const0_rtx),
6905 : r, 1))
6906 : {
6907 0 : if (pass)
6908 0 : continue;
6909 0 : reload_inherited[r] = 0;
6910 0 : reload_override_in[r] = 0;
6911 : }
6912 : /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6913 : reload_override_in, then we do not need its related
6914 : RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6915 : likewise for other reload types.
6916 : We handle this by removing a reload when its only replacement
6917 : is mentioned in reload_in of the reload we are going to inherit.
6918 : A special case are auto_inc expressions; even if the input is
6919 : inherited, we still need the address for the output. We can
6920 : recognize them because they have RELOAD_OUT set to RELOAD_IN.
6921 : If we succeeded removing some reload and we are doing a preliminary
6922 : pass just to remove such reloads, make another pass, since the
6923 : removal of one reload might allow us to inherit another one. */
6924 0 : else if (rld[r].in
6925 0 : && rld[r].out != rld[r].in
6926 0 : && remove_address_replacements (rld[r].in))
6927 : {
6928 0 : if (pass)
6929 0 : pass = 2;
6930 : }
6931 : /* If we needed a memory location for the reload, we also have to
6932 : remove its related reloads. */
6933 0 : else if (rld[r].in
6934 0 : && rld[r].out != rld[r].in
6935 0 : && (tem = replaced_subreg (rld[r].in), REG_P (tem))
6936 0 : && REGNO (tem) < FIRST_PSEUDO_REGISTER
6937 0 : && (targetm.secondary_memory_needed
6938 0 : (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
6939 0 : rld[r].rclass))
6940 0 : && remove_address_replacements
6941 0 : (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
6942 : rld[r].when_needed)))
6943 : {
6944 0 : if (pass)
6945 0 : pass = 2;
6946 : }
6947 : }
6948 : }
6949 :
6950 : /* Now that reload_override_in is known valid,
6951 : actually override reload_in. */
6952 0 : for (j = 0; j < n_reloads; j++)
6953 0 : if (reload_override_in[j])
6954 0 : rld[j].in = reload_override_in[j];
6955 :
6956 : /* If this reload won't be done because it has been canceled or is
6957 : optional and not inherited, clear reload_reg_rtx so other
6958 : routines (such as subst_reloads) don't get confused. */
6959 0 : for (j = 0; j < n_reloads; j++)
6960 0 : if (rld[j].reg_rtx != 0
6961 0 : && ((rld[j].optional && ! reload_inherited[j])
6962 0 : || (rld[j].in == 0 && rld[j].out == 0
6963 0 : && ! rld[j].secondary_p)))
6964 : {
6965 0 : int regno = true_regnum (rld[j].reg_rtx);
6966 :
6967 0 : if (spill_reg_order[regno] >= 0)
6968 0 : clear_reload_reg_in_use (regno, rld[j].opnum,
6969 : rld[j].when_needed, rld[j].mode);
6970 0 : rld[j].reg_rtx = 0;
6971 0 : reload_spill_index[j] = -1;
6972 : }
6973 :
6974 : /* Record which pseudos and which spill regs have output reloads. */
6975 0 : for (j = 0; j < n_reloads; j++)
6976 : {
6977 0 : int r = reload_order[j];
6978 :
6979 0 : i = reload_spill_index[r];
6980 :
6981 : /* I is nonneg if this reload uses a register.
6982 : If rld[r].reg_rtx is 0, this is an optional reload
6983 : that we opted to ignore. */
6984 0 : if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6985 0 : && rld[r].reg_rtx != 0)
6986 : {
6987 0 : int nregno = REGNO (rld[r].out_reg);
6988 0 : int nr = 1;
6989 :
6990 0 : if (nregno < FIRST_PSEUDO_REGISTER)
6991 0 : nr = hard_regno_nregs (nregno, rld[r].mode);
6992 :
6993 0 : while (--nr >= 0)
6994 0 : SET_REGNO_REG_SET (®_has_output_reload,
6995 : nregno + nr);
6996 :
6997 0 : if (i >= 0)
6998 0 : add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
6999 :
7000 0 : gcc_assert (rld[r].when_needed == RELOAD_OTHER
7001 : || rld[r].when_needed == RELOAD_FOR_OUTPUT
7002 : || rld[r].when_needed == RELOAD_FOR_INSN);
7003 : }
7004 : }
7005 0 : }
7006 :
7007 : /* Deallocate the reload register for reload R. This is called from
7008 : remove_address_replacements. */
7009 :
7010 : void
7011 0 : deallocate_reload_reg (int r)
7012 : {
7013 0 : int regno;
7014 :
7015 0 : if (! rld[r].reg_rtx)
7016 : return;
7017 0 : regno = true_regnum (rld[r].reg_rtx);
7018 0 : rld[r].reg_rtx = 0;
7019 0 : if (spill_reg_order[regno] >= 0)
7020 0 : clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7021 : rld[r].mode);
7022 0 : reload_spill_index[r] = -1;
7023 : }
7024 :
7025 : /* These arrays are filled by emit_reload_insns and its subroutines. */
7026 : static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7027 : static rtx_insn *other_input_address_reload_insns = 0;
7028 : static rtx_insn *other_input_reload_insns = 0;
7029 : static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7030 : static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7031 : static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7032 : static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7033 : static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7034 : static rtx_insn *operand_reload_insns = 0;
7035 : static rtx_insn *other_operand_reload_insns = 0;
7036 : static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7037 :
7038 : /* Values to be put in spill_reg_store are put here first. Instructions
7039 : must only be placed here if the associated reload register reaches
7040 : the end of the instruction's reload sequence. */
7041 : static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7042 : static HARD_REG_SET reg_reloaded_died;
7043 :
7044 : /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7045 : of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7046 : is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7047 : adjusted register, and return true. Otherwise, return false. */
7048 : static bool
7049 0 : reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7050 : enum reg_class new_class,
7051 : machine_mode new_mode)
7052 :
7053 : {
7054 0 : rtx reg;
7055 :
7056 0 : for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7057 : {
7058 0 : unsigned regno = REGNO (reg);
7059 :
7060 0 : if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7061 0 : continue;
7062 0 : if (GET_MODE (reg) != new_mode)
7063 : {
7064 0 : if (!targetm.hard_regno_mode_ok (regno, new_mode))
7065 0 : continue;
7066 0 : if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7067 0 : continue;
7068 0 : reg = reload_adjust_reg_for_mode (reg, new_mode);
7069 : }
7070 0 : *reload_reg = reg;
7071 0 : return true;
7072 : }
7073 : return false;
7074 : }
7075 :
7076 : /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7077 : pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7078 : nonzero, if that is suitable. On success, change *RELOAD_REG to the
7079 : adjusted register, and return true. Otherwise, return false. */
7080 : static bool
7081 0 : reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7082 : enum insn_code icode)
7083 :
7084 : {
7085 0 : enum reg_class new_class = scratch_reload_class (icode);
7086 0 : machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7087 :
7088 0 : return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7089 0 : new_class, new_mode);
7090 : }
7091 :
7092 : /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7093 : has the number J. OLD contains the value to be used as input. */
7094 :
7095 : static void
7096 0 : emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
7097 : rtx old, int j)
7098 : {
7099 0 : rtx_insn *insn = chain->insn;
7100 0 : rtx reloadreg;
7101 0 : rtx oldequiv_reg = 0;
7102 0 : rtx oldequiv = 0;
7103 0 : int special = 0;
7104 0 : machine_mode mode;
7105 0 : rtx_insn **where;
7106 :
7107 : /* delete_output_reload is only invoked properly if old contains
7108 : the original pseudo register. Since this is replaced with a
7109 : hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7110 : find the pseudo in RELOAD_IN_REG. This is also used to
7111 : determine whether a secondary reload is needed. */
7112 0 : if (reload_override_in[j]
7113 0 : && (REG_P (rl->in_reg)
7114 0 : || (GET_CODE (rl->in_reg) == SUBREG
7115 0 : && REG_P (SUBREG_REG (rl->in_reg)))))
7116 : {
7117 0 : oldequiv = old;
7118 0 : old = rl->in_reg;
7119 : }
7120 0 : if (oldequiv == 0)
7121 : oldequiv = old;
7122 0 : else if (REG_P (oldequiv))
7123 : oldequiv_reg = oldequiv;
7124 0 : else if (GET_CODE (oldequiv) == SUBREG)
7125 0 : oldequiv_reg = SUBREG_REG (oldequiv);
7126 :
7127 0 : reloadreg = reload_reg_rtx_for_input[j];
7128 0 : mode = GET_MODE (reloadreg);
7129 :
7130 : /* If we are reloading from a register that was recently stored in
7131 : with an output-reload, see if we can prove there was
7132 : actually no need to store the old value in it. */
7133 :
7134 0 : if (optimize && REG_P (oldequiv)
7135 0 : && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7136 0 : && spill_reg_store[REGNO (oldequiv)]
7137 0 : && REG_P (old)
7138 0 : && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7139 0 : || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7140 0 : rl->out_reg)))
7141 0 : delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7142 :
7143 : /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7144 : OLDEQUIV. */
7145 :
7146 0 : while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7147 0 : oldequiv = SUBREG_REG (oldequiv);
7148 0 : if (GET_MODE (oldequiv) != VOIDmode
7149 0 : && mode != GET_MODE (oldequiv))
7150 0 : oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7151 :
7152 : /* Switch to the right place to emit the reload insns. */
7153 0 : switch (rl->when_needed)
7154 : {
7155 : case RELOAD_OTHER:
7156 0 : where = &other_input_reload_insns;
7157 : break;
7158 0 : case RELOAD_FOR_INPUT:
7159 0 : where = &input_reload_insns[rl->opnum];
7160 0 : break;
7161 0 : case RELOAD_FOR_INPUT_ADDRESS:
7162 0 : where = &input_address_reload_insns[rl->opnum];
7163 0 : break;
7164 0 : case RELOAD_FOR_INPADDR_ADDRESS:
7165 0 : where = &inpaddr_address_reload_insns[rl->opnum];
7166 0 : break;
7167 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
7168 0 : where = &output_address_reload_insns[rl->opnum];
7169 0 : break;
7170 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
7171 0 : where = &outaddr_address_reload_insns[rl->opnum];
7172 0 : break;
7173 0 : case RELOAD_FOR_OPERAND_ADDRESS:
7174 0 : where = &operand_reload_insns;
7175 0 : break;
7176 0 : case RELOAD_FOR_OPADDR_ADDR:
7177 0 : where = &other_operand_reload_insns;
7178 0 : break;
7179 0 : case RELOAD_FOR_OTHER_ADDRESS:
7180 0 : where = &other_input_address_reload_insns;
7181 0 : break;
7182 0 : default:
7183 0 : gcc_unreachable ();
7184 : }
7185 :
7186 0 : push_to_sequence (*where);
7187 :
7188 : /* Auto-increment addresses must be reloaded in a special way. */
7189 0 : if (rl->out && ! rl->out_reg)
7190 : {
7191 : /* We are not going to bother supporting the case where a
7192 : incremented register can't be copied directly from
7193 : OLDEQUIV since this seems highly unlikely. */
7194 0 : gcc_assert (rl->secondary_in_reload < 0);
7195 :
7196 0 : if (reload_inherited[j])
7197 0 : oldequiv = reloadreg;
7198 :
7199 0 : old = XEXP (rl->in_reg, 0);
7200 :
7201 : /* Prevent normal processing of this reload. */
7202 0 : special = 1;
7203 : /* Output a special code sequence for this case. */
7204 0 : inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7205 : }
7206 :
7207 : /* If we are reloading a pseudo-register that was set by the previous
7208 : insn, see if we can get rid of that pseudo-register entirely
7209 : by redirecting the previous insn into our reload register. */
7210 :
7211 0 : else if (optimize && REG_P (old)
7212 0 : && REGNO (old) >= FIRST_PSEUDO_REGISTER
7213 0 : && dead_or_set_p (insn, old)
7214 : /* This is unsafe if some other reload
7215 : uses the same reg first. */
7216 0 : && ! conflicts_with_override (reloadreg)
7217 0 : && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7218 : rl->when_needed, old, rl->out, j, 0))
7219 : {
7220 0 : rtx_insn *temp = PREV_INSN (insn);
7221 0 : while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7222 0 : temp = PREV_INSN (temp);
7223 0 : if (temp
7224 0 : && NONJUMP_INSN_P (temp)
7225 0 : && GET_CODE (PATTERN (temp)) == SET
7226 0 : && SET_DEST (PATTERN (temp)) == old
7227 : /* Make sure we can access insn_operand_constraint. */
7228 0 : && asm_noperands (PATTERN (temp)) < 0
7229 : /* This is unsafe if operand occurs more than once in current
7230 : insn. Perhaps some occurrences aren't reloaded. */
7231 0 : && count_occurrences (PATTERN (insn), old, 0) == 1)
7232 : {
7233 0 : rtx old = SET_DEST (PATTERN (temp));
7234 : /* Store into the reload register instead of the pseudo. */
7235 0 : SET_DEST (PATTERN (temp)) = reloadreg;
7236 :
7237 : /* Verify that resulting insn is valid.
7238 :
7239 : Note that we have replaced the destination of TEMP with
7240 : RELOADREG. If TEMP references RELOADREG within an
7241 : autoincrement addressing mode, then the resulting insn
7242 : is ill-formed and we must reject this optimization. */
7243 0 : extract_insn (temp);
7244 0 : if (constrain_operands (1, get_enabled_alternatives (temp))
7245 0 : && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7246 : {
7247 : /* If the previous insn is an output reload, the source is
7248 : a reload register, and its spill_reg_store entry will
7249 : contain the previous destination. This is now
7250 : invalid. */
7251 0 : if (REG_P (SET_SRC (PATTERN (temp)))
7252 0 : && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7253 : {
7254 0 : spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7255 0 : spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7256 : }
7257 :
7258 : /* If these are the only uses of the pseudo reg,
7259 : pretend for GDB it lives in the reload reg we used. */
7260 0 : if (REG_N_DEATHS (REGNO (old)) == 1
7261 0 : && REG_N_SETS (REGNO (old)) == 1)
7262 : {
7263 0 : reg_renumber[REGNO (old)] = REGNO (reloadreg);
7264 0 : if (ira_conflicts_p)
7265 : /* Inform IRA about the change. */
7266 0 : ira_mark_allocation_change (REGNO (old));
7267 0 : alter_reg (REGNO (old), -1, false);
7268 : }
7269 0 : special = 1;
7270 :
7271 : /* Adjust any debug insns between temp and insn. */
7272 0 : while ((temp = NEXT_INSN (temp)) != insn)
7273 0 : if (DEBUG_BIND_INSN_P (temp))
7274 0 : INSN_VAR_LOCATION_LOC (temp)
7275 0 : = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7276 : old, reloadreg);
7277 : else
7278 0 : gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7279 : }
7280 : else
7281 : {
7282 0 : SET_DEST (PATTERN (temp)) = old;
7283 : }
7284 : }
7285 : }
7286 :
7287 : /* We can't do that, so output an insn to load RELOADREG. */
7288 :
7289 : /* If we have a secondary reload, pick up the secondary register
7290 : and icode, if any. If OLDEQUIV and OLD are different or
7291 : if this is an in-out reload, recompute whether or not we
7292 : still need a secondary register and what the icode should
7293 : be. If we still need a secondary register and the class or
7294 : icode is different, go back to reloading from OLD if using
7295 : OLDEQUIV means that we got the wrong type of register. We
7296 : cannot have different class or icode due to an in-out reload
7297 : because we don't make such reloads when both the input and
7298 : output need secondary reload registers. */
7299 :
7300 0 : if (! special && rl->secondary_in_reload >= 0)
7301 : {
7302 0 : rtx second_reload_reg = 0;
7303 0 : rtx third_reload_reg = 0;
7304 0 : int secondary_reload = rl->secondary_in_reload;
7305 0 : rtx real_oldequiv = oldequiv;
7306 0 : rtx real_old = old;
7307 0 : rtx tmp;
7308 0 : enum insn_code icode;
7309 0 : enum insn_code tertiary_icode = CODE_FOR_nothing;
7310 :
7311 : /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7312 : and similarly for OLD.
7313 : See comments in get_secondary_reload in reload.cc. */
7314 : /* If it is a pseudo that cannot be replaced with its
7315 : equivalent MEM, we must fall back to reload_in, which
7316 : will have all the necessary substitutions registered.
7317 : Likewise for a pseudo that can't be replaced with its
7318 : equivalent constant.
7319 :
7320 : Take extra care for subregs of such pseudos. Note that
7321 : we cannot use reg_equiv_mem in this case because it is
7322 : not in the right mode. */
7323 :
7324 0 : tmp = oldequiv;
7325 0 : if (GET_CODE (tmp) == SUBREG)
7326 0 : tmp = SUBREG_REG (tmp);
7327 0 : if (REG_P (tmp)
7328 0 : && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7329 0 : && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7330 0 : || reg_equiv_constant (REGNO (tmp)) != 0))
7331 : {
7332 0 : if (! reg_equiv_mem (REGNO (tmp))
7333 0 : || num_not_at_initial_offset
7334 0 : || GET_CODE (oldequiv) == SUBREG)
7335 0 : real_oldequiv = rl->in;
7336 : else
7337 : real_oldequiv = reg_equiv_mem (REGNO (tmp));
7338 : }
7339 :
7340 0 : tmp = old;
7341 0 : if (GET_CODE (tmp) == SUBREG)
7342 0 : tmp = SUBREG_REG (tmp);
7343 0 : if (REG_P (tmp)
7344 0 : && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7345 0 : && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7346 0 : || reg_equiv_constant (REGNO (tmp)) != 0))
7347 : {
7348 0 : if (! reg_equiv_mem (REGNO (tmp))
7349 0 : || num_not_at_initial_offset
7350 0 : || GET_CODE (old) == SUBREG)
7351 0 : real_old = rl->in;
7352 : else
7353 : real_old = reg_equiv_mem (REGNO (tmp));
7354 : }
7355 :
7356 0 : second_reload_reg = rld[secondary_reload].reg_rtx;
7357 0 : if (rld[secondary_reload].secondary_in_reload >= 0)
7358 : {
7359 0 : int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7360 :
7361 0 : third_reload_reg = rld[tertiary_reload].reg_rtx;
7362 0 : tertiary_icode = rld[secondary_reload].secondary_in_icode;
7363 : /* We'd have to add more code for quartary reloads. */
7364 0 : gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7365 : }
7366 0 : icode = rl->secondary_in_icode;
7367 :
7368 0 : if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7369 0 : || (rl->in != 0 && rl->out != 0))
7370 : {
7371 0 : secondary_reload_info sri, sri2;
7372 0 : enum reg_class new_class, new_t_class;
7373 :
7374 0 : sri.icode = CODE_FOR_nothing;
7375 0 : sri.prev_sri = NULL;
7376 0 : new_class
7377 0 : = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7378 0 : rl->rclass, mode,
7379 : &sri);
7380 :
7381 0 : if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7382 0 : second_reload_reg = 0;
7383 0 : else if (new_class == NO_REGS)
7384 : {
7385 0 : if (reload_adjust_reg_for_icode (&second_reload_reg,
7386 : third_reload_reg,
7387 : (enum insn_code) sri.icode))
7388 : {
7389 0 : icode = (enum insn_code) sri.icode;
7390 0 : third_reload_reg = 0;
7391 : }
7392 : else
7393 : {
7394 : oldequiv = old;
7395 : real_oldequiv = real_old;
7396 : }
7397 : }
7398 0 : else if (sri.icode != CODE_FOR_nothing)
7399 : /* We currently lack a way to express this in reloads. */
7400 0 : gcc_unreachable ();
7401 : else
7402 : {
7403 0 : sri2.icode = CODE_FOR_nothing;
7404 0 : sri2.prev_sri = &sri;
7405 0 : new_t_class
7406 0 : = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7407 : new_class, mode,
7408 : &sri);
7409 0 : if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7410 : {
7411 0 : if (reload_adjust_reg_for_temp (&second_reload_reg,
7412 : third_reload_reg,
7413 : new_class, mode))
7414 : {
7415 0 : third_reload_reg = 0;
7416 0 : tertiary_icode = (enum insn_code) sri2.icode;
7417 : }
7418 : else
7419 : {
7420 : oldequiv = old;
7421 : real_oldequiv = real_old;
7422 : }
7423 : }
7424 : else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7425 : {
7426 : rtx intermediate = second_reload_reg;
7427 :
7428 : if (reload_adjust_reg_for_temp (&intermediate, NULL,
7429 : new_class, mode)
7430 : && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7431 : ((enum insn_code)
7432 : sri2.icode)))
7433 : {
7434 : second_reload_reg = intermediate;
7435 : tertiary_icode = (enum insn_code) sri2.icode;
7436 : }
7437 : else
7438 : {
7439 : oldequiv = old;
7440 : real_oldequiv = real_old;
7441 : }
7442 : }
7443 : else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7444 : {
7445 0 : rtx intermediate = second_reload_reg;
7446 :
7447 0 : if (reload_adjust_reg_for_temp (&intermediate, NULL,
7448 : new_class, mode)
7449 0 : && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7450 : new_t_class, mode))
7451 : {
7452 0 : second_reload_reg = intermediate;
7453 0 : tertiary_icode = (enum insn_code) sri2.icode;
7454 : }
7455 : else
7456 : {
7457 : oldequiv = old;
7458 : real_oldequiv = real_old;
7459 : }
7460 0 : }
7461 : else
7462 : {
7463 : /* This could be handled more intelligently too. */
7464 : oldequiv = old;
7465 : real_oldequiv = real_old;
7466 : }
7467 : }
7468 : }
7469 :
7470 : /* If we still need a secondary reload register, check
7471 : to see if it is being used as a scratch or intermediate
7472 : register and generate code appropriately. If we need
7473 : a scratch register, use REAL_OLDEQUIV since the form of
7474 : the insn may depend on the actual address if it is
7475 : a MEM. */
7476 :
7477 0 : if (second_reload_reg)
7478 : {
7479 0 : if (icode != CODE_FOR_nothing)
7480 : {
7481 : /* We'd have to add extra code to handle this case. */
7482 0 : gcc_assert (!third_reload_reg);
7483 :
7484 0 : emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7485 : second_reload_reg));
7486 0 : special = 1;
7487 : }
7488 : else
7489 : {
7490 : /* See if we need a scratch register to load the
7491 : intermediate register (a tertiary reload). */
7492 0 : if (tertiary_icode != CODE_FOR_nothing)
7493 : {
7494 0 : emit_insn ((GEN_FCN (tertiary_icode)
7495 0 : (second_reload_reg, real_oldequiv,
7496 : third_reload_reg)));
7497 : }
7498 0 : else if (third_reload_reg)
7499 : {
7500 0 : gen_reload (third_reload_reg, real_oldequiv,
7501 : rl->opnum,
7502 : rl->when_needed);
7503 0 : gen_reload (second_reload_reg, third_reload_reg,
7504 : rl->opnum,
7505 : rl->when_needed);
7506 : }
7507 : else
7508 0 : gen_reload (second_reload_reg, real_oldequiv,
7509 : rl->opnum,
7510 : rl->when_needed);
7511 :
7512 : oldequiv = second_reload_reg;
7513 : }
7514 : }
7515 : }
7516 :
7517 0 : if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7518 : {
7519 0 : rtx real_oldequiv = oldequiv;
7520 :
7521 0 : if ((REG_P (oldequiv)
7522 0 : && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7523 0 : && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7524 0 : || reg_equiv_constant (REGNO (oldequiv)) != 0))
7525 0 : || (GET_CODE (oldequiv) == SUBREG
7526 0 : && REG_P (SUBREG_REG (oldequiv))
7527 0 : && (REGNO (SUBREG_REG (oldequiv))
7528 : >= FIRST_PSEUDO_REGISTER)
7529 0 : && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7530 0 : || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7531 0 : || (CONSTANT_P (oldequiv)
7532 0 : && (targetm.preferred_reload_class (oldequiv,
7533 0 : REGNO_REG_CLASS (REGNO (reloadreg)))
7534 : == NO_REGS)))
7535 0 : real_oldequiv = rl->in;
7536 0 : gen_reload (reloadreg, real_oldequiv, rl->opnum,
7537 : rl->when_needed);
7538 : }
7539 :
7540 0 : if (cfun->can_throw_non_call_exceptions)
7541 0 : copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7542 :
7543 : /* End this sequence. */
7544 0 : *where = end_sequence ();
7545 :
7546 : /* Update reload_override_in so that delete_address_reloads_1
7547 : can see the actual register usage. */
7548 0 : if (oldequiv_reg)
7549 0 : reload_override_in[j] = oldequiv;
7550 0 : }
7551 :
7552 : /* Generate insns to for the output reload RL, which is for the insn described
7553 : by CHAIN and has the number J. */
7554 : static void
7555 0 : emit_output_reload_insns (class insn_chain *chain, struct reload *rl,
7556 : int j)
7557 : {
7558 0 : rtx reloadreg;
7559 0 : rtx_insn *insn = chain->insn;
7560 0 : int special = 0;
7561 0 : rtx old = rl->out;
7562 0 : machine_mode mode;
7563 0 : rtx_insn *p;
7564 0 : rtx rl_reg_rtx;
7565 :
7566 0 : if (rl->when_needed == RELOAD_OTHER)
7567 0 : start_sequence ();
7568 : else
7569 0 : push_to_sequence (output_reload_insns[rl->opnum]);
7570 :
7571 0 : rl_reg_rtx = reload_reg_rtx_for_output[j];
7572 0 : mode = GET_MODE (rl_reg_rtx);
7573 :
7574 0 : reloadreg = rl_reg_rtx;
7575 :
7576 : /* If we need two reload regs, set RELOADREG to the intermediate
7577 : one, since it will be stored into OLD. We might need a secondary
7578 : register only for an input reload, so check again here. */
7579 :
7580 0 : if (rl->secondary_out_reload >= 0)
7581 : {
7582 0 : rtx real_old = old;
7583 0 : int secondary_reload = rl->secondary_out_reload;
7584 0 : int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7585 :
7586 0 : if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7587 0 : && reg_equiv_mem (REGNO (old)) != 0)
7588 0 : real_old = reg_equiv_mem (REGNO (old));
7589 :
7590 0 : if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7591 : {
7592 0 : rtx second_reloadreg = reloadreg;
7593 0 : reloadreg = rld[secondary_reload].reg_rtx;
7594 :
7595 : /* See if RELOADREG is to be used as a scratch register
7596 : or as an intermediate register. */
7597 0 : if (rl->secondary_out_icode != CODE_FOR_nothing)
7598 : {
7599 : /* We'd have to add extra code to handle this case. */
7600 0 : gcc_assert (tertiary_reload < 0);
7601 :
7602 0 : emit_insn ((GEN_FCN (rl->secondary_out_icode)
7603 0 : (real_old, second_reloadreg, reloadreg)));
7604 0 : special = 1;
7605 : }
7606 : else
7607 : {
7608 : /* See if we need both a scratch and intermediate reload
7609 : register. */
7610 :
7611 0 : enum insn_code tertiary_icode
7612 : = rld[secondary_reload].secondary_out_icode;
7613 :
7614 : /* We'd have to add more code for quartary reloads. */
7615 0 : gcc_assert (tertiary_reload < 0
7616 : || rld[tertiary_reload].secondary_out_reload < 0);
7617 :
7618 0 : if (GET_MODE (reloadreg) != mode)
7619 0 : reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7620 :
7621 0 : if (tertiary_icode != CODE_FOR_nothing)
7622 : {
7623 0 : rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7624 :
7625 : /* Copy primary reload reg to secondary reload reg.
7626 : (Note that these have been swapped above, then
7627 : secondary reload reg to OLD using our insn.) */
7628 :
7629 : /* If REAL_OLD is a paradoxical SUBREG, remove it
7630 : and try to put the opposite SUBREG on
7631 : RELOADREG. */
7632 0 : strip_paradoxical_subreg (&real_old, &reloadreg);
7633 :
7634 0 : gen_reload (reloadreg, second_reloadreg,
7635 : rl->opnum, rl->when_needed);
7636 0 : emit_insn ((GEN_FCN (tertiary_icode)
7637 0 : (real_old, reloadreg, third_reloadreg)));
7638 0 : special = 1;
7639 : }
7640 :
7641 : else
7642 : {
7643 : /* Copy between the reload regs here and then to
7644 : OUT later. */
7645 :
7646 0 : gen_reload (reloadreg, second_reloadreg,
7647 : rl->opnum, rl->when_needed);
7648 0 : if (tertiary_reload >= 0)
7649 : {
7650 0 : rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7651 :
7652 0 : gen_reload (third_reloadreg, reloadreg,
7653 : rl->opnum, rl->when_needed);
7654 0 : reloadreg = third_reloadreg;
7655 : }
7656 : }
7657 : }
7658 : }
7659 : }
7660 :
7661 : /* Output the last reload insn. */
7662 0 : if (! special)
7663 : {
7664 0 : rtx set;
7665 :
7666 : /* Don't output the last reload if OLD is not the dest of
7667 : INSN and is in the src and is clobbered by INSN. */
7668 0 : if (! flag_expensive_optimizations
7669 0 : || !REG_P (old)
7670 0 : || !(set = single_set (insn))
7671 0 : || rtx_equal_p (old, SET_DEST (set))
7672 0 : || !reg_mentioned_p (old, SET_SRC (set))
7673 0 : || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7674 0 : && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7675 0 : gen_reload (old, reloadreg, rl->opnum,
7676 : rl->when_needed);
7677 : }
7678 :
7679 : /* Look at all insns we emitted, just to be safe. */
7680 0 : for (p = get_insns (); p; p = NEXT_INSN (p))
7681 0 : if (INSN_P (p))
7682 : {
7683 0 : rtx pat = PATTERN (p);
7684 :
7685 : /* If this output reload doesn't come from a spill reg,
7686 : clear any memory of reloaded copies of the pseudo reg.
7687 : If this output reload comes from a spill reg,
7688 : reg_has_output_reload will make this do nothing. */
7689 0 : note_stores (p, forget_old_reloads_1, NULL);
7690 :
7691 0 : if (reg_mentioned_p (rl_reg_rtx, pat))
7692 : {
7693 0 : rtx set = single_set (insn);
7694 0 : if (reload_spill_index[j] < 0
7695 0 : && set
7696 0 : && SET_SRC (set) == rl_reg_rtx)
7697 : {
7698 0 : int src = REGNO (SET_SRC (set));
7699 :
7700 0 : reload_spill_index[j] = src;
7701 0 : SET_HARD_REG_BIT (reg_is_output_reload, src);
7702 0 : if (find_regno_note (insn, REG_DEAD, src))
7703 0 : SET_HARD_REG_BIT (reg_reloaded_died, src);
7704 : }
7705 0 : if (HARD_REGISTER_P (rl_reg_rtx))
7706 : {
7707 0 : int s = rl->secondary_out_reload;
7708 0 : set = single_set (p);
7709 : /* If this reload copies only to the secondary reload
7710 : register, the secondary reload does the actual
7711 : store. */
7712 0 : if (s >= 0 && set == NULL_RTX)
7713 : /* We can't tell what function the secondary reload
7714 : has and where the actual store to the pseudo is
7715 : made; leave new_spill_reg_store alone. */
7716 : ;
7717 0 : else if (s >= 0
7718 0 : && SET_SRC (set) == rl_reg_rtx
7719 0 : && SET_DEST (set) == rld[s].reg_rtx)
7720 : {
7721 : /* Usually the next instruction will be the
7722 : secondary reload insn; if we can confirm
7723 : that it is, setting new_spill_reg_store to
7724 : that insn will allow an extra optimization. */
7725 0 : rtx s_reg = rld[s].reg_rtx;
7726 0 : rtx_insn *next = NEXT_INSN (p);
7727 0 : rld[s].out = rl->out;
7728 0 : rld[s].out_reg = rl->out_reg;
7729 0 : set = single_set (next);
7730 0 : if (set && SET_SRC (set) == s_reg
7731 0 : && reload_reg_rtx_reaches_end_p (s_reg, s))
7732 : {
7733 0 : SET_HARD_REG_BIT (reg_is_output_reload,
7734 : REGNO (s_reg));
7735 0 : new_spill_reg_store[REGNO (s_reg)] = next;
7736 : }
7737 : }
7738 0 : else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7739 0 : new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7740 : }
7741 : }
7742 : }
7743 :
7744 0 : if (rl->when_needed == RELOAD_OTHER)
7745 : {
7746 0 : emit_insn (other_output_reload_insns[rl->opnum]);
7747 0 : other_output_reload_insns[rl->opnum] = get_insns ();
7748 : }
7749 : else
7750 0 : output_reload_insns[rl->opnum] = get_insns ();
7751 :
7752 0 : if (cfun->can_throw_non_call_exceptions)
7753 0 : copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7754 :
7755 0 : end_sequence ();
7756 0 : }
7757 :
7758 : /* Do input reloading for reload RL, which is for the insn described by CHAIN
7759 : and has the number J. */
7760 : static void
7761 0 : do_input_reload (class insn_chain *chain, struct reload *rl, int j)
7762 : {
7763 0 : rtx_insn *insn = chain->insn;
7764 0 : rtx old = (rl->in && MEM_P (rl->in)
7765 0 : ? rl->in_reg : rl->in);
7766 0 : rtx reg_rtx = rl->reg_rtx;
7767 :
7768 0 : if (old && reg_rtx)
7769 : {
7770 0 : machine_mode mode;
7771 :
7772 : /* Determine the mode to reload in.
7773 : This is very tricky because we have three to choose from.
7774 : There is the mode the insn operand wants (rl->inmode).
7775 : There is the mode of the reload register RELOADREG.
7776 : There is the intrinsic mode of the operand, which we could find
7777 : by stripping some SUBREGs.
7778 : It turns out that RELOADREG's mode is irrelevant:
7779 : we can change that arbitrarily.
7780 :
7781 : Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7782 : then the reload reg may not support QImode moves, so use SImode.
7783 : If foo is in memory due to spilling a pseudo reg, this is safe,
7784 : because the QImode value is in the least significant part of a
7785 : slot big enough for a SImode. If foo is some other sort of
7786 : memory reference, then it is impossible to reload this case,
7787 : so previous passes had better make sure this never happens.
7788 :
7789 : Then consider a one-word union which has SImode and one of its
7790 : members is a float, being fetched as (SUBREG:SF union:SI).
7791 : We must fetch that as SFmode because we could be loading into
7792 : a float-only register. In this case OLD's mode is correct.
7793 :
7794 : Consider an immediate integer: it has VOIDmode. Here we need
7795 : to get a mode from something else.
7796 :
7797 : In some cases, there is a fourth mode, the operand's
7798 : containing mode. If the insn specifies a containing mode for
7799 : this operand, it overrides all others.
7800 :
7801 : I am not sure whether the algorithm here is always right,
7802 : but it does the right things in those cases. */
7803 :
7804 0 : mode = GET_MODE (old);
7805 0 : if (mode == VOIDmode)
7806 0 : mode = rl->inmode;
7807 :
7808 : /* We cannot use gen_lowpart_common since it can do the wrong thing
7809 : when REG_RTX has a multi-word mode. Note that REG_RTX must
7810 : always be a REG here. */
7811 0 : if (GET_MODE (reg_rtx) != mode)
7812 0 : reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7813 : }
7814 0 : reload_reg_rtx_for_input[j] = reg_rtx;
7815 :
7816 0 : if (old != 0
7817 : /* AUTO_INC reloads need to be handled even if inherited. We got an
7818 : AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7819 0 : && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7820 0 : && ! rtx_equal_p (reg_rtx, old)
7821 0 : && reg_rtx != 0)
7822 0 : emit_input_reload_insns (chain, rld + j, old, j);
7823 :
7824 : /* When inheriting a wider reload, we have a MEM in rl->in,
7825 : e.g. inheriting a SImode output reload for
7826 : (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7827 0 : if (optimize && reload_inherited[j] && rl->in
7828 0 : && MEM_P (rl->in)
7829 0 : && MEM_P (rl->in_reg)
7830 0 : && reload_spill_index[j] >= 0
7831 0 : && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7832 0 : rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7833 :
7834 : /* If we are reloading a register that was recently stored in with an
7835 : output-reload, see if we can prove there was
7836 : actually no need to store the old value in it. */
7837 :
7838 0 : if (optimize
7839 0 : && (reload_inherited[j] || reload_override_in[j])
7840 0 : && reg_rtx
7841 0 : && REG_P (reg_rtx)
7842 0 : && spill_reg_store[REGNO (reg_rtx)] != 0
7843 : #if 0
7844 : /* There doesn't seem to be any reason to restrict this to pseudos
7845 : and doing so loses in the case where we are copying from a
7846 : register of the wrong class. */
7847 : && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7848 : #endif
7849 : /* The insn might have already some references to stackslots
7850 : replaced by MEMs, while reload_out_reg still names the
7851 : original pseudo. */
7852 0 : && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7853 0 : || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7854 0 : delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7855 0 : }
7856 :
7857 : /* Do output reloading for reload RL, which is for the insn described by
7858 : CHAIN and has the number J.
7859 : ??? At some point we need to support handling output reloads of
7860 : JUMP_INSNs. */
7861 : static void
7862 0 : do_output_reload (class insn_chain *chain, struct reload *rl, int j)
7863 : {
7864 0 : rtx note, old;
7865 0 : rtx_insn *insn = chain->insn;
7866 : /* If this is an output reload that stores something that is
7867 : not loaded in this same reload, see if we can eliminate a previous
7868 : store. */
7869 0 : rtx pseudo = rl->out_reg;
7870 0 : rtx reg_rtx = rl->reg_rtx;
7871 :
7872 0 : if (rl->out && reg_rtx)
7873 : {
7874 0 : machine_mode mode;
7875 :
7876 : /* Determine the mode to reload in.
7877 : See comments above (for input reloading). */
7878 0 : mode = GET_MODE (rl->out);
7879 0 : if (mode == VOIDmode)
7880 : {
7881 : /* VOIDmode should never happen for an output. */
7882 0 : if (asm_noperands (PATTERN (insn)) < 0)
7883 : /* It's the compiler's fault. */
7884 0 : fatal_insn ("VOIDmode on an output", insn);
7885 0 : error_for_asm (insn, "output operand is constant in %<asm%>");
7886 : /* Prevent crash--use something we know is valid. */
7887 0 : mode = word_mode;
7888 0 : rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7889 : }
7890 0 : if (GET_MODE (reg_rtx) != mode)
7891 0 : reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7892 : }
7893 0 : reload_reg_rtx_for_output[j] = reg_rtx;
7894 :
7895 0 : if (pseudo
7896 0 : && optimize
7897 0 : && REG_P (pseudo)
7898 0 : && ! rtx_equal_p (rl->in_reg, pseudo)
7899 0 : && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7900 0 : && reg_last_reload_reg[REGNO (pseudo)])
7901 : {
7902 0 : int pseudo_no = REGNO (pseudo);
7903 0 : int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7904 :
7905 : /* We don't need to test full validity of last_regno for
7906 : inherit here; we only want to know if the store actually
7907 : matches the pseudo. */
7908 0 : if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7909 0 : && reg_reloaded_contents[last_regno] == pseudo_no
7910 0 : && spill_reg_store[last_regno]
7911 0 : && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7912 0 : delete_output_reload (insn, j, last_regno, reg_rtx);
7913 : }
7914 :
7915 0 : old = rl->out_reg;
7916 0 : if (old == 0
7917 0 : || reg_rtx == 0
7918 0 : || rtx_equal_p (old, reg_rtx))
7919 0 : return;
7920 :
7921 : /* An output operand that dies right away does need a reload,
7922 : but need not be copied from it. Show the new location in the
7923 : REG_UNUSED note. */
7924 0 : if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7925 0 : && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7926 : {
7927 0 : XEXP (note, 0) = reg_rtx;
7928 0 : return;
7929 : }
7930 : /* Likewise for a SUBREG of an operand that dies. */
7931 0 : else if (GET_CODE (old) == SUBREG
7932 0 : && REG_P (SUBREG_REG (old))
7933 0 : && (note = find_reg_note (insn, REG_UNUSED,
7934 : SUBREG_REG (old))) != 0)
7935 : {
7936 0 : XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7937 0 : return;
7938 : }
7939 0 : else if (GET_CODE (old) == SCRATCH)
7940 : /* If we aren't optimizing, there won't be a REG_UNUSED note,
7941 : but we don't want to make an output reload. */
7942 : return;
7943 :
7944 : /* If is a JUMP_INSN, we can't support output reloads yet. */
7945 0 : gcc_assert (NONJUMP_INSN_P (insn));
7946 :
7947 0 : emit_output_reload_insns (chain, rld + j, j);
7948 : }
7949 :
7950 : /* A reload copies values of MODE from register SRC to register DEST.
7951 : Return true if it can be treated for inheritance purposes like a
7952 : group of reloads, each one reloading a single hard register. The
7953 : caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7954 : occupy the same number of hard registers. */
7955 :
7956 : static bool
7957 0 : inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7958 : int src ATTRIBUTE_UNUSED,
7959 : machine_mode mode ATTRIBUTE_UNUSED)
7960 : {
7961 0 : return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7962 0 : && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7963 : }
7964 :
7965 : /* Output insns to reload values in and out of the chosen reload regs. */
7966 :
7967 : static void
7968 0 : emit_reload_insns (class insn_chain *chain)
7969 : {
7970 0 : rtx_insn *insn = chain->insn;
7971 :
7972 0 : int j;
7973 :
7974 0 : CLEAR_HARD_REG_SET (reg_reloaded_died);
7975 :
7976 0 : for (j = 0; j < reload_n_operands; j++)
7977 0 : input_reload_insns[j] = input_address_reload_insns[j]
7978 0 : = inpaddr_address_reload_insns[j]
7979 0 : = output_reload_insns[j] = output_address_reload_insns[j]
7980 0 : = outaddr_address_reload_insns[j]
7981 0 : = other_output_reload_insns[j] = 0;
7982 0 : other_input_address_reload_insns = 0;
7983 0 : other_input_reload_insns = 0;
7984 0 : operand_reload_insns = 0;
7985 0 : other_operand_reload_insns = 0;
7986 :
7987 : /* Dump reloads into the dump file. */
7988 0 : if (dump_file)
7989 : {
7990 0 : fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7991 0 : debug_reload_to_stream (dump_file);
7992 : }
7993 :
7994 0 : for (j = 0; j < n_reloads; j++)
7995 0 : if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7996 : {
7997 : unsigned int i;
7998 :
7999 0 : for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8000 0 : new_spill_reg_store[i] = 0;
8001 : }
8002 :
8003 : /* Now output the instructions to copy the data into and out of the
8004 : reload registers. Do these in the order that the reloads were reported,
8005 : since reloads of base and index registers precede reloads of operands
8006 : and the operands may need the base and index registers reloaded. */
8007 :
8008 0 : for (j = 0; j < n_reloads; j++)
8009 : {
8010 0 : do_input_reload (chain, rld + j, j);
8011 0 : do_output_reload (chain, rld + j, j);
8012 : }
8013 :
8014 : /* Now write all the insns we made for reloads in the order expected by
8015 : the allocation functions. Prior to the insn being reloaded, we write
8016 : the following reloads:
8017 :
8018 : RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8019 :
8020 : RELOAD_OTHER reloads.
8021 :
8022 : For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8023 : by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8024 : RELOAD_FOR_INPUT reload for the operand.
8025 :
8026 : RELOAD_FOR_OPADDR_ADDRS reloads.
8027 :
8028 : RELOAD_FOR_OPERAND_ADDRESS reloads.
8029 :
8030 : After the insn being reloaded, we write the following:
8031 :
8032 : For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8033 : by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8034 : RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8035 : reloads for the operand. The RELOAD_OTHER output reloads are
8036 : output in descending order by reload number. */
8037 :
8038 0 : emit_insn_before (other_input_address_reload_insns, insn);
8039 0 : emit_insn_before (other_input_reload_insns, insn);
8040 :
8041 0 : for (j = 0; j < reload_n_operands; j++)
8042 : {
8043 0 : emit_insn_before (inpaddr_address_reload_insns[j], insn);
8044 0 : emit_insn_before (input_address_reload_insns[j], insn);
8045 0 : emit_insn_before (input_reload_insns[j], insn);
8046 : }
8047 :
8048 0 : emit_insn_before (other_operand_reload_insns, insn);
8049 0 : emit_insn_before (operand_reload_insns, insn);
8050 :
8051 0 : for (j = 0; j < reload_n_operands; j++)
8052 : {
8053 0 : rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8054 0 : x = emit_insn_after (output_address_reload_insns[j], x);
8055 0 : x = emit_insn_after (output_reload_insns[j], x);
8056 0 : emit_insn_after (other_output_reload_insns[j], x);
8057 : }
8058 :
8059 : /* For all the spill regs newly reloaded in this instruction,
8060 : record what they were reloaded from, so subsequent instructions
8061 : can inherit the reloads.
8062 :
8063 : Update spill_reg_store for the reloads of this insn.
8064 : Copy the elements that were updated in the loop above. */
8065 :
8066 0 : for (j = 0; j < n_reloads; j++)
8067 : {
8068 0 : int r = reload_order[j];
8069 0 : int i = reload_spill_index[r];
8070 :
8071 : /* If this is a non-inherited input reload from a pseudo, we must
8072 : clear any memory of a previous store to the same pseudo. Only do
8073 : something if there will not be an output reload for the pseudo
8074 : being reloaded. */
8075 0 : if (rld[r].in_reg != 0
8076 0 : && ! (reload_inherited[r] || reload_override_in[r]))
8077 : {
8078 0 : rtx reg = rld[r].in_reg;
8079 :
8080 0 : if (GET_CODE (reg) == SUBREG)
8081 0 : reg = SUBREG_REG (reg);
8082 :
8083 0 : if (REG_P (reg)
8084 0 : && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8085 0 : && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8086 : {
8087 0 : int nregno = REGNO (reg);
8088 :
8089 0 : if (reg_last_reload_reg[nregno])
8090 : {
8091 0 : int last_regno = REGNO (reg_last_reload_reg[nregno]);
8092 :
8093 0 : if (reg_reloaded_contents[last_regno] == nregno)
8094 0 : spill_reg_store[last_regno] = 0;
8095 : }
8096 : }
8097 : }
8098 :
8099 : /* I is nonneg if this reload used a register.
8100 : If rld[r].reg_rtx is 0, this is an optional reload
8101 : that we opted to ignore. */
8102 :
8103 0 : if (i >= 0 && rld[r].reg_rtx != 0)
8104 : {
8105 0 : int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8106 0 : int k;
8107 :
8108 : /* For a multi register reload, we need to check if all or part
8109 : of the value lives to the end. */
8110 0 : for (k = 0; k < nr; k++)
8111 0 : if (reload_reg_reaches_end_p (i + k, r))
8112 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8113 :
8114 : /* Maybe the spill reg contains a copy of reload_out. */
8115 0 : if (rld[r].out != 0
8116 0 : && (REG_P (rld[r].out)
8117 0 : || (rld[r].out_reg
8118 0 : ? REG_P (rld[r].out_reg)
8119 : /* The reload value is an auto-modification of
8120 : some kind. For PRE_INC, POST_INC, PRE_DEC
8121 : and POST_DEC, we record an equivalence
8122 : between the reload register and the operand
8123 : on the optimistic assumption that we can make
8124 : the equivalence hold. reload_as_needed must
8125 : then either make it hold or invalidate the
8126 : equivalence.
8127 :
8128 : PRE_MODIFY and POST_MODIFY addresses are reloaded
8129 : somewhat differently, and allowing them here leads
8130 : to problems. */
8131 : : (GET_CODE (rld[r].out) != POST_MODIFY
8132 0 : && GET_CODE (rld[r].out) != PRE_MODIFY))))
8133 : {
8134 0 : rtx reg;
8135 :
8136 0 : reg = reload_reg_rtx_for_output[r];
8137 0 : if (reload_reg_rtx_reaches_end_p (reg, r))
8138 : {
8139 0 : machine_mode mode = GET_MODE (reg);
8140 0 : int regno = REGNO (reg);
8141 0 : int nregs = REG_NREGS (reg);
8142 0 : rtx out = (REG_P (rld[r].out)
8143 0 : ? rld[r].out
8144 0 : : rld[r].out_reg
8145 0 : ? rld[r].out_reg
8146 0 : /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8147 0 : int out_regno = REGNO (out);
8148 0 : int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8149 0 : : hard_regno_nregs (out_regno, mode));
8150 0 : bool piecemeal;
8151 :
8152 0 : spill_reg_store[regno] = new_spill_reg_store[regno];
8153 0 : spill_reg_stored_to[regno] = out;
8154 0 : reg_last_reload_reg[out_regno] = reg;
8155 :
8156 0 : piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8157 0 : && nregs == out_nregs
8158 0 : && inherit_piecemeal_p (out_regno, regno, mode));
8159 :
8160 : /* If OUT_REGNO is a hard register, it may occupy more than
8161 : one register. If it does, say what is in the
8162 : rest of the registers assuming that both registers
8163 : agree on how many words the object takes. If not,
8164 : invalidate the subsequent registers. */
8165 :
8166 0 : if (HARD_REGISTER_NUM_P (out_regno))
8167 0 : for (k = 1; k < out_nregs; k++)
8168 0 : reg_last_reload_reg[out_regno + k]
8169 0 : = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8170 :
8171 : /* Now do the inverse operation. */
8172 0 : for (k = 0; k < nregs; k++)
8173 : {
8174 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8175 0 : reg_reloaded_contents[regno + k]
8176 0 : = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8177 0 : ? out_regno
8178 : : out_regno + k);
8179 0 : reg_reloaded_insn[regno + k] = insn;
8180 0 : SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8181 : }
8182 : }
8183 : }
8184 : /* Maybe the spill reg contains a copy of reload_in. Only do
8185 : something if there will not be an output reload for
8186 : the register being reloaded. */
8187 0 : else if (rld[r].out_reg == 0
8188 0 : && rld[r].in != 0
8189 0 : && ((REG_P (rld[r].in)
8190 0 : && !HARD_REGISTER_P (rld[r].in)
8191 0 : && !REGNO_REG_SET_P (®_has_output_reload,
8192 : REGNO (rld[r].in)))
8193 0 : || (REG_P (rld[r].in_reg)
8194 0 : && !REGNO_REG_SET_P (®_has_output_reload,
8195 : REGNO (rld[r].in_reg))))
8196 0 : && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8197 : {
8198 0 : rtx reg;
8199 :
8200 0 : reg = reload_reg_rtx_for_input[r];
8201 0 : if (reload_reg_rtx_reaches_end_p (reg, r))
8202 : {
8203 0 : machine_mode mode;
8204 0 : int regno;
8205 0 : int nregs;
8206 0 : int in_regno;
8207 0 : int in_nregs;
8208 0 : rtx in;
8209 0 : bool piecemeal;
8210 :
8211 0 : mode = GET_MODE (reg);
8212 0 : regno = REGNO (reg);
8213 0 : nregs = REG_NREGS (reg);
8214 0 : if (REG_P (rld[r].in)
8215 0 : && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8216 : in = rld[r].in;
8217 0 : else if (REG_P (rld[r].in_reg))
8218 : in = rld[r].in_reg;
8219 : else
8220 0 : in = XEXP (rld[r].in_reg, 0);
8221 0 : in_regno = REGNO (in);
8222 :
8223 0 : in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8224 0 : : hard_regno_nregs (in_regno, mode));
8225 :
8226 0 : reg_last_reload_reg[in_regno] = reg;
8227 :
8228 0 : piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8229 0 : && nregs == in_nregs
8230 0 : && inherit_piecemeal_p (regno, in_regno, mode));
8231 :
8232 0 : if (HARD_REGISTER_NUM_P (in_regno))
8233 0 : for (k = 1; k < in_nregs; k++)
8234 0 : reg_last_reload_reg[in_regno + k]
8235 0 : = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8236 :
8237 : /* Unless we inherited this reload, show we haven't
8238 : recently done a store.
8239 : Previous stores of inherited auto_inc expressions
8240 : also have to be discarded. */
8241 0 : if (! reload_inherited[r]
8242 0 : || (rld[r].out && ! rld[r].out_reg))
8243 0 : spill_reg_store[regno] = 0;
8244 :
8245 0 : for (k = 0; k < nregs; k++)
8246 : {
8247 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8248 0 : reg_reloaded_contents[regno + k]
8249 0 : = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8250 0 : ? in_regno
8251 : : in_regno + k);
8252 0 : reg_reloaded_insn[regno + k] = insn;
8253 0 : SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8254 : }
8255 : }
8256 : }
8257 : }
8258 :
8259 : /* The following if-statement was #if 0'd in 1.34 (or before...).
8260 : It's re-enabled in 1.35 because supposedly nothing else
8261 : deals with this problem. */
8262 :
8263 : /* If a register gets output-reloaded from a non-spill register,
8264 : that invalidates any previous reloaded copy of it.
8265 : But forget_old_reloads_1 won't get to see it, because
8266 : it thinks only about the original insn. So invalidate it here.
8267 : Also do the same thing for RELOAD_OTHER constraints where the
8268 : output is discarded. */
8269 0 : if (i < 0
8270 0 : && ((rld[r].out != 0
8271 0 : && (REG_P (rld[r].out)
8272 0 : || (MEM_P (rld[r].out)
8273 0 : && REG_P (rld[r].out_reg))))
8274 0 : || (rld[r].out == 0 && rld[r].out_reg
8275 0 : && REG_P (rld[r].out_reg))))
8276 : {
8277 0 : rtx out = ((rld[r].out && REG_P (rld[r].out))
8278 0 : ? rld[r].out : rld[r].out_reg);
8279 0 : int out_regno = REGNO (out);
8280 0 : machine_mode mode = GET_MODE (out);
8281 :
8282 : /* REG_RTX is now set or clobbered by the main instruction.
8283 : As the comment above explains, forget_old_reloads_1 only
8284 : sees the original instruction, and there is no guarantee
8285 : that the original instruction also clobbered REG_RTX.
8286 : For example, if find_reloads sees that the input side of
8287 : a matched operand pair dies in this instruction, it may
8288 : use the input register as the reload register.
8289 :
8290 : Calling forget_old_reloads_1 is a waste of effort if
8291 : REG_RTX is also the output register.
8292 :
8293 : If we know that REG_RTX holds the value of a pseudo
8294 : register, the code after the call will record that fact. */
8295 0 : if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8296 0 : forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8297 :
8298 0 : if (!HARD_REGISTER_NUM_P (out_regno))
8299 : {
8300 0 : rtx src_reg;
8301 0 : rtx_insn *store_insn = NULL;
8302 :
8303 0 : reg_last_reload_reg[out_regno] = 0;
8304 :
8305 : /* If we can find a hard register that is stored, record
8306 : the storing insn so that we may delete this insn with
8307 : delete_output_reload. */
8308 0 : src_reg = reload_reg_rtx_for_output[r];
8309 :
8310 0 : if (src_reg)
8311 : {
8312 0 : if (reload_reg_rtx_reaches_end_p (src_reg, r))
8313 0 : store_insn = new_spill_reg_store[REGNO (src_reg)];
8314 : else
8315 : src_reg = NULL_RTX;
8316 : }
8317 : else
8318 : {
8319 : /* If this is an optional reload, try to find the
8320 : source reg from an input reload. */
8321 0 : rtx set = single_set (insn);
8322 0 : if (set && SET_DEST (set) == rld[r].out)
8323 : {
8324 0 : int k;
8325 :
8326 0 : src_reg = SET_SRC (set);
8327 0 : store_insn = insn;
8328 0 : for (k = 0; k < n_reloads; k++)
8329 : {
8330 0 : if (rld[k].in == src_reg)
8331 : {
8332 0 : src_reg = reload_reg_rtx_for_input[k];
8333 0 : break;
8334 : }
8335 : }
8336 : }
8337 : }
8338 0 : if (src_reg && REG_P (src_reg)
8339 0 : && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8340 : {
8341 0 : int src_regno, src_nregs, k;
8342 0 : rtx note;
8343 :
8344 0 : gcc_assert (GET_MODE (src_reg) == mode);
8345 0 : src_regno = REGNO (src_reg);
8346 0 : src_nregs = hard_regno_nregs (src_regno, mode);
8347 : /* The place where to find a death note varies with
8348 : PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8349 : necessarily checked exactly in the code that moves
8350 : notes, so just check both locations. */
8351 0 : note = find_regno_note (insn, REG_DEAD, src_regno);
8352 0 : if (! note && store_insn)
8353 0 : note = find_regno_note (store_insn, REG_DEAD, src_regno);
8354 0 : for (k = 0; k < src_nregs; k++)
8355 : {
8356 0 : spill_reg_store[src_regno + k] = store_insn;
8357 0 : spill_reg_stored_to[src_regno + k] = out;
8358 0 : reg_reloaded_contents[src_regno + k] = out_regno;
8359 0 : reg_reloaded_insn[src_regno + k] = store_insn;
8360 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8361 0 : SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8362 0 : SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8363 0 : if (note)
8364 0 : SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8365 : else
8366 0 : CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8367 : }
8368 0 : reg_last_reload_reg[out_regno] = src_reg;
8369 : /* We have to set reg_has_output_reload here, or else
8370 : forget_old_reloads_1 will clear reg_last_reload_reg
8371 : right away. */
8372 0 : SET_REGNO_REG_SET (®_has_output_reload,
8373 : out_regno);
8374 : }
8375 : }
8376 : else
8377 : {
8378 0 : int k, out_nregs = hard_regno_nregs (out_regno, mode);
8379 :
8380 0 : for (k = 0; k < out_nregs; k++)
8381 0 : reg_last_reload_reg[out_regno + k] = 0;
8382 : }
8383 : }
8384 : }
8385 0 : reg_reloaded_dead |= reg_reloaded_died;
8386 0 : }
8387 :
8388 :
8389 : /* Helper for emit_insn_if_valid_for_reload. */
8390 :
8391 : static rtx_insn *
8392 0 : emit_insn_if_valid_for_reload_1 (rtx pat)
8393 : {
8394 0 : rtx_insn *last = get_last_insn ();
8395 0 : int code;
8396 :
8397 0 : rtx_insn *insn = emit_insn (pat);
8398 0 : code = recog_memoized (insn);
8399 :
8400 0 : if (code >= 0)
8401 : {
8402 0 : extract_insn (insn);
8403 : /* We want constrain operands to treat this insn strictly in its
8404 : validity determination, i.e., the way it would after reload has
8405 : completed. */
8406 0 : if (constrain_operands (1, get_enabled_alternatives (insn)))
8407 : return insn;
8408 : }
8409 :
8410 0 : delete_insns_since (last);
8411 0 : return NULL;
8412 : }
8413 :
8414 : /* Go through the motions to emit INSN and test if it is strictly valid.
8415 : Return the emitted insn if valid, else return NULL. */
8416 :
8417 : static rtx_insn *
8418 0 : emit_insn_if_valid_for_reload (rtx pat)
8419 : {
8420 0 : rtx_insn *insn = emit_insn_if_valid_for_reload_1 (pat);
8421 :
8422 0 : if (insn)
8423 : return insn;
8424 :
8425 : /* If the pattern is a SET, and this target has a single
8426 : flags-register, try again with a PARALLEL that clobbers that
8427 : register. */
8428 0 : if (targetm.flags_regnum == INVALID_REGNUM || GET_CODE (pat) != SET)
8429 : return NULL;
8430 :
8431 0 : rtx flags_clobber = gen_hard_reg_clobber (CCmode, targetm.flags_regnum);
8432 0 : rtx parpat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, flags_clobber));
8433 :
8434 0 : return emit_insn_if_valid_for_reload (parpat);
8435 : }
8436 :
8437 : /* Emit code to perform a reload from IN (which may be a reload register) to
8438 : OUT (which may also be a reload register). IN or OUT is from operand
8439 : OPNUM with reload type TYPE.
8440 :
8441 : Returns first insn emitted. */
8442 :
8443 : static rtx_insn *
8444 0 : gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8445 : {
8446 0 : rtx_insn *last = get_last_insn ();
8447 0 : rtx_insn *tem;
8448 0 : rtx tem1, tem2;
8449 :
8450 : /* If IN is a paradoxical SUBREG, remove it and try to put the
8451 : opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8452 0 : if (!strip_paradoxical_subreg (&in, &out))
8453 0 : strip_paradoxical_subreg (&out, &in);
8454 :
8455 : /* How to do this reload can get quite tricky. Normally, we are being
8456 : asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8457 : register that didn't get a hard register. In that case we can just
8458 : call emit_move_insn.
8459 :
8460 : We can also be asked to reload a PLUS that adds a register or a MEM to
8461 : another register, constant or MEM. This can occur during frame pointer
8462 : elimination and while reloading addresses. This case is handled by
8463 : trying to emit a single insn to perform the add. If it is not valid,
8464 : we use a two insn sequence.
8465 :
8466 : Or we can be asked to reload an unary operand that was a fragment of
8467 : an addressing mode, into a register. If it isn't recognized as-is,
8468 : we try making the unop operand and the reload-register the same:
8469 : (set reg:X (unop:X expr:Y))
8470 : -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8471 :
8472 : Finally, we could be called to handle an 'o' constraint by putting
8473 : an address into a register. In that case, we first try to do this
8474 : with a named pattern of "reload_load_address". If no such pattern
8475 : exists, we just emit a SET insn and hope for the best (it will normally
8476 : be valid on machines that use 'o').
8477 :
8478 : This entire process is made complex because reload will never
8479 : process the insns we generate here and so we must ensure that
8480 : they will fit their constraints and also by the fact that parts of
8481 : IN might be being reloaded separately and replaced with spill registers.
8482 : Because of this, we are, in some sense, just guessing the right approach
8483 : here. The one listed above seems to work.
8484 :
8485 : ??? At some point, this whole thing needs to be rethought. */
8486 :
8487 0 : if (GET_CODE (in) == PLUS
8488 0 : && (REG_P (XEXP (in, 0))
8489 : || GET_CODE (XEXP (in, 0)) == SUBREG
8490 : || MEM_P (XEXP (in, 0)))
8491 0 : && (REG_P (XEXP (in, 1))
8492 0 : || GET_CODE (XEXP (in, 1)) == SUBREG
8493 0 : || CONSTANT_P (XEXP (in, 1))
8494 0 : || MEM_P (XEXP (in, 1))))
8495 : {
8496 : /* We need to compute the sum of a register or a MEM and another
8497 : register, constant, or MEM, and put it into the reload
8498 : register. The best possible way of doing this is if the machine
8499 : has a three-operand ADD insn that accepts the required operands.
8500 :
8501 : The simplest approach is to try to generate such an insn and see if it
8502 : is recognized and matches its constraints. If so, it can be used.
8503 :
8504 : It might be better not to actually emit the insn unless it is valid,
8505 : but we need to pass the insn as an operand to `recog' and
8506 : `extract_insn' and it is simpler to emit and then delete the insn if
8507 : not valid than to dummy things up. */
8508 :
8509 0 : rtx op0, op1, tem;
8510 0 : rtx_insn *insn;
8511 0 : enum insn_code code;
8512 :
8513 0 : op0 = find_replacement (&XEXP (in, 0));
8514 0 : op1 = find_replacement (&XEXP (in, 1));
8515 :
8516 : /* Since constraint checking is strict, commutativity won't be
8517 : checked, so we need to do that here to avoid spurious failure
8518 : if the add instruction is two-address and the second operand
8519 : of the add is the same as the reload reg, which is frequently
8520 : the case. If the insn would be A = B + A, rearrange it so
8521 : it will be A = A + B as constrain_operands expects. */
8522 :
8523 0 : if (REG_P (XEXP (in, 1))
8524 0 : && REGNO (out) == REGNO (XEXP (in, 1)))
8525 : tem = op0, op0 = op1, op1 = tem;
8526 :
8527 0 : if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8528 0 : in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8529 :
8530 0 : insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8531 0 : if (insn)
8532 : return insn;
8533 :
8534 : /* If that failed, we must use a conservative two-insn sequence.
8535 :
8536 : Use a move to copy one operand into the reload register. Prefer
8537 : to reload a constant, MEM or pseudo since the move patterns can
8538 : handle an arbitrary operand. If OP1 is not a constant, MEM or
8539 : pseudo and OP1 is not a valid operand for an add instruction, then
8540 : reload OP1.
8541 :
8542 : After reloading one of the operands into the reload register, add
8543 : the reload register to the output register.
8544 :
8545 : If there is another way to do this for a specific machine, a
8546 : DEFINE_PEEPHOLE should be specified that recognizes the sequence
8547 : we emit below. */
8548 :
8549 0 : code = optab_handler (add_optab, GET_MODE (out));
8550 :
8551 0 : if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8552 0 : || (REG_P (op1)
8553 0 : && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8554 0 : || (code != CODE_FOR_nothing
8555 0 : && !insn_operand_matches (code, 2, op1)))
8556 : tem = op0, op0 = op1, op1 = tem;
8557 :
8558 0 : gen_reload (out, op0, opnum, type);
8559 :
8560 : /* If OP0 and OP1 are the same, we can use OUT for OP1.
8561 : This fixes a problem on the 32K where the stack pointer cannot
8562 : be used as an operand of an add insn. */
8563 :
8564 0 : if (rtx_equal_p (op0, op1))
8565 0 : op1 = out;
8566 :
8567 0 : insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8568 0 : if (insn)
8569 : {
8570 : /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8571 0 : set_dst_reg_note (insn, REG_EQUIV, in, out);
8572 0 : return insn;
8573 : }
8574 :
8575 : /* If that failed, copy the address register to the reload register.
8576 : Then add the constant to the reload register. */
8577 :
8578 0 : gcc_assert (!reg_overlap_mentioned_p (out, op0));
8579 0 : gen_reload (out, op1, opnum, type);
8580 0 : insn = emit_insn (gen_add2_insn (out, op0));
8581 0 : set_dst_reg_note (insn, REG_EQUIV, in, out);
8582 0 : }
8583 :
8584 : /* If we need a memory location to do the move, do it that way. */
8585 0 : else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8586 0 : (REG_P (tem1) && REG_P (tem2)))
8587 0 : && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8588 0 : && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8589 0 : && targetm.secondary_memory_needed (GET_MODE (out),
8590 0 : REGNO_REG_CLASS (REGNO (tem1)),
8591 0 : REGNO_REG_CLASS (REGNO (tem2))))
8592 : {
8593 : /* Get the memory to use and rewrite both registers to its mode. */
8594 0 : rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8595 :
8596 0 : if (GET_MODE (loc) != GET_MODE (out))
8597 0 : out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8598 :
8599 0 : if (GET_MODE (loc) != GET_MODE (in))
8600 0 : in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8601 :
8602 0 : gen_reload (loc, in, opnum, type);
8603 0 : gen_reload (out, loc, opnum, type);
8604 : }
8605 0 : else if (REG_P (out) && UNARY_P (in))
8606 : {
8607 0 : rtx op1;
8608 0 : rtx out_moded;
8609 0 : rtx_insn *set;
8610 :
8611 0 : op1 = find_replacement (&XEXP (in, 0));
8612 0 : if (op1 != XEXP (in, 0))
8613 0 : in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8614 :
8615 : /* First, try a plain SET. */
8616 0 : set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8617 0 : if (set)
8618 : return set;
8619 :
8620 : /* If that failed, move the inner operand to the reload
8621 : register, and try the same unop with the inner expression
8622 : replaced with the reload register. */
8623 :
8624 0 : if (GET_MODE (op1) != GET_MODE (out))
8625 0 : out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8626 : else
8627 : out_moded = out;
8628 :
8629 0 : gen_reload (out_moded, op1, opnum, type);
8630 :
8631 0 : rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8632 : out_moded));
8633 0 : rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8634 0 : if (insn)
8635 : {
8636 0 : set_unique_reg_note (insn, REG_EQUIV, in);
8637 0 : return insn;
8638 : }
8639 :
8640 0 : fatal_insn ("failure trying to reload:", in);
8641 : }
8642 : /* If IN is a simple operand, use gen_move_insn. */
8643 0 : else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8644 : {
8645 0 : tem = emit_insn (gen_move_insn (out, in));
8646 : /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8647 0 : mark_jump_label (in, tem, 0);
8648 : }
8649 :
8650 0 : else if (targetm.have_reload_load_address ())
8651 0 : emit_insn (targetm.gen_reload_load_address (out, in));
8652 :
8653 : /* Otherwise, just write (set OUT IN) and hope for the best. */
8654 : else
8655 0 : emit_insn (gen_rtx_SET (out, in));
8656 :
8657 : /* Return the first insn emitted.
8658 : We cannot just return get_last_insn, because there may have
8659 : been multiple instructions emitted. Also note that gen_move_insn may
8660 : emit more than one insn itself, so we cannot assume that there is one
8661 : insn emitted per emit_insn_before call. */
8662 :
8663 0 : return last ? NEXT_INSN (last) : get_insns ();
8664 : }
8665 :
8666 : /* Delete a previously made output-reload whose result we now believe
8667 : is not needed. First we double-check.
8668 :
8669 : INSN is the insn now being processed.
8670 : LAST_RELOAD_REG is the hard register number for which we want to delete
8671 : the last output reload.
8672 : J is the reload-number that originally used REG. The caller has made
8673 : certain that reload J doesn't use REG any longer for input.
8674 : NEW_RELOAD_REG is reload register that reload J is using for REG. */
8675 :
8676 : static void
8677 0 : delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8678 : rtx new_reload_reg)
8679 : {
8680 0 : rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8681 0 : rtx reg = spill_reg_stored_to[last_reload_reg];
8682 0 : int k;
8683 0 : int n_occurrences;
8684 0 : int n_inherited = 0;
8685 0 : rtx substed;
8686 0 : unsigned regno;
8687 0 : int nregs;
8688 :
8689 : /* It is possible that this reload has been only used to set another reload
8690 : we eliminated earlier and thus deleted this instruction too. */
8691 0 : if (output_reload_insn->deleted ())
8692 : return;
8693 :
8694 : /* Get the raw pseudo-register referred to. */
8695 :
8696 0 : while (GET_CODE (reg) == SUBREG)
8697 0 : reg = SUBREG_REG (reg);
8698 0 : substed = reg_equiv_memory_loc (REGNO (reg));
8699 :
8700 : /* This is unsafe if the operand occurs more often in the current
8701 : insn than it is inherited. */
8702 0 : for (k = n_reloads - 1; k >= 0; k--)
8703 : {
8704 0 : rtx reg2 = rld[k].in;
8705 0 : if (! reg2)
8706 0 : continue;
8707 0 : if (MEM_P (reg2) || reload_override_in[k])
8708 0 : reg2 = rld[k].in_reg;
8709 :
8710 : if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8711 : reg2 = XEXP (rld[k].in_reg, 0);
8712 :
8713 0 : while (GET_CODE (reg2) == SUBREG)
8714 0 : reg2 = SUBREG_REG (reg2);
8715 0 : if (rtx_equal_p (reg2, reg))
8716 : {
8717 0 : if (reload_inherited[k] || reload_override_in[k] || k == j)
8718 0 : n_inherited++;
8719 : else
8720 : return;
8721 : }
8722 : }
8723 0 : n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8724 0 : if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8725 0 : n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8726 : reg, 0);
8727 0 : if (substed)
8728 0 : n_occurrences += count_occurrences (PATTERN (insn),
8729 0 : eliminate_regs (substed, VOIDmode,
8730 : NULL_RTX), 0);
8731 0 : for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8732 : {
8733 0 : gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8734 0 : n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8735 : }
8736 0 : if (n_occurrences > n_inherited)
8737 : return;
8738 :
8739 0 : regno = REGNO (reg);
8740 0 : nregs = REG_NREGS (reg);
8741 :
8742 : /* If the pseudo-reg we are reloading is no longer referenced
8743 : anywhere between the store into it and here,
8744 : and we're within the same basic block, then the value can only
8745 : pass through the reload reg and end up here.
8746 : Otherwise, give up--return. */
8747 0 : for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8748 0 : i1 != insn; i1 = NEXT_INSN (i1))
8749 : {
8750 0 : if (NOTE_INSN_BASIC_BLOCK_P (i1))
8751 : return;
8752 0 : if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8753 0 : && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8754 : {
8755 : /* If this is USE in front of INSN, we only have to check that
8756 : there are no more references than accounted for by inheritance. */
8757 0 : while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8758 : {
8759 0 : n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8760 0 : i1 = NEXT_INSN (i1);
8761 : }
8762 0 : if (n_occurrences <= n_inherited && i1 == insn)
8763 : break;
8764 : return;
8765 : }
8766 : }
8767 :
8768 : /* We will be deleting the insn. Remove the spill reg information. */
8769 0 : for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8770 : {
8771 0 : spill_reg_store[last_reload_reg + k] = 0;
8772 0 : spill_reg_stored_to[last_reload_reg + k] = 0;
8773 : }
8774 :
8775 : /* The caller has already checked that REG dies or is set in INSN.
8776 : It has also checked that we are optimizing, and thus some
8777 : inaccuracies in the debugging information are acceptable.
8778 : So we could just delete output_reload_insn. But in some cases
8779 : we can improve the debugging information without sacrificing
8780 : optimization - maybe even improving the code: See if the pseudo
8781 : reg has been completely replaced with reload regs. If so, delete
8782 : the store insn and forget we had a stack slot for the pseudo. */
8783 0 : if (rld[j].out != rld[j].in
8784 0 : && REG_N_DEATHS (REGNO (reg)) == 1
8785 0 : && REG_N_SETS (REGNO (reg)) == 1
8786 0 : && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8787 0 : && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8788 : {
8789 0 : rtx_insn *i2;
8790 :
8791 : /* We know that it was used only between here and the beginning of
8792 : the current basic block. (We also know that the last use before
8793 : INSN was the output reload we are thinking of deleting, but never
8794 : mind that.) Search that range; see if any ref remains. */
8795 0 : for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8796 : {
8797 0 : rtx set = single_set (i2);
8798 :
8799 : /* Uses which just store in the pseudo don't count,
8800 : since if they are the only uses, they are dead. */
8801 0 : if (set != 0 && SET_DEST (set) == reg)
8802 0 : continue;
8803 0 : if (LABEL_P (i2) || JUMP_P (i2))
8804 : break;
8805 0 : if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8806 0 : && reg_mentioned_p (reg, PATTERN (i2)))
8807 : {
8808 : /* Some other ref remains; just delete the output reload we
8809 : know to be dead. */
8810 0 : delete_address_reloads (output_reload_insn, insn);
8811 0 : delete_insn (output_reload_insn);
8812 0 : return;
8813 : }
8814 : }
8815 :
8816 : /* Delete the now-dead stores into this pseudo. Note that this
8817 : loop also takes care of deleting output_reload_insn. */
8818 0 : for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8819 : {
8820 0 : rtx set = single_set (i2);
8821 :
8822 0 : if (set != 0 && SET_DEST (set) == reg)
8823 : {
8824 0 : delete_address_reloads (i2, insn);
8825 0 : delete_insn (i2);
8826 : }
8827 0 : if (LABEL_P (i2) || JUMP_P (i2))
8828 : break;
8829 : }
8830 :
8831 : /* For the debugging info, say the pseudo lives in this reload reg. */
8832 0 : reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8833 0 : if (ira_conflicts_p)
8834 : /* Inform IRA about the change. */
8835 0 : ira_mark_allocation_change (REGNO (reg));
8836 0 : alter_reg (REGNO (reg), -1, false);
8837 : }
8838 : else
8839 : {
8840 0 : delete_address_reloads (output_reload_insn, insn);
8841 0 : delete_insn (output_reload_insn);
8842 : }
8843 : }
8844 :
8845 : /* We are going to delete DEAD_INSN. Recursively delete loads of
8846 : reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8847 : CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8848 : static void
8849 0 : delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8850 : {
8851 0 : rtx set = single_set (dead_insn);
8852 0 : rtx set2, dst;
8853 0 : rtx_insn *prev, *next;
8854 0 : if (set)
8855 : {
8856 0 : rtx dst = SET_DEST (set);
8857 0 : if (MEM_P (dst))
8858 0 : delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8859 : }
8860 : /* If we deleted the store from a reloaded post_{in,de}c expression,
8861 : we can delete the matching adds. */
8862 0 : prev = PREV_INSN (dead_insn);
8863 0 : next = NEXT_INSN (dead_insn);
8864 0 : if (! prev || ! next)
8865 : return;
8866 0 : set = single_set (next);
8867 0 : set2 = single_set (prev);
8868 0 : if (! set || ! set2
8869 0 : || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8870 0 : || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8871 0 : || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8872 : return;
8873 0 : dst = SET_DEST (set);
8874 0 : if (! rtx_equal_p (dst, SET_DEST (set2))
8875 0 : || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8876 0 : || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8877 0 : || (INTVAL (XEXP (SET_SRC (set), 1))
8878 0 : != -INTVAL (XEXP (SET_SRC (set2), 1))))
8879 0 : return;
8880 0 : delete_related_insns (prev);
8881 0 : delete_related_insns (next);
8882 : }
8883 :
8884 : /* Subfunction of delete_address_reloads: process registers found in X. */
8885 : static void
8886 0 : delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8887 : {
8888 0 : rtx_insn *prev, *i2;
8889 0 : rtx set, dst;
8890 0 : int i, j;
8891 0 : enum rtx_code code = GET_CODE (x);
8892 :
8893 0 : if (code != REG)
8894 : {
8895 0 : const char *fmt = GET_RTX_FORMAT (code);
8896 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8897 : {
8898 0 : if (fmt[i] == 'e')
8899 0 : delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8900 0 : else if (fmt[i] == 'E')
8901 : {
8902 0 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8903 0 : delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8904 : current_insn);
8905 : }
8906 : }
8907 : return;
8908 : }
8909 :
8910 0 : if (spill_reg_order[REGNO (x)] < 0)
8911 : return;
8912 :
8913 : /* Scan backwards for the insn that sets x. This might be a way back due
8914 : to inheritance. */
8915 0 : for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8916 : {
8917 0 : code = GET_CODE (prev);
8918 0 : if (code == CODE_LABEL || code == JUMP_INSN)
8919 : return;
8920 0 : if (!INSN_P (prev))
8921 0 : continue;
8922 0 : if (reg_set_p (x, PATTERN (prev)))
8923 : break;
8924 0 : if (reg_referenced_p (x, PATTERN (prev)))
8925 : return;
8926 : }
8927 0 : if (! prev || INSN_UID (prev) < reload_first_uid)
8928 : return;
8929 : /* Check that PREV only sets the reload register. */
8930 0 : set = single_set (prev);
8931 0 : if (! set)
8932 : return;
8933 0 : dst = SET_DEST (set);
8934 0 : if (!REG_P (dst)
8935 0 : || ! rtx_equal_p (dst, x))
8936 0 : return;
8937 0 : if (! reg_set_p (dst, PATTERN (dead_insn)))
8938 : {
8939 : /* Check if DST was used in a later insn -
8940 : it might have been inherited. */
8941 0 : for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8942 : {
8943 0 : if (LABEL_P (i2))
8944 : break;
8945 0 : if (! INSN_P (i2))
8946 0 : continue;
8947 0 : if (reg_referenced_p (dst, PATTERN (i2)))
8948 : {
8949 : /* If there is a reference to the register in the current insn,
8950 : it might be loaded in a non-inherited reload. If no other
8951 : reload uses it, that means the register is set before
8952 : referenced. */
8953 0 : if (i2 == current_insn)
8954 : {
8955 0 : for (j = n_reloads - 1; j >= 0; j--)
8956 0 : if ((rld[j].reg_rtx == dst && reload_inherited[j])
8957 0 : || reload_override_in[j] == dst)
8958 : return;
8959 0 : for (j = n_reloads - 1; j >= 0; j--)
8960 0 : if (rld[j].in && rld[j].reg_rtx == dst)
8961 : break;
8962 0 : if (j >= 0)
8963 : break;
8964 : }
8965 : return;
8966 : }
8967 0 : if (JUMP_P (i2))
8968 : break;
8969 : /* If DST is still live at CURRENT_INSN, check if it is used for
8970 : any reload. Note that even if CURRENT_INSN sets DST, we still
8971 : have to check the reloads. */
8972 0 : if (i2 == current_insn)
8973 : {
8974 0 : for (j = n_reloads - 1; j >= 0; j--)
8975 0 : if ((rld[j].reg_rtx == dst && reload_inherited[j])
8976 0 : || reload_override_in[j] == dst)
8977 : return;
8978 : /* ??? We can't finish the loop here, because dst might be
8979 : allocated to a pseudo in this block if no reload in this
8980 : block needs any of the classes containing DST - see
8981 : spill_hard_reg. There is no easy way to tell this, so we
8982 : have to scan till the end of the basic block. */
8983 : }
8984 0 : if (reg_set_p (dst, PATTERN (i2)))
8985 : break;
8986 : }
8987 : }
8988 0 : delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8989 0 : reg_reloaded_contents[REGNO (dst)] = -1;
8990 0 : delete_insn (prev);
8991 : }
8992 :
8993 : /* Output reload-insns to reload VALUE into RELOADREG.
8994 : VALUE is an autoincrement or autodecrement RTX whose operand
8995 : is a register or memory location;
8996 : so reloading involves incrementing that location.
8997 : IN is either identical to VALUE, or some cheaper place to reload from.
8998 :
8999 : INC_AMOUNT is the number to increment or decrement by (always positive).
9000 : This cannot be deduced from VALUE. */
9001 :
9002 : static void
9003 0 : inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
9004 : {
9005 : /* REG or MEM to be copied and incremented. */
9006 0 : rtx incloc = find_replacement (&XEXP (value, 0));
9007 : /* Nonzero if increment after copying. */
9008 0 : int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9009 0 : || GET_CODE (value) == POST_MODIFY);
9010 0 : rtx_insn *last;
9011 0 : rtx inc;
9012 0 : rtx_insn *add_insn;
9013 0 : int code;
9014 0 : rtx real_in = in == value ? incloc : in;
9015 :
9016 : /* No hard register is equivalent to this register after
9017 : inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9018 : we could inc/dec that register as well (maybe even using it for
9019 : the source), but I'm not sure it's worth worrying about. */
9020 0 : if (REG_P (incloc))
9021 0 : reg_last_reload_reg[REGNO (incloc)] = 0;
9022 :
9023 0 : if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9024 : {
9025 0 : gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9026 0 : inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9027 : }
9028 : else
9029 : {
9030 0 : if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9031 0 : inc_amount = -inc_amount;
9032 :
9033 0 : inc = gen_int_mode (inc_amount, Pmode);
9034 : }
9035 :
9036 : /* If this is post-increment, first copy the location to the reload reg. */
9037 0 : if (post && real_in != reloadreg)
9038 0 : emit_insn (gen_move_insn (reloadreg, real_in));
9039 :
9040 0 : if (in == value)
9041 : {
9042 : /* See if we can directly increment INCLOC. Use a method similar to
9043 : that in gen_reload. */
9044 :
9045 0 : last = get_last_insn ();
9046 0 : add_insn = emit_insn (gen_rtx_SET (incloc,
9047 : gen_rtx_PLUS (GET_MODE (incloc),
9048 : incloc, inc)));
9049 :
9050 0 : code = recog_memoized (add_insn);
9051 0 : if (code >= 0)
9052 : {
9053 0 : extract_insn (add_insn);
9054 0 : if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9055 : {
9056 : /* If this is a pre-increment and we have incremented the value
9057 : where it lives, copy the incremented value to RELOADREG to
9058 : be used as an address. */
9059 :
9060 0 : if (! post)
9061 0 : emit_insn (gen_move_insn (reloadreg, incloc));
9062 0 : return;
9063 : }
9064 : }
9065 0 : delete_insns_since (last);
9066 : }
9067 :
9068 : /* If couldn't do the increment directly, must increment in RELOADREG.
9069 : The way we do this depends on whether this is pre- or post-increment.
9070 : For pre-increment, copy INCLOC to the reload register, increment it
9071 : there, then save back. */
9072 :
9073 0 : if (! post)
9074 : {
9075 0 : if (in != reloadreg)
9076 0 : emit_insn (gen_move_insn (reloadreg, real_in));
9077 0 : emit_insn (gen_add2_insn (reloadreg, inc));
9078 0 : emit_insn (gen_move_insn (incloc, reloadreg));
9079 : }
9080 : else
9081 : {
9082 : /* Postincrement.
9083 : Because this might be a jump insn or a compare, and because RELOADREG
9084 : may not be available after the insn in an input reload, we must do
9085 : the incrementation before the insn being reloaded for.
9086 :
9087 : We have already copied IN to RELOADREG. Increment the copy in
9088 : RELOADREG, save that back, then decrement RELOADREG so it has
9089 : the original value. */
9090 :
9091 0 : emit_insn (gen_add2_insn (reloadreg, inc));
9092 0 : emit_insn (gen_move_insn (incloc, reloadreg));
9093 0 : if (CONST_INT_P (inc))
9094 0 : emit_insn (gen_add2_insn (reloadreg,
9095 0 : gen_int_mode (-INTVAL (inc),
9096 0 : GET_MODE (reloadreg))));
9097 : else
9098 0 : emit_insn (gen_sub2_insn (reloadreg, inc));
9099 : }
9100 : }
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