Line data Source code
1 : /* Reload pseudo regs into hard regs for insns that require hard regs.
2 : Copyright (C) 1987-2026 Free Software Foundation, Inc.
3 :
4 : This file is part of GCC.
5 :
6 : GCC is free software; you can redistribute it and/or modify it under
7 : the terms of the GNU General Public License as published by the Free
8 : Software Foundation; either version 3, or (at your option) any later
9 : version.
10 :
11 : GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 : WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 : FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 : for more details.
15 :
16 : You should have received a copy of the GNU General Public License
17 : along with GCC; see the file COPYING3. If not see
18 : <http://www.gnu.org/licenses/>. */
19 :
20 : #include "config.h"
21 : #include "system.h"
22 : #include "coretypes.h"
23 : #include "backend.h"
24 : #include "target.h"
25 : #include "rtl.h"
26 : #include "tree.h"
27 : #include "predict.h"
28 : #include "df.h"
29 : #include "memmodel.h"
30 : #include "tm_p.h"
31 : #include "optabs.h"
32 : #include "regs.h"
33 : #include "ira.h"
34 : #include "recog.h"
35 :
36 : #include "rtl-error.h"
37 : #include "expr.h"
38 : #include "addresses.h"
39 : #include "cfgrtl.h"
40 : #include "cfgbuild.h"
41 : #include "reload.h"
42 : #include "except.h"
43 : #include "dumpfile.h"
44 : #include "rtl-iter.h"
45 : #include "function-abi.h"
46 :
47 : /* This file contains the reload pass of the compiler, which is
48 : run after register allocation has been done. It checks that
49 : each insn is valid (operands required to be in registers really
50 : are in registers of the proper class) and fixes up invalid ones
51 : by copying values temporarily into registers for the insns
52 : that need them.
53 :
54 : The results of register allocation are described by the vector
55 : reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 : can be used to find which hard reg, if any, a pseudo reg is in.
57 :
58 : The technique we always use is to free up a few hard regs that are
59 : called ``reload regs'', and for each place where a pseudo reg
60 : must be in a hard reg, copy it temporarily into one of the reload regs.
61 :
62 : Reload regs are allocated locally for every instruction that needs
63 : reloads. When there are pseudos which are allocated to a register that
64 : has been chosen as a reload reg, such pseudos must be ``spilled''.
65 : This means that they go to other hard regs, or to stack slots if no other
66 : available hard regs can be found. Spilling can invalidate more
67 : insns, requiring additional need for reloads, so we must keep checking
68 : until the process stabilizes.
69 :
70 : For machines with different classes of registers, we must keep track
71 : of the register class needed for each reload, and make sure that
72 : we allocate enough reload registers of each class.
73 :
74 : The file reload.cc contains the code that checks one insn for
75 : validity and reports the reloads that it needs. This file
76 : is in charge of scanning the entire rtl code, accumulating the
77 : reload needs, spilling, assigning reload registers to use for
78 : fixing up each insn, and generating the new insns to copy values
79 : into the reload registers. */
80 :
81 : struct target_reload default_target_reload;
82 : #if SWITCHABLE_TARGET
83 : struct target_reload *this_target_reload = &default_target_reload;
84 : #endif
85 :
86 : #define spill_indirect_levels \
87 : (this_target_reload->x_spill_indirect_levels)
88 :
89 : /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 : into which reg N has been reloaded (perhaps for a previous insn). */
91 : static rtx *reg_last_reload_reg;
92 :
93 : /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 : for an output reload that stores into reg N. */
95 : static regset_head reg_has_output_reload;
96 :
97 : /* Indicates which hard regs are reload-registers for an output reload
98 : in the current insn. */
99 : static HARD_REG_SET reg_is_output_reload;
100 :
101 : /* Widest mode in which each pseudo reg is referred to (via subreg). */
102 : static machine_mode *reg_max_ref_mode;
103 :
104 : /* Vector to remember old contents of reg_renumber before spilling. */
105 : static short *reg_old_renumber;
106 :
107 : /* During reload_as_needed, element N contains the last pseudo regno reloaded
108 : into hard register N. If that pseudo reg occupied more than one register,
109 : reg_reloaded_contents points to that pseudo for each spill register in
110 : use; all of these must remain set for an inheritance to occur. */
111 : static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
112 :
113 : /* During reload_as_needed, element N contains the insn for which
114 : hard register N was last used. Its contents are significant only
115 : when reg_reloaded_valid is set for this register. */
116 : static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
117 :
118 : /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
119 : static HARD_REG_SET reg_reloaded_valid;
120 : /* Indicate if the register was dead at the end of the reload.
121 : This is only valid if reg_reloaded_contents is set and valid. */
122 : static HARD_REG_SET reg_reloaded_dead;
123 :
124 : /* Number of spill-regs so far; number of valid elements of spill_regs. */
125 : static int n_spills;
126 :
127 : /* In parallel with spill_regs, contains REG rtx's for those regs.
128 : Holds the last rtx used for any given reg, or 0 if it has never
129 : been used for spilling yet. This rtx is reused, provided it has
130 : the proper mode. */
131 : static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
132 :
133 : /* In parallel with spill_regs, contains nonzero for a spill reg
134 : that was stored after the last time it was used.
135 : The precise value is the insn generated to do the store. */
136 : static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER];
137 :
138 : /* This is the register that was stored with spill_reg_store. This is a
139 : copy of reload_out / reload_out_reg when the value was stored; if
140 : reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
141 : static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
142 :
143 : /* This table is the inverse mapping of spill_regs:
144 : indexed by hard reg number,
145 : it contains the position of that reg in spill_regs,
146 : or -1 for something that is not in spill_regs.
147 :
148 : ?!? This is no longer accurate. */
149 : static short spill_reg_order[FIRST_PSEUDO_REGISTER];
150 :
151 : /* This reg set indicates registers that can't be used as spill registers for
152 : the currently processed insn. These are the hard registers which are live
153 : during the insn, but not allocated to pseudos, as well as fixed
154 : registers. */
155 : static HARD_REG_SET bad_spill_regs;
156 :
157 : /* These are the hard registers that can't be used as spill register for any
158 : insn. This includes registers used for user variables and registers that
159 : we can't eliminate. A register that appears in this set also can't be used
160 : to retry register allocation. */
161 : static HARD_REG_SET bad_spill_regs_global;
162 :
163 : /* Describes order of use of registers for reloading
164 : of spilled pseudo-registers. `n_spills' is the number of
165 : elements that are actually valid; new ones are added at the end.
166 :
167 : Both spill_regs and spill_reg_order are used on two occasions:
168 : once during find_reload_regs, where they keep track of the spill registers
169 : for a single insn, but also during reload_as_needed where they show all
170 : the registers ever used by reload. For the latter case, the information
171 : is calculated during finish_spills. */
172 : static short spill_regs[FIRST_PSEUDO_REGISTER];
173 :
174 : /* This vector of reg sets indicates, for each pseudo, which hard registers
175 : may not be used for retrying global allocation because the register was
176 : formerly spilled from one of them. If we allowed reallocating a pseudo to
177 : a register that it was already allocated to, reload might not
178 : terminate. */
179 : static HARD_REG_SET *pseudo_previous_regs;
180 :
181 : /* This vector of reg sets indicates, for each pseudo, which hard
182 : registers may not be used for retrying global allocation because they
183 : are used as spill registers during one of the insns in which the
184 : pseudo is live. */
185 : static HARD_REG_SET *pseudo_forbidden_regs;
186 :
187 : /* All hard regs that have been used as spill registers for any insn are
188 : marked in this set. */
189 : static HARD_REG_SET used_spill_regs;
190 :
191 : /* Index of last register assigned as a spill register. We allocate in
192 : a round-robin fashion. */
193 : static int last_spill_reg;
194 :
195 : /* Record the stack slot for each spilled hard register. */
196 : static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
197 :
198 : /* Width allocated so far for that stack slot. */
199 : static poly_uint64 spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
200 :
201 : /* Record which pseudos needed to be spilled. */
202 : static regset_head spilled_pseudos;
203 :
204 : /* Record which pseudos changed their allocation in finish_spills. */
205 : static regset_head changed_allocation_pseudos;
206 :
207 : /* Used for communication between order_regs_for_reload and count_pseudo.
208 : Used to avoid counting one pseudo twice. */
209 : static regset_head pseudos_counted;
210 :
211 : /* First uid used by insns created by reload in this function.
212 : Used in find_equiv_reg. */
213 : int reload_first_uid;
214 :
215 : /* Flag set by local-alloc or global-alloc if anything is live in
216 : a call-clobbered reg across calls. */
217 : int caller_save_needed;
218 :
219 : /* Set to 1 while reload_as_needed is operating.
220 : Required by some machines to handle any generated moves differently. */
221 : int reload_in_progress = 0;
222 :
223 : /* This obstack is used for allocation of rtl during register elimination.
224 : The allocated storage can be freed once find_reloads has processed the
225 : insn. */
226 : static struct obstack reload_obstack;
227 :
228 : /* Points to the beginning of the reload_obstack. All insn_chain structures
229 : are allocated first. */
230 : static char *reload_startobj;
231 :
232 : /* The point after all insn_chain structures. Used to quickly deallocate
233 : memory allocated in copy_reloads during calculate_needs_all_insns. */
234 : static char *reload_firstobj;
235 :
236 : /* This points before all local rtl generated by register elimination.
237 : Used to quickly free all memory after processing one insn. */
238 : static char *reload_insn_firstobj;
239 :
240 : /* List of insn_chain instructions, one for every insn that reload needs to
241 : examine. */
242 : class insn_chain *reload_insn_chain;
243 :
244 : /* TRUE if we potentially left dead insns in the insn stream and want to
245 : run DCE immediately after reload, FALSE otherwise. */
246 : static bool need_dce;
247 :
248 : /* List of all insns needing reloads. */
249 : static class insn_chain *insns_need_reload;
250 :
251 : /* This structure is used to record information about register eliminations.
252 : Each array entry describes one possible way of eliminating a register
253 : in favor of another. If there is more than one way of eliminating a
254 : particular register, the most preferred should be specified first. */
255 :
256 : struct elim_table
257 : {
258 : int from; /* Register number to be eliminated. */
259 : int to; /* Register number used as replacement. */
260 : poly_int64 initial_offset; /* Initial difference between values. */
261 : int can_eliminate; /* Nonzero if this elimination can be done. */
262 : int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
263 : target hook in previous scan over insns
264 : made by reload. */
265 : poly_int64 offset; /* Current offset between the two regs. */
266 : poly_int64 previous_offset; /* Offset at end of previous insn. */
267 : int ref_outside_mem; /* "to" has been referenced outside a MEM. */
268 : rtx from_rtx; /* REG rtx for the register to be eliminated.
269 : We cannot simply compare the number since
270 : we might then spuriously replace a hard
271 : register corresponding to a pseudo
272 : assigned to the reg to be eliminated. */
273 : rtx to_rtx; /* REG rtx for the replacement. */
274 : };
275 :
276 : static struct elim_table *reg_eliminate = 0;
277 :
278 : /* This is an intermediate structure to initialize the table. It has
279 : exactly the members provided by ELIMINABLE_REGS. */
280 : static const struct elim_table_1
281 : {
282 : const int from;
283 : const int to;
284 : } reg_eliminate_1[] =
285 :
286 : /* Reload and LRA don't agree on how a multi-register frame pointer
287 : is represented for elimination. See avr.h for a use case. */
288 : #ifdef RELOAD_ELIMINABLE_REGS
289 : RELOAD_ELIMINABLE_REGS;
290 : #else
291 : ELIMINABLE_REGS;
292 : #endif
293 :
294 : #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
295 :
296 : /* Record the number of pending eliminations that have an offset not equal
297 : to their initial offset. If nonzero, we use a new copy of each
298 : replacement result in any insns encountered. */
299 : int num_not_at_initial_offset;
300 :
301 : /* Count the number of registers that we may be able to eliminate. */
302 : static int num_eliminable;
303 : /* And the number of registers that are equivalent to a constant that
304 : can be eliminated to frame_pointer / arg_pointer + constant. */
305 : static int num_eliminable_invariants;
306 :
307 : /* For each label, we record the offset of each elimination. If we reach
308 : a label by more than one path and an offset differs, we cannot do the
309 : elimination. This information is indexed by the difference of the
310 : number of the label and the first label number. We can't offset the
311 : pointer itself as this can cause problems on machines with segmented
312 : memory. The first table is an array of flags that records whether we
313 : have yet encountered a label and the second table is an array of arrays,
314 : one entry in the latter array for each elimination. */
315 :
316 : static int first_label_num;
317 : static char *offsets_known_at;
318 : static poly_int64 (*offsets_at)[NUM_ELIMINABLE_REGS];
319 :
320 : vec<reg_equivs_t, va_gc> *reg_equivs;
321 :
322 : /* Stack of addresses where an rtx has been changed. We can undo the
323 : changes by popping items off the stack and restoring the original
324 : value at each location.
325 :
326 : We use this simplistic undo capability rather than copy_rtx as copy_rtx
327 : will not make a deep copy of a normally sharable rtx, such as
328 : (const (plus (symbol_ref) (const_int))). If such an expression appears
329 : as R1 in gen_reload_chain_without_interm_reg_p, then a shared
330 : rtx expression would be changed. See PR 42431. */
331 :
332 : typedef rtx *rtx_p;
333 : static vec<rtx_p> substitute_stack;
334 :
335 : /* Number of labels in the current function. */
336 :
337 : static int num_labels;
338 :
339 : static void replace_pseudos_in (rtx *, machine_mode, rtx);
340 : static void maybe_fix_stack_asms (void);
341 : static void copy_reloads (class insn_chain *);
342 : static void calculate_needs_all_insns (int);
343 : static int find_reg (class insn_chain *, int);
344 : static void find_reload_regs (class insn_chain *);
345 : static void select_reload_regs (void);
346 : static void delete_caller_save_insns (void);
347 :
348 : static void spill_failure (rtx_insn *, enum reg_class);
349 : static void count_spilled_pseudo (int, int, int);
350 : static void delete_dead_insn (rtx_insn *);
351 : static void alter_reg (int, int, bool);
352 : static void set_label_offsets (rtx, rtx_insn *, int);
353 : static void check_eliminable_occurrences (rtx);
354 : static void elimination_effects (rtx, machine_mode);
355 : static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool);
356 : static int eliminate_regs_in_insn (rtx_insn *, int);
357 : static void update_eliminable_offsets (void);
358 : static void mark_not_eliminable (rtx, const_rtx, void *);
359 : static void set_initial_elim_offsets (void);
360 : static bool verify_initial_elim_offsets (void);
361 : static void set_initial_label_offsets (void);
362 : static void set_offsets_for_label (rtx_insn *);
363 : static void init_eliminable_invariants (rtx_insn *, bool);
364 : static void init_elim_table (void);
365 : static void free_reg_equiv (void);
366 : static void update_eliminables (HARD_REG_SET *);
367 : static bool update_eliminables_and_spill (void);
368 : static void elimination_costs_in_insn (rtx_insn *);
369 : static void spill_hard_reg (unsigned int, int);
370 : static int finish_spills (int);
371 : static void scan_paradoxical_subregs (rtx);
372 : static void count_pseudo (int);
373 : static void order_regs_for_reload (class insn_chain *);
374 : static void reload_as_needed (int);
375 : static void forget_old_reloads_1 (rtx, const_rtx, void *);
376 : static void forget_marked_reloads (regset);
377 : static int reload_reg_class_lower (const void *, const void *);
378 : static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
379 : machine_mode);
380 : static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
381 : machine_mode);
382 : static int reload_reg_free_p (unsigned int, int, enum reload_type);
383 : static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
384 : rtx, rtx, int, int);
385 : static int free_for_value_p (int, machine_mode, int, enum reload_type,
386 : rtx, rtx, int, int);
387 : static int allocate_reload_reg (class insn_chain *, int, int);
388 : static int conflicts_with_override (rtx);
389 : static void failed_reload (rtx_insn *, int);
390 : static int set_reload_reg (int, int);
391 : static void choose_reload_regs_init (class insn_chain *, rtx *);
392 : static void choose_reload_regs (class insn_chain *);
393 : static void emit_input_reload_insns (class insn_chain *, struct reload *,
394 : rtx, int);
395 : static void emit_output_reload_insns (class insn_chain *, struct reload *,
396 : int);
397 : static void do_input_reload (class insn_chain *, struct reload *, int);
398 : static void do_output_reload (class insn_chain *, struct reload *, int);
399 : static void emit_reload_insns (class insn_chain *);
400 : static void delete_output_reload (rtx_insn *, int, int, rtx);
401 : static void delete_address_reloads (rtx_insn *, rtx_insn *);
402 : static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *);
403 : static void inc_for_reload (rtx, rtx, rtx, poly_int64);
404 : static void substitute (rtx *, const_rtx, rtx);
405 : static bool gen_reload_chain_without_interm_reg_p (int, int);
406 : static int reloads_conflict (int, int);
407 : static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type);
408 : static rtx_insn *emit_insn_if_valid_for_reload (rtx);
409 :
410 : /* Initialize the reload pass. This is called at the beginning of compilation
411 : and may be called again if the target is reinitialized. */
412 :
413 : void
414 0 : init_reload (void)
415 : {
416 0 : int i;
417 :
418 : /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
419 : Set spill_indirect_levels to the number of levels such addressing is
420 : permitted, zero if it is not permitted at all. */
421 :
422 0 : rtx tem
423 0 : = gen_rtx_MEM (Pmode,
424 0 : gen_rtx_PLUS (Pmode,
425 : gen_rtx_REG (Pmode,
426 : LAST_VIRTUAL_REGISTER + 1),
427 : gen_int_mode (4, Pmode)));
428 0 : spill_indirect_levels = 0;
429 :
430 0 : while (memory_address_p (QImode, tem))
431 : {
432 0 : spill_indirect_levels++;
433 0 : tem = gen_rtx_MEM (Pmode, tem);
434 : }
435 :
436 : /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 :
438 0 : tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
439 0 : indirect_symref_ok = memory_address_p (QImode, tem);
440 :
441 : /* See if reg+reg is a valid (and offsettable) address. */
442 :
443 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
444 : {
445 0 : tem = gen_rtx_PLUS (Pmode,
446 : gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
447 : gen_rtx_REG (Pmode, i));
448 :
449 : /* This way, we make sure that reg+reg is an offsettable address. */
450 0 : tem = plus_constant (Pmode, tem, 4);
451 :
452 0 : for (int mode = 0; mode < MAX_MACHINE_MODE; mode++)
453 0 : if (!double_reg_address_ok[mode]
454 0 : && memory_address_p ((enum machine_mode)mode, tem))
455 0 : double_reg_address_ok[mode] = 1;
456 : }
457 :
458 : /* Initialize obstack for our rtl allocation. */
459 0 : if (reload_startobj == NULL)
460 : {
461 0 : gcc_obstack_init (&reload_obstack);
462 0 : reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
463 : }
464 :
465 0 : INIT_REG_SET (&spilled_pseudos);
466 0 : INIT_REG_SET (&changed_allocation_pseudos);
467 0 : INIT_REG_SET (&pseudos_counted);
468 0 : }
469 :
470 : /* List of insn chains that are currently unused. */
471 : static class insn_chain *unused_insn_chains = 0;
472 :
473 : /* Allocate an empty insn_chain structure. */
474 : class insn_chain *
475 0 : new_insn_chain (void)
476 : {
477 0 : class insn_chain *c;
478 :
479 0 : if (unused_insn_chains == 0)
480 : {
481 0 : c = XOBNEW (&reload_obstack, class insn_chain);
482 0 : INIT_REG_SET (&c->live_throughout);
483 0 : INIT_REG_SET (&c->dead_or_set);
484 : }
485 : else
486 : {
487 0 : c = unused_insn_chains;
488 0 : unused_insn_chains = c->next;
489 : }
490 0 : c->is_caller_save_insn = 0;
491 0 : c->need_operand_change = 0;
492 0 : c->need_reload = 0;
493 0 : c->need_elim = 0;
494 0 : return c;
495 : }
496 :
497 : /* Small utility function to set all regs in hard reg set TO which are
498 : allocated to pseudos in regset FROM. */
499 :
500 : void
501 5551707 : compute_use_by_pseudos (HARD_REG_SET *to, regset from)
502 : {
503 5551707 : unsigned int regno;
504 5551707 : reg_set_iterator rsi;
505 :
506 5551707 : EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
507 : {
508 0 : int r = reg_renumber[regno];
509 :
510 0 : if (r < 0)
511 : {
512 : /* reload_combine uses the information from DF_LIVE_IN,
513 : which might still contain registers that have not
514 : actually been allocated since they have an
515 : equivalence. */
516 0 : gcc_assert (ira_conflicts_p || reload_completed);
517 : }
518 : else
519 0 : add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
520 : }
521 5551707 : }
522 :
523 : /* Replace all pseudos found in LOC with their corresponding
524 : equivalences. */
525 :
526 : static void
527 0 : replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage)
528 : {
529 0 : rtx x = *loc;
530 0 : enum rtx_code code;
531 0 : const char *fmt;
532 0 : int i, j;
533 :
534 0 : if (! x)
535 : return;
536 :
537 0 : code = GET_CODE (x);
538 0 : if (code == REG)
539 : {
540 0 : unsigned int regno = REGNO (x);
541 :
542 0 : if (regno < FIRST_PSEUDO_REGISTER)
543 : return;
544 :
545 0 : x = eliminate_regs_1 (x, mem_mode, usage, true, false);
546 0 : if (x != *loc)
547 : {
548 0 : *loc = x;
549 0 : replace_pseudos_in (loc, mem_mode, usage);
550 0 : return;
551 : }
552 :
553 0 : if (reg_equiv_constant (regno))
554 0 : *loc = reg_equiv_constant (regno);
555 0 : else if (reg_equiv_invariant (regno))
556 0 : *loc = reg_equiv_invariant (regno);
557 0 : else if (reg_equiv_mem (regno))
558 0 : *loc = reg_equiv_mem (regno);
559 0 : else if (reg_equiv_address (regno))
560 0 : *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
561 : else
562 : {
563 0 : gcc_assert (!REG_P (regno_reg_rtx[regno])
564 : || REGNO (regno_reg_rtx[regno]) != regno);
565 0 : *loc = regno_reg_rtx[regno];
566 : }
567 :
568 : return;
569 : }
570 0 : else if (code == MEM)
571 : {
572 0 : replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
573 0 : return;
574 : }
575 :
576 : /* Process each of our operands recursively. */
577 0 : fmt = GET_RTX_FORMAT (code);
578 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
579 0 : if (*fmt == 'e')
580 0 : replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
581 0 : else if (*fmt == 'E')
582 0 : for (j = 0; j < XVECLEN (x, i); j++)
583 0 : replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
584 : }
585 :
586 : /* Determine if the current function has an exception receiver block
587 : that reaches the exit block via non-exceptional edges */
588 :
589 : static bool
590 0 : has_nonexceptional_receiver (void)
591 : {
592 0 : edge e;
593 0 : edge_iterator ei;
594 0 : basic_block *tos, *worklist, bb;
595 :
596 : /* If we're not optimizing, then just err on the safe side. */
597 0 : if (!optimize)
598 : return true;
599 :
600 : /* First determine which blocks can reach exit via normal paths. */
601 0 : tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
602 :
603 0 : FOR_EACH_BB_FN (bb, cfun)
604 0 : bb->flags &= ~BB_REACHABLE;
605 :
606 : /* Place the exit block on our worklist. */
607 0 : EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
608 0 : *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
609 :
610 : /* Iterate: find everything reachable from what we've already seen. */
611 0 : while (tos != worklist)
612 : {
613 0 : bb = *--tos;
614 :
615 0 : FOR_EACH_EDGE (e, ei, bb->preds)
616 0 : if (!(e->flags & EDGE_ABNORMAL))
617 : {
618 0 : basic_block src = e->src;
619 :
620 0 : if (!(src->flags & BB_REACHABLE))
621 : {
622 0 : src->flags |= BB_REACHABLE;
623 0 : *tos++ = src;
624 : }
625 : }
626 : }
627 0 : free (worklist);
628 :
629 : /* Now see if there's a reachable block with an exceptional incoming
630 : edge. */
631 0 : FOR_EACH_BB_FN (bb, cfun)
632 0 : if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
633 : return true;
634 :
635 : /* No exceptional block reached exit unexceptionally. */
636 : return false;
637 : }
638 :
639 : /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
640 : zero elements) to MAX_REG_NUM elements.
641 :
642 : Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 : void
644 2877729 : grow_reg_equivs (void)
645 : {
646 2877729 : int old_size = vec_safe_length (reg_equivs);
647 2877729 : int max_regno = max_reg_num ();
648 2877729 : int i;
649 2877729 : reg_equivs_t ze;
650 :
651 2877729 : memset (&ze, 0, sizeof (reg_equivs_t));
652 2877729 : vec_safe_reserve (reg_equivs, max_regno);
653 217379901 : for (i = old_size; i < max_regno; i++)
654 211624443 : reg_equivs->quick_insert (i, ze);
655 2877729 : }
656 :
657 :
658 : /* Global variables used by reload and its subroutines. */
659 :
660 : /* The current basic block while in calculate_elim_costs_all_insns. */
661 : static basic_block elim_bb;
662 :
663 : /* Set during calculate_needs if an insn needs register elimination. */
664 : static int something_needs_elimination;
665 : /* Set during calculate_needs if an insn needs an operand changed. */
666 : static int something_needs_operands_changed;
667 : /* Set by alter_regs if we spilled a register to the stack. */
668 : static bool something_was_spilled;
669 :
670 : /* Nonzero means we couldn't get enough spill regs. */
671 : static int failure;
672 :
673 : /* Temporary array of pseudo-register number. */
674 : static int *temp_pseudo_reg_arr;
675 :
676 : /* If a pseudo has no hard reg, delete the insns that made the equivalence.
677 : If that insn didn't set the register (i.e., it copied the register to
678 : memory), just delete that insn instead of the equivalencing insn plus
679 : anything now dead. If we call delete_dead_insn on that insn, we may
680 : delete the insn that actually sets the register if the register dies
681 : there and that is incorrect. */
682 : static void
683 0 : remove_init_insns ()
684 : {
685 0 : for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 : {
687 0 : if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
688 : {
689 : rtx list;
690 0 : for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
691 : {
692 0 : rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0));
693 :
694 : /* If we already deleted the insn or if it may trap, we can't
695 : delete it. The latter case shouldn't happen, but can
696 : if an insn has a variable address, gets a REG_EH_REGION
697 : note added to it, and then gets converted into a load
698 : from a constant address. */
699 0 : if (NOTE_P (equiv_insn)
700 0 : || can_throw_internal (equiv_insn))
701 : ;
702 0 : else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
703 0 : delete_dead_insn (equiv_insn);
704 : else
705 0 : SET_INSN_DELETED (equiv_insn);
706 : }
707 : }
708 : }
709 0 : }
710 :
711 : /* Return true if remove_init_insns will delete INSN. */
712 : static bool
713 0 : will_delete_init_insn_p (rtx_insn *insn)
714 : {
715 0 : rtx set = single_set (insn);
716 0 : if (!set || !REG_P (SET_DEST (set)))
717 : return false;
718 0 : unsigned regno = REGNO (SET_DEST (set));
719 :
720 0 : if (can_throw_internal (insn))
721 : return false;
722 :
723 0 : if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
724 : return false;
725 :
726 0 : for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1))
727 : {
728 0 : rtx equiv_insn = XEXP (list, 0);
729 0 : if (equiv_insn == insn)
730 : return true;
731 : }
732 : return false;
733 : }
734 :
735 : /* Main entry point for the reload pass.
736 :
737 : FIRST is the first insn of the function being compiled.
738 :
739 : GLOBAL nonzero means we were called from global_alloc
740 : and should attempt to reallocate any pseudoregs that we
741 : displace from hard regs we will use for reloads.
742 : If GLOBAL is zero, we do not have enough information to do that,
743 : so any pseudo reg that is spilled must go to the stack.
744 :
745 : Return value is TRUE if reload likely left dead insns in the
746 : stream and a DCE pass should be run to eliminate them. Else the
747 : return value is FALSE. */
748 :
749 : bool
750 0 : reload (rtx_insn *first, int global)
751 : {
752 0 : int i, n;
753 0 : rtx_insn *insn;
754 0 : struct elim_table *ep;
755 0 : basic_block bb;
756 0 : bool inserted;
757 :
758 : /* Make sure even insns with volatile mem refs are recognizable. */
759 0 : init_recog ();
760 :
761 0 : failure = 0;
762 :
763 0 : reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
764 :
765 : /* Make sure that the last insn in the chain
766 : is not something that needs reloading. */
767 0 : emit_note (NOTE_INSN_DELETED);
768 :
769 : /* Enable find_equiv_reg to distinguish insns made by reload. */
770 0 : reload_first_uid = get_max_uid ();
771 :
772 : /* Initialize the secondary memory table. */
773 0 : clear_secondary_mem ();
774 :
775 : /* We don't have a stack slot for any spill reg yet. */
776 0 : memset (spill_stack_slot, 0, sizeof spill_stack_slot);
777 0 : memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
778 :
779 : /* Initialize the save area information for caller-save, in case some
780 : are needed. */
781 0 : init_save_areas ();
782 :
783 : /* Compute which hard registers are now in use
784 : as homes for pseudo registers.
785 : This is done here rather than (eg) in global_alloc
786 : because this point is reached even if not optimizing. */
787 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
788 0 : mark_home_live (i);
789 :
790 : /* A function that has a nonlocal label that can reach the exit
791 : block via non-exceptional paths must save all call-saved
792 : registers. */
793 0 : if (cfun->has_nonlocal_label
794 0 : && has_nonexceptional_receiver ())
795 0 : crtl->saves_all_registers = 1;
796 :
797 0 : if (crtl->saves_all_registers)
798 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
799 0 : if (! crtl->abi->clobbers_full_reg_p (i)
800 0 : && ! fixed_regs[i]
801 0 : && ! LOCAL_REGNO (i))
802 0 : df_set_regs_ever_live (i, true);
803 :
804 : /* Find all the pseudo registers that didn't get hard regs
805 : but do have known equivalent constants or memory slots.
806 : These include parameters (known equivalent to parameter slots)
807 : and cse'd or loop-moved constant memory addresses.
808 :
809 : Record constant equivalents in reg_equiv_constant
810 : so they will be substituted by find_reloads.
811 : Record memory equivalents in reg_mem_equiv so they can
812 : be substituted eventually by altering the REG-rtx's. */
813 :
814 0 : grow_reg_equivs ();
815 0 : reg_old_renumber = XCNEWVEC (short, max_regno);
816 0 : memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
817 0 : pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
818 0 : pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
819 :
820 0 : CLEAR_HARD_REG_SET (bad_spill_regs_global);
821 :
822 0 : init_eliminable_invariants (first, true);
823 0 : init_elim_table ();
824 :
825 : /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
826 : stack slots to the pseudos that lack hard regs or equivalents.
827 : Do not touch virtual registers. */
828 :
829 0 : temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
830 0 : for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 0 : temp_pseudo_reg_arr[n++] = i;
832 :
833 0 : if (ira_conflicts_p)
834 : /* Ask IRA to order pseudo-registers for better stack slot
835 : sharing. */
836 0 : ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode);
837 :
838 0 : for (i = 0; i < n; i++)
839 0 : alter_reg (temp_pseudo_reg_arr[i], -1, false);
840 :
841 : /* If we have some registers we think can be eliminated, scan all insns to
842 : see if there is an insn that sets one of these registers to something
843 : other than itself plus a constant. If so, the register cannot be
844 : eliminated. Doing this scan here eliminates an extra pass through the
845 : main reload loop in the most common case where register elimination
846 : cannot be done. */
847 0 : for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
848 0 : if (INSN_P (insn))
849 0 : note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULL);
850 :
851 0 : maybe_fix_stack_asms ();
852 :
853 0 : insns_need_reload = 0;
854 0 : something_needs_elimination = 0;
855 :
856 : /* Initialize to -1, which means take the first spill register. */
857 0 : last_spill_reg = -1;
858 :
859 : /* Spill any hard regs that we know we can't eliminate. */
860 0 : CLEAR_HARD_REG_SET (used_spill_regs);
861 : /* There can be multiple ways to eliminate a register;
862 : they should be listed adjacently.
863 : Elimination for any register fails only if all possible ways fail. */
864 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
865 : {
866 0 : int from = ep->from;
867 0 : int can_eliminate = 0;
868 0 : do
869 : {
870 0 : can_eliminate |= ep->can_eliminate;
871 0 : ep++;
872 : }
873 0 : while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
874 0 : if (! can_eliminate)
875 0 : spill_hard_reg (from, 1);
876 : }
877 :
878 0 : if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed)
879 0 : spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
880 :
881 0 : finish_spills (global);
882 :
883 : /* From now on, we may need to generate moves differently. We may also
884 : allow modifications of insns which cause them to not be recognized.
885 : Any such modifications will be cleaned up during reload itself. */
886 0 : reload_in_progress = 1;
887 :
888 : /* This loop scans the entire function each go-round
889 : and repeats until one repetition spills no additional hard regs. */
890 0 : for (;;)
891 : {
892 0 : int something_changed;
893 0 : poly_int64 starting_frame_size;
894 :
895 0 : starting_frame_size = get_frame_size ();
896 0 : something_was_spilled = false;
897 :
898 0 : set_initial_elim_offsets ();
899 0 : set_initial_label_offsets ();
900 :
901 : /* For each pseudo register that has an equivalent location defined,
902 : try to eliminate any eliminable registers (such as the frame pointer)
903 : assuming initial offsets for the replacement register, which
904 : is the normal case.
905 :
906 : If the resulting location is directly addressable, substitute
907 : the MEM we just got directly for the old REG.
908 :
909 : If it is not addressable but is a constant or the sum of a hard reg
910 : and constant, it is probably not addressable because the constant is
911 : out of range, in that case record the address; we will generate
912 : hairy code to compute the address in a register each time it is
913 : needed. Similarly if it is a hard register, but one that is not
914 : valid as an address register.
915 :
916 : If the location is not addressable, but does not have one of the
917 : above forms, assign a stack slot. We have to do this to avoid the
918 : potential of producing lots of reloads if, e.g., a location involves
919 : a pseudo that didn't get a hard register and has an equivalent memory
920 : location that also involves a pseudo that didn't get a hard register.
921 :
922 : Perhaps at some point we will improve reload_when_needed handling
923 : so this problem goes away. But that's very hairy. */
924 :
925 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
926 0 : if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
927 : {
928 0 : rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
929 : NULL_RTX);
930 :
931 0 : if (strict_memory_address_addr_space_p
932 0 : (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
933 0 : MEM_ADDR_SPACE (x)))
934 0 : reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
935 0 : else if (CONSTANT_P (XEXP (x, 0))
936 0 : || (REG_P (XEXP (x, 0))
937 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
938 0 : || (GET_CODE (XEXP (x, 0)) == PLUS
939 0 : && REG_P (XEXP (XEXP (x, 0), 0))
940 0 : && (REGNO (XEXP (XEXP (x, 0), 0))
941 : < FIRST_PSEUDO_REGISTER)
942 0 : && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
943 0 : reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
944 : else
945 : {
946 : /* Make a new stack slot. Then indicate that something
947 : changed so we go back and recompute offsets for
948 : eliminable registers because the allocation of memory
949 : below might change some offset. reg_equiv_{mem,address}
950 : will be set up for this pseudo on the next pass around
951 : the loop. */
952 0 : reg_equiv_memory_loc (i) = 0;
953 0 : reg_equiv_init (i) = 0;
954 0 : alter_reg (i, -1, true);
955 : }
956 : }
957 :
958 0 : if (caller_save_needed)
959 0 : setup_save_areas ();
960 :
961 0 : if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed)
962 : {
963 : /* If we have a stack frame, we must align it now. The
964 : stack size may be a part of the offset computation for
965 : register elimination. So if this changes the stack size,
966 : then repeat the elimination bookkeeping. We don't
967 : realign when there is no stack, as that will cause a
968 : stack frame when none is needed should
969 : TARGET_STARTING_FRAME_OFFSET not be already aligned to
970 : STACK_BOUNDARY. */
971 0 : assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
972 : }
973 : /* If we allocated another stack slot, redo elimination bookkeeping. */
974 0 : if (something_was_spilled
975 0 : || maybe_ne (starting_frame_size, get_frame_size ()))
976 : {
977 0 : if (update_eliminables_and_spill ())
978 0 : finish_spills (0);
979 0 : continue;
980 : }
981 :
982 0 : if (caller_save_needed)
983 : {
984 0 : save_call_clobbered_regs ();
985 : /* That might have allocated new insn_chain structures. */
986 0 : reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
987 : }
988 :
989 0 : calculate_needs_all_insns (global);
990 :
991 0 : if (! ira_conflicts_p)
992 : /* Don't do it for IRA. We need this info because we don't
993 : change live_throughout and dead_or_set for chains when IRA
994 : is used. */
995 0 : CLEAR_REG_SET (&spilled_pseudos);
996 :
997 0 : something_changed = 0;
998 :
999 : /* If we allocated any new memory locations, make another pass
1000 : since it might have changed elimination offsets. */
1001 0 : if (something_was_spilled
1002 0 : || maybe_ne (starting_frame_size, get_frame_size ()))
1003 : something_changed = 1;
1004 :
1005 : /* Even if the frame size remained the same, we might still have
1006 : changed elimination offsets, e.g. if find_reloads called
1007 : force_const_mem requiring the back end to allocate a constant
1008 : pool base register that needs to be saved on the stack. */
1009 0 : else if (!verify_initial_elim_offsets ())
1010 0 : something_changed = 1;
1011 :
1012 0 : if (update_eliminables_and_spill ())
1013 : {
1014 0 : finish_spills (0);
1015 0 : something_changed = 1;
1016 : }
1017 : else
1018 : {
1019 0 : select_reload_regs ();
1020 0 : if (failure)
1021 0 : goto failed;
1022 0 : if (insns_need_reload)
1023 0 : something_changed |= finish_spills (global);
1024 : }
1025 :
1026 0 : if (! something_changed)
1027 : break;
1028 :
1029 0 : if (caller_save_needed)
1030 0 : delete_caller_save_insns ();
1031 :
1032 0 : obstack_free (&reload_obstack, reload_firstobj);
1033 : }
1034 :
1035 : /* If global-alloc was run, notify it of any register eliminations we have
1036 : done. */
1037 0 : if (global)
1038 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 0 : if (ep->can_eliminate)
1040 0 : mark_elimination (ep->from, ep->to);
1041 :
1042 0 : remove_init_insns ();
1043 :
1044 : /* Use the reload registers where necessary
1045 : by generating move instructions to move the must-be-register
1046 : values into or out of the reload registers. */
1047 :
1048 0 : if (insns_need_reload != 0 || something_needs_elimination
1049 0 : || something_needs_operands_changed)
1050 : {
1051 0 : poly_int64 old_frame_size = get_frame_size ();
1052 :
1053 0 : reload_as_needed (global);
1054 :
1055 0 : gcc_assert (known_eq (old_frame_size, get_frame_size ()));
1056 :
1057 0 : gcc_assert (verify_initial_elim_offsets ());
1058 : }
1059 :
1060 : /* If we were able to eliminate the frame pointer, show that it is no
1061 : longer live at the start of any basic block. If it ls live by
1062 : virtue of being in a pseudo, that pseudo will be marked live
1063 : and hence the frame pointer will be known to be live via that
1064 : pseudo. */
1065 :
1066 0 : if (! frame_pointer_needed)
1067 0 : FOR_EACH_BB_FN (bb, cfun)
1068 0 : bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1069 :
1070 : /* Come here (with failure set nonzero) if we can't get enough spill
1071 : regs. */
1072 0 : failed:
1073 :
1074 0 : CLEAR_REG_SET (&changed_allocation_pseudos);
1075 0 : CLEAR_REG_SET (&spilled_pseudos);
1076 0 : reload_in_progress = 0;
1077 :
1078 : /* Now eliminate all pseudo regs by modifying them into
1079 : their equivalent memory references.
1080 : The REG-rtx's for the pseudos are modified in place,
1081 : so all insns that used to refer to them now refer to memory.
1082 :
1083 : For a reg that has a reg_equiv_address, all those insns
1084 : were changed by reloading so that no insns refer to it any longer;
1085 : but the DECL_RTL of a variable decl may refer to it,
1086 : and if so this causes the debugging info to mention the variable. */
1087 :
1088 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1089 : {
1090 0 : rtx addr = 0;
1091 :
1092 0 : if (reg_equiv_mem (i))
1093 0 : addr = XEXP (reg_equiv_mem (i), 0);
1094 :
1095 0 : if (reg_equiv_address (i))
1096 0 : addr = reg_equiv_address (i);
1097 :
1098 0 : if (addr)
1099 : {
1100 0 : if (reg_renumber[i] < 0)
1101 : {
1102 0 : rtx reg = regno_reg_rtx[i];
1103 :
1104 0 : REG_USERVAR_P (reg) = 0;
1105 0 : PUT_CODE (reg, MEM);
1106 0 : XEXP (reg, 0) = addr;
1107 0 : if (reg_equiv_memory_loc (i))
1108 0 : MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1109 : else
1110 0 : MEM_ATTRS (reg) = 0;
1111 0 : MEM_NOTRAP_P (reg) = 1;
1112 : }
1113 0 : else if (reg_equiv_mem (i))
1114 0 : XEXP (reg_equiv_mem (i), 0) = addr;
1115 : }
1116 :
1117 : /* We don't want complex addressing modes in debug insns
1118 : if simpler ones will do, so delegitimize equivalences
1119 : in debug insns. */
1120 0 : if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0)
1121 : {
1122 0 : rtx reg = regno_reg_rtx[i];
1123 0 : rtx equiv = 0;
1124 0 : df_ref use, next;
1125 :
1126 0 : if (reg_equiv_constant (i))
1127 : equiv = reg_equiv_constant (i);
1128 0 : else if (reg_equiv_invariant (i))
1129 : equiv = reg_equiv_invariant (i);
1130 0 : else if (reg && MEM_P (reg))
1131 0 : equiv = targetm.delegitimize_address (reg);
1132 0 : else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1133 : equiv = reg;
1134 :
1135 0 : if (equiv == reg)
1136 0 : continue;
1137 :
1138 0 : for (use = DF_REG_USE_CHAIN (i); use; use = next)
1139 : {
1140 0 : insn = DF_REF_INSN (use);
1141 :
1142 : /* Make sure the next ref is for a different instruction,
1143 : so that we're not affected by the rescan. */
1144 0 : next = DF_REF_NEXT_REG (use);
1145 0 : while (next && DF_REF_INSN (next) == insn)
1146 0 : next = DF_REF_NEXT_REG (next);
1147 :
1148 0 : if (DEBUG_BIND_INSN_P (insn))
1149 : {
1150 0 : if (!equiv)
1151 : {
1152 0 : INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1153 0 : df_insn_rescan_debug_internal (insn);
1154 : }
1155 : else
1156 0 : INSN_VAR_LOCATION_LOC (insn)
1157 0 : = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1158 : reg, equiv);
1159 : }
1160 : }
1161 : }
1162 : }
1163 :
1164 : /* We must set reload_completed now since the cleanup_subreg_operands call
1165 : below will re-recognize each insn and reload may have generated insns
1166 : which are only valid during and after reload. */
1167 0 : reload_completed = 1;
1168 :
1169 : /* Make a pass over all the insns and delete all USEs which we inserted
1170 : only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1171 : notes. Delete all CLOBBER insns, except those that refer to the return
1172 : value and the special mem:BLK CLOBBERs added to prevent the scheduler
1173 : from misarranging variable-array code, and simplify (subreg (reg))
1174 : operands. Strip and regenerate REG_INC notes that may have been moved
1175 : around. */
1176 :
1177 0 : for (insn = first; insn; insn = NEXT_INSN (insn))
1178 0 : if (INSN_P (insn))
1179 : {
1180 0 : rtx *pnote;
1181 :
1182 0 : if (CALL_P (insn))
1183 0 : replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1184 : VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1185 :
1186 0 : if ((GET_CODE (PATTERN (insn)) == USE
1187 : /* We mark with QImode USEs introduced by reload itself. */
1188 0 : && (GET_MODE (insn) == QImode
1189 0 : || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1190 0 : || (GET_CODE (PATTERN (insn)) == CLOBBER
1191 0 : && (!MEM_P (XEXP (PATTERN (insn), 0))
1192 0 : || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1193 0 : || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1194 0 : && XEXP (XEXP (PATTERN (insn), 0), 0)
1195 0 : != stack_pointer_rtx))
1196 0 : && (!REG_P (XEXP (PATTERN (insn), 0))
1197 0 : || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1198 : {
1199 0 : delete_insn (insn);
1200 0 : continue;
1201 : }
1202 :
1203 : /* Some CLOBBERs may survive until here and still reference unassigned
1204 : pseudos with const equivalent, which may in turn cause ICE in later
1205 : passes if the reference remains in place. */
1206 0 : if (GET_CODE (PATTERN (insn)) == CLOBBER)
1207 0 : replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1208 0 : VOIDmode, PATTERN (insn));
1209 :
1210 : /* Discard obvious no-ops, even without -O. This optimization
1211 : is fast and doesn't interfere with debugging. */
1212 0 : if (NONJUMP_INSN_P (insn)
1213 0 : && GET_CODE (PATTERN (insn)) == SET
1214 0 : && REG_P (SET_SRC (PATTERN (insn)))
1215 0 : && REG_P (SET_DEST (PATTERN (insn)))
1216 0 : && (REGNO (SET_SRC (PATTERN (insn)))
1217 0 : == REGNO (SET_DEST (PATTERN (insn)))))
1218 : {
1219 0 : delete_insn (insn);
1220 0 : continue;
1221 : }
1222 :
1223 0 : pnote = ®_NOTES (insn);
1224 0 : while (*pnote != 0)
1225 : {
1226 0 : if (REG_NOTE_KIND (*pnote) == REG_DEAD
1227 0 : || REG_NOTE_KIND (*pnote) == REG_UNUSED
1228 0 : || REG_NOTE_KIND (*pnote) == REG_INC)
1229 0 : *pnote = XEXP (*pnote, 1);
1230 : else
1231 0 : pnote = &XEXP (*pnote, 1);
1232 : }
1233 :
1234 0 : if (AUTO_INC_DEC)
1235 : add_auto_inc_notes (insn, PATTERN (insn));
1236 :
1237 : /* Simplify (subreg (reg)) if it appears as an operand. */
1238 0 : cleanup_subreg_operands (insn);
1239 :
1240 : /* Clean up invalid ASMs so that they don't confuse later passes.
1241 : See PR 21299. */
1242 0 : if (asm_noperands (PATTERN (insn)) >= 0)
1243 : {
1244 0 : extract_insn (insn);
1245 0 : if (!constrain_operands (1, get_enabled_alternatives (insn)))
1246 : {
1247 0 : error_for_asm (insn,
1248 : "%<asm%> operand has impossible constraints");
1249 0 : delete_insn (insn);
1250 0 : continue;
1251 : }
1252 : }
1253 : }
1254 :
1255 0 : free (temp_pseudo_reg_arr);
1256 :
1257 : /* Indicate that we no longer have known memory locations or constants. */
1258 0 : free_reg_equiv ();
1259 :
1260 0 : free (reg_max_ref_mode);
1261 0 : free (reg_old_renumber);
1262 0 : free (pseudo_previous_regs);
1263 0 : free (pseudo_forbidden_regs);
1264 :
1265 0 : CLEAR_HARD_REG_SET (used_spill_regs);
1266 0 : for (i = 0; i < n_spills; i++)
1267 0 : SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1268 :
1269 : /* Free all the insn_chain structures at once. */
1270 0 : obstack_free (&reload_obstack, reload_startobj);
1271 0 : unused_insn_chains = 0;
1272 :
1273 0 : inserted = fixup_abnormal_edges ();
1274 :
1275 : /* Split basic blocks if we've possibly turned single trapping insn
1276 : into multiple ones or otherwise the backend requested to do so. */
1277 0 : if (cfun->can_throw_non_call_exceptions
1278 0 : || cfun->split_basic_blocks_after_reload)
1279 : {
1280 0 : auto_sbitmap blocks (last_basic_block_for_fn (cfun));
1281 0 : bitmap_ones (blocks);
1282 0 : find_many_sub_basic_blocks (blocks);
1283 0 : }
1284 :
1285 0 : if (inserted)
1286 0 : commit_edge_insertions ();
1287 :
1288 : /* Replacing pseudos with their memory equivalents might have
1289 : created shared rtx. Subsequent passes would get confused
1290 : by this, so unshare everything here. */
1291 0 : unshare_all_rtl_again (first);
1292 :
1293 : #ifdef STACK_BOUNDARY
1294 : /* init_emit has set the alignment of the hard frame pointer
1295 : to STACK_BOUNDARY. It is very likely no longer valid if
1296 : the hard frame pointer was used for register allocation. */
1297 0 : if (!frame_pointer_needed)
1298 0 : REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1299 : #endif
1300 :
1301 0 : substitute_stack.release ();
1302 :
1303 0 : gcc_assert (bitmap_empty_p (&spilled_pseudos));
1304 :
1305 0 : reload_completed = !failure;
1306 :
1307 0 : return need_dce;
1308 : }
1309 :
1310 : /* Yet another special case. Unfortunately, reg-stack forces people to
1311 : write incorrect clobbers in asm statements. These clobbers must not
1312 : cause the register to appear in bad_spill_regs, otherwise we'll call
1313 : fatal_insn later. We clear the corresponding regnos in the live
1314 : register sets to avoid this.
1315 : The whole thing is rather sick, I'm afraid. */
1316 :
1317 : static void
1318 0 : maybe_fix_stack_asms (void)
1319 : {
1320 : #ifdef STACK_REGS
1321 0 : const char *constraints[MAX_RECOG_OPERANDS];
1322 0 : machine_mode operand_mode[MAX_RECOG_OPERANDS];
1323 0 : class insn_chain *chain;
1324 :
1325 0 : for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1326 : {
1327 0 : int i, noperands;
1328 0 : HARD_REG_SET clobbered, allowed;
1329 0 : rtx pat;
1330 :
1331 0 : if (! INSN_P (chain->insn)
1332 0 : || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1333 0 : continue;
1334 0 : pat = PATTERN (chain->insn);
1335 0 : if (GET_CODE (pat) != PARALLEL)
1336 0 : continue;
1337 :
1338 0 : CLEAR_HARD_REG_SET (clobbered);
1339 0 : CLEAR_HARD_REG_SET (allowed);
1340 :
1341 : /* First, make a mask of all stack regs that are clobbered. */
1342 0 : for (i = 0; i < XVECLEN (pat, 0); i++)
1343 : {
1344 0 : rtx t = XVECEXP (pat, 0, i);
1345 0 : if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1346 0 : SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1347 : }
1348 :
1349 : /* Get the operand values and constraints out of the insn. */
1350 0 : decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1351 : constraints, operand_mode, NULL);
1352 :
1353 : /* For every operand, see what registers are allowed. */
1354 0 : for (i = 0; i < noperands; i++)
1355 : {
1356 0 : const char *p = constraints[i];
1357 : /* For every alternative, we compute the class of registers allowed
1358 : for reloading in CLS, and merge its contents into the reg set
1359 : ALLOWED. */
1360 0 : int cls = (int) NO_REGS;
1361 :
1362 0 : for (;;)
1363 : {
1364 0 : char c = *p;
1365 :
1366 0 : if (c == '\0' || c == ',' || c == '#')
1367 : {
1368 : /* End of one alternative - mark the regs in the current
1369 : class, and reset the class. */
1370 0 : allowed |= reg_class_contents[cls];
1371 0 : cls = NO_REGS;
1372 0 : p++;
1373 0 : if (c == '#')
1374 0 : do {
1375 0 : c = *p++;
1376 0 : } while (c != '\0' && c != ',');
1377 0 : if (c == '\0')
1378 : break;
1379 0 : continue;
1380 : }
1381 :
1382 : switch (c)
1383 : {
1384 0 : case 'g':
1385 0 : cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 0 : break;
1387 :
1388 0 : default:
1389 0 : enum constraint_num cn = lookup_constraint (p);
1390 0 : if (insn_extra_address_constraint (cn))
1391 0 : cls = (int) reg_class_subunion[cls]
1392 0 : [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1393 : ADDRESS, SCRATCH, NULL_RTX,
1394 0 : chain->insn)];
1395 : else
1396 0 : cls = (int) reg_class_subunion[cls]
1397 0 : [reg_class_for_constraint (cn)];
1398 : break;
1399 : }
1400 0 : p += CONSTRAINT_LEN (c, p);
1401 : }
1402 : }
1403 : /* Those of the registers which are clobbered, but allowed by the
1404 : constraints, must be usable as reload registers. So clear them
1405 : out of the life information. */
1406 0 : allowed &= clobbered;
1407 0 : hard_reg_set_iterator hrsi;
1408 0 : unsigned int j = 0;
1409 0 : EXECUTE_IF_SET_IN_HARD_REG_SET (allowed, 0, j, hrsi)
1410 : {
1411 0 : CLEAR_REGNO_REG_SET (&chain->live_throughout, j);
1412 0 : CLEAR_REGNO_REG_SET (&chain->dead_or_set, j);
1413 : }
1414 : }
1415 :
1416 : #endif
1417 0 : }
1418 :
1419 : /* Copy the global variables n_reloads and rld into the corresponding elts
1420 : of CHAIN. */
1421 : static void
1422 0 : copy_reloads (class insn_chain *chain)
1423 : {
1424 0 : chain->n_reloads = n_reloads;
1425 0 : chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1426 0 : memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1427 0 : reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1428 0 : }
1429 :
1430 : /* Walk the chain of insns, and determine for each whether it needs reloads
1431 : and/or eliminations. Build the corresponding insns_need_reload list, and
1432 : set something_needs_elimination as appropriate. */
1433 : static void
1434 0 : calculate_needs_all_insns (int global)
1435 : {
1436 0 : class insn_chain **pprev_reload = &insns_need_reload;
1437 0 : class insn_chain *chain, *next = 0;
1438 :
1439 0 : something_needs_elimination = 0;
1440 :
1441 0 : reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1442 0 : for (chain = reload_insn_chain; chain != 0; chain = next)
1443 : {
1444 0 : rtx_insn *insn = chain->insn;
1445 :
1446 0 : next = chain->next;
1447 :
1448 : /* Clear out the shortcuts. */
1449 0 : chain->n_reloads = 0;
1450 0 : chain->need_elim = 0;
1451 0 : chain->need_reload = 0;
1452 0 : chain->need_operand_change = 0;
1453 :
1454 : /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1455 : include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1456 : what effects this has on the known offsets at labels. */
1457 :
1458 0 : if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1459 0 : || (INSN_P (insn) && REG_NOTES (insn) != 0))
1460 0 : set_label_offsets (insn, insn, 0);
1461 :
1462 0 : if (INSN_P (insn))
1463 : {
1464 0 : rtx old_body = PATTERN (insn);
1465 0 : int old_code = INSN_CODE (insn);
1466 0 : rtx old_notes = REG_NOTES (insn);
1467 0 : int did_elimination = 0;
1468 0 : int operands_changed = 0;
1469 :
1470 : /* Skip insns that only set an equivalence. */
1471 0 : if (will_delete_init_insn_p (insn))
1472 0 : continue;
1473 :
1474 : /* If needed, eliminate any eliminable registers. */
1475 0 : if (num_eliminable || num_eliminable_invariants)
1476 0 : did_elimination = eliminate_regs_in_insn (insn, 0);
1477 :
1478 : /* Analyze the instruction. */
1479 0 : operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1480 : global, spill_reg_order);
1481 :
1482 : /* If a no-op set needs more than one reload, this is likely
1483 : to be something that needs input address reloads. We
1484 : can't get rid of this cleanly later, and it is of no use
1485 : anyway, so discard it now.
1486 : We only do this when expensive_optimizations is enabled,
1487 : since this complements reload inheritance / output
1488 : reload deletion, and it can make debugging harder. */
1489 0 : if (flag_expensive_optimizations && n_reloads > 1)
1490 : {
1491 0 : rtx set = single_set (insn);
1492 0 : if (set
1493 0 : &&
1494 0 : ((SET_SRC (set) == SET_DEST (set)
1495 0 : && REG_P (SET_SRC (set))
1496 0 : && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1497 0 : || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1498 0 : && reg_renumber[REGNO (SET_SRC (set))] < 0
1499 0 : && reg_renumber[REGNO (SET_DEST (set))] < 0
1500 0 : && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1501 0 : && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1502 0 : && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1503 0 : reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1504 : {
1505 0 : if (ira_conflicts_p)
1506 : /* Inform IRA about the insn deletion. */
1507 0 : ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1508 0 : REGNO (SET_SRC (set)));
1509 0 : delete_insn (insn);
1510 : /* Delete it from the reload chain. */
1511 0 : if (chain->prev)
1512 0 : chain->prev->next = next;
1513 : else
1514 0 : reload_insn_chain = next;
1515 0 : if (next)
1516 0 : next->prev = chain->prev;
1517 0 : chain->next = unused_insn_chains;
1518 0 : unused_insn_chains = chain;
1519 0 : continue;
1520 : }
1521 : }
1522 0 : if (num_eliminable)
1523 0 : update_eliminable_offsets ();
1524 :
1525 : /* Remember for later shortcuts which insns had any reloads or
1526 : register eliminations. */
1527 0 : chain->need_elim = did_elimination;
1528 0 : chain->need_reload = n_reloads > 0;
1529 0 : chain->need_operand_change = operands_changed;
1530 :
1531 : /* Discard any register replacements done. */
1532 0 : if (did_elimination)
1533 : {
1534 0 : obstack_free (&reload_obstack, reload_insn_firstobj);
1535 0 : PATTERN (insn) = old_body;
1536 0 : INSN_CODE (insn) = old_code;
1537 0 : REG_NOTES (insn) = old_notes;
1538 0 : something_needs_elimination = 1;
1539 : }
1540 :
1541 0 : something_needs_operands_changed |= operands_changed;
1542 :
1543 0 : if (n_reloads != 0)
1544 : {
1545 0 : copy_reloads (chain);
1546 0 : *pprev_reload = chain;
1547 0 : pprev_reload = &chain->next_need_reload;
1548 : }
1549 : }
1550 : }
1551 0 : *pprev_reload = 0;
1552 0 : }
1553 :
1554 : /* This function is called from the register allocator to set up estimates
1555 : for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1556 : an invariant. The structure is similar to calculate_needs_all_insns. */
1557 :
1558 : void
1559 0 : calculate_elim_costs_all_insns (void)
1560 : {
1561 0 : int *reg_equiv_init_cost;
1562 0 : basic_block bb;
1563 0 : int i;
1564 :
1565 0 : reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1566 0 : init_elim_table ();
1567 0 : init_eliminable_invariants (get_insns (), false);
1568 :
1569 0 : set_initial_elim_offsets ();
1570 0 : set_initial_label_offsets ();
1571 :
1572 0 : FOR_EACH_BB_FN (bb, cfun)
1573 : {
1574 0 : rtx_insn *insn;
1575 0 : elim_bb = bb;
1576 :
1577 0 : FOR_BB_INSNS (bb, insn)
1578 : {
1579 : /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1580 : include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1581 : what effects this has on the known offsets at labels. */
1582 :
1583 0 : if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1584 0 : || (INSN_P (insn) && REG_NOTES (insn) != 0))
1585 0 : set_label_offsets (insn, insn, 0);
1586 :
1587 0 : if (INSN_P (insn))
1588 : {
1589 0 : rtx set = single_set (insn);
1590 :
1591 : /* Skip insns that only set an equivalence. */
1592 0 : if (set && REG_P (SET_DEST (set))
1593 0 : && reg_renumber[REGNO (SET_DEST (set))] < 0
1594 0 : && (reg_equiv_constant (REGNO (SET_DEST (set)))
1595 0 : || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1596 : {
1597 0 : unsigned regno = REGNO (SET_DEST (set));
1598 0 : rtx_insn_list *init = reg_equiv_init (regno);
1599 0 : if (init)
1600 : {
1601 0 : rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1602 : false, true);
1603 0 : machine_mode mode = GET_MODE (SET_DEST (set));
1604 0 : int cost = set_src_cost (t, mode,
1605 : optimize_bb_for_speed_p (bb));
1606 0 : int freq = REG_FREQ_FROM_BB (bb);
1607 :
1608 0 : reg_equiv_init_cost[regno] = cost * freq;
1609 0 : continue;
1610 0 : }
1611 : }
1612 : /* If needed, eliminate any eliminable registers. */
1613 0 : if (num_eliminable || num_eliminable_invariants)
1614 0 : elimination_costs_in_insn (insn);
1615 :
1616 0 : if (num_eliminable)
1617 0 : update_eliminable_offsets ();
1618 : }
1619 : }
1620 : }
1621 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1622 : {
1623 0 : if (reg_equiv_invariant (i))
1624 : {
1625 0 : if (reg_equiv_init (i))
1626 : {
1627 0 : int cost = reg_equiv_init_cost[i];
1628 0 : if (dump_file)
1629 0 : fprintf (dump_file,
1630 : "Reg %d has equivalence, initial gains %d\n", i, cost);
1631 0 : if (cost != 0)
1632 0 : ira_adjust_equiv_reg_cost (i, cost);
1633 : }
1634 : else
1635 : {
1636 0 : if (dump_file)
1637 0 : fprintf (dump_file,
1638 : "Reg %d had equivalence, but can't be eliminated\n",
1639 : i);
1640 0 : ira_adjust_equiv_reg_cost (i, 0);
1641 : }
1642 : }
1643 : }
1644 :
1645 0 : free (reg_equiv_init_cost);
1646 0 : free (offsets_known_at);
1647 0 : free (offsets_at);
1648 0 : offsets_at = NULL;
1649 0 : offsets_known_at = NULL;
1650 0 : }
1651 :
1652 : /* Comparison function for qsort to decide which of two reloads
1653 : should be handled first. *P1 and *P2 are the reload numbers. */
1654 :
1655 : static int
1656 0 : reload_reg_class_lower (const void *r1p, const void *r2p)
1657 : {
1658 0 : int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1659 0 : int t;
1660 :
1661 : /* Consider required reloads before optional ones. */
1662 0 : t = rld[r1].optional - rld[r2].optional;
1663 0 : if (t != 0)
1664 : return t;
1665 :
1666 : /* Count all solitary classes before non-solitary ones. */
1667 0 : t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1668 0 : - (reg_class_size[(int) rld[r1].rclass] == 1));
1669 0 : if (t != 0)
1670 : return t;
1671 :
1672 : /* Aside from solitaires, consider all multi-reg groups first. */
1673 0 : t = rld[r2].nregs - rld[r1].nregs;
1674 0 : if (t != 0)
1675 : return t;
1676 :
1677 : /* Consider reloads in order of increasing reg-class number. */
1678 0 : t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1679 0 : if (t != 0)
1680 : return t;
1681 :
1682 : /* If reloads are equally urgent, sort by reload number,
1683 : so that the results of qsort leave nothing to chance. */
1684 0 : return r1 - r2;
1685 : }
1686 :
1687 : /* The cost of spilling each hard reg. */
1688 : static int spill_cost[FIRST_PSEUDO_REGISTER];
1689 :
1690 : /* When spilling multiple hard registers, we use SPILL_COST for the first
1691 : spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1692 : only the first hard reg for a multi-reg pseudo. */
1693 : static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1694 :
1695 : /* Map of hard regno to pseudo regno currently occupying the hard
1696 : reg. */
1697 : static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1698 :
1699 : /* Update the spill cost arrays, considering that pseudo REG is live. */
1700 :
1701 : static void
1702 0 : count_pseudo (int reg)
1703 : {
1704 0 : int freq = REG_FREQ (reg);
1705 0 : int r = reg_renumber[reg];
1706 0 : int nregs;
1707 :
1708 : /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1709 0 : if (ira_conflicts_p && r < 0)
1710 : return;
1711 :
1712 0 : if (REGNO_REG_SET_P (&pseudos_counted, reg)
1713 0 : || REGNO_REG_SET_P (&spilled_pseudos, reg))
1714 : return;
1715 :
1716 0 : SET_REGNO_REG_SET (&pseudos_counted, reg);
1717 :
1718 0 : gcc_assert (r >= 0);
1719 :
1720 0 : spill_add_cost[r] += freq;
1721 0 : nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1722 0 : while (nregs-- > 0)
1723 : {
1724 0 : hard_regno_to_pseudo_regno[r + nregs] = reg;
1725 0 : spill_cost[r + nregs] += freq;
1726 : }
1727 : }
1728 :
1729 : /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1730 : contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1731 :
1732 : static void
1733 0 : order_regs_for_reload (class insn_chain *chain)
1734 : {
1735 0 : unsigned i;
1736 0 : HARD_REG_SET used_by_pseudos;
1737 0 : HARD_REG_SET used_by_pseudos2;
1738 0 : reg_set_iterator rsi;
1739 :
1740 0 : bad_spill_regs = fixed_reg_set;
1741 :
1742 0 : memset (spill_cost, 0, sizeof spill_cost);
1743 0 : memset (spill_add_cost, 0, sizeof spill_add_cost);
1744 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1745 0 : hard_regno_to_pseudo_regno[i] = -1;
1746 :
1747 : /* Count number of uses of each hard reg by pseudo regs allocated to it
1748 : and then order them by decreasing use. First exclude hard registers
1749 : that are live in or across this insn. */
1750 :
1751 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1752 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1753 0 : bad_spill_regs |= used_by_pseudos;
1754 0 : bad_spill_regs |= used_by_pseudos2;
1755 :
1756 : /* Now find out which pseudos are allocated to it, and update
1757 : hard_reg_n_uses. */
1758 0 : CLEAR_REG_SET (&pseudos_counted);
1759 :
1760 0 : EXECUTE_IF_SET_IN_REG_SET
1761 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1762 : {
1763 0 : count_pseudo (i);
1764 : }
1765 0 : EXECUTE_IF_SET_IN_REG_SET
1766 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1767 : {
1768 0 : count_pseudo (i);
1769 : }
1770 0 : CLEAR_REG_SET (&pseudos_counted);
1771 0 : }
1772 :
1773 : /* Vector of reload-numbers showing the order in which the reloads should
1774 : be processed. */
1775 : static short reload_order[MAX_RELOADS];
1776 :
1777 : /* This is used to keep track of the spill regs used in one insn. */
1778 : static HARD_REG_SET used_spill_regs_local;
1779 :
1780 : /* We decided to spill hard register SPILLED, which has a size of
1781 : SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1782 : is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1783 : update SPILL_COST/SPILL_ADD_COST. */
1784 :
1785 : static void
1786 0 : count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1787 : {
1788 0 : int freq = REG_FREQ (reg);
1789 0 : int r = reg_renumber[reg];
1790 0 : int nregs;
1791 :
1792 : /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1793 0 : if (ira_conflicts_p && r < 0)
1794 : return;
1795 :
1796 0 : gcc_assert (r >= 0);
1797 :
1798 0 : nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg));
1799 :
1800 0 : if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1801 0 : || spilled + spilled_nregs <= r || r + nregs <= spilled)
1802 : return;
1803 :
1804 0 : SET_REGNO_REG_SET (&spilled_pseudos, reg);
1805 :
1806 0 : spill_add_cost[r] -= freq;
1807 0 : while (nregs-- > 0)
1808 : {
1809 0 : hard_regno_to_pseudo_regno[r + nregs] = -1;
1810 0 : spill_cost[r + nregs] -= freq;
1811 : }
1812 : }
1813 :
1814 : /* Find reload register to use for reload number ORDER. */
1815 :
1816 : static int
1817 0 : find_reg (class insn_chain *chain, int order)
1818 : {
1819 0 : int rnum = reload_order[order];
1820 0 : struct reload *rl = rld + rnum;
1821 0 : int best_cost = INT_MAX;
1822 0 : int best_reg = -1;
1823 0 : unsigned int i, j, n;
1824 0 : int k;
1825 0 : HARD_REG_SET not_usable;
1826 0 : HARD_REG_SET used_by_other_reload;
1827 0 : reg_set_iterator rsi;
1828 0 : static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1829 0 : static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1830 :
1831 0 : not_usable = (bad_spill_regs
1832 0 : | bad_spill_regs_global
1833 0 : | ~reg_class_contents[rl->rclass]);
1834 :
1835 0 : CLEAR_HARD_REG_SET (used_by_other_reload);
1836 0 : for (k = 0; k < order; k++)
1837 : {
1838 0 : int other = reload_order[k];
1839 :
1840 0 : if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1841 0 : for (j = 0; j < rld[other].nregs; j++)
1842 0 : SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1843 : }
1844 :
1845 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1846 : {
1847 : #ifdef REG_ALLOC_ORDER
1848 0 : unsigned int regno = reg_alloc_order[i];
1849 : #else
1850 : unsigned int regno = i;
1851 : #endif
1852 :
1853 0 : if (! TEST_HARD_REG_BIT (not_usable, regno)
1854 0 : && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1855 0 : && targetm.hard_regno_mode_ok (regno, rl->mode))
1856 : {
1857 0 : int this_cost = spill_cost[regno];
1858 0 : int ok = 1;
1859 0 : unsigned int this_nregs = hard_regno_nregs (regno, rl->mode);
1860 :
1861 0 : for (j = 1; j < this_nregs; j++)
1862 : {
1863 0 : this_cost += spill_add_cost[regno + j];
1864 0 : if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1865 0 : || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1866 : ok = 0;
1867 : }
1868 0 : if (! ok)
1869 0 : continue;
1870 :
1871 0 : if (ira_conflicts_p)
1872 : {
1873 : /* Ask IRA to find a better pseudo-register for
1874 : spilling. */
1875 0 : for (n = j = 0; j < this_nregs; j++)
1876 : {
1877 0 : int r = hard_regno_to_pseudo_regno[regno + j];
1878 :
1879 0 : if (r < 0)
1880 0 : continue;
1881 0 : if (n == 0 || regno_pseudo_regs[n - 1] != r)
1882 0 : regno_pseudo_regs[n++] = r;
1883 : }
1884 0 : regno_pseudo_regs[n++] = -1;
1885 0 : if (best_reg < 0
1886 0 : || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1887 : best_regno_pseudo_regs,
1888 : rl->in, rl->out,
1889 : chain->insn))
1890 : {
1891 0 : best_reg = regno;
1892 0 : for (j = 0;; j++)
1893 : {
1894 0 : best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1895 0 : if (regno_pseudo_regs[j] < 0)
1896 : break;
1897 : }
1898 : }
1899 0 : continue;
1900 0 : }
1901 :
1902 0 : if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1903 0 : this_cost--;
1904 0 : if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1905 0 : this_cost--;
1906 0 : if (this_cost < best_cost
1907 : /* Among registers with equal cost, prefer caller-saved ones, or
1908 : use REG_ALLOC_ORDER if it is defined. */
1909 0 : || (this_cost == best_cost
1910 : #ifdef REG_ALLOC_ORDER
1911 0 : && (inv_reg_alloc_order[regno]
1912 0 : < inv_reg_alloc_order[best_reg])
1913 : #else
1914 : && crtl->abi->clobbers_full_reg_p (regno)
1915 : && !crtl->abi->clobbers_full_reg_p (best_reg)
1916 : #endif
1917 : ))
1918 : {
1919 0 : best_reg = regno;
1920 0 : best_cost = this_cost;
1921 : }
1922 : }
1923 : }
1924 0 : if (best_reg == -1)
1925 : return 0;
1926 :
1927 0 : if (dump_file)
1928 0 : fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1929 :
1930 0 : rl->nregs = hard_regno_nregs (best_reg, rl->mode);
1931 0 : rl->regno = best_reg;
1932 :
1933 0 : EXECUTE_IF_SET_IN_REG_SET
1934 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1935 : {
1936 0 : count_spilled_pseudo (best_reg, rl->nregs, j);
1937 : }
1938 :
1939 0 : EXECUTE_IF_SET_IN_REG_SET
1940 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1941 : {
1942 0 : count_spilled_pseudo (best_reg, rl->nregs, j);
1943 : }
1944 :
1945 0 : for (i = 0; i < rl->nregs; i++)
1946 : {
1947 0 : gcc_assert (spill_cost[best_reg + i] == 0);
1948 0 : gcc_assert (spill_add_cost[best_reg + i] == 0);
1949 0 : gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1950 0 : SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1951 : }
1952 : return 1;
1953 : }
1954 :
1955 : /* Find more reload regs to satisfy the remaining need of an insn, which
1956 : is given by CHAIN.
1957 : Do it by ascending class number, since otherwise a reg
1958 : might be spilled for a big class and might fail to count
1959 : for a smaller class even though it belongs to that class. */
1960 :
1961 : static void
1962 0 : find_reload_regs (class insn_chain *chain)
1963 : {
1964 0 : int i;
1965 :
1966 : /* In order to be certain of getting the registers we need,
1967 : we must sort the reloads into order of increasing register class.
1968 : Then our grabbing of reload registers will parallel the process
1969 : that provided the reload registers. */
1970 0 : for (i = 0; i < chain->n_reloads; i++)
1971 : {
1972 : /* Show whether this reload already has a hard reg. */
1973 0 : if (chain->rld[i].reg_rtx)
1974 : {
1975 0 : chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx);
1976 0 : chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx);
1977 : }
1978 : else
1979 0 : chain->rld[i].regno = -1;
1980 0 : reload_order[i] = i;
1981 : }
1982 :
1983 0 : n_reloads = chain->n_reloads;
1984 0 : memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1985 :
1986 0 : CLEAR_HARD_REG_SET (used_spill_regs_local);
1987 :
1988 0 : if (dump_file)
1989 0 : fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1990 :
1991 0 : qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1992 :
1993 : /* Compute the order of preference for hard registers to spill. */
1994 :
1995 0 : order_regs_for_reload (chain);
1996 :
1997 0 : for (i = 0; i < n_reloads; i++)
1998 : {
1999 0 : int r = reload_order[i];
2000 :
2001 : /* Ignore reloads that got marked inoperative. */
2002 0 : if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2003 0 : && ! rld[r].optional
2004 0 : && rld[r].regno == -1)
2005 0 : if (! find_reg (chain, i))
2006 : {
2007 0 : if (dump_file)
2008 0 : fprintf (dump_file, "reload failure for reload %d\n", r);
2009 0 : spill_failure (chain->insn, rld[r].rclass);
2010 0 : failure = 1;
2011 0 : return;
2012 : }
2013 : }
2014 :
2015 0 : chain->used_spill_regs = used_spill_regs_local;
2016 0 : used_spill_regs |= used_spill_regs_local;
2017 :
2018 0 : memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2019 : }
2020 :
2021 : static void
2022 0 : select_reload_regs (void)
2023 : {
2024 0 : class insn_chain *chain;
2025 :
2026 : /* Try to satisfy the needs for each insn. */
2027 0 : for (chain = insns_need_reload; chain != 0;
2028 0 : chain = chain->next_need_reload)
2029 0 : find_reload_regs (chain);
2030 0 : }
2031 :
2032 : /* Delete all insns that were inserted by emit_caller_save_insns during
2033 : this iteration. */
2034 : static void
2035 0 : delete_caller_save_insns (void)
2036 : {
2037 0 : class insn_chain *c = reload_insn_chain;
2038 :
2039 0 : while (c != 0)
2040 : {
2041 0 : while (c != 0 && c->is_caller_save_insn)
2042 : {
2043 0 : class insn_chain *next = c->next;
2044 0 : rtx_insn *insn = c->insn;
2045 :
2046 0 : if (c == reload_insn_chain)
2047 0 : reload_insn_chain = next;
2048 0 : delete_insn (insn);
2049 :
2050 0 : if (next)
2051 0 : next->prev = c->prev;
2052 0 : if (c->prev)
2053 0 : c->prev->next = next;
2054 0 : c->next = unused_insn_chains;
2055 0 : unused_insn_chains = c;
2056 0 : c = next;
2057 : }
2058 0 : if (c != 0)
2059 0 : c = c->next;
2060 : }
2061 0 : }
2062 :
2063 : /* Handle the failure to find a register to spill.
2064 : INSN should be one of the insns which needed this particular spill reg. */
2065 :
2066 : static void
2067 0 : spill_failure (rtx_insn *insn, enum reg_class rclass)
2068 : {
2069 0 : if (asm_noperands (PATTERN (insn)) >= 0)
2070 0 : error_for_asm (insn, "cannot find a register in class %qs while "
2071 : "reloading %<asm%>",
2072 0 : reg_class_names[rclass]);
2073 : else
2074 : {
2075 0 : error ("unable to find a register to spill in class %qs",
2076 0 : reg_class_names[rclass]);
2077 :
2078 0 : if (dump_file)
2079 : {
2080 0 : fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2081 0 : debug_reload_to_stream (dump_file);
2082 : }
2083 0 : fatal_insn ("this is the insn:", insn);
2084 : }
2085 0 : }
2086 :
2087 : /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2088 : data that is dead in INSN. */
2089 :
2090 : static void
2091 0 : delete_dead_insn (rtx_insn *insn)
2092 : {
2093 0 : rtx_insn *prev = prev_active_insn (insn);
2094 0 : rtx prev_dest;
2095 :
2096 : /* If the previous insn sets a register that dies in our insn make
2097 : a note that we want to run DCE immediately after reload.
2098 :
2099 : We used to delete the previous insn & recurse, but that's wrong for
2100 : block local equivalences. Instead of trying to figure out the exact
2101 : circumstances where we can delete the potentially dead insns, just
2102 : let DCE do the job. */
2103 0 : if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn)
2104 0 : && GET_CODE (PATTERN (prev)) == SET
2105 0 : && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2106 0 : && reg_mentioned_p (prev_dest, PATTERN (insn))
2107 0 : && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2108 0 : && ! side_effects_p (SET_SRC (PATTERN (prev))))
2109 0 : need_dce = 1;
2110 :
2111 0 : SET_INSN_DELETED (insn);
2112 0 : }
2113 :
2114 : /* Modify the home of pseudo-reg I.
2115 : The new home is present in reg_renumber[I].
2116 :
2117 : FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2118 : or it may be -1, meaning there is none or it is not relevant.
2119 : This is used so that all pseudos spilled from a given hard reg
2120 : can share one stack slot. */
2121 :
2122 : static void
2123 0 : alter_reg (int i, int from_reg, bool dont_share_p)
2124 : {
2125 : /* When outputting an inline function, this can happen
2126 : for a reg that isn't actually used. */
2127 0 : if (regno_reg_rtx[i] == 0)
2128 : return;
2129 :
2130 : /* If the reg got changed to a MEM at rtl-generation time,
2131 : ignore it. */
2132 0 : if (!REG_P (regno_reg_rtx[i]))
2133 : return;
2134 :
2135 : /* Modify the reg-rtx to contain the new hard reg
2136 : number or else to contain its pseudo reg number. */
2137 0 : SET_REGNO (regno_reg_rtx[i],
2138 : reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2139 :
2140 : /* If we have a pseudo that is needed but has no hard reg or equivalent,
2141 : allocate a stack slot for it. */
2142 :
2143 0 : if (reg_renumber[i] < 0
2144 0 : && REG_N_REFS (i) > 0
2145 0 : && reg_equiv_constant (i) == 0
2146 0 : && (reg_equiv_invariant (i) == 0
2147 0 : || reg_equiv_init (i) == 0)
2148 0 : && reg_equiv_memory_loc (i) == 0)
2149 : {
2150 0 : rtx x = NULL_RTX;
2151 0 : machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2152 0 : poly_uint64 inherent_size = GET_MODE_SIZE (mode);
2153 0 : unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2154 0 : machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]);
2155 0 : poly_uint64 total_size = GET_MODE_SIZE (wider_mode);
2156 : /* ??? Seems strange to derive the minimum alignment from the size,
2157 : but that's the traditional behavior. For polynomial-size modes,
2158 : the natural extension is to use the minimum possible size. */
2159 0 : unsigned int min_align
2160 0 : = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i]));
2161 0 : poly_int64 adjust = 0;
2162 :
2163 0 : something_was_spilled = true;
2164 :
2165 0 : if (ira_conflicts_p)
2166 : {
2167 : /* Mark the spill for IRA. */
2168 0 : SET_REGNO_REG_SET (&spilled_pseudos, i);
2169 0 : if (!dont_share_p)
2170 0 : x = ira_reuse_stack_slot (i, inherent_size, total_size);
2171 : }
2172 :
2173 0 : if (x)
2174 : ;
2175 :
2176 : /* Each pseudo reg has an inherent size which comes from its own mode,
2177 : and a total size which provides room for paradoxical subregs
2178 : which refer to the pseudo reg in wider modes.
2179 :
2180 : We can use a slot already allocated if it provides both
2181 : enough inherent space and enough total space.
2182 : Otherwise, we allocate a new slot, making sure that it has no less
2183 : inherent space, and no less total space, then the previous slot. */
2184 0 : else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2185 : {
2186 0 : rtx stack_slot;
2187 :
2188 : /* The sizes are taken from a subreg operation, which guarantees
2189 : that they're ordered. */
2190 0 : gcc_checking_assert (ordered_p (total_size, inherent_size));
2191 :
2192 : /* No known place to spill from => no slot to reuse. */
2193 0 : x = assign_stack_local (mode, total_size,
2194 : min_align > inherent_align
2195 0 : || maybe_gt (total_size, inherent_size)
2196 : ? -1 : 0);
2197 :
2198 0 : stack_slot = x;
2199 :
2200 : /* Cancel the big-endian correction done in assign_stack_local.
2201 : Get the address of the beginning of the slot. This is so we
2202 : can do a big-endian correction unconditionally below. */
2203 0 : if (BYTES_BIG_ENDIAN)
2204 : {
2205 : adjust = inherent_size - total_size;
2206 : if (maybe_ne (adjust, 0))
2207 : {
2208 : poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2209 : machine_mode mem_mode
2210 : = int_mode_for_size (total_bits, 1).else_blk ();
2211 : stack_slot = adjust_address_nv (x, mem_mode, adjust);
2212 : }
2213 : }
2214 :
2215 0 : if (! dont_share_p && ira_conflicts_p)
2216 : /* Inform IRA about allocation a new stack slot. */
2217 0 : ira_mark_new_stack_slot (stack_slot, i, total_size);
2218 : }
2219 :
2220 : /* Reuse a stack slot if possible. */
2221 0 : else if (spill_stack_slot[from_reg] != 0
2222 0 : && known_ge (spill_stack_slot_width[from_reg], total_size)
2223 0 : && known_ge (GET_MODE_SIZE
2224 : (GET_MODE (spill_stack_slot[from_reg])),
2225 : inherent_size)
2226 0 : && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2227 : x = spill_stack_slot[from_reg];
2228 :
2229 : /* Allocate a bigger slot. */
2230 : else
2231 : {
2232 : /* Compute maximum size needed, both for inherent size
2233 : and for total size. */
2234 0 : rtx stack_slot;
2235 :
2236 0 : if (spill_stack_slot[from_reg])
2237 : {
2238 0 : if (partial_subreg_p (mode,
2239 0 : GET_MODE (spill_stack_slot[from_reg])))
2240 0 : mode = GET_MODE (spill_stack_slot[from_reg]);
2241 0 : total_size = ordered_max (total_size,
2242 0 : spill_stack_slot_width[from_reg]);
2243 0 : if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2244 : min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2245 : }
2246 :
2247 : /* The sizes are taken from a subreg operation, which guarantees
2248 : that they're ordered. */
2249 0 : gcc_checking_assert (ordered_p (total_size, inherent_size));
2250 :
2251 : /* Make a slot with that size. */
2252 0 : x = assign_stack_local (mode, total_size,
2253 : min_align > inherent_align
2254 0 : || maybe_gt (total_size, inherent_size)
2255 : ? -1 : 0);
2256 0 : stack_slot = x;
2257 :
2258 : /* Cancel the big-endian correction done in assign_stack_local.
2259 : Get the address of the beginning of the slot. This is so we
2260 : can do a big-endian correction unconditionally below. */
2261 0 : if (BYTES_BIG_ENDIAN)
2262 : {
2263 : adjust = GET_MODE_SIZE (mode) - total_size;
2264 : if (maybe_ne (adjust, 0))
2265 : {
2266 : poly_uint64 total_bits = total_size * BITS_PER_UNIT;
2267 : machine_mode mem_mode
2268 : = int_mode_for_size (total_bits, 1).else_blk ();
2269 : stack_slot = adjust_address_nv (x, mem_mode, adjust);
2270 : }
2271 : }
2272 :
2273 0 : spill_stack_slot[from_reg] = stack_slot;
2274 0 : spill_stack_slot_width[from_reg] = total_size;
2275 : }
2276 :
2277 : /* On a big endian machine, the "address" of the slot
2278 : is the address of the low part that fits its inherent mode. */
2279 0 : adjust += subreg_size_lowpart_offset (inherent_size, total_size);
2280 :
2281 : /* If we have any adjustment to make, or if the stack slot is the
2282 : wrong mode, make a new stack slot. */
2283 0 : x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2284 :
2285 : /* Set all of the memory attributes as appropriate for a spill. */
2286 0 : set_mem_attrs_for_spill (x);
2287 :
2288 : /* Save the stack slot for later. */
2289 0 : reg_equiv_memory_loc (i) = x;
2290 : }
2291 : }
2292 :
2293 : /* Mark the slots in regs_ever_live for the hard regs used by
2294 : pseudo-reg number REGNO, accessed in MODE. */
2295 :
2296 : static void
2297 0 : mark_home_live_1 (int regno, machine_mode mode)
2298 : {
2299 0 : int i, lim;
2300 :
2301 0 : i = reg_renumber[regno];
2302 0 : if (i < 0)
2303 : return;
2304 0 : lim = end_hard_regno (mode, i);
2305 0 : while (i < lim)
2306 0 : df_set_regs_ever_live (i++, true);
2307 : }
2308 :
2309 : /* Mark the slots in regs_ever_live for the hard regs
2310 : used by pseudo-reg number REGNO. */
2311 :
2312 : void
2313 0 : mark_home_live (int regno)
2314 : {
2315 0 : if (reg_renumber[regno] >= 0)
2316 0 : mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2317 0 : }
2318 :
2319 : /* This function handles the tracking of elimination offsets around branches.
2320 :
2321 : X is a piece of RTL being scanned.
2322 :
2323 : INSN is the insn that it came from, if any.
2324 :
2325 : INITIAL_P is nonzero if we are to set the offset to be the initial
2326 : offset and zero if we are setting the offset of the label to be the
2327 : current offset. */
2328 :
2329 : static void
2330 0 : set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
2331 : {
2332 0 : enum rtx_code code = GET_CODE (x);
2333 0 : rtx tem;
2334 0 : unsigned int i;
2335 0 : struct elim_table *p;
2336 :
2337 0 : switch (code)
2338 : {
2339 0 : case LABEL_REF:
2340 0 : if (LABEL_REF_NONLOCAL_P (x))
2341 : return;
2342 :
2343 0 : x = label_ref_label (x);
2344 :
2345 : /* fall through */
2346 :
2347 0 : case CODE_LABEL:
2348 : /* If we know nothing about this label, set the desired offsets. Note
2349 : that this sets the offset at a label to be the offset before a label
2350 : if we don't know anything about the label. This is not correct for
2351 : the label after a BARRIER, but is the best guess we can make. If
2352 : we guessed wrong, we will suppress an elimination that might have
2353 : been possible had we been able to guess correctly. */
2354 :
2355 0 : if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2356 : {
2357 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2358 0 : offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2359 0 : = (initial_p ? reg_eliminate[i].initial_offset
2360 0 : : reg_eliminate[i].offset);
2361 0 : offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2362 : }
2363 :
2364 : /* Otherwise, if this is the definition of a label and it is
2365 : preceded by a BARRIER, set our offsets to the known offset of
2366 : that label. */
2367 :
2368 0 : else if (x == insn
2369 0 : && (tem = prev_nonnote_insn (insn)) != 0
2370 0 : && BARRIER_P (tem))
2371 0 : set_offsets_for_label (insn);
2372 : else
2373 : /* If neither of the above cases is true, compare each offset
2374 : with those previously recorded and suppress any eliminations
2375 : where the offsets disagree. */
2376 :
2377 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2378 0 : if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i],
2379 0 : (initial_p ? reg_eliminate[i].initial_offset
2380 0 : : reg_eliminate[i].offset)))
2381 0 : reg_eliminate[i].can_eliminate = 0;
2382 :
2383 : return;
2384 :
2385 0 : case JUMP_TABLE_DATA:
2386 0 : set_label_offsets (PATTERN (insn), insn, initial_p);
2387 0 : return;
2388 :
2389 0 : case JUMP_INSN:
2390 0 : set_label_offsets (PATTERN (insn), insn, initial_p);
2391 :
2392 : /* fall through */
2393 :
2394 0 : case INSN:
2395 0 : case CALL_INSN:
2396 : /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2397 : to indirectly and hence must have all eliminations at their
2398 : initial offsets. */
2399 0 : for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2400 0 : if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2401 0 : set_label_offsets (XEXP (tem, 0), insn, 1);
2402 : return;
2403 :
2404 : case PARALLEL:
2405 : case ADDR_VEC:
2406 : case ADDR_DIFF_VEC:
2407 : /* Each of the labels in the parallel or address vector must be
2408 : at their initial offsets. We want the first field for PARALLEL
2409 : and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2410 :
2411 0 : for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2412 0 : set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2413 : insn, initial_p);
2414 : return;
2415 :
2416 0 : case SET:
2417 : /* We only care about setting PC. If the source is not RETURN,
2418 : IF_THEN_ELSE, or a label, disable any eliminations not at
2419 : their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2420 : isn't one of those possibilities. For branches to a label,
2421 : call ourselves recursively.
2422 :
2423 : Note that this can disable elimination unnecessarily when we have
2424 : a non-local goto since it will look like a non-constant jump to
2425 : someplace in the current function. This isn't a significant
2426 : problem since such jumps will normally be when all elimination
2427 : pairs are back to their initial offsets. */
2428 :
2429 0 : if (SET_DEST (x) != pc_rtx)
2430 : return;
2431 :
2432 0 : switch (GET_CODE (SET_SRC (x)))
2433 : {
2434 : case PC:
2435 : case RETURN:
2436 : return;
2437 :
2438 : case LABEL_REF:
2439 : set_label_offsets (SET_SRC (x), insn, initial_p);
2440 : return;
2441 :
2442 0 : case IF_THEN_ELSE:
2443 0 : tem = XEXP (SET_SRC (x), 1);
2444 0 : if (GET_CODE (tem) == LABEL_REF)
2445 0 : set_label_offsets (label_ref_label (tem), insn, initial_p);
2446 0 : else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2447 : break;
2448 :
2449 0 : tem = XEXP (SET_SRC (x), 2);
2450 0 : if (GET_CODE (tem) == LABEL_REF)
2451 0 : set_label_offsets (label_ref_label (tem), insn, initial_p);
2452 0 : else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2453 : break;
2454 : return;
2455 :
2456 : default:
2457 : break;
2458 : }
2459 :
2460 : /* If we reach here, all eliminations must be at their initial
2461 : offset because we are doing a jump to a variable address. */
2462 0 : for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2463 0 : if (maybe_ne (p->offset, p->initial_offset))
2464 0 : p->can_eliminate = 0;
2465 : break;
2466 :
2467 : default:
2468 : break;
2469 : }
2470 : }
2471 :
2472 : /* This function examines every reg that occurs in X and adjusts the
2473 : costs for its elimination which are gathered by IRA. INSN is the
2474 : insn in which X occurs. We do not recurse into MEM expressions. */
2475 :
2476 : static void
2477 0 : note_reg_elim_costly (const_rtx x, rtx insn)
2478 : {
2479 0 : subrtx_iterator::array_type array;
2480 0 : FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2481 : {
2482 0 : const_rtx x = *iter;
2483 0 : if (MEM_P (x))
2484 0 : iter.skip_subrtxes ();
2485 0 : else if (REG_P (x)
2486 0 : && REGNO (x) >= FIRST_PSEUDO_REGISTER
2487 0 : && reg_equiv_init (REGNO (x))
2488 0 : && reg_equiv_invariant (REGNO (x)))
2489 : {
2490 0 : rtx t = reg_equiv_invariant (REGNO (x));
2491 0 : rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2492 0 : int cost = set_src_cost (new_rtx, Pmode,
2493 : optimize_bb_for_speed_p (elim_bb));
2494 0 : int freq = REG_FREQ_FROM_BB (elim_bb);
2495 :
2496 0 : if (cost != 0)
2497 0 : ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2498 : }
2499 : }
2500 0 : }
2501 :
2502 : /* Scan X and replace any eliminable registers (such as fp) with a
2503 : replacement (such as sp), plus an offset.
2504 :
2505 : MEM_MODE is the mode of an enclosing MEM. We need this to know how
2506 : much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2507 : MEM, we are allowed to replace a sum of a register and the constant zero
2508 : with the register, which we cannot do outside a MEM. In addition, we need
2509 : to record the fact that a register is referenced outside a MEM.
2510 :
2511 : If INSN is an insn, it is the insn containing X. If we replace a REG
2512 : in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2513 : CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2514 : the REG is being modified.
2515 :
2516 : Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2517 : That's used when we eliminate in expressions stored in notes.
2518 : This means, do not set ref_outside_mem even if the reference
2519 : is outside of MEMs.
2520 :
2521 : If FOR_COSTS is true, we are being called before reload in order to
2522 : estimate the costs of keeping registers with an equivalence unallocated.
2523 :
2524 : REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2525 : replacements done assuming all offsets are at their initial values. If
2526 : they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2527 : encounter, return the actual location so that find_reloads will do
2528 : the proper thing. */
2529 :
2530 : static rtx
2531 0 : eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
2532 : bool may_use_invariant, bool for_costs)
2533 : {
2534 0 : enum rtx_code code = GET_CODE (x);
2535 0 : struct elim_table *ep;
2536 0 : int regno;
2537 0 : rtx new_rtx;
2538 0 : int i, j;
2539 0 : const char *fmt;
2540 0 : int copied = 0;
2541 :
2542 0 : if (! current_function_decl)
2543 : return x;
2544 :
2545 0 : switch (code)
2546 : {
2547 : CASE_CONST_ANY:
2548 : case CONST:
2549 : case SYMBOL_REF:
2550 : case CODE_LABEL:
2551 : case PC:
2552 : case ASM_INPUT:
2553 : case ADDR_VEC:
2554 : case ADDR_DIFF_VEC:
2555 : case RETURN:
2556 : return x;
2557 :
2558 0 : case REG:
2559 0 : regno = REGNO (x);
2560 :
2561 : /* First handle the case where we encounter a bare register that
2562 : is eliminable. Replace it with a PLUS. */
2563 0 : if (regno < FIRST_PSEUDO_REGISTER)
2564 : {
2565 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2566 : ep++)
2567 0 : if (ep->from_rtx == x && ep->can_eliminate)
2568 0 : return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2569 :
2570 : }
2571 0 : else if (reg_renumber && reg_renumber[regno] < 0
2572 0 : && reg_equivs
2573 0 : && reg_equiv_invariant (regno))
2574 : {
2575 0 : if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2576 0 : return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2577 0 : mem_mode, insn, true, for_costs);
2578 : /* There exists at least one use of REGNO that cannot be
2579 : eliminated. Prevent the defining insn from being deleted. */
2580 0 : reg_equiv_init (regno) = NULL;
2581 0 : if (!for_costs)
2582 0 : alter_reg (regno, -1, true);
2583 : }
2584 : return x;
2585 :
2586 : /* You might think handling MINUS in a manner similar to PLUS is a
2587 : good idea. It is not. It has been tried multiple times and every
2588 : time the change has had to have been reverted.
2589 :
2590 : Other parts of reload know a PLUS is special (gen_reload for example)
2591 : and require special code to handle code a reloaded PLUS operand.
2592 :
2593 : Also consider backends where the flags register is clobbered by a
2594 : MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2595 : lea instruction comes to mind). If we try to reload a MINUS, we
2596 : may kill the flags register that was holding a useful value.
2597 :
2598 : So, please before trying to handle MINUS, consider reload as a
2599 : whole instead of this little section as well as the backend issues. */
2600 0 : case PLUS:
2601 : /* If this is the sum of an eliminable register and a constant, rework
2602 : the sum. */
2603 0 : if (REG_P (XEXP (x, 0))
2604 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2605 0 : && CONSTANT_P (XEXP (x, 1)))
2606 : {
2607 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2608 : ep++)
2609 0 : if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2610 : {
2611 : /* The only time we want to replace a PLUS with a REG (this
2612 : occurs when the constant operand of the PLUS is the negative
2613 : of the offset) is when we are inside a MEM. We won't want
2614 : to do so at other times because that would change the
2615 : structure of the insn in a way that reload can't handle.
2616 : We special-case the commonest situation in
2617 : eliminate_regs_in_insn, so just replace a PLUS with a
2618 : PLUS here, unless inside a MEM. In DEBUG_INSNs, it is
2619 : always ok to replace a PLUS with just a REG. */
2620 0 : if ((mem_mode != 0 || (insn && DEBUG_INSN_P (insn)))
2621 0 : && CONST_INT_P (XEXP (x, 1))
2622 0 : && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset))
2623 0 : return ep->to_rtx;
2624 : else
2625 0 : return gen_rtx_PLUS (Pmode, ep->to_rtx,
2626 : plus_constant (Pmode, XEXP (x, 1),
2627 : ep->previous_offset));
2628 : }
2629 :
2630 : /* If the register is not eliminable, we are done since the other
2631 : operand is a constant. */
2632 : return x;
2633 : }
2634 :
2635 : /* If this is part of an address, we want to bring any constant to the
2636 : outermost PLUS. We will do this by doing register replacement in
2637 : our operands and seeing if a constant shows up in one of them.
2638 :
2639 : Note that there is no risk of modifying the structure of the insn,
2640 : since we only get called for its operands, thus we are either
2641 : modifying the address inside a MEM, or something like an address
2642 : operand of a load-address insn. */
2643 :
2644 0 : {
2645 0 : rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2646 : for_costs);
2647 0 : rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2648 : for_costs);
2649 :
2650 0 : if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2651 : {
2652 : /* If one side is a PLUS and the other side is a pseudo that
2653 : didn't get a hard register but has a reg_equiv_constant,
2654 : we must replace the constant here since it may no longer
2655 : be in the position of any operand. */
2656 0 : if (GET_CODE (new0) == PLUS && REG_P (new1)
2657 0 : && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2658 0 : && reg_renumber[REGNO (new1)] < 0
2659 0 : && reg_equivs
2660 0 : && reg_equiv_constant (REGNO (new1)) != 0)
2661 : new1 = reg_equiv_constant (REGNO (new1));
2662 0 : else if (GET_CODE (new1) == PLUS && REG_P (new0)
2663 0 : && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2664 0 : && reg_renumber[REGNO (new0)] < 0
2665 0 : && reg_equiv_constant (REGNO (new0)) != 0)
2666 : new0 = reg_equiv_constant (REGNO (new0));
2667 :
2668 0 : new_rtx = form_sum (GET_MODE (x), new0, new1);
2669 :
2670 : /* As above, if we are not inside a MEM we do not want to
2671 : turn a PLUS into something else. We might try to do so here
2672 : for an addition of 0 if we aren't optimizing. */
2673 0 : if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2674 0 : return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2675 : else
2676 : return new_rtx;
2677 : }
2678 : }
2679 : return x;
2680 :
2681 0 : case MULT:
2682 : /* If this is the product of an eliminable register and a
2683 : constant, apply the distribute law and move the constant out
2684 : so that we have (plus (mult ..) ..). This is needed in order
2685 : to keep load-address insns valid. This case is pathological.
2686 : We ignore the possibility of overflow here. */
2687 0 : if (REG_P (XEXP (x, 0))
2688 0 : && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2689 0 : && CONST_INT_P (XEXP (x, 1)))
2690 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2691 : ep++)
2692 0 : if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2693 : {
2694 0 : if (! mem_mode
2695 : /* Refs inside notes or in DEBUG_INSNs don't count for
2696 : this purpose. */
2697 0 : && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2698 0 : || GET_CODE (insn) == INSN_LIST
2699 0 : || DEBUG_INSN_P (insn))))
2700 0 : ep->ref_outside_mem = 1;
2701 :
2702 0 : return
2703 0 : plus_constant (Pmode,
2704 0 : gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2705 0 : ep->previous_offset * INTVAL (XEXP (x, 1)));
2706 : }
2707 :
2708 : /* fall through */
2709 :
2710 0 : case CALL:
2711 0 : case COMPARE:
2712 : /* See comments before PLUS about handling MINUS. */
2713 0 : case MINUS:
2714 0 : case DIV: case UDIV:
2715 0 : case MOD: case UMOD:
2716 0 : case AND: case IOR: case XOR:
2717 0 : case ROTATERT: case ROTATE:
2718 0 : case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2719 0 : case NE: case EQ:
2720 0 : case GE: case GT: case GEU: case GTU:
2721 0 : case LE: case LT: case LEU: case LTU:
2722 0 : {
2723 0 : rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2724 : for_costs);
2725 0 : rtx new1 = XEXP (x, 1)
2726 0 : ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2727 : for_costs) : 0;
2728 :
2729 0 : if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2730 0 : return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2731 : }
2732 : return x;
2733 :
2734 0 : case EXPR_LIST:
2735 : /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2736 0 : if (XEXP (x, 0))
2737 : {
2738 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2739 : for_costs);
2740 0 : if (new_rtx != XEXP (x, 0))
2741 : {
2742 : /* If this is a REG_DEAD note, it is not valid anymore.
2743 : Using the eliminated version could result in creating a
2744 : REG_DEAD note for the stack or frame pointer. */
2745 0 : if (REG_NOTE_KIND (x) == REG_DEAD)
2746 0 : return (XEXP (x, 1)
2747 0 : ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2748 : for_costs)
2749 : : NULL_RTX);
2750 :
2751 0 : x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2752 : }
2753 : }
2754 :
2755 : /* fall through */
2756 :
2757 0 : case INSN_LIST:
2758 0 : case INT_LIST:
2759 : /* Now do eliminations in the rest of the chain. If this was
2760 : an EXPR_LIST, this might result in allocating more memory than is
2761 : strictly needed, but it simplifies the code. */
2762 0 : if (XEXP (x, 1))
2763 : {
2764 0 : new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2765 : for_costs);
2766 0 : if (new_rtx != XEXP (x, 1))
2767 0 : return
2768 0 : gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2769 : }
2770 : return x;
2771 :
2772 : case PRE_INC:
2773 : case POST_INC:
2774 : case PRE_DEC:
2775 : case POST_DEC:
2776 : /* We do not support elimination of a register that is modified.
2777 : elimination_effects has already make sure that this does not
2778 : happen. */
2779 : return x;
2780 :
2781 0 : case PRE_MODIFY:
2782 0 : case POST_MODIFY:
2783 : /* We do not support elimination of a register that is modified.
2784 : elimination_effects has already make sure that this does not
2785 : happen. The only remaining case we need to consider here is
2786 : that the increment value may be an eliminable register. */
2787 0 : if (GET_CODE (XEXP (x, 1)) == PLUS
2788 0 : && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2789 : {
2790 0 : rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2791 : insn, true, for_costs);
2792 :
2793 0 : if (new_rtx != XEXP (XEXP (x, 1), 1))
2794 0 : return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2795 : gen_rtx_PLUS (GET_MODE (x),
2796 : XEXP (x, 0), new_rtx));
2797 : }
2798 : return x;
2799 :
2800 0 : case STRICT_LOW_PART:
2801 0 : case NEG: case NOT:
2802 0 : case SIGN_EXTEND: case ZERO_EXTEND:
2803 0 : case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2804 0 : case FLOAT: case FIX:
2805 0 : case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2806 0 : case ABS:
2807 0 : case SQRT:
2808 0 : case FFS:
2809 0 : case CLZ:
2810 0 : case CTZ:
2811 0 : case POPCOUNT:
2812 0 : case PARITY:
2813 0 : case BSWAP:
2814 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2815 : for_costs);
2816 0 : if (new_rtx != XEXP (x, 0))
2817 0 : return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2818 : return x;
2819 :
2820 0 : case SUBREG:
2821 : /* Similar to above processing, but preserve SUBREG_BYTE.
2822 : Convert (subreg (mem)) to (mem) if not paradoxical.
2823 : Also, if we have a non-paradoxical (subreg (pseudo)) and the
2824 : pseudo didn't get a hard reg, we must replace this with the
2825 : eliminated version of the memory location because push_reload
2826 : may do the replacement in certain circumstances. */
2827 0 : if (REG_P (SUBREG_REG (x))
2828 0 : && !paradoxical_subreg_p (x)
2829 0 : && reg_equivs
2830 0 : && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2831 : {
2832 : new_rtx = SUBREG_REG (x);
2833 : }
2834 : else
2835 0 : new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2836 :
2837 0 : if (new_rtx != SUBREG_REG (x))
2838 : {
2839 0 : poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x));
2840 0 : poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2841 :
2842 0 : if (MEM_P (new_rtx)
2843 0 : && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx))
2844 : /* On RISC machines, combine can create rtl of the form
2845 : (set (subreg:m1 (reg:m2 R) 0) ...)
2846 : where m1 < m2, and expects something interesting to
2847 : happen to the entire word. Moreover, it will use the
2848 : (reg:m2 R) later, expecting all bits to be preserved.
2849 : So if the number of words is the same, preserve the
2850 : subreg so that push_reload can see it. */
2851 : && !(WORD_REGISTER_OPERATIONS
2852 : && known_equal_after_align_down (x_size - 1,
2853 : new_size - 1,
2854 : UNITS_PER_WORD)))
2855 0 : || known_eq (x_size, new_size))
2856 : )
2857 0 : return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2858 0 : else if (insn && GET_CODE (insn) == DEBUG_INSN)
2859 0 : return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2860 : else
2861 0 : return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2862 : }
2863 :
2864 : return x;
2865 :
2866 0 : case MEM:
2867 : /* Our only special processing is to pass the mode of the MEM to our
2868 : recursive call and copy the flags. While we are here, handle this
2869 : case more efficiently. */
2870 :
2871 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2872 : for_costs);
2873 0 : if (for_costs
2874 0 : && memory_address_p (GET_MODE (x), XEXP (x, 0))
2875 0 : && !memory_address_p (GET_MODE (x), new_rtx))
2876 0 : note_reg_elim_costly (XEXP (x, 0), insn);
2877 :
2878 0 : return replace_equiv_address_nv (x, new_rtx);
2879 :
2880 0 : case USE:
2881 : /* Handle insn_list USE that a call to a pure function may generate. */
2882 0 : new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2883 : for_costs);
2884 0 : if (new_rtx != XEXP (x, 0))
2885 0 : return gen_rtx_USE (GET_MODE (x), new_rtx);
2886 : return x;
2887 :
2888 0 : case CLOBBER:
2889 0 : case ASM_OPERANDS:
2890 0 : gcc_assert (insn && DEBUG_INSN_P (insn));
2891 : break;
2892 :
2893 0 : case SET:
2894 0 : gcc_unreachable ();
2895 :
2896 : default:
2897 : break;
2898 : }
2899 :
2900 : /* Process each of our operands recursively. If any have changed, make a
2901 : copy of the rtx. */
2902 0 : fmt = GET_RTX_FORMAT (code);
2903 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2904 : {
2905 0 : if (*fmt == 'e')
2906 : {
2907 0 : new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2908 : for_costs);
2909 0 : if (new_rtx != XEXP (x, i) && ! copied)
2910 : {
2911 0 : x = shallow_copy_rtx (x);
2912 0 : copied = 1;
2913 : }
2914 0 : XEXP (x, i) = new_rtx;
2915 : }
2916 0 : else if (*fmt == 'E')
2917 : {
2918 : int copied_vec = 0;
2919 0 : for (j = 0; j < XVECLEN (x, i); j++)
2920 : {
2921 0 : new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2922 : for_costs);
2923 0 : if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2924 : {
2925 0 : rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2926 0 : XVEC (x, i)->elem);
2927 0 : if (! copied)
2928 : {
2929 0 : x = shallow_copy_rtx (x);
2930 0 : copied = 1;
2931 : }
2932 0 : XVEC (x, i) = new_v;
2933 0 : copied_vec = 1;
2934 : }
2935 0 : XVECEXP (x, i, j) = new_rtx;
2936 : }
2937 : }
2938 : }
2939 :
2940 : return x;
2941 : }
2942 :
2943 : rtx
2944 0 : eliminate_regs (rtx x, machine_mode mem_mode, rtx insn)
2945 : {
2946 0 : if (reg_eliminate == NULL)
2947 : {
2948 0 : gcc_assert (targetm.no_register_allocation);
2949 : return x;
2950 : }
2951 0 : return eliminate_regs_1 (x, mem_mode, insn, false, false);
2952 : }
2953 :
2954 : /* Scan rtx X for modifications of elimination target registers. Update
2955 : the table of eliminables to reflect the changed state. MEM_MODE is
2956 : the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2957 :
2958 : static void
2959 0 : elimination_effects (rtx x, machine_mode mem_mode)
2960 : {
2961 0 : enum rtx_code code = GET_CODE (x);
2962 0 : struct elim_table *ep;
2963 0 : int regno;
2964 0 : int i, j;
2965 0 : const char *fmt;
2966 :
2967 0 : switch (code)
2968 : {
2969 : CASE_CONST_ANY:
2970 : case CONST:
2971 : case SYMBOL_REF:
2972 : case CODE_LABEL:
2973 : case PC:
2974 : case ASM_INPUT:
2975 : case ADDR_VEC:
2976 : case ADDR_DIFF_VEC:
2977 : case RETURN:
2978 : return;
2979 :
2980 0 : case REG:
2981 0 : regno = REGNO (x);
2982 :
2983 : /* First handle the case where we encounter a bare register that
2984 : is eliminable. Replace it with a PLUS. */
2985 0 : if (regno < FIRST_PSEUDO_REGISTER)
2986 : {
2987 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2988 : ep++)
2989 0 : if (ep->from_rtx == x && ep->can_eliminate)
2990 : {
2991 0 : if (! mem_mode)
2992 0 : ep->ref_outside_mem = 1;
2993 : return;
2994 : }
2995 :
2996 : }
2997 0 : else if (reg_renumber[regno] < 0
2998 0 : && reg_equivs
2999 0 : && reg_equiv_constant (regno)
3000 0 : && ! function_invariant_p (reg_equiv_constant (regno)))
3001 0 : elimination_effects (reg_equiv_constant (regno), mem_mode);
3002 : return;
3003 :
3004 0 : case PRE_INC:
3005 0 : case POST_INC:
3006 0 : case PRE_DEC:
3007 0 : case POST_DEC:
3008 0 : case POST_MODIFY:
3009 0 : case PRE_MODIFY:
3010 : /* If we modify the source of an elimination rule, disable it. */
3011 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3012 0 : if (ep->from_rtx == XEXP (x, 0))
3013 0 : ep->can_eliminate = 0;
3014 :
3015 : /* If we modify the target of an elimination rule by adding a constant,
3016 : update its offset. If we modify the target in any other way, we'll
3017 : have to disable the rule as well. */
3018 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3019 0 : if (ep->to_rtx == XEXP (x, 0))
3020 : {
3021 0 : poly_int64 size = GET_MODE_SIZE (mem_mode);
3022 :
3023 : /* If more bytes than MEM_MODE are pushed, account for them. */
3024 : #ifdef PUSH_ROUNDING
3025 0 : if (ep->to_rtx == stack_pointer_rtx)
3026 0 : size = PUSH_ROUNDING (size);
3027 : #endif
3028 0 : if (code == PRE_DEC || code == POST_DEC)
3029 0 : ep->offset += size;
3030 0 : else if (code == PRE_INC || code == POST_INC)
3031 0 : ep->offset -= size;
3032 0 : else if (code == PRE_MODIFY || code == POST_MODIFY)
3033 : {
3034 0 : if (GET_CODE (XEXP (x, 1)) == PLUS
3035 0 : && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3036 0 : && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3037 0 : ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3038 : else
3039 0 : ep->can_eliminate = 0;
3040 : }
3041 : }
3042 :
3043 : /* These two aren't unary operators. */
3044 0 : if (code == POST_MODIFY || code == PRE_MODIFY)
3045 : break;
3046 :
3047 : /* Fall through to generic unary operation case. */
3048 0 : gcc_fallthrough ();
3049 0 : case STRICT_LOW_PART:
3050 0 : case NEG: case NOT:
3051 0 : case SIGN_EXTEND: case ZERO_EXTEND:
3052 0 : case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3053 0 : case FLOAT: case FIX:
3054 0 : case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3055 0 : case ABS:
3056 0 : case SQRT:
3057 0 : case FFS:
3058 0 : case CLZ:
3059 0 : case CTZ:
3060 0 : case POPCOUNT:
3061 0 : case PARITY:
3062 0 : case BSWAP:
3063 0 : elimination_effects (XEXP (x, 0), mem_mode);
3064 0 : return;
3065 :
3066 0 : case SUBREG:
3067 0 : if (REG_P (SUBREG_REG (x))
3068 0 : && !paradoxical_subreg_p (x)
3069 0 : && reg_equivs
3070 0 : && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3071 : return;
3072 :
3073 : elimination_effects (SUBREG_REG (x), mem_mode);
3074 : return;
3075 :
3076 0 : case USE:
3077 : /* If using a register that is the source of an eliminate we still
3078 : think can be performed, note it cannot be performed since we don't
3079 : know how this register is used. */
3080 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3081 0 : if (ep->from_rtx == XEXP (x, 0))
3082 0 : ep->can_eliminate = 0;
3083 :
3084 0 : elimination_effects (XEXP (x, 0), mem_mode);
3085 0 : return;
3086 :
3087 0 : case CLOBBER:
3088 : /* If clobbering a register that is the replacement register for an
3089 : elimination we still think can be performed, note that it cannot
3090 : be performed. Otherwise, we need not be concerned about it. */
3091 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3092 0 : if (ep->to_rtx == XEXP (x, 0))
3093 0 : ep->can_eliminate = 0;
3094 :
3095 0 : elimination_effects (XEXP (x, 0), mem_mode);
3096 0 : return;
3097 :
3098 0 : case SET:
3099 : /* Check for setting a register that we know about. */
3100 0 : if (REG_P (SET_DEST (x)))
3101 : {
3102 : /* See if this is setting the replacement register for an
3103 : elimination.
3104 :
3105 : If DEST is the hard frame pointer, we do nothing because we
3106 : assume that all assignments to the frame pointer are for
3107 : non-local gotos and are being done at a time when they are valid
3108 : and do not disturb anything else. Some machines want to
3109 : eliminate a fake argument pointer (or even a fake frame pointer)
3110 : with either the real frame or the stack pointer. Assignments to
3111 : the hard frame pointer must not prevent this elimination. */
3112 :
3113 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3114 : ep++)
3115 0 : if (ep->to_rtx == SET_DEST (x)
3116 0 : && SET_DEST (x) != hard_frame_pointer_rtx)
3117 : {
3118 : /* If it is being incremented, adjust the offset. Otherwise,
3119 : this elimination can't be done. */
3120 0 : rtx src = SET_SRC (x);
3121 :
3122 0 : if (GET_CODE (src) == PLUS
3123 0 : && XEXP (src, 0) == SET_DEST (x)
3124 0 : && CONST_INT_P (XEXP (src, 1)))
3125 0 : ep->offset -= INTVAL (XEXP (src, 1));
3126 : else
3127 0 : ep->can_eliminate = 0;
3128 : }
3129 : }
3130 :
3131 0 : elimination_effects (SET_DEST (x), VOIDmode);
3132 0 : elimination_effects (SET_SRC (x), VOIDmode);
3133 0 : return;
3134 :
3135 0 : case MEM:
3136 : /* Our only special processing is to pass the mode of the MEM to our
3137 : recursive call. */
3138 0 : elimination_effects (XEXP (x, 0), GET_MODE (x));
3139 0 : return;
3140 :
3141 : default:
3142 : break;
3143 : }
3144 :
3145 0 : fmt = GET_RTX_FORMAT (code);
3146 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3147 : {
3148 0 : if (*fmt == 'e')
3149 0 : elimination_effects (XEXP (x, i), mem_mode);
3150 0 : else if (*fmt == 'E')
3151 0 : for (j = 0; j < XVECLEN (x, i); j++)
3152 0 : elimination_effects (XVECEXP (x, i, j), mem_mode);
3153 : }
3154 : }
3155 :
3156 : /* Descend through rtx X and verify that no references to eliminable registers
3157 : remain. If any do remain, mark the involved register as not
3158 : eliminable. */
3159 :
3160 : static void
3161 0 : check_eliminable_occurrences (rtx x)
3162 : {
3163 0 : const char *fmt;
3164 0 : int i;
3165 0 : enum rtx_code code;
3166 :
3167 0 : if (x == 0)
3168 : return;
3169 :
3170 0 : code = GET_CODE (x);
3171 :
3172 0 : if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3173 : {
3174 0 : struct elim_table *ep;
3175 :
3176 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3177 0 : if (ep->from_rtx == x)
3178 0 : ep->can_eliminate = 0;
3179 : return;
3180 : }
3181 :
3182 0 : fmt = GET_RTX_FORMAT (code);
3183 0 : for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3184 : {
3185 0 : if (*fmt == 'e')
3186 0 : check_eliminable_occurrences (XEXP (x, i));
3187 0 : else if (*fmt == 'E')
3188 : {
3189 : int j;
3190 0 : for (j = 0; j < XVECLEN (x, i); j++)
3191 0 : check_eliminable_occurrences (XVECEXP (x, i, j));
3192 : }
3193 : }
3194 : }
3195 :
3196 : /* Scan INSN and eliminate all eliminable registers in it.
3197 :
3198 : If REPLACE is nonzero, do the replacement destructively. Also
3199 : delete the insn as dead it if it is setting an eliminable register.
3200 :
3201 : If REPLACE is zero, do all our allocations in reload_obstack.
3202 :
3203 : If no eliminations were done and this insn doesn't require any elimination
3204 : processing (these are not identical conditions: it might be updating sp,
3205 : but not referencing fp; this needs to be seen during reload_as_needed so
3206 : that the offset between fp and sp can be taken into consideration), zero
3207 : is returned. Otherwise, 1 is returned. */
3208 :
3209 : static int
3210 0 : eliminate_regs_in_insn (rtx_insn *insn, int replace)
3211 : {
3212 0 : int icode = recog_memoized (insn);
3213 0 : rtx old_body = PATTERN (insn);
3214 0 : int insn_is_asm = asm_noperands (old_body) >= 0;
3215 0 : rtx old_set = single_set (insn);
3216 0 : rtx new_body;
3217 0 : int val = 0;
3218 0 : int i;
3219 0 : rtx substed_operand[MAX_RECOG_OPERANDS];
3220 0 : rtx orig_operand[MAX_RECOG_OPERANDS];
3221 0 : struct elim_table *ep;
3222 0 : rtx plus_src, plus_cst_src;
3223 :
3224 0 : if (! insn_is_asm && icode < 0)
3225 : {
3226 0 : gcc_assert (DEBUG_INSN_P (insn)
3227 : || GET_CODE (PATTERN (insn)) == USE
3228 : || GET_CODE (PATTERN (insn)) == CLOBBER
3229 : || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3230 0 : if (DEBUG_BIND_INSN_P (insn))
3231 0 : INSN_VAR_LOCATION_LOC (insn)
3232 0 : = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3233 : return 0;
3234 : }
3235 :
3236 : /* We allow one special case which happens to work on all machines we
3237 : currently support: a single set with the source or a REG_EQUAL
3238 : note being a PLUS of an eliminable register and a constant. */
3239 0 : plus_src = plus_cst_src = 0;
3240 0 : if (old_set && REG_P (SET_DEST (old_set)))
3241 : {
3242 0 : if (GET_CODE (SET_SRC (old_set)) == PLUS)
3243 0 : plus_src = SET_SRC (old_set);
3244 : /* First see if the source is of the form (plus (...) CST). */
3245 0 : if (plus_src
3246 0 : && CONST_INT_P (XEXP (plus_src, 1)))
3247 : plus_cst_src = plus_src;
3248 0 : else if (REG_P (SET_SRC (old_set))
3249 0 : || plus_src)
3250 : {
3251 : /* Otherwise, see if we have a REG_EQUAL note of the form
3252 : (plus (...) CST). */
3253 0 : rtx links;
3254 0 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3255 : {
3256 0 : if ((REG_NOTE_KIND (links) == REG_EQUAL
3257 0 : || REG_NOTE_KIND (links) == REG_EQUIV)
3258 0 : && GET_CODE (XEXP (links, 0)) == PLUS
3259 0 : && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3260 : {
3261 : plus_cst_src = XEXP (links, 0);
3262 : break;
3263 : }
3264 : }
3265 : }
3266 :
3267 : /* Check that the first operand of the PLUS is a hard reg or
3268 : the lowpart subreg of one. */
3269 0 : if (plus_cst_src)
3270 : {
3271 0 : rtx reg = XEXP (plus_cst_src, 0);
3272 0 : if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3273 0 : reg = SUBREG_REG (reg);
3274 :
3275 0 : if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3276 : plus_cst_src = 0;
3277 : }
3278 : }
3279 0 : if (plus_cst_src)
3280 : {
3281 0 : rtx reg = XEXP (plus_cst_src, 0);
3282 0 : poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
3283 :
3284 0 : if (GET_CODE (reg) == SUBREG)
3285 0 : reg = SUBREG_REG (reg);
3286 :
3287 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3288 0 : if (ep->from_rtx == reg && ep->can_eliminate)
3289 : {
3290 0 : rtx to_rtx = ep->to_rtx;
3291 0 : offset += ep->offset;
3292 0 : offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3293 :
3294 0 : if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3295 0 : to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3296 : to_rtx);
3297 : /* If we have a nonzero offset, and the source is already
3298 : a simple REG, the following transformation would
3299 : increase the cost of the insn by replacing a simple REG
3300 : with (plus (reg sp) CST). So try only when we already
3301 : had a PLUS before. */
3302 0 : if (known_eq (offset, 0) || plus_src)
3303 : {
3304 0 : rtx new_src = plus_constant (GET_MODE (to_rtx),
3305 : to_rtx, offset);
3306 :
3307 0 : new_body = old_body;
3308 0 : if (! replace)
3309 : {
3310 0 : new_body = copy_insn (old_body);
3311 0 : if (REG_NOTES (insn))
3312 0 : REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3313 : }
3314 0 : PATTERN (insn) = new_body;
3315 0 : old_set = single_set (insn);
3316 :
3317 : /* First see if this insn remains valid when we make the
3318 : change. If not, try to replace the whole pattern with
3319 : a simple set (this may help if the original insn was a
3320 : PARALLEL that was only recognized as single_set due to
3321 : REG_UNUSED notes). If this isn't valid either, keep
3322 : the INSN_CODE the same and let reload fix it up. */
3323 0 : if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3324 : {
3325 0 : rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
3326 :
3327 0 : if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3328 0 : SET_SRC (old_set) = new_src;
3329 : }
3330 : }
3331 : else
3332 : break;
3333 :
3334 0 : val = 1;
3335 : /* This can't have an effect on elimination offsets, so skip right
3336 : to the end. */
3337 0 : goto done;
3338 : }
3339 : }
3340 :
3341 : /* Determine the effects of this insn on elimination offsets. */
3342 0 : elimination_effects (old_body, VOIDmode);
3343 :
3344 : /* Eliminate all eliminable registers occurring in operands that
3345 : can be handled by reload. */
3346 0 : extract_insn (insn);
3347 0 : for (i = 0; i < recog_data.n_operands; i++)
3348 : {
3349 0 : orig_operand[i] = recog_data.operand[i];
3350 0 : substed_operand[i] = recog_data.operand[i];
3351 :
3352 : /* For an asm statement, every operand is eliminable. */
3353 0 : if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3354 : {
3355 0 : bool is_set_src, in_plus;
3356 :
3357 : /* Check for setting a register that we know about. */
3358 0 : if (recog_data.operand_type[i] != OP_IN
3359 0 : && REG_P (orig_operand[i]))
3360 : {
3361 : /* If we are assigning to a register that can be eliminated, it
3362 : must be as part of a PARALLEL, since the code above handles
3363 : single SETs. We must indicate that we can no longer
3364 : eliminate this reg. */
3365 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3366 : ep++)
3367 0 : if (ep->from_rtx == orig_operand[i])
3368 0 : ep->can_eliminate = 0;
3369 : }
3370 :
3371 : /* Companion to the above plus substitution, we can allow
3372 : invariants as the source of a plain move. */
3373 0 : is_set_src = false;
3374 0 : if (old_set
3375 0 : && recog_data.operand_loc[i] == &SET_SRC (old_set))
3376 0 : is_set_src = true;
3377 0 : in_plus = false;
3378 0 : if (plus_src
3379 0 : && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3380 0 : || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3381 0 : in_plus = true;
3382 :
3383 0 : substed_operand[i]
3384 0 : = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3385 : replace ? insn : NULL_RTX,
3386 : is_set_src || in_plus, false);
3387 0 : if (substed_operand[i] != orig_operand[i])
3388 0 : val = 1;
3389 : /* Terminate the search in check_eliminable_occurrences at
3390 : this point. */
3391 0 : *recog_data.operand_loc[i] = 0;
3392 :
3393 : /* If an output operand changed from a REG to a MEM and INSN is an
3394 : insn, write a CLOBBER insn. */
3395 0 : if (recog_data.operand_type[i] != OP_IN
3396 0 : && REG_P (orig_operand[i])
3397 0 : && MEM_P (substed_operand[i])
3398 0 : && replace)
3399 0 : emit_insn_after (gen_clobber (orig_operand[i]), insn);
3400 : }
3401 : }
3402 :
3403 0 : for (i = 0; i < recog_data.n_dups; i++)
3404 0 : *recog_data.dup_loc[i]
3405 0 : = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3406 :
3407 : /* If any eliminable remain, they aren't eliminable anymore. */
3408 0 : check_eliminable_occurrences (old_body);
3409 :
3410 : /* Substitute the operands; the new values are in the substed_operand
3411 : array. */
3412 0 : for (i = 0; i < recog_data.n_operands; i++)
3413 0 : *recog_data.operand_loc[i] = substed_operand[i];
3414 0 : for (i = 0; i < recog_data.n_dups; i++)
3415 0 : *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3416 :
3417 : /* If we are replacing a body that was a (set X (plus Y Z)), try to
3418 : re-recognize the insn. We do this in case we had a simple addition
3419 : but now can do this as a load-address. This saves an insn in this
3420 : common case.
3421 : If re-recognition fails, the old insn code number will still be used,
3422 : and some register operands may have changed into PLUS expressions.
3423 : These will be handled by find_reloads by loading them into a register
3424 : again. */
3425 :
3426 0 : if (val)
3427 : {
3428 : /* If we aren't replacing things permanently and we changed something,
3429 : make another copy to ensure that all the RTL is new. Otherwise
3430 : things can go wrong if find_reload swaps commutative operands
3431 : and one is inside RTL that has been copied while the other is not. */
3432 0 : new_body = old_body;
3433 0 : if (! replace)
3434 : {
3435 0 : new_body = copy_insn (old_body);
3436 0 : if (REG_NOTES (insn))
3437 0 : REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3438 : }
3439 0 : PATTERN (insn) = new_body;
3440 :
3441 : /* If we had a move insn but now we don't, rerecognize it. This will
3442 : cause spurious re-recognition if the old move had a PARALLEL since
3443 : the new one still will, but we can't call single_set without
3444 : having put NEW_BODY into the insn and the re-recognition won't
3445 : hurt in this rare case. */
3446 : /* ??? Why this huge if statement - why don't we just rerecognize the
3447 : thing always? */
3448 0 : if (! insn_is_asm
3449 0 : && old_set != 0
3450 0 : && ((REG_P (SET_SRC (old_set))
3451 0 : && (GET_CODE (new_body) != SET
3452 0 : || !REG_P (SET_SRC (new_body))))
3453 : /* If this was a load from or store to memory, compare
3454 : the MEM in recog_data.operand to the one in the insn.
3455 : If they are not equal, then rerecognize the insn. */
3456 : || (old_set != 0
3457 0 : && ((MEM_P (SET_SRC (old_set))
3458 0 : && SET_SRC (old_set) != recog_data.operand[1])
3459 0 : || (MEM_P (SET_DEST (old_set))
3460 0 : && SET_DEST (old_set) != recog_data.operand[0])))
3461 : /* If this was an add insn before, rerecognize. */
3462 0 : || GET_CODE (SET_SRC (old_set)) == PLUS))
3463 : {
3464 0 : int new_icode = recog (PATTERN (insn), insn, 0);
3465 0 : if (new_icode >= 0)
3466 0 : INSN_CODE (insn) = new_icode;
3467 : }
3468 : }
3469 :
3470 : /* Restore the old body. If there were any changes to it, we made a copy
3471 : of it while the changes were still in place, so we'll correctly return
3472 : a modified insn below. */
3473 0 : if (! replace)
3474 : {
3475 : /* Restore the old body. */
3476 0 : for (i = 0; i < recog_data.n_operands; i++)
3477 : /* Restoring a top-level match_parallel would clobber the new_body
3478 : we installed in the insn. */
3479 0 : if (recog_data.operand_loc[i] != &PATTERN (insn))
3480 0 : *recog_data.operand_loc[i] = orig_operand[i];
3481 0 : for (i = 0; i < recog_data.n_dups; i++)
3482 0 : *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3483 : }
3484 :
3485 : /* Update all elimination pairs to reflect the status after the current
3486 : insn. The changes we make were determined by the earlier call to
3487 : elimination_effects.
3488 :
3489 : We also detect cases where register elimination cannot be done,
3490 : namely, if a register would be both changed and referenced outside a MEM
3491 : in the resulting insn since such an insn is often undefined and, even if
3492 : not, we cannot know what meaning will be given to it. Note that it is
3493 : valid to have a register used in an address in an insn that changes it
3494 : (presumably with a pre- or post-increment or decrement).
3495 :
3496 : If anything changes, return nonzero. */
3497 :
3498 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3499 : {
3500 0 : if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3501 0 : ep->can_eliminate = 0;
3502 :
3503 0 : ep->ref_outside_mem = 0;
3504 :
3505 0 : if (maybe_ne (ep->previous_offset, ep->offset))
3506 0 : val = 1;
3507 : }
3508 :
3509 0 : done:
3510 : /* If we changed something, perform elimination in REG_NOTES. This is
3511 : needed even when REPLACE is zero because a REG_DEAD note might refer
3512 : to a register that we eliminate and could cause a different number
3513 : of spill registers to be needed in the final reload pass than in
3514 : the pre-passes. */
3515 0 : if (val && REG_NOTES (insn) != 0)
3516 0 : REG_NOTES (insn)
3517 0 : = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3518 : false);
3519 :
3520 : return val;
3521 : }
3522 :
3523 : /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3524 : register allocator. INSN is the instruction we need to examine, we perform
3525 : eliminations in its operands and record cases where eliminating a reg with
3526 : an invariant equivalence would add extra cost. */
3527 :
3528 : #pragma GCC diagnostic push
3529 : #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3530 : static void
3531 0 : elimination_costs_in_insn (rtx_insn *insn)
3532 : {
3533 0 : int icode = recog_memoized (insn);
3534 0 : rtx old_body = PATTERN (insn);
3535 0 : int insn_is_asm = asm_noperands (old_body) >= 0;
3536 0 : rtx old_set = single_set (insn);
3537 0 : int i;
3538 0 : rtx orig_operand[MAX_RECOG_OPERANDS];
3539 0 : rtx orig_dup[MAX_RECOG_OPERANDS];
3540 0 : struct elim_table *ep;
3541 0 : rtx plus_src, plus_cst_src;
3542 0 : bool sets_reg_p;
3543 :
3544 0 : if (! insn_is_asm && icode < 0)
3545 : {
3546 0 : gcc_assert (DEBUG_INSN_P (insn)
3547 : || GET_CODE (PATTERN (insn)) == USE
3548 : || GET_CODE (PATTERN (insn)) == CLOBBER
3549 : || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3550 : return;
3551 : }
3552 :
3553 0 : if (old_set != 0 && REG_P (SET_DEST (old_set))
3554 0 : && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3555 : {
3556 : /* Check for setting an eliminable register. */
3557 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3558 0 : if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3559 : return;
3560 : }
3561 :
3562 : /* We allow one special case which happens to work on all machines we
3563 : currently support: a single set with the source or a REG_EQUAL
3564 : note being a PLUS of an eliminable register and a constant. */
3565 0 : plus_src = plus_cst_src = 0;
3566 0 : sets_reg_p = false;
3567 0 : if (old_set && REG_P (SET_DEST (old_set)))
3568 : {
3569 0 : sets_reg_p = true;
3570 0 : if (GET_CODE (SET_SRC (old_set)) == PLUS)
3571 0 : plus_src = SET_SRC (old_set);
3572 : /* First see if the source is of the form (plus (...) CST). */
3573 0 : if (plus_src
3574 0 : && CONST_INT_P (XEXP (plus_src, 1)))
3575 0 : plus_cst_src = plus_src;
3576 0 : else if (REG_P (SET_SRC (old_set))
3577 : || plus_src)
3578 : {
3579 : /* Otherwise, see if we have a REG_EQUAL note of the form
3580 : (plus (...) CST). */
3581 0 : rtx links;
3582 0 : for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3583 : {
3584 : if ((REG_NOTE_KIND (links) == REG_EQUAL
3585 : || REG_NOTE_KIND (links) == REG_EQUIV)
3586 : && GET_CODE (XEXP (links, 0)) == PLUS
3587 : && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3588 : {
3589 : plus_cst_src = XEXP (links, 0);
3590 : break;
3591 : }
3592 : }
3593 : }
3594 : }
3595 :
3596 : /* Determine the effects of this insn on elimination offsets. */
3597 0 : elimination_effects (old_body, VOIDmode);
3598 :
3599 : /* Eliminate all eliminable registers occurring in operands that
3600 : can be handled by reload. */
3601 0 : extract_insn (insn);
3602 0 : int n_dups = recog_data.n_dups;
3603 0 : for (i = 0; i < n_dups; i++)
3604 0 : orig_dup[i] = *recog_data.dup_loc[i];
3605 :
3606 0 : int n_operands = recog_data.n_operands;
3607 0 : for (i = 0; i < n_operands; i++)
3608 : {
3609 0 : orig_operand[i] = recog_data.operand[i];
3610 :
3611 : /* For an asm statement, every operand is eliminable. */
3612 0 : if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3613 : {
3614 0 : bool is_set_src, in_plus;
3615 :
3616 : /* Check for setting a register that we know about. */
3617 0 : if (recog_data.operand_type[i] != OP_IN
3618 0 : && REG_P (orig_operand[i]))
3619 : {
3620 : /* If we are assigning to a register that can be eliminated, it
3621 : must be as part of a PARALLEL, since the code above handles
3622 : single SETs. We must indicate that we can no longer
3623 : eliminate this reg. */
3624 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3625 : ep++)
3626 0 : if (ep->from_rtx == orig_operand[i])
3627 0 : ep->can_eliminate = 0;
3628 : }
3629 :
3630 : /* Companion to the above plus substitution, we can allow
3631 : invariants as the source of a plain move. */
3632 0 : is_set_src = false;
3633 0 : if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3634 0 : is_set_src = true;
3635 0 : if (is_set_src && !sets_reg_p)
3636 0 : note_reg_elim_costly (SET_SRC (old_set), insn);
3637 0 : in_plus = false;
3638 0 : if (plus_src && sets_reg_p
3639 0 : && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3640 0 : || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3641 0 : in_plus = true;
3642 :
3643 0 : eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3644 : NULL_RTX,
3645 : is_set_src || in_plus, true);
3646 : /* Terminate the search in check_eliminable_occurrences at
3647 : this point. */
3648 0 : *recog_data.operand_loc[i] = 0;
3649 : }
3650 : }
3651 :
3652 0 : for (i = 0; i < n_dups; i++)
3653 0 : *recog_data.dup_loc[i]
3654 0 : = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3655 :
3656 : /* If any eliminable remain, they aren't eliminable anymore. */
3657 0 : check_eliminable_occurrences (old_body);
3658 :
3659 : /* Restore the old body. */
3660 0 : for (i = 0; i < n_operands; i++)
3661 0 : *recog_data.operand_loc[i] = orig_operand[i];
3662 0 : for (i = 0; i < n_dups; i++)
3663 0 : *recog_data.dup_loc[i] = orig_dup[i];
3664 :
3665 : /* Update all elimination pairs to reflect the status after the current
3666 : insn. The changes we make were determined by the earlier call to
3667 : elimination_effects. */
3668 :
3669 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3670 : {
3671 0 : if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem)
3672 0 : ep->can_eliminate = 0;
3673 :
3674 0 : ep->ref_outside_mem = 0;
3675 : }
3676 :
3677 : return;
3678 : }
3679 : #pragma GCC diagnostic pop
3680 :
3681 : /* Loop through all elimination pairs.
3682 : Recalculate the number not at initial offset.
3683 :
3684 : Compute the maximum offset (minimum offset if the stack does not
3685 : grow downward) for each elimination pair. */
3686 :
3687 : static void
3688 0 : update_eliminable_offsets (void)
3689 : {
3690 0 : struct elim_table *ep;
3691 :
3692 0 : num_not_at_initial_offset = 0;
3693 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3694 : {
3695 0 : ep->previous_offset = ep->offset;
3696 0 : if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3697 0 : num_not_at_initial_offset++;
3698 : }
3699 0 : }
3700 :
3701 : /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3702 : replacement we currently believe is valid, mark it as not eliminable if X
3703 : modifies DEST in any way other than by adding a constant integer to it.
3704 :
3705 : If DEST is the frame pointer, we do nothing because we assume that
3706 : all assignments to the hard frame pointer are nonlocal gotos and are being
3707 : done at a time when they are valid and do not disturb anything else.
3708 : Some machines want to eliminate a fake argument pointer with either the
3709 : frame or stack pointer. Assignments to the hard frame pointer must not
3710 : prevent this elimination.
3711 :
3712 : Called via note_stores from reload before starting its passes to scan
3713 : the insns of the function. */
3714 :
3715 : static void
3716 0 : mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3717 : {
3718 0 : unsigned int i;
3719 :
3720 : /* A SUBREG of a hard register here is just changing its mode. We should
3721 : not see a SUBREG of an eliminable hard register, but check just in
3722 : case. */
3723 0 : if (GET_CODE (dest) == SUBREG)
3724 0 : dest = SUBREG_REG (dest);
3725 :
3726 0 : if (dest == hard_frame_pointer_rtx)
3727 : return;
3728 :
3729 0 : for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3730 0 : if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3731 0 : && (GET_CODE (x) != SET
3732 0 : || GET_CODE (SET_SRC (x)) != PLUS
3733 0 : || XEXP (SET_SRC (x), 0) != dest
3734 0 : || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3735 : {
3736 0 : reg_eliminate[i].can_eliminate_previous
3737 0 : = reg_eliminate[i].can_eliminate = 0;
3738 0 : num_eliminable--;
3739 : }
3740 : }
3741 :
3742 : /* Verify that the initial elimination offsets did not change since the
3743 : last call to set_initial_elim_offsets. This is used to catch cases
3744 : where something illegal happened during reload_as_needed that could
3745 : cause incorrect code to be generated if we did not check for it. */
3746 :
3747 : static bool
3748 0 : verify_initial_elim_offsets (void)
3749 : {
3750 0 : poly_int64 t;
3751 0 : struct elim_table *ep;
3752 :
3753 0 : if (!num_eliminable)
3754 : return true;
3755 :
3756 0 : targetm.compute_frame_layout ();
3757 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3758 : {
3759 0 : INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3760 0 : if (maybe_ne (t, ep->initial_offset))
3761 : return false;
3762 : }
3763 :
3764 : return true;
3765 : }
3766 :
3767 : /* Reset all offsets on eliminable registers to their initial values. */
3768 :
3769 : static void
3770 0 : set_initial_elim_offsets (void)
3771 : {
3772 0 : struct elim_table *ep = reg_eliminate;
3773 :
3774 0 : targetm.compute_frame_layout ();
3775 0 : for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3776 : {
3777 0 : INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3778 0 : ep->previous_offset = ep->offset = ep->initial_offset;
3779 : }
3780 :
3781 0 : num_not_at_initial_offset = 0;
3782 0 : }
3783 :
3784 : /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3785 :
3786 : static void
3787 0 : set_initial_eh_label_offset (rtx label)
3788 : {
3789 0 : set_label_offsets (label, NULL, 1);
3790 0 : }
3791 :
3792 : /* Initialize the known label offsets.
3793 : Set a known offset for each forced label to be at the initial offset
3794 : of each elimination. We do this because we assume that all
3795 : computed jumps occur from a location where each elimination is
3796 : at its initial offset.
3797 : For all other labels, show that we don't know the offsets. */
3798 :
3799 : static void
3800 0 : set_initial_label_offsets (void)
3801 : {
3802 0 : memset (offsets_known_at, 0, num_labels);
3803 :
3804 0 : unsigned int i;
3805 0 : rtx_insn *insn;
3806 0 : FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn)
3807 0 : set_label_offsets (insn, NULL, 1);
3808 :
3809 0 : for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ())
3810 0 : if (x->insn ())
3811 0 : set_label_offsets (x->insn (), NULL, 1);
3812 :
3813 0 : for_each_eh_label (set_initial_eh_label_offset);
3814 0 : }
3815 :
3816 : /* Set all elimination offsets to the known values for the code label given
3817 : by INSN. */
3818 :
3819 : static void
3820 0 : set_offsets_for_label (rtx_insn *insn)
3821 : {
3822 0 : unsigned int i;
3823 0 : int label_nr = CODE_LABEL_NUMBER (insn);
3824 0 : struct elim_table *ep;
3825 :
3826 0 : num_not_at_initial_offset = 0;
3827 0 : for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3828 : {
3829 0 : ep->offset = ep->previous_offset
3830 0 : = offsets_at[label_nr - first_label_num][i];
3831 0 : if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset))
3832 0 : num_not_at_initial_offset++;
3833 : }
3834 0 : }
3835 :
3836 : /* See if anything that happened changes which eliminations are valid.
3837 : For example, on the SPARC, whether or not the frame pointer can
3838 : be eliminated can depend on what registers have been used. We need
3839 : not check some conditions again (such as flag_omit_frame_pointer)
3840 : since they can't have changed. */
3841 :
3842 : static void
3843 0 : update_eliminables (HARD_REG_SET *pset)
3844 : {
3845 0 : int previous_frame_pointer_needed = frame_pointer_needed;
3846 0 : struct elim_table *ep;
3847 :
3848 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3849 0 : if ((ep->from == HARD_FRAME_POINTER_REGNUM
3850 0 : && targetm.frame_pointer_required ())
3851 0 : || ! targetm.can_eliminate (ep->from, ep->to)
3852 : )
3853 0 : ep->can_eliminate = 0;
3854 :
3855 : /* Look for the case where we have discovered that we can't replace
3856 : register A with register B and that means that we will now be
3857 : trying to replace register A with register C. This means we can
3858 : no longer replace register C with register B and we need to disable
3859 : such an elimination, if it exists. This occurs often with A == ap,
3860 : B == sp, and C == fp. */
3861 :
3862 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3863 : {
3864 0 : struct elim_table *op;
3865 0 : int new_to = -1;
3866 :
3867 0 : if (! ep->can_eliminate && ep->can_eliminate_previous)
3868 : {
3869 : /* Find the current elimination for ep->from, if there is a
3870 : new one. */
3871 0 : for (op = reg_eliminate;
3872 0 : op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3873 0 : if (op->from == ep->from && op->can_eliminate)
3874 : {
3875 0 : new_to = op->to;
3876 0 : break;
3877 : }
3878 :
3879 : /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3880 : disable it. */
3881 0 : for (op = reg_eliminate;
3882 0 : op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3883 0 : if (op->from == new_to && op->to == ep->to)
3884 0 : op->can_eliminate = 0;
3885 : }
3886 : }
3887 :
3888 : /* See if any registers that we thought we could eliminate the previous
3889 : time are no longer eliminable. If so, something has changed and we
3890 : must spill the register. Also, recompute the number of eliminable
3891 : registers and see if the frame pointer is needed; it is if there is
3892 : no elimination of the frame pointer that we can perform. */
3893 :
3894 0 : frame_pointer_needed = 1;
3895 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3896 : {
3897 0 : if (ep->can_eliminate
3898 0 : && ep->from == FRAME_POINTER_REGNUM
3899 0 : && ep->to != HARD_FRAME_POINTER_REGNUM
3900 0 : && (! SUPPORTS_STACK_ALIGNMENT
3901 0 : || ! crtl->stack_realign_needed))
3902 0 : frame_pointer_needed = 0;
3903 :
3904 0 : if (! ep->can_eliminate && ep->can_eliminate_previous)
3905 : {
3906 0 : ep->can_eliminate_previous = 0;
3907 0 : SET_HARD_REG_BIT (*pset, ep->from);
3908 0 : num_eliminable--;
3909 : }
3910 : }
3911 :
3912 : /* If we didn't need a frame pointer last time, but we do now, spill
3913 : the hard frame pointer. */
3914 0 : if (frame_pointer_needed && ! previous_frame_pointer_needed)
3915 0 : SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3916 0 : }
3917 :
3918 : /* Call update_eliminables an spill any registers we can't eliminate anymore.
3919 : Return true iff a register was spilled. */
3920 :
3921 : static bool
3922 0 : update_eliminables_and_spill (void)
3923 : {
3924 0 : unsigned int i;
3925 0 : bool did_spill = false;
3926 0 : HARD_REG_SET to_spill;
3927 0 : CLEAR_HARD_REG_SET (to_spill);
3928 0 : update_eliminables (&to_spill);
3929 0 : used_spill_regs &= ~to_spill;
3930 :
3931 0 : hard_reg_set_iterator hrsi;
3932 0 : EXECUTE_IF_SET_IN_HARD_REG_SET (to_spill, 0, i, hrsi)
3933 : {
3934 0 : spill_hard_reg (i, 1);
3935 0 : did_spill = true;
3936 :
3937 : /* Regardless of the state of spills, if we previously had
3938 : a register that we thought we could eliminate, but now
3939 : cannot eliminate, we must run another pass.
3940 :
3941 : Consider pseudos which have an entry in reg_equiv_* which
3942 : reference an eliminable register. We must make another pass
3943 : to update reg_equiv_* so that we do not substitute in the
3944 : old value from when we thought the elimination could be
3945 : performed. */
3946 : }
3947 0 : return did_spill;
3948 : }
3949 :
3950 : /* Return true if X is used as the target register of an elimination. */
3951 :
3952 : bool
3953 0 : elimination_target_reg_p (rtx x)
3954 : {
3955 0 : struct elim_table *ep;
3956 :
3957 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3958 0 : if (ep->to_rtx == x && ep->can_eliminate)
3959 : return true;
3960 :
3961 : return false;
3962 : }
3963 :
3964 : /* Initialize the table of registers to eliminate.
3965 : Pre-condition: global flag frame_pointer_needed has been set before
3966 : calling this function. */
3967 :
3968 : static void
3969 0 : init_elim_table (void)
3970 : {
3971 0 : struct elim_table *ep;
3972 0 : const struct elim_table_1 *ep1;
3973 :
3974 0 : if (!reg_eliminate)
3975 0 : reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3976 :
3977 0 : num_eliminable = 0;
3978 :
3979 0 : for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3980 0 : ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3981 : {
3982 0 : ep->from = ep1->from;
3983 0 : ep->to = ep1->to;
3984 0 : ep->can_eliminate = ep->can_eliminate_previous
3985 0 : = (targetm.can_eliminate (ep->from, ep->to)
3986 0 : && ! (ep->to == STACK_POINTER_REGNUM
3987 0 : && frame_pointer_needed
3988 0 : && (! SUPPORTS_STACK_ALIGNMENT
3989 0 : || ! stack_realign_fp)));
3990 : }
3991 :
3992 : /* Count the number of eliminable registers and build the FROM and TO
3993 : REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3994 : gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3995 : We depend on this. */
3996 0 : for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3997 : {
3998 0 : num_eliminable += ep->can_eliminate;
3999 0 : ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4000 0 : ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4001 : }
4002 0 : }
4003 :
4004 : /* Find all the pseudo registers that didn't get hard regs
4005 : but do have known equivalent constants or memory slots.
4006 : These include parameters (known equivalent to parameter slots)
4007 : and cse'd or loop-moved constant memory addresses.
4008 :
4009 : Record constant equivalents in reg_equiv_constant
4010 : so they will be substituted by find_reloads.
4011 : Record memory equivalents in reg_mem_equiv so they can
4012 : be substituted eventually by altering the REG-rtx's. */
4013 :
4014 : static void
4015 0 : init_eliminable_invariants (rtx_insn *first, bool do_subregs)
4016 : {
4017 0 : int i;
4018 0 : rtx_insn *insn;
4019 :
4020 0 : grow_reg_equivs ();
4021 0 : if (do_subregs)
4022 0 : reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno);
4023 : else
4024 : reg_max_ref_mode = NULL;
4025 :
4026 0 : num_eliminable_invariants = 0;
4027 :
4028 0 : first_label_num = get_first_label_num ();
4029 0 : num_labels = max_label_num () - first_label_num;
4030 :
4031 : /* Allocate the tables used to store offset information at labels. */
4032 0 : offsets_known_at = XNEWVEC (char, num_labels);
4033 0 : offsets_at = (poly_int64 (*)[NUM_ELIMINABLE_REGS])
4034 0 : xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64));
4035 :
4036 : /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4037 : to. If DO_SUBREGS is true, also find all paradoxical subregs and
4038 : find largest such for each pseudo. FIRST is the head of the insn
4039 : list. */
4040 :
4041 0 : for (insn = first; insn; insn = NEXT_INSN (insn))
4042 : {
4043 0 : rtx set = single_set (insn);
4044 :
4045 : /* We may introduce USEs that we want to remove at the end, so
4046 : we'll mark them with QImode. Make sure there are no
4047 : previously-marked insns left by say regmove. */
4048 0 : if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4049 0 : && GET_MODE (insn) != VOIDmode)
4050 0 : PUT_MODE (insn, VOIDmode);
4051 :
4052 0 : if (do_subregs && NONDEBUG_INSN_P (insn))
4053 0 : scan_paradoxical_subregs (PATTERN (insn));
4054 :
4055 0 : if (set != 0 && REG_P (SET_DEST (set)))
4056 : {
4057 0 : rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4058 0 : rtx x;
4059 :
4060 0 : if (! note)
4061 0 : continue;
4062 :
4063 0 : i = REGNO (SET_DEST (set));
4064 0 : x = XEXP (note, 0);
4065 :
4066 0 : if (i <= LAST_VIRTUAL_REGISTER)
4067 0 : continue;
4068 :
4069 : /* If flag_pic and we have constant, verify it's legitimate. */
4070 0 : if (!CONSTANT_P (x)
4071 0 : || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4072 : {
4073 : /* It can happen that a REG_EQUIV note contains a MEM
4074 : that is not a legitimate memory operand. As later
4075 : stages of reload assume that all addresses found
4076 : in the reg_equiv_* arrays were originally legitimate,
4077 : we ignore such REG_EQUIV notes. */
4078 0 : if (memory_operand (x, VOIDmode))
4079 : {
4080 : /* Always unshare the equivalence, so we can
4081 : substitute into this insn without touching the
4082 : equivalence. */
4083 0 : reg_equiv_memory_loc (i) = copy_rtx (x);
4084 : }
4085 0 : else if (function_invariant_p (x))
4086 : {
4087 0 : machine_mode mode;
4088 :
4089 0 : mode = GET_MODE (SET_DEST (set));
4090 0 : if (GET_CODE (x) == PLUS)
4091 : {
4092 : /* This is PLUS of frame pointer and a constant,
4093 : and might be shared. Unshare it. */
4094 0 : reg_equiv_invariant (i) = copy_rtx (x);
4095 0 : num_eliminable_invariants++;
4096 : }
4097 0 : else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4098 : {
4099 0 : reg_equiv_invariant (i) = x;
4100 0 : num_eliminable_invariants++;
4101 : }
4102 0 : else if (targetm.legitimate_constant_p (mode, x))
4103 0 : reg_equiv_constant (i) = x;
4104 : else
4105 : {
4106 0 : reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4107 0 : if (! reg_equiv_memory_loc (i))
4108 0 : reg_equiv_init (i) = NULL;
4109 : }
4110 : }
4111 : else
4112 : {
4113 0 : reg_equiv_init (i) = NULL;
4114 0 : continue;
4115 : }
4116 : }
4117 : else
4118 0 : reg_equiv_init (i) = NULL;
4119 : }
4120 : }
4121 :
4122 0 : if (dump_file)
4123 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4124 0 : if (reg_equiv_init (i))
4125 : {
4126 0 : fprintf (dump_file, "init_insns for %u: ", i);
4127 0 : print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4128 0 : fprintf (dump_file, "\n");
4129 : }
4130 0 : }
4131 :
4132 : /* Indicate that we no longer have known memory locations or constants.
4133 : Free all data involved in tracking these. */
4134 :
4135 : static void
4136 0 : free_reg_equiv (void)
4137 : {
4138 0 : int i;
4139 :
4140 0 : free (offsets_known_at);
4141 0 : free (offsets_at);
4142 0 : offsets_at = 0;
4143 0 : offsets_known_at = 0;
4144 :
4145 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4146 0 : if (reg_equiv_alt_mem_list (i))
4147 0 : free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4148 0 : vec_free (reg_equivs);
4149 0 : }
4150 :
4151 : /* Kick all pseudos out of hard register REGNO.
4152 :
4153 : If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4154 : because we found we can't eliminate some register. In the case, no pseudos
4155 : are allowed to be in the register, even if they are only in a block that
4156 : doesn't require spill registers, unlike the case when we are spilling this
4157 : hard reg to produce another spill register.
4158 :
4159 : Return nonzero if any pseudos needed to be kicked out. */
4160 :
4161 : static void
4162 0 : spill_hard_reg (unsigned int regno, int cant_eliminate)
4163 : {
4164 0 : int i;
4165 :
4166 0 : if (cant_eliminate)
4167 : {
4168 0 : SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4169 0 : df_set_regs_ever_live (regno, true);
4170 : }
4171 :
4172 : /* Spill every pseudo reg that was allocated to this reg
4173 : or to something that overlaps this reg. */
4174 :
4175 0 : for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4176 0 : if (reg_renumber[i] >= 0
4177 0 : && (unsigned int) reg_renumber[i] <= regno
4178 0 : && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4179 0 : SET_REGNO_REG_SET (&spilled_pseudos, i);
4180 0 : }
4181 :
4182 : /* After spill_hard_reg was called and/or find_reload_regs was run for all
4183 : insns that need reloads, this function is used to actually spill pseudo
4184 : registers and try to reallocate them. It also sets up the spill_regs
4185 : array for use by choose_reload_regs.
4186 :
4187 : GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4188 : that we displace from hard registers. */
4189 :
4190 : static int
4191 0 : finish_spills (int global)
4192 : {
4193 0 : class insn_chain *chain;
4194 0 : int something_changed = 0;
4195 0 : unsigned i;
4196 0 : reg_set_iterator rsi;
4197 :
4198 : /* Build the spill_regs array for the function. */
4199 : /* If there are some registers still to eliminate and one of the spill regs
4200 : wasn't ever used before, additional stack space may have to be
4201 : allocated to store this register. Thus, we may have changed the offset
4202 : between the stack and frame pointers, so mark that something has changed.
4203 :
4204 : One might think that we need only set VAL to 1 if this is a call-used
4205 : register. However, the set of registers that must be saved by the
4206 : prologue is not identical to the call-used set. For example, the
4207 : register used by the call insn for the return PC is a call-used register,
4208 : but must be saved by the prologue. */
4209 :
4210 0 : n_spills = 0;
4211 0 : for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4212 0 : if (TEST_HARD_REG_BIT (used_spill_regs, i))
4213 : {
4214 0 : spill_reg_order[i] = n_spills;
4215 0 : spill_regs[n_spills++] = i;
4216 0 : if (num_eliminable && ! df_regs_ever_live_p (i))
4217 : something_changed = 1;
4218 0 : df_set_regs_ever_live (i, true);
4219 : }
4220 : else
4221 0 : spill_reg_order[i] = -1;
4222 :
4223 0 : EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4224 0 : if (reg_renumber[i] >= 0)
4225 : {
4226 0 : SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4227 : /* Mark it as no longer having a hard register home. */
4228 0 : reg_renumber[i] = -1;
4229 0 : if (ira_conflicts_p)
4230 : /* Inform IRA about the change. */
4231 0 : ira_mark_allocation_change (i);
4232 : /* We will need to scan everything again. */
4233 : something_changed = 1;
4234 : }
4235 :
4236 : /* Retry global register allocation if possible. */
4237 0 : if (global && ira_conflicts_p)
4238 : {
4239 0 : unsigned int n;
4240 :
4241 0 : memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4242 : /* For every insn that needs reloads, set the registers used as spill
4243 : regs in pseudo_forbidden_regs for every pseudo live across the
4244 : insn. */
4245 0 : for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4246 : {
4247 0 : EXECUTE_IF_SET_IN_REG_SET
4248 : (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4249 : {
4250 0 : pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4251 : }
4252 0 : EXECUTE_IF_SET_IN_REG_SET
4253 : (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4254 : {
4255 0 : pseudo_forbidden_regs[i] |= chain->used_spill_regs;
4256 : }
4257 : }
4258 :
4259 : /* Retry allocating the pseudos spilled in IRA and the
4260 : reload. For each reg, merge the various reg sets that
4261 : indicate which hard regs can't be used, and call
4262 : ira_reassign_pseudos. */
4263 0 : for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4264 0 : if (reg_old_renumber[i] != reg_renumber[i])
4265 : {
4266 0 : if (reg_renumber[i] < 0)
4267 0 : temp_pseudo_reg_arr[n++] = i;
4268 : else
4269 0 : CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4270 : }
4271 0 : if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4272 : bad_spill_regs_global,
4273 : pseudo_forbidden_regs, pseudo_previous_regs,
4274 : &spilled_pseudos))
4275 0 : something_changed = 1;
4276 : }
4277 : /* Fix up the register information in the insn chain.
4278 : This involves deleting those of the spilled pseudos which did not get
4279 : a new hard register home from the live_{before,after} sets. */
4280 0 : for (chain = reload_insn_chain; chain; chain = chain->next)
4281 : {
4282 0 : HARD_REG_SET used_by_pseudos;
4283 0 : HARD_REG_SET used_by_pseudos2;
4284 :
4285 0 : if (! ira_conflicts_p)
4286 : {
4287 : /* Don't do it for IRA because IRA and the reload still can
4288 : assign hard registers to the spilled pseudos on next
4289 : reload iterations. */
4290 0 : AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4291 0 : AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4292 : }
4293 : /* Mark any unallocated hard regs as available for spills. That
4294 : makes inheritance work somewhat better. */
4295 0 : if (chain->need_reload)
4296 : {
4297 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4298 0 : REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4299 0 : used_by_pseudos |= used_by_pseudos2;
4300 :
4301 0 : compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4302 0 : compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4303 : /* Value of chain->used_spill_regs from previous iteration
4304 : may be not included in the value calculated here because
4305 : of possible removing caller-saves insns (see function
4306 : delete_caller_save_insns. */
4307 0 : chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
4308 : }
4309 : }
4310 :
4311 0 : CLEAR_REG_SET (&changed_allocation_pseudos);
4312 : /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4313 0 : for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4314 : {
4315 0 : int regno = reg_renumber[i];
4316 0 : if (reg_old_renumber[i] == regno)
4317 0 : continue;
4318 :
4319 0 : SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4320 :
4321 0 : alter_reg (i, reg_old_renumber[i], false);
4322 0 : reg_old_renumber[i] = regno;
4323 0 : if (dump_file)
4324 : {
4325 0 : if (regno == -1)
4326 0 : fprintf (dump_file, " Register %d now on stack.\n\n", i);
4327 : else
4328 0 : fprintf (dump_file, " Register %d now in %d.\n\n",
4329 0 : i, reg_renumber[i]);
4330 : }
4331 : }
4332 :
4333 0 : return something_changed;
4334 : }
4335 :
4336 : /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4337 :
4338 : static void
4339 0 : scan_paradoxical_subregs (rtx x)
4340 : {
4341 0 : int i;
4342 0 : const char *fmt;
4343 0 : enum rtx_code code = GET_CODE (x);
4344 :
4345 0 : switch (code)
4346 : {
4347 : case REG:
4348 : case CONST:
4349 : case SYMBOL_REF:
4350 : case LABEL_REF:
4351 : CASE_CONST_ANY:
4352 : case PC:
4353 : case USE:
4354 : case CLOBBER:
4355 : return;
4356 :
4357 0 : case SUBREG:
4358 0 : if (REG_P (SUBREG_REG (x)))
4359 : {
4360 0 : unsigned int regno = REGNO (SUBREG_REG (x));
4361 0 : if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x)))
4362 : {
4363 0 : reg_max_ref_mode[regno] = GET_MODE (x);
4364 0 : mark_home_live_1 (regno, GET_MODE (x));
4365 : }
4366 : }
4367 : return;
4368 :
4369 0 : default:
4370 0 : break;
4371 : }
4372 :
4373 0 : fmt = GET_RTX_FORMAT (code);
4374 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4375 : {
4376 0 : if (fmt[i] == 'e')
4377 0 : scan_paradoxical_subregs (XEXP (x, i));
4378 0 : else if (fmt[i] == 'E')
4379 : {
4380 0 : int j;
4381 0 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4382 0 : scan_paradoxical_subregs (XVECEXP (x, i, j));
4383 : }
4384 : }
4385 : }
4386 :
4387 : /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4388 : If *OP_PTR is a paradoxical subreg, try to remove that subreg
4389 : and apply the corresponding narrowing subreg to *OTHER_PTR.
4390 : Return true if the operands were changed, false otherwise. */
4391 :
4392 : static bool
4393 0 : strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4394 : {
4395 0 : rtx op, inner, other, tem;
4396 :
4397 0 : op = *op_ptr;
4398 0 : if (!paradoxical_subreg_p (op))
4399 : return false;
4400 0 : inner = SUBREG_REG (op);
4401 :
4402 0 : other = *other_ptr;
4403 0 : tem = gen_lowpart_common (GET_MODE (inner), other);
4404 0 : if (!tem)
4405 : return false;
4406 :
4407 : /* If the lowpart operation turned a hard register into a subreg,
4408 : rather than simplifying it to another hard register, then the
4409 : mode change cannot be properly represented. For example, OTHER
4410 : might be valid in its current mode, but not in the new one. */
4411 0 : if (GET_CODE (tem) == SUBREG
4412 0 : && REG_P (other)
4413 0 : && HARD_REGISTER_P (other))
4414 : return false;
4415 :
4416 0 : *op_ptr = inner;
4417 0 : *other_ptr = tem;
4418 0 : return true;
4419 : }
4420 :
4421 : /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4422 : examine all of the reload insns between PREV and NEXT exclusive, and
4423 : annotate all that may trap. */
4424 :
4425 : static void
4426 0 : fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4427 : {
4428 0 : rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4429 0 : if (note == NULL)
4430 : return;
4431 0 : if (!insn_could_throw_p (insn))
4432 0 : remove_note (insn, note);
4433 0 : copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4434 : }
4435 :
4436 : /* Reload pseudo-registers into hard regs around each insn as needed.
4437 : Additional register load insns are output before the insn that needs it
4438 : and perhaps store insns after insns that modify the reloaded pseudo reg.
4439 :
4440 : reg_last_reload_reg and reg_reloaded_contents keep track of
4441 : which registers are already available in reload registers.
4442 : We update these for the reloads that we perform,
4443 : as the insns are scanned. */
4444 :
4445 : static void
4446 0 : reload_as_needed (int live_known)
4447 : {
4448 0 : class insn_chain *chain;
4449 : #if AUTO_INC_DEC
4450 : int i;
4451 : #endif
4452 0 : rtx_note *marker;
4453 :
4454 0 : memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4455 0 : memset (spill_reg_store, 0, sizeof spill_reg_store);
4456 0 : reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4457 0 : INIT_REG_SET (®_has_output_reload);
4458 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4459 :
4460 0 : set_initial_elim_offsets ();
4461 :
4462 : /* Generate a marker insn that we will move around. */
4463 0 : marker = emit_note (NOTE_INSN_DELETED);
4464 0 : unlink_insn_chain (marker, marker);
4465 :
4466 0 : for (chain = reload_insn_chain; chain; chain = chain->next)
4467 : {
4468 0 : rtx_insn *prev = 0;
4469 0 : rtx_insn *insn = chain->insn;
4470 0 : rtx_insn *old_next = NEXT_INSN (insn);
4471 : #if AUTO_INC_DEC
4472 : rtx_insn *old_prev = PREV_INSN (insn);
4473 : #endif
4474 :
4475 0 : if (will_delete_init_insn_p (insn))
4476 0 : continue;
4477 :
4478 : /* If we pass a label, copy the offsets from the label information
4479 : into the current offsets of each elimination. */
4480 0 : if (LABEL_P (insn))
4481 0 : set_offsets_for_label (insn);
4482 :
4483 0 : else if (INSN_P (insn))
4484 : {
4485 0 : regset_head regs_to_forget;
4486 0 : INIT_REG_SET (®s_to_forget);
4487 0 : note_stores (insn, forget_old_reloads_1, ®s_to_forget);
4488 :
4489 : /* If this is a USE and CLOBBER of a MEM, ensure that any
4490 : references to eliminable registers have been removed. */
4491 :
4492 0 : if ((GET_CODE (PATTERN (insn)) == USE
4493 0 : || GET_CODE (PATTERN (insn)) == CLOBBER)
4494 0 : && MEM_P (XEXP (PATTERN (insn), 0)))
4495 0 : XEXP (XEXP (PATTERN (insn), 0), 0)
4496 0 : = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4497 0 : GET_MODE (XEXP (PATTERN (insn), 0)),
4498 : NULL_RTX);
4499 :
4500 : /* If we need to do register elimination processing, do so.
4501 : This might delete the insn, in which case we are done. */
4502 0 : if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4503 : {
4504 0 : eliminate_regs_in_insn (insn, 1);
4505 0 : if (NOTE_P (insn))
4506 : {
4507 0 : update_eliminable_offsets ();
4508 0 : CLEAR_REG_SET (®s_to_forget);
4509 0 : continue;
4510 : }
4511 : }
4512 :
4513 : /* If need_elim is nonzero but need_reload is zero, one might think
4514 : that we could simply set n_reloads to 0. However, find_reloads
4515 : could have done some manipulation of the insn (such as swapping
4516 : commutative operands), and these manipulations are lost during
4517 : the first pass for every insn that needs register elimination.
4518 : So the actions of find_reloads must be redone here. */
4519 :
4520 0 : if (! chain->need_elim && ! chain->need_reload
4521 0 : && ! chain->need_operand_change)
4522 0 : n_reloads = 0;
4523 : /* First find the pseudo regs that must be reloaded for this insn.
4524 : This info is returned in the tables reload_... (see reload.h).
4525 : Also modify the body of INSN by substituting RELOAD
4526 : rtx's for those pseudo regs. */
4527 : else
4528 : {
4529 0 : CLEAR_REG_SET (®_has_output_reload);
4530 0 : CLEAR_HARD_REG_SET (reg_is_output_reload);
4531 :
4532 0 : find_reloads (insn, 1, spill_indirect_levels, live_known,
4533 : spill_reg_order);
4534 : }
4535 :
4536 0 : if (n_reloads > 0)
4537 : {
4538 0 : rtx_insn *next = NEXT_INSN (insn);
4539 :
4540 : /* ??? PREV can get deleted by reload inheritance.
4541 : Work around this by emitting a marker note. */
4542 0 : prev = PREV_INSN (insn);
4543 0 : reorder_insns_nobb (marker, marker, prev);
4544 :
4545 : /* Now compute which reload regs to reload them into. Perhaps
4546 : reusing reload regs from previous insns, or else output
4547 : load insns to reload them. Maybe output store insns too.
4548 : Record the choices of reload reg in reload_reg_rtx. */
4549 0 : choose_reload_regs (chain);
4550 :
4551 : /* Generate the insns to reload operands into or out of
4552 : their reload regs. */
4553 0 : emit_reload_insns (chain);
4554 :
4555 : /* Substitute the chosen reload regs from reload_reg_rtx
4556 : into the insn's body (or perhaps into the bodies of other
4557 : load and store insn that we just made for reloading
4558 : and that we moved the structure into). */
4559 0 : subst_reloads (insn);
4560 :
4561 0 : prev = PREV_INSN (marker);
4562 0 : unlink_insn_chain (marker, marker);
4563 :
4564 : /* Adjust the exception region notes for loads and stores. */
4565 0 : if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4566 0 : fixup_eh_region_note (insn, prev, next);
4567 :
4568 : /* Adjust the location of REG_ARGS_SIZE. */
4569 0 : rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4570 0 : if (p)
4571 : {
4572 0 : remove_note (insn, p);
4573 0 : fixup_args_size_notes (prev, PREV_INSN (next),
4574 : get_args_size (p));
4575 : }
4576 :
4577 : /* If this was an ASM, make sure that all the reload insns
4578 : we have generated are valid. If not, give an error
4579 : and delete them. */
4580 0 : if (asm_noperands (PATTERN (insn)) >= 0)
4581 0 : for (rtx_insn *p = NEXT_INSN (prev);
4582 0 : p != next;
4583 0 : p = NEXT_INSN (p))
4584 0 : if (p != insn && INSN_P (p)
4585 0 : && GET_CODE (PATTERN (p)) != USE
4586 0 : && (recog_memoized (p) < 0
4587 0 : || (extract_insn (p),
4588 0 : !(constrain_operands (1,
4589 : get_enabled_alternatives (p))))))
4590 : {
4591 0 : error_for_asm (insn,
4592 : "%<asm%> operand requires "
4593 : "impossible reload");
4594 0 : delete_insn (p);
4595 : }
4596 : }
4597 :
4598 0 : if (num_eliminable && chain->need_elim)
4599 0 : update_eliminable_offsets ();
4600 :
4601 : /* Any previously reloaded spilled pseudo reg, stored in this insn,
4602 : is no longer validly lying around to save a future reload.
4603 : Note that this does not detect pseudos that were reloaded
4604 : for this insn in order to be stored in
4605 : (obeying register constraints). That is correct; such reload
4606 : registers ARE still valid. */
4607 0 : forget_marked_reloads (®s_to_forget);
4608 0 : CLEAR_REG_SET (®s_to_forget);
4609 :
4610 : /* There may have been CLOBBER insns placed after INSN. So scan
4611 : between INSN and NEXT and use them to forget old reloads. */
4612 0 : for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4613 0 : if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4614 0 : note_stores (x, forget_old_reloads_1, NULL);
4615 :
4616 : #if AUTO_INC_DEC
4617 : /* Likewise for regs altered by auto-increment in this insn.
4618 : REG_INC notes have been changed by reloading:
4619 : find_reloads_address_1 records substitutions for them,
4620 : which have been performed by subst_reloads above. */
4621 : for (i = n_reloads - 1; i >= 0; i--)
4622 : {
4623 : rtx in_reg = rld[i].in_reg;
4624 : if (in_reg)
4625 : {
4626 : enum rtx_code code = GET_CODE (in_reg);
4627 : /* PRE_INC / PRE_DEC will have the reload register ending up
4628 : with the same value as the stack slot, but that doesn't
4629 : hold true for POST_INC / POST_DEC. Either we have to
4630 : convert the memory access to a true POST_INC / POST_DEC,
4631 : or we can't use the reload register for inheritance. */
4632 : if ((code == POST_INC || code == POST_DEC)
4633 : && TEST_HARD_REG_BIT (reg_reloaded_valid,
4634 : REGNO (rld[i].reg_rtx))
4635 : /* Make sure it is the inc/dec pseudo, and not
4636 : some other (e.g. output operand) pseudo. */
4637 : && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4638 : == REGNO (XEXP (in_reg, 0))))
4639 :
4640 : {
4641 : rtx reload_reg = rld[i].reg_rtx;
4642 : machine_mode mode = GET_MODE (reload_reg);
4643 : int n = 0;
4644 : rtx_insn *p;
4645 :
4646 : for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4647 : {
4648 : /* We really want to ignore REG_INC notes here, so
4649 : use PATTERN (p) as argument to reg_set_p . */
4650 : if (reg_set_p (reload_reg, PATTERN (p)))
4651 : break;
4652 : n = count_occurrences (PATTERN (p), reload_reg, 0);
4653 : if (! n)
4654 : continue;
4655 : if (n == 1)
4656 : {
4657 : rtx replace_reg
4658 : = gen_rtx_fmt_e (code, mode, reload_reg);
4659 :
4660 : validate_replace_rtx_group (reload_reg,
4661 : replace_reg, p);
4662 : n = verify_changes (0);
4663 :
4664 : /* We must also verify that the constraints
4665 : are met after the replacement. Make sure
4666 : extract_insn is only called for an insn
4667 : where the replacements were found to be
4668 : valid so far. */
4669 : if (n)
4670 : {
4671 : extract_insn (p);
4672 : n = constrain_operands (1,
4673 : get_enabled_alternatives (p));
4674 : }
4675 :
4676 : /* If the constraints were not met, then
4677 : undo the replacement, else confirm it. */
4678 : if (!n)
4679 : cancel_changes (0);
4680 : else
4681 : confirm_change_group ();
4682 : }
4683 : break;
4684 : }
4685 : if (n == 1)
4686 : {
4687 : add_reg_note (p, REG_INC, reload_reg);
4688 : /* Mark this as having an output reload so that the
4689 : REG_INC processing code below won't invalidate
4690 : the reload for inheritance. */
4691 : SET_HARD_REG_BIT (reg_is_output_reload,
4692 : REGNO (reload_reg));
4693 : SET_REGNO_REG_SET (®_has_output_reload,
4694 : REGNO (XEXP (in_reg, 0)));
4695 : }
4696 : else
4697 : forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4698 : NULL);
4699 : }
4700 : else if ((code == PRE_INC || code == PRE_DEC)
4701 : && TEST_HARD_REG_BIT (reg_reloaded_valid,
4702 : REGNO (rld[i].reg_rtx))
4703 : /* Make sure it is the inc/dec pseudo, and not
4704 : some other (e.g. output operand) pseudo. */
4705 : && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4706 : == REGNO (XEXP (in_reg, 0))))
4707 : {
4708 : SET_HARD_REG_BIT (reg_is_output_reload,
4709 : REGNO (rld[i].reg_rtx));
4710 : SET_REGNO_REG_SET (®_has_output_reload,
4711 : REGNO (XEXP (in_reg, 0)));
4712 : }
4713 : else if (code == PRE_INC || code == PRE_DEC
4714 : || code == POST_INC || code == POST_DEC)
4715 : {
4716 : int in_regno = REGNO (XEXP (in_reg, 0));
4717 :
4718 : if (reg_last_reload_reg[in_regno] != NULL_RTX)
4719 : {
4720 : int in_hard_regno;
4721 : bool forget_p = true;
4722 :
4723 : in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4724 : if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4725 : in_hard_regno))
4726 : {
4727 : for (rtx_insn *x = (old_prev ?
4728 : NEXT_INSN (old_prev) : insn);
4729 : x != old_next;
4730 : x = NEXT_INSN (x))
4731 : if (x == reg_reloaded_insn[in_hard_regno])
4732 : {
4733 : forget_p = false;
4734 : break;
4735 : }
4736 : }
4737 : /* If for some reasons, we didn't set up
4738 : reg_last_reload_reg in this insn,
4739 : invalidate inheritance from previous
4740 : insns for the incremented/decremented
4741 : register. Such registers will be not in
4742 : reg_has_output_reload. Invalidate it
4743 : also if the corresponding element in
4744 : reg_reloaded_insn is also
4745 : invalidated. */
4746 : if (forget_p)
4747 : forget_old_reloads_1 (XEXP (in_reg, 0),
4748 : NULL_RTX, NULL);
4749 : }
4750 : }
4751 : }
4752 : }
4753 : /* If a pseudo that got a hard register is auto-incremented,
4754 : we must purge records of copying it into pseudos without
4755 : hard registers. */
4756 : for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1))
4757 : if (REG_NOTE_KIND (x) == REG_INC)
4758 : {
4759 : /* See if this pseudo reg was reloaded in this insn.
4760 : If so, its last-reload info is still valid
4761 : because it is based on this insn's reload. */
4762 : for (i = 0; i < n_reloads; i++)
4763 : if (rld[i].out == XEXP (x, 0))
4764 : break;
4765 :
4766 : if (i == n_reloads)
4767 : forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4768 : }
4769 : #endif
4770 : }
4771 : /* A reload reg's contents are unknown after a label. */
4772 0 : if (LABEL_P (insn))
4773 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4774 :
4775 : /* Don't assume a reload reg is still good after a call insn
4776 : if it is a call-used reg, or if it contains a value that will
4777 : be partially clobbered by the call. */
4778 0 : else if (CALL_P (insn))
4779 : {
4780 0 : reg_reloaded_valid
4781 0 : &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers ();
4782 :
4783 : /* If this is a call to a setjmp-type function, we must not
4784 : reuse any reload reg contents across the call; that will
4785 : just be clobbered by other uses of the register in later
4786 : code, before the longjmp. */
4787 0 : if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4788 0 : CLEAR_HARD_REG_SET (reg_reloaded_valid);
4789 : }
4790 : }
4791 :
4792 : /* Clean up. */
4793 0 : free (reg_last_reload_reg);
4794 0 : CLEAR_REG_SET (®_has_output_reload);
4795 0 : }
4796 :
4797 : /* Discard all record of any value reloaded from X,
4798 : or reloaded in X from someplace else;
4799 : unless X is an output reload reg of the current insn.
4800 :
4801 : X may be a hard reg (the reload reg)
4802 : or it may be a pseudo reg that was reloaded from.
4803 :
4804 : When DATA is non-NULL just mark the registers in regset
4805 : to be forgotten later. */
4806 :
4807 : static void
4808 0 : forget_old_reloads_1 (rtx x, const_rtx, void *data)
4809 : {
4810 0 : unsigned int regno;
4811 0 : unsigned int nr;
4812 0 : regset regs = (regset) data;
4813 :
4814 : /* note_stores does give us subregs of hard regs,
4815 : subreg_regno_offset requires a hard reg. */
4816 0 : while (GET_CODE (x) == SUBREG)
4817 : {
4818 : /* We ignore the subreg offset when calculating the regno,
4819 : because we are using the entire underlying hard register
4820 : below. */
4821 0 : x = SUBREG_REG (x);
4822 : }
4823 :
4824 0 : if (!REG_P (x))
4825 : return;
4826 :
4827 0 : regno = REGNO (x);
4828 :
4829 0 : if (regno >= FIRST_PSEUDO_REGISTER)
4830 : nr = 1;
4831 : else
4832 : {
4833 0 : unsigned int i;
4834 :
4835 0 : nr = REG_NREGS (x);
4836 : /* Storing into a spilled-reg invalidates its contents.
4837 : This can happen if a block-local pseudo is allocated to that reg
4838 : and it wasn't spilled because this block's total need is 0.
4839 : Then some insn might have an optional reload and use this reg. */
4840 0 : if (!regs)
4841 0 : for (i = 0; i < nr; i++)
4842 : /* But don't do this if the reg actually serves as an output
4843 : reload reg in the current instruction. */
4844 0 : if (n_reloads == 0
4845 0 : || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4846 : {
4847 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4848 0 : spill_reg_store[regno + i] = 0;
4849 : }
4850 : }
4851 :
4852 0 : if (regs)
4853 0 : while (nr-- > 0)
4854 0 : SET_REGNO_REG_SET (regs, regno + nr);
4855 : else
4856 : {
4857 : /* Since value of X has changed,
4858 : forget any value previously copied from it. */
4859 :
4860 0 : while (nr-- > 0)
4861 : /* But don't forget a copy if this is the output reload
4862 : that establishes the copy's validity. */
4863 0 : if (n_reloads == 0
4864 0 : || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4865 0 : reg_last_reload_reg[regno + nr] = 0;
4866 : }
4867 : }
4868 :
4869 : /* Forget the reloads marked in regset by previous function. */
4870 : static void
4871 0 : forget_marked_reloads (regset regs)
4872 : {
4873 0 : unsigned int reg;
4874 0 : reg_set_iterator rsi;
4875 0 : EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4876 : {
4877 0 : if (reg < FIRST_PSEUDO_REGISTER
4878 : /* But don't do this if the reg actually serves as an output
4879 : reload reg in the current instruction. */
4880 0 : && (n_reloads == 0
4881 0 : || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4882 : {
4883 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4884 0 : spill_reg_store[reg] = 0;
4885 : }
4886 0 : if (n_reloads == 0
4887 0 : || !REGNO_REG_SET_P (®_has_output_reload, reg))
4888 0 : reg_last_reload_reg[reg] = 0;
4889 : }
4890 0 : }
4891 :
4892 : /* The following HARD_REG_SETs indicate when each hard register is
4893 : used for a reload of various parts of the current insn. */
4894 :
4895 : /* If reg is unavailable for all reloads. */
4896 : static HARD_REG_SET reload_reg_unavailable;
4897 : /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4898 : static HARD_REG_SET reload_reg_used;
4899 : /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4900 : static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4901 : /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4902 : static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4903 : /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4904 : static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4905 : /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4906 : static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4907 : /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4908 : static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4909 : /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4910 : static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4911 : /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4912 : static HARD_REG_SET reload_reg_used_in_op_addr;
4913 : /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4914 : static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4915 : /* If reg is in use for a RELOAD_FOR_INSN reload. */
4916 : static HARD_REG_SET reload_reg_used_in_insn;
4917 : /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4918 : static HARD_REG_SET reload_reg_used_in_other_addr;
4919 :
4920 : /* If reg is in use as a reload reg for any sort of reload. */
4921 : static HARD_REG_SET reload_reg_used_at_all;
4922 :
4923 : /* If reg is use as an inherited reload. We just mark the first register
4924 : in the group. */
4925 : static HARD_REG_SET reload_reg_used_for_inherit;
4926 :
4927 : /* Records which hard regs are used in any way, either as explicit use or
4928 : by being allocated to a pseudo during any point of the current insn. */
4929 : static HARD_REG_SET reg_used_in_insn;
4930 :
4931 : /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4932 : TYPE. MODE is used to indicate how many consecutive regs are
4933 : actually used. */
4934 :
4935 : static void
4936 0 : mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4937 : machine_mode mode)
4938 : {
4939 0 : switch (type)
4940 : {
4941 0 : case RELOAD_OTHER:
4942 0 : add_to_hard_reg_set (&reload_reg_used, mode, regno);
4943 0 : break;
4944 :
4945 0 : case RELOAD_FOR_INPUT_ADDRESS:
4946 0 : add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
4947 0 : break;
4948 :
4949 0 : case RELOAD_FOR_INPADDR_ADDRESS:
4950 0 : add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
4951 0 : break;
4952 :
4953 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
4954 0 : add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
4955 0 : break;
4956 :
4957 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
4958 0 : add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
4959 0 : break;
4960 :
4961 0 : case RELOAD_FOR_OPERAND_ADDRESS:
4962 0 : add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
4963 0 : break;
4964 :
4965 0 : case RELOAD_FOR_OPADDR_ADDR:
4966 0 : add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
4967 0 : break;
4968 :
4969 0 : case RELOAD_FOR_OTHER_ADDRESS:
4970 0 : add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
4971 0 : break;
4972 :
4973 0 : case RELOAD_FOR_INPUT:
4974 0 : add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
4975 0 : break;
4976 :
4977 0 : case RELOAD_FOR_OUTPUT:
4978 0 : add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
4979 0 : break;
4980 :
4981 0 : case RELOAD_FOR_INSN:
4982 0 : add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
4983 0 : break;
4984 : }
4985 :
4986 0 : add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
4987 0 : }
4988 :
4989 : /* Similarly, but show REGNO is no longer in use for a reload. */
4990 :
4991 : static void
4992 0 : clear_reload_reg_in_use (unsigned int regno, int opnum,
4993 : enum reload_type type, machine_mode mode)
4994 : {
4995 0 : unsigned int nregs = hard_regno_nregs (regno, mode);
4996 0 : unsigned int start_regno, end_regno, r;
4997 0 : int i;
4998 : /* A complication is that for some reload types, inheritance might
4999 : allow multiple reloads of the same types to share a reload register.
5000 : We set check_opnum if we have to check only reloads with the same
5001 : operand number, and check_any if we have to check all reloads. */
5002 0 : int check_opnum = 0;
5003 0 : int check_any = 0;
5004 0 : HARD_REG_SET *used_in_set;
5005 :
5006 0 : switch (type)
5007 : {
5008 : case RELOAD_OTHER:
5009 : used_in_set = &reload_reg_used;
5010 : break;
5011 :
5012 0 : case RELOAD_FOR_INPUT_ADDRESS:
5013 0 : used_in_set = &reload_reg_used_in_input_addr[opnum];
5014 0 : break;
5015 :
5016 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5017 0 : check_opnum = 1;
5018 0 : used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5019 0 : break;
5020 :
5021 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5022 0 : used_in_set = &reload_reg_used_in_output_addr[opnum];
5023 0 : break;
5024 :
5025 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5026 0 : check_opnum = 1;
5027 0 : used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5028 0 : break;
5029 :
5030 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5031 0 : used_in_set = &reload_reg_used_in_op_addr;
5032 0 : break;
5033 :
5034 0 : case RELOAD_FOR_OPADDR_ADDR:
5035 0 : check_any = 1;
5036 0 : used_in_set = &reload_reg_used_in_op_addr_reload;
5037 0 : break;
5038 :
5039 0 : case RELOAD_FOR_OTHER_ADDRESS:
5040 0 : used_in_set = &reload_reg_used_in_other_addr;
5041 0 : check_any = 1;
5042 0 : break;
5043 :
5044 0 : case RELOAD_FOR_INPUT:
5045 0 : used_in_set = &reload_reg_used_in_input[opnum];
5046 0 : break;
5047 :
5048 0 : case RELOAD_FOR_OUTPUT:
5049 0 : used_in_set = &reload_reg_used_in_output[opnum];
5050 0 : break;
5051 :
5052 0 : case RELOAD_FOR_INSN:
5053 0 : used_in_set = &reload_reg_used_in_insn;
5054 0 : break;
5055 0 : default:
5056 0 : gcc_unreachable ();
5057 : }
5058 : /* We resolve conflicts with remaining reloads of the same type by
5059 : excluding the intervals of reload registers by them from the
5060 : interval of freed reload registers. Since we only keep track of
5061 : one set of interval bounds, we might have to exclude somewhat
5062 : more than what would be necessary if we used a HARD_REG_SET here.
5063 : But this should only happen very infrequently, so there should
5064 : be no reason to worry about it. */
5065 :
5066 0 : start_regno = regno;
5067 0 : end_regno = regno + nregs;
5068 0 : if (check_opnum || check_any)
5069 : {
5070 0 : for (i = n_reloads - 1; i >= 0; i--)
5071 : {
5072 0 : if (rld[i].when_needed == type
5073 0 : && (check_any || rld[i].opnum == opnum)
5074 0 : && rld[i].reg_rtx)
5075 : {
5076 0 : unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5077 0 : unsigned int conflict_end
5078 0 : = end_hard_regno (rld[i].mode, conflict_start);
5079 :
5080 : /* If there is an overlap with the first to-be-freed register,
5081 : adjust the interval start. */
5082 0 : if (conflict_start <= start_regno && conflict_end > start_regno)
5083 0 : start_regno = conflict_end;
5084 : /* Otherwise, if there is a conflict with one of the other
5085 : to-be-freed registers, adjust the interval end. */
5086 0 : if (conflict_start > start_regno && conflict_start < end_regno)
5087 0 : end_regno = conflict_start;
5088 : }
5089 : }
5090 : }
5091 :
5092 0 : for (r = start_regno; r < end_regno; r++)
5093 0 : CLEAR_HARD_REG_BIT (*used_in_set, r);
5094 0 : }
5095 :
5096 : /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5097 : specified by OPNUM and TYPE. */
5098 :
5099 : static int
5100 0 : reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5101 : {
5102 0 : int i;
5103 :
5104 : /* In use for a RELOAD_OTHER means it's not available for anything. */
5105 0 : if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5106 0 : || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5107 : return 0;
5108 :
5109 0 : switch (type)
5110 : {
5111 0 : case RELOAD_OTHER:
5112 : /* In use for anything means we can't use it for RELOAD_OTHER. */
5113 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5114 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5115 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5116 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5117 : return 0;
5118 :
5119 0 : for (i = 0; i < reload_n_operands; i++)
5120 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5121 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5122 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5123 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5124 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5125 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5126 : return 0;
5127 :
5128 : return 1;
5129 :
5130 0 : case RELOAD_FOR_INPUT:
5131 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5132 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5133 : return 0;
5134 :
5135 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5136 : return 0;
5137 :
5138 : /* If it is used for some other input, can't use it. */
5139 0 : for (i = 0; i < reload_n_operands; i++)
5140 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5141 : return 0;
5142 :
5143 : /* If it is used in a later operand's address, can't use it. */
5144 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5145 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5146 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5147 : return 0;
5148 :
5149 : return 1;
5150 :
5151 0 : case RELOAD_FOR_INPUT_ADDRESS:
5152 : /* Can't use a register if it is used for an input address for this
5153 : operand or used as an input in an earlier one. */
5154 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5155 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5156 : return 0;
5157 :
5158 0 : for (i = 0; i < opnum; i++)
5159 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5160 : return 0;
5161 :
5162 : return 1;
5163 :
5164 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5165 : /* Can't use a register if it is used for an input address
5166 : for this operand or used as an input in an earlier
5167 : one. */
5168 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5169 : return 0;
5170 :
5171 0 : for (i = 0; i < opnum; i++)
5172 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5173 : return 0;
5174 :
5175 : return 1;
5176 :
5177 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5178 : /* Can't use a register if it is used for an output address for this
5179 : operand or used as an output in this or a later operand. Note
5180 : that multiple output operands are emitted in reverse order, so
5181 : the conflicting ones are those with lower indices. */
5182 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5183 : return 0;
5184 :
5185 0 : for (i = 0; i <= opnum; i++)
5186 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5187 : return 0;
5188 :
5189 : return 1;
5190 :
5191 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5192 : /* Can't use a register if it is used for an output address
5193 : for this operand or used as an output in this or a
5194 : later operand. Note that multiple output operands are
5195 : emitted in reverse order, so the conflicting ones are
5196 : those with lower indices. */
5197 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5198 : return 0;
5199 :
5200 0 : for (i = 0; i <= opnum; i++)
5201 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5202 : return 0;
5203 :
5204 : return 1;
5205 :
5206 : case RELOAD_FOR_OPERAND_ADDRESS:
5207 0 : for (i = 0; i < reload_n_operands; i++)
5208 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5209 : return 0;
5210 :
5211 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5212 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5213 :
5214 : case RELOAD_FOR_OPADDR_ADDR:
5215 0 : for (i = 0; i < reload_n_operands; i++)
5216 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5217 : return 0;
5218 :
5219 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5220 :
5221 0 : case RELOAD_FOR_OUTPUT:
5222 : /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5223 : outputs, or an operand address for this or an earlier output.
5224 : Note that multiple output operands are emitted in reverse order,
5225 : so the conflicting ones are those with higher indices. */
5226 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5227 : return 0;
5228 :
5229 0 : for (i = 0; i < reload_n_operands; i++)
5230 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5231 : return 0;
5232 :
5233 0 : for (i = opnum; i < reload_n_operands; i++)
5234 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5235 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5236 : return 0;
5237 :
5238 : return 1;
5239 :
5240 : case RELOAD_FOR_INSN:
5241 0 : for (i = 0; i < reload_n_operands; i++)
5242 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5243 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5244 : return 0;
5245 :
5246 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5247 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5248 :
5249 0 : case RELOAD_FOR_OTHER_ADDRESS:
5250 0 : return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5251 :
5252 0 : default:
5253 0 : gcc_unreachable ();
5254 : }
5255 : }
5256 :
5257 : /* Return 1 if the value in reload reg REGNO, as used by the reload with
5258 : the number RELOADNUM, is still available in REGNO at the end of the insn.
5259 :
5260 : We can assume that the reload reg was already tested for availability
5261 : at the time it is needed, and we should not check this again,
5262 : in case the reg has already been marked in use. */
5263 :
5264 : static int
5265 0 : reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5266 : {
5267 0 : int opnum = rld[reloadnum].opnum;
5268 0 : enum reload_type type = rld[reloadnum].when_needed;
5269 0 : int i;
5270 :
5271 : /* See if there is a reload with the same type for this operand, using
5272 : the same register. This case is not handled by the code below. */
5273 0 : for (i = reloadnum + 1; i < n_reloads; i++)
5274 : {
5275 0 : rtx reg;
5276 :
5277 0 : if (rld[i].opnum != opnum || rld[i].when_needed != type)
5278 0 : continue;
5279 0 : reg = rld[i].reg_rtx;
5280 0 : if (reg == NULL_RTX)
5281 0 : continue;
5282 0 : if (regno >= REGNO (reg) && regno < END_REGNO (reg))
5283 : return 0;
5284 : }
5285 :
5286 0 : switch (type)
5287 : {
5288 : case RELOAD_OTHER:
5289 : /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5290 : its value must reach the end. */
5291 : return 1;
5292 :
5293 : /* If this use is for part of the insn,
5294 : its value reaches if no subsequent part uses the same register.
5295 : Just like the above function, don't try to do this with lots
5296 : of fallthroughs. */
5297 :
5298 : case RELOAD_FOR_OTHER_ADDRESS:
5299 : /* Here we check for everything else, since these don't conflict
5300 : with anything else and everything comes later. */
5301 :
5302 0 : for (i = 0; i < reload_n_operands; i++)
5303 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5304 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5305 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5306 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5307 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5308 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5309 : return 0;
5310 :
5311 0 : return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5312 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5313 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5314 0 : && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5315 :
5316 : case RELOAD_FOR_INPUT_ADDRESS:
5317 : case RELOAD_FOR_INPADDR_ADDRESS:
5318 : /* Similar, except that we check only for this and subsequent inputs
5319 : and the address of only subsequent inputs and we do not need
5320 : to check for RELOAD_OTHER objects since they are known not to
5321 : conflict. */
5322 :
5323 0 : for (i = opnum; i < reload_n_operands; i++)
5324 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5325 : return 0;
5326 :
5327 : /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5328 : could be killed if the register is also used by reload with type
5329 : RELOAD_FOR_INPUT_ADDRESS, so check it. */
5330 0 : if (type == RELOAD_FOR_INPADDR_ADDRESS
5331 0 : && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5332 : return 0;
5333 :
5334 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5335 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5336 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5337 : return 0;
5338 :
5339 0 : for (i = 0; i < reload_n_operands; i++)
5340 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5341 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5342 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5343 : return 0;
5344 :
5345 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5346 : return 0;
5347 :
5348 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5349 0 : && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5350 0 : && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5351 :
5352 0 : case RELOAD_FOR_INPUT:
5353 : /* Similar to input address, except we start at the next operand for
5354 : both input and input address and we do not check for
5355 : RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5356 : would conflict. */
5357 :
5358 0 : for (i = opnum + 1; i < reload_n_operands; i++)
5359 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5360 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5361 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5362 : return 0;
5363 :
5364 : /* ... fall through ... */
5365 :
5366 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5367 : /* Check outputs and their addresses. */
5368 :
5369 0 : for (i = 0; i < reload_n_operands; i++)
5370 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5371 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5372 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5373 : return 0;
5374 :
5375 0 : return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5376 :
5377 : case RELOAD_FOR_OPADDR_ADDR:
5378 0 : for (i = 0; i < reload_n_operands; i++)
5379 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5380 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5381 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5382 : return 0;
5383 :
5384 0 : return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5385 0 : && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5386 0 : && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5387 :
5388 0 : case RELOAD_FOR_INSN:
5389 : /* These conflict with other outputs with RELOAD_OTHER. So
5390 : we need only check for output addresses. */
5391 :
5392 0 : opnum = reload_n_operands;
5393 :
5394 : /* fall through */
5395 :
5396 0 : case RELOAD_FOR_OUTPUT:
5397 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5398 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5399 : /* We already know these can't conflict with a later output. So the
5400 : only thing to check are later output addresses.
5401 : Note that multiple output operands are emitted in reverse order,
5402 : so the conflicting ones are those with lower indices. */
5403 0 : for (i = 0; i < opnum; i++)
5404 0 : if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5405 0 : || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5406 : return 0;
5407 :
5408 : /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5409 : could be killed if the register is also used by reload with type
5410 : RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5411 0 : if (type == RELOAD_FOR_OUTADDR_ADDRESS
5412 0 : && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5413 0 : return 0;
5414 :
5415 : return 1;
5416 :
5417 0 : default:
5418 0 : gcc_unreachable ();
5419 : }
5420 : }
5421 :
5422 : /* Like reload_reg_reaches_end_p, but check that the condition holds for
5423 : every register in REG. */
5424 :
5425 : static bool
5426 0 : reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5427 : {
5428 0 : unsigned int i;
5429 :
5430 0 : for (i = REGNO (reg); i < END_REGNO (reg); i++)
5431 0 : if (!reload_reg_reaches_end_p (i, reloadnum))
5432 : return false;
5433 : return true;
5434 : }
5435 :
5436 :
5437 : /* Returns whether R1 and R2 are uniquely chained: the value of one
5438 : is used by the other, and that value is not used by any other
5439 : reload for this insn. This is used to partially undo the decision
5440 : made in find_reloads when in the case of multiple
5441 : RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5442 : RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5443 : reloads. This code tries to avoid the conflict created by that
5444 : change. It might be cleaner to explicitly keep track of which
5445 : RELOAD_FOR_OPADDR_ADDR reload is associated with which
5446 : RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5447 : this after the fact. */
5448 : static bool
5449 0 : reloads_unique_chain_p (int r1, int r2)
5450 : {
5451 0 : int i;
5452 :
5453 : /* We only check input reloads. */
5454 0 : if (! rld[r1].in || ! rld[r2].in)
5455 : return false;
5456 :
5457 : /* Avoid anything with output reloads. */
5458 0 : if (rld[r1].out || rld[r2].out)
5459 : return false;
5460 :
5461 : /* "chained" means one reload is a component of the other reload,
5462 : not the same as the other reload. */
5463 0 : if (rld[r1].opnum != rld[r2].opnum
5464 0 : || rtx_equal_p (rld[r1].in, rld[r2].in)
5465 0 : || rld[r1].optional || rld[r2].optional
5466 0 : || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5467 0 : || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5468 : return false;
5469 :
5470 : /* The following loop assumes that r1 is the reload that feeds r2. */
5471 0 : if (r1 > r2)
5472 0 : std::swap (r1, r2);
5473 :
5474 0 : for (i = 0; i < n_reloads; i ++)
5475 : /* Look for input reloads that aren't our two */
5476 0 : if (i != r1 && i != r2 && rld[i].in)
5477 : {
5478 : /* If our reload is mentioned at all, it isn't a simple chain. */
5479 0 : if (reg_mentioned_p (rld[r1].in, rld[i].in))
5480 : return false;
5481 : }
5482 : return true;
5483 : }
5484 :
5485 : /* The recursive function change all occurrences of WHAT in *WHERE
5486 : to REPL. */
5487 : static void
5488 0 : substitute (rtx *where, const_rtx what, rtx repl)
5489 : {
5490 0 : const char *fmt;
5491 0 : int i;
5492 0 : enum rtx_code code;
5493 :
5494 0 : if (*where == 0)
5495 : return;
5496 :
5497 0 : if (*where == what || rtx_equal_p (*where, what))
5498 : {
5499 : /* Record the location of the changed rtx. */
5500 0 : substitute_stack.safe_push (where);
5501 0 : *where = repl;
5502 0 : return;
5503 : }
5504 :
5505 0 : code = GET_CODE (*where);
5506 0 : fmt = GET_RTX_FORMAT (code);
5507 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5508 : {
5509 0 : if (fmt[i] == 'E')
5510 : {
5511 0 : int j;
5512 :
5513 0 : for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5514 0 : substitute (&XVECEXP (*where, i, j), what, repl);
5515 : }
5516 0 : else if (fmt[i] == 'e')
5517 0 : substitute (&XEXP (*where, i), what, repl);
5518 : }
5519 : }
5520 :
5521 : /* The function returns TRUE if chain of reload R1 and R2 (in any
5522 : order) can be evaluated without usage of intermediate register for
5523 : the reload containing another reload. It is important to see
5524 : gen_reload to understand what the function is trying to do. As an
5525 : example, let us have reload chain
5526 :
5527 : r2: const
5528 : r1: <something> + const
5529 :
5530 : and reload R2 got reload reg HR. The function returns true if
5531 : there is a correct insn HR = HR + <something>. Otherwise,
5532 : gen_reload will use intermediate register (and this is the reload
5533 : reg for R1) to reload <something>.
5534 :
5535 : We need this function to find a conflict for chain reloads. In our
5536 : example, if HR = HR + <something> is incorrect insn, then we cannot
5537 : use HR as a reload register for R2. If we do use it then we get a
5538 : wrong code:
5539 :
5540 : HR = const
5541 : HR = <something>
5542 : HR = HR + HR
5543 :
5544 : */
5545 : static bool
5546 0 : gen_reload_chain_without_interm_reg_p (int r1, int r2)
5547 : {
5548 : /* Assume other cases in gen_reload are not possible for
5549 : chain reloads or do need an intermediate hard registers. */
5550 0 : bool result = true;
5551 0 : int regno, code;
5552 0 : rtx out, in;
5553 0 : rtx_insn *insn;
5554 0 : rtx_insn *last = get_last_insn ();
5555 :
5556 : /* Make r2 a component of r1. */
5557 0 : if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5558 0 : std::swap (r1, r2);
5559 :
5560 0 : gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5561 0 : regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5562 0 : gcc_assert (regno >= 0);
5563 0 : out = gen_rtx_REG (rld[r1].mode, regno);
5564 0 : in = rld[r1].in;
5565 0 : substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5566 :
5567 : /* If IN is a paradoxical SUBREG, remove it and try to put the
5568 : opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5569 0 : strip_paradoxical_subreg (&in, &out);
5570 :
5571 0 : if (GET_CODE (in) == PLUS
5572 0 : && (REG_P (XEXP (in, 0))
5573 : || GET_CODE (XEXP (in, 0)) == SUBREG
5574 : || MEM_P (XEXP (in, 0)))
5575 0 : && (REG_P (XEXP (in, 1))
5576 0 : || GET_CODE (XEXP (in, 1)) == SUBREG
5577 0 : || CONSTANT_P (XEXP (in, 1))
5578 0 : || MEM_P (XEXP (in, 1))))
5579 : {
5580 0 : insn = emit_insn (gen_rtx_SET (out, in));
5581 0 : code = recog_memoized (insn);
5582 0 : result = false;
5583 :
5584 0 : if (code >= 0)
5585 : {
5586 0 : extract_insn (insn);
5587 : /* We want constrain operands to treat this insn strictly in
5588 : its validity determination, i.e., the way it would after
5589 : reload has completed. */
5590 0 : result = constrain_operands (1, get_enabled_alternatives (insn));
5591 : }
5592 :
5593 0 : delete_insns_since (last);
5594 : }
5595 :
5596 : /* Restore the original value at each changed address within R1. */
5597 0 : while (!substitute_stack.is_empty ())
5598 : {
5599 0 : rtx *where = substitute_stack.pop ();
5600 0 : *where = rld[r2].in;
5601 : }
5602 :
5603 0 : return result;
5604 : }
5605 :
5606 : /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5607 : Return 0 otherwise.
5608 :
5609 : This function uses the same algorithm as reload_reg_free_p above. */
5610 :
5611 : static int
5612 0 : reloads_conflict (int r1, int r2)
5613 : {
5614 0 : enum reload_type r1_type = rld[r1].when_needed;
5615 0 : enum reload_type r2_type = rld[r2].when_needed;
5616 0 : int r1_opnum = rld[r1].opnum;
5617 0 : int r2_opnum = rld[r2].opnum;
5618 :
5619 : /* RELOAD_OTHER conflicts with everything. */
5620 0 : if (r2_type == RELOAD_OTHER)
5621 : return 1;
5622 :
5623 : /* Otherwise, check conflicts differently for each type. */
5624 :
5625 0 : switch (r1_type)
5626 : {
5627 0 : case RELOAD_FOR_INPUT:
5628 0 : return (r2_type == RELOAD_FOR_INSN
5629 0 : || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5630 0 : || r2_type == RELOAD_FOR_OPADDR_ADDR
5631 0 : || r2_type == RELOAD_FOR_INPUT
5632 0 : || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5633 0 : || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5634 0 : && r2_opnum > r1_opnum));
5635 :
5636 0 : case RELOAD_FOR_INPUT_ADDRESS:
5637 0 : return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5638 0 : || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5639 :
5640 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5641 0 : return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5642 0 : || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5643 :
5644 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5645 0 : return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5646 0 : || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5647 :
5648 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5649 0 : return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5650 0 : || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5651 :
5652 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5653 0 : return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5654 0 : || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5655 0 : && (!reloads_unique_chain_p (r1, r2)
5656 0 : || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5657 :
5658 0 : case RELOAD_FOR_OPADDR_ADDR:
5659 0 : return (r2_type == RELOAD_FOR_INPUT
5660 0 : || r2_type == RELOAD_FOR_OPADDR_ADDR);
5661 :
5662 0 : case RELOAD_FOR_OUTPUT:
5663 0 : return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5664 0 : || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5665 0 : || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5666 0 : && r2_opnum >= r1_opnum));
5667 :
5668 0 : case RELOAD_FOR_INSN:
5669 0 : return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5670 0 : || r2_type == RELOAD_FOR_INSN
5671 0 : || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5672 :
5673 0 : case RELOAD_FOR_OTHER_ADDRESS:
5674 0 : return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5675 :
5676 : case RELOAD_OTHER:
5677 : return 1;
5678 :
5679 0 : default:
5680 0 : gcc_unreachable ();
5681 : }
5682 : }
5683 :
5684 : /* Indexed by reload number, 1 if incoming value
5685 : inherited from previous insns. */
5686 : static char reload_inherited[MAX_RELOADS];
5687 :
5688 : /* For an inherited reload, this is the insn the reload was inherited from,
5689 : if we know it. Otherwise, this is 0. */
5690 : static rtx_insn *reload_inheritance_insn[MAX_RELOADS];
5691 :
5692 : /* If nonzero, this is a place to get the value of the reload,
5693 : rather than using reload_in. */
5694 : static rtx reload_override_in[MAX_RELOADS];
5695 :
5696 : /* For each reload, the hard register number of the register used,
5697 : or -1 if we did not need a register for this reload. */
5698 : static int reload_spill_index[MAX_RELOADS];
5699 :
5700 : /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5701 : static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5702 :
5703 : /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5704 : static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5705 :
5706 : /* Subroutine of free_for_value_p, used to check a single register.
5707 : START_REGNO is the starting regno of the full reload register
5708 : (possibly comprising multiple hard registers) that we are considering. */
5709 :
5710 : static int
5711 0 : reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5712 : enum reload_type type, rtx value, rtx out,
5713 : int reloadnum, int ignore_address_reloads)
5714 : {
5715 0 : int time1;
5716 : /* Set if we see an input reload that must not share its reload register
5717 : with any new earlyclobber, but might otherwise share the reload
5718 : register with an output or input-output reload. */
5719 0 : int check_earlyclobber = 0;
5720 0 : int i;
5721 0 : int copy = 0;
5722 :
5723 0 : if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5724 : return 0;
5725 :
5726 0 : if (out == const0_rtx)
5727 : {
5728 0 : copy = 1;
5729 0 : out = NULL_RTX;
5730 : }
5731 :
5732 : /* We use some pseudo 'time' value to check if the lifetimes of the
5733 : new register use would overlap with the one of a previous reload
5734 : that is not read-only or uses a different value.
5735 : The 'time' used doesn't have to be linear in any shape or form, just
5736 : monotonic.
5737 : Some reload types use different 'buckets' for each operand.
5738 : So there are MAX_RECOG_OPERANDS different time values for each
5739 : such reload type.
5740 : We compute TIME1 as the time when the register for the prospective
5741 : new reload ceases to be live, and TIME2 for each existing
5742 : reload as the time when that the reload register of that reload
5743 : becomes live.
5744 : Where there is little to be gained by exact lifetime calculations,
5745 : we just make conservative assumptions, i.e. a longer lifetime;
5746 : this is done in the 'default:' cases. */
5747 0 : switch (type)
5748 : {
5749 0 : case RELOAD_FOR_OTHER_ADDRESS:
5750 : /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5751 0 : time1 = copy ? 0 : 1;
5752 0 : break;
5753 0 : case RELOAD_OTHER:
5754 0 : time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5755 : break;
5756 : /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5757 : RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5758 : respectively, to the time values for these, we get distinct time
5759 : values. To get distinct time values for each operand, we have to
5760 : multiply opnum by at least three. We round that up to four because
5761 : multiply by four is often cheaper. */
5762 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5763 0 : time1 = opnum * 4 + 2;
5764 0 : break;
5765 0 : case RELOAD_FOR_INPUT_ADDRESS:
5766 0 : time1 = opnum * 4 + 3;
5767 0 : break;
5768 0 : case RELOAD_FOR_INPUT:
5769 : /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5770 : executes (inclusive). */
5771 0 : time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5772 : break;
5773 : case RELOAD_FOR_OPADDR_ADDR:
5774 : /* opnum * 4 + 4
5775 : <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5776 : time1 = MAX_RECOG_OPERANDS * 4 + 1;
5777 : break;
5778 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5779 : /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5780 : is executed. */
5781 0 : time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5782 : break;
5783 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5784 0 : time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5785 0 : break;
5786 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5787 0 : time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5788 0 : break;
5789 : default:
5790 0 : time1 = MAX_RECOG_OPERANDS * 5 + 5;
5791 : }
5792 :
5793 0 : for (i = 0; i < n_reloads; i++)
5794 : {
5795 0 : rtx reg = rld[i].reg_rtx;
5796 0 : if (reg && REG_P (reg)
5797 0 : && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg)
5798 0 : && i != reloadnum)
5799 : {
5800 0 : rtx other_input = rld[i].in;
5801 :
5802 : /* If the other reload loads the same input value, that
5803 : will not cause a conflict only if it's loading it into
5804 : the same register. */
5805 0 : if (true_regnum (reg) != start_regno)
5806 : other_input = NULL_RTX;
5807 0 : if (! other_input || ! rtx_equal_p (other_input, value)
5808 0 : || rld[i].out || out)
5809 : {
5810 0 : int time2;
5811 0 : switch (rld[i].when_needed)
5812 : {
5813 : case RELOAD_FOR_OTHER_ADDRESS:
5814 : time2 = 0;
5815 : break;
5816 0 : case RELOAD_FOR_INPADDR_ADDRESS:
5817 : /* find_reloads makes sure that a
5818 : RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5819 : by at most one - the first -
5820 : RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5821 : address reload is inherited, the address address reload
5822 : goes away, so we can ignore this conflict. */
5823 0 : if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5824 0 : && ignore_address_reloads
5825 : /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5826 : Then the address address is still needed to store
5827 : back the new address. */
5828 0 : && ! rld[reloadnum].out)
5829 0 : continue;
5830 : /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5831 : RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5832 : reloads go away. */
5833 0 : if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5834 0 : && ignore_address_reloads
5835 : /* Unless we are reloading an auto_inc expression. */
5836 0 : && ! rld[reloadnum].out)
5837 0 : continue;
5838 0 : time2 = rld[i].opnum * 4 + 2;
5839 0 : break;
5840 0 : case RELOAD_FOR_INPUT_ADDRESS:
5841 0 : if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5842 0 : && ignore_address_reloads
5843 0 : && ! rld[reloadnum].out)
5844 0 : continue;
5845 0 : time2 = rld[i].opnum * 4 + 3;
5846 0 : break;
5847 0 : case RELOAD_FOR_INPUT:
5848 0 : time2 = rld[i].opnum * 4 + 4;
5849 0 : check_earlyclobber = 1;
5850 0 : break;
5851 : /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5852 : == MAX_RECOG_OPERAND * 4 */
5853 0 : case RELOAD_FOR_OPADDR_ADDR:
5854 0 : if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5855 0 : && ignore_address_reloads
5856 0 : && ! rld[reloadnum].out)
5857 0 : continue;
5858 : time2 = MAX_RECOG_OPERANDS * 4 + 1;
5859 : break;
5860 0 : case RELOAD_FOR_OPERAND_ADDRESS:
5861 0 : time2 = MAX_RECOG_OPERANDS * 4 + 2;
5862 0 : check_earlyclobber = 1;
5863 0 : break;
5864 0 : case RELOAD_FOR_INSN:
5865 0 : time2 = MAX_RECOG_OPERANDS * 4 + 3;
5866 0 : break;
5867 0 : case RELOAD_FOR_OUTPUT:
5868 : /* All RELOAD_FOR_OUTPUT reloads become live just after the
5869 : instruction is executed. */
5870 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4;
5871 0 : break;
5872 : /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5873 : the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5874 : value. */
5875 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
5876 0 : if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5877 0 : && ignore_address_reloads
5878 0 : && ! rld[reloadnum].out)
5879 0 : continue;
5880 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5881 0 : break;
5882 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
5883 0 : time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5884 0 : break;
5885 0 : case RELOAD_OTHER:
5886 : /* If there is no conflict in the input part, handle this
5887 : like an output reload. */
5888 0 : if (! rld[i].in || rtx_equal_p (other_input, value))
5889 : {
5890 0 : time2 = MAX_RECOG_OPERANDS * 4 + 4;
5891 : /* Earlyclobbered outputs must conflict with inputs. */
5892 0 : if (earlyclobber_operand_p (rld[i].out))
5893 0 : time2 = MAX_RECOG_OPERANDS * 4 + 3;
5894 :
5895 : break;
5896 : }
5897 0 : time2 = 1;
5898 : /* RELOAD_OTHER might be live beyond instruction execution,
5899 : but this is not obvious when we set time2 = 1. So check
5900 : here if there might be a problem with the new reload
5901 : clobbering the register used by the RELOAD_OTHER. */
5902 0 : if (out)
5903 : return 0;
5904 : break;
5905 : default:
5906 : return 0;
5907 : }
5908 0 : if ((time1 >= time2
5909 0 : && (! rld[i].in || rld[i].out
5910 0 : || ! rtx_equal_p (other_input, value)))
5911 0 : || (out && rld[reloadnum].out_reg
5912 0 : && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5913 : return 0;
5914 : }
5915 : }
5916 : }
5917 :
5918 : /* Earlyclobbered outputs must conflict with inputs. */
5919 0 : if (check_earlyclobber && out && earlyclobber_operand_p (out))
5920 0 : return 0;
5921 :
5922 : return 1;
5923 : }
5924 :
5925 : /* Return 1 if the value in reload reg REGNO, as used by a reload
5926 : needed for the part of the insn specified by OPNUM and TYPE,
5927 : may be used to load VALUE into it.
5928 :
5929 : MODE is the mode in which the register is used, this is needed to
5930 : determine how many hard regs to test.
5931 :
5932 : Other read-only reloads with the same value do not conflict
5933 : unless OUT is nonzero and these other reloads have to live while
5934 : output reloads live.
5935 : If OUT is CONST0_RTX, this is a special case: it means that the
5936 : test should not be for using register REGNO as reload register, but
5937 : for copying from register REGNO into the reload register.
5938 :
5939 : RELOADNUM is the number of the reload we want to load this value for;
5940 : a reload does not conflict with itself.
5941 :
5942 : When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5943 : reloads that load an address for the very reload we are considering.
5944 :
5945 : The caller has to make sure that there is no conflict with the return
5946 : register. */
5947 :
5948 : static int
5949 0 : free_for_value_p (int regno, machine_mode mode, int opnum,
5950 : enum reload_type type, rtx value, rtx out, int reloadnum,
5951 : int ignore_address_reloads)
5952 : {
5953 0 : int nregs = hard_regno_nregs (regno, mode);
5954 0 : while (nregs-- > 0)
5955 0 : if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5956 : value, out, reloadnum,
5957 : ignore_address_reloads))
5958 : return 0;
5959 : return 1;
5960 : }
5961 :
5962 : /* Return true if the rtx X is invariant over the current function. */
5963 : /* ??? Actually, the places where we use this expect exactly what is
5964 : tested here, and not everything that is function invariant. In
5965 : particular, the frame pointer and arg pointer are special cased;
5966 : pic_offset_table_rtx is not, and we must not spill these things to
5967 : memory. */
5968 :
5969 : bool
5970 18022938 : function_invariant_p (const_rtx x)
5971 : {
5972 18022938 : if (CONSTANT_P (x))
5973 : return 1;
5974 13758317 : if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5975 : return 1;
5976 13751344 : if (GET_CODE (x) == PLUS
5977 3586310 : && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5978 1717975 : && GET_CODE (XEXP (x, 1)) == CONST_INT)
5979 1717885 : return 1;
5980 : return 0;
5981 : }
5982 :
5983 : /* Determine whether the reload reg X overlaps any rtx'es used for
5984 : overriding inheritance. Return nonzero if so. */
5985 :
5986 : static int
5987 0 : conflicts_with_override (rtx x)
5988 : {
5989 0 : int i;
5990 0 : for (i = 0; i < n_reloads; i++)
5991 0 : if (reload_override_in[i]
5992 0 : && reg_overlap_mentioned_p (x, reload_override_in[i]))
5993 : return 1;
5994 : return 0;
5995 : }
5996 :
5997 : /* Give an error message saying we failed to find a reload for INSN,
5998 : and clear out reload R. */
5999 : static void
6000 0 : failed_reload (rtx_insn *insn, int r)
6001 : {
6002 0 : if (asm_noperands (PATTERN (insn)) < 0)
6003 : /* It's the compiler's fault. */
6004 0 : fatal_insn ("could not find a spill register", insn);
6005 :
6006 : /* It's the user's fault; the operand's mode and constraint
6007 : don't match. Disable this reload so we don't crash in final. */
6008 0 : error_for_asm (insn,
6009 : "%<asm%> operand constraint incompatible with operand size");
6010 0 : rld[r].in = 0;
6011 0 : rld[r].out = 0;
6012 0 : rld[r].reg_rtx = 0;
6013 0 : rld[r].optional = 1;
6014 0 : rld[r].secondary_p = 1;
6015 0 : }
6016 :
6017 : /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6018 : for reload R. If it's valid, get an rtx for it. Return nonzero if
6019 : successful. */
6020 : static int
6021 0 : set_reload_reg (int i, int r)
6022 : {
6023 0 : int regno;
6024 0 : rtx reg = spill_reg_rtx[i];
6025 :
6026 0 : if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6027 0 : spill_reg_rtx[i] = reg
6028 0 : = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6029 :
6030 0 : regno = true_regnum (reg);
6031 :
6032 : /* Detect when the reload reg can't hold the reload mode.
6033 : This used to be one `if', but Sequent compiler can't handle that. */
6034 0 : if (targetm.hard_regno_mode_ok (regno, rld[r].mode))
6035 : {
6036 0 : machine_mode test_mode = VOIDmode;
6037 0 : if (rld[r].in)
6038 0 : test_mode = GET_MODE (rld[r].in);
6039 : /* If rld[r].in has VOIDmode, it means we will load it
6040 : in whatever mode the reload reg has: to wit, rld[r].mode.
6041 : We have already tested that for validity. */
6042 : /* Aside from that, we need to test that the expressions
6043 : to reload from or into have modes which are valid for this
6044 : reload register. Otherwise the reload insns would be invalid. */
6045 0 : if (! (rld[r].in != 0 && test_mode != VOIDmode
6046 0 : && !targetm.hard_regno_mode_ok (regno, test_mode)))
6047 0 : if (! (rld[r].out != 0
6048 0 : && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out))))
6049 : {
6050 : /* The reg is OK. */
6051 0 : last_spill_reg = i;
6052 :
6053 : /* Mark as in use for this insn the reload regs we use
6054 : for this. */
6055 0 : mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6056 : rld[r].when_needed, rld[r].mode);
6057 :
6058 0 : rld[r].reg_rtx = reg;
6059 0 : reload_spill_index[r] = spill_regs[i];
6060 0 : return 1;
6061 : }
6062 : }
6063 : return 0;
6064 : }
6065 :
6066 : /* Find a spill register to use as a reload register for reload R.
6067 : LAST_RELOAD is nonzero if this is the last reload for the insn being
6068 : processed.
6069 :
6070 : Set rld[R].reg_rtx to the register allocated.
6071 :
6072 : We return 1 if successful, or 0 if we couldn't find a spill reg and
6073 : we didn't change anything. */
6074 :
6075 : static int
6076 0 : allocate_reload_reg (class insn_chain *chain ATTRIBUTE_UNUSED, int r,
6077 : int last_reload)
6078 : {
6079 0 : int i, pass, count;
6080 :
6081 : /* If we put this reload ahead, thinking it is a group,
6082 : then insist on finding a group. Otherwise we can grab a
6083 : reg that some other reload needs.
6084 : (That can happen when we have a 68000 DATA_OR_FP_REG
6085 : which is a group of data regs or one fp reg.)
6086 : We need not be so restrictive if there are no more reloads
6087 : for this insn.
6088 :
6089 : ??? Really it would be nicer to have smarter handling
6090 : for that kind of reg class, where a problem like this is normal.
6091 : Perhaps those classes should be avoided for reloading
6092 : by use of more alternatives. */
6093 :
6094 0 : int force_group = rld[r].nregs > 1 && ! last_reload;
6095 :
6096 : /* If we want a single register and haven't yet found one,
6097 : take any reg in the right class and not in use.
6098 : If we want a consecutive group, here is where we look for it.
6099 :
6100 : We use three passes so we can first look for reload regs to
6101 : reuse, which are already in use for other reloads in this insn,
6102 : and only then use additional registers which are not "bad", then
6103 : finally any register.
6104 :
6105 : I think that maximizing reuse is needed to make sure we don't
6106 : run out of reload regs. Suppose we have three reloads, and
6107 : reloads A and B can share regs. These need two regs.
6108 : Suppose A and B are given different regs.
6109 : That leaves none for C. */
6110 0 : for (pass = 0; pass < 3; pass++)
6111 : {
6112 : /* I is the index in spill_regs.
6113 : We advance it round-robin between insns to use all spill regs
6114 : equally, so that inherited reloads have a chance
6115 : of leapfrogging each other. */
6116 :
6117 0 : i = last_spill_reg;
6118 :
6119 0 : for (count = 0; count < n_spills; count++)
6120 : {
6121 0 : int rclass = (int) rld[r].rclass;
6122 0 : int regnum;
6123 :
6124 0 : i++;
6125 0 : if (i >= n_spills)
6126 0 : i -= n_spills;
6127 0 : regnum = spill_regs[i];
6128 :
6129 0 : if ((reload_reg_free_p (regnum, rld[r].opnum,
6130 : rld[r].when_needed)
6131 0 : || (rld[r].in
6132 : /* We check reload_reg_used to make sure we
6133 : don't clobber the return register. */
6134 0 : && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6135 0 : && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6136 : rld[r].when_needed, rld[r].in,
6137 : rld[r].out, r, 1)))
6138 0 : && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6139 0 : && targetm.hard_regno_mode_ok (regnum, rld[r].mode)
6140 : /* Look first for regs to share, then for unshared. But
6141 : don't share regs used for inherited reloads; they are
6142 : the ones we want to preserve. */
6143 0 : && (pass
6144 0 : || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6145 : regnum)
6146 0 : && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6147 : regnum))))
6148 : {
6149 0 : int nr = hard_regno_nregs (regnum, rld[r].mode);
6150 :
6151 : /* During the second pass we want to avoid reload registers
6152 : which are "bad" for this reload. */
6153 0 : if (pass == 1
6154 0 : && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6155 0 : continue;
6156 :
6157 : /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6158 : (on 68000) got us two FP regs. If NR is 1,
6159 : we would reject both of them. */
6160 0 : if (force_group)
6161 0 : nr = rld[r].nregs;
6162 : /* If we need only one reg, we have already won. */
6163 0 : if (nr == 1)
6164 : {
6165 : /* But reject a single reg if we demand a group. */
6166 0 : if (force_group)
6167 0 : continue;
6168 : break;
6169 : }
6170 : /* Otherwise check that as many consecutive regs as we need
6171 : are available here. */
6172 0 : while (nr > 1)
6173 : {
6174 0 : int regno = regnum + nr - 1;
6175 0 : if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6176 0 : && spill_reg_order[regno] >= 0
6177 0 : && reload_reg_free_p (regno, rld[r].opnum,
6178 : rld[r].when_needed)))
6179 : break;
6180 0 : nr--;
6181 : }
6182 0 : if (nr == 1)
6183 : break;
6184 : }
6185 : }
6186 :
6187 : /* If we found something on the current pass, omit later passes. */
6188 0 : if (count < n_spills)
6189 : break;
6190 : }
6191 :
6192 : /* We should have found a spill register by now. */
6193 0 : if (count >= n_spills)
6194 : return 0;
6195 :
6196 : /* I is the index in SPILL_REG_RTX of the reload register we are to
6197 : allocate. Get an rtx for it and find its register number. */
6198 :
6199 0 : return set_reload_reg (i, r);
6200 : }
6201 :
6202 : /* Initialize all the tables needed to allocate reload registers.
6203 : CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6204 : is the array we use to restore the reg_rtx field for every reload. */
6205 :
6206 : static void
6207 0 : choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
6208 : {
6209 0 : int i;
6210 :
6211 0 : for (i = 0; i < n_reloads; i++)
6212 0 : rld[i].reg_rtx = save_reload_reg_rtx[i];
6213 :
6214 0 : memset (reload_inherited, 0, MAX_RELOADS);
6215 0 : memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6216 0 : memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6217 :
6218 0 : CLEAR_HARD_REG_SET (reload_reg_used);
6219 0 : CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6220 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6221 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6222 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6223 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6224 :
6225 0 : CLEAR_HARD_REG_SET (reg_used_in_insn);
6226 : {
6227 : HARD_REG_SET tmp;
6228 0 : REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6229 0 : reg_used_in_insn |= tmp;
6230 0 : REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6231 0 : reg_used_in_insn |= tmp;
6232 0 : compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6233 0 : compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6234 : }
6235 :
6236 0 : for (i = 0; i < reload_n_operands; i++)
6237 : {
6238 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6239 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6240 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6241 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6242 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6243 0 : CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6244 : }
6245 :
6246 0 : reload_reg_unavailable = ~chain->used_spill_regs;
6247 :
6248 0 : CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6249 :
6250 0 : for (i = 0; i < n_reloads; i++)
6251 : /* If we have already decided to use a certain register,
6252 : don't use it in another way. */
6253 0 : if (rld[i].reg_rtx)
6254 0 : mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6255 : rld[i].when_needed, rld[i].mode);
6256 0 : }
6257 :
6258 : /* If X is not a subreg, return it unmodified. If it is a subreg,
6259 : look up whether we made a replacement for the SUBREG_REG. Return
6260 : either the replacement or the SUBREG_REG. */
6261 :
6262 : static rtx
6263 0 : replaced_subreg (rtx x)
6264 : {
6265 0 : if (GET_CODE (x) == SUBREG)
6266 0 : return find_replacement (&SUBREG_REG (x));
6267 : return x;
6268 : }
6269 :
6270 : /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6271 : mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6272 : SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6273 : otherwise it is NULL. */
6274 :
6275 : static poly_int64
6276 0 : compute_reload_subreg_offset (machine_mode outermode,
6277 : rtx subreg,
6278 : machine_mode innermode)
6279 : {
6280 0 : poly_int64 outer_offset;
6281 0 : machine_mode middlemode;
6282 :
6283 0 : if (!subreg)
6284 0 : return subreg_lowpart_offset (outermode, innermode);
6285 :
6286 0 : outer_offset = SUBREG_BYTE (subreg);
6287 0 : middlemode = GET_MODE (SUBREG_REG (subreg));
6288 :
6289 : /* If SUBREG is paradoxical then return the normal lowpart offset
6290 : for OUTERMODE and INNERMODE. Our caller has already checked
6291 : that OUTERMODE fits in INNERMODE. */
6292 0 : if (paradoxical_subreg_p (outermode, middlemode))
6293 0 : return subreg_lowpart_offset (outermode, innermode);
6294 :
6295 : /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6296 : plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6297 0 : return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6298 : }
6299 :
6300 : /* Assign hard reg targets for the pseudo-registers we must reload
6301 : into hard regs for this insn.
6302 : Also output the instructions to copy them in and out of the hard regs.
6303 :
6304 : For machines with register classes, we are responsible for
6305 : finding a reload reg in the proper class. */
6306 :
6307 : static void
6308 0 : choose_reload_regs (class insn_chain *chain)
6309 : {
6310 0 : rtx_insn *insn = chain->insn;
6311 0 : int i, j;
6312 0 : unsigned int max_group_size = 1;
6313 0 : enum reg_class group_class = NO_REGS;
6314 0 : int pass, win, inheritance;
6315 :
6316 0 : rtx save_reload_reg_rtx[MAX_RELOADS];
6317 :
6318 : /* In order to be certain of getting the registers we need,
6319 : we must sort the reloads into order of increasing register class.
6320 : Then our grabbing of reload registers will parallel the process
6321 : that provided the reload registers.
6322 :
6323 : Also note whether any of the reloads wants a consecutive group of regs.
6324 : If so, record the maximum size of the group desired and what
6325 : register class contains all the groups needed by this insn. */
6326 :
6327 0 : for (j = 0; j < n_reloads; j++)
6328 : {
6329 0 : reload_order[j] = j;
6330 0 : if (rld[j].reg_rtx != NULL_RTX)
6331 : {
6332 0 : gcc_assert (REG_P (rld[j].reg_rtx)
6333 : && HARD_REGISTER_P (rld[j].reg_rtx));
6334 0 : reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6335 : }
6336 : else
6337 0 : reload_spill_index[j] = -1;
6338 :
6339 0 : if (rld[j].nregs > 1)
6340 : {
6341 0 : max_group_size = MAX (rld[j].nregs, max_group_size);
6342 0 : group_class
6343 0 : = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6344 : }
6345 :
6346 0 : save_reload_reg_rtx[j] = rld[j].reg_rtx;
6347 : }
6348 :
6349 0 : if (n_reloads > 1)
6350 0 : qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6351 :
6352 : /* If -O, try first with inheritance, then turning it off.
6353 : If not -O, don't do inheritance.
6354 : Using inheritance when not optimizing leads to paradoxes
6355 : with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6356 : because one side of the comparison might be inherited. */
6357 0 : win = 0;
6358 0 : for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6359 : {
6360 0 : choose_reload_regs_init (chain, save_reload_reg_rtx);
6361 :
6362 : /* Process the reloads in order of preference just found.
6363 : Beyond this point, subregs can be found in reload_reg_rtx.
6364 :
6365 : This used to look for an existing reloaded home for all of the
6366 : reloads, and only then perform any new reloads. But that could lose
6367 : if the reloads were done out of reg-class order because a later
6368 : reload with a looser constraint might have an old home in a register
6369 : needed by an earlier reload with a tighter constraint.
6370 :
6371 : To solve this, we make two passes over the reloads, in the order
6372 : described above. In the first pass we try to inherit a reload
6373 : from a previous insn. If there is a later reload that needs a
6374 : class that is a proper subset of the class being processed, we must
6375 : also allocate a spill register during the first pass.
6376 :
6377 : Then make a second pass over the reloads to allocate any reloads
6378 : that haven't been given registers yet. */
6379 :
6380 0 : for (j = 0; j < n_reloads; j++)
6381 : {
6382 0 : int r = reload_order[j];
6383 0 : rtx search_equiv = NULL_RTX;
6384 :
6385 : /* Ignore reloads that got marked inoperative. */
6386 0 : if (rld[r].out == 0 && rld[r].in == 0
6387 0 : && ! rld[r].secondary_p)
6388 0 : continue;
6389 :
6390 : /* If find_reloads chose to use reload_in or reload_out as a reload
6391 : register, we don't need to chose one. Otherwise, try even if it
6392 : found one since we might save an insn if we find the value lying
6393 : around.
6394 : Try also when reload_in is a pseudo without a hard reg. */
6395 0 : if (rld[r].in != 0 && rld[r].reg_rtx != 0
6396 0 : && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6397 0 : || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6398 0 : && !MEM_P (rld[r].in)
6399 0 : && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6400 0 : continue;
6401 :
6402 : #if 0 /* No longer needed for correct operation.
6403 : It might give better code, or might not; worth an experiment? */
6404 : /* If this is an optional reload, we can't inherit from earlier insns
6405 : until we are sure that any non-optional reloads have been allocated.
6406 : The following code takes advantage of the fact that optional reloads
6407 : are at the end of reload_order. */
6408 : if (rld[r].optional != 0)
6409 : for (i = 0; i < j; i++)
6410 : if ((rld[reload_order[i]].out != 0
6411 : || rld[reload_order[i]].in != 0
6412 : || rld[reload_order[i]].secondary_p)
6413 : && ! rld[reload_order[i]].optional
6414 : && rld[reload_order[i]].reg_rtx == 0)
6415 : allocate_reload_reg (chain, reload_order[i], 0);
6416 : #endif
6417 :
6418 : /* First see if this pseudo is already available as reloaded
6419 : for a previous insn. We cannot try to inherit for reloads
6420 : that are smaller than the maximum number of registers needed
6421 : for groups unless the register we would allocate cannot be used
6422 : for the groups.
6423 :
6424 : We could check here to see if this is a secondary reload for
6425 : an object that is already in a register of the desired class.
6426 : This would avoid the need for the secondary reload register.
6427 : But this is complex because we can't easily determine what
6428 : objects might want to be loaded via this reload. So let a
6429 : register be allocated here. In `emit_reload_insns' we suppress
6430 : one of the loads in the case described above. */
6431 :
6432 0 : if (inheritance)
6433 : {
6434 0 : poly_int64 byte = 0;
6435 0 : int regno = -1;
6436 0 : machine_mode mode = VOIDmode;
6437 0 : rtx subreg = NULL_RTX;
6438 :
6439 0 : if (rld[r].in == 0)
6440 : ;
6441 0 : else if (REG_P (rld[r].in))
6442 : {
6443 0 : regno = REGNO (rld[r].in);
6444 0 : mode = GET_MODE (rld[r].in);
6445 : }
6446 0 : else if (REG_P (rld[r].in_reg))
6447 : {
6448 0 : regno = REGNO (rld[r].in_reg);
6449 0 : mode = GET_MODE (rld[r].in_reg);
6450 : }
6451 0 : else if (GET_CODE (rld[r].in_reg) == SUBREG
6452 0 : && REG_P (SUBREG_REG (rld[r].in_reg)))
6453 : {
6454 0 : regno = REGNO (SUBREG_REG (rld[r].in_reg));
6455 0 : if (regno < FIRST_PSEUDO_REGISTER)
6456 0 : regno = subreg_regno (rld[r].in_reg);
6457 : else
6458 : {
6459 0 : subreg = rld[r].in_reg;
6460 0 : byte = SUBREG_BYTE (subreg);
6461 : }
6462 0 : mode = GET_MODE (rld[r].in_reg);
6463 : }
6464 : #if AUTO_INC_DEC
6465 : else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6466 : && REG_P (XEXP (rld[r].in_reg, 0)))
6467 : {
6468 : regno = REGNO (XEXP (rld[r].in_reg, 0));
6469 : mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6470 : rld[r].out = rld[r].in;
6471 : }
6472 : #endif
6473 : #if 0
6474 : /* This won't work, since REGNO can be a pseudo reg number.
6475 : Also, it takes much more hair to keep track of all the things
6476 : that can invalidate an inherited reload of part of a pseudoreg. */
6477 : else if (GET_CODE (rld[r].in) == SUBREG
6478 : && REG_P (SUBREG_REG (rld[r].in)))
6479 : regno = subreg_regno (rld[r].in);
6480 : #endif
6481 :
6482 0 : if (regno >= 0
6483 0 : && reg_last_reload_reg[regno] != 0
6484 0 : && (known_ge
6485 : (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])),
6486 : GET_MODE_SIZE (mode) + byte))
6487 : /* Verify that the register it's in can be used in
6488 : mode MODE. */
6489 0 : && (REG_CAN_CHANGE_MODE_P
6490 : (REGNO (reg_last_reload_reg[regno]),
6491 : GET_MODE (reg_last_reload_reg[regno]),
6492 : mode)))
6493 : {
6494 0 : enum reg_class rclass = rld[r].rclass, last_class;
6495 0 : rtx last_reg = reg_last_reload_reg[regno];
6496 :
6497 0 : i = REGNO (last_reg);
6498 0 : byte = compute_reload_subreg_offset (mode,
6499 : subreg,
6500 0 : GET_MODE (last_reg));
6501 0 : i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6502 0 : last_class = REGNO_REG_CLASS (i);
6503 :
6504 0 : if (reg_reloaded_contents[i] == regno
6505 0 : && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6506 0 : && targetm.hard_regno_mode_ok (i, rld[r].mode)
6507 0 : && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6508 : /* Even if we can't use this register as a reload
6509 : register, we might use it for reload_override_in,
6510 : if copying it to the desired class is cheap
6511 : enough. */
6512 0 : || ((register_move_cost (mode, last_class, rclass)
6513 0 : < memory_move_cost (mode, rclass, true))
6514 0 : && (secondary_reload_class (1, rclass, mode,
6515 : last_reg)
6516 : == NO_REGS)
6517 0 : && !(targetm.secondary_memory_needed
6518 0 : (mode, last_class, rclass))))
6519 0 : && (rld[r].nregs == max_group_size
6520 0 : || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6521 : i))
6522 0 : && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6523 : rld[r].when_needed, rld[r].in,
6524 : const0_rtx, r, 1))
6525 : {
6526 : /* If a group is needed, verify that all the subsequent
6527 : registers still have their values intact. */
6528 0 : int nr = hard_regno_nregs (i, rld[r].mode);
6529 0 : int k;
6530 :
6531 0 : for (k = 1; k < nr; k++)
6532 0 : if (reg_reloaded_contents[i + k] != regno
6533 0 : || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6534 : break;
6535 :
6536 0 : if (k == nr)
6537 : {
6538 0 : int i1;
6539 0 : int bad_for_class;
6540 :
6541 0 : last_reg = (GET_MODE (last_reg) == mode
6542 0 : ? last_reg : gen_rtx_REG (mode, i));
6543 :
6544 0 : bad_for_class = 0;
6545 0 : for (k = 0; k < nr; k++)
6546 0 : bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6547 0 : i+k);
6548 :
6549 : /* We found a register that contains the
6550 : value we need. If this register is the
6551 : same as an `earlyclobber' operand of the
6552 : current insn, just mark it as a place to
6553 : reload from since we can't use it as the
6554 : reload register itself. */
6555 :
6556 0 : for (i1 = 0; i1 < n_earlyclobbers; i1++)
6557 0 : if (reg_overlap_mentioned_for_reload_p
6558 0 : (reg_last_reload_reg[regno],
6559 : reload_earlyclobbers[i1]))
6560 : break;
6561 :
6562 0 : if (i1 != n_earlyclobbers
6563 0 : || ! (free_for_value_p (i, rld[r].mode,
6564 : rld[r].opnum,
6565 : rld[r].when_needed, rld[r].in,
6566 : rld[r].out, r, 1))
6567 : /* Don't use it if we'd clobber a pseudo reg. */
6568 0 : || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6569 0 : && rld[r].out
6570 0 : && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6571 : /* Don't clobber the frame pointer. */
6572 0 : || (i == HARD_FRAME_POINTER_REGNUM
6573 0 : && frame_pointer_needed
6574 0 : && rld[r].out)
6575 : /* Don't really use the inherited spill reg
6576 : if we need it wider than we've got it. */
6577 0 : || paradoxical_subreg_p (rld[r].mode, mode)
6578 0 : || bad_for_class
6579 :
6580 : /* If find_reloads chose reload_out as reload
6581 : register, stay with it - that leaves the
6582 : inherited register for subsequent reloads. */
6583 0 : || (rld[r].out && rld[r].reg_rtx
6584 0 : && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6585 : {
6586 0 : if (! rld[r].optional)
6587 : {
6588 0 : reload_override_in[r] = last_reg;
6589 0 : reload_inheritance_insn[r]
6590 0 : = reg_reloaded_insn[i];
6591 : }
6592 : }
6593 : else
6594 : {
6595 0 : int k;
6596 : /* We can use this as a reload reg. */
6597 : /* Mark the register as in use for this part of
6598 : the insn. */
6599 0 : mark_reload_reg_in_use (i,
6600 : rld[r].opnum,
6601 : rld[r].when_needed,
6602 : rld[r].mode);
6603 0 : rld[r].reg_rtx = last_reg;
6604 0 : reload_inherited[r] = 1;
6605 0 : reload_inheritance_insn[r]
6606 0 : = reg_reloaded_insn[i];
6607 0 : reload_spill_index[r] = i;
6608 0 : for (k = 0; k < nr; k++)
6609 0 : SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6610 0 : i + k);
6611 : }
6612 : }
6613 : }
6614 : }
6615 : }
6616 :
6617 : /* Here's another way to see if the value is already lying around. */
6618 0 : if (inheritance
6619 0 : && rld[r].in != 0
6620 0 : && ! reload_inherited[r]
6621 0 : && rld[r].out == 0
6622 0 : && (CONSTANT_P (rld[r].in)
6623 : || GET_CODE (rld[r].in) == PLUS
6624 : || REG_P (rld[r].in)
6625 : || MEM_P (rld[r].in))
6626 0 : && (rld[r].nregs == max_group_size
6627 0 : || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6628 0 : search_equiv = rld[r].in;
6629 :
6630 0 : if (search_equiv)
6631 : {
6632 0 : rtx equiv
6633 0 : = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6634 : -1, NULL, 0, rld[r].mode);
6635 0 : int regno = 0;
6636 :
6637 0 : if (equiv != 0)
6638 : {
6639 0 : if (REG_P (equiv))
6640 0 : regno = REGNO (equiv);
6641 : else
6642 : {
6643 : /* This must be a SUBREG of a hard register.
6644 : Make a new REG since this might be used in an
6645 : address and not all machines support SUBREGs
6646 : there. */
6647 0 : gcc_assert (GET_CODE (equiv) == SUBREG);
6648 0 : regno = subreg_regno (equiv);
6649 0 : equiv = gen_rtx_REG (rld[r].mode, regno);
6650 : /* If we choose EQUIV as the reload register, but the
6651 : loop below decides to cancel the inheritance, we'll
6652 : end up reloading EQUIV in rld[r].mode, not the mode
6653 : it had originally. That isn't safe when EQUIV isn't
6654 : available as a spill register since its value might
6655 : still be live at this point. */
6656 0 : for (i = regno; i < regno + (int) rld[r].nregs; i++)
6657 0 : if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6658 0 : equiv = 0;
6659 : }
6660 : }
6661 :
6662 : /* If we found a spill reg, reject it unless it is free
6663 : and of the desired class. */
6664 0 : if (equiv != 0)
6665 : {
6666 0 : int regs_used = 0;
6667 0 : int bad_for_class = 0;
6668 0 : int max_regno = regno + rld[r].nregs;
6669 :
6670 0 : for (i = regno; i < max_regno; i++)
6671 : {
6672 0 : regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6673 : i);
6674 0 : bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6675 : i);
6676 : }
6677 :
6678 0 : if ((regs_used
6679 0 : && ! free_for_value_p (regno, rld[r].mode,
6680 : rld[r].opnum, rld[r].when_needed,
6681 : rld[r].in, rld[r].out, r, 1))
6682 0 : || bad_for_class)
6683 : equiv = 0;
6684 : }
6685 :
6686 0 : if (equiv != 0
6687 0 : && !targetm.hard_regno_mode_ok (regno, rld[r].mode))
6688 : equiv = 0;
6689 :
6690 : /* We found a register that contains the value we need.
6691 : If this register is the same as an `earlyclobber' operand
6692 : of the current insn, just mark it as a place to reload from
6693 : since we can't use it as the reload register itself. */
6694 :
6695 0 : if (equiv != 0)
6696 0 : for (i = 0; i < n_earlyclobbers; i++)
6697 0 : if (reg_overlap_mentioned_for_reload_p (equiv,
6698 : reload_earlyclobbers[i]))
6699 : {
6700 0 : if (! rld[r].optional)
6701 0 : reload_override_in[r] = equiv;
6702 : equiv = 0;
6703 : break;
6704 : }
6705 :
6706 : /* If the equiv register we have found is explicitly clobbered
6707 : in the current insn, it depends on the reload type if we
6708 : can use it, use it for reload_override_in, or not at all.
6709 : In particular, we then can't use EQUIV for a
6710 : RELOAD_FOR_OUTPUT_ADDRESS reload. */
6711 :
6712 0 : if (equiv != 0)
6713 : {
6714 0 : if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6715 0 : switch (rld[r].when_needed)
6716 : {
6717 : case RELOAD_FOR_OTHER_ADDRESS:
6718 : case RELOAD_FOR_INPADDR_ADDRESS:
6719 : case RELOAD_FOR_INPUT_ADDRESS:
6720 : case RELOAD_FOR_OPADDR_ADDR:
6721 : break;
6722 0 : case RELOAD_OTHER:
6723 0 : case RELOAD_FOR_INPUT:
6724 0 : case RELOAD_FOR_OPERAND_ADDRESS:
6725 0 : if (! rld[r].optional)
6726 0 : reload_override_in[r] = equiv;
6727 : /* Fall through. */
6728 : default:
6729 : equiv = 0;
6730 : break;
6731 : }
6732 0 : else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6733 0 : switch (rld[r].when_needed)
6734 : {
6735 : case RELOAD_FOR_OTHER_ADDRESS:
6736 : case RELOAD_FOR_INPADDR_ADDRESS:
6737 : case RELOAD_FOR_INPUT_ADDRESS:
6738 : case RELOAD_FOR_OPADDR_ADDR:
6739 : case RELOAD_FOR_OPERAND_ADDRESS:
6740 : case RELOAD_FOR_INPUT:
6741 : break;
6742 0 : case RELOAD_OTHER:
6743 0 : if (! rld[r].optional)
6744 0 : reload_override_in[r] = equiv;
6745 : /* Fall through. */
6746 : default:
6747 : equiv = 0;
6748 : break;
6749 : }
6750 : }
6751 :
6752 : /* If we found an equivalent reg, say no code need be generated
6753 : to load it, and use it as our reload reg. */
6754 0 : if (equiv != 0
6755 0 : && (regno != HARD_FRAME_POINTER_REGNUM
6756 0 : || !frame_pointer_needed))
6757 : {
6758 0 : int nr = hard_regno_nregs (regno, rld[r].mode);
6759 0 : int k;
6760 0 : rld[r].reg_rtx = equiv;
6761 0 : reload_spill_index[r] = regno;
6762 0 : reload_inherited[r] = 1;
6763 :
6764 : /* If reg_reloaded_valid is not set for this register,
6765 : there might be a stale spill_reg_store lying around.
6766 : We must clear it, since otherwise emit_reload_insns
6767 : might delete the store. */
6768 0 : if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6769 0 : spill_reg_store[regno] = NULL;
6770 : /* If any of the hard registers in EQUIV are spill
6771 : registers, mark them as in use for this insn. */
6772 0 : for (k = 0; k < nr; k++)
6773 : {
6774 0 : i = spill_reg_order[regno + k];
6775 0 : if (i >= 0)
6776 : {
6777 0 : mark_reload_reg_in_use (regno, rld[r].opnum,
6778 : rld[r].when_needed,
6779 : rld[r].mode);
6780 0 : SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6781 : regno + k);
6782 : }
6783 : }
6784 : }
6785 : }
6786 :
6787 : /* If we found a register to use already, or if this is an optional
6788 : reload, we are done. */
6789 0 : if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6790 0 : continue;
6791 :
6792 : #if 0
6793 : /* No longer needed for correct operation. Might or might
6794 : not give better code on the average. Want to experiment? */
6795 :
6796 : /* See if there is a later reload that has a class different from our
6797 : class that intersects our class or that requires less register
6798 : than our reload. If so, we must allocate a register to this
6799 : reload now, since that reload might inherit a previous reload
6800 : and take the only available register in our class. Don't do this
6801 : for optional reloads since they will force all previous reloads
6802 : to be allocated. Also don't do this for reloads that have been
6803 : turned off. */
6804 :
6805 : for (i = j + 1; i < n_reloads; i++)
6806 : {
6807 : int s = reload_order[i];
6808 :
6809 : if ((rld[s].in == 0 && rld[s].out == 0
6810 : && ! rld[s].secondary_p)
6811 : || rld[s].optional)
6812 : continue;
6813 :
6814 : if ((rld[s].rclass != rld[r].rclass
6815 : && reg_classes_intersect_p (rld[r].rclass,
6816 : rld[s].rclass))
6817 : || rld[s].nregs < rld[r].nregs)
6818 : break;
6819 : }
6820 :
6821 : if (i == n_reloads)
6822 : continue;
6823 :
6824 : allocate_reload_reg (chain, r, j == n_reloads - 1);
6825 : #endif
6826 : }
6827 :
6828 : /* Now allocate reload registers for anything non-optional that
6829 : didn't get one yet. */
6830 0 : for (j = 0; j < n_reloads; j++)
6831 : {
6832 0 : int r = reload_order[j];
6833 :
6834 : /* Ignore reloads that got marked inoperative. */
6835 0 : if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6836 0 : continue;
6837 :
6838 : /* Skip reloads that already have a register allocated or are
6839 : optional. */
6840 0 : if (rld[r].reg_rtx != 0 || rld[r].optional)
6841 0 : continue;
6842 :
6843 0 : if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6844 : break;
6845 : }
6846 :
6847 : /* If that loop got all the way, we have won. */
6848 0 : if (j == n_reloads)
6849 : {
6850 : win = 1;
6851 : break;
6852 : }
6853 :
6854 : /* Loop around and try without any inheritance. */
6855 : }
6856 :
6857 0 : if (! win)
6858 : {
6859 : /* First undo everything done by the failed attempt
6860 : to allocate with inheritance. */
6861 0 : choose_reload_regs_init (chain, save_reload_reg_rtx);
6862 :
6863 : /* Some sanity tests to verify that the reloads found in the first
6864 : pass are identical to the ones we have now. */
6865 0 : gcc_assert (chain->n_reloads == n_reloads);
6866 :
6867 0 : for (i = 0; i < n_reloads; i++)
6868 : {
6869 0 : if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6870 0 : continue;
6871 0 : gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6872 0 : for (j = 0; j < n_spills; j++)
6873 0 : if (spill_regs[j] == chain->rld[i].regno)
6874 0 : if (! set_reload_reg (j, i))
6875 0 : failed_reload (chain->insn, i);
6876 : }
6877 : }
6878 :
6879 : /* If we thought we could inherit a reload, because it seemed that
6880 : nothing else wanted the same reload register earlier in the insn,
6881 : verify that assumption, now that all reloads have been assigned.
6882 : Likewise for reloads where reload_override_in has been set. */
6883 :
6884 : /* If doing expensive optimizations, do one preliminary pass that doesn't
6885 : cancel any inheritance, but removes reloads that have been needed only
6886 : for reloads that we know can be inherited. */
6887 0 : for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6888 : {
6889 0 : for (j = 0; j < n_reloads; j++)
6890 : {
6891 0 : int r = reload_order[j];
6892 0 : rtx check_reg;
6893 0 : rtx tem;
6894 0 : if (reload_inherited[r] && rld[r].reg_rtx)
6895 : check_reg = rld[r].reg_rtx;
6896 0 : else if (reload_override_in[r]
6897 0 : && (REG_P (reload_override_in[r])
6898 0 : || GET_CODE (reload_override_in[r]) == SUBREG))
6899 : check_reg = reload_override_in[r];
6900 : else
6901 0 : continue;
6902 0 : if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6903 : rld[r].opnum, rld[r].when_needed, rld[r].in,
6904 : (reload_inherited[r]
6905 : ? rld[r].out : const0_rtx),
6906 : r, 1))
6907 : {
6908 0 : if (pass)
6909 0 : continue;
6910 0 : reload_inherited[r] = 0;
6911 0 : reload_override_in[r] = 0;
6912 : }
6913 : /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6914 : reload_override_in, then we do not need its related
6915 : RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6916 : likewise for other reload types.
6917 : We handle this by removing a reload when its only replacement
6918 : is mentioned in reload_in of the reload we are going to inherit.
6919 : A special case are auto_inc expressions; even if the input is
6920 : inherited, we still need the address for the output. We can
6921 : recognize them because they have RELOAD_OUT set to RELOAD_IN.
6922 : If we succeeded removing some reload and we are doing a preliminary
6923 : pass just to remove such reloads, make another pass, since the
6924 : removal of one reload might allow us to inherit another one. */
6925 0 : else if (rld[r].in
6926 0 : && rld[r].out != rld[r].in
6927 0 : && remove_address_replacements (rld[r].in))
6928 : {
6929 0 : if (pass)
6930 0 : pass = 2;
6931 : }
6932 : /* If we needed a memory location for the reload, we also have to
6933 : remove its related reloads. */
6934 0 : else if (rld[r].in
6935 0 : && rld[r].out != rld[r].in
6936 0 : && (tem = replaced_subreg (rld[r].in), REG_P (tem))
6937 0 : && REGNO (tem) < FIRST_PSEUDO_REGISTER
6938 0 : && (targetm.secondary_memory_needed
6939 0 : (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)),
6940 0 : rld[r].rclass))
6941 0 : && remove_address_replacements
6942 0 : (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
6943 : rld[r].when_needed)))
6944 : {
6945 0 : if (pass)
6946 0 : pass = 2;
6947 : }
6948 : }
6949 : }
6950 :
6951 : /* Now that reload_override_in is known valid,
6952 : actually override reload_in. */
6953 0 : for (j = 0; j < n_reloads; j++)
6954 0 : if (reload_override_in[j])
6955 0 : rld[j].in = reload_override_in[j];
6956 :
6957 : /* If this reload won't be done because it has been canceled or is
6958 : optional and not inherited, clear reload_reg_rtx so other
6959 : routines (such as subst_reloads) don't get confused. */
6960 0 : for (j = 0; j < n_reloads; j++)
6961 0 : if (rld[j].reg_rtx != 0
6962 0 : && ((rld[j].optional && ! reload_inherited[j])
6963 0 : || (rld[j].in == 0 && rld[j].out == 0
6964 0 : && ! rld[j].secondary_p)))
6965 : {
6966 0 : int regno = true_regnum (rld[j].reg_rtx);
6967 :
6968 0 : if (spill_reg_order[regno] >= 0)
6969 0 : clear_reload_reg_in_use (regno, rld[j].opnum,
6970 : rld[j].when_needed, rld[j].mode);
6971 0 : rld[j].reg_rtx = 0;
6972 0 : reload_spill_index[j] = -1;
6973 : }
6974 :
6975 : /* Record which pseudos and which spill regs have output reloads. */
6976 0 : for (j = 0; j < n_reloads; j++)
6977 : {
6978 0 : int r = reload_order[j];
6979 :
6980 0 : i = reload_spill_index[r];
6981 :
6982 : /* I is nonneg if this reload uses a register.
6983 : If rld[r].reg_rtx is 0, this is an optional reload
6984 : that we opted to ignore. */
6985 0 : if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6986 0 : && rld[r].reg_rtx != 0)
6987 : {
6988 0 : int nregno = REGNO (rld[r].out_reg);
6989 0 : int nr = 1;
6990 :
6991 0 : if (nregno < FIRST_PSEUDO_REGISTER)
6992 0 : nr = hard_regno_nregs (nregno, rld[r].mode);
6993 :
6994 0 : while (--nr >= 0)
6995 0 : SET_REGNO_REG_SET (®_has_output_reload,
6996 : nregno + nr);
6997 :
6998 0 : if (i >= 0)
6999 0 : add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7000 :
7001 0 : gcc_assert (rld[r].when_needed == RELOAD_OTHER
7002 : || rld[r].when_needed == RELOAD_FOR_OUTPUT
7003 : || rld[r].when_needed == RELOAD_FOR_INSN);
7004 : }
7005 : }
7006 0 : }
7007 :
7008 : /* Deallocate the reload register for reload R. This is called from
7009 : remove_address_replacements. */
7010 :
7011 : void
7012 0 : deallocate_reload_reg (int r)
7013 : {
7014 0 : int regno;
7015 :
7016 0 : if (! rld[r].reg_rtx)
7017 : return;
7018 0 : regno = true_regnum (rld[r].reg_rtx);
7019 0 : rld[r].reg_rtx = 0;
7020 0 : if (spill_reg_order[regno] >= 0)
7021 0 : clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7022 : rld[r].mode);
7023 0 : reload_spill_index[r] = -1;
7024 : }
7025 :
7026 : /* These arrays are filled by emit_reload_insns and its subroutines. */
7027 : static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS];
7028 : static rtx_insn *other_input_address_reload_insns = 0;
7029 : static rtx_insn *other_input_reload_insns = 0;
7030 : static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS];
7031 : static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7032 : static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS];
7033 : static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS];
7034 : static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7035 : static rtx_insn *operand_reload_insns = 0;
7036 : static rtx_insn *other_operand_reload_insns = 0;
7037 : static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS];
7038 :
7039 : /* Values to be put in spill_reg_store are put here first. Instructions
7040 : must only be placed here if the associated reload register reaches
7041 : the end of the instruction's reload sequence. */
7042 : static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7043 : static HARD_REG_SET reg_reloaded_died;
7044 :
7045 : /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7046 : of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7047 : is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7048 : adjusted register, and return true. Otherwise, return false. */
7049 : static bool
7050 0 : reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7051 : enum reg_class new_class,
7052 : machine_mode new_mode)
7053 :
7054 : {
7055 0 : rtx reg;
7056 :
7057 0 : for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7058 : {
7059 0 : unsigned regno = REGNO (reg);
7060 :
7061 0 : if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7062 0 : continue;
7063 0 : if (GET_MODE (reg) != new_mode)
7064 : {
7065 0 : if (!targetm.hard_regno_mode_ok (regno, new_mode))
7066 0 : continue;
7067 0 : if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg))
7068 0 : continue;
7069 0 : reg = reload_adjust_reg_for_mode (reg, new_mode);
7070 : }
7071 0 : *reload_reg = reg;
7072 0 : return true;
7073 : }
7074 : return false;
7075 : }
7076 :
7077 : /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7078 : pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7079 : nonzero, if that is suitable. On success, change *RELOAD_REG to the
7080 : adjusted register, and return true. Otherwise, return false. */
7081 : static bool
7082 0 : reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7083 : enum insn_code icode)
7084 :
7085 : {
7086 0 : enum reg_class new_class = scratch_reload_class (icode);
7087 0 : machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7088 :
7089 0 : return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7090 0 : new_class, new_mode);
7091 : }
7092 :
7093 : /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7094 : has the number J. OLD contains the value to be used as input. */
7095 :
7096 : static void
7097 0 : emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
7098 : rtx old, int j)
7099 : {
7100 0 : rtx_insn *insn = chain->insn;
7101 0 : rtx reloadreg;
7102 0 : rtx oldequiv_reg = 0;
7103 0 : rtx oldequiv = 0;
7104 0 : int special = 0;
7105 0 : machine_mode mode;
7106 0 : rtx_insn **where;
7107 :
7108 : /* delete_output_reload is only invoked properly if old contains
7109 : the original pseudo register. Since this is replaced with a
7110 : hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7111 : find the pseudo in RELOAD_IN_REG. This is also used to
7112 : determine whether a secondary reload is needed. */
7113 0 : if (reload_override_in[j]
7114 0 : && (REG_P (rl->in_reg)
7115 0 : || (GET_CODE (rl->in_reg) == SUBREG
7116 0 : && REG_P (SUBREG_REG (rl->in_reg)))))
7117 : {
7118 0 : oldequiv = old;
7119 0 : old = rl->in_reg;
7120 : }
7121 0 : if (oldequiv == 0)
7122 : oldequiv = old;
7123 0 : else if (REG_P (oldequiv))
7124 : oldequiv_reg = oldequiv;
7125 0 : else if (GET_CODE (oldequiv) == SUBREG)
7126 0 : oldequiv_reg = SUBREG_REG (oldequiv);
7127 :
7128 0 : reloadreg = reload_reg_rtx_for_input[j];
7129 0 : mode = GET_MODE (reloadreg);
7130 :
7131 : /* If we are reloading from a register that was recently stored in
7132 : with an output-reload, see if we can prove there was
7133 : actually no need to store the old value in it. */
7134 :
7135 0 : if (optimize && REG_P (oldequiv)
7136 0 : && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7137 0 : && spill_reg_store[REGNO (oldequiv)]
7138 0 : && REG_P (old)
7139 0 : && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7140 0 : || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7141 0 : rl->out_reg)))
7142 0 : delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7143 :
7144 : /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7145 : OLDEQUIV. */
7146 :
7147 0 : while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7148 0 : oldequiv = SUBREG_REG (oldequiv);
7149 0 : if (GET_MODE (oldequiv) != VOIDmode
7150 0 : && mode != GET_MODE (oldequiv))
7151 0 : oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7152 :
7153 : /* Switch to the right place to emit the reload insns. */
7154 0 : switch (rl->when_needed)
7155 : {
7156 : case RELOAD_OTHER:
7157 0 : where = &other_input_reload_insns;
7158 : break;
7159 0 : case RELOAD_FOR_INPUT:
7160 0 : where = &input_reload_insns[rl->opnum];
7161 0 : break;
7162 0 : case RELOAD_FOR_INPUT_ADDRESS:
7163 0 : where = &input_address_reload_insns[rl->opnum];
7164 0 : break;
7165 0 : case RELOAD_FOR_INPADDR_ADDRESS:
7166 0 : where = &inpaddr_address_reload_insns[rl->opnum];
7167 0 : break;
7168 0 : case RELOAD_FOR_OUTPUT_ADDRESS:
7169 0 : where = &output_address_reload_insns[rl->opnum];
7170 0 : break;
7171 0 : case RELOAD_FOR_OUTADDR_ADDRESS:
7172 0 : where = &outaddr_address_reload_insns[rl->opnum];
7173 0 : break;
7174 0 : case RELOAD_FOR_OPERAND_ADDRESS:
7175 0 : where = &operand_reload_insns;
7176 0 : break;
7177 0 : case RELOAD_FOR_OPADDR_ADDR:
7178 0 : where = &other_operand_reload_insns;
7179 0 : break;
7180 0 : case RELOAD_FOR_OTHER_ADDRESS:
7181 0 : where = &other_input_address_reload_insns;
7182 0 : break;
7183 0 : default:
7184 0 : gcc_unreachable ();
7185 : }
7186 :
7187 0 : push_to_sequence (*where);
7188 :
7189 : /* Auto-increment addresses must be reloaded in a special way. */
7190 0 : if (rl->out && ! rl->out_reg)
7191 : {
7192 : /* We are not going to bother supporting the case where a
7193 : incremented register can't be copied directly from
7194 : OLDEQUIV since this seems highly unlikely. */
7195 0 : gcc_assert (rl->secondary_in_reload < 0);
7196 :
7197 0 : if (reload_inherited[j])
7198 0 : oldequiv = reloadreg;
7199 :
7200 0 : old = XEXP (rl->in_reg, 0);
7201 :
7202 : /* Prevent normal processing of this reload. */
7203 0 : special = 1;
7204 : /* Output a special code sequence for this case. */
7205 0 : inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7206 : }
7207 :
7208 : /* If we are reloading a pseudo-register that was set by the previous
7209 : insn, see if we can get rid of that pseudo-register entirely
7210 : by redirecting the previous insn into our reload register. */
7211 :
7212 0 : else if (optimize && REG_P (old)
7213 0 : && REGNO (old) >= FIRST_PSEUDO_REGISTER
7214 0 : && dead_or_set_p (insn, old)
7215 : /* This is unsafe if some other reload
7216 : uses the same reg first. */
7217 0 : && ! conflicts_with_override (reloadreg)
7218 0 : && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7219 : rl->when_needed, old, rl->out, j, 0))
7220 : {
7221 0 : rtx_insn *temp = PREV_INSN (insn);
7222 0 : while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7223 0 : temp = PREV_INSN (temp);
7224 0 : if (temp
7225 0 : && NONJUMP_INSN_P (temp)
7226 0 : && GET_CODE (PATTERN (temp)) == SET
7227 0 : && SET_DEST (PATTERN (temp)) == old
7228 : /* Make sure we can access insn_operand_constraint. */
7229 0 : && asm_noperands (PATTERN (temp)) < 0
7230 : /* This is unsafe if operand occurs more than once in current
7231 : insn. Perhaps some occurrences aren't reloaded. */
7232 0 : && count_occurrences (PATTERN (insn), old, 0) == 1)
7233 : {
7234 0 : rtx old = SET_DEST (PATTERN (temp));
7235 : /* Store into the reload register instead of the pseudo. */
7236 0 : SET_DEST (PATTERN (temp)) = reloadreg;
7237 :
7238 : /* Verify that resulting insn is valid.
7239 :
7240 : Note that we have replaced the destination of TEMP with
7241 : RELOADREG. If TEMP references RELOADREG within an
7242 : autoincrement addressing mode, then the resulting insn
7243 : is ill-formed and we must reject this optimization. */
7244 0 : extract_insn (temp);
7245 0 : if (constrain_operands (1, get_enabled_alternatives (temp))
7246 0 : && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg)))
7247 : {
7248 : /* If the previous insn is an output reload, the source is
7249 : a reload register, and its spill_reg_store entry will
7250 : contain the previous destination. This is now
7251 : invalid. */
7252 0 : if (REG_P (SET_SRC (PATTERN (temp)))
7253 0 : && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7254 : {
7255 0 : spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7256 0 : spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7257 : }
7258 :
7259 : /* If these are the only uses of the pseudo reg,
7260 : pretend for GDB it lives in the reload reg we used. */
7261 0 : if (REG_N_DEATHS (REGNO (old)) == 1
7262 0 : && REG_N_SETS (REGNO (old)) == 1)
7263 : {
7264 0 : reg_renumber[REGNO (old)] = REGNO (reloadreg);
7265 0 : if (ira_conflicts_p)
7266 : /* Inform IRA about the change. */
7267 0 : ira_mark_allocation_change (REGNO (old));
7268 0 : alter_reg (REGNO (old), -1, false);
7269 : }
7270 0 : special = 1;
7271 :
7272 : /* Adjust any debug insns between temp and insn. */
7273 0 : while ((temp = NEXT_INSN (temp)) != insn)
7274 0 : if (DEBUG_BIND_INSN_P (temp))
7275 0 : INSN_VAR_LOCATION_LOC (temp)
7276 0 : = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp),
7277 : old, reloadreg);
7278 : else
7279 0 : gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp));
7280 : }
7281 : else
7282 : {
7283 0 : SET_DEST (PATTERN (temp)) = old;
7284 : }
7285 : }
7286 : }
7287 :
7288 : /* We can't do that, so output an insn to load RELOADREG. */
7289 :
7290 : /* If we have a secondary reload, pick up the secondary register
7291 : and icode, if any. If OLDEQUIV and OLD are different or
7292 : if this is an in-out reload, recompute whether or not we
7293 : still need a secondary register and what the icode should
7294 : be. If we still need a secondary register and the class or
7295 : icode is different, go back to reloading from OLD if using
7296 : OLDEQUIV means that we got the wrong type of register. We
7297 : cannot have different class or icode due to an in-out reload
7298 : because we don't make such reloads when both the input and
7299 : output need secondary reload registers. */
7300 :
7301 0 : if (! special && rl->secondary_in_reload >= 0)
7302 : {
7303 0 : rtx second_reload_reg = 0;
7304 0 : rtx third_reload_reg = 0;
7305 0 : int secondary_reload = rl->secondary_in_reload;
7306 0 : rtx real_oldequiv = oldequiv;
7307 0 : rtx real_old = old;
7308 0 : rtx tmp;
7309 0 : enum insn_code icode;
7310 0 : enum insn_code tertiary_icode = CODE_FOR_nothing;
7311 :
7312 : /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7313 : and similarly for OLD.
7314 : See comments in get_secondary_reload in reload.cc. */
7315 : /* If it is a pseudo that cannot be replaced with its
7316 : equivalent MEM, we must fall back to reload_in, which
7317 : will have all the necessary substitutions registered.
7318 : Likewise for a pseudo that can't be replaced with its
7319 : equivalent constant.
7320 :
7321 : Take extra care for subregs of such pseudos. Note that
7322 : we cannot use reg_equiv_mem in this case because it is
7323 : not in the right mode. */
7324 :
7325 0 : tmp = oldequiv;
7326 0 : if (GET_CODE (tmp) == SUBREG)
7327 0 : tmp = SUBREG_REG (tmp);
7328 0 : if (REG_P (tmp)
7329 0 : && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7330 0 : && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7331 0 : || reg_equiv_constant (REGNO (tmp)) != 0))
7332 : {
7333 0 : if (! reg_equiv_mem (REGNO (tmp))
7334 0 : || num_not_at_initial_offset
7335 0 : || GET_CODE (oldequiv) == SUBREG)
7336 0 : real_oldequiv = rl->in;
7337 : else
7338 : real_oldequiv = reg_equiv_mem (REGNO (tmp));
7339 : }
7340 :
7341 0 : tmp = old;
7342 0 : if (GET_CODE (tmp) == SUBREG)
7343 0 : tmp = SUBREG_REG (tmp);
7344 0 : if (REG_P (tmp)
7345 0 : && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7346 0 : && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7347 0 : || reg_equiv_constant (REGNO (tmp)) != 0))
7348 : {
7349 0 : if (! reg_equiv_mem (REGNO (tmp))
7350 0 : || num_not_at_initial_offset
7351 0 : || GET_CODE (old) == SUBREG)
7352 0 : real_old = rl->in;
7353 : else
7354 : real_old = reg_equiv_mem (REGNO (tmp));
7355 : }
7356 :
7357 0 : second_reload_reg = rld[secondary_reload].reg_rtx;
7358 0 : if (rld[secondary_reload].secondary_in_reload >= 0)
7359 : {
7360 0 : int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7361 :
7362 0 : third_reload_reg = rld[tertiary_reload].reg_rtx;
7363 0 : tertiary_icode = rld[secondary_reload].secondary_in_icode;
7364 : /* We'd have to add more code for quartary reloads. */
7365 0 : gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7366 : }
7367 0 : icode = rl->secondary_in_icode;
7368 :
7369 0 : if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7370 0 : || (rl->in != 0 && rl->out != 0))
7371 : {
7372 0 : secondary_reload_info sri, sri2;
7373 0 : enum reg_class new_class, new_t_class;
7374 :
7375 0 : sri.icode = CODE_FOR_nothing;
7376 0 : sri.prev_sri = NULL;
7377 0 : new_class
7378 0 : = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7379 0 : rl->rclass, mode,
7380 : &sri);
7381 :
7382 0 : if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7383 0 : second_reload_reg = 0;
7384 0 : else if (new_class == NO_REGS)
7385 : {
7386 0 : if (reload_adjust_reg_for_icode (&second_reload_reg,
7387 : third_reload_reg,
7388 : (enum insn_code) sri.icode))
7389 : {
7390 0 : icode = (enum insn_code) sri.icode;
7391 0 : third_reload_reg = 0;
7392 : }
7393 : else
7394 : {
7395 : oldequiv = old;
7396 : real_oldequiv = real_old;
7397 : }
7398 : }
7399 0 : else if (sri.icode != CODE_FOR_nothing)
7400 : /* We currently lack a way to express this in reloads. */
7401 0 : gcc_unreachable ();
7402 : else
7403 : {
7404 0 : sri2.icode = CODE_FOR_nothing;
7405 0 : sri2.prev_sri = &sri;
7406 0 : new_t_class
7407 0 : = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7408 : new_class, mode,
7409 : &sri);
7410 0 : if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7411 : {
7412 0 : if (reload_adjust_reg_for_temp (&second_reload_reg,
7413 : third_reload_reg,
7414 : new_class, mode))
7415 : {
7416 0 : third_reload_reg = 0;
7417 0 : tertiary_icode = (enum insn_code) sri2.icode;
7418 : }
7419 : else
7420 : {
7421 : oldequiv = old;
7422 : real_oldequiv = real_old;
7423 : }
7424 : }
7425 : else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7426 : {
7427 : rtx intermediate = second_reload_reg;
7428 :
7429 : if (reload_adjust_reg_for_temp (&intermediate, NULL,
7430 : new_class, mode)
7431 : && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7432 : ((enum insn_code)
7433 : sri2.icode)))
7434 : {
7435 : second_reload_reg = intermediate;
7436 : tertiary_icode = (enum insn_code) sri2.icode;
7437 : }
7438 : else
7439 : {
7440 : oldequiv = old;
7441 : real_oldequiv = real_old;
7442 : }
7443 : }
7444 : else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7445 : {
7446 0 : rtx intermediate = second_reload_reg;
7447 :
7448 0 : if (reload_adjust_reg_for_temp (&intermediate, NULL,
7449 : new_class, mode)
7450 0 : && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7451 : new_t_class, mode))
7452 : {
7453 0 : second_reload_reg = intermediate;
7454 0 : tertiary_icode = (enum insn_code) sri2.icode;
7455 : }
7456 : else
7457 : {
7458 : oldequiv = old;
7459 : real_oldequiv = real_old;
7460 : }
7461 0 : }
7462 : else
7463 : {
7464 : /* This could be handled more intelligently too. */
7465 : oldequiv = old;
7466 : real_oldequiv = real_old;
7467 : }
7468 : }
7469 : }
7470 :
7471 : /* If we still need a secondary reload register, check
7472 : to see if it is being used as a scratch or intermediate
7473 : register and generate code appropriately. If we need
7474 : a scratch register, use REAL_OLDEQUIV since the form of
7475 : the insn may depend on the actual address if it is
7476 : a MEM. */
7477 :
7478 0 : if (second_reload_reg)
7479 : {
7480 0 : if (icode != CODE_FOR_nothing)
7481 : {
7482 : /* We'd have to add extra code to handle this case. */
7483 0 : gcc_assert (!third_reload_reg);
7484 :
7485 0 : emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7486 : second_reload_reg));
7487 0 : special = 1;
7488 : }
7489 : else
7490 : {
7491 : /* See if we need a scratch register to load the
7492 : intermediate register (a tertiary reload). */
7493 0 : if (tertiary_icode != CODE_FOR_nothing)
7494 : {
7495 0 : emit_insn ((GEN_FCN (tertiary_icode)
7496 0 : (second_reload_reg, real_oldequiv,
7497 : third_reload_reg)));
7498 : }
7499 0 : else if (third_reload_reg)
7500 : {
7501 0 : gen_reload (third_reload_reg, real_oldequiv,
7502 : rl->opnum,
7503 : rl->when_needed);
7504 0 : gen_reload (second_reload_reg, third_reload_reg,
7505 : rl->opnum,
7506 : rl->when_needed);
7507 : }
7508 : else
7509 0 : gen_reload (second_reload_reg, real_oldequiv,
7510 : rl->opnum,
7511 : rl->when_needed);
7512 :
7513 : oldequiv = second_reload_reg;
7514 : }
7515 : }
7516 : }
7517 :
7518 0 : if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7519 : {
7520 0 : rtx real_oldequiv = oldequiv;
7521 :
7522 0 : if ((REG_P (oldequiv)
7523 0 : && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7524 0 : && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7525 0 : || reg_equiv_constant (REGNO (oldequiv)) != 0))
7526 0 : || (GET_CODE (oldequiv) == SUBREG
7527 0 : && REG_P (SUBREG_REG (oldequiv))
7528 0 : && (REGNO (SUBREG_REG (oldequiv))
7529 : >= FIRST_PSEUDO_REGISTER)
7530 0 : && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7531 0 : || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7532 0 : || (CONSTANT_P (oldequiv)
7533 0 : && (targetm.preferred_reload_class (oldequiv,
7534 0 : REGNO_REG_CLASS (REGNO (reloadreg)))
7535 : == NO_REGS)))
7536 0 : real_oldequiv = rl->in;
7537 0 : gen_reload (reloadreg, real_oldequiv, rl->opnum,
7538 : rl->when_needed);
7539 : }
7540 :
7541 0 : if (cfun->can_throw_non_call_exceptions)
7542 0 : copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7543 :
7544 : /* End this sequence. */
7545 0 : *where = end_sequence ();
7546 :
7547 : /* Update reload_override_in so that delete_address_reloads_1
7548 : can see the actual register usage. */
7549 0 : if (oldequiv_reg)
7550 0 : reload_override_in[j] = oldequiv;
7551 0 : }
7552 :
7553 : /* Generate insns to for the output reload RL, which is for the insn described
7554 : by CHAIN and has the number J. */
7555 : static void
7556 0 : emit_output_reload_insns (class insn_chain *chain, struct reload *rl,
7557 : int j)
7558 : {
7559 0 : rtx reloadreg;
7560 0 : rtx_insn *insn = chain->insn;
7561 0 : int special = 0;
7562 0 : rtx old = rl->out;
7563 0 : machine_mode mode;
7564 0 : rtx_insn *p;
7565 0 : rtx rl_reg_rtx;
7566 :
7567 0 : if (rl->when_needed == RELOAD_OTHER)
7568 0 : start_sequence ();
7569 : else
7570 0 : push_to_sequence (output_reload_insns[rl->opnum]);
7571 :
7572 0 : rl_reg_rtx = reload_reg_rtx_for_output[j];
7573 0 : mode = GET_MODE (rl_reg_rtx);
7574 :
7575 0 : reloadreg = rl_reg_rtx;
7576 :
7577 : /* If we need two reload regs, set RELOADREG to the intermediate
7578 : one, since it will be stored into OLD. We might need a secondary
7579 : register only for an input reload, so check again here. */
7580 :
7581 0 : if (rl->secondary_out_reload >= 0)
7582 : {
7583 0 : rtx real_old = old;
7584 0 : int secondary_reload = rl->secondary_out_reload;
7585 0 : int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7586 :
7587 0 : if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7588 0 : && reg_equiv_mem (REGNO (old)) != 0)
7589 0 : real_old = reg_equiv_mem (REGNO (old));
7590 :
7591 0 : if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7592 : {
7593 0 : rtx second_reloadreg = reloadreg;
7594 0 : reloadreg = rld[secondary_reload].reg_rtx;
7595 :
7596 : /* See if RELOADREG is to be used as a scratch register
7597 : or as an intermediate register. */
7598 0 : if (rl->secondary_out_icode != CODE_FOR_nothing)
7599 : {
7600 : /* We'd have to add extra code to handle this case. */
7601 0 : gcc_assert (tertiary_reload < 0);
7602 :
7603 0 : emit_insn ((GEN_FCN (rl->secondary_out_icode)
7604 0 : (real_old, second_reloadreg, reloadreg)));
7605 0 : special = 1;
7606 : }
7607 : else
7608 : {
7609 : /* See if we need both a scratch and intermediate reload
7610 : register. */
7611 :
7612 0 : enum insn_code tertiary_icode
7613 : = rld[secondary_reload].secondary_out_icode;
7614 :
7615 : /* We'd have to add more code for quartary reloads. */
7616 0 : gcc_assert (tertiary_reload < 0
7617 : || rld[tertiary_reload].secondary_out_reload < 0);
7618 :
7619 0 : if (GET_MODE (reloadreg) != mode)
7620 0 : reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7621 :
7622 0 : if (tertiary_icode != CODE_FOR_nothing)
7623 : {
7624 0 : rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7625 :
7626 : /* Copy primary reload reg to secondary reload reg.
7627 : (Note that these have been swapped above, then
7628 : secondary reload reg to OLD using our insn.) */
7629 :
7630 : /* If REAL_OLD is a paradoxical SUBREG, remove it
7631 : and try to put the opposite SUBREG on
7632 : RELOADREG. */
7633 0 : strip_paradoxical_subreg (&real_old, &reloadreg);
7634 :
7635 0 : gen_reload (reloadreg, second_reloadreg,
7636 : rl->opnum, rl->when_needed);
7637 0 : emit_insn ((GEN_FCN (tertiary_icode)
7638 0 : (real_old, reloadreg, third_reloadreg)));
7639 0 : special = 1;
7640 : }
7641 :
7642 : else
7643 : {
7644 : /* Copy between the reload regs here and then to
7645 : OUT later. */
7646 :
7647 0 : gen_reload (reloadreg, second_reloadreg,
7648 : rl->opnum, rl->when_needed);
7649 0 : if (tertiary_reload >= 0)
7650 : {
7651 0 : rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7652 :
7653 0 : gen_reload (third_reloadreg, reloadreg,
7654 : rl->opnum, rl->when_needed);
7655 0 : reloadreg = third_reloadreg;
7656 : }
7657 : }
7658 : }
7659 : }
7660 : }
7661 :
7662 : /* Output the last reload insn. */
7663 0 : if (! special)
7664 : {
7665 0 : rtx set;
7666 :
7667 : /* Don't output the last reload if OLD is not the dest of
7668 : INSN and is in the src and is clobbered by INSN. */
7669 0 : if (! flag_expensive_optimizations
7670 0 : || !REG_P (old)
7671 0 : || !(set = single_set (insn))
7672 0 : || rtx_equal_p (old, SET_DEST (set))
7673 0 : || !reg_mentioned_p (old, SET_SRC (set))
7674 0 : || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7675 0 : && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7676 0 : gen_reload (old, reloadreg, rl->opnum,
7677 : rl->when_needed);
7678 : }
7679 :
7680 : /* Look at all insns we emitted, just to be safe. */
7681 0 : for (p = get_insns (); p; p = NEXT_INSN (p))
7682 0 : if (INSN_P (p))
7683 : {
7684 0 : rtx pat = PATTERN (p);
7685 :
7686 : /* If this output reload doesn't come from a spill reg,
7687 : clear any memory of reloaded copies of the pseudo reg.
7688 : If this output reload comes from a spill reg,
7689 : reg_has_output_reload will make this do nothing. */
7690 0 : note_stores (p, forget_old_reloads_1, NULL);
7691 :
7692 0 : if (reg_mentioned_p (rl_reg_rtx, pat))
7693 : {
7694 0 : rtx set = single_set (insn);
7695 0 : if (reload_spill_index[j] < 0
7696 0 : && set
7697 0 : && SET_SRC (set) == rl_reg_rtx)
7698 : {
7699 0 : int src = REGNO (SET_SRC (set));
7700 :
7701 0 : reload_spill_index[j] = src;
7702 0 : SET_HARD_REG_BIT (reg_is_output_reload, src);
7703 0 : if (find_regno_note (insn, REG_DEAD, src))
7704 0 : SET_HARD_REG_BIT (reg_reloaded_died, src);
7705 : }
7706 0 : if (HARD_REGISTER_P (rl_reg_rtx))
7707 : {
7708 0 : int s = rl->secondary_out_reload;
7709 0 : set = single_set (p);
7710 : /* If this reload copies only to the secondary reload
7711 : register, the secondary reload does the actual
7712 : store. */
7713 0 : if (s >= 0 && set == NULL_RTX)
7714 : /* We can't tell what function the secondary reload
7715 : has and where the actual store to the pseudo is
7716 : made; leave new_spill_reg_store alone. */
7717 : ;
7718 0 : else if (s >= 0
7719 0 : && SET_SRC (set) == rl_reg_rtx
7720 0 : && SET_DEST (set) == rld[s].reg_rtx)
7721 : {
7722 : /* Usually the next instruction will be the
7723 : secondary reload insn; if we can confirm
7724 : that it is, setting new_spill_reg_store to
7725 : that insn will allow an extra optimization. */
7726 0 : rtx s_reg = rld[s].reg_rtx;
7727 0 : rtx_insn *next = NEXT_INSN (p);
7728 0 : rld[s].out = rl->out;
7729 0 : rld[s].out_reg = rl->out_reg;
7730 0 : set = single_set (next);
7731 0 : if (set && SET_SRC (set) == s_reg
7732 0 : && reload_reg_rtx_reaches_end_p (s_reg, s))
7733 : {
7734 0 : SET_HARD_REG_BIT (reg_is_output_reload,
7735 : REGNO (s_reg));
7736 0 : new_spill_reg_store[REGNO (s_reg)] = next;
7737 : }
7738 : }
7739 0 : else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7740 0 : new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7741 : }
7742 : }
7743 : }
7744 :
7745 0 : if (rl->when_needed == RELOAD_OTHER)
7746 : {
7747 0 : emit_insn (other_output_reload_insns[rl->opnum]);
7748 0 : other_output_reload_insns[rl->opnum] = get_insns ();
7749 : }
7750 : else
7751 0 : output_reload_insns[rl->opnum] = get_insns ();
7752 :
7753 0 : if (cfun->can_throw_non_call_exceptions)
7754 0 : copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7755 :
7756 0 : end_sequence ();
7757 0 : }
7758 :
7759 : /* Do input reloading for reload RL, which is for the insn described by CHAIN
7760 : and has the number J. */
7761 : static void
7762 0 : do_input_reload (class insn_chain *chain, struct reload *rl, int j)
7763 : {
7764 0 : rtx_insn *insn = chain->insn;
7765 0 : rtx old = (rl->in && MEM_P (rl->in)
7766 0 : ? rl->in_reg : rl->in);
7767 0 : rtx reg_rtx = rl->reg_rtx;
7768 :
7769 0 : if (old && reg_rtx)
7770 : {
7771 0 : machine_mode mode;
7772 :
7773 : /* Determine the mode to reload in.
7774 : This is very tricky because we have three to choose from.
7775 : There is the mode the insn operand wants (rl->inmode).
7776 : There is the mode of the reload register RELOADREG.
7777 : There is the intrinsic mode of the operand, which we could find
7778 : by stripping some SUBREGs.
7779 : It turns out that RELOADREG's mode is irrelevant:
7780 : we can change that arbitrarily.
7781 :
7782 : Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7783 : then the reload reg may not support QImode moves, so use SImode.
7784 : If foo is in memory due to spilling a pseudo reg, this is safe,
7785 : because the QImode value is in the least significant part of a
7786 : slot big enough for a SImode. If foo is some other sort of
7787 : memory reference, then it is impossible to reload this case,
7788 : so previous passes had better make sure this never happens.
7789 :
7790 : Then consider a one-word union which has SImode and one of its
7791 : members is a float, being fetched as (SUBREG:SF union:SI).
7792 : We must fetch that as SFmode because we could be loading into
7793 : a float-only register. In this case OLD's mode is correct.
7794 :
7795 : Consider an immediate integer: it has VOIDmode. Here we need
7796 : to get a mode from something else.
7797 :
7798 : In some cases, there is a fourth mode, the operand's
7799 : containing mode. If the insn specifies a containing mode for
7800 : this operand, it overrides all others.
7801 :
7802 : I am not sure whether the algorithm here is always right,
7803 : but it does the right things in those cases. */
7804 :
7805 0 : mode = GET_MODE (old);
7806 0 : if (mode == VOIDmode)
7807 0 : mode = rl->inmode;
7808 :
7809 : /* We cannot use gen_lowpart_common since it can do the wrong thing
7810 : when REG_RTX has a multi-word mode. Note that REG_RTX must
7811 : always be a REG here. */
7812 0 : if (GET_MODE (reg_rtx) != mode)
7813 0 : reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7814 : }
7815 0 : reload_reg_rtx_for_input[j] = reg_rtx;
7816 :
7817 0 : if (old != 0
7818 : /* AUTO_INC reloads need to be handled even if inherited. We got an
7819 : AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7820 0 : && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7821 0 : && ! rtx_equal_p (reg_rtx, old)
7822 0 : && reg_rtx != 0)
7823 0 : emit_input_reload_insns (chain, rld + j, old, j);
7824 :
7825 : /* When inheriting a wider reload, we have a MEM in rl->in,
7826 : e.g. inheriting a SImode output reload for
7827 : (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7828 0 : if (optimize && reload_inherited[j] && rl->in
7829 0 : && MEM_P (rl->in)
7830 0 : && MEM_P (rl->in_reg)
7831 0 : && reload_spill_index[j] >= 0
7832 0 : && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7833 0 : rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7834 :
7835 : /* If we are reloading a register that was recently stored in with an
7836 : output-reload, see if we can prove there was
7837 : actually no need to store the old value in it. */
7838 :
7839 0 : if (optimize
7840 0 : && (reload_inherited[j] || reload_override_in[j])
7841 0 : && reg_rtx
7842 0 : && REG_P (reg_rtx)
7843 0 : && spill_reg_store[REGNO (reg_rtx)] != 0
7844 : #if 0
7845 : /* There doesn't seem to be any reason to restrict this to pseudos
7846 : and doing so loses in the case where we are copying from a
7847 : register of the wrong class. */
7848 : && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7849 : #endif
7850 : /* The insn might have already some references to stackslots
7851 : replaced by MEMs, while reload_out_reg still names the
7852 : original pseudo. */
7853 0 : && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7854 0 : || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7855 0 : delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7856 0 : }
7857 :
7858 : /* Do output reloading for reload RL, which is for the insn described by
7859 : CHAIN and has the number J.
7860 : ??? At some point we need to support handling output reloads of
7861 : JUMP_INSNs. */
7862 : static void
7863 0 : do_output_reload (class insn_chain *chain, struct reload *rl, int j)
7864 : {
7865 0 : rtx note, old;
7866 0 : rtx_insn *insn = chain->insn;
7867 : /* If this is an output reload that stores something that is
7868 : not loaded in this same reload, see if we can eliminate a previous
7869 : store. */
7870 0 : rtx pseudo = rl->out_reg;
7871 0 : rtx reg_rtx = rl->reg_rtx;
7872 :
7873 0 : if (rl->out && reg_rtx)
7874 : {
7875 0 : machine_mode mode;
7876 :
7877 : /* Determine the mode to reload in.
7878 : See comments above (for input reloading). */
7879 0 : mode = GET_MODE (rl->out);
7880 0 : if (mode == VOIDmode)
7881 : {
7882 : /* VOIDmode should never happen for an output. */
7883 0 : if (asm_noperands (PATTERN (insn)) < 0)
7884 : /* It's the compiler's fault. */
7885 0 : fatal_insn ("VOIDmode on an output", insn);
7886 0 : error_for_asm (insn, "output operand is constant in %<asm%>");
7887 : /* Prevent crash--use something we know is valid. */
7888 0 : mode = word_mode;
7889 0 : rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7890 : }
7891 0 : if (GET_MODE (reg_rtx) != mode)
7892 0 : reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7893 : }
7894 0 : reload_reg_rtx_for_output[j] = reg_rtx;
7895 :
7896 0 : if (pseudo
7897 0 : && optimize
7898 0 : && REG_P (pseudo)
7899 0 : && ! rtx_equal_p (rl->in_reg, pseudo)
7900 0 : && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7901 0 : && reg_last_reload_reg[REGNO (pseudo)])
7902 : {
7903 0 : int pseudo_no = REGNO (pseudo);
7904 0 : int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7905 :
7906 : /* We don't need to test full validity of last_regno for
7907 : inherit here; we only want to know if the store actually
7908 : matches the pseudo. */
7909 0 : if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7910 0 : && reg_reloaded_contents[last_regno] == pseudo_no
7911 0 : && spill_reg_store[last_regno]
7912 0 : && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7913 0 : delete_output_reload (insn, j, last_regno, reg_rtx);
7914 : }
7915 :
7916 0 : old = rl->out_reg;
7917 0 : if (old == 0
7918 0 : || reg_rtx == 0
7919 0 : || rtx_equal_p (old, reg_rtx))
7920 : return;
7921 :
7922 : /* An output operand that dies right away does need a reload,
7923 : but need not be copied from it. Show the new location in the
7924 : REG_UNUSED note. */
7925 0 : if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7926 0 : && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7927 : {
7928 0 : XEXP (note, 0) = reg_rtx;
7929 0 : return;
7930 : }
7931 : /* Likewise for a SUBREG of an operand that dies. */
7932 0 : else if (GET_CODE (old) == SUBREG
7933 0 : && REG_P (SUBREG_REG (old))
7934 0 : && (note = find_reg_note (insn, REG_UNUSED,
7935 : SUBREG_REG (old))) != 0)
7936 : {
7937 0 : XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7938 0 : return;
7939 : }
7940 0 : else if (GET_CODE (old) == SCRATCH)
7941 : /* If we aren't optimizing, there won't be a REG_UNUSED note,
7942 : but we don't want to make an output reload. */
7943 : return;
7944 :
7945 : /* If is a JUMP_INSN, we can't support output reloads yet. */
7946 0 : gcc_assert (NONJUMP_INSN_P (insn));
7947 :
7948 0 : emit_output_reload_insns (chain, rld + j, j);
7949 : }
7950 :
7951 : /* A reload copies values of MODE from register SRC to register DEST.
7952 : Return true if it can be treated for inheritance purposes like a
7953 : group of reloads, each one reloading a single hard register. The
7954 : caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7955 : occupy the same number of hard registers. */
7956 :
7957 : static bool
7958 0 : inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7959 : int src ATTRIBUTE_UNUSED,
7960 : machine_mode mode ATTRIBUTE_UNUSED)
7961 : {
7962 0 : return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7963 0 : && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7964 : }
7965 :
7966 : /* Output insns to reload values in and out of the chosen reload regs. */
7967 :
7968 : static void
7969 0 : emit_reload_insns (class insn_chain *chain)
7970 : {
7971 0 : rtx_insn *insn = chain->insn;
7972 :
7973 0 : int j;
7974 :
7975 0 : CLEAR_HARD_REG_SET (reg_reloaded_died);
7976 :
7977 0 : for (j = 0; j < reload_n_operands; j++)
7978 0 : input_reload_insns[j] = input_address_reload_insns[j]
7979 0 : = inpaddr_address_reload_insns[j]
7980 0 : = output_reload_insns[j] = output_address_reload_insns[j]
7981 0 : = outaddr_address_reload_insns[j]
7982 0 : = other_output_reload_insns[j] = 0;
7983 0 : other_input_address_reload_insns = 0;
7984 0 : other_input_reload_insns = 0;
7985 0 : operand_reload_insns = 0;
7986 0 : other_operand_reload_insns = 0;
7987 :
7988 : /* Dump reloads into the dump file. */
7989 0 : if (dump_file)
7990 : {
7991 0 : fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7992 0 : debug_reload_to_stream (dump_file);
7993 : }
7994 :
7995 0 : for (j = 0; j < n_reloads; j++)
7996 0 : if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7997 : {
7998 : unsigned int i;
7999 :
8000 0 : for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8001 0 : new_spill_reg_store[i] = 0;
8002 : }
8003 :
8004 : /* Now output the instructions to copy the data into and out of the
8005 : reload registers. Do these in the order that the reloads were reported,
8006 : since reloads of base and index registers precede reloads of operands
8007 : and the operands may need the base and index registers reloaded. */
8008 :
8009 0 : for (j = 0; j < n_reloads; j++)
8010 : {
8011 0 : do_input_reload (chain, rld + j, j);
8012 0 : do_output_reload (chain, rld + j, j);
8013 : }
8014 :
8015 : /* Now write all the insns we made for reloads in the order expected by
8016 : the allocation functions. Prior to the insn being reloaded, we write
8017 : the following reloads:
8018 :
8019 : RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8020 :
8021 : RELOAD_OTHER reloads.
8022 :
8023 : For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8024 : by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8025 : RELOAD_FOR_INPUT reload for the operand.
8026 :
8027 : RELOAD_FOR_OPADDR_ADDRS reloads.
8028 :
8029 : RELOAD_FOR_OPERAND_ADDRESS reloads.
8030 :
8031 : After the insn being reloaded, we write the following:
8032 :
8033 : For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8034 : by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8035 : RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8036 : reloads for the operand. The RELOAD_OTHER output reloads are
8037 : output in descending order by reload number. */
8038 :
8039 0 : emit_insn_before (other_input_address_reload_insns, insn);
8040 0 : emit_insn_before (other_input_reload_insns, insn);
8041 :
8042 0 : for (j = 0; j < reload_n_operands; j++)
8043 : {
8044 0 : emit_insn_before (inpaddr_address_reload_insns[j], insn);
8045 0 : emit_insn_before (input_address_reload_insns[j], insn);
8046 0 : emit_insn_before (input_reload_insns[j], insn);
8047 : }
8048 :
8049 0 : emit_insn_before (other_operand_reload_insns, insn);
8050 0 : emit_insn_before (operand_reload_insns, insn);
8051 :
8052 0 : for (j = 0; j < reload_n_operands; j++)
8053 : {
8054 0 : rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8055 0 : x = emit_insn_after (output_address_reload_insns[j], x);
8056 0 : x = emit_insn_after (output_reload_insns[j], x);
8057 0 : emit_insn_after (other_output_reload_insns[j], x);
8058 : }
8059 :
8060 : /* For all the spill regs newly reloaded in this instruction,
8061 : record what they were reloaded from, so subsequent instructions
8062 : can inherit the reloads.
8063 :
8064 : Update spill_reg_store for the reloads of this insn.
8065 : Copy the elements that were updated in the loop above. */
8066 :
8067 0 : for (j = 0; j < n_reloads; j++)
8068 : {
8069 0 : int r = reload_order[j];
8070 0 : int i = reload_spill_index[r];
8071 :
8072 : /* If this is a non-inherited input reload from a pseudo, we must
8073 : clear any memory of a previous store to the same pseudo. Only do
8074 : something if there will not be an output reload for the pseudo
8075 : being reloaded. */
8076 0 : if (rld[r].in_reg != 0
8077 0 : && ! (reload_inherited[r] || reload_override_in[r]))
8078 : {
8079 0 : rtx reg = rld[r].in_reg;
8080 :
8081 0 : if (GET_CODE (reg) == SUBREG)
8082 0 : reg = SUBREG_REG (reg);
8083 :
8084 0 : if (REG_P (reg)
8085 0 : && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8086 0 : && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8087 : {
8088 0 : int nregno = REGNO (reg);
8089 :
8090 0 : if (reg_last_reload_reg[nregno])
8091 : {
8092 0 : int last_regno = REGNO (reg_last_reload_reg[nregno]);
8093 :
8094 0 : if (reg_reloaded_contents[last_regno] == nregno)
8095 0 : spill_reg_store[last_regno] = 0;
8096 : }
8097 : }
8098 : }
8099 :
8100 : /* I is nonneg if this reload used a register.
8101 : If rld[r].reg_rtx is 0, this is an optional reload
8102 : that we opted to ignore. */
8103 :
8104 0 : if (i >= 0 && rld[r].reg_rtx != 0)
8105 : {
8106 0 : int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx));
8107 0 : int k;
8108 :
8109 : /* For a multi register reload, we need to check if all or part
8110 : of the value lives to the end. */
8111 0 : for (k = 0; k < nr; k++)
8112 0 : if (reload_reg_reaches_end_p (i + k, r))
8113 0 : CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8114 :
8115 : /* Maybe the spill reg contains a copy of reload_out. */
8116 0 : if (rld[r].out != 0
8117 0 : && (REG_P (rld[r].out)
8118 0 : || (rld[r].out_reg
8119 0 : ? REG_P (rld[r].out_reg)
8120 : /* The reload value is an auto-modification of
8121 : some kind. For PRE_INC, POST_INC, PRE_DEC
8122 : and POST_DEC, we record an equivalence
8123 : between the reload register and the operand
8124 : on the optimistic assumption that we can make
8125 : the equivalence hold. reload_as_needed must
8126 : then either make it hold or invalidate the
8127 : equivalence.
8128 :
8129 : PRE_MODIFY and POST_MODIFY addresses are reloaded
8130 : somewhat differently, and allowing them here leads
8131 : to problems. */
8132 : : (GET_CODE (rld[r].out) != POST_MODIFY
8133 0 : && GET_CODE (rld[r].out) != PRE_MODIFY))))
8134 : {
8135 0 : rtx reg;
8136 :
8137 0 : reg = reload_reg_rtx_for_output[r];
8138 0 : if (reload_reg_rtx_reaches_end_p (reg, r))
8139 : {
8140 0 : machine_mode mode = GET_MODE (reg);
8141 0 : int regno = REGNO (reg);
8142 0 : int nregs = REG_NREGS (reg);
8143 0 : rtx out = (REG_P (rld[r].out)
8144 0 : ? rld[r].out
8145 0 : : rld[r].out_reg
8146 0 : ? rld[r].out_reg
8147 0 : /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8148 0 : int out_regno = REGNO (out);
8149 0 : int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8150 0 : : hard_regno_nregs (out_regno, mode));
8151 0 : bool piecemeal;
8152 :
8153 0 : spill_reg_store[regno] = new_spill_reg_store[regno];
8154 0 : spill_reg_stored_to[regno] = out;
8155 0 : reg_last_reload_reg[out_regno] = reg;
8156 :
8157 0 : piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8158 0 : && nregs == out_nregs
8159 0 : && inherit_piecemeal_p (out_regno, regno, mode));
8160 :
8161 : /* If OUT_REGNO is a hard register, it may occupy more than
8162 : one register. If it does, say what is in the
8163 : rest of the registers assuming that both registers
8164 : agree on how many words the object takes. If not,
8165 : invalidate the subsequent registers. */
8166 :
8167 0 : if (HARD_REGISTER_NUM_P (out_regno))
8168 0 : for (k = 1; k < out_nregs; k++)
8169 0 : reg_last_reload_reg[out_regno + k]
8170 0 : = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8171 :
8172 : /* Now do the inverse operation. */
8173 0 : for (k = 0; k < nregs; k++)
8174 : {
8175 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8176 0 : reg_reloaded_contents[regno + k]
8177 0 : = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8178 0 : ? out_regno
8179 : : out_regno + k);
8180 0 : reg_reloaded_insn[regno + k] = insn;
8181 0 : SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8182 : }
8183 : }
8184 : }
8185 : /* Maybe the spill reg contains a copy of reload_in. Only do
8186 : something if there will not be an output reload for
8187 : the register being reloaded. */
8188 0 : else if (rld[r].out_reg == 0
8189 0 : && rld[r].in != 0
8190 0 : && ((REG_P (rld[r].in)
8191 0 : && !HARD_REGISTER_P (rld[r].in)
8192 0 : && !REGNO_REG_SET_P (®_has_output_reload,
8193 : REGNO (rld[r].in)))
8194 0 : || (REG_P (rld[r].in_reg)
8195 0 : && !REGNO_REG_SET_P (®_has_output_reload,
8196 : REGNO (rld[r].in_reg))))
8197 0 : && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8198 : {
8199 0 : rtx reg;
8200 :
8201 0 : reg = reload_reg_rtx_for_input[r];
8202 0 : if (reload_reg_rtx_reaches_end_p (reg, r))
8203 : {
8204 0 : machine_mode mode;
8205 0 : int regno;
8206 0 : int nregs;
8207 0 : int in_regno;
8208 0 : int in_nregs;
8209 0 : rtx in;
8210 0 : bool piecemeal;
8211 :
8212 0 : mode = GET_MODE (reg);
8213 0 : regno = REGNO (reg);
8214 0 : nregs = REG_NREGS (reg);
8215 0 : if (REG_P (rld[r].in)
8216 0 : && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8217 : in = rld[r].in;
8218 0 : else if (REG_P (rld[r].in_reg))
8219 : in = rld[r].in_reg;
8220 : else
8221 0 : in = XEXP (rld[r].in_reg, 0);
8222 0 : in_regno = REGNO (in);
8223 :
8224 0 : in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8225 0 : : hard_regno_nregs (in_regno, mode));
8226 :
8227 0 : reg_last_reload_reg[in_regno] = reg;
8228 :
8229 0 : piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8230 0 : && nregs == in_nregs
8231 0 : && inherit_piecemeal_p (regno, in_regno, mode));
8232 :
8233 0 : if (HARD_REGISTER_NUM_P (in_regno))
8234 0 : for (k = 1; k < in_nregs; k++)
8235 0 : reg_last_reload_reg[in_regno + k]
8236 0 : = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8237 :
8238 : /* Unless we inherited this reload, show we haven't
8239 : recently done a store.
8240 : Previous stores of inherited auto_inc expressions
8241 : also have to be discarded. */
8242 0 : if (! reload_inherited[r]
8243 0 : || (rld[r].out && ! rld[r].out_reg))
8244 0 : spill_reg_store[regno] = 0;
8245 :
8246 0 : for (k = 0; k < nregs; k++)
8247 : {
8248 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8249 0 : reg_reloaded_contents[regno + k]
8250 0 : = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8251 0 : ? in_regno
8252 : : in_regno + k);
8253 0 : reg_reloaded_insn[regno + k] = insn;
8254 0 : SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8255 : }
8256 : }
8257 : }
8258 : }
8259 :
8260 : /* The following if-statement was #if 0'd in 1.34 (or before...).
8261 : It's re-enabled in 1.35 because supposedly nothing else
8262 : deals with this problem. */
8263 :
8264 : /* If a register gets output-reloaded from a non-spill register,
8265 : that invalidates any previous reloaded copy of it.
8266 : But forget_old_reloads_1 won't get to see it, because
8267 : it thinks only about the original insn. So invalidate it here.
8268 : Also do the same thing for RELOAD_OTHER constraints where the
8269 : output is discarded. */
8270 : if (i < 0
8271 0 : && ((rld[r].out != 0
8272 0 : && (REG_P (rld[r].out)
8273 0 : || (MEM_P (rld[r].out)
8274 0 : && REG_P (rld[r].out_reg))))
8275 0 : || (rld[r].out == 0 && rld[r].out_reg
8276 0 : && REG_P (rld[r].out_reg))))
8277 : {
8278 0 : rtx out = ((rld[r].out && REG_P (rld[r].out))
8279 0 : ? rld[r].out : rld[r].out_reg);
8280 0 : int out_regno = REGNO (out);
8281 0 : machine_mode mode = GET_MODE (out);
8282 :
8283 : /* REG_RTX is now set or clobbered by the main instruction.
8284 : As the comment above explains, forget_old_reloads_1 only
8285 : sees the original instruction, and there is no guarantee
8286 : that the original instruction also clobbered REG_RTX.
8287 : For example, if find_reloads sees that the input side of
8288 : a matched operand pair dies in this instruction, it may
8289 : use the input register as the reload register.
8290 :
8291 : Calling forget_old_reloads_1 is a waste of effort if
8292 : REG_RTX is also the output register.
8293 :
8294 : If we know that REG_RTX holds the value of a pseudo
8295 : register, the code after the call will record that fact. */
8296 0 : if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8297 0 : forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8298 :
8299 0 : if (!HARD_REGISTER_NUM_P (out_regno))
8300 : {
8301 0 : rtx src_reg;
8302 0 : rtx_insn *store_insn = NULL;
8303 :
8304 0 : reg_last_reload_reg[out_regno] = 0;
8305 :
8306 : /* If we can find a hard register that is stored, record
8307 : the storing insn so that we may delete this insn with
8308 : delete_output_reload. */
8309 0 : src_reg = reload_reg_rtx_for_output[r];
8310 :
8311 0 : if (src_reg)
8312 : {
8313 0 : if (reload_reg_rtx_reaches_end_p (src_reg, r))
8314 0 : store_insn = new_spill_reg_store[REGNO (src_reg)];
8315 : else
8316 : src_reg = NULL_RTX;
8317 : }
8318 : else
8319 : {
8320 : /* If this is an optional reload, try to find the
8321 : source reg from an input reload. */
8322 0 : rtx set = single_set (insn);
8323 0 : if (set && SET_DEST (set) == rld[r].out)
8324 : {
8325 0 : int k;
8326 :
8327 0 : src_reg = SET_SRC (set);
8328 0 : store_insn = insn;
8329 0 : for (k = 0; k < n_reloads; k++)
8330 : {
8331 0 : if (rld[k].in == src_reg)
8332 : {
8333 0 : src_reg = reload_reg_rtx_for_input[k];
8334 0 : break;
8335 : }
8336 : }
8337 : }
8338 : }
8339 0 : if (src_reg && REG_P (src_reg)
8340 0 : && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8341 : {
8342 0 : int src_regno, src_nregs, k;
8343 0 : rtx note;
8344 :
8345 0 : gcc_assert (GET_MODE (src_reg) == mode);
8346 0 : src_regno = REGNO (src_reg);
8347 0 : src_nregs = hard_regno_nregs (src_regno, mode);
8348 : /* The place where to find a death note varies with
8349 : PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8350 : necessarily checked exactly in the code that moves
8351 : notes, so just check both locations. */
8352 0 : note = find_regno_note (insn, REG_DEAD, src_regno);
8353 0 : if (! note && store_insn)
8354 0 : note = find_regno_note (store_insn, REG_DEAD, src_regno);
8355 0 : for (k = 0; k < src_nregs; k++)
8356 : {
8357 0 : spill_reg_store[src_regno + k] = store_insn;
8358 0 : spill_reg_stored_to[src_regno + k] = out;
8359 0 : reg_reloaded_contents[src_regno + k] = out_regno;
8360 0 : reg_reloaded_insn[src_regno + k] = store_insn;
8361 0 : CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8362 0 : SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8363 0 : SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8364 0 : if (note)
8365 0 : SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8366 : else
8367 0 : CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8368 : }
8369 0 : reg_last_reload_reg[out_regno] = src_reg;
8370 : /* We have to set reg_has_output_reload here, or else
8371 : forget_old_reloads_1 will clear reg_last_reload_reg
8372 : right away. */
8373 0 : SET_REGNO_REG_SET (®_has_output_reload,
8374 : out_regno);
8375 : }
8376 : }
8377 : else
8378 : {
8379 0 : int k, out_nregs = hard_regno_nregs (out_regno, mode);
8380 :
8381 0 : for (k = 0; k < out_nregs; k++)
8382 0 : reg_last_reload_reg[out_regno + k] = 0;
8383 : }
8384 : }
8385 : }
8386 0 : reg_reloaded_dead |= reg_reloaded_died;
8387 0 : }
8388 :
8389 :
8390 : /* Helper for emit_insn_if_valid_for_reload. */
8391 :
8392 : static rtx_insn *
8393 0 : emit_insn_if_valid_for_reload_1 (rtx pat)
8394 : {
8395 0 : rtx_insn *last = get_last_insn ();
8396 0 : int code;
8397 :
8398 0 : rtx_insn *insn = emit_insn (pat);
8399 0 : code = recog_memoized (insn);
8400 :
8401 0 : if (code >= 0)
8402 : {
8403 0 : extract_insn (insn);
8404 : /* We want constrain operands to treat this insn strictly in its
8405 : validity determination, i.e., the way it would after reload has
8406 : completed. */
8407 0 : if (constrain_operands (1, get_enabled_alternatives (insn)))
8408 : return insn;
8409 : }
8410 :
8411 0 : delete_insns_since (last);
8412 0 : return NULL;
8413 : }
8414 :
8415 : /* Go through the motions to emit INSN and test if it is strictly valid.
8416 : Return the emitted insn if valid, else return NULL. */
8417 :
8418 : static rtx_insn *
8419 0 : emit_insn_if_valid_for_reload (rtx pat)
8420 : {
8421 0 : rtx_insn *insn = emit_insn_if_valid_for_reload_1 (pat);
8422 :
8423 0 : if (insn)
8424 : return insn;
8425 :
8426 : /* If the pattern is a SET, and this target has a single
8427 : flags-register, try again with a PARALLEL that clobbers that
8428 : register. */
8429 0 : if (targetm.flags_regnum == INVALID_REGNUM || GET_CODE (pat) != SET)
8430 : return NULL;
8431 :
8432 0 : rtx flags_clobber = gen_hard_reg_clobber (CCmode, targetm.flags_regnum);
8433 0 : rtx parpat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, flags_clobber));
8434 :
8435 0 : return emit_insn_if_valid_for_reload (parpat);
8436 : }
8437 :
8438 : /* Emit code to perform a reload from IN (which may be a reload register) to
8439 : OUT (which may also be a reload register). IN or OUT is from operand
8440 : OPNUM with reload type TYPE.
8441 :
8442 : Returns first insn emitted. */
8443 :
8444 : static rtx_insn *
8445 0 : gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8446 : {
8447 0 : rtx_insn *last = get_last_insn ();
8448 0 : rtx_insn *tem;
8449 0 : rtx tem1, tem2;
8450 :
8451 : /* If IN is a paradoxical SUBREG, remove it and try to put the
8452 : opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8453 0 : if (!strip_paradoxical_subreg (&in, &out))
8454 0 : strip_paradoxical_subreg (&out, &in);
8455 :
8456 : /* How to do this reload can get quite tricky. Normally, we are being
8457 : asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8458 : register that didn't get a hard register. In that case we can just
8459 : call emit_move_insn.
8460 :
8461 : We can also be asked to reload a PLUS that adds a register or a MEM to
8462 : another register, constant or MEM. This can occur during frame pointer
8463 : elimination and while reloading addresses. This case is handled by
8464 : trying to emit a single insn to perform the add. If it is not valid,
8465 : we use a two insn sequence.
8466 :
8467 : Or we can be asked to reload an unary operand that was a fragment of
8468 : an addressing mode, into a register. If it isn't recognized as-is,
8469 : we try making the unop operand and the reload-register the same:
8470 : (set reg:X (unop:X expr:Y))
8471 : -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8472 :
8473 : Finally, we could be called to handle an 'o' constraint by putting
8474 : an address into a register. In that case, we first try to do this
8475 : with a named pattern of "reload_load_address". If no such pattern
8476 : exists, we just emit a SET insn and hope for the best (it will normally
8477 : be valid on machines that use 'o').
8478 :
8479 : This entire process is made complex because reload will never
8480 : process the insns we generate here and so we must ensure that
8481 : they will fit their constraints and also by the fact that parts of
8482 : IN might be being reloaded separately and replaced with spill registers.
8483 : Because of this, we are, in some sense, just guessing the right approach
8484 : here. The one listed above seems to work.
8485 :
8486 : ??? At some point, this whole thing needs to be rethought. */
8487 :
8488 0 : if (GET_CODE (in) == PLUS
8489 0 : && (REG_P (XEXP (in, 0))
8490 : || GET_CODE (XEXP (in, 0)) == SUBREG
8491 : || MEM_P (XEXP (in, 0)))
8492 0 : && (REG_P (XEXP (in, 1))
8493 0 : || GET_CODE (XEXP (in, 1)) == SUBREG
8494 0 : || CONSTANT_P (XEXP (in, 1))
8495 0 : || MEM_P (XEXP (in, 1))))
8496 : {
8497 : /* We need to compute the sum of a register or a MEM and another
8498 : register, constant, or MEM, and put it into the reload
8499 : register. The best possible way of doing this is if the machine
8500 : has a three-operand ADD insn that accepts the required operands.
8501 :
8502 : The simplest approach is to try to generate such an insn and see if it
8503 : is recognized and matches its constraints. If so, it can be used.
8504 :
8505 : It might be better not to actually emit the insn unless it is valid,
8506 : but we need to pass the insn as an operand to `recog' and
8507 : `extract_insn' and it is simpler to emit and then delete the insn if
8508 : not valid than to dummy things up. */
8509 :
8510 0 : rtx op0, op1, tem;
8511 0 : rtx_insn *insn;
8512 0 : enum insn_code code;
8513 :
8514 0 : op0 = find_replacement (&XEXP (in, 0));
8515 0 : op1 = find_replacement (&XEXP (in, 1));
8516 :
8517 : /* Since constraint checking is strict, commutativity won't be
8518 : checked, so we need to do that here to avoid spurious failure
8519 : if the add instruction is two-address and the second operand
8520 : of the add is the same as the reload reg, which is frequently
8521 : the case. If the insn would be A = B + A, rearrange it so
8522 : it will be A = A + B as constrain_operands expects. */
8523 :
8524 0 : if (REG_P (XEXP (in, 1))
8525 0 : && REGNO (out) == REGNO (XEXP (in, 1)))
8526 : tem = op0, op0 = op1, op1 = tem;
8527 :
8528 0 : if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8529 0 : in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8530 :
8531 0 : insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8532 0 : if (insn)
8533 : return insn;
8534 :
8535 : /* If that failed, we must use a conservative two-insn sequence.
8536 :
8537 : Use a move to copy one operand into the reload register. Prefer
8538 : to reload a constant, MEM or pseudo since the move patterns can
8539 : handle an arbitrary operand. If OP1 is not a constant, MEM or
8540 : pseudo and OP1 is not a valid operand for an add instruction, then
8541 : reload OP1.
8542 :
8543 : After reloading one of the operands into the reload register, add
8544 : the reload register to the output register.
8545 :
8546 : If there is another way to do this for a specific machine, a
8547 : DEFINE_PEEPHOLE should be specified that recognizes the sequence
8548 : we emit below. */
8549 :
8550 0 : code = optab_handler (add_optab, GET_MODE (out));
8551 :
8552 0 : if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8553 0 : || (REG_P (op1)
8554 0 : && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8555 0 : || (code != CODE_FOR_nothing
8556 0 : && !insn_operand_matches (code, 2, op1)))
8557 : tem = op0, op0 = op1, op1 = tem;
8558 :
8559 0 : gen_reload (out, op0, opnum, type);
8560 :
8561 : /* If OP0 and OP1 are the same, we can use OUT for OP1.
8562 : This fixes a problem on the 32K where the stack pointer cannot
8563 : be used as an operand of an add insn. */
8564 :
8565 0 : if (rtx_equal_p (op0, op1))
8566 0 : op1 = out;
8567 :
8568 0 : insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8569 0 : if (insn)
8570 : {
8571 : /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8572 0 : set_dst_reg_note (insn, REG_EQUIV, in, out);
8573 0 : return insn;
8574 : }
8575 :
8576 : /* If that failed, copy the address register to the reload register.
8577 : Then add the constant to the reload register. */
8578 :
8579 0 : gcc_assert (!reg_overlap_mentioned_p (out, op0));
8580 0 : gen_reload (out, op1, opnum, type);
8581 0 : insn = emit_insn (gen_add2_insn (out, op0));
8582 0 : set_dst_reg_note (insn, REG_EQUIV, in, out);
8583 0 : }
8584 :
8585 : /* If we need a memory location to do the move, do it that way. */
8586 0 : else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8587 0 : (REG_P (tem1) && REG_P (tem2)))
8588 0 : && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8589 0 : && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8590 0 : && targetm.secondary_memory_needed (GET_MODE (out),
8591 0 : REGNO_REG_CLASS (REGNO (tem1)),
8592 0 : REGNO_REG_CLASS (REGNO (tem2))))
8593 : {
8594 : /* Get the memory to use and rewrite both registers to its mode. */
8595 0 : rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8596 :
8597 0 : if (GET_MODE (loc) != GET_MODE (out))
8598 0 : out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8599 :
8600 0 : if (GET_MODE (loc) != GET_MODE (in))
8601 0 : in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8602 :
8603 0 : gen_reload (loc, in, opnum, type);
8604 0 : gen_reload (out, loc, opnum, type);
8605 : }
8606 0 : else if (REG_P (out) && UNARY_P (in))
8607 : {
8608 0 : rtx op1;
8609 0 : rtx out_moded;
8610 0 : rtx_insn *set;
8611 :
8612 0 : op1 = find_replacement (&XEXP (in, 0));
8613 0 : if (op1 != XEXP (in, 0))
8614 0 : in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8615 :
8616 : /* First, try a plain SET. */
8617 0 : set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in));
8618 0 : if (set)
8619 : return set;
8620 :
8621 : /* If that failed, move the inner operand to the reload
8622 : register, and try the same unop with the inner expression
8623 : replaced with the reload register. */
8624 :
8625 0 : if (GET_MODE (op1) != GET_MODE (out))
8626 0 : out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8627 : else
8628 : out_moded = out;
8629 :
8630 0 : gen_reload (out_moded, op1, opnum, type);
8631 :
8632 0 : rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8633 : out_moded));
8634 0 : rtx_insn *insn = emit_insn_if_valid_for_reload (temp);
8635 0 : if (insn)
8636 : {
8637 0 : set_unique_reg_note (insn, REG_EQUIV, in);
8638 0 : return insn;
8639 : }
8640 :
8641 0 : fatal_insn ("failure trying to reload:", in);
8642 : }
8643 : /* If IN is a simple operand, use gen_move_insn. */
8644 0 : else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8645 : {
8646 0 : tem = emit_insn (gen_move_insn (out, in));
8647 : /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8648 0 : mark_jump_label (in, tem, 0);
8649 : }
8650 :
8651 0 : else if (targetm.have_reload_load_address ())
8652 0 : emit_insn (targetm.gen_reload_load_address (out, in));
8653 :
8654 : /* Otherwise, just write (set OUT IN) and hope for the best. */
8655 : else
8656 0 : emit_insn (gen_rtx_SET (out, in));
8657 :
8658 : /* Return the first insn emitted.
8659 : We cannot just return get_last_insn, because there may have
8660 : been multiple instructions emitted. Also note that gen_move_insn may
8661 : emit more than one insn itself, so we cannot assume that there is one
8662 : insn emitted per emit_insn_before call. */
8663 :
8664 0 : return last ? NEXT_INSN (last) : get_insns ();
8665 : }
8666 :
8667 : /* Delete a previously made output-reload whose result we now believe
8668 : is not needed. First we double-check.
8669 :
8670 : INSN is the insn now being processed.
8671 : LAST_RELOAD_REG is the hard register number for which we want to delete
8672 : the last output reload.
8673 : J is the reload-number that originally used REG. The caller has made
8674 : certain that reload J doesn't use REG any longer for input.
8675 : NEW_RELOAD_REG is reload register that reload J is using for REG. */
8676 :
8677 : static void
8678 0 : delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
8679 : rtx new_reload_reg)
8680 : {
8681 0 : rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg];
8682 0 : rtx reg = spill_reg_stored_to[last_reload_reg];
8683 0 : int k;
8684 0 : int n_occurrences;
8685 0 : int n_inherited = 0;
8686 0 : rtx substed;
8687 0 : unsigned regno;
8688 0 : int nregs;
8689 :
8690 : /* It is possible that this reload has been only used to set another reload
8691 : we eliminated earlier and thus deleted this instruction too. */
8692 0 : if (output_reload_insn->deleted ())
8693 : return;
8694 :
8695 : /* Get the raw pseudo-register referred to. */
8696 :
8697 0 : while (GET_CODE (reg) == SUBREG)
8698 0 : reg = SUBREG_REG (reg);
8699 0 : substed = reg_equiv_memory_loc (REGNO (reg));
8700 :
8701 : /* This is unsafe if the operand occurs more often in the current
8702 : insn than it is inherited. */
8703 0 : for (k = n_reloads - 1; k >= 0; k--)
8704 : {
8705 0 : rtx reg2 = rld[k].in;
8706 0 : if (! reg2)
8707 0 : continue;
8708 0 : if (MEM_P (reg2) || reload_override_in[k])
8709 0 : reg2 = rld[k].in_reg;
8710 :
8711 : if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
8712 : reg2 = XEXP (rld[k].in_reg, 0);
8713 :
8714 0 : while (GET_CODE (reg2) == SUBREG)
8715 0 : reg2 = SUBREG_REG (reg2);
8716 0 : if (rtx_equal_p (reg2, reg))
8717 : {
8718 0 : if (reload_inherited[k] || reload_override_in[k] || k == j)
8719 0 : n_inherited++;
8720 : else
8721 : return;
8722 : }
8723 : }
8724 0 : n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8725 0 : if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8726 0 : n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8727 : reg, 0);
8728 0 : if (substed)
8729 0 : n_occurrences += count_occurrences (PATTERN (insn),
8730 0 : eliminate_regs (substed, VOIDmode,
8731 : NULL_RTX), 0);
8732 0 : for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8733 : {
8734 0 : gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8735 0 : n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8736 : }
8737 0 : if (n_occurrences > n_inherited)
8738 : return;
8739 :
8740 0 : regno = REGNO (reg);
8741 0 : nregs = REG_NREGS (reg);
8742 :
8743 : /* If the pseudo-reg we are reloading is no longer referenced
8744 : anywhere between the store into it and here,
8745 : and we're within the same basic block, then the value can only
8746 : pass through the reload reg and end up here.
8747 : Otherwise, give up--return. */
8748 0 : for (rtx_insn *i1 = NEXT_INSN (output_reload_insn);
8749 0 : i1 != insn; i1 = NEXT_INSN (i1))
8750 : {
8751 0 : if (NOTE_INSN_BASIC_BLOCK_P (i1))
8752 : return;
8753 0 : if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8754 0 : && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8755 : {
8756 : /* If this is USE in front of INSN, we only have to check that
8757 : there are no more references than accounted for by inheritance. */
8758 0 : while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8759 : {
8760 0 : n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8761 0 : i1 = NEXT_INSN (i1);
8762 : }
8763 0 : if (n_occurrences <= n_inherited && i1 == insn)
8764 : break;
8765 : return;
8766 : }
8767 : }
8768 :
8769 : /* We will be deleting the insn. Remove the spill reg information. */
8770 0 : for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; )
8771 : {
8772 0 : spill_reg_store[last_reload_reg + k] = 0;
8773 0 : spill_reg_stored_to[last_reload_reg + k] = 0;
8774 : }
8775 :
8776 : /* The caller has already checked that REG dies or is set in INSN.
8777 : It has also checked that we are optimizing, and thus some
8778 : inaccuracies in the debugging information are acceptable.
8779 : So we could just delete output_reload_insn. But in some cases
8780 : we can improve the debugging information without sacrificing
8781 : optimization - maybe even improving the code: See if the pseudo
8782 : reg has been completely replaced with reload regs. If so, delete
8783 : the store insn and forget we had a stack slot for the pseudo. */
8784 0 : if (rld[j].out != rld[j].in
8785 0 : && REG_N_DEATHS (REGNO (reg)) == 1
8786 0 : && REG_N_SETS (REGNO (reg)) == 1
8787 0 : && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8788 0 : && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8789 : {
8790 0 : rtx_insn *i2;
8791 :
8792 : /* We know that it was used only between here and the beginning of
8793 : the current basic block. (We also know that the last use before
8794 : INSN was the output reload we are thinking of deleting, but never
8795 : mind that.) Search that range; see if any ref remains. */
8796 0 : for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8797 : {
8798 0 : rtx set = single_set (i2);
8799 :
8800 : /* Uses which just store in the pseudo don't count,
8801 : since if they are the only uses, they are dead. */
8802 0 : if (set != 0 && SET_DEST (set) == reg)
8803 0 : continue;
8804 0 : if (LABEL_P (i2) || JUMP_P (i2))
8805 : break;
8806 0 : if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8807 0 : && reg_mentioned_p (reg, PATTERN (i2)))
8808 : {
8809 : /* Some other ref remains; just delete the output reload we
8810 : know to be dead. */
8811 0 : delete_address_reloads (output_reload_insn, insn);
8812 0 : delete_insn (output_reload_insn);
8813 0 : return;
8814 : }
8815 : }
8816 :
8817 : /* Delete the now-dead stores into this pseudo. Note that this
8818 : loop also takes care of deleting output_reload_insn. */
8819 0 : for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8820 : {
8821 0 : rtx set = single_set (i2);
8822 :
8823 0 : if (set != 0 && SET_DEST (set) == reg)
8824 : {
8825 0 : delete_address_reloads (i2, insn);
8826 0 : delete_insn (i2);
8827 : }
8828 0 : if (LABEL_P (i2) || JUMP_P (i2))
8829 : break;
8830 : }
8831 :
8832 : /* For the debugging info, say the pseudo lives in this reload reg. */
8833 0 : reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8834 0 : if (ira_conflicts_p)
8835 : /* Inform IRA about the change. */
8836 0 : ira_mark_allocation_change (REGNO (reg));
8837 0 : alter_reg (REGNO (reg), -1, false);
8838 : }
8839 : else
8840 : {
8841 0 : delete_address_reloads (output_reload_insn, insn);
8842 0 : delete_insn (output_reload_insn);
8843 : }
8844 : }
8845 :
8846 : /* We are going to delete DEAD_INSN. Recursively delete loads of
8847 : reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8848 : CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8849 : static void
8850 0 : delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn)
8851 : {
8852 0 : rtx set = single_set (dead_insn);
8853 0 : rtx set2, dst;
8854 0 : rtx_insn *prev, *next;
8855 0 : if (set)
8856 : {
8857 0 : rtx dst = SET_DEST (set);
8858 0 : if (MEM_P (dst))
8859 0 : delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8860 : }
8861 : /* If we deleted the store from a reloaded post_{in,de}c expression,
8862 : we can delete the matching adds. */
8863 0 : prev = PREV_INSN (dead_insn);
8864 0 : next = NEXT_INSN (dead_insn);
8865 0 : if (! prev || ! next)
8866 : return;
8867 0 : set = single_set (next);
8868 0 : set2 = single_set (prev);
8869 0 : if (! set || ! set2
8870 0 : || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8871 0 : || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8872 0 : || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8873 : return;
8874 0 : dst = SET_DEST (set);
8875 0 : if (! rtx_equal_p (dst, SET_DEST (set2))
8876 0 : || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8877 0 : || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8878 0 : || (INTVAL (XEXP (SET_SRC (set), 1))
8879 0 : != -INTVAL (XEXP (SET_SRC (set2), 1))))
8880 : return;
8881 0 : delete_related_insns (prev);
8882 0 : delete_related_insns (next);
8883 : }
8884 :
8885 : /* Subfunction of delete_address_reloads: process registers found in X. */
8886 : static void
8887 0 : delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn)
8888 : {
8889 0 : rtx_insn *prev, *i2;
8890 0 : rtx set, dst;
8891 0 : int i, j;
8892 0 : enum rtx_code code = GET_CODE (x);
8893 :
8894 0 : if (code != REG)
8895 : {
8896 0 : const char *fmt = GET_RTX_FORMAT (code);
8897 0 : for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8898 : {
8899 0 : if (fmt[i] == 'e')
8900 0 : delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8901 0 : else if (fmt[i] == 'E')
8902 : {
8903 0 : for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8904 0 : delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8905 : current_insn);
8906 : }
8907 : }
8908 : return;
8909 : }
8910 :
8911 0 : if (spill_reg_order[REGNO (x)] < 0)
8912 : return;
8913 :
8914 : /* Scan backwards for the insn that sets x. This might be a way back due
8915 : to inheritance. */
8916 0 : for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8917 : {
8918 0 : code = GET_CODE (prev);
8919 0 : if (code == CODE_LABEL || code == JUMP_INSN)
8920 : return;
8921 0 : if (!INSN_P (prev))
8922 0 : continue;
8923 0 : if (reg_set_p (x, PATTERN (prev)))
8924 : break;
8925 0 : if (reg_referenced_p (x, PATTERN (prev)))
8926 : return;
8927 : }
8928 0 : if (! prev || INSN_UID (prev) < reload_first_uid)
8929 : return;
8930 : /* Check that PREV only sets the reload register. */
8931 0 : set = single_set (prev);
8932 0 : if (! set)
8933 : return;
8934 0 : dst = SET_DEST (set);
8935 0 : if (!REG_P (dst)
8936 0 : || ! rtx_equal_p (dst, x))
8937 : return;
8938 0 : if (! reg_set_p (dst, PATTERN (dead_insn)))
8939 : {
8940 : /* Check if DST was used in a later insn -
8941 : it might have been inherited. */
8942 0 : for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8943 : {
8944 0 : if (LABEL_P (i2))
8945 : break;
8946 0 : if (! INSN_P (i2))
8947 0 : continue;
8948 0 : if (reg_referenced_p (dst, PATTERN (i2)))
8949 : {
8950 : /* If there is a reference to the register in the current insn,
8951 : it might be loaded in a non-inherited reload. If no other
8952 : reload uses it, that means the register is set before
8953 : referenced. */
8954 0 : if (i2 == current_insn)
8955 : {
8956 0 : for (j = n_reloads - 1; j >= 0; j--)
8957 0 : if ((rld[j].reg_rtx == dst && reload_inherited[j])
8958 0 : || reload_override_in[j] == dst)
8959 : return;
8960 0 : for (j = n_reloads - 1; j >= 0; j--)
8961 0 : if (rld[j].in && rld[j].reg_rtx == dst)
8962 : break;
8963 0 : if (j >= 0)
8964 : break;
8965 : }
8966 : return;
8967 : }
8968 0 : if (JUMP_P (i2))
8969 : break;
8970 : /* If DST is still live at CURRENT_INSN, check if it is used for
8971 : any reload. Note that even if CURRENT_INSN sets DST, we still
8972 : have to check the reloads. */
8973 0 : if (i2 == current_insn)
8974 : {
8975 0 : for (j = n_reloads - 1; j >= 0; j--)
8976 0 : if ((rld[j].reg_rtx == dst && reload_inherited[j])
8977 0 : || reload_override_in[j] == dst)
8978 : return;
8979 : /* ??? We can't finish the loop here, because dst might be
8980 : allocated to a pseudo in this block if no reload in this
8981 : block needs any of the classes containing DST - see
8982 : spill_hard_reg. There is no easy way to tell this, so we
8983 : have to scan till the end of the basic block. */
8984 : }
8985 0 : if (reg_set_p (dst, PATTERN (i2)))
8986 : break;
8987 : }
8988 : }
8989 0 : delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8990 0 : reg_reloaded_contents[REGNO (dst)] = -1;
8991 0 : delete_insn (prev);
8992 : }
8993 :
8994 : /* Output reload-insns to reload VALUE into RELOADREG.
8995 : VALUE is an autoincrement or autodecrement RTX whose operand
8996 : is a register or memory location;
8997 : so reloading involves incrementing that location.
8998 : IN is either identical to VALUE, or some cheaper place to reload from.
8999 :
9000 : INC_AMOUNT is the number to increment or decrement by (always positive).
9001 : This cannot be deduced from VALUE. */
9002 :
9003 : static void
9004 0 : inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount)
9005 : {
9006 : /* REG or MEM to be copied and incremented. */
9007 0 : rtx incloc = find_replacement (&XEXP (value, 0));
9008 : /* Nonzero if increment after copying. */
9009 0 : int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9010 0 : || GET_CODE (value) == POST_MODIFY);
9011 0 : rtx_insn *last;
9012 0 : rtx inc;
9013 0 : rtx_insn *add_insn;
9014 0 : int code;
9015 0 : rtx real_in = in == value ? incloc : in;
9016 :
9017 : /* No hard register is equivalent to this register after
9018 : inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9019 : we could inc/dec that register as well (maybe even using it for
9020 : the source), but I'm not sure it's worth worrying about. */
9021 0 : if (REG_P (incloc))
9022 0 : reg_last_reload_reg[REGNO (incloc)] = 0;
9023 :
9024 0 : if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9025 : {
9026 0 : gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9027 0 : inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9028 : }
9029 : else
9030 : {
9031 0 : if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9032 0 : inc_amount = -inc_amount;
9033 :
9034 0 : inc = gen_int_mode (inc_amount, Pmode);
9035 : }
9036 :
9037 : /* If this is post-increment, first copy the location to the reload reg. */
9038 0 : if (post && real_in != reloadreg)
9039 0 : emit_insn (gen_move_insn (reloadreg, real_in));
9040 :
9041 0 : if (in == value)
9042 : {
9043 : /* See if we can directly increment INCLOC. Use a method similar to
9044 : that in gen_reload. */
9045 :
9046 0 : last = get_last_insn ();
9047 0 : add_insn = emit_insn (gen_rtx_SET (incloc,
9048 : gen_rtx_PLUS (GET_MODE (incloc),
9049 : incloc, inc)));
9050 :
9051 0 : code = recog_memoized (add_insn);
9052 0 : if (code >= 0)
9053 : {
9054 0 : extract_insn (add_insn);
9055 0 : if (constrain_operands (1, get_enabled_alternatives (add_insn)))
9056 : {
9057 : /* If this is a pre-increment and we have incremented the value
9058 : where it lives, copy the incremented value to RELOADREG to
9059 : be used as an address. */
9060 :
9061 0 : if (! post)
9062 0 : emit_insn (gen_move_insn (reloadreg, incloc));
9063 : return;
9064 : }
9065 : }
9066 0 : delete_insns_since (last);
9067 : }
9068 :
9069 : /* If couldn't do the increment directly, must increment in RELOADREG.
9070 : The way we do this depends on whether this is pre- or post-increment.
9071 : For pre-increment, copy INCLOC to the reload register, increment it
9072 : there, then save back. */
9073 :
9074 0 : if (! post)
9075 : {
9076 0 : if (in != reloadreg)
9077 0 : emit_insn (gen_move_insn (reloadreg, real_in));
9078 0 : emit_insn (gen_add2_insn (reloadreg, inc));
9079 0 : emit_insn (gen_move_insn (incloc, reloadreg));
9080 : }
9081 : else
9082 : {
9083 : /* Postincrement.
9084 : Because this might be a jump insn or a compare, and because RELOADREG
9085 : may not be available after the insn in an input reload, we must do
9086 : the incrementation before the insn being reloaded for.
9087 :
9088 : We have already copied IN to RELOADREG. Increment the copy in
9089 : RELOADREG, save that back, then decrement RELOADREG so it has
9090 : the original value. */
9091 :
9092 0 : emit_insn (gen_add2_insn (reloadreg, inc));
9093 0 : emit_insn (gen_move_insn (incloc, reloadreg));
9094 0 : if (CONST_INT_P (inc))
9095 0 : emit_insn (gen_add2_insn (reloadreg,
9096 0 : gen_int_mode (-INTVAL (inc),
9097 0 : GET_MODE (reloadreg))));
9098 : else
9099 0 : emit_insn (gen_sub2_insn (reloadreg, inc));
9100 : }
9101 : }
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