GCC Middle and Back End API Reference
ira.h
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1/* Communication between the Integrated Register Allocator (IRA) and
2 the rest of the compiler.
3 Copyright (C) 2006-2024 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify it under
9the terms of the GNU General Public License as published by the Free
10Software Foundation; either version 3, or (at your option) any later
11version.
12
13GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14WARRANTY; without even the implied warranty of MERCHANTABILITY or
15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#ifndef GCC_IRA_H
23#define GCC_IRA_H
24
25#include "emit-rtl.h"
26
27/* True when we use LRA instead of reload pass for the current
28 function. */
29extern bool ira_use_lra_p;
30
31/* True if we have allocno conflicts. It is false for non-optimized
32 mode or when the conflict table is too big. */
33extern bool ira_conflicts_p;
34
36{
37 /* Map: hard register number -> allocno class it belongs to. If the
38 corresponding class is NO_REGS, the hard register is not available
39 for allocation. */
40 enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
41
42 /* Number of allocno classes. Allocno classes are register classes
43 which can be used for allocations of allocnos. */
45
46 /* The array containing allocno classes. Only first
47 IRA_ALLOCNO_CLASSES_NUM elements are used for this. */
48 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
49
50 /* Map of all register classes to corresponding allocno classes
51 containing the given class. If given class is not a subset of an
52 allocno class, we translate it into the cheapest allocno class. */
53 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
54
55 /* Number of pressure classes. Pressure classes are register
56 classes for which we calculate register pressure. */
58
59 /* The array containing pressure classes. Only first
60 IRA_PRESSURE_CLASSES_NUM elements are used for this. */
61 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
62
63 /* Map of all register classes to corresponding pressure classes
64 containing the given class. If given class is not a subset of an
65 pressure class, we translate it into the cheapest pressure
66 class. */
67 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
68
69 /* Biggest pressure register class containing stack registers.
70 NO_REGS if there are no stack registers. */
72
73 /* Maps: register class x machine mode -> maximal/minimal number of
74 hard registers of given class needed to store value of given
75 mode. */
76 unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
77 unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
78
79 /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */
80 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
81
82 /* Array of number of hard registers of given class which are
83 available for the allocation. The order is defined by the
84 allocation order. */
85 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
86
87 /* The number of elements of the above array for given register
88 class. */
89 int x_ira_class_hard_regs_num[N_REG_CLASSES];
90
91 /* Register class subset relation: TRUE if the first class is a subset
92 of the second one considering only hard registers available for the
93 allocation. */
94 int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
95
96 /* The biggest class inside of intersection of the two classes (that
97 is calculated taking only hard registers available for allocation
98 into account. If the both classes contain no hard registers
99 available for allocation, the value is calculated with taking all
100 hard-registers including fixed ones into account. */
101 enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
102
103 /* True if the two classes (that is calculated taking only hard
104 registers available for allocation into account; are
105 intersected. */
106 bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
107
108 /* If class CL has a single allocatable register of mode M,
109 index [CL][M] gives the number of that register, otherwise it is -1. */
110 short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
111
112 /* Function specific hard registers cannot be used for the register
113 allocation. */
115
116 /* Array whose values are hard regset of hard registers available for
117 the allocation of given register class whose targetm.hard_regno_mode_ok
118 values for given mode are false. */
119 HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
120
121 /* When an allocatable hard register in given mode can not be placed in given
122 register class, it is in the set of the following array element. It can
123 happen only when given mode requires more one hard register. */
124 HARD_REG_SET x_ira_exclude_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
125};
126
127extern struct target_ira default_target_ira;
128#if SWITCHABLE_TARGET
129extern struct target_ira *this_target_ira;
130#else
131#define this_target_ira (&default_target_ira)
132#endif
133
134#define ira_hard_regno_allocno_class \
135 (this_target_ira->x_ira_hard_regno_allocno_class)
136#define ira_allocno_classes_num \
137 (this_target_ira->x_ira_allocno_classes_num)
138#define ira_allocno_classes \
139 (this_target_ira->x_ira_allocno_classes)
140#define ira_allocno_class_translate \
141 (this_target_ira->x_ira_allocno_class_translate)
142#define ira_pressure_classes_num \
143 (this_target_ira->x_ira_pressure_classes_num)
144#define ira_pressure_classes \
145 (this_target_ira->x_ira_pressure_classes)
146#define ira_pressure_class_translate \
147 (this_target_ira->x_ira_pressure_class_translate)
148#define ira_stack_reg_pressure_class \
149 (this_target_ira->x_ira_stack_reg_pressure_class)
150#define ira_reg_class_max_nregs \
151 (this_target_ira->x_ira_reg_class_max_nregs)
152#define ira_reg_class_min_nregs \
153 (this_target_ira->x_ira_reg_class_min_nregs)
154#define ira_memory_move_cost \
155 (this_target_ira->x_ira_memory_move_cost)
156#define ira_class_hard_regs \
157 (this_target_ira->x_ira_class_hard_regs)
158#define ira_class_hard_regs_num \
159 (this_target_ira->x_ira_class_hard_regs_num)
160#define ira_class_subset_p \
161 (this_target_ira->x_ira_class_subset_p)
162#define ira_reg_class_subset \
163 (this_target_ira->x_ira_reg_class_subset)
164#define ira_reg_classes_intersect_p \
165 (this_target_ira->x_ira_reg_classes_intersect_p)
166#define ira_class_singleton \
167 (this_target_ira->x_ira_class_singleton)
168#define ira_no_alloc_regs \
169 (this_target_ira->x_ira_no_alloc_regs)
170#define ira_prohibited_class_mode_regs \
171 (this_target_ira->x_ira_prohibited_class_mode_regs)
172#define ira_exclude_class_mode_regs \
173 (this_target_ira->x_ira_exclude_class_mode_regs)
174
175/* Major structure describing equivalence info for a pseudo. */
177{
178 /* True if we can use this as a general equivalence. */
180 /* True if we can use this equivalence only for caller save/restore
181 location. */
183 /* True if the usage of the equivalence is profitable. */
185 /* Equiv. memory, constant, invariant, and initializing insns of
186 given pseudo-register or NULL_RTX. */
190 /* Always NULL_RTX if defined_p is false. */
192};
193
194/* The length of the following array. */
195extern int ira_reg_equiv_len;
196
197/* Info about equiv. info for each register. */
198extern struct ira_reg_equiv_s *ira_reg_equiv;
199
200extern void ira_init_once (void);
201extern void ira_init (void);
202extern void ira_setup_eliminable_regset (void);
203extern rtx ira_eliminate_regs (rtx, machine_mode);
204extern void ira_set_pseudo_classes (bool, FILE *);
205extern void ira_expand_reg_equiv (void);
206extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
207
208extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *);
209extern void ira_mark_allocation_change (int);
210extern void ira_mark_memory_move_deletion (int, int);
211extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
214extern void ira_mark_new_stack_slot (rtx, int, poly_uint64);
215extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx_insn *);
216extern bool ira_bad_reload_regno (int, rtx, rtx);
217
218extern void ira_adjust_equiv_reg_cost (unsigned, int);
219
220extern bool ira_former_scratch_p (int regno);
221extern bool ira_former_scratch_operand_p (rtx_insn *insn, int nop);
222extern void ira_register_new_scratch_op (rtx_insn *insn, int nop, int icode);
223extern bool ira_remove_insn_scratches (rtx_insn *insn, bool all_p, FILE *dump_file,
224 rtx (*get_reg) (rtx original));
225extern void ira_restore_scratches (FILE *dump_file);
226extern void ira_nullify_asm_goto (rtx_insn *insn);
227
228/* ira-costs.cc */
229extern void ira_costs_cc_finalize (void);
230
231/* ira-lives.cc */
233
234/* Spilling static chain pseudo may result in generation of wrong
235 non-local goto code using frame-pointer to address saved stack
236 pointer value after restoring old frame pointer value. The
237 function returns TRUE if REGNO is such a static chain pseudo. */
238inline bool
240{
241 return (cfun->static_chain_decl && crtl->has_nonlocal_goto
242 && REG_EXPR (regno_reg_rtx[regno]) == cfun->static_chain_decl);
243}
244
245#endif /* GCC_IRA_H */
class bitmap_head * bitmap
Definition coretypes.h:51
FILE * dump_file
Definition dumpfile.cc:64
rtx * regno_reg_rtx
Definition emit-rtl.cc:90
#define crtl
Definition emit-rtl.h:347
#define cfun
Definition function.h:478
HARD_REG_ELT_TYPE HARD_REG_SET
Definition hard-reg-set.h:47
rtx ira_eliminate_regs(rtx, machine_mode)
bool ira_use_lra_p
Definition ira.cc:5540
bool ira_bad_reload_regno(int, rtx, rtx)
Definition ira.cc:2348
rtx non_conflicting_reg_copy_p(rtx_insn *)
Definition ira-lives.cc:1195
void ira_update_equiv_info_by_shuffle_insn(int, int, rtx_insn *)
Definition ira.cc:2716
void ira_init(void)
Definition ira.cc:1716
void ira_mark_new_stack_slot(rtx, int, poly_uint64)
Definition ira-color.cc:5039
void ira_sort_regnos_for_alter_reg(int *, int, machine_mode *)
Definition ira-color.cc:4569
void ira_mark_memory_move_deletion(int, int)
Definition ira-color.cc:4735
void ira_costs_cc_finalize(void)
Definition ira-costs.cc:2741
void ira_nullify_asm_goto(rtx_insn *insn)
Definition ira.cc:5935
void ira_init_once(void)
Definition ira.cc:1669
void ira_register_new_scratch_op(rtx_insn *insn, int nop, int icode)
Definition ira.cc:5345
bool non_spilled_static_chain_regno_p(int regno)
Definition ira.h:239
#define this_target_ira
Definition ira.h:131
void ira_expand_reg_equiv(void)
Definition ira.cc:2989
bool ira_better_spill_reload_regno_p(int *, int *, rtx, rtx, rtx_insn *)
Definition ira-color.cc:5133
rtx ira_reuse_stack_slot(int, poly_uint64, poly_uint64)
Definition ira-color.cc:4919
bool ira_conflicts_p
Definition ira.cc:5544
bool ira_former_scratch_operand_p(rtx_insn *insn, int nop)
Definition ira.cc:5336
void ira_adjust_equiv_reg_cost(unsigned, int)
Definition ira-costs.cc:2731
bool ira_remove_insn_scratches(rtx_insn *insn, bool all_p, FILE *dump_file, rtx(*get_reg)(rtx original))
Definition ira.cc:5378
void ira_mark_allocation_change(int)
Definition ira-color.cc:4688
struct target_ira default_target_ira
Definition ira.cc:396
bool ira_former_scratch_p(int regno)
Definition ira.cc:5329
int ira_reg_equiv_len
Definition ira.cc:2982
void ira_set_pseudo_classes(bool, FILE *)
Definition ira-costs.cc:2609
struct ira_reg_equiv_s * ira_reg_equiv
Definition ira.cc:2985
void ira_restore_scratches(FILE *dump_file)
Definition ira.cc:5440
bool ira_reassign_pseudos(int *, int, HARD_REG_SET, HARD_REG_SET *, HARD_REG_SET *, bitmap)
Definition ira-color.cc:4834
void ira_setup_eliminable_regset(void)
Definition ira.cc:2384
#define REG_EXPR(RTX)
Definition rtl.h:2682
Definition ira.h:177
rtx invariant
Definition ira.h:189
bool caller_save_p
Definition ira.h:182
bool defined_p
Definition ira.h:179
rtx memory
Definition ira.h:187
rtx_insn_list * init_insns
Definition ira.h:191
rtx constant
Definition ira.h:188
bool profitable_p
Definition ira.h:184
Definition rtl.h:312
Definition rtl.h:480
Definition rtl.h:546
Definition ira.h:36
short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]
Definition ira.h:85
unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]
Definition ira.h:76
int x_ira_allocno_classes_num
Definition ira.h:44
enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES]
Definition ira.h:67
HARD_REG_SET x_ira_no_alloc_regs
Definition ira.h:114
short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE]
Definition ira.h:110
enum reg_class x_ira_stack_reg_pressure_class
Definition ira.h:71
int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES]
Definition ira.h:94
enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES]
Definition ira.h:53
HARD_REG_SET x_ira_exclude_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]
Definition ira.h:124
short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]
Definition ira.h:80
int x_ira_pressure_classes_num
Definition ira.h:57
enum reg_class x_ira_pressure_classes[N_REG_CLASSES]
Definition ira.h:61
enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES]
Definition ira.h:101
int x_ira_class_hard_regs_num[N_REG_CLASSES]
Definition ira.h:89
enum reg_class x_ira_allocno_classes[N_REG_CLASSES]
Definition ira.h:48
bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES]
Definition ira.h:106
enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER]
Definition ira.h:40
HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES]
Definition ira.h:119
unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]
Definition ira.h:77