#include "config.h"#include "system.h"#include "coretypes.h"#include "backend.h"#include "target.h"#include "rtl.h"#include "tree.h"#include "df.h"#include "memmodel.h"#include "tm_p.h"#include "insn-config.h"#include "regs.h"#include "ira.h"#include "ira-int.h"#include "diagnostic-core.h"#include "cfgrtl.h"#include "cfgbuild.h"#include "cfgcleanup.h"#include "expr.h"#include "tree-pass.h"#include "output.h"#include "reload.h"#include "cfgloop.h"#include "lra.h"#include "dce.h"#include "dbgcnt.h"#include "rtl-iter.h"#include "shrink-wrap.h"#include "print-rtl.h"
Data Structures | |
| struct | equivalence |
| struct | equiv_mem_data |
| struct | sloc |
Macros | |
| #define | last_mode_for_init_move_cost (this_target_ira_int->x_last_mode_for_init_move_cost) |
| #define | no_unit_alloc_regs (this_target_ira_int->x_no_unit_alloc_regs) |
| #define | alloc_reg_class_subclasses (this_target_ira_int->x_alloc_reg_class_subclasses) |
| #define | IRA_NO_OBSTACK |
| #define | ira_prohibited_mode_move_regs_initialized_p (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) |
Typedefs | |
| typedef struct sloc * | sloc_t |
Enumerations | |
| enum | valid_equiv { valid_none , valid_combine , valid_reload } |
Macro Definition Documentation
◆ alloc_reg_class_subclasses
| #define alloc_reg_class_subclasses (this_target_ira_int->x_alloc_reg_class_subclasses) |
Referenced by setup_class_translate_array(), setup_pressure_classes(), setup_reg_class_nregs(), and setup_reg_subclasses().
◆ IRA_NO_OBSTACK
| #define IRA_NO_OBSTACK |
Define the following macro if allocation through malloc if preferable.
◆ ira_prohibited_mode_move_regs_initialized_p
| #define ira_prohibited_mode_move_regs_initialized_p (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) |
Referenced by setup_prohibited_mode_move_regs().
◆ last_mode_for_init_move_cost
| #define last_mode_for_init_move_cost (this_target_ira_int->x_last_mode_for_init_move_cost) |
Referenced by target_ira_int::free_register_move_costs(), and ira_init_register_move_cost().
◆ no_unit_alloc_regs
| #define no_unit_alloc_regs (this_target_ira_int->x_no_unit_alloc_regs) |
Typedef Documentation
◆ sloc_t
Enumeration Type Documentation
◆ valid_equiv
Function Documentation
◆ add_store_equivs()
For insns that set a MEM to the contents of a REG that is only used in a single basic block, see if the register is always equivalent to that memory location and if moving the store from INSN to the insn that sets REG is safe. If so, put a REG_EQUIV note on the initializing insn.
References bitmap_bit_p, bitmap_set_bit, copy_rtx(), df_notes_rescan(), DF_REG_DEF_COUNT, dump_file, find_reg_note(), gen_rtx_INSN_LIST(), get_insns(), ggc_alloc(), ira_reg_equiv_s::init_insns, df_insn_info::insn, INSN_P, INSN_UID(), ira_reg_equiv, MEM_P, memref_used_between_p(), NEXT_INSN(), NULL, NULL_RTX, NUM_FIXED_BLOCKS, REG_BASIC_BLOCK, reg_equiv, REG_P, REGNO, SET_DEST, SET_SRC, set_unique_reg_note(), single_set(), valid_reload, and validate_equiv_mem().
Referenced by ira().
◆ adjust_cleared_regs()
In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the equivalent replacement.
References adjust_cleared_regs(), bitmap_bit_p, copy_rtx(), ggc_alloc(), NULL_RTX, reg_equiv, REG_P, REGNO, and simplify_replace_fn_rtx().
Referenced by adjust_cleared_regs(), and combine_and_move_insns().
◆ allocate_initial_values()
If the backend knows where to allocate pseudos for hard register initial values, register these allocations now.
References cfun, df_get_live_in(), df_get_live_out(), FOR_EACH_BB_FN, gcc_assert, gcc_checking_assert, ggc_alloc(), HARD_REGISTER_NUM_P, i, initial_value_entry(), MEM_P, reg_equiv_memory_loc, REG_N_SETS(), REG_P, reg_renumber, sloc::regno, REGNO, REGNO_REG_SET_P, SET_REGNO, SET_REGNO_REG_SET, and targetm.
Referenced by ira().
◆ build_insn_chain()
Walk the insns of the current function and build reload_insn_chain, and record register life information.
References BARRIER_P, BB_HEAD, bitmap_and_compl_into(), bitmap_bit_p, bitmap_clear(), bitmap_clear_bit(), bitmap_copy(), bitmap_empty_p(), bitmap_set_bit, BLOCK_FOR_INSN(), cfun, CLEAR_REG_SET, df_get_live_out(), DF_INSN_INFO_GET, DF_REF_CONDITIONAL, DF_REF_FLAGS_IS_SET, DF_REF_MAY_CLOBBER, DF_REF_PARTIAL, DF_REF_READ_WRITE, DF_REF_REG, DF_REF_REGNO, DF_REF_SIGN_EXTRACT, DF_REF_STRICT_LOW_PART, DF_REF_SUBREG, DF_REF_ZERO_EXTRACT, dump_file, eliminable_regset, EXECUTE_IF_SET_IN_BITMAP, fixed_regs, FOR_BB_INSNS_REVERSE, FOR_EACH_BB_REVERSE_FN, FOR_EACH_INSN_INFO_DEF, FOR_EACH_INSN_INFO_USE, free(), GET_CODE, get_subreg_tracking_sizes(), ggc_alloc(), i, basic_block_def::index, init_live_subregs(), df_insn_info::insn, ira_conflicts_p, last, max_regno, new_insn_chain(), NONDEBUG_INSN_P, NOTE_P, NULL, PREV_INSN(), print_insn_chains(), pseudo_for_reload_consideration_p(), reg_renumber, reload_insn_chain, sbitmap_free(), SBITMAP_SIZE, and TEST_HARD_REG_BIT.
Referenced by do_reload().
◆ calculate_allocation_cost()
Evaluate overall allocation cost and the costs for using hard registers and memory for allocnos.
References a, ALLOCNO_CLASS, ALLOCNO_CLASS_COST, ALLOCNO_HARD_REG_COSTS, ALLOCNO_HARD_REGNO, ALLOCNO_MEMORY_COST, ALLOCNO_MODE, FOR_EACH_ALLOCNO, ggc_alloc(), internal_flag_ira_verbose, ira_additional_jumps_num, ira_assert, ira_class_hard_reg_index, ira_dump_file, ira_hard_reg_in_set_p(), ira_load_cost, ira_mem_cost, ira_move_loops_num, ira_overall_cost, ira_reg_cost, ira_shuffle_cost, ira_store_cost, NULL, PRId64, and reg_class_contents.
Referenced by ira().
◆ clarify_prohibited_class_mode_regs()
Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers spanning from one register pressure class to another one. It is called after defining the pressure classes.
References add_to_hard_reg_set(), CLEAR_HARD_REG_SET, ggc_alloc(), hard_regno_nregs(), ira_class_hard_regs, ira_class_hard_regs_num, ira_pressure_class_translate, ira_prohibited_class_mode_regs, ira_useful_class_mode_regs, SET_HARD_REG_BIT, and TEST_HARD_REG_BIT.
Referenced by ira_init().
◆ combine_and_move_insns()
Scan all regs killed in an insn to see if any of them are registers only used that once. If so, see if we can replace the reference with the equivalent form. If we can, delete the initializing reference and this register will go away. If we can't replace the reference, and the initializing reference is within the same loop (or in an inner loop), then move the register initialization just before the use, so that they are in the same basic block.
References adjust_cleared_regs(), asm_noperands(), BB_HEAD, bb_loop_depth(), bitmap_and_compl_into(), bitmap_empty_p(), bitmap_set_bit, BLOCK_FOR_INSN(), can_throw_internal(), cfun, DEBUG_BIND_INSN_P, DEBUG_INSN_P, delete_insn(), df_insn_rescan(), df_live, DF_LIVE_IN, DF_LIVE_OUT, DF_LR_IN, DF_LR_OUT, DF_REF_INSN, DF_REF_INSN_INFO, DF_REF_NEXT_REG, DF_REF_REGNO, DF_REG_DEF_CHAIN, DF_REG_DEF_COUNT, DF_REG_USE_CHAIN, emit_insn_before(), find_reg_note(), FOR_EACH_BB_FN, FOR_EACH_INSN_USE, gcc_assert, gen_rtx_INSN_LIST(), GET_CODE, get_insns(), ggc_alloc(), HARD_REGISTER_NUM_P, equivalence::init_insns, ira_reg_equiv_s::init_insns, df_insn_info::insn, INSN_CODE, INSN_VAR_LOCATION_LOC, ira_reg_equiv, JUMP_P, max_reg_num(), MAY_HAVE_DEBUG_BIND_INSNS, multiple_sets(), NEXT_INSN(), no_equiv(), NULL, NULL_RTX, PATTERN(), prev_nondebug_insn(), REG_BASIC_BLOCK, reg_equiv, REG_FREQ, REG_N_CALLS_CROSSED, REG_NOTE_KIND, REG_NOTES, REG_P, regno_reg_rtx, remove_death(), equivalence::replace, SET_DEST, SET_REG_N_REFS, simplify_replace_fn_rtx(), single_set(), validate_replace_rtx(), and XEXP.
Referenced by ira().
◆ comp_reg_classes_func()
The function used to sort the important classes.
References allocno_class_order, ggc_alloc(), and ira_allocno_class_translate.
Referenced by reorder_important_classes().
◆ compute_regs_asm_clobbered()
Add register clobbers from asm statements.
References add_to_hard_reg_set(), asm_noperands(), cfun, crtl, DF_REF_REAL_REG, DF_REF_REGNO, FOR_BB_INSNS_REVERSE, FOR_EACH_BB_FN, FOR_EACH_INSN_DEF, GET_MODE, ggc_alloc(), HARD_REGISTER_NUM_P, NONDEBUG_INSN_P, and PATTERN().
Referenced by ira_setup_eliminable_regset().
◆ contains_X_constraint_p()
Return true if string STR contains constraint 'X'.
References ggc_alloc().
Referenced by ira_remove_insn_scratches().
◆ decrease_live_ranges_number()
Search forward to see if the source register of a copy insn dies before either it or the destination register is modified, but don't scan past the end of the basic block. If so, we can replace the source with the destination and let the source die in the copy insn. This will reduce the number of registers live in that range and may enable the destination and the source coalescing, thus often saving one register in addition to a register-register copy.
References asm_noperands(), BLOCK_FOR_INSN(), CALL_P, cfun, dead_or_set_p(), find_reg_fusage(), find_reg_note(), find_regno_note(), FOR_BB_INSNS, FOR_EACH_BB_FN, GET_CODE, GET_MODE, ggc_alloc(), INSN_P, ira_dump_file, NEXT_INSN(), next_real_insn(), NULL_RTX, PATTERN(), PUT_REG_NOTE_KIND, reg_mentioned_p(), REG_NOTES, reg_overlap_mentioned_p(), REG_P, reg_set_p(), REGNO, remove_note(), SET_DEST, SET_SRC, single_set(), targetm, validate_replace_rtx(), and XEXP.
Referenced by ira().
◆ def_dominates_uses()
Given register REGNO is set only once, return true if the defining insn dominates all uses.
References BLOCK_FOR_INSN(), CDI_DOMINATORS, DEBUG_INSN_P, DF_INSN_INFO_LUID, DF_REF_INSN, DF_REF_INSN_INFO, DF_REF_NEXT_REG, DF_REG_DEF_CHAIN, DF_REG_DEF_COUNT, DF_REG_USE_CHAIN, dominated_by_p(), gcc_assert, ggc_alloc(), and NULL.
Referenced by update_equiv_regs().
◆ do_reload()
References bitmap_obstack_release(), build_insn_chain(), CDI_DOMINATORS, cfun, cleanup_cfg(), CLEANUP_EXPENSIVE, crtl, current_function_decl, current_loops, DECL_SOURCE_LOCATION, df_analyze(), df_finish_pass(), df_live_add_problem(), df_live_set_all_dirty(), DF_NO_INSN_RESCAN, df_regs_ever_live_p(), df_scan_alloc(), df_scan_blocks(), df_set_flags(), dump_file, error_at(), finish_reg_equiv(), fixed_regs, FOR_ALL_BB_FN, frame_pointer_needed, free_dominance_info(), gen_rtx_REG(), GENERIC_STACK_CHECK, get_frame_size(), get_insns(), ggc_alloc(), global_regs, global_regs_decl, HARD_FRAME_POINTER_REGNUM, i, inform(), internal_flag_ira_verbose, INVALID_REGNUM, ira_bitmap_obstack, ira_conflicts_p, ira_destroy(), ira_dump_file, ira_finish_assign(), ira_free(), ira_overall_cost, ira_spilled_reg_stack_slots, ira_use_lra_p, basic_block_def::loop_father, loop_optimizer_finalize(), lra(), need_dce, NULL, overall_cost_before, pic_offset_table_rtx, PRId64, reg_equivs, REGNO, regstat_free_n_sets_and_refs(), regstat_free_ri(), reload(), run_fast_dce(), saved_flag_ira_share_spill_slots, timevar_pop(), timevar_push(), vec_free(), and warning().
◆ equiv_init_movable_p()
Returns true if X (used to initialize register REGNO) is movable. X is only movable if the registers it uses have equivalent initializations which appear to be within the same loop (or in an inner loop) and movable or if they are not candidates for local_alloc and don't vary.
References equiv_init_movable_p(), GET_CODE, GET_RTX_FORMAT, GET_RTX_LENGTH, ggc_alloc(), i, loop_depth(), MEM_VOLATILE_P, NUM_FIXED_BLOCKS, REG_BASIC_BLOCK, reg_equiv, REGNO, rtx_varies_p(), SET, SET_SRC, XEXP, XVECEXP, and XVECLEN.
Referenced by equiv_init_movable_p(), and update_equiv_regs().
◆ equiv_init_varies_p()
Returns false if X is known to be invariant.
References CASE_CONST_ANY, equiv_init_varies_p(), GET_CODE, GET_RTX_FORMAT, GET_RTX_LENGTH, ggc_alloc(), i, MEM_READONLY_P, MEM_VOLATILE_P, reg_equiv, REGNO, equivalence::replace, RTX_CODE, rtx_varies_p(), XEXP, XVECEXP, and XVECLEN.
Referenced by equiv_init_varies_p(), update_equiv_regs(), and validate_equiv_mem().
◆ expand_reg_info()
Regional allocation can create new pseudo-registers. This function expands some arrays for pseudo-registers.
References allocated_reg_info_size, ggc_alloc(), i, max_reg_num(), resize_reg_info(), setup_preferred_alternate_classes_for_new_pseudos(), and setup_reg_classes().
Referenced by find_moveable_pseudos(), and ira().
◆ find_moveable_pseudos()
Look for instances where we have an instruction that is known to increase register pressure, and whose result is not used immediately. If it is possible to move the instruction downwards to just before its first use, split its lifetime into two ranges. We create a new pseudo to compute the value, and emit a move instruction just before the first use. If, after register allocation, the new pseudo remains unallocated, the function move_unallocated_pseudos then deletes the move instruction and places the computation just before the first use. Such a move is safe and profitable if all the input registers remain live and unchanged between the original computation and its first use. In such a situation, the computation is known to increase register pressure, and moving it is known to at least not worsen it. We restrict moves to only those cases where a register remains unallocated, in order to avoid interfering too much with the instruction schedule. As an exception, we may move insns which only modify their input register (typically induction variables), as this increases the freedom for our intended transformation, and does not limit the second instruction scheduler pass.
References bitmap_and_into(), bitmap_bit_p, bitmap_clear(), bitmap_clear_bit(), bitmap_copy(), bitmap_initialize(), bitmap_set_bit, BLOCK_FOR_INSN(), calculate_dominance_info(), CDI_DOMINATORS, cfun, const0_rtx, control_flow_insn_p(), dbg_cnt(), DEBUG_INSN_P, df_analyze(), df_get_live_in(), df_get_live_out(), DF_INSN_INFO_GET, DF_REF_INSN, DF_REF_INSN_INFO, DF_REF_NEXT_REG, DF_REF_REAL_LOC, DF_REF_REG, DF_REF_REGNO, DF_REG_DEF_CHAIN, DF_REG_DEF_COUNT, DF_REG_EQ_USE_COUNT, DF_REG_USE_CHAIN, df_single_def(), df_single_use(), dump_file, emit_insn_after(), emit_insn_before(), EXECUTE_IF_SET_IN_BITMAP, expand_reg_info(), first_moveable_pseudo, fix_reg_equiv_init(), FLOAT_MODE_P, FOR_BB_INSNS, FOR_EACH_BB_FN, FOR_EACH_INSN_INFO_DEF, FOR_EACH_INSN_INFO_USE, FOR_EACH_INSN_USE, free(), free_dominance_info(), gcc_assert, gen_move_insn(), get_max_uid(), GET_MODE, ggc_alloc(), HARD_REGISTER_NUM_P, i, basic_block_def::index, df_insn_info::insn, insn_dominated_by_p(), INSN_UID(), INTEGRAL_MODE_P, ira_create_new_reg(), last_basic_block_for_fn, last_moveable_pseudo, max_reg_num(), max_uid, MEM_P, modified_between_p(), modified_in_p(), NEXT_INSN(), next_nonnote_nondebug_insn(), NONDEBUG_INSN_P, NULL, NULL_RTX, OP_IN, OPAQUE_MODE_P, PATTERN(), pseudo_replaced_reg, reg_equiv_init, REG_NOTE_KIND, REG_NOTES, REG_P, REGNO, regstat_compute_ri(), regstat_free_n_sets_and_refs(), regstat_free_ri(), regstat_init_n_sets_and_refs(), rtx_moveable_p(), set_insn_deleted(), single_set(), transp, validate_change(), and XEXP.
Referenced by ira().
◆ find_reg_classes()
Set up different arrays concerning class subsets, allocno and important classes.
References reorder_important_classes(), setup_allocno_and_important_classes(), setup_class_translate(), and setup_reg_class_relations().
Referenced by ira_init().
◆ finish_reg_equiv()
References free(), and ira_reg_equiv.
Referenced by do_reload().
◆ fix_reg_equiv_init()
Fix values of array REG_EQUIV_INIT after live range splitting done by IRA.
References gcc_unreachable, ggc_alloc(), grow_reg_equivs(), i, rtx_insn_list::insn(), ira_assert, max_reg_num(), max_regno, max_regno_before_ira, rtx_insn_list::next(), NULL, NULL_RTX, ORIGINAL_REGNO, reg_equiv_init, reg_equivs, REG_P, REGNO, SET_DEST, SET_SRC, single_set(), vec_safe_length(), and XEXP.
Referenced by find_moveable_pseudos(), and ira().
◆ get_scratch_reg()
Return new register of the same mode as ORIGINAL. Used in remove_scratches.
References gen_reg_rtx(), GET_MODE, and ggc_alloc().
Referenced by remove_scratches().
◆ get_subreg_tracking_sizes()
|
static |
Return true if we can track the individual bytes of subreg X. When returning true, set *OUTER_SIZE to the number of bytes in X itself, *INNER_SIZE to the number of bytes in the inner register and *START to the offset of the first byte.
References GET_MODE, GET_MODE_SIZE(), ggc_alloc(), REGNO, regno_reg_rtx, SUBREG_BYTE, and SUBREG_REG.
Referenced by build_insn_chain().
◆ indirect_jump_optimize()
A pass over indirect jumps, converting simple cases to direct jumps. Combine does this optimization too, but only within a basic block.
References BB_END, cfun, delete_unreachable_blocks(), DF_REF_INSN, DF_REF_IS_ARTIFICIAL, DF_REG_DEF_CHAIN, DF_REG_DEF_COUNT, find_reg_note(), FOR_EACH_BB_REVERSE_FN, GET_CODE, get_insns(), ggc_alloc(), df_insn_info::insn, JUMP_P, NULL_RTX, pc_set(), purge_all_dead_edges(), rebuild_jump_labels(), REG_P, REGNO, SET_SRC, single_set(), timevar_pop(), timevar_push(), validate_replace_rtx(), and XEXP.
Referenced by ira().
◆ init_live_subregs()
|
static |
Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for a register with SIZE bytes, making the register live if INIT_VALUE.
References bitmap_bit_p, bitmap_clear(), bitmap_ones(), bitmap_set_bit, gcc_assert, ggc_alloc(), NULL, and sbitmap_alloc().
Referenced by build_insn_chain().
◆ init_reg_equiv()
References ira_expand_reg_equiv(), ira_reg_equiv, ira_reg_equiv_len, and NULL.
Referenced by ira().
◆ insn_dominated_by_p()
A wrapper around dominated_by_p, which uses the information in UID_LUID to give dominance relationships between two insns I1 and I2.
References BLOCK_FOR_INSN(), CDI_DOMINATORS, dominated_by_p(), ggc_alloc(), i1, i2, and INSN_UID().
Referenced by find_moveable_pseudos().
◆ interesting_dest_for_shprep()
|
static |
If insn is interesting for parameter range-splitting shrink-wrapping preparation, i.e. it is a single set from a hard register to a pseudo, which is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a parallel statement with only one such statement, return the destination. Otherwise return NULL.
References GET_CODE, ggc_alloc(), i, df_insn_info::insn, INSN_P, interesting_dest_for_shprep_1(), NULL, PATTERN(), SET, side_effects_p(), XVECEXP, and XVECLEN.
Referenced by split_live_ranges_for_shrink_wrap().
◆ interesting_dest_for_shprep_1()
|
static |
If SET pattern SET is an assignment from a hard register to a pseudo which is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return the destination. Otherwise return NULL.
References bitmap_bit_p, df_get_live_in(), ggc_alloc(), HARD_REGISTER_P, NULL, REG_P, REGNO, SET_DEST, and SET_SRC.
Referenced by interesting_dest_for_shprep().
◆ ira()
This is the main entry of IRA.
References a, add_store_equivs(), allocate_initial_values(), allocated_reg_info_size, ALLOCNO_EMIT_DATA, ALLOCNO_REGNO, AVOID_CFG_MODIFICATIONS, BB_END, bitmap_obstack_initialize(), calculate_allocation_cost(), calculate_dominance_info(), CDI_DOMINATORS, cfun, df_d::changeable_flags, clear_bb_flags(), combine_and_move_insns(), commit_edge_insertions(), const1_rtx, crtl, current_loops, decrease_live_ranges_number(), delete_trivially_dead_insns(), df, df_analyze(), df_clear_flags(), df_live, DF_NO_INSN_RESCAN, df_note_add_problem(), DF_REG_DEF_COUNT, DF_REG_SIZE, DF_REG_USE_COUNT, df_remove_problem(), DF_VERIFY_SCHEDULED, EDGE_CRITICAL_P, emit_insn(), end(), end_alias_analysis(), end_sequence(), EXIT_BLOCK_PTR_FOR_FN, expand_reg_info(), extract_insn(), find_moveable_pseudos(), fix_reg_equiv_init(), FOR_EACH_ALLOCNO, FOR_EACH_BB_FN, FOR_EACH_EDGE, free(), free_dominance_info(), gcc_assert, gcc_checking_assert, gcc_obstack_init, generate_setjmp_warnings(), get_insns(), get_max_uid(), ggc_alloc(), grow_reg_equivs(), i, indirect_jump_optimize(), init_alias_analysis(), init_caller_save(), init_reg_equiv(), insert_insn_on_edge(), insns, internal_flag_ira_verbose, ira_additional_jumps_num, ira_allocate(), ira_assert, ira_bitmap_obstack, ira_build(), ira_color(), ira_conflicts_p, ira_dump_file, ira_emit(), ira_expand_reg_equiv(), ira_finish_emit_data(), ira_flattening(), ira_initiate_assign(), ira_initiate_emit_data(), ira_load_cost, ira_max_point, ira_mem_cost, ira_move_loops_num, ira_overall_cost, ira_reassign_conflict_allocnos(), ira_reg_cost, IRA_REGION_ALL, IRA_REGION_MIXED, IRA_REGION_ONE, ira_set_pseudo_classes(), ira_setup_eliminable_regset(), ira_shuffle_cost, ira_spilled_reg_stack_slots, ira_spilled_reg_stack_slots_num, ira_store_cost, ira_use_lra_p, JUMP_P, last_basic_block_for_fn, leaf_function_p(), loop_optimizer_finalize(), loop_optimizer_init(), LOOPS_HAVE_RECORDED_EXITS, lra_simple_p, max_reg_num(), max_regno, max_regno_before_ira, move_unallocated_pseudos(), recog_data_d::n_operands, NULL, OP_IN, recog_data_d::operand_type, overall_cost_before, recog_data, reg_allocno_class(), reg_alternate_class(), reg_equiv, reg_preferred_class(), REGNO, regstat_compute_ri(), regstat_free_n_sets_and_refs(), regstat_free_ri(), regstat_init_n_sets_and_refs(), remove_scratches(), resize_reg_info(), saved_flag_ira_share_spill_slots, setup_allocno_assignment_flags(), setup_prohibited_mode_move_regs(), setup_reg_classes(), setup_reg_equiv(), setup_reg_equiv_init(), setup_reg_renumber(), split_live_ranges_for_shrink_wrap(), start_sequence(), basic_block_def::succs, targetm, too_high_register_pressure_p(), update_equiv_regs(), and update_equiv_regs_prescan().
◆ ira_allocate()
Allocate memory of size LEN for IRA data.
References ggc_alloc().
Referenced by add_allocno_hard_regs(), add_to_conflicts(), allocate_conflict_bit_vec(), build_conflict_bit_table(), build_conflicts(), coalesce_spill_slots(), color_pass(), compress_conflict_vecs(), create_loop_tree_nodes(), create_move(), create_new_allocno(), create_new_allocno_hard_regs_node(), create_start_finish_chains(), fast_allocation(), find_costs_and_classes(), form_allocno_hard_regs_nodes_forest(), init_costs(), init_loop_tree_node(), initiate_allocnos(), initiate_cost_update(), initiate_regno_cost_classes(), ira(), ira_allocate_conflict_vec(), ira_costs(), ira_create_allocno_live_ranges(), ira_emit(), ira_flattening(), ira_initiate_assign(), ira_initiate_emit_data(), ira_sort_regnos_for_alter_reg(), mark_loops_for_removal(), modify_move_list(), rebuild_regno_allocno_maps(), remove_some_program_points_and_update_live_ranges(), remove_unnecessary_allocnos(), setup_cost_classes(), and setup_min_max_conflict_allocno_ids().
◆ ira_allocate_bitmap()
Allocate and returns bitmap for IRA.
References BITMAP_ALLOC, and ira_bitmap_obstack.
Referenced by add_ranges_and_copies(), do_coloring(), init_loop_tree_node(), ira_emit(), ira_initiate_assign(), ira_reassign_conflict_allocnos(), and ira_sort_regnos_for_alter_reg().
◆ ira_bad_reload_regno()
Return nonzero if REGNO is a particularly bad choice for reloading IN or OUT.
References ira_bad_reload_regno_1().
Referenced by allocate_reload_reg().
◆ ira_bad_reload_regno_1()
Return nonzero if REGNO is a particularly bad choice for reloading X.
References a, ALLOCNO_NUM_OBJECTS, ALLOCNO_OBJECT, GET_CODE, ggc_alloc(), i, ira_regno_allocno_map, OBJECT_TOTAL_CONFLICT_HARD_REGS, pref, reg_class_contents, reg_class_size, reg_preferred_class(), REGNO, and TEST_HARD_REG_BIT.
Referenced by ira_bad_reload_regno().
◆ ira_debug_allocno_classes()
Output all possible allocno and translation classes and the translation maps into stderr.
References ggc_alloc(), print_translated_classes(), and print_uniform_and_important_classes().
◆ ira_debug_disposition()
Outputs information about allocation of all allocnos into stderr.
References ggc_alloc(), and ira_print_disposition().
◆ ira_expand_reg_equiv()
Expand ira_reg_equiv if necessary.
References gcc_assert, ggc_alloc(), ira_reg_equiv, ira_reg_equiv_len, and max_reg_num().
Referenced by expand_reg_data(), init_reg_equiv(), ira(), ira_create_new_reg(), lra_copy_reg_equiv(), and lra_init_equiv().
◆ ira_former_scratch_operand_p()
Return true if the operand NOP of INSN is a former scratch.
References bitmap_bit_p, ggc_alloc(), sloc::insn, INSN_UID(), sloc::nop, and scratch_operand_bitmap.
◆ ira_former_scratch_p()
| bool ira_former_scratch_p | ( | int | regno | ) |
Return true if pseudo REGNO is made of SCRATCH.
References bitmap_bit_p, sloc::regno, and scratch_bitmap.
Referenced by curr_insn_transform(), ira_restore_scratches(), lra_need_for_scratch_reg_p(), lra_need_for_spills_p(), lra_spill(), process_alt_operands(), remove_pseudos(), spill_pseudos(), and update_scratch_ops().
◆ ira_free()
Free memory ADDR allocated for IRA data.
References free().
Referenced by add_to_conflicts(), build_conflicts(), coalesce_spill_slots(), color_pass(), compress_conflict_vecs(), do_reload(), fast_allocation(), find_costs_and_classes(), finish_allocno_hard_regs(), finish_allocno_hard_regs_nodes_forest(), finish_allocno_hard_regs_nodes_tree(), finish_allocnos(), finish_cost_update(), finish_costs(), finish_loop_tree_node(), finish_loop_tree_nodes(), finish_regno_cost_classes(), free_move(), ira_build_conflicts(), ira_costs(), ira_create_allocno_live_ranges(), ira_emit(), ira_finish_allocno_live_ranges(), ira_finish_assign(), ira_finish_emit_data(), ira_flattening(), ira_free_allocno_costs(), ira_rebuild_start_finish_chains(), ira_sort_regnos_for_alter_reg(), mark_loops_for_removal(), rebuild_regno_allocno_maps(), cost_classes_hasher::remove(), remove_some_program_points_and_update_live_ranges(), remove_unnecessary_allocnos(), remove_unused_allocno_hard_regs_nodes(), and setup_min_max_conflict_allocno_ids().
◆ ira_free_bitmap()
Free bitmap B allocated for IRA.
Referenced by add_ranges_and_copies(), do_coloring(), finish_loop_tree_node(), finish_loop_tree_nodes(), ira_emit(), ira_finish_assign(), ira_reassign_conflict_allocnos(), and ira_sort_regnos_for_alter_reg().
◆ ira_get_dup_out_num()
| int ira_get_dup_out_num | ( | int | op_num, |
| alternative_mask | alts, | ||
| bool & | single_input_op_has_cstr_p ) |
Return the number of the output non-early clobber operand which should be the same in any case as operand with number OP_NUM (or negative value if there is no such operand). ALTS is the mask of alternatives that we should consider. SINGLE_INPUT_OP_HAS_CSTR_P should be set in this function, it indicates whether there is only a single input operand which has the matching constraint on the output operand at the position specified in return value. If the pattern allows any one of several input operands holds the matching constraint, it's set as false, one typical case is destructive FMA instruction on target rs6000. Note that for a non-NO_REG preferred register class with no free register move copy, if the parameter PARAM_IRA_CONSIDER_DUP_IN_ALL_ALTS is set to one, this function will check all available alternatives for matching constraints, even if it has found or will find one alternative with non-NO_REG regclass, it can respect more cases with matching constraints. If PARAM_IRA_CONSIDER_DUP_IN_ALL_ALTS is set to zero, SINGLE_INPUT_OP_HAS_CSTR_P is always true, it will stop to find matching constraint relationship once it hits some alternative with some non-NO_REG regclass.
References ALTERNATIVE_BIT, recog_data_d::constraints, end(), gcc_assert, GET_MODE, ggc_alloc(), ira_init_register_move_cost_if_necessary(), ira_may_move_in_cost, ira_reg_class_intersect, ira_register_move_cost, recog_data_d::n_alternatives, recog_data_d::n_operands, OP_IN, OP_OUT, recog_data_d::operand, recog_data_d::operand_type, recog_data, recog_op_alt, reg_or_subregno(), reg_preferred_class(), targetm, and TEST_BIT.
Referenced by add_insn_allocno_copies().
◆ ira_init()
This is called every time when register related information is changed.
References clarify_prohibited_class_mode_regs(), find_reg_classes(), ggc_alloc(), ira_init_costs(), setup_alloc_regs(), setup_class_subset_and_memory_move_costs(), setup_hard_regno_aclass(), setup_prohibited_and_exclude_class_mode_regs(), setup_reg_class_nregs(), setup_reg_mode_hard_regset(), and this_target_ira_int.
Referenced by backend_init_target(), and reinit_regs().
◆ ira_init_once()
This is called once during compiler work. It sets up different arrays whose values don't depend on the compiled function.
References ira_init_costs_once(), ira_use_lra_p, lra_init_once(), and targetm.
Referenced by initialize_rtl().
◆ ira_init_register_move_cost()
| void ira_init_register_move_cost | ( | machine_mode | mode | ) |
Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST and IRA_MAY_MOVE_OUT_COST for MODE.
References CLEAR_HARD_REG_SET, ggc_alloc(), hard_reg_set_intersect_p(), i, ira_assert, ira_class_hard_regs_num, ira_class_subset_p, ira_may_move_in_cost, ira_may_move_out_cost, ira_memory_move_cost, ira_reg_class_max_nregs, ira_register_move_cost, last_mode_for_init_move_cost, MAX, NULL, reg_class_contents, reg_class_subclasses, register_move_cost(), SET_HARD_REG_BIT, and targetm.
Referenced by ira_init_register_move_cost_if_necessary().
◆ ira_nullify_asm_goto()
Modify asm goto to avoid further trouble with this insn. We can not replace the insn by USE as in other asm insns as we still need to keep CFG consistency.
References ASM_OPERANDS_LABEL_VEC, ASM_OPERANDS_SOURCE_LOCATION, extract_asm_operands(), ggc_alloc(), ggc_strdup, INSN_CODE, ira_assert, JUMP_P, PATTERN(), and rtvec_alloc().
Referenced by curr_insn_transform(), find_reloads(), and lra_asm_insn_error().
◆ ira_print_disposition()
Output information about allocation of all allocnos (except for caps) into file F.
References a, ALLOCNO_HARD_REGNO, ALLOCNO_LOOP_TREE_NODE, ALLOCNO_NEXT_REGNO_ALLOCNO, ALLOCNO_NUM, ALLOCNO_REGNO, ggc_alloc(), i, basic_block_def::index, ira_regno_allocno_map, max_reg_num(), max_regno, and NULL.
Referenced by do_coloring(), fast_allocation(), and ira_debug_disposition().
◆ ira_register_new_scratch_op()
Register operand NOP in INSN as a former scratch. It will be changed to scratch back, if it is necessary, at the LRA end.
References add_reg_note(), bitmap_set_bit, ggc_alloc(), sloc::icode, sloc::insn, INSN_UID(), ira_assert, sloc::nop, recog_data_d::operand_loc, recog_data, REG_P, sloc::regno, REGNO, scratch_bitmap, scratch_operand_bitmap, and scratches.
Referenced by ira_remove_insn_scratches(), and update_scratch_ops().
◆ ira_remove_insn_scratches()
| bool ira_remove_insn_scratches | ( | rtx_insn * | insn, |
| bool | all_p, | ||
| FILE * | dump_file, | ||
| rtx(*)(rtx original) | get_reg ) |
Change INSN's scratches into pseudos and save their location. Return true if we changed any scratch.
References recog_data_d::constraints, contains_X_constraint_p(), dump_file, extract_insn(), GET_CODE, GET_MODE, ggc_alloc(), i, sloc::insn, INSN_CODE, INSN_UID(), ira_dump_file, ira_register_new_scratch_op(), recog_data_d::n_operands, NULL, recog_data_d::operand_loc, recog_data, and REGNO.
Referenced by remove_insn_scratches(), and remove_scratches().
◆ ira_restore_scratches()
Changes pseudos created by function remove_scratches onto scratches.
References bitmap_clear(), dump_file, recog_data_d::dup_loc, recog_data_d::dup_num, extract_insn(), free(), GET_MODE, ggc_alloc(), i, sloc::icode, sloc::insn, INSN_CODE, INSN_UID(), ira_assert, ira_former_scratch_p(), recog_data_d::n_dups, sloc::nop, NOTE_KIND, NOTE_P, NULL, recog_data_d::operand_loc, recog_data, REG_P, reg_renumber, sloc::regno, REGNO, scratch_bitmap, scratch_operand_bitmap, and scratches.
Referenced by lra().
◆ ira_setup_alts()
| alternative_mask ira_setup_alts | ( | rtx_insn * | insn | ) |
Extract INSN and return the set of alternatives that we should consider. This excludes any alternatives whose constraints are obviously impossible to meet (e.g. because the constraint requires a constant and the operand is nonconstant). It also excludes alternatives that are bound to need a spill or reload, as long as we have other alternatives that match exactly.
References ALTERNATIVE_BIT, CHAR_BIT, CONST_INT_P, recog_data_d::constraints, curr_swapped, end(), extract_insn(), extract_mem_from_operand(), get_preferred_alternatives(), ggc_alloc(), INTVAL, ira_assert, MAX, MEM_P, recog_data_d::n_alternatives, recog_data_d::n_operands, NULL, recog_data_d::operand, preprocess_constraints(), recog_data, recog_op_alt, REG_P, rtx_equal_p(), SUBREG_P, and TEST_BIT.
Referenced by add_insn_allocno_copies(), and process_bb_node_lives().
◆ ira_setup_eliminable_regset()
Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE.
References cfun, CLEAR_HARD_REG_SET, compute_regs_asm_clobbered(), crtl, df_set_regs_ever_live(), eliminable_regset, error(), EXIT_IGNORE_STACK, frame_pointer_needed, ggc_alloc(), global_regs, HARD_FRAME_POINTER_IS_FRAME_POINTER, HARD_FRAME_POINTER_REGNUM, hard_regno_nregs(), i, ira_no_alloc_regs, leaf_function_p(), no_unit_alloc_regs, reg_names, SET_HARD_REG_BIT, SUPPORTS_STACK_ALIGNMENT, targetm, and TEST_HARD_REG_BIT.
Referenced by calculate_bb_reg_pressure(), calculate_loop_reg_pressure(), and ira().
◆ ira_update_equiv_info_by_shuffle_insn()
Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS are insns which were generated for such movement. It is assumed that FROM_REGNO and TO_REGNO always have the same value at the point of any move containing such registers. This function is used to update equiv info for register shuffles on the region borders and for caller save/restore insns.
References ira_reg_equiv_s::caller_save_p, ira_reg_equiv_s::constant, copy_rtx(), ira_reg_equiv_s::defined_p, dump_value_slim(), find_reg_note(), gcc_assert, gen_rtx_INSN_LIST(), ggc_alloc(), ira_reg_equiv_s::init_insns, INSN_UID(), insns, internal_flag_ira_verbose, ira_reg_equiv_s::invariant, ira_assert, ira_dump_file, ira_reg_equiv, MEM_READONLY_P, ira_reg_equiv_s::memory, NEXT_INSN(), NULL, NULL_RTX, rtx_equal_p(), and set_unique_reg_note().
Referenced by emit_move_list().
◆ make_pass_ira()
| rtl_opt_pass * make_pass_ira | ( | gcc::context * | ctxt | ) |
References ggc_alloc().
◆ make_pass_reload()
| rtl_opt_pass * make_pass_reload | ( | gcc::context * | ctxt | ) |
References ggc_alloc().
◆ mark_elimination()
| void mark_elimination | ( | int | from, |
| int | to ) |
Indicate that hard register number FROM was eliminated and replaced with an offset from hard register number TO. The status of hard registers live at the start of a basic block is updated by replacing a use of FROM with a use of TO.
References bitmap_bit_p, bitmap_clear_bit(), bitmap_set_bit, cfun, df_live, DF_LIVE_IN, DF_LR_IN, FOR_EACH_BB_FN, and r.
Referenced by reload().
◆ memref_referenced_p()
TRUE if X references a memory location (as a read if READ_P) that would be affected by a store to MEMREF.
References CASE_CONST_ANY, GET_CODE, GET_RTX_FORMAT, GET_RTX_LENGTH, ggc_alloc(), i, memref_referenced_p(), process_set_for_memref_referenced_p(), reg_equiv, REGNO, SET, SET_DEST, SET_SRC, true_dependence(), XEXP, XVECEXP, and XVECLEN.
Referenced by memref_referenced_p(), memref_used_between_p(), and process_set_for_memref_referenced_p().
◆ memref_used_between_p()
TRUE if some insn in the range (START, END] references a memory location that would be affected by a store to MEMREF. Callers should not call this routine if START is after END in the RTL chain.
References CALL_P, end(), gcc_assert, ggc_alloc(), memref_referenced_p(), NEXT_INSN(), NONDEBUG_INSN_P, PATTERN(), and RTL_CONST_CALL_P.
Referenced by add_store_equivs().
◆ move_unallocated_pseudos()
Perform the second half of the transformation started in find_moveable_pseudos. We look for instances where the newly introduced pseudo remains unallocated, and remove it by moving the definition to just before its use, replacing the move instruction generated by find_moveable_pseudos.
References delete_insn(), DF_REF_INSN, DF_REG_DEF_CHAIN, dump_file, emit_insn_after(), first_moveable_pseudo, gcc_assert, ggc_alloc(), i, INSN_UID(), last_moveable_pseudo, PATTERN(), pseudo_replaced_reg, reg_renumber, REGNO, SET_DEST, SET_REG_N_REFS, single_set(), and validate_change().
Referenced by ira().
◆ no_equiv()
Mark REG as having no known equivalence. Some instructions might have been processed before and furnished with REG_EQUIV notes for this register; these notes will have to be removed. STORE is the piece of RTL that does the non-constant / conflicting assignment - a SET, CLOBBER or REG_INC note. It is currently not used, but needs to be there because this function is called from note_stores.
References ira_reg_equiv_s::caller_save_p, ira_reg_equiv_s::defined_p, find_reg_note(), gen_rtx_INSN_LIST(), ggc_alloc(), equivalence::init_insns, ira_reg_equiv_s::init_insns, rtx_insn_list::insn(), ira_reg_equiv, rtx_insn_list::next(), equivalence::no_equiv, NULL, NULL_RTX, reg_equiv, REG_P, REGNO, remove_note(), and equivalence::replacement.
Referenced by combine_and_move_insns(), and update_equiv_regs().
◆ print_insn_chain()
|
static |
Print chain C to FILE.
References bitmap_print(), ggc_alloc(), and INSN_UID().
Referenced by print_insn_chains().
◆ print_insn_chains()
Print all reload_insn_chains to FILE.
References ggc_alloc(), print_insn_chain(), and reload_insn_chain.
Referenced by build_insn_chain().
◆ print_translated_classes()
Output all possible allocno or pressure classes and their translation map into file F.
References ggc_alloc(), i, ira_allocno_class_translate, ira_allocno_classes, ira_allocno_classes_num, ira_pressure_class_translate, ira_pressure_classes, ira_pressure_classes_num, and reg_class_names.
Referenced by ira_debug_allocno_classes().
◆ print_uniform_and_important_classes()
Output all uniform and important classes into file F.
References ggc_alloc(), i, ira_important_classes, ira_important_classes_num, ira_uniform_class_p, and reg_class_names.
Referenced by ira_debug_allocno_classes().
◆ process_set_for_memref_referenced_p()
Auxiliary function for memref_referenced_p. Process setting X for MEMREF store.
References ggc_alloc(), MEM_P, memref_referenced_p(), and XEXP.
Referenced by memref_referenced_p().
◆ pseudo_for_reload_consideration_p()
Return true if pseudo REGNO should be added to set live_throughout or dead_or_set of the insn chains for reload consideration.
References ira_conflicts_p, and reg_renumber.
Referenced by build_insn_chain().
◆ remove_scratches()
Change scratches into pseudos and save their location. Return true if we changed any scratch.
References bitmap_initialize(), cfun, df_insn_rescan(), FOR_BB_INSNS, FOR_EACH_BB_FN, get_max_uid(), get_scratch_reg(), ggc_alloc(), sloc::insn, INSN_P, ira_dump_file, ira_remove_insn_scratches(), reg_obstack, scratch_bitmap, scratch_operand_bitmap, and scratches.
Referenced by ira().
◆ reorder_important_classes()
For correct work of function setup_reg_class_relation we need to reorder important classes according to the order of their allocno classes. It places important classes containing the same allocatable hard register set adjacent to each other and allocno class with the allocatable hard register set right after the other important classes with the same set. In example from comments of function setup_allocno_and_important_classes, it places LEGACY_REGS and GENERAL_REGS close to each other and GENERAL_REGS is after LEGACY_REGS.
References allocno_class_order, comp_reg_classes_func(), ggc_alloc(), i, ira_allocno_classes, ira_allocno_classes_num, ira_important_class_nums, ira_important_classes, ira_important_classes_num, and qsort.
Referenced by find_reg_classes().
◆ rtx_moveable_p()
Examine the rtx found in *LOC, which is read or written to as determined by TYPE. Return false if we find a reason why an insn containing this rtx should not be moved (such as accesses to non-constant memory), true otherwise.
References CASE_CONST_ANY, frame_pointer_rtx, GET_CODE, GET_RTX_FORMAT, GET_RTX_LENGTH, ggc_alloc(), HARD_REGISTER_P, i, MEM_READONLY_P, MEM_VOLATILE_P, OP_IN, OP_OUT, rtx_moveable_p(), SET, SET_DEST, SET_SRC, XEXP, XVECEXP, and XVECLEN.
Referenced by find_moveable_pseudos(), and rtx_moveable_p().
◆ set_paradoxical_subreg()
Check whether the SUBREG is a paradoxical subreg and set the result in PDX_SUBREGS.
References FOR_EACH_SUBRTX, GET_CODE, ggc_alloc(), paradoxical_subreg_p(), PATTERN(), equivalence::pdx_subregs, reg_equiv, REG_P, REGNO, and SUBREG_REG.
Referenced by update_equiv_regs_prescan().
◆ setup_alloc_regs()
Set up global variables defining info about hard registers for the allocation. These depend on USE_HARD_FRAME_P whose TRUE value means that we can use the hard frame pointer for the allocation.
References add_to_hard_reg_set(), fixed_nonglobal_reg_set, ggc_alloc(), HARD_FRAME_POINTER_REGNUM, no_unit_alloc_regs, and setup_class_hard_regs().
Referenced by ira_init().
◆ setup_allocno_and_important_classes()
Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. Target may have many subtargets and not all target hard registers can be used for allocation, e.g. x86 port in 32-bit mode cannot use hard registers introduced in x86-64 like r8-r15). Some classes might have the same allocatable hard registers, e.g. INDEX_REGS and GENERAL_REGS in x86 port in 32-bit mode. To decrease different calculations efforts we introduce allocno classes which contain unique non-empty sets of allocatable hard-registers. Pseudo class cost calculation in ira-costs.cc is very expensive. Therefore we are trying to decrease number of classes involved in such calculation. Register classes used in the cost calculation are called important classes. They are allocno classes and other non-empty classes whose allocatable hard register sets are inside of an allocno class hard register set. From the first sight, it looks like that they are just allocno classes. It is not true. In example of x86-port in 32-bit mode, allocno classes will contain GENERAL_REGS but not LEGACY_REGS (because allocatable hard registers are the same for the both classes). The important classes will contain GENERAL_REGS and LEGACY_REGS. It is done because a machine description insn constraint may refers for LEGACY_REGS and code in ira-costs.cc is mostly base on investigation of the insn constraints.
References ggc_alloc(), hard_reg_set_subset_p(), i, ira_allocno_classes, ira_allocno_classes_num, ira_class_hard_regs_num, ira_important_classes, ira_important_classes_num, ira_reg_allocno_class_p, ira_reg_pressure_class_p, reg_class_contents, setup_pressure_classes(), setup_uniform_class_p(), targetm, and temp_hard_regset.
Referenced by find_reg_classes().
◆ setup_allocno_assignment_flags()
Set up allocno assignment flags for further allocation improvements.
References a, ALLOCNO_ASSIGNED_P, ALLOCNO_CLASS, ALLOCNO_CLASS_COST, ALLOCNO_EMIT_DATA, ALLOCNO_HARD_REGNO, ALLOCNO_MEMORY_COST, ALLOCNO_MODE, FOR_EACH_ALLOCNO, ggc_alloc(), ira_assert, ira_free_allocno_updated_costs(), ira_hard_reg_in_set_p(), and reg_class_contents.
Referenced by ira().
◆ setup_class_hard_regs()
The function sets up the three arrays declared above.
References CLEAR_HARD_REG_SET, ggc_alloc(), i, ira_assert, ira_class_hard_reg_index, ira_class_hard_regs, ira_class_hard_regs_num, ira_non_ordered_class_hard_regs, reg_alloc_order, reg_class_contents, SET_HARD_REG_BIT, SHRT_MAX, temp_hard_regset, and TEST_HARD_REG_BIT.
Referenced by setup_alloc_regs().
◆ setup_class_subset_and_memory_move_costs()
Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST.
References ggc_alloc(), hard_reg_set_empty_p(), hard_reg_set_subset_p(), ira_class_hard_regs, ira_class_subset_p, ira_max_memory_move_cost, ira_memory_move_cost, memory_move_cost(), reg_class_contents, setup_reg_subclasses(), SHRT_MAX, targetm, and temp_hard_regset.
Referenced by ira_init().
◆ setup_class_translate()
Set up array IRA_ALLOCNO_CLASS_TRANSLATE and IRA_PRESSURE_CLASS_TRANSLATE.
References ira_allocno_class_translate, ira_allocno_classes, ira_allocno_classes_num, ira_pressure_class_translate, ira_pressure_classes, ira_pressure_classes_num, and setup_class_translate_array().
Referenced by find_reg_classes().
◆ setup_class_translate_array()
|
static |
Setup translation in CLASS_TRANSLATE of all classes into a class given by array CLASSES of length CLASSES_NUM. The function is used make translation any reg class to an allocno class or to an pressure class. This translation is necessary for some calculations when we can use only allocno or pressure classes and such translation represents an approximate representation of all classes. The translation in case when allocatable hard register set of a given class is subset of allocatable hard register set of a class in CLASSES is pretty simple. We use smallest classes from CLASSES containing a given class. If allocatable hard register set of a given class is not a subset of any corresponding set of a class from CLASSES, we use the cheapest (with load/store point of view) class from CLASSES whose set intersects with given class set.
References alloc_reg_class_subclasses, ggc_alloc(), hard_reg_set_empty_p(), i, INT_MAX, ira_memory_move_cost, reg_class_contents, and temp_hard_regset.
Referenced by setup_class_translate().
◆ setup_hard_regno_aclass()
Set up the array above.
References ggc_alloc(), i, ira_allocno_class_translate, ira_allocno_classes, ira_allocno_classes_num, ira_class_hard_reg_index, ira_hard_regno_allocno_class, no_unit_alloc_regs, and TEST_HARD_REG_BIT.
Referenced by ira_init().
◆ setup_preferred_alternate_classes_for_new_pseudos()
Setup preferred and alternative classes for new pseudo-registers created by IRA starting with START.
References ggc_alloc(), i, internal_flag_ira_verbose, ira_assert, ira_dump_file, max_reg_num(), max_regno, NULL, ORIGINAL_REGNO, reg_allocno_class(), reg_alternate_class(), reg_class_names, reg_preferred_class(), regno_reg_rtx, and setup_reg_classes().
Referenced by expand_reg_info().
◆ setup_pressure_classes()
Find pressure classes which are register classes for which we calculate register pressure in IRA, register pressure sensitive insn scheduling, and register pressure sensitive loop invariant motion. To make register pressure calculation easy, we always use non-intersected register pressure classes. A move of hard registers from one register pressure class is not more expensive than load and store of the hard registers. Most likely an allocno class will be a subset of a register pressure class and in many cases a register pressure class. That makes usage of register pressure classes a good approximation to find a high register pressure.
References alloc_reg_class_subclasses, CLEAR_HARD_REG_SET, contains_reg_of_mode, ggc_alloc(), hard_reg_set_empty_p(), hard_reg_set_subset_p(), i, ira_assert, ira_class_hard_regs_num, ira_init_register_move_cost_if_necessary(), ira_max_memory_move_cost, ira_pressure_classes, ira_pressure_classes_num, ira_prohibited_class_mode_regs, ira_reg_pressure_class_p, ira_register_move_cost, no_unit_alloc_regs, reg_class_contents, SET_HARD_REG_BIT, setup_stack_reg_pressure_class(), targetm, and temp_hard_regset.
Referenced by setup_allocno_and_important_classes().
◆ setup_prohibited_and_exclude_class_mode_regs()
Set up IRA_PROHIBITED_CLASS_MODE_REGS, IRA_EXCLUDE_CLASS_MODE_REGS, and IRA_CLASS_SINGLETON. This function is called once IRA_CLASS_HARD_REGS has been initialized.
References CLEAR_HARD_REG_SET, count, ggc_alloc(), in_hard_reg_set_p(), ira_class_hard_regs, ira_class_hard_regs_num, ira_class_singleton, ira_exclude_class_mode_regs, ira_prohibited_class_mode_regs, reg_class_contents, SET_HARD_REG_BIT, targetm, and temp_hard_regset.
Referenced by ira_init().
◆ setup_prohibited_mode_move_regs()
Set up IRA_PROHIBITED_MODE_MOVE_REGS.
References CLEAR_HARD_REG_BIT, constrain_operands(), extract_insn(), gen_rtx_INSN(), gen_rtx_REG(), get_enabled_alternatives(), ggc_alloc(), i, INSN_CODE, ira_prohibited_mode_move_regs, ira_prohibited_mode_move_regs_initialized_p, LAST_VIRTUAL_REGISTER, recog_memoized(), SET_HARD_REG_SET, set_mode_and_regno(), targetm, and word_mode.
Referenced by ira().
◆ setup_reg_class_nregs()
Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps.
References alloc_reg_class_subclasses, ggc_alloc(), i, ira_reg_class_max_nregs, ira_reg_class_min_nregs, and targetm.
Referenced by ira_init().
◆ setup_reg_class_relations()
Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, please see corresponding comments in ira-int.h.
References ggc_alloc(), hard_reg_set_empty_p(), hard_reg_set_intersect_p(), hard_reg_set_subset_p(), i, ira_important_classes, ira_important_classes_num, ira_reg_class_intersect, ira_reg_class_subset, ira_reg_class_subunion, ira_reg_class_super_classes, ira_reg_class_superunion, ira_reg_classes_intersect_p, no_unit_alloc_regs, reg_class_contents, reg_class_subclasses, reg_class_subset_p(), reg_class_subunion, reg_class_superunion, and temp_hard_regset.
Referenced by find_reg_classes().
◆ setup_reg_equiv()
Set up fields memory, constant, and invariant from init_insns in the structures of array ira_reg_equiv.
References arg_pointer_rtx, ira_reg_equiv_s::caller_save_p, ira_reg_equiv_s::constant, CONSTANT_P, ira_reg_equiv_s::defined_p, find_reg_note(), force_const_mem(), frame_pointer_rtx, function_invariant_p(), gcc_assert, GET_CODE, GET_MODE, ggc_alloc(), i, ira_reg_equiv_s::init_insns, df_insn_info::insn, rtx_insn_list::insn(), ira_reg_equiv_s::invariant, ira_reg_equiv, ira_reg_equiv_len, LEGITIMATE_PIC_OPERAND_P, MEM_P, ira_reg_equiv_s::memory, memory_operand(), rtx_insn_list::next(), NULL, NULL_RTX, REG_P, REGNO, rtx_equal_p(), SET_DEST, SET_SRC, single_set(), targetm, and XEXP.
Referenced by ira().
◆ setup_reg_equiv_init()
Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should be already calculated.
References i, ira_reg_equiv_s::init_insns, ira_reg_equiv, max_reg_num(), max_regno, and reg_equiv_init.
Referenced by ira().
◆ setup_reg_mode_hard_regset()
The function sets up the map IRA_REG_MODE_HARD_REGSET.
References CLEAR_HARD_REG_SET, ggc_alloc(), hard_regno_nregs(), i, ira_reg_mode_hard_regset, and SET_HARD_REG_BIT.
Referenced by ira_init().
◆ setup_reg_renumber()
Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from the allocation found by IRA.
References a, ALLOCNO_ASSIGNED_P, ALLOCNO_CALLS_CROSSED_NUM, ALLOCNO_CAP_MEMBER, ALLOCNO_CHEAP_CALLS_CROSSED_NUM, ALLOCNO_HARD_REGNO, ALLOCNO_NUM_OBJECTS, ALLOCNO_OBJECT, ALLOCNO_REGNO, caller_save_needed, FOR_EACH_ALLOCNO, ggc_alloc(), i, ira_assert, ira_equiv_no_lvalue_p(), ira_free_allocno_updated_costs(), ira_need_caller_save_p(), ira_pressure_class_translate, ira_reg_equiv_len, ira_use_lra_p, NULL, OBJECT_TOTAL_CONFLICT_HARD_REGS, and reg_renumber.
Referenced by ira().
◆ setup_reg_subclasses()
Initialize the table of subclasses of each reg class.
References alloc_reg_class_subclasses, ggc_alloc(), hard_reg_set_empty_p(), hard_reg_set_subset_p(), i, reg_class_contents, and temp_hard_regset.
Referenced by setup_class_subset_and_memory_move_costs().
◆ setup_stack_reg_pressure_class()
Set up ira_stack_reg_pressure_class which is the biggest pressure register class containing stack registers or NO_REGS if there are no stack registers. To find this class, we iterate through all register pressure classes and choose the first register pressure class containing all the stack registers and having the biggest size.
References CLEAR_HARD_REG_SET, ggc_alloc(), hard_reg_set_size(), i, ira_pressure_classes, ira_pressure_classes_num, ira_stack_reg_pressure_class, reg_class_contents, SET_HARD_REG_BIT, and temp_hard_regset.
Referenced by setup_pressure_classes().
◆ setup_uniform_class_p()
Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class whose register move cost between any registers of the class is the same as for all its subclasses. We use the data to speed up the 2nd pass of calculations of allocno costs.
References contains_reg_of_mode, ggc_alloc(), i, ira_class_hard_regs_num, ira_init_register_move_cost_if_necessary(), ira_register_move_cost, ira_uniform_class_p, and reg_class_subclasses.
Referenced by setup_allocno_and_important_classes().
◆ split_live_ranges_for_shrink_wrap()
Split live ranges of pseudos that are loaded from hard registers in the first BB in a BB that dominates all non-sibling call if such a BB can be found and is not in a loop. Return true if the function has made any changes.
References apply_change_group(), AVOID_CFG_MODIFICATIONS, bb_loop_depth(), bb_note(), bitmap_bit_p, bitmap_set_bit, BLOCK_FOR_INSN(), calculate_dominance_info(), CALL_P, CDI_DOMINATORS, CDI_POST_DOMINATORS, cfun, DEBUG_INSN_P, DF_REF_BB, DF_REF_INSN, DF_REF_NEXT_REG, DF_REF_REAL_LOC, DF_REG_DEF_COUNT, DF_REG_USE_CHAIN, dominated_by_p(), dump_file, emit_insn_after(), ENTRY_BLOCK_PTR_FOR_FN, EXIT_BLOCK_PTR_FOR_FN, FOR_BB_INSNS, FOR_EACH_BB_FN, FOR_EACH_EDGE, free_dominance_info(), gen_move_insn(), get_immediate_dominator(), ggc_alloc(), basic_block_def::index, df_insn_info::insn, interesting_dest_for_shprep(), ira_create_new_reg(), loop_optimizer_finalize(), loop_optimizer_init(), n_basic_blocks_for_fn, nearest_common_dominator_for_set(), NULL, pic_offset_table_rtx, print_rtl_single(), queue, REGNO, SHRINK_WRAPPING_ENABLED, SIBLING_CALL_P, single_succ(), basic_block_def::succs, and validate_change().
Referenced by ira().
◆ too_high_register_pressure_p()
Return TRUE if there is too high register pressure in the function. It is used to decide when stack slot sharing is worth to do.
References ggc_alloc(), i, ira_loop_tree_root, ira_pressure_classes, ira_pressure_classes_num, and ira_loop_tree_node::reg_pressure.
Referenced by ira().
◆ update_equiv_regs()
Find registers that are equivalent to a single value throughout the compilation (either because they can be referenced in memory or are set once from a single constant). Lower their priority for a register. If such a register is only referenced once, try substituting its value into the using insn. If it succeeds, we can eliminate the register completely. Initialize init_insns in ira_reg_equiv array.
References BB_END, BB_HEAD, bb_loop_depth(), bitmap_bit_p, ira_reg_equiv_s::caller_save_p, cfun, copy_rtx(), def_dominates_uses(), DF_REG_DEF_COUNT, equiv_init_movable_p(), equiv_init_varies_p(), find_reg_note(), FOR_EACH_BB_FN, gcc_assert, gen_rtx_INSN_LIST(), GET_CODE, ggc_alloc(), i, equivalence::init_insns, ira_reg_equiv_s::init_insns, df_insn_info::insn, rtx_insn_list::insn(), INSN_P, ira_reg_equiv, ira_use_lra_p, equivalence::is_arg_equivalence, loop_depth(), equivalence::loop_depth, may_trap_or_fault_p(), MEM_P, rtx_insn_list::next(), NEXT_INSN(), no_equiv(), NONJUMP_INSN_P, note_pattern_stores(), NULL, NULL_RTX, NUM_FIXED_BLOCKS, PATTERN(), REG_BASIC_BLOCK, reg_equiv, REG_N_REFS(), REG_NOTE_KIND, REG_NOTES, REG_P, reg_preferred_class(), REGNO, regstat_get_setjmp_crosses(), remove_note(), equivalence::replacement, rtx_equal_p(), rtx_varies_p(), SET_DEST, SET_SRC, set_unique_reg_note(), setjmp_crosses, side_effects_p(), single_set(), equivalence::src_p, targetm, valid_none, valid_reload, validate_equiv_mem(), XEXP, XVECEXP, and XVECLEN.
Referenced by ira().
◆ update_equiv_regs_prescan()
Scan the instructions before update_equiv_regs. Record which registers are referenced as paradoxical subregs. Also check for cases in which the current function needs to save a register that one of its call instructions clobbers. These things are logically unrelated, but it's more efficient to do them together.
References CALL_P, cfun, crtl, df_set_regs_ever_live(), FOR_BB_INSNS, FOR_EACH_BB_FN, ggc_alloc(), hard_reg_set_empty_p(), df_insn_info::insn, insn_callee_abi(), NONDEBUG_INSN_P, set_paradoxical_subreg(), and TEST_HARD_REG_BIT.
Referenced by ira().
◆ validate_equiv_mem()
Verify that no store between START and the death of REG invalidates MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, by storing into an overlapping memory location, or with a non-const CALL_INSN. Return VALID_RELOAD if MEMREF remains valid for both reload and combine_and_move insns, VALID_COMBINE if only valid for combine_and_move_insns, and VALID_NONE otherwise.
References CALL_P, equiv_init_varies_p(), equiv_mem_data::equiv_mem_modified, find_reg_note(), ggc_alloc(), INSN_P, MEM_READONLY_P, NEXT_INSN(), note_stores(), REG_NOTE_KIND, REG_NOTES, reg_overlap_mentioned_p(), REG_P, RTL_CONST_OR_PURE_CALL_P, side_effects_p(), valid_combine, valid_none, valid_reload, validate_equiv_mem_from_store(), and XEXP.
Referenced by add_store_equivs(), and update_equiv_regs().
◆ validate_equiv_mem_from_store()
If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. Called via note_stores.
References anti_dependence(), equiv_mem_data::equiv_mem, equiv_mem_data::equiv_mem_modified, MEM_P, reg_overlap_mentioned_p(), and REG_P.
Referenced by validate_equiv_mem().
Variable Documentation
◆ allocated_reg_info_size
|
static |
The number of entries allocated in reg_info.
Referenced by expand_reg_info(), and ira().
◆ allocno_class_order
|
static |
Order numbers of allocno classes in original target allocno class array, -1 for non-allocno classes.
Referenced by comp_reg_classes_func(), and reorder_important_classes().
◆ default_target_ira
| struct target_ira default_target_ira |
Integrated Register Allocator (IRA) entry point. Copyright (C) 2006-2024 Free Software Foundation, Inc. Contributed by Vladimir Makarov <vmakarov@redhat.com>. This file is part of GCC. GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3, or (at your option) any later version. GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see <http://www.gnu.org/licenses/>.
The integrated register allocator (IRA) is a
regional register allocator performing graph coloring on a top-down
traversal of nested regions. Graph coloring in a region is based
on Chaitin-Briggs algorithm. It is called integrated because
register coalescing, register live range splitting, and choosing a
better hard register are done on-the-fly during coloring. Register
coalescing and choosing a cheaper hard register is done by hard
register preferencing during hard register assigning. The live
range splitting is a byproduct of the regional register allocation.
Major IRA notions are:
o *Region* is a part of CFG where graph coloring based on
Chaitin-Briggs algorithm is done. IRA can work on any set of
nested CFG regions forming a tree. Currently the regions are
the entire function for the root region and natural loops for
the other regions. Therefore data structure representing a
region is called loop_tree_node.
o *Allocno class* is a register class used for allocation of
given allocno. It means that only hard register of given
register class can be assigned to given allocno. In reality,
even smaller subset of (*profitable*) hard registers can be
assigned. In rare cases, the subset can be even smaller
because our modification of Chaitin-Briggs algorithm requires
that sets of hard registers can be assigned to allocnos forms a
forest, i.e. the sets can be ordered in a way where any
previous set is not intersected with given set or is a superset
of given set.
o *Pressure class* is a register class belonging to a set of
register classes containing all of the hard-registers available
for register allocation. The set of all pressure classes for a
target is defined in the corresponding machine-description file
according some criteria. Register pressure is calculated only
for pressure classes and it affects some IRA decisions as
forming allocation regions.
o *Allocno* represents the live range of a pseudo-register in a
region. Besides the obvious attributes like the corresponding
pseudo-register number, allocno class, conflicting allocnos and
conflicting hard-registers, there are a few allocno attributes
which are important for understanding the allocation algorithm:
- *Live ranges*. This is a list of ranges of *program points*
where the allocno lives. Program points represent places
where a pseudo can be born or become dead (there are
approximately two times more program points than the insns)
and they are represented by integers starting with 0. The
live ranges are used to find conflicts between allocnos.
They also play very important role for the transformation of
the IRA internal representation of several regions into a one
region representation. The later is used during the reload
pass work because each allocno represents all of the
corresponding pseudo-registers.
- *Hard-register costs*. This is a vector of size equal to the
number of available hard-registers of the allocno class. The
cost of a callee-clobbered hard-register for an allocno is
increased by the cost of save/restore code around the calls
through the given allocno's life. If the allocno is a move
instruction operand and another operand is a hard-register of
the allocno class, the cost of the hard-register is decreased
by the move cost.
When an allocno is assigned, the hard-register with minimal
full cost is used. Initially, a hard-register's full cost is
the corresponding value from the hard-register's cost vector.
If the allocno is connected by a *copy* (see below) to
another allocno which has just received a hard-register, the
cost of the hard-register is decreased. Before choosing a
hard-register for an allocno, the allocno's current costs of
the hard-registers are modified by the conflict hard-register
costs of all of the conflicting allocnos which are not
assigned yet.
- *Conflict hard-register costs*. This is a vector of the same
size as the hard-register costs vector. To permit an
unassigned allocno to get a better hard-register, IRA uses
this vector to calculate the final full cost of the
available hard-registers. Conflict hard-register costs of an
unassigned allocno are also changed with a change of the
hard-register cost of the allocno when a copy involving the
allocno is processed as described above. This is done to
show other unassigned allocnos that a given allocno prefers
some hard-registers in order to remove the move instruction
corresponding to the copy.
o *Cap*. If a pseudo-register does not live in a region but
lives in a nested region, IRA creates a special allocno called
a cap in the outer region. A region cap is also created for a
subregion cap.
o *Copy*. Allocnos can be connected by copies. Copies are used
to modify hard-register costs for allocnos during coloring.
Such modifications reflects a preference to use the same
hard-register for the allocnos connected by copies. Usually
copies are created for move insns (in this case it results in
register coalescing). But IRA also creates copies for operands
of an insn which should be assigned to the same hard-register
due to constraints in the machine description (it usually
results in removing a move generated in reload to satisfy
the constraints) and copies referring to the allocno which is
the output operand of an instruction and the allocno which is
an input operand dying in the instruction (creation of such
copies results in less register shuffling). IRA *does not*
create copies between the same register allocnos from different
regions because we use another technique for propagating
hard-register preference on the borders of regions.
Allocnos (including caps) for the upper region in the region tree
*accumulate* information important for coloring from allocnos with
the same pseudo-register from nested regions. This includes
hard-register and memory costs, conflicts with hard-registers,
allocno conflicts, allocno copies and more. *Thus, attributes for
allocnos in a region have the same values as if the region had no
subregions*. It means that attributes for allocnos in the
outermost region corresponding to the function have the same values
as though the allocation used only one region which is the entire
function. It also means that we can look at IRA work as if the
first IRA did allocation for all function then it improved the
allocation for loops then their subloops and so on.
IRA major passes are:
o Building IRA internal representation which consists of the
following subpasses:
* First, IRA builds regions and creates allocnos (file
ira-build.cc) and initializes most of their attributes.
* Then IRA finds an allocno class for each allocno and
calculates its initial (non-accumulated) cost of memory and
each hard-register of its allocno class (file ira-cost.c).
* IRA creates live ranges of each allocno, calculates register
pressure for each pressure class in each region, sets up
conflict hard registers for each allocno and info about calls
the allocno lives through (file ira-lives.cc).
* IRA removes low register pressure loops from the regions
mostly to speed IRA up (file ira-build.cc).
* IRA propagates accumulated allocno info from lower region
allocnos to corresponding upper region allocnos (file
ira-build.cc).
* IRA creates all caps (file ira-build.cc).
* Having live-ranges of allocnos and their classes, IRA creates
conflicting allocnos for each allocno. Conflicting allocnos
are stored as a bit vector or array of pointers to the
conflicting allocnos whatever is more profitable (file
ira-conflicts.cc). At this point IRA creates allocno copies.
o Coloring. Now IRA has all necessary info to start graph coloring
process. It is done in each region on top-down traverse of the
region tree (file ira-color.cc). There are following subpasses:
* Finding profitable hard registers of corresponding allocno
class for each allocno. For example, only callee-saved hard
registers are frequently profitable for allocnos living
through colors. If the profitable hard register set of
allocno does not form a tree based on subset relation, we use
some approximation to form the tree. This approximation is
used to figure out trivial colorability of allocnos. The
approximation is a pretty rare case.
* Putting allocnos onto the coloring stack. IRA uses Briggs
optimistic coloring which is a major improvement over
Chaitin's coloring. Therefore IRA does not spill allocnos at
this point. There is some freedom in the order of putting
allocnos on the stack which can affect the final result of
the allocation. IRA uses some heuristics to improve the
order. The major one is to form *threads* from colorable
allocnos and push them on the stack by threads. Thread is a
set of non-conflicting colorable allocnos connected by
copies. The thread contains allocnos from the colorable
bucket or colorable allocnos already pushed onto the coloring
stack. Pushing thread allocnos one after another onto the
stack increases chances of removing copies when the allocnos
get the same hard reg.
We also use a modification of Chaitin-Briggs algorithm which
works for intersected register classes of allocnos. To
figure out trivial colorability of allocnos, the mentioned
above tree of hard register sets is used. To get an idea how
the algorithm works in i386 example, let us consider an
allocno to which any general hard register can be assigned.
If the allocno conflicts with eight allocnos to which only
EAX register can be assigned, given allocno is still
trivially colorable because all conflicting allocnos might be
assigned only to EAX and all other general hard registers are
still free.
To get an idea of the used trivial colorability criterion, it
is also useful to read article "Graph-Coloring Register
Allocation for Irregular Architectures" by Michael D. Smith
and Glen Holloway. Major difference between the article
approach and approach used in IRA is that Smith's approach
takes register classes only from machine description and IRA
calculate register classes from intermediate code too
(e.g. an explicit usage of hard registers in RTL code for
parameter passing can result in creation of additional
register classes which contain or exclude the hard
registers). That makes IRA approach useful for improving
coloring even for architectures with regular register files
and in fact some benchmarking shows the improvement for
regular class architectures is even bigger than for irregular
ones. Another difference is that Smith's approach chooses
intersection of classes of all insn operands in which a given
pseudo occurs. IRA can use bigger classes if it is still
more profitable than memory usage.
* Popping the allocnos from the stack and assigning them hard
registers. If IRA cannot assign a hard register to an
allocno and the allocno is coalesced, IRA undoes the
coalescing and puts the uncoalesced allocnos onto the stack in
the hope that some such allocnos will get a hard register
separately. If IRA fails to assign hard register or memory
is more profitable for it, IRA spills the allocno. IRA
assigns the allocno the hard-register with minimal full
allocation cost which reflects the cost of usage of the
hard-register for the allocno and cost of usage of the
hard-register for allocnos conflicting with given allocno.
* Chaitin-Briggs coloring assigns as many pseudos as possible
to hard registers. After coloring we try to improve
allocation with cost point of view. We improve the
allocation by spilling some allocnos and assigning the freed
hard registers to other allocnos if it decreases the overall
allocation cost.
* After allocno assigning in the region, IRA modifies the hard
register and memory costs for the corresponding allocnos in
the subregions to reflect the cost of possible loads, stores,
or moves on the border of the region and its subregions.
When default regional allocation algorithm is used
(-fira-algorithm=mixed), IRA just propagates the assignment
for allocnos if the register pressure in the region for the
corresponding pressure class is less than number of available
hard registers for given pressure class.
o Spill/restore code moving. When IRA performs an allocation
by traversing regions in top-down order, it does not know what
happens below in the region tree. Therefore, sometimes IRA
misses opportunities to perform a better allocation. A simple
optimization tries to improve allocation in a region having
subregions and containing in another region. If the
corresponding allocnos in the subregion are spilled, it spills
the region allocno if it is profitable. The optimization
implements a simple iterative algorithm performing profitable
transformations while they are still possible. It is fast in
practice, so there is no real need for a better time complexity
algorithm.
o Code change. After coloring, two allocnos representing the
same pseudo-register outside and inside a region respectively
may be assigned to different locations (hard-registers or
memory). In this case IRA creates and uses a new
pseudo-register inside the region and adds code to move allocno
values on the region's borders. This is done during top-down
traversal of the regions (file ira-emit.cc). In some
complicated cases IRA can create a new allocno to move allocno
values (e.g. when a swap of values stored in two hard-registers
is needed). At this stage, the new allocno is marked as
spilled. IRA still creates the pseudo-register and the moves
on the region borders even when both allocnos were assigned to
the same hard-register. If the reload pass spills a
pseudo-register for some reason, the effect will be smaller
because another allocno will still be in the hard-register. In
most cases, this is better then spilling both allocnos. If
reload does not change the allocation for the two
pseudo-registers, the trivial move will be removed by
post-reload optimizations. IRA does not generate moves for
allocnos assigned to the same hard register when the default
regional allocation algorithm is used and the register pressure
in the region for the corresponding pressure class is less than
number of available hard registers for given pressure class.
IRA also does some optimizations to remove redundant stores and
to reduce code duplication on the region borders.
o Flattening internal representation. After changing code, IRA
transforms its internal representation for several regions into
one region representation (file ira-build.cc). This process is
called IR flattening. Such process is more complicated than IR
rebuilding would be, but is much faster.
o After IR flattening, IRA tries to assign hard registers to all
spilled allocnos. This is implemented by a simple and fast
priority coloring algorithm (see function
ira_reassign_conflict_allocnos::ira-color.cc). Here new allocnos
created during the code change pass can be assigned to hard
registers.
o At the end IRA calls the reload pass. The reload pass
communicates with IRA through several functions in file
ira-color.cc to improve its decisions in
* sharing stack slots for the spilled pseudos based on IRA info
about pseudo-register conflicts.
* reassigning hard-registers to all spilled pseudos at the end
of each reload iteration.
* choosing a better hard-register to spill based on IRA info
about pseudo-register live ranges and the register pressure
in places where the pseudo-register lives.
IRA uses a lot of data representing the target processors. These
data are initialized in file ira.cc.
If function has no loops (or the loops are ignored when
-fira-algorithm=CB is used), we have classic Chaitin-Briggs
coloring (only instead of separate pass of coalescing, we use hard
register preferencing). In such case, IRA works much faster
because many things are not made (like IR flattening, the
spill/restore optimization, and the code change).
Literature is worth to read for better understanding the code:
o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
Graph Coloring Register Allocation.
o David Callahan, Brian Koblenz. Register allocation via
hierarchical graph coloring.
o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
Coloring Register Allocation: A Study of the Chaitin-Briggs and
Callahan-Koblenz Algorithms.
o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
Register Allocation Based on Graph Fusion.
o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
Allocation for Irregular Architectures
o Vladimir Makarov. The Integrated Register Allocator for GCC.
o Vladimir Makarov. The top-down register allocator for irregular
register file architectures.
◆ default_target_ira_int
| class target_ira_int default_target_ira_int |
◆ eliminable_regset
| HARD_REG_SET eliminable_regset |
All registers that can be eliminated.
Referenced by assign_spill_hard_regs(), build_insn_chain(), get_regno_pressure_class(), get_regno_pressure_class(), inherit_in_ebb(), invariant_p(), ira_setup_eliminable_regset(), make_hard_regno_dead(), make_hard_regno_live(), mark_hard_reg_live(), need_for_split_p(), process_bb_node_lives(), and update_reg_eliminate().
◆ first_moveable_pseudo
| int first_moveable_pseudo |
Record the range of register numbers added by find_moveable_pseudos.
Referenced by find_costs_and_classes(), find_moveable_pseudos(), and move_unallocated_pseudos().
◆ internal_flag_ira_verbose
| int internal_flag_ira_verbose |
A modified value of flag `-fira-verbose' used internally.
Referenced by add_range_and_copies_from_move_list(), allocno_reload_assign(), assign_hard_reg(), build_conflict_bit_table(), calculate_allocation_cost(), change_loop(), coalesce_allocnos(), coalesce_spill_slots(), color_allocnos(), color_pass(), copy_allocno_live_ranges(), create_cap_allocno(), do_coloring(), do_reload(), fast_allocation(), find_costs_and_classes(), form_threads_from_colorable_allocno(), form_threads_from_copies(), generate_edge_moves(), improve_allocation(), ira(), ira_build(), ira_build_conflicts(), ira_compress_allocno_live_ranges(), ira_create_allocno_live_ranges(), ira_create_new_reg(), ira_flattening(), ira_mark_new_stack_slot(), ira_reassign_conflict_allocnos(), ira_reassign_pseudos(), ira_rebuild_regno_allocno_list(), ira_remove_pref(), ira_reuse_stack_slot(), ira_set_pseudo_classes(), ira_sort_regnos_for_alter_reg(), ira_update_equiv_info_by_shuffle_insn(), mark_all_loops_for_removal(), mark_loops_for_removal(), modify_move_list(), move_allocno_live_ranges(), move_spill_restore(), pop_allocnos_from_stack(), process_bb_node_lives(), push_allocno_to_stack(), push_only_colorable(), record_reg_classes(), remove_allocno_from_bucket_and_push(), remove_some_program_points_and_update_live_ranges(), restore_costs_from_copies(), scan_one_insn(), setup_allocno_available_regs_num(), setup_preferred_alternate_classes_for_new_pseudos(), update_costs_from_allocno(), update_costs_from_copies(), and update_costs_from_prefs().
◆ ira_additional_jumps_num
| int ira_additional_jumps_num |
Referenced by calculate_allocation_cost(), and ira().
◆ ira_bitmap_obstack
|
static |
Obstack used for storing all bitmaps of the IRA.
Referenced by do_reload(), ira(), and ira_allocate_bitmap().
◆ ira_conflicts_p
| bool ira_conflicts_p |
True if we have allocno conflicts. It is false for non-optimized mode or when the conflict table is too big.
Referenced by alter_reg(), build_insn_chain(), calculate_needs_all_insns(), compute_use_by_pseudos(), count_pseudo(), count_spilled_pseudo(), delete_output_reload(), do_reload(), emit_input_reload_insns(), find_reg(), finish_spills(), ira(), ira_build(), ira_build_conflicts(), ira_color(), pseudo_for_reload_consideration_p(), and reload().
◆ ira_dump_file
| FILE* ira_dump_file |
Dump file of the allocator if it is not NULL.
Referenced by add_range_and_copies_from_move_list(), allocno_reload_assign(), assign_hard_reg(), build_conflict_bit_table(), calculate_allocation_cost(), change_loop(), coalesce_allocnos(), coalesce_spill_slots(), color_allocnos(), color_pass(), copy_allocno_live_ranges(), create_cap_allocno(), decrease_live_ranges_number(), do_coloring(), do_reload(), fast_allocation(), find_costs_and_classes(), form_threads_from_colorable_allocno(), form_threads_from_copies(), generate_edge_moves(), improve_allocation(), ira(), ira_build(), ira_build_conflicts(), ira_compress_allocno_live_ranges(), ira_create_allocno_live_ranges(), ira_create_new_reg(), ira_flattening(), ira_mark_new_stack_slot(), ira_print_expanded_allocno(), ira_reassign_conflict_allocnos(), ira_reassign_pseudos(), ira_rebuild_regno_allocno_list(), ira_remove_insn_scratches(), ira_remove_pref(), ira_reuse_stack_slot(), ira_set_pseudo_classes(), ira_sort_regnos_for_alter_reg(), ira_update_equiv_info_by_shuffle_insn(), mark_all_loops_for_removal(), mark_loops_for_removal(), modify_move_list(), move_allocno_live_ranges(), move_spill_restore(), pop_allocnos_from_stack(), print_allocno_costs(), print_loop_title(), print_pseudo_costs(), process_bb_node_lives(), push_allocno_to_stack(), push_only_colorable(), record_reg_classes(), remove_allocno_from_bucket_and_push(), remove_scratches(), remove_some_program_points_and_update_live_ranges(), restore_costs_from_copies(), scan_one_insn(), setup_allocno_available_regs_num(), setup_preferred_alternate_classes_for_new_pseudos(), update_costs_from_allocno(), update_costs_from_copies(), and update_costs_from_prefs().
◆ ira_in_progress
◆ ira_load_cost
| int64_t ira_load_cost |
Referenced by calculate_allocation_cost(), emit_move_list(), and ira().
◆ ira_mem_cost
| int64_t ira_mem_cost |
Referenced by calculate_allocation_cost(), and ira().
◆ ira_move_loops_num
| int ira_move_loops_num |
Referenced by calculate_allocation_cost(), ira(), and modify_move_list().
◆ ira_overall_cost
| int64_t ira_overall_cost |
Correspondingly overall cost of the allocation, overall cost before reload, cost of the allocnos assigned to hard-registers, cost of the allocnos assigned to memory, cost of loads, stores and register move insns generated for pseudo-register live range splitting (see ira-emit.cc).
Referenced by allocno_reload_assign(), calculate_allocation_cost(), do_reload(), emit_move_list(), ira(), and ira_mark_allocation_change().
◆ ira_reg_cost
| int64_t ira_reg_cost |
Referenced by calculate_allocation_cost(), and ira().
◆ ira_reg_equiv
| struct ira_reg_equiv_s* ira_reg_equiv |
Info about equiv. info for each register.
Referenced by add_store_equivs(), calculate_equiv_gains(), coalescable_pseudo_p(), combine_and_move_insns(), contains_reloaded_insn_p(), eliminate_regs_in_insn(), emit_move_list(), finish_reg_equiv(), get_equiv(), get_equiv_regno(), init_insn_rhs_dead_pseudo_p(), init_reg_equiv(), ira_equiv_no_lvalue_p(), ira_expand_reg_equiv(), ira_update_equiv_info_by_shuffle_insn(), lra_constraints(), lra_copy_reg_equiv(), lra_init_equiv(), no_equiv(), reverse_equiv_p(), setup_reg_equiv(), setup_reg_equiv_init(), spill_for(), update_equiv(), and update_equiv_regs().
◆ ira_reg_equiv_len
| int ira_reg_equiv_len |
The length of the following array.
Referenced by change_loop(), eliminate_regs_in_insn(), emit_move_list(), init_reg_equiv(), ira_equiv_no_lvalue_p(), ira_expand_reg_equiv(), ira_subloop_allocnos_can_differ_p(), setup_reg_equiv(), and setup_reg_renumber().
◆ ira_shuffle_cost
| int64_t ira_shuffle_cost |
Referenced by calculate_allocation_cost(), and ira().
◆ ira_spilled_reg_stack_slots
| class ira_spilled_reg_stack_slot* ira_spilled_reg_stack_slots |
The following array contains info about spilled pseudo-registers stack slots used in current function so far.
Referenced by do_reload(), ira(), ira_mark_new_stack_slot(), and ira_reuse_stack_slot().
◆ ira_spilled_reg_stack_slots_num
| int ira_spilled_reg_stack_slots_num |
The number of elements in the following array.
Referenced by ira(), ira_mark_new_stack_slot(), ira_reuse_stack_slot(), and ira_sort_regnos_for_alter_reg().
◆ ira_store_cost
| int64_t ira_store_cost |
Referenced by calculate_allocation_cost(), and ira().
◆ ira_use_lra_p
| bool ira_use_lra_p |
True when we use LRA instead of reload pass for the current function.
Referenced by backend_init_target(), based_loc_descr(), compute_frame_pointer_to_fb_displacement(), do_reload(), emit_move_list(), find_costs_and_classes(), ira(), ira_adjust_equiv_reg_cost(), ira_costs(), ira_init_once(), ira_mark_new_stack_slot(), ira_reuse_stack_slot(), ira_sort_regnos_for_alter_reg(), ira_subloop_allocnos_can_differ_p(), reg_loc_descriptor(), scan_one_insn(), setup_reg_renumber(), update_equiv_regs(), and vt_initialize().
◆ last_moveable_pseudo
| int last_moveable_pseudo |
Referenced by find_moveable_pseudos(), and move_unallocated_pseudos().
◆ max_regno_before_ira
|
static |
Value of max_reg_num () before IRA work start. This value helps us to recognize a situation when new pseudos were created during IRA work.
Referenced by fix_reg_equiv_init(), and ira().
◆ overall_cost_before
| int64_t overall_cost_before |
Referenced by do_reload(), and ira().
◆ pseudo_replaced_reg
These two vectors hold data for every register added by find_movable_pseudos, with index 0 holding data for the first_moveable_pseudo.
The original home register.
Referenced by find_moveable_pseudos(), and move_unallocated_pseudos().
◆ reg_equiv
|
static |
reg_equiv[N] (where N is a pseudo reg number) is the equivalence structure for that register.
Referenced by add_store_equivs(), adjust_cleared_regs(), combine_and_move_insns(), equiv_init_movable_p(), equiv_init_varies_p(), ira(), memref_referenced_p(), no_equiv(), set_paradoxical_subreg(), and update_equiv_regs().
◆ reg_renumber
| short* reg_renumber |
Vector of substitutions of register numbers, used to map pseudo regs into hardware regs. This is set up as a result of register allocation. Element N is the hard reg assigned to pseudo reg N, or is -1 if no hard reg was assigned. If N is a hard reg number, element N is N.
Referenced by add_used_regs(), allocate_initial_values(), allocate_reg_info(), allocno_reload_assign(), alter_reg(), assign_by_spills(), assign_mem_slot(), build_insn_chain(), calculate_elim_costs_all_insns(), calculate_needs_all_insns(), calculate_spill_cost(), check_and_process_move(), compute_use_by_pseudos(), constrain_operands(), count_pseudo(), count_spilled_pseudo(), create_cands(), create_live_range_start_chains(), cselib_invalidate_regno(), curr_insn_transform(), delete_output_reload(), do_remat(), eliminate_regs_1(), elimination_effects(), emit_input_reload_insns(), find_reloads(), find_reloads_address_1(), find_reloads_toplev(), finish_spills(), free_reg_info(), get_hard_regs(), improve_inheritance(), inherit_in_ebb(), init_regno_assign_info(), ira_mark_allocation_change(), ira_reassign_pseudos(), ira_restore_scratches(), lra_assign(), lra_create_live_ranges_1(), lra_get_regno_hard_regno(), lra_setup_reg_renumber(), lra_split_hard_reg_for(), lra_undo_inheritance(), mark_home_live(), mark_home_live_1(), mark_referenced_regs(), mem_move_p(), move_unallocated_pseudos(), need_for_call_save_p(), need_for_split_p(), operand_to_remat(), prepare_function_start(), process_bb_lives(), pseudo_for_reload_consideration_p(), push_reload(), reg_overlap_for_remat_p(), regno_ok_for_base_p(), reload(), remove_init_insns(), resize_reg_info(), rtx_renumbered_equal_p(), save_call_clobbered_regs(), setup_live_pseudos_and_spill_after_risky_transforms(), setup_next_usage_insn(), setup_reg_renumber(), setup_save_areas(), spill_for(), spill_hard_reg(), spill_pseudos(), split_reg(), subst_indexed_address(), true_regnum(), undo_optional_reloads(), update_hard_regno_preference(), update_lives(), and will_delete_init_insn_p().
◆ saved_flag_ira_share_spill_slots
|
static |
Saved between IRA and reload.
Referenced by do_reload(), and ira().
◆ scratch_bitmap
|
static |
Bitmap of scratch regnos.
Referenced by ira_former_scratch_p(), ira_register_new_scratch_op(), ira_restore_scratches(), and remove_scratches().
◆ scratch_operand_bitmap
|
static |
Bitmap of scratch operands.
Referenced by ira_former_scratch_operand_p(), ira_register_new_scratch_op(), ira_restore_scratches(), and remove_scratches().
◆ scratches
Locations of the former scratches.
Referenced by ira_register_new_scratch_op(), ira_restore_scratches(), and remove_scratches().
◆ temp_hard_regset
|
static |
Temporary hard reg set used for a different calculation.
Referenced by setup_allocno_and_important_classes(), setup_class_hard_regs(), setup_class_subset_and_memory_move_costs(), setup_class_translate_array(), setup_pressure_classes(), setup_prohibited_and_exclude_class_mode_regs(), setup_reg_class_relations(), setup_reg_subclasses(), and setup_stack_reg_pressure_class().
